@woosh/meep-engine 3.14.6 → 3.16.0

package/src/shade/renderer/particles/sort/shader_particle_sort.js

@@ -5,9 +5,12 @@ import { ComputeShader } from "../../shader/ComputeShader.js";
 import { CodeChunk } from "../../shader/compiler/CodeChunk.js";
 import { ShaderResourceSetDescriptor } from "../../shader/resource/ShaderResourceSetDescriptor.js";
 import { PREFIX_SCAN_CSDLDF_HEADER_WORDS } from "../../gpu_primitive/prefix_sum/v1/shader_prefix_scan_csdldf.js";
+import { CAMERA_UNIFORM_STRUCT } from "../../camera/CAMERA_UNIFORM_STRUCT.js";
 import { PARTICLE_RECORD_HEADER_EMITTER, PARTICLE_RECORD_WORD_COUNT } from "../ParticleConstants.js";
-import { EMITTER_ATTRIBUTE_ABSENT } from "../data/PARTICLE_EMITTER_LAYOUT.js";
+import { PARTICLE_COUNTER } from "../data/PARTICLE_COUNTERS.js";
+import { EMITTER_ATTRIBUTE_ABSENT } from "../data/PARTICLE_EMITTER_STRUCT.js";
 import { chunk_particle_emitter } from "../data/chunk_particle_emitter.js";
+import { chunk_particle_header } from "../data/particle_header.js";
 
 /**
  * Depth-sort shaders. Three passes bracket a `csdldf` prefix scan:
@@ -101,7 +104,7 @@ fn main(@builtin(global_invocation_id) gid : vec3<u32>) {
 `);
 
 /**
- * Dispatch this over `PREFIX_SCAN_CSDLDF_HEADER_WORDS + round_up_4(bucket_count)` threads, not over
+ * Dispatch this over `PREFIX_SCAN_CSDLDF_HEADER_WORDS + align_4(bucket_count)` threads, not over
  * `bucket_count`: its widest loop is the scan header plus the bins rounded up to the whole vec4 the
  * last bin lands in. Under-dispatching leaves the tail of that vec4 holding last frame's counts,
  * and the scan adds them in.
@@ -114,40 +117,32 @@ export const shader_particle_sort_reset = ComputeShader.from({
     body: reset_body,
 });
 
-const READ_MAT4 = /* wgsl */ `
-fn particle_read_mat4(m : ptr<storage, array<u32>, read>, o : u32) -> mat4x4<f32> {
-    return mat4x4<f32>(
-        vec4<f32>(bitcast<f32>((*m)[o + 0u]), bitcast<f32>((*m)[o + 1u]), bitcast<f32>((*m)[o + 2u]), bitcast<f32>((*m)[o + 3u])),
-        vec4<f32>(bitcast<f32>((*m)[o + 4u]), bitcast<f32>((*m)[o + 5u]), bitcast<f32>((*m)[o + 6u]), bitcast<f32>((*m)[o + 7u])),
-        vec4<f32>(bitcast<f32>((*m)[o + 8u]), bitcast<f32>((*m)[o + 9u]), bitcast<f32>((*m)[o + 10u]), bitcast<f32>((*m)[o + 11u])),
-        vec4<f32>(bitcast<f32>((*m)[o + 12u]), bitcast<f32>((*m)[o + 13u]), bitcast<f32>((*m)[o + 14u]), bitcast<f32>((*m)[o + 15u])),
-    );
-}
-`;
-
 // --- histogram pass ---
 
 /**
- * Per-dispatch, 16 bytes, read-only. Four uniforms meant four transient buffers per sort;
+ * Per-dispatch, 12 bytes, read-only. Separate uniforms meant a transient buffer each per sort;
  * WGSL allows one immediate per entry point, so they travel together.
  *
+ * The particle count is NOT here: it is the alive counter the simulate pass finished writing on
+ * the GPU, read from the counters buffer. A host-supplied count would be last frame's.
+ *
  * @type {WebGPUStruct}
  */
 const SORT_HISTOGRAM_SETTINGS = WebGPUStruct.from({
     u_near: f32,
     u_far: f32,
     u_bucket_count: u32,
-    u_count: u32,
 }, 'ParticleSortHistogramSettings');
 
 const histogram_resources = new ShaderResourceSetDescriptor();
 
 histogram_resources.setImmediate('settings', SORT_HISTOGRAM_SETTINGS);
 histogram_resources.createGroup()
-    .addStorageBuffer("emitters", WebGPUArray.u32, false)
+    .addUniform("camera", CAMERA_UNIFORM_STRUCT)
+    .addStorageBuffer("emitter_database", WebGPUArray.u32, false)
     .addStorageBuffer("pool", WebGPUArray.u32, false)
     .addStorageBuffer("alive", WebGPUArray.u32, false)
-    .addStorageBuffer("view_matrix", WebGPUArray.u32, false)
+    .addStorageBuffer("counters", WebGPUArray.from(atomic_u32), true) // atomics require a read_write binding even for atomicLoad
     .addStorageBuffer("keys", WebGPUArray.u32, true)
     .addStorageBuffer("histogram", WebGPUArray.from(atomic_u32), true);
 const histogram_body = CodeChunk.from(/* wgsl */ `
@@ -155,18 +150,17 @@ ${COMMON}
 const PARTICLE_RECORD_WORDS : u32 = ${PARTICLE_RECORD_WORD_COUNT}u;
 const PARTICLE_HEADER_EMITTER : u32 = ${PARTICLE_RECORD_HEADER_EMITTER}u;
 const PARTICLE_ATTRIBUTE_ABSENT : u32 = ${EMITTER_ATTRIBUTE_ABSENT}u;
-
-${READ_MAT4}
+const COUNTER_ALIVE : u32 = ${PARTICLE_COUNTER.ALIVE}u;
 
 @compute @workgroup_size(${PARTICLE_SORT_WORKGROUP_SIZE}, 1, 1)
 fn main(@builtin(global_invocation_id) gid : vec3<u32>) {
     let i = gid.x;
-    if (i >= settings.u_count) { return; }
+    if (i >= atomicLoad(&counters[COUNTER_ALIVE])) { return; }
 
     let slot = alive[i];
     let base = slot * PARTICLE_RECORD_WORDS;
-    let emitter_index = pool[base + PARTICLE_HEADER_EMITTER];
-    let em = particle_emitter_read(&emitters, emitter_index);
+    let emitter_index = particle_header_emitter(pool[base + PARTICLE_HEADER_EMITTER]);
+    let em = particle_emitter_read(&emitter_database, emitter_index);
 
     var world_pos = vec3<f32>(0.0);
     if (em.render_position != PARTICLE_ATTRIBUTE_ABSENT) {
@@ -174,8 +168,7 @@ fn main(@builtin(global_invocation_id) gid : vec3<u32>) {
         world_pos = vec3<f32>(bitcast<f32>(pool[o]), bitcast<f32>(pool[o + 1u]), bitcast<f32>(pool[o + 2u]));
     }
 
-    let view = particle_read_mat4(&view_matrix, 0u);
-    let view_depth = -(view * vec4<f32>(world_pos, 1.0)).z;
+    let view_depth = -(camera.view_matrix * vec4<f32>(world_pos, 1.0)).z;
 
     let t = (view_depth - settings.u_near) / max(settings.u_far - settings.u_near, 1e-6);
     let clamped = clamp(1.0 - t, 0.0, 1.0);
@@ -184,7 +177,7 @@ fn main(@builtin(global_invocation_id) gid : vec3<u32>) {
     keys[i] = bucket;
     atomicAdd(&histogram[SORT_HEADER_WORDS + bucket], 1u);
 }
-`, [chunk_particle_emitter]);
+`, [chunk_particle_emitter, chunk_particle_header]);
 
 export const shader_particle_sort_histogram = ComputeShader.from({
     label: "Particle Sort Histogram",
@@ -194,31 +187,23 @@ export const shader_particle_sort_histogram = ComputeShader.from({
 
 // --- scatter pass ---
 
-/**
- * Per-dispatch, four bytes, read-only: immediate data rather than a uniform buffer.
- *
- * @type {WebGPUStruct}
- */
-const SORT_SCATTER_SETTINGS = WebGPUStruct.from({
-    u_count: u32,
-}, 'ParticleSortScatterSettings');
-
 const scatter_resources = new ShaderResourceSetDescriptor();
 
-scatter_resources.setImmediate('settings', SORT_SCATTER_SETTINGS);
 scatter_resources.createGroup()
     .addStorageBuffer("keys", WebGPUArray.u32, false)
     .addStorageBuffer("alive", WebGPUArray.u32, false)
     .addStorageBuffer("scanned", WebGPUArray.u32, false)
+    .addStorageBuffer("counters", WebGPUArray.from(atomic_u32), true) // atomics require a read_write binding even for atomicLoad
     .addStorageBuffer("cursor", WebGPUArray.from(atomic_u32), true)
     .addStorageBuffer("sorted", WebGPUArray.u32, true);
 const scatter_body = CodeChunk.from(/* wgsl */ `
 ${COMMON}
+const COUNTER_ALIVE : u32 = ${PARTICLE_COUNTER.ALIVE}u;
 
 @compute @workgroup_size(${PARTICLE_SORT_WORKGROUP_SIZE}, 1, 1)
 fn main(@builtin(global_invocation_id) gid : vec3<u32>) {
     let i = gid.x;
-    if (i >= settings.u_count) { return; }
+    if (i >= atomicLoad(&counters[COUNTER_ALIVE])) { return; }
 
     let bucket = keys[i];
 

package/src/shade/renderer/particles/vm/ParticleVMReference.d.ts

@@ -28,8 +28,8 @@ export function u32_to_unit_f32(u: number): number;
  *
  * @param {object} params
  * @param {Uint32Array} params.words instruction words for the section (SPAWN or UPDATE)
- * @param {Float32Array} params.constants constant pool (4 floats per entry)
- * @param {number} params.register_count
+ * @param {Float32Array} params.constants constant pool, one float per word
+ * @param {number} params.register_count size of the register file in `f32` slots
  * @param {Uint32Array} params.record particle record words (mutated in place); attributes are f32 bits
  * @param {number[][]} [params.builtins] builtin values indexed by {@link VM_BUILTIN} id, each a 4-array
  * @param {number} [params.rng_state] initial RNG state (u32)

package/src/shade/renderer/particles/vm/ParticleVMReference.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"ParticleVMReference.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/ParticleVMReference.js"],"names":[],"mappings":"AAQA;;;;;;;GAOG;AACH,gCAHW,MAAM;WACK,MAAM;WAAS,MAAM;EAW1C;AAED;;;;;GAKG;AACH,mCAHW,MAAM,GACJ,MAAM,CAIlB;AAED;;;;;;;;;;;;;;;;;;GAkBG;AACH;WATW,WAAW;eACX,YAAY;oBACZ,MAAM;YACN,WAAW;eACX,MAAM,EAAE,EAAE;gBACV,MAAM;2BACG,MAAM,KAAK,MAAM,KAAK,MAAM;;YACzB,OAAO;eAAa,MAAM;EAoPhD"}
+{"version":3,"file":"ParticleVMReference.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/ParticleVMReference.js"],"names":[],"mappings":"AAWA;;;;;;;GAOG;AACH,gCAHW,MAAM;WACK,MAAM;WAAS,MAAM;EAW1C;AAED;;;;;GAKG;AACH,mCAHW,MAAM,GACJ,MAAM,CAIlB;AAED;;;;;;;;;;;;;;;;;;GAkBG;AACH;WATW,WAAW;eACX,YAAY;oBACZ,MAAM;YACN,WAAW;eACX,MAAM,EAAE,EAAE;gBACV,MAAM;2BACG,MAAM,KAAK,MAAM,KAAK,MAAM;;YACzB,OAAO;eAAa,MAAM;EA2PhD"}

package/src/shade/renderer/particles/vm/ParticleVMReference.js

@@ -2,9 +2,12 @@ import {
     PARTICLE_VM_INSTRUCTION_WORDS,
     PARTICLE_VM_MAX_INSTRUCTIONS,
 } from "../ParticleConstants.js";
-import { VM_OP, VM_RANDOM_MODE } from "../isa/ParticleVMISA.js";
-
-const TWO_PI = Math.PI * 2;
+import {
+    VM_OP,
+    vm_decode_op,
+    vm_decode_width,
+    vm_operation_width,
+} from "../isa/ParticleVMISA.js";
 
 /**
  * PCG-RXS-M-XS-32 step. Deterministic `u32 -> u32`, byte-identical to the WGSL implementation in
@@ -46,8 +49,8 @@ export function u32_to_unit_f32(u) {
  *
  * @param {object} params
  * @param {Uint32Array} params.words instruction words for the section (SPAWN or UPDATE)
- * @param {Float32Array} params.constants constant pool (4 floats per entry)
- * @param {number} params.register_count
+ * @param {Float32Array} params.constants constant pool, one float per word
+ * @param {number} params.register_count size of the register file in `f32` slots
  * @param {Uint32Array} params.record particle record words (mutated in place); attributes are f32 bits
  * @param {number[][]} [params.builtins] builtin values indexed by {@link VM_BUILTIN} id, each a 4-array
  * @param {number} [params.rng_state] initial RNG state (u32)
@@ -63,8 +66,8 @@ export function execute_particle_vm({
     rng_state = 0,
     sampleCurve = () => 0,
 }) {
-    // Register file: register_count lanes of vec4, flat.
-    const reg = new Float32Array(register_count * 4);
+    // Register file: one f32 per slot. A value of width w occupies w consecutive slots.
+    const reg = new Float32Array(register_count);
 
     // Reinterpret the record's u32 words as f32 for attribute load/store.
     const record_f32 = new Float32Array(record.buffer, record.byteOffset, record.length);
@@ -82,16 +85,21 @@ export function execute_particle_vm({
 
     for (let pc = 0; pc < instruction_count; pc++) {
         const base = pc * PARTICLE_VM_INSTRUCTION_WORDS;
-        const op = words[base];
+        const word0 = words[base];
+        const op = vm_decode_op(word0);
         const dst = words[base + 1];
         const s0 = words[base + 2];
         const s1 = words[base + 3];
         const s2 = words[base + 4];
 
-        const d = dst * 4;
-        const a = s0 * 4;
-        const b = s1 * 4;
-        const c = s2 * 4;
+        /** Lanes this instruction spans. Fixed-width opcodes ignore the encoded field. */
+        const w = vm_operation_width(op, vm_decode_width(word0));
+
+        // Register operands are slot indices; lane `i` of an operand is slot `base + i`.
+        const d = dst;
+        const a = s0;
+        const b = s1;
+        const c = s2;
 
         switch (op) {
             case VM_OP.HALT:
@@ -100,193 +108,195 @@ export function execute_particle_vm({
                 break;
 
             case VM_OP.MOV:
-                reg[d] = reg[a]; reg[d + 1] = reg[a + 1]; reg[d + 2] = reg[a + 2]; reg[d + 3] = reg[a + 3];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i];
                 break;
 
             case VM_OP.LOAD_CONST: {
-                const k = s0 * 4;
-                reg[d] = constants[k]; reg[d + 1] = constants[k + 1]; reg[d + 2] = constants[k + 2]; reg[d + 3] = constants[k + 3];
+                // The pool is addressed by word, so the operand is where the value starts, not
+                // which vec4 slot holds it.
+                for (let i = 0; i < w; i++) reg[d + i] = constants[s0 + i];
                 break;
             }
 
             case VM_OP.LOAD_ATTR: {
+                // Lanes past the attribute's component count read zero — a one-component attribute
+                // asked for at width 3 is (x, 0, 0), which is what widening it costs: nothing.
                 const off = s0; const comp = s1;
-                reg[d] = comp > 0 ? record_f32[off] : 0;
-                reg[d + 1] = comp > 1 ? record_f32[off + 1] : 0;
-                reg[d + 2] = comp > 2 ? record_f32[off + 2] : 0;
-                reg[d + 3] = comp > 3 ? record_f32[off + 3] : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = i < comp ? record_f32[off + i] : 0;
                 break;
             }
 
             case VM_OP.STORE_ATTR: {
-                const off = s0; const comp = s1; const src = dst * 4;
-                if (comp > 0) record_f32[off] = reg[src];
-                if (comp > 1) record_f32[off + 1] = reg[src + 1];
-                if (comp > 2) record_f32[off + 2] = reg[src + 2];
-                if (comp > 3) record_f32[off + 3] = reg[src + 3];
+                const off = s0; const comp = s1; const src = dst;
+                for (let i = 0; i < comp; i++) record_f32[off + i] = reg[src + i];
                 break;
             }
 
             case VM_OP.LOAD_BUILTIN: {
                 const v = builtins[s0] ?? [0, 0, 0, 0];
-                reg[d] = v[0] ?? 0; reg[d + 1] = v[1] ?? 0; reg[d + 2] = v[2] ?? 0; reg[d + 3] = v[3] ?? 0;
+                for (let i = 0; i < w; i++) reg[d + i] = v[i] ?? 0;
                 break;
             }
 
             case VM_OP.KILL:
-                if (reg[dst * 4] > 0) killed = true;
+                if (reg[dst] > 0) killed = true;
                 break;
 
             case VM_OP.ADD:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] + reg[b + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] + reg[b + i];
                 break;
             case VM_OP.SUB:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] - reg[b + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] - reg[b + i];
                 break;
             case VM_OP.MUL:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] * reg[b + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * reg[b + i];
                 break;
             case VM_OP.DIV:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] / reg[b + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] / reg[b + i];
                 break;
             case VM_OP.MAD:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] * reg[b + i] + reg[c + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * reg[b + i] + reg[c + i];
                 break;
             case VM_OP.MIN:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.min(reg[a + i], reg[b + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.min(reg[a + i], reg[b + i]);
                 break;
             case VM_OP.MAX:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.max(reg[a + i], reg[b + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.max(reg[a + i], reg[b + i]);
                 break;
             case VM_OP.MIX:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] + (reg[b + i] - reg[a + i]) * reg[c + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] + (reg[b + i] - reg[a + i]) * reg[c + i];
                 break;
             case VM_OP.CLAMP:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.min(Math.max(reg[a + i], reg[b + i]), reg[c + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.min(Math.max(reg[a + i], reg[b + i]), reg[c + i]);
                 break;
             case VM_OP.SCALE: {
                 const scale = reg[b];
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] * scale;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * scale;
                 break;
             }
 
             case VM_OP.NEG:
-                for (let i = 0; i < 4; i++) reg[d + i] = -reg[a + i];
+                for (let i = 0; i < w; i++) reg[d + i] = -reg[a + i];
                 break;
             case VM_OP.ABS:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.abs(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.abs(reg[a + i]);
                 break;
             case VM_OP.FLOOR:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.floor(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.floor(reg[a + i]);
                 break;
             case VM_OP.FRACT:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] - Math.floor(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] - Math.floor(reg[a + i]);
                 break;
             case VM_OP.SQRT:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.sqrt(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.sqrt(reg[a + i]);
                 break;
             case VM_OP.SIN:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.sin(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.sin(reg[a + i]);
                 break;
             case VM_OP.COS:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.cos(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.cos(reg[a + i]);
                 break;
             case VM_OP.EXP:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.exp(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.exp(reg[a + i]);
                 break;
             case VM_OP.LOG:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.log(reg[a + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.log(reg[a + i]);
                 break;
             case VM_OP.POW:
-                for (let i = 0; i < 4; i++) reg[d + i] = Math.pow(reg[a + i], reg[b + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = Math.pow(reg[a + i], reg[b + i]);
                 break;
             case VM_OP.STEP:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[b + i] < reg[a + i] ? 0 : 1;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[b + i] < reg[a + i] ? 0 : 1;
                 break;
             case VM_OP.SMOOTHSTEP:
-                for (let i = 0; i < 4; i++) reg[d + i] = smoothstep(reg[a + i], reg[b + i], reg[c + i]);
+                for (let i = 0; i < w; i++) reg[d + i] = smoothstep(reg[a + i], reg[b + i], reg[c + i]);
                 break;
 
+            // The reductions write a single lane. Whatever wants the result wider gets an explicit
+            // broadcast from the compiler; the implicit fill-all-four is gone.
             case VM_OP.DOT: {
-                const dp = reg[a] * reg[b] + reg[a + 1] * reg[b + 1] + reg[a + 2] * reg[b + 2];
-                reg[d] = dp; reg[d + 1] = dp; reg[d + 2] = dp; reg[d + 3] = dp;
+                let dp = 0;
+                for (let i = 0; i < w; i++) dp += reg[a + i] * reg[b + i];
+                reg[d] = dp;
                 break;
             }
             case VM_OP.CROSS: {
-                const x = reg[a + 1] * reg[b + 2] - reg[a + 2] * reg[b + 1];
-                const y = reg[a + 2] * reg[b] - reg[a] * reg[b + 2];
-                const z = reg[a] * reg[b + 1] - reg[a + 1] * reg[b];
-                reg[d] = x; reg[d + 1] = y; reg[d + 2] = z; reg[d + 3] = 0;
+                // Read both sources out before writing: the destination is allowed to be one of them.
+                const ax = reg[a], ay = reg[a + 1], az = reg[a + 2];
+                const bx = reg[b], by = reg[b + 1], bz = reg[b + 2];
+                reg[d] = ay * bz - az * by;
+                reg[d + 1] = az * bx - ax * bz;
+                reg[d + 2] = ax * by - ay * bx;
+                // A fourth lane, if asked for, is the zero the opcode used to append.
+                for (let i = 3; i < w; i++) reg[d + i] = 0;
                 break;
             }
             case VM_OP.LENGTH: {
-                const len = Math.sqrt(reg[a] * reg[a] + reg[a + 1] * reg[a + 1] + reg[a + 2] * reg[a + 2]);
-                reg[d] = len; reg[d + 1] = len; reg[d + 2] = len; reg[d + 3] = len;
+                let sum = 0;
+                for (let i = 0; i < w; i++) sum += reg[a + i] * reg[a + i];
+                reg[d] = Math.sqrt(sum);
                 break;
             }
             case VM_OP.NORMALIZE: {
-                const len = Math.sqrt(reg[a] * reg[a] + reg[a + 1] * reg[a + 1] + reg[a + 2] * reg[a + 2]);
+                let sum = 0;
+                for (let i = 0; i < w; i++) sum += reg[a + i] * reg[a + i];
+                const len = Math.sqrt(sum);
                 const inv = len > 0 ? 1 / len : 0;
-                reg[d] = reg[a] * inv; reg[d + 1] = reg[a + 1] * inv; reg[d + 2] = reg[a + 2] * inv; reg[d + 3] = reg[a + 3];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] * inv;
                 break;
             }
             case VM_OP.DISTANCE: {
-                const dx = reg[a] - reg[b], dy = reg[a + 1] - reg[b + 1], dz = reg[a + 2] - reg[b + 2];
-                const dist = Math.sqrt(dx * dx + dy * dy + dz * dz);
-                reg[d] = dist; reg[d + 1] = dist; reg[d + 2] = dist; reg[d + 3] = dist;
+                let sum = 0;
+                for (let i = 0; i < w; i++) {
+                    const e = reg[a + i] - reg[b + i];
+                    sum += e * e;
+                }
+                reg[d] = Math.sqrt(sum);
                 break;
             }
             case VM_OP.SWIZZLE: {
+                // Selected lanes are read before any is written, so an in-place swizzle is safe.
                 const pattern = s1;
-                const src = [reg[a], reg[a + 1], reg[a + 2], reg[a + 3]];
-                reg[d] = src[pattern & 3];
-                reg[d + 1] = src[(pattern >> 2) & 3];
-                reg[d + 2] = src[(pattern >> 4) & 3];
-                reg[d + 3] = src[(pattern >> 6) & 3];
+                const l0 = reg[a + (pattern & 3)];
+                const l1 = reg[a + ((pattern >> 2) & 3)];
+                const l2 = reg[a + ((pattern >> 4) & 3)];
+                const l3 = reg[a + ((pattern >> 6) & 3)];
+                if (w > 0) reg[d] = l0;
+                if (w > 1) reg[d + 1] = l1;
+                if (w > 2) reg[d + 2] = l2;
+                if (w > 3) reg[d + 3] = l3;
                 break;
             }
 
             case VM_OP.CMP_LT:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] < reg[b + i] ? 1 : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] < reg[b + i] ? 1 : 0;
                 break;
             case VM_OP.CMP_LE:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] <= reg[b + i] ? 1 : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] <= reg[b + i] ? 1 : 0;
                 break;
             case VM_OP.CMP_GT:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] > reg[b + i] ? 1 : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] > reg[b + i] ? 1 : 0;
                 break;
             case VM_OP.CMP_GE:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] >= reg[b + i] ? 1 : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] >= reg[b + i] ? 1 : 0;
                 break;
             case VM_OP.CMP_EQ:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[a + i] === reg[b + i] ? 1 : 0;
+                for (let i = 0; i < w; i++) reg[d + i] = reg[a + i] === reg[b + i] ? 1 : 0;
                 break;
             case VM_OP.SELECT:
-                for (let i = 0; i < 4; i++) reg[d + i] = reg[c + i] > 0.5 ? reg[b + i] : reg[a + i];
+                for (let i = 0; i < w; i++) reg[d + i] = reg[c + i] > 0.5 ? reg[b + i] : reg[a + i];
                 break;
 
-            case VM_OP.RANDOM: {
-                const mode = s0;
-                if (mode === VM_RANDOM_MODE.UNIFORM) {
-                    reg[d] = draw_unit(); reg[d + 1] = draw_unit(); reg[d + 2] = draw_unit(); reg[d + 3] = draw_unit();
-                } else if (mode === VM_RANDOM_MODE.UNIFORM_SIGNED) {
-                    reg[d] = draw_unit() * 2 - 1; reg[d + 1] = draw_unit() * 2 - 1; reg[d + 2] = draw_unit() * 2 - 1; reg[d + 3] = draw_unit() * 2 - 1;
-                } else if (mode === VM_RANDOM_MODE.UNIT_SPHERE) {
-                    const z = draw_unit() * 2 - 1;
-                    const ang = draw_unit() * TWO_PI;
-                    const r = Math.sqrt(Math.max(0, 1 - z * z));
-                    reg[d] = r * Math.cos(ang); reg[d + 1] = r * Math.sin(ang); reg[d + 2] = z; reg[d + 3] = 0;
-                } else { // UNIT_DISK
-                    const r = Math.sqrt(draw_unit());
-                    const ang = draw_unit() * TWO_PI;
-                    reg[d] = r * Math.cos(ang); reg[d + 1] = r * Math.sin(ang); reg[d + 2] = 0; reg[d + 3] = 0;
-                }
+            // One draw per lane. Draw counts are part of the program's meaning — the draws are a
+            // sequence, so one fewer moves every value after it — and with distributions gone the
+            // count is exactly the width.
+            case VM_OP.RANDOM:
+                for (let i = 0; i < w; i++) reg[d + i] = draw_unit();
                 break;
-            }
 
             case VM_OP.CURVE: {
                 const v = sampleCurve(s0, reg[b]);
-                reg[d] = v; reg[d + 1] = v; reg[d + 2] = v; reg[d + 3] = v;
+                for (let i = 0; i < w; i++) reg[d + i] = v;
                 break;
             }
 

package/src/shade/renderer/particles/vm/chunk_particle_vm.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"chunk_particle_vm.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/chunk_particle_vm.js"],"names":[],"mappings":"AA+OA;;;GAGG;AACH,gCAFU,SAAS,CAEqC;0BAnP9B,oCAAoC"}
+{"version":3,"file":"chunk_particle_vm.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/vm/chunk_particle_vm.js"],"names":[],"mappings":"AAmXA;;;GAGG;AACH,gCAFU,SAAS,CAEqD;0BAvX9C,oCAAoC"}