@woosh/meep-engine 3.15.0 → 3.17.0

package/src/shade/renderer/particles/isa/ParticleVMISA.d.ts

@@ -1,11 +1,46 @@
 /**
+ * Pack word 0.
+ *
  * @param {number} op
- * @returns {string} mnemonic, or `OP_<n>` if unknown
+ * @param {number} width lane count, `0..4`
+ * @param {number} dst destination register, `0..255`
+ * @param {number} kinds the three source kinds as one field — see {@link vm_pack_kinds}
+ * @returns {number}
+ */
+export function vm_encode_word0(op: number, width: number, dst: number, kinds: number): number;
+/**
+ * The three source kinds as the one field {@link vm_encode_word0} takes.
+ *
+ * @param {number} s0
+ * @param {number} s1
+ * @param {number} s2
+ * @returns {number}
  */
-export function vm_op_name(op: number): string;
+export function vm_pack_kinds(s0: number, s1: number, s2: number): number;
+/** @param {number} word0 @returns {number} opcode */
+export function vm_decode_op(word0: number): number;
+/** @param {number} word0 @returns {number} lane count */
+export function vm_decode_width(word0: number): number;
+/** @param {number} word0 @returns {number} destination register */
+export function vm_decode_dst(word0: number): number;
+/** @param {number} word0 @returns {number} the three source kinds as one field */
+export function vm_decode_kinds(word0: number): number;
 /**
- * Pack a swizzle pattern from four lane selectors into the 8-bit form used by the `SWIZZLE` opcode.
- * Selector values: 0=x, 1=y, 2=z, 3=w.
+ * @param {number} word0
+ * @param {number} slot source slot, `0..2`
+ * @returns {number} a {@link VM_KIND}
+ */
+export function vm_decode_kind(word0: number, slot: number): number;
+/** @returns {number} word 0 with its width replaced */
+export function vm_with_width(word0: any, width: any): number;
+/** @returns {number} word 0 with its destination replaced */
+export function vm_with_dst(word0: any, dst: any): number;
+/** @returns {number} word 0 with one source's kind replaced */
+export function vm_with_kind(word0: any, slot: any, kind: any): number;
+/**
+ * Pack a swizzle pattern from four lane selectors: selector `i` in bits `[2i, 2i+2)`, values
+ * 0=x, 1=y, 2=z, 3=w.
+ *
  * @param {number} x
  * @param {number} y
  * @param {number} z
@@ -14,20 +49,236 @@ export function vm_op_name(op: number): string;
  */
 export function pack_swizzle(x: number, y: number, z: number, w: number): number;
 /**
- * Operand slot roles, used for documentation, assembler validation and disassembly.
+ * @param {number} pattern
+ * @param {number} lane
+ * @returns {number} the lane the pattern selects for output lane `lane`
+ */
+export function swizzle_selector(pattern: number, lane: number): number;
+/**
+ * A register operand word: a base slot read through a pattern.
+ *
+ * The pattern is stored XOR {@link VM_SWIZZLE_IDENTITY}, so the identity is a zero byte and a bare
+ * slot index is the run at that slot. Nothing else about the word depends on that choice; read the
+ * pattern back with {@link vm_operand_pattern} rather than the bits.
+ *
+ * @param {number} base first register slot
+ * @param {number} [pattern] a packed swizzle; the run as it lies when left out
+ * @returns {number}
+ */
+export function vm_register(base: number, pattern?: number): number;
+/** @param {number} word a register operand @returns {number} its base slot */
+export function vm_operand_base(word: number): number;
+/** @param {number} word a register operand @returns {number} its swizzle, as {@link pack_swizzle} packs one */
+export function vm_operand_pattern(word: number): number;
+/**
+ * @param {number} word a register operand
+ * @param {number} lane
+ * @returns {number} the slot lane `lane` of the operand reads
+ */
+export function vm_operand_slot(word: number, lane: number): number;
+/** @returns {number} the operand moved to another base, keeping its swizzle */
+export function vm_operand_with_base(word: any, base: any): number;
+/**
+ * How far into the file a register operand reaches when `lanes` lanes of it are read: one past the
+ * widest selector among them. The selectors above `lanes` are never read and do not count.
+ *
+ * @param {number} word a register operand
+ * @param {number} lanes how many lanes the instruction reads of it
+ * @returns {number}
+ */
+export function vm_operand_span(word: number, lanes: number): number;
+/**
+ * The canonical spelling of a register operand read at `lanes` lanes: the base is the lowest slot
+ * any lane reads, and selectors above the lanes read are the identity, since they name nothing. So
+ * `r0.yz` is `r1`, `r0.zy` is `r1.yx`, and a broadcast of lane 3 is the run at lane 3 — one
+ * spelling per meaning, which is what lets two instructions be compared word for word.
+ *
+ * @param {number} word a register operand
+ * @param {number} lanes how many lanes the instruction reads of it
+ * @returns {number}
+ */
+export function vm_canonical_register(word: number, lanes: number): number;
+/** @param {number} value @returns {number} the `f32` bit pattern the value rounds to */
+export function vm_f32_bits(value: number): number;
+/** @param {number} bits @returns {number} the `f32` those bits are */
+export function vm_f32_value(bits: number): number;
+/**
+ * A literal source operand, as `InstructionStream.emit` takes one in a source slot.
+ *
+ * @param {number} value
+ * @returns {{kind: number, word: number}}
+ */
+export function vm_immediate(value: number): {
+    kind: number;
+    word: number;
+};
+/**
+ * Widths are read out of the opcode's metadata; see {@link VM_ISA}.
+ *
+ * @param {number} op
+ * @param {number} width the instruction's width field
+ * @returns {number} the lane count the opcode actually operates on
+ */
+export function vm_operation_width(op: number, width: number): number;
+/**
+ * How many lanes an instruction writes to its destination register.
+ * @param {number} op
+ * @param {number} width the instruction's width field
+ * @returns {number}
+ */
+export function vm_dest_width(op: number, width: number): number;
+/**
+ * The four words of an instruction, with every register operand in its canonical spelling.
+ *
+ * Both the assembler's `InstructionStream.emit` and the assembly parser build instructions here, so
+ * the one encoding rule that is a choice rather than a fact — how a swizzle is spelled — is made in
+ * one place: selectors above the lanes an operand is read at are the identity, and a run of
+ * consecutive selectors is the identity at a higher base. Two instructions that mean the same thing
+ * then have the same words, which is what lets the optimizer compare them.
+ *
+ * @param {number} op
+ * @param {number} width lane count, `0..4`
+ * @param {number} dst destination register
+ * @param {number[]} kinds a {@link VM_KIND} per source slot
+ * @param {number[]} sources the three source words
+ * @returns {number[]}
+ */
+export function vm_pack_instruction(op: number, width: number, dst: number, kinds: number[], sources: number[]): number[];
+/**
+ * An encoded instruction, re-spelled canonically — what a pass wants after it has moved an operand.
+ *
+ * @param {ArrayLike<number>} words the four words of a single instruction
+ * @returns {number[]}
+ */
+export function vm_repack_instruction(words: ArrayLike<number>): number[];
+/**
+ * @typedef {object} ParticleVMOperand
+ * @property {number} slot source slot, `0..2`
+ * @property {number} kind a {@link VM_KIND}, never `NONE`
+ * @property {number} word the source word as encoded
+ * @property {number} lanes how many lanes the instruction reads of it: the operation's width, or one
+ *   for a slot the ISA marks scalar
+ * @property {number} span register slots the operand reaches from its base, for a register; `0` for a
+ *   literal
+ */
+/**
+ * Visit every source operand of an instruction — every slot whose kind is not `NONE` — with how
+ * many lanes the opcode reads of it and how far into the file it reaches.
+ *
+ * The rules for the reach are not uniform and live here rather than in each caller: a source is
+ * read as wide as the operation runs unless the ISA marks that slot scalar, and a register operand
+ * reaches as far as its widest selector among the lanes read.
+ *
+ * @param {ArrayLike<number>} words an instruction stream
+ * @param {number} base index of the instruction's first word
+ * @param {function(ParticleVMOperand):void} visit the one object is reused between calls; copy it
+ *   to keep it
+ */
+export function vm_visit_operands(words: ArrayLike<number>, base: number, visit: (arg0: ParticleVMOperand) => void): void;
+/**
+ * Visit every run of the register file an instruction touches, as the slot it starts at and how
+ * many consecutive slots it reaches: the destination as far as the opcode writes, and each register
+ * source as far as its selectors read. What anyone sizing or bounds-checking the file wants; a
+ * literal is not a run of the file and is not visited.
+ *
+ * @param {ArrayLike<number>} words an instruction stream
+ * @param {number} base index of the instruction's first word
+ * @param {function(number, number):void} visit called `(slot, span)` per run
+ */
+export function vm_visit_register_runs(words: ArrayLike<number>, base: number, visit: (arg0: number, arg1: number) => void): void;
+/**
+ * Whether the kind bits of an instruction agree with what its opcode reads: a register-role slot
+ * carries a register or a literal, every other slot carries nothing. Both the assembler and
+ * `ParticleProgram.validate` ask here rather than each restating the rule.
+ *
+ * @param {ArrayLike<number>} words an instruction stream
+ * @param {number} base index of the instruction's first word
+ * @returns {string|null} what is wrong, or `null` when nothing is
+ */
+export function vm_kinds_problem(words: ArrayLike<number>, base: number): string | null;
+/**
+ * The kinds an opcode's sources carry when every register-role slot holds a register: the default
+ * an assembler starts from, before any literal is marked.
+ *
+ * @param {number} op
+ * @returns {number} a kinds field for {@link vm_encode_word0}
+ */
+export function vm_register_kinds(op: number): number;
+/**
+ * Particle VM instruction-set architecture — the single source of truth.
+ *
+ * Both executors (the JS reference in {@link ../vm/ParticleVMReference.js} and the WGSL interpreter
+ * in {@link ../vm/chunk_particle_vm.js}) implement exactly this table, and the parity spec asserts
+ * that neither drifts from it. The assembler and node compiler emit against these opcode numbers.
+ *
+ * ## Encoding
+ *
+ * Every instruction is {@link PARTICLE_VM_INSTRUCTION_WORDS} `u32` words — the size of one
+ * `vec4<u32>`, so the four loads that fetch it are one 16-byte load by the time a shader compiler is
+ * done with them:
+ *
+ *     [ op | width << 8 | kinds << 16 | dst << 24,   s0,   s1,   s2 ]
+ *
+ * Word 0 packs the opcode (bits 0..7), the lane count the operation spans (8..10), the kind of each
+ * source (two bits per slot at 16..21) and the destination register (24..31). The other three words
+ * are the sources. Registers hold single floats, so a `vec3` value is three consecutive slots and an
+ * `ADD` with width 3 adds three lanes; widths are what stop every value costing four registers.
+ *
+ * ## Operands
+ *
+ * A source word means what its kind says — see {@link VM_KIND}:
+ *
+ * - `NONE`: not an operand the VM resolves — an unused slot, or a raw field the opcode reads for
+ *   itself: an attribute offset, a component count, a builtin id, a curve handle, a pool index.
+ * - `REG`: a register operand. Bits 0..7 are the first slot, bits 8..15 a swizzle — see below.
+ * - `IMM`: the word IS the `f32` bit pattern of a literal, read in every lane. A scalar or a
+ *   lane-uniform vector costs no register and no load; only a vector whose lanes differ still goes
+ *   through the pool with `LOAD_CONST`.
+ *
+ * The kinds exist so the interpreter can resolve every source the same way, before the opcode runs
+ * and without consulting a table: it reads the kind, gathers the lanes, and the opcode body sees
+ * three four-lane values whatever they came from. A kind is encoding, not an opcode mode.
+ *
+ * ## Swizzles
+ *
+ * Every register operand carries a swizzle: four two-bit lane selectors in bits 8..15, packed as
+ * {@link pack_swizzle} packs them, and stored XOR the identity pattern `.xyzw`
+ * ({@link VM_SWIZZLE_IDENTITY}). That choice is what makes a bare slot index a register operand:
+ * with a zero swizzle byte lane `c` reads slot `base + c`, the run as it lies, and `r5.xxxx` is the
+ * same word with the selectors that name lane 0 four times. Lane `c` of an operand reads slot
+ * `base + selector[c]`, so an operand reaches as far into the file as its widest selector below the
+ * instruction's width — never further, whatever the selectors above the width say.
+ *
+ * Swizzles are why there is no `SWIZZLE` opcode and no `SCALE`: a permutation or a broadcast is a
+ * `MOV` whose source is swizzled, and a vector times a scalar is `MUL v, s.xxxx`. Both were
+ * opcodes that existed to do what an operand can now say for itself, which is the direction the
+ * ISA takes whenever it can — see {@link VM_OP} for the holes they left.
+ *
+ * ## Resolution before execution
+ *
+ * The interpreter reads every source lane before it writes any destination lane. Operands may
+ * therefore overlap the destination in any way — `MOV.2 r0, r0.yx` swaps two slots in place — and
+ * there is no aliasing rule for a program to break. The reductions write one lane whatever they
+ * read (see {@link VM_DEST}); a few opcodes fix their lane count (see {@link VM_WIDTH}).
+ *
+ * There is no control flow: conditionals are `CMP` + `SELECT` and destruction is `KILL`, which
+ * keeps the interpreter a flat `switch` inside a bounded loop.
+ */
+/** Words per instruction. Four, so an instruction is one `vec4<u32>` fetch. @type {number} */
+export const PARTICLE_VM_INSTRUCTION_WORDS: number;
+/**
+ * Operand slot roles: what an opcode reads a source slot as. Used for assembler validation,
+ * disassembly and for deriving each slot's {@link VM_KIND }.
  */
 export type VM_OPERAND = string;
 export namespace VM_OPERAND {
     let NONE: string;
     let REG: string;
-    let DST: string;
     let CONST: string;
     let ATTR_OFFSET: string;
     let COMP: string;
     let BUILTIN: string;
     let CURVE: string;
-    let RANDOM_MODE: string;
-    let SWIZZLE: string;
 }
 /**
  * Builtin inputs the host shader assembles per-invocation and the VM reads via `LOAD_BUILTIN`.
@@ -44,17 +295,18 @@ export namespace VM_BUILTIN {
     let TIME: number;
 }
 /**
- * Random distribution modes for the `RANDOM` opcode.
+ * How many lanes each builtin fills. The lanes past that read zero when a load is wider — see
+ * `vm_load_builtin` in {@link ../vm/chunk_particle_vm.js} — so this is a builtin's type as far as
+ * a program is concerned, and it is what types a `builtin` node in a graph.
+ *
+ * @type {Object<number, number>}
  */
-export type VM_RANDOM_MODE = number;
-export namespace VM_RANDOM_MODE {
-    let UNIFORM: number;
-    let UNIFORM_SIGNED: number;
-    let UNIT_SPHERE: number;
-    let UNIT_DISK: number;
-}
+export const VM_BUILTIN_COMPONENTS: {
+    [x: number]: number;
+};
 /**
- * Opcodes. Numbers are stable wire values — never renumber, only append.
+ * Opcodes. Numbers are stable wire values — never renumber, only append. 19 was `SCALE` and 45 was
+ * `SWIZZLE`; both are spelled by an operand swizzle now and the numbers stay unused.
  */
 export type VM_OP = number;
 export namespace VM_OP {
@@ -75,7 +327,6 @@ export namespace VM_OP {
     export let MAX: number;
     export let MIX: number;
     export let CLAMP: number;
-    export let SCALE: number;
     export let NEG: number;
     export let ABS: number;
     export let FLOOR: number;
@@ -88,13 +339,16 @@ export namespace VM_OP {
     export let POW: number;
     export let STEP: number;
     export let SMOOTHSTEP: number;
+    export let RSQRT: number;
+    export let TAN: number;
+    export let ASIN: number;
+    export let ACOS: number;
+    export let ATAN2: number;
     export let DOT: number;
     export let CROSS: number;
     export let LENGTH: number;
     export let NORMALIZE: number;
     export let DISTANCE: number;
-    let SWIZZLE_1: number;
-    export { SWIZZLE_1 as SWIZZLE };
     export let CMP_LT: number;
     export let CMP_LE: number;
     export let CMP_GT: number;
@@ -106,15 +360,111 @@ export namespace VM_OP {
     export { CURVE_1 as CURVE };
 }
 /**
- * Per-opcode metadata: mnemonic + the role of each of the three operand slots `[s0, s1, s2]`.
+ * How an opcode reads the instruction's width field — the lane count it operates on.
+ */
+export type VM_WIDTH = string;
+export namespace VM_WIDTH {
+    let NONE_1: string;
+    export { NONE_1 as NONE };
+    export let VARIABLE: string;
+    export let ONE: string;
+    export let THREE: string;
+}
+/**
+ * How many lanes an opcode writes to its destination, relative to the operation's width.
+ */
+export type VM_DEST = string;
+export namespace VM_DEST {
+    let NONE_2: string;
+    export { NONE_2 as NONE };
+    export let WIDTH: string;
+    let ONE_1: string;
+    export { ONE_1 as ONE };
+}
+/**
+ * Widest an operation may be. Registers hold scalars; four is what a `vec4` value needs and what a
+ * two-bit lane selector can address.
+ * @type {number}
+ */
+export const VM_MAX_WIDTH: number;
+/** Mask selecting the opcode out of word 0. @type {number} */
+export const VM_OP_MASK: number;
+/** Bit position of the width field in word 0. @type {number} */
+export const VM_WIDTH_SHIFT: number;
+/** Mask selecting the width out of word 0, once shifted down. @type {number} */
+export const VM_WIDTH_MASK: number;
+/**
+ * What a source word means. Wire values; never renumber.
+ */
+export type VM_KIND = number;
+export namespace VM_KIND {
+    let NONE_3: number;
+    export { NONE_3 as NONE };
+    let REG_1: number;
+    export { REG_1 as REG };
+    export let IMM: number;
+}
+/**
+ * Bit position of the first source's kind in word 0. Source `n` has its two kind bits at
+ * `VM_KIND_SHIFT + 2n`, so the three together are bits 16..21.
+ * @type {number}
+ */
+export const VM_KIND_SHIFT: number;
+/** Bits per kind field. @type {number} */
+export const VM_KIND_BITS: number;
+/** Mask selecting one kind field, once shifted down. @type {number} */
+export const VM_KIND_MASK: number;
+/** Bit position of the destination register in word 0. @type {number} */
+export const VM_DST_SHIFT: number;
+/** Mask selecting the destination register out of word 0, once shifted down. @type {number} */
+export const VM_DST_MASK: number;
+/** The pattern that reads a run as it lies: `.xyzw`. @type {number} */
+export const VM_SWIZZLE_IDENTITY: number;
+/** The pattern that reads lane 0 in every lane: `.xxxx`. @type {number} */
+export const VM_SWIZZLE_BROADCAST: number;
+/** Mask selecting the base slot out of a register operand word. @type {number} */
+export const VM_OPERAND_BASE_MASK: number;
+/** Bit position of the swizzle byte in a register operand word. @type {number} */
+export const VM_OPERAND_SWIZZLE_SHIFT: number;
+/**
+ * Per-opcode metadata: mnemonic, whether it writes a destination, and the role of each source slot.
  *
  * Keyed by opcode number. Used by the assembler for validation/disassembly and by the parity
  * meta-test to enforce that every opcode is handled by both executors.
- * @type {Map<number, {name: string, dst: boolean, operands: [string, string, string]}>}
+ * @type {Map<number, {name: string, dst: boolean, operands: [string, string, string], width: string, dest: string, default_width: number, min_width: number, scalar_operands: number[]}>}
  */
 export const VM_ISA: Map<number, {
     name: string;
     dst: boolean;
     operands: [string, string, string];
+    width: string;
+    dest: string;
+    default_width: number;
+    min_width: number;
+    scalar_operands: number[];
 }>;
+export type ParticleVMOperand = {
+    /**
+     * source slot, `0..2`
+     */
+    slot: number;
+    /**
+     * a {@link VM_KIND }, never `NONE`
+     */
+    kind: number;
+    /**
+     * the source word as encoded
+     */
+    word: number;
+    /**
+     * how many lanes the instruction reads of it: the operation's width, or one
+     * for a slot the ISA marks scalar
+     */
+    lanes: number;
+    /**
+     * register slots the operand reaches from its base, for a register; `0` for a
+     * literal
+     */
+    span: number;
+};
 //# sourceMappingURL=ParticleVMISA.d.ts.map

package/src/shade/renderer/particles/isa/ParticleVMISA.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"ParticleVMISA.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/isa/ParticleVMISA.js"],"names":[],"mappings":"AAyNA;;;GAGG;AACH,+BAHW,MAAM,GACJ,MAAM,CAKlB;AAED;;;;;;;;GAQG;AACH,gCANW,MAAM,KACN,MAAM,KACN,MAAM,KACN,MAAM,GACJ,MAAM,CAIlB;;;;yBApNS,MAAM;;;;;;;;;;;;;;;;yBA2BN,MAAM;;;;;;;;;;;;;;6BA0BN,MAAM;;;;;;;;;;oBAeN,MAAM;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;AA0DhB;;;;;;GAMG;AACH,qBAFU,IAAI,MAAM,EAAE;IAAC,MAAM,MAAM,CAAC;IAAC,GAAG,EAAE,OAAO,CAAC;IAAC,QAAQ,EAAE,CAAC,MAAM,EAAE,MAAM,EAAE,MAAM,CAAC,CAAA;CAAC,CAAC,CAEvD"}
+{"version":3,"file":"ParticleVMISA.d.ts","sourceRoot":"","sources":["../../../../../../src/shade/renderer/particles/isa/ParticleVMISA.js"],"names":[],"mappings":"AA+QA;;;;;;;;GAQG;AACH,oCANW,MAAM,SACN,MAAM,OACN,MAAM,SACN,MAAM,GACJ,MAAM,CASlB;AAED;;;;;;;GAOG;AACH,kCALW,MAAM,MACN,MAAM,MACN,MAAM,GACJ,MAAM,CAQlB;AAED,qDAAqD;AACrD,oCADY,MAAM,GAAkB,MAAM,CAGzC;AAED,yDAAyD;AACzD,uCADY,MAAM,GAAkB,MAAM,CAGzC;AAED,mEAAmE;AACnE,qCADY,MAAM,GAAkB,MAAM,CAGzC;AAED,kFAAkF;AAClF,uCADY,MAAM,GAAkB,MAAM,CAGzC;AAED;;;;GAIG;AACH,sCAJW,MAAM,QACN,MAAM,GACJ,MAAM,CAIlB;AAED,uDAAuD;AACvD,uDADc,MAAM,CAGnB;AAED,6DAA6D;AAC7D,mDADc,MAAM,CAGnB;AAED,+DAA+D;AAC/D,gEADc,MAAM,CAKnB;AAID;;;;;;;;;GASG;AACH,gCANW,MAAM,KACN,MAAM,KACN,MAAM,KACN,MAAM,GACJ,MAAM,CAIlB;AAED;;;;GAIG;AACH,0CAJW,MAAM,QACN,MAAM,GACJ,MAAM,CAIlB;AAcD;;;;;;;;;;GAUG;AACH,kCAJW,MAAM,YACN,MAAM,GACJ,MAAM,CAIlB;AAED,8EAA8E;AAC9E,sCADY,MAAM,GAAoC,MAAM,CAG3D;AAED,+GAA+G;AAC/G,yCADY,MAAM,GAAoC,MAAM,CAG3D;AAED;;;;GAIG;AACH,sCAJW,MAAM,QACN,MAAM,GACJ,MAAM,CAIlB;AAED,+EAA+E;AAC/E,4DADc,MAAM,CAGnB;AAED;;;;;;;GAOG;AACH,sCAJW,MAAM,SACN,MAAM,GACJ,MAAM,CAYlB;AAED;;;;;;;;;GASG;AACH,4CAJW,MAAM,SACN,MAAM,GACJ,MAAM,CAoBlB;AAUD,wFAAwF;AACxF,mCADY,MAAM,GAAkB,MAAM,CAKzC;AAED,sEAAsE;AACtE,mCADY,MAAM,GAAiB,MAAM,CAKxC;AAED;;;;;GAKG;AACH,oCAHW,MAAM,GACJ;IAAC,IAAI,EAAE,MAAM,CAAC;IAAC,IAAI,EAAE,MAAM,CAAA;CAAC,CAIxC;AAID;;;;;;GAMG;AACH,uCAJW,MAAM,SACN,MAAM,GACJ,MAAM,CAelB;AAED;;;;;GAKG;AACH,kCAJW,MAAM,SACN,MAAM,GACJ,MAAM,CAclB;AA6HD;;;;;;;;;;;;;;;GAeG;AACH,wCAPW,MAAM,SACN,MAAM,OACN,MAAM,SACN,MAAM,EAAE,WACR,MAAM,EAAE,GACN,MAAM,EAAE,CAgBpB;AAED;;;;;GAKG;AACH,6CAHW,UAAU,MAAM,CAAC,GACf,MAAM,EAAE,CAYpB;AAID;;;;;;;;;GASG;AAEH;;;;;;;;;;;;GAYG;AACH,yCALW,UAAU,MAAM,CAAC,QACjB,MAAM,gBACG,iBAAiB,KAAE,IAAI,QAgC1C;AAED;;;;;;;;;GASG;AACH,8CAJW,UAAU,MAAM,CAAC,QACjB,MAAM,gBACG,MAAM,QAAE,MAAM,KAAE,IAAI,QAgBvC;AAED;;;;;;;;GAQG;AACH,wCAJW,UAAU,MAAM,CAAC,QACjB,MAAM,GACJ,MAAM,GAAC,IAAI,CA4BvB;AAED;;;;;;GAMG;AACH,sCAHW,MAAM,GACJ,MAAM,CAclB;AAj2BD;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;GA2DG;AAEH,8FAA8F;AAC9F,4CADoF,MAAM,CAC3C;;;;;yBAKrC,MAAM;;;;;;;;;;;;;yBAqBN,MAAM;;;;;;;;;;;AAwBhB;;;;;;GAMG;AACH;QAFiB,MAAM,GAAE,MAAM;EAW5B;;;;;oBAKO,MAAM;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;uBA2DN,MAAM;;;;;;;;;;;sBAeN,MAAM;;;;;;;;AAWhB;;;;GAIG;AACH,2BAFU,MAAM,CAEc;AAI9B,8DAA8D;AAC9D,yBADoD,MAAM,CAC3B;AAE/B,gEAAgE;AAChE,6BADsD,MAAM,CAC5B;AAEhC,gFAAgF;AAChF,4BADsE,MAAM,CAC3C;;;;sBAIvB,MAAM;;;;;;;;AAWhB;;;;GAIG;AACH,4BAFU,MAAM,CAEgB;AAEhC,0CAA0C;AAC1C,2BADgC,MAAM,CACR;AAE9B,uEAAuE;AACvE,2BAD6D,MAAM,CACnC;AAKhC,yEAAyE;AACzE,2BAD+D,MAAM,CACtC;AAE/B,+FAA+F;AAC/F,0BADqF,MAAM,CAC3D;AA2GhC,uEAAuE;AACvE,kCAD6D,MAAM,CACP;AAE5D,2EAA2E;AAC3E,mCADiE,MAAM,CACV;AAE7D,kFAAkF;AAClF,mCADwE,MAAM,CACrC;AAEzC,kFAAkF;AAClF,uCADwE,MAAM,CACpC;AA0K1C;;;;;;GAMG;AACH,qBAFU,IAAI,MAAM,EAAE;IAAC,MAAM,MAAM,CAAC;IAAC,GAAG,EAAE,OAAO,CAAC;IAAC,QAAQ,EAAE,CAAC,MAAM,EAAE,MAAM,EAAE,MAAM,CAAC,CAAC;IAAC,KAAK,EAAE,MAAM,CAAC;IAAC,IAAI,EAAE,MAAM,CAAC;IAAC,aAAa,EAAE,MAAM,CAAC;IAAC,SAAS,EAAE,MAAM,CAAC;IAAC,eAAe,EAAE,MAAM,EAAE,CAAA;CAAC,CAAC,CAEzJ;;;;;UAuKlB,MAAM;;;;UACN,MAAM;;;;UACN,MAAM;;;;;WACN,MAAM;;;;;UAEN,MAAM"}