wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,4481 @@
1
+ ;; x86-64 instruction selection and CLIF-to-MachInst lowering.
2
+
3
+ ;; The main lowering constructor term: takes a clif `Inst` and returns the
4
+ ;; register(s) within which the lowered instruction's result values live.
5
+ (decl partial lower (Inst) InstOutput)
6
+
7
+ ;; A variant of the main lowering constructor term, used for branches.
8
+ ;; The only difference is that it gets an extra argument holding a vector
9
+ ;; of branch targets to be used.
10
+ (decl partial lower_branch (Inst MachLabelSlice) Unit)
11
+
12
+ ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13
+
14
+ ;; `i64` and smaller.
15
+ (rule (lower (has_type (fits_in_64 ty)
16
+ (iconst (u64_from_imm64 x))))
17
+ (imm ty x))
18
+
19
+ ;; `i128`
20
+ (rule 1 (lower (has_type $I128
21
+ (iconst (u64_from_imm64 x))))
22
+ (value_regs (imm $I64 x)
23
+ (imm $I64 0)))
24
+
25
+ ;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
26
+
27
+ (rule (lower (f32const (u32_from_ieee32 x)))
28
+ (imm $F32 x))
29
+
30
+ ;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
31
+
32
+ (rule (lower (f64const (u64_from_ieee64 x)))
33
+ (imm $F64 x))
34
+
35
+ ;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
36
+
37
+ (rule (lower (has_type ty (null)))
38
+ (imm ty 0))
39
+
40
+ ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
41
+
42
+ ;; `i64` and smaller.
43
+
44
+ ;; Base case for 8 and 16-bit types
45
+ (rule -6 (lower (has_type (fits_in_16 ty)
46
+ (iadd x y)))
47
+ (x64_add ty x y))
48
+
49
+ ;; Base case for 32 and 64-bit types which might end up using the `lea`
50
+ ;; instruction to fold multiple operations into one.
51
+ ;;
52
+ ;; Note that at this time this always generates a `lea` pseudo-instruction,
53
+ ;; but the actual instruction emitted might be an `add` if it's equivalent.
54
+ ;; For more details on this see the `emit.rs` logic to emit
55
+ ;; `LoadEffectiveAddress`.
56
+ (rule -5 (lower (has_type (ty_32_or_64 ty) (iadd x y)))
57
+ (x64_lea ty (to_amode_add (mem_flags_trusted) x y (zero_offset))))
58
+
59
+ ;; Higher-priority cases than the previous two where a load can be sunk into
60
+ ;; the add instruction itself. Note that both operands are tested for
61
+ ;; sink-ability since addition is commutative
62
+ (rule -4 (lower (has_type (fits_in_64 ty)
63
+ (iadd x (sinkable_load y))))
64
+ (x64_add ty x y))
65
+ (rule -3 (lower (has_type (fits_in_64 ty)
66
+ (iadd (sinkable_load x) y)))
67
+ (x64_add ty y x))
68
+
69
+ ;; SSE.
70
+
71
+ (rule (lower (has_type (multi_lane 8 16)
72
+ (iadd x y)))
73
+ (x64_paddb x y))
74
+
75
+ (rule (lower (has_type (multi_lane 16 8)
76
+ (iadd x y)))
77
+ (x64_paddw x y))
78
+
79
+ (rule (lower (has_type (multi_lane 32 4)
80
+ (iadd x y)))
81
+ (x64_paddd x y))
82
+
83
+ (rule (lower (has_type (multi_lane 64 2)
84
+ (iadd x y)))
85
+ (x64_paddq x y))
86
+
87
+ ;; `i128`
88
+ (rule 1 (lower (has_type $I128 (iadd x y)))
89
+ ;; Get the high/low registers for `x`.
90
+ (let ((x_regs ValueRegs x)
91
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
92
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
93
+ ;; Get the high/low registers for `y`.
94
+ (let ((y_regs ValueRegs y)
95
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
96
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
97
+ ;; Do an add followed by an add-with-carry.
98
+ (with_flags (x64_add_with_flags_paired $I64 x_lo y_lo)
99
+ (x64_adc_paired $I64 x_hi y_hi)))))
100
+
101
+ ;;;; Helpers for `*_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
102
+
103
+ (decl construct_overflow_op (CC ProducesFlags) InstOutput)
104
+ (rule (construct_overflow_op cc inst)
105
+ (let ((results ValueRegs (with_flags inst
106
+ (x64_setcc_paired cc))))
107
+ (output_pair (value_regs_get results 0)
108
+ (value_regs_get results 1))))
109
+
110
+ (decl construct_overflow_op_alu (Type CC AluRmiROpcode Gpr GprMemImm) InstOutput)
111
+ (rule (construct_overflow_op_alu ty cc alu_op src1 src2)
112
+ (construct_overflow_op cc (x64_alurmi_with_flags_paired alu_op ty src1 src2)))
113
+
114
+ ;; This essentially creates
115
+ ;; alu_<op1> x_lo, y_lo
116
+ ;; alu_<op2> x_hi, y_hi
117
+ ;; set<cc> r8
118
+ (decl construct_overflow_op_alu_128 (CC AluRmiROpcode AluRmiROpcode Value Value) InstOutput)
119
+ (rule (construct_overflow_op_alu_128 cc op1 op2 x y)
120
+ ;; Get the high/low registers for `x`.
121
+ (let ((x_regs ValueRegs x)
122
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
123
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
124
+ ;; Get the high/low registers for `y`.
125
+ (let ((y_regs ValueRegs y)
126
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
127
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
128
+ (let ((lo_inst ProducesFlags (x64_alurmi_with_flags_paired op1 $I64 x_lo y_lo))
129
+ (hi_inst ConsumesAndProducesFlags (x64_alurmi_with_flags_chained op2 $I64 x_hi y_hi))
130
+ (of_inst ConsumesFlags (x64_setcc_paired cc))
131
+
132
+ (result MultiReg (with_flags_chained lo_inst hi_inst of_inst)))
133
+ (multi_reg_to_pair_and_single result)))))
134
+
135
+ ;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
136
+
137
+ (rule 1 (lower (uadd_overflow x y @ (value_type (fits_in_64 ty))))
138
+ (construct_overflow_op_alu ty (CC.B) (AluRmiROpcode.Add) x y))
139
+
140
+ ;; i128 gets lowered into adc and add
141
+ (rule 0 (lower (uadd_overflow x y @ (value_type $I128)))
142
+ (construct_overflow_op_alu_128 (CC.B) (AluRmiROpcode.Add) (AluRmiROpcode.Adc) x y))
143
+
144
+ ;;;; Rules for `sadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
145
+
146
+ (rule 1 (lower (sadd_overflow x y @ (value_type (fits_in_64 ty))))
147
+ (construct_overflow_op_alu ty (CC.O) (AluRmiROpcode.Add) x y))
148
+
149
+ (rule 0 (lower (sadd_overflow x y @ (value_type $I128)))
150
+ (construct_overflow_op_alu_128 (CC.O) (AluRmiROpcode.Add) (AluRmiROpcode.Adc) x y))
151
+
152
+ ;;;; Rules for `usub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
153
+
154
+ (rule 1 (lower (usub_overflow x y @ (value_type (fits_in_64 ty))))
155
+ (construct_overflow_op_alu ty (CC.B) (AluRmiROpcode.Sub) x y))
156
+
157
+ (rule 0 (lower (usub_overflow x y @ (value_type $I128)))
158
+ (construct_overflow_op_alu_128 (CC.B) (AluRmiROpcode.Sub) (AluRmiROpcode.Sbb) x y))
159
+
160
+ ;;;; Rules for `ssub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
161
+
162
+ (rule 1 (lower (ssub_overflow x y @ (value_type (fits_in_64 ty))))
163
+ (construct_overflow_op_alu ty (CC.O) (AluRmiROpcode.Sub) x y))
164
+
165
+ (rule 0 (lower (ssub_overflow x y @ (value_type $I128)))
166
+ (construct_overflow_op_alu_128 (CC.O) (AluRmiROpcode.Sub) (AluRmiROpcode.Sbb) x y))
167
+
168
+ ;;;; Rules for `umul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
169
+
170
+ (rule 2 (lower (umul_overflow x y @ (value_type (fits_in_64 ty))))
171
+ (construct_overflow_op (CC.O) (x64_umullo_with_flags_paired ty x y)))
172
+
173
+ ;;;; Rules for `smul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
174
+
175
+ (rule 2 (lower (smul_overflow x y @ (value_type (ty_int_ref_16_to_64 ty))))
176
+ (construct_overflow_op_alu ty (CC.O) (AluRmiROpcode.Mul) x y))
177
+
178
+ ;; there is no 8bit imul with an immediate operand so we need to put it in a register or memory
179
+ (rule 1 (lower (smul_overflow x y @ (value_type $I8)))
180
+ (construct_overflow_op (CC.O) (x64_alurmi_with_flags_paired (AluRmiROpcode.Mul) $I8 x (reg_mem_to_reg_mem_imm (put_in_reg_mem y)))))
181
+
182
+ ;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
183
+
184
+ (rule (lower (has_type (multi_lane 8 16)
185
+ (sadd_sat x y)))
186
+ (x64_paddsb x y))
187
+
188
+ (rule (lower (has_type (multi_lane 16 8)
189
+ (sadd_sat x y)))
190
+ (x64_paddsw x y))
191
+
192
+ ;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
193
+
194
+ (rule (lower (has_type (multi_lane 8 16)
195
+ (uadd_sat x y)))
196
+ (x64_paddusb x y))
197
+
198
+ (rule (lower (has_type (multi_lane 16 8)
199
+ (uadd_sat x y)))
200
+ (x64_paddusw x y))
201
+
202
+ ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
203
+
204
+ ;; `i64` and smaller.
205
+
206
+ ;; Sub two registers.
207
+ (rule -3 (lower (has_type (fits_in_64 ty)
208
+ (isub x y)))
209
+ (x64_sub ty x y))
210
+
211
+ ;; SSE.
212
+
213
+ (rule (lower (has_type (multi_lane 8 16)
214
+ (isub x y)))
215
+ (x64_psubb x y))
216
+
217
+ (rule (lower (has_type (multi_lane 16 8)
218
+ (isub x y)))
219
+ (x64_psubw x y))
220
+
221
+ (rule (lower (has_type (multi_lane 32 4)
222
+ (isub x y)))
223
+ (x64_psubd x y))
224
+
225
+ (rule (lower (has_type (multi_lane 64 2)
226
+ (isub x y)))
227
+ (x64_psubq x y))
228
+
229
+ ;; `i128`
230
+ (rule 1 (lower (has_type $I128 (isub x y)))
231
+ ;; Get the high/low registers for `x`.
232
+ (let ((x_regs ValueRegs x)
233
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
234
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
235
+ ;; Get the high/low registers for `y`.
236
+ (let ((y_regs ValueRegs y)
237
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
238
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
239
+ ;; Do a sub followed by an sub-with-borrow.
240
+ (with_flags (x64_sub_with_flags_paired $I64 x_lo y_lo)
241
+ (x64_sbb_paired $I64 x_hi y_hi)))))
242
+
243
+ ;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
244
+
245
+ (rule (lower (has_type (multi_lane 8 16)
246
+ (ssub_sat x y)))
247
+ (x64_psubsb x y))
248
+
249
+ (rule (lower (has_type (multi_lane 16 8)
250
+ (ssub_sat x y)))
251
+ (x64_psubsw x y))
252
+
253
+ ;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
254
+
255
+ (rule (lower (has_type (multi_lane 8 16)
256
+ (usub_sat x y)))
257
+ (x64_psubusb x y))
258
+
259
+ (rule (lower (has_type (multi_lane 16 8)
260
+ (usub_sat x y)))
261
+ (x64_psubusw x y))
262
+
263
+ ;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
264
+
265
+ ;; `{i,b}64` and smaller.
266
+
267
+ ;; And two registers.
268
+ (rule 0 (lower (has_type ty (band x y)))
269
+ (if (ty_int_ref_scalar_64 ty))
270
+ (x64_and ty x y))
271
+
272
+ ;; The above case automatically handles when the rhs is an immediate or a
273
+ ;; sinkable load, but additionally handle the lhs here.
274
+
275
+ (rule 1 (lower (has_type ty (band (sinkable_load x) y)))
276
+ (if (ty_int_ref_scalar_64 ty))
277
+ (x64_and ty y x))
278
+
279
+ (rule 2 (lower (has_type ty (band (simm32_from_value x) y)))
280
+ (if (ty_int_ref_scalar_64 ty))
281
+ (x64_and ty y x))
282
+
283
+ ;; f32 and f64
284
+
285
+ (rule 5 (lower (has_type (ty_scalar_float ty) (band x y)))
286
+ (sse_and ty x y))
287
+
288
+ ;; SSE.
289
+
290
+ (decl sse_and (Type Xmm XmmMem) Xmm)
291
+ (rule (sse_and $F32X4 x y) (x64_andps x y))
292
+ (rule (sse_and $F64X2 x y) (x64_andpd x y))
293
+ (rule (sse_and $F32 x y) (x64_andps x y))
294
+ (rule (sse_and $F64 x y) (x64_andpd x y))
295
+ (rule -1 (sse_and (multi_lane _bits _lanes) x y) (x64_pand x y))
296
+
297
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes)
298
+ (band x y)))
299
+ (sse_and ty x y))
300
+
301
+ ;; `i128`.
302
+
303
+ (rule 7 (lower (has_type $I128 (band x y)))
304
+ (let ((x_regs ValueRegs x)
305
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
306
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
307
+ (y_regs ValueRegs y)
308
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
309
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
310
+ (value_gprs (x64_and $I64 x_lo y_lo)
311
+ (x64_and $I64 x_hi y_hi))))
312
+
313
+ ;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
314
+ ;; by Cranelift's `band_not` instruction that is legalized into the simpler
315
+ ;; forms early on.
316
+
317
+ (decl sse_and_not (Type Xmm XmmMem) Xmm)
318
+ (rule (sse_and_not $F32X4 x y) (x64_andnps x y))
319
+ (rule (sse_and_not $F64X2 x y) (x64_andnpd x y))
320
+ (rule -1 (sse_and_not (multi_lane _bits _lanes) x y) (x64_pandn x y))
321
+
322
+ ;; Note the flipping of operands below as we're match
323
+ ;;
324
+ ;; (band x (bnot y))
325
+ ;;
326
+ ;; while x86 does
327
+ ;;
328
+ ;; pandn(x, y) = and(not(x), y)
329
+ (rule 8 (lower (has_type ty @ (multi_lane _bits _lane) (band x (bnot y))))
330
+ (sse_and_not ty y x))
331
+ (rule 9 (lower (has_type ty @ (multi_lane _bits _lane) (band (bnot y) x)))
332
+ (sse_and_not ty y x))
333
+
334
+ (rule 10 (lower (has_type ty (band x (bnot y))))
335
+ (if (ty_int_ref_scalar_64 ty))
336
+ (if-let $true (use_bmi1))
337
+ ;; the first argument is the one that gets inverted with andn
338
+ (x64_andn ty y x))
339
+ (rule 11 (lower (has_type ty (band (bnot y) x)))
340
+ (if (ty_int_ref_scalar_64 ty))
341
+ (if-let $true (use_bmi1))
342
+ (x64_andn ty y x))
343
+
344
+ ;; Specialization of `blsr` for BMI1
345
+
346
+ (rule 12 (lower (has_type (ty_32_or_64 ty) (band (isub x (iconst (u64_from_imm64 1))) x)))
347
+ (if-let $true (use_bmi1))
348
+ (x64_blsr ty x))
349
+ (rule 13 (lower (has_type (ty_32_or_64 ty) (band x (isub x (iconst (u64_from_imm64 1))))))
350
+ (if-let $true (use_bmi1))
351
+ (x64_blsr ty x))
352
+
353
+ ;; Specialization of `blsi` for BMI1
354
+
355
+ (rule 12 (lower (has_type (ty_32_or_64 ty) (band (ineg x) x)))
356
+ (if-let $true (use_bmi1))
357
+ (x64_blsi ty x))
358
+ (rule 13 (lower (has_type (ty_32_or_64 ty) (band x (ineg x))))
359
+ (if-let $true (use_bmi1))
360
+ (x64_blsi ty x))
361
+
362
+ ;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
363
+
364
+ ;; `{i,b}64` and smaller.
365
+
366
+ ;; Or two registers.
367
+ (rule 0 (lower (has_type ty (bor x y)))
368
+ (if (ty_int_ref_scalar_64 ty))
369
+ (x64_or ty x y))
370
+
371
+ ;; Handle immediates/sinkable loads on the lhs in addition to the automatic
372
+ ;; handling of the rhs above
373
+
374
+ (rule 1 (lower (has_type ty (bor (sinkable_load x) y)))
375
+ (if (ty_int_ref_scalar_64 ty))
376
+ (x64_or ty y x))
377
+
378
+ (rule 2 (lower (has_type ty (bor (simm32_from_value x) y)))
379
+ (if (ty_int_ref_scalar_64 ty))
380
+ (x64_or ty y x))
381
+
382
+ ;; f32 and f64
383
+
384
+ (rule 5 (lower (has_type (ty_scalar_float ty) (bor x y)))
385
+ (sse_or ty x y))
386
+
387
+ ;; SSE.
388
+
389
+ (decl sse_or (Type Xmm XmmMem) Xmm)
390
+ (rule (sse_or $F32X4 x y) (x64_orps x y))
391
+ (rule (sse_or $F64X2 x y) (x64_orpd x y))
392
+ (rule (sse_or $F32 x y) (x64_orps x y))
393
+ (rule (sse_or $F64 x y) (x64_orpd x y))
394
+ (rule -1 (sse_or (multi_lane _bits _lanes) x y) (x64_por x y))
395
+
396
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes)
397
+ (bor x y)))
398
+ (sse_or ty x y))
399
+
400
+ ;; `{i,b}128`.
401
+
402
+ (decl or_i128 (ValueRegs ValueRegs) ValueRegs)
403
+ (rule (or_i128 x y)
404
+ (let ((x_lo Gpr (value_regs_get_gpr x 0))
405
+ (x_hi Gpr (value_regs_get_gpr x 1))
406
+ (y_lo Gpr (value_regs_get_gpr y 0))
407
+ (y_hi Gpr (value_regs_get_gpr y 1)))
408
+ (value_gprs (x64_or $I64 x_lo y_lo)
409
+ (x64_or $I64 x_hi y_hi))))
410
+
411
+ (rule 7 (lower (has_type $I128 (bor x y)))
412
+ (or_i128 x y))
413
+
414
+ ;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
415
+
416
+ ;; `{i,b}64` and smaller.
417
+
418
+ ;; Xor two registers.
419
+ (rule 0 (lower (has_type ty (bxor x y)))
420
+ (if (ty_int_ref_scalar_64 ty))
421
+ (x64_xor ty x y))
422
+
423
+ ;; Handle xor with lhs immediates/sinkable loads in addition to the automatic
424
+ ;; handling of the rhs above.
425
+
426
+ (rule 1 (lower (has_type ty (bxor (sinkable_load x) y)))
427
+ (if (ty_int_ref_scalar_64 ty))
428
+ (x64_xor ty y x))
429
+
430
+ (rule 4 (lower (has_type ty (bxor (simm32_from_value x) y)))
431
+ (if (ty_int_ref_scalar_64 ty))
432
+ (x64_xor ty y x))
433
+
434
+ ;; f32 and f64
435
+
436
+ (rule 5 (lower (has_type (ty_scalar_float ty) (bxor x y)))
437
+ (x64_xor_vector ty x y))
438
+
439
+ ;; SSE.
440
+
441
+ (rule 6 (lower (has_type ty @ (multi_lane _bits _lanes) (bxor x y)))
442
+ (x64_xor_vector ty x y))
443
+
444
+ ;; `{i,b}128`.
445
+
446
+ (rule 7 (lower (has_type $I128 (bxor x y)))
447
+ (let ((x_regs ValueRegs x)
448
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
449
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
450
+ (y_regs ValueRegs y)
451
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
452
+ (y_hi Gpr (value_regs_get_gpr y_regs 1)))
453
+ (value_gprs (x64_xor $I64 x_lo y_lo)
454
+ (x64_xor $I64 x_hi y_hi))))
455
+
456
+ ;; Specialization of `blsmsk` for BMI1
457
+
458
+ (rule 8 (lower (has_type (ty_32_or_64 ty) (bxor (isub x (iconst (u64_from_imm64 1))) x)))
459
+ (if-let $true (use_bmi1))
460
+ (x64_blsmsk ty x))
461
+ (rule 9 (lower (has_type (ty_32_or_64 ty) (bxor x (isub x (iconst (u64_from_imm64 1))))))
462
+ (if-let $true (use_bmi1))
463
+ (x64_blsmsk ty x))
464
+
465
+ ;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
466
+
467
+ ;; `i64` and smaller.
468
+
469
+ (rule -1 (lower (has_type (fits_in_64 ty) (ishl src amt)))
470
+ (x64_shl ty src (put_masked_in_imm8_gpr amt ty)))
471
+
472
+ ;; `i128`.
473
+
474
+ (decl shl_i128 (ValueRegs Gpr) ValueRegs)
475
+ (rule (shl_i128 src amt)
476
+ ;; Unpack the registers that make up the 128-bit value being shifted.
477
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
478
+ (src_hi Gpr (value_regs_get_gpr src 1))
479
+ ;; Do two 64-bit shifts.
480
+ (lo_shifted Gpr (x64_shl $I64 src_lo amt))
481
+ (hi_shifted Gpr (x64_shl $I64 src_hi amt))
482
+ ;; `src_lo >> (64 - amt)` are the bits to carry over from the lo
483
+ ;; into the hi.
484
+ (carry Gpr (x64_shr $I64
485
+ src_lo
486
+ (x64_sub $I64
487
+ (imm $I64 64)
488
+ amt)))
489
+ (zero Gpr (imm $I64 0))
490
+ ;; Nullify the carry if we are shifting in by a multiple of 128.
491
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64)
492
+ (RegMemImm.Imm 127)
493
+ amt)
494
+ (cmove $I64
495
+ (CC.Z)
496
+ zero
497
+ carry)))
498
+ ;; Add the carry into the high half.
499
+ (hi_shifted_ Gpr (x64_or $I64 carry_ hi_shifted)))
500
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
501
+ ;; (modulo 128), then the low bits are zero and the high bits are our
502
+ ;; low bits.
503
+ (with_flags (x64_test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
504
+ (consumes_flags_concat
505
+ (cmove $I64 (CC.Z) lo_shifted zero)
506
+ (cmove $I64 (CC.Z) hi_shifted_ lo_shifted)))))
507
+
508
+ (rule (lower (has_type $I128 (ishl src amt)))
509
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
510
+ ;; amount to the value's bit width.
511
+ (let ((amt_ Gpr (lo_gpr amt)))
512
+ (shl_i128 src amt_)))
513
+
514
+ ;; SSE.
515
+
516
+ ;; Since the x86 instruction set does not have any 8x16 shift instructions (even
517
+ ;; in higher feature sets like AVX), we lower the `ishl.i8x16` to a sequence of
518
+ ;; instructions. The basic idea, whether the amount to shift by is an immediate
519
+ ;; or not, is to use a 16x8 shift and then mask off the incorrect bits to 0s.
520
+ (rule (lower (has_type ty @ $I8X16 (ishl src amt)))
521
+ (let (
522
+ ;; Mask the amount to ensure wrapping behaviour
523
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
524
+ ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
525
+ ;; correct for half of the lanes; the others must be fixed up with
526
+ ;; the mask below.
527
+ (unmasked Xmm (x64_psllw src (mov_rmi_to_xmm masked_amt)))
528
+ (mask_addr SyntheticAmode (ishl_i8x16_mask masked_amt))
529
+ (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
530
+ (sse_and $I8X16 unmasked (RegMem.Reg mask))))
531
+
532
+ ;; Get the address of the mask to use when fixing up the lanes that weren't
533
+ ;; correctly generated by the 16x8 shift.
534
+ (decl ishl_i8x16_mask (RegMemImm) SyntheticAmode)
535
+
536
+ ;; When the shift amount is known, we can statically (i.e. at compile time)
537
+ ;; determine the mask to use and only emit that.
538
+ (decl ishl_i8x16_mask_for_const (u32) SyntheticAmode)
539
+ (extern constructor ishl_i8x16_mask_for_const ishl_i8x16_mask_for_const)
540
+ (rule (ishl_i8x16_mask (RegMemImm.Imm amt))
541
+ (ishl_i8x16_mask_for_const amt))
542
+
543
+ ;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
544
+ ;; time) find the correct mask offset in the table. We use `lea` to find the
545
+ ;; base address of the mask table and then complex addressing to offset to the
546
+ ;; right mask: `base_address + amt << 4`
547
+ (decl ishl_i8x16_mask_table () SyntheticAmode)
548
+ (extern constructor ishl_i8x16_mask_table ishl_i8x16_mask_table)
549
+ (rule (ishl_i8x16_mask (RegMemImm.Reg amt))
550
+ (let ((mask_table SyntheticAmode (ishl_i8x16_mask_table))
551
+ (base_mask_addr Gpr (x64_lea $I64 mask_table))
552
+ (mask_offset Gpr (x64_shl $I64 amt
553
+ (imm8_to_imm8_gpr 4))))
554
+ (Amode.ImmRegRegShift 0
555
+ base_mask_addr
556
+ mask_offset
557
+ 0
558
+ (mem_flags_trusted))))
559
+
560
+ (rule (ishl_i8x16_mask (RegMemImm.Mem amt))
561
+ (ishl_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
562
+
563
+ ;; 16x8, 32x4, and 64x2 shifts can each use a single instruction, once the shift amount is masked.
564
+
565
+ (rule (lower (has_type ty @ $I16X8 (ishl src amt)))
566
+ (x64_psllw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
567
+
568
+ (rule (lower (has_type ty @ $I32X4 (ishl src amt)))
569
+ (x64_pslld src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
570
+
571
+ (rule (lower (has_type ty @ $I64X2 (ishl src amt)))
572
+ (x64_psllq src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
573
+
574
+ ;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
575
+
576
+ ;; `i64` and smaller.
577
+
578
+ (rule -1 (lower (has_type (fits_in_64 ty) (ushr src amt)))
579
+ (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Zero))))
580
+ (x64_shr ty src_ (put_masked_in_imm8_gpr amt ty))))
581
+
582
+ ;; `i128`.
583
+
584
+ (decl shr_i128 (ValueRegs Gpr) ValueRegs)
585
+ (rule (shr_i128 src amt)
586
+ ;; Unpack the lo/hi halves of `src`.
587
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
588
+ (src_hi Gpr (value_regs_get_gpr src 1))
589
+ ;; Do a shift on each half.
590
+ (lo_shifted Gpr (x64_shr $I64 src_lo amt))
591
+ (hi_shifted Gpr (x64_shr $I64 src_hi amt))
592
+ ;; `src_hi << (64 - amt)` are the bits to carry over from the hi
593
+ ;; into the lo.
594
+ (carry Gpr (x64_shl $I64
595
+ src_hi
596
+ (x64_sub $I64
597
+ (imm $I64 64)
598
+ amt)))
599
+ ;; Share the zero value to reduce register pressure
600
+ (zero Gpr (imm $I64 0))
601
+
602
+ ;; Nullify the carry if we are shifting by a multiple of 128.
603
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64) (RegMemImm.Imm 127) amt)
604
+ (cmove $I64 (CC.Z) zero carry)))
605
+ ;; Add the carry bits into the lo.
606
+ (lo_shifted_ Gpr (x64_or $I64 carry_ lo_shifted)))
607
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
608
+ ;; (modulo 128), then the hi bits are zero and the lo bits are what
609
+ ;; would otherwise be our hi bits.
610
+ (with_flags (x64_test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
611
+ (consumes_flags_concat
612
+ (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
613
+ (cmove $I64 (CC.Z) hi_shifted zero)))))
614
+
615
+ (rule (lower (has_type $I128 (ushr src amt)))
616
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
617
+ ;; amount to the value's bit width.
618
+ (let ((amt_ Gpr (lo_gpr amt)))
619
+ (shr_i128 src amt_)))
620
+
621
+ ;; SSE.
622
+
623
+ ;; There are no 8x16 shifts in x64. Do the same 16x8-shift-and-mask thing we do
624
+ ;; with 8x16 `ishl`.
625
+ (rule (lower (has_type ty @ $I8X16 (ushr src amt)))
626
+ (let (
627
+ ;; Mask the amount to ensure wrapping behaviour
628
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
629
+ ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
630
+ ;; correct for half of the lanes; the others must be fixed up with
631
+ ;; the mask below.
632
+ (unmasked Xmm (x64_psrlw src (mov_rmi_to_xmm masked_amt))))
633
+ (sse_and $I8X16
634
+ unmasked
635
+ (ushr_i8x16_mask masked_amt))))
636
+
637
+ ;; Get the address of the mask to use when fixing up the lanes that weren't
638
+ ;; correctly generated by the 16x8 shift.
639
+ (decl ushr_i8x16_mask (RegMemImm) SyntheticAmode)
640
+
641
+ ;; When the shift amount is known, we can statically (i.e. at compile time)
642
+ ;; determine the mask to use and only emit that.
643
+ (decl ushr_i8x16_mask_for_const (u32) SyntheticAmode)
644
+ (extern constructor ushr_i8x16_mask_for_const ushr_i8x16_mask_for_const)
645
+ (rule (ushr_i8x16_mask (RegMemImm.Imm amt))
646
+ (ushr_i8x16_mask_for_const amt))
647
+
648
+ ;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
649
+ ;; time) find the correct mask offset in the table. We use `lea` to find the
650
+ ;; base address of the mask table and then complex addressing to offset to the
651
+ ;; right mask: `base_address + amt << 4`
652
+ (decl ushr_i8x16_mask_table () SyntheticAmode)
653
+ (extern constructor ushr_i8x16_mask_table ushr_i8x16_mask_table)
654
+ (rule (ushr_i8x16_mask (RegMemImm.Reg amt))
655
+ (let ((mask_table SyntheticAmode (ushr_i8x16_mask_table))
656
+ (base_mask_addr Gpr (x64_lea $I64 mask_table))
657
+ (mask_offset Gpr (x64_shl $I64
658
+ amt
659
+ (imm8_to_imm8_gpr 4))))
660
+ (Amode.ImmRegRegShift 0
661
+ base_mask_addr
662
+ mask_offset
663
+ 0
664
+ (mem_flags_trusted))))
665
+
666
+ (rule (ushr_i8x16_mask (RegMemImm.Mem amt))
667
+ (ushr_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
668
+
669
+ ;; 16x8, 32x4, and 64x2 shifts can each use a single instruction, once the shift amount is masked.
670
+
671
+ (rule (lower (has_type ty @ $I16X8 (ushr src amt)))
672
+ (x64_psrlw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
673
+
674
+ (rule (lower (has_type ty @ $I32X4 (ushr src amt)))
675
+ (x64_psrld src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
676
+
677
+ (rule (lower (has_type ty @ $I64X2 (ushr src amt)))
678
+ (x64_psrlq src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
679
+
680
+ (decl mask_xmm_shift (Type Value) RegMemImm)
681
+ (rule (mask_xmm_shift ty amt)
682
+ (gpr_to_reg (x64_and $I64 amt (RegMemImm.Imm (shift_mask ty)))))
683
+ (rule 1 (mask_xmm_shift ty (iconst n))
684
+ (RegMemImm.Imm (shift_amount_masked ty n)))
685
+
686
+ ;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
687
+
688
+ ;; `i64` and smaller.
689
+
690
+ (rule -1 (lower (has_type (fits_in_64 ty) (sshr src amt)))
691
+ (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Sign))))
692
+ (x64_sar ty src_ (put_masked_in_imm8_gpr amt ty))))
693
+
694
+ ;; `i128`.
695
+
696
+ (decl sar_i128 (ValueRegs Gpr) ValueRegs)
697
+ (rule (sar_i128 src amt)
698
+ ;; Unpack the low/high halves of `src`.
699
+ (let ((src_lo Gpr (value_regs_get_gpr src 0))
700
+ (src_hi Gpr (value_regs_get_gpr src 1))
701
+ ;; Do a shift of each half. NB: the low half uses an unsigned shift
702
+ ;; because its MSB is not a sign bit.
703
+ (lo_shifted Gpr (x64_shr $I64 src_lo amt))
704
+ (hi_shifted Gpr (x64_sar $I64 src_hi amt))
705
+ ;; `src_hi << (64 - amt)` are the bits to carry over from the low
706
+ ;; half to the high half.
707
+ (carry Gpr (x64_shl $I64
708
+ src_hi
709
+ (x64_sub $I64
710
+ (imm $I64 64)
711
+ amt)))
712
+ ;; Nullify the carry if we are shifting by a multiple of 128.
713
+ (carry_ Gpr (with_flags_reg (x64_test (OperandSize.Size64) (RegMemImm.Imm 127) amt)
714
+ (cmove $I64 (CC.Z) (imm $I64 0) carry)))
715
+ ;; Add the carry into the low half.
716
+ (lo_shifted_ Gpr (x64_or $I64 lo_shifted carry_))
717
+ ;; Get all sign bits.
718
+ (sign_bits Gpr (x64_sar $I64 src_hi (imm8_to_imm8_gpr 63))))
719
+ ;; Combine the two shifted halves. However, if we are shifting by >= 64
720
+ ;; (modulo 128), then the hi bits are all sign bits and the lo bits are
721
+ ;; what would otherwise be our hi bits.
722
+ (with_flags (x64_test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
723
+ (consumes_flags_concat
724
+ (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
725
+ (cmove $I64 (CC.Z) hi_shifted sign_bits)))))
726
+
727
+ (rule (lower (has_type $I128 (sshr src amt)))
728
+ ;; NB: Only the low bits of `amt` matter since we logically mask the shift
729
+ ;; amount to the value's bit width.
730
+ (let ((amt_ Gpr (lo_gpr amt)))
731
+ (sar_i128 src amt_)))
732
+
733
+ ;; SSE.
734
+
735
+ ;; Since the x86 instruction set does not have an 8x16 shift instruction and the
736
+ ;; approach used for `ishl` and `ushr` cannot be easily used (the masks do not
737
+ ;; preserve the sign), we use a different approach here: separate the low and
738
+ ;; high lanes, shift them separately, and merge them into the final result.
739
+ ;;
740
+ ;; Visually, this looks like the following, where `src.i8x16 = [s0, s1, ...,
741
+ ;; s15]:
742
+ ;;
743
+ ;; lo.i16x8 = [(s0, s0), (s1, s1), ..., (s7, s7)]
744
+ ;; shifted_lo.i16x8 = shift each lane of `low`
745
+ ;; hi.i16x8 = [(s8, s8), (s9, s9), ..., (s15, s15)]
746
+ ;; shifted_hi.i16x8 = shift each lane of `high`
747
+ ;; result = [s0'', s1'', ..., s15'']
748
+ (rule (lower (has_type ty @ $I8X16 (sshr src amt @ (value_type amt_ty))))
749
+ (let ((src_ Xmm (put_in_xmm src))
750
+ ;; Mask the amount to ensure wrapping behaviour
751
+ (masked_amt RegMemImm (mask_xmm_shift ty amt))
752
+ ;; In order for `packsswb` later to only use the high byte of each
753
+ ;; 16x8 lane, we shift right an extra 8 bits, relying on `psraw` to
754
+ ;; fill in the upper bits appropriately.
755
+ (lo Xmm (x64_punpcklbw src_ src_))
756
+ (hi Xmm (x64_punpckhbw src_ src_))
757
+ (amt_ XmmMemImm (sshr_i8x16_bigger_shift amt_ty masked_amt))
758
+ (shifted_lo Xmm (x64_psraw lo amt_))
759
+ (shifted_hi Xmm (x64_psraw hi amt_)))
760
+ (x64_packsswb shifted_lo shifted_hi)))
761
+
762
+ (decl sshr_i8x16_bigger_shift (Type RegMemImm) XmmMemImm)
763
+ (rule (sshr_i8x16_bigger_shift _ty (RegMemImm.Imm i))
764
+ (xmm_mem_imm_new (RegMemImm.Imm (u32_add i 8))))
765
+ (rule (sshr_i8x16_bigger_shift ty (RegMemImm.Reg r))
766
+ (mov_rmi_to_xmm (RegMemImm.Reg (x64_add ty
767
+ r
768
+ (RegMemImm.Imm 8)))))
769
+ (rule (sshr_i8x16_bigger_shift ty rmi @ (RegMemImm.Mem _m))
770
+ (mov_rmi_to_xmm (RegMemImm.Reg (x64_add ty
771
+ (imm ty 8)
772
+ rmi))))
773
+
774
+ ;; `sshr.{i16x8,i32x4}` can be a simple `psra{w,d}`, we just have to make sure
775
+ ;; that if the shift amount is in a register, it is in an XMM register.
776
+
777
+ (rule (lower (has_type ty @ $I16X8 (sshr src amt)))
778
+ (x64_psraw src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
779
+
780
+ (rule (lower (has_type ty @ $I32X4 (sshr src amt)))
781
+ (x64_psrad src (mov_rmi_to_xmm (mask_xmm_shift ty amt))))
782
+
783
+ ;; The `sshr.i64x2` CLIF instruction has no single x86 instruction in the older
784
+ ;; feature sets. To remedy this, a small dance is done with an unsigned right
785
+ ;; shift plus some extra ops.
786
+ (rule 3 (lower (has_type ty @ $I64X2 (sshr src (iconst n))))
787
+ (if-let $true (use_avx512vl_simd))
788
+ (if-let $true (use_avx512f_simd))
789
+ (x64_vpsraq_imm src (shift_amount_masked ty n)))
790
+
791
+ (rule 2 (lower (has_type ty @ $I64X2 (sshr src amt)))
792
+ (if-let $true (use_avx512vl_simd))
793
+ (if-let $true (use_avx512f_simd))
794
+ (let ((masked Gpr (x64_and $I64 amt (RegMemImm.Imm (shift_mask ty)))))
795
+ (x64_vpsraq src (x64_movd_to_xmm masked))))
796
+
797
+ (rule 1 (lower (has_type $I64X2 (sshr src (iconst (u64_from_imm64 (u64_as_u32 amt))))))
798
+ (lower_i64x2_sshr_imm src (u32_and amt 63)))
799
+
800
+ (rule (lower (has_type $I64X2 (sshr src amt)))
801
+ (lower_i64x2_sshr_gpr src (x64_and $I64 amt (RegMemImm.Imm 63))))
802
+
803
+ (decl lower_i64x2_sshr_imm (Xmm u32) Xmm)
804
+
805
+ ;; If the shift amount is less than 32 then do an sshr with 32-bit lanes to
806
+ ;; produce the upper halves of each result, followed by a ushr of 64-bit lanes
807
+ ;; to produce the lower halves of each result. Interleave results at the end.
808
+ (rule 2 (lower_i64x2_sshr_imm vec imm)
809
+ (if-let $true (u64_lt imm 32))
810
+ (let (
811
+ (high32 Xmm (x64_psrad vec (xmi_imm imm)))
812
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
813
+ (low32 Xmm (x64_psrlq vec (xmi_imm imm)))
814
+ (low32 Xmm (x64_pshufd low32 0b11_10_10_00))
815
+ )
816
+ (x64_punpckldq low32 high32)))
817
+
818
+ ;; If the shift amount is 32 then the `psrlq` from the above rule can be avoided
819
+ (rule 1 (lower_i64x2_sshr_imm vec 32)
820
+ (let (
821
+ (low32 Xmm (x64_pshufd vec 0b11_10_11_01))
822
+ (high32 Xmm (x64_psrad vec (xmi_imm 31)))
823
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
824
+ )
825
+ (x64_punpckldq low32 high32)))
826
+
827
+ ;; Shifts >= 32 use one `psrad` to generate the upper bits and second `psrad` to
828
+ ;; generate the lower bits. Everything is then woven back together with
829
+ ;; shuffles.
830
+ (rule (lower_i64x2_sshr_imm vec imm)
831
+ (if-let $true (u64_lt 32 imm))
832
+ (let (
833
+ (high32 Xmm (x64_psrad vec (xmi_imm 31)))
834
+ (high32 Xmm (x64_pshufd high32 0b11_10_11_01))
835
+ (low32 Xmm (x64_psrad vec (xmi_imm (u32_sub imm 32))))
836
+ (low32 Xmm (x64_pshufd low32 0b11_10_10_01))
837
+ )
838
+ (x64_punpckldq low32 high32)))
839
+
840
+ ;; A variable shift amount is slightly more complicated than the immediate
841
+ ;; shift amounts from above. The `Gpr` argument is guaranteed to be <= 63 by
842
+ ;; earlier masking. A `ushr` operation is used with some xor/sub math to
843
+ ;; generate the sign bits.
844
+ (decl lower_i64x2_sshr_gpr (Xmm Gpr) Xmm)
845
+ (rule (lower_i64x2_sshr_gpr vec val)
846
+ (let (
847
+ (val Xmm (x64_movq_to_xmm val))
848
+ (mask Xmm (flip_high_bit_mask $I64X2))
849
+ (sign_bit_loc Xmm (x64_psrlq mask val))
850
+ (ushr Xmm (x64_psrlq vec val))
851
+ (ushr_sign_bit_flip Xmm (x64_pxor sign_bit_loc ushr))
852
+ )
853
+ (x64_psubq ushr_sign_bit_flip sign_bit_loc)))
854
+
855
+ ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
856
+
857
+ ;; `i64` and smaller: we can rely on x86's rotate-amount masking since
858
+ ;; we operate on the whole register. For const's we mask the constant.
859
+
860
+ (rule -1 (lower (has_type (fits_in_64 ty) (rotl src amt)))
861
+ (x64_rotl ty src (put_masked_in_imm8_gpr amt ty)))
862
+
863
+
864
+ ;; `i128`.
865
+
866
+ (rule (lower (has_type $I128 (rotl src amt)))
867
+ (let ((src_ ValueRegs src)
868
+ ;; NB: Only the low bits of `amt` matter since we logically mask the
869
+ ;; rotation amount to the value's bit width.
870
+ (amt_ Gpr (lo_gpr amt)))
871
+ (or_i128 (shl_i128 src_ amt_)
872
+ (shr_i128 src_ (x64_sub $I64
873
+ (imm $I64 128)
874
+ amt_)))))
875
+
876
+ ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
877
+
878
+ ;; `i64` and smaller: we can rely on x86's rotate-amount masking since
879
+ ;; we operate on the whole register. For const's we mask the constant.
880
+
881
+ (rule -1 (lower (has_type (fits_in_64 ty) (rotr src amt)))
882
+ (x64_rotr ty src (put_masked_in_imm8_gpr amt ty)))
883
+
884
+
885
+ ;; `i128`.
886
+
887
+ (rule (lower (has_type $I128 (rotr src amt)))
888
+ (let ((src_ ValueRegs src)
889
+ ;; NB: Only the low bits of `amt` matter since we logically mask the
890
+ ;; rotation amount to the value's bit width.
891
+ (amt_ Gpr (lo_gpr amt)))
892
+ (or_i128 (shr_i128 src_ amt_)
893
+ (shl_i128 src_ (x64_sub $I64
894
+ (imm $I64 128)
895
+ amt_)))))
896
+
897
+ ;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
898
+
899
+ ;; `i64` and smaller.
900
+
901
+ (rule -1 (lower (has_type (fits_in_64 ty) (ineg x)))
902
+ (x64_neg ty x))
903
+
904
+ (rule -2 (lower (has_type $I128 (ineg x)))
905
+ ;; Get the high/low registers for `x`.
906
+ (let ((regs ValueRegs x)
907
+ (lo Gpr (value_regs_get_gpr regs 0))
908
+ (hi Gpr (value_regs_get_gpr regs 1)))
909
+ ;; Do a neg followed by an sub-with-borrow.
910
+ (with_flags (x64_neg_paired $I64 lo)
911
+ (x64_sbb_paired $I64 (imm $I64 0) hi))))
912
+
913
+ ;; SSE.
914
+
915
+ (rule (lower (has_type $I8X16 (ineg x)))
916
+ (x64_psubb (imm $I8X16 0) x))
917
+
918
+ (rule (lower (has_type $I16X8 (ineg x)))
919
+ (x64_psubw (imm $I16X8 0) x))
920
+
921
+ (rule (lower (has_type $I32X4 (ineg x)))
922
+ (x64_psubd (imm $I32X4 0) x))
923
+
924
+ (rule (lower (has_type $I64X2 (ineg x)))
925
+ (x64_psubq (imm $I64X2 0) x))
926
+
927
+ ;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
928
+
929
+ (rule (lower (has_type (multi_lane 8 16)
930
+ (avg_round x y)))
931
+ (x64_pavgb x y))
932
+
933
+ (rule (lower (has_type (multi_lane 16 8)
934
+ (avg_round x y)))
935
+ (x64_pavgw x y))
936
+
937
+ ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
938
+
939
+ ;; `i64` and smaller.
940
+
941
+ ;; Multiply two registers.
942
+ (rule -5 (lower (has_type (fits_in_64 ty) (imul x y)))
943
+ (x64_mul ty x y))
944
+
945
+ ;; Handle multiplication where the lhs is an immediate or sinkable load in
946
+ ;; addition to the automatic rhs handling above.
947
+
948
+ (rule -4 (lower (has_type (fits_in_64 ty)
949
+ (imul (simm32_from_value x) y)))
950
+ (x64_mul ty y x))
951
+ (rule -3 (lower (has_type (fits_in_64 ty)
952
+ (imul (sinkable_load x) y)))
953
+ (x64_mul ty y x))
954
+
955
+ ;; `i128`.
956
+
957
+ ;; mul:
958
+ ;; dst_lo = lhs_lo * rhs_lo
959
+ ;; dst_hi = umulhi(lhs_lo, rhs_lo) +
960
+ ;; lhs_lo * rhs_hi +
961
+ ;; lhs_hi * rhs_lo
962
+ ;;
963
+ ;; so we emit:
964
+ ;; lo_hi = mul x_lo, y_hi
965
+ ;; hi_lo = mul x_hi, y_lo
966
+ ;; hilo_hilo = add lo_hi, hi_lo
967
+ ;; dst_lo:hi_lolo = mulhi_u x_lo, y_lo
968
+ ;; dst_hi = add hilo_hilo, hi_lolo
969
+ ;; return (dst_lo, dst_hi)
970
+ (rule 2 (lower (has_type $I128 (imul x y)))
971
+ ;; Put `x` into registers and unpack its hi/lo halves.
972
+ (let ((x_regs ValueRegs x)
973
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
974
+ (x_hi Gpr (value_regs_get_gpr x_regs 1))
975
+ ;; Put `y` into registers and unpack its hi/lo halves.
976
+ (y_regs ValueRegs y)
977
+ (y_lo Gpr (value_regs_get_gpr y_regs 0))
978
+ (y_hi Gpr (value_regs_get_gpr y_regs 1))
979
+ ;; lo_hi = mul x_lo, y_hi
980
+ (lo_hi Gpr (x64_mul $I64 x_lo y_hi))
981
+ ;; hi_lo = mul x_hi, y_lo
982
+ (hi_lo Gpr (x64_mul $I64 x_hi y_lo))
983
+ ;; hilo_hilo = add lo_hi, hi_lo
984
+ (hilo_hilo Gpr (x64_add $I64 lo_hi hi_lo))
985
+ ;; dst_lo:hi_lolo = mulhi_u x_lo, y_lo
986
+ (mul_regs ValueRegs (mulhi_u $I64 x_lo y_lo))
987
+ (dst_lo Gpr (value_regs_get_gpr mul_regs 0))
988
+ (hi_lolo Gpr (value_regs_get_gpr mul_regs 1))
989
+ ;; dst_hi = add hilo_hilo, hi_lolo
990
+ (dst_hi Gpr (x64_add $I64 hilo_hilo hi_lolo)))
991
+ (value_gprs dst_lo dst_hi)))
992
+
993
+ ;; SSE.
994
+
995
+ ;; (No i8x16 multiply.)
996
+
997
+ (rule (lower (has_type (multi_lane 16 8) (imul x y)))
998
+ (x64_pmullw x y))
999
+
1000
+ (rule (lower (has_type (multi_lane 32 4) (imul x y)))
1001
+ (if-let $true (use_sse41))
1002
+ (x64_pmulld x y))
1003
+
1004
+ ;; Without `pmulld` the `pmuludq` instruction is used instead which performs
1005
+ ;; 32-bit multiplication storing the 64-bit result. The 64-bit result is
1006
+ ;; truncated to 32-bits and everything else is woven into place.
1007
+ (rule -1 (lower (has_type (multi_lane 32 4) (imul x y)))
1008
+ (let (
1009
+ (x Xmm x)
1010
+ (y Xmm y)
1011
+ (x_hi Xmm (x64_pshufd x 0b00_11_00_01))
1012
+ (y_hi Xmm (x64_pshufd y 0b00_11_00_01))
1013
+ (mul_lo Xmm (x64_pshufd (x64_pmuludq x y) 0b00_00_10_00))
1014
+ (mul_hi Xmm (x64_pshufd (x64_pmuludq x_hi y_hi) 0b00_00_10_00))
1015
+ )
1016
+ (x64_punpckldq mul_lo mul_hi)))
1017
+
1018
+ ;; With AVX-512 we can implement `i64x2` multiplication with a single
1019
+ ;; instruction.
1020
+ (rule 3 (lower (has_type (multi_lane 64 2) (imul x y)))
1021
+ (if-let $true (use_avx512vl_simd))
1022
+ (if-let $true (use_avx512dq_simd))
1023
+ (x64_vpmullq x y))
1024
+
1025
+ ;; Otherwise, for i64x2 multiplication we describe a lane A as being composed of
1026
+ ;; a 32-bit upper half "Ah" and a 32-bit lower half "Al". The 32-bit long hand
1027
+ ;; multiplication can then be written as:
1028
+ ;;
1029
+ ;; Ah Al
1030
+ ;; * Bh Bl
1031
+ ;; -----
1032
+ ;; Al * Bl
1033
+ ;; + (Ah * Bl) << 32
1034
+ ;; + (Al * Bh) << 32
1035
+ ;;
1036
+ ;; So for each lane we will compute:
1037
+ ;;
1038
+ ;; A * B = (Al * Bl) + ((Ah * Bl) + (Al * Bh)) << 32
1039
+ ;;
1040
+ ;; Note, the algorithm will use `pmuludq` which operates directly on the lower
1041
+ ;; 32-bit (`Al` or `Bl`) of a lane and writes the result to the full 64-bits of
1042
+ ;; the lane of the destination. For this reason we don't need shifts to isolate
1043
+ ;; the lower 32-bits, however, we will need to use shifts to isolate the high
1044
+ ;; 32-bits when doing calculations, i.e., `Ah == A >> 32`.
1045
+ (rule (lower (has_type (multi_lane 64 2)
1046
+ (imul a b)))
1047
+ (let ((a0 Xmm a)
1048
+ (b0 Xmm b)
1049
+ ;; a_hi = A >> 32
1050
+ (a_hi Xmm (x64_psrlq a0 (xmi_imm 32)))
1051
+ ;; ah_bl = Ah * Bl
1052
+ (ah_bl Xmm (x64_pmuludq a_hi b0))
1053
+ ;; b_hi = B >> 32
1054
+ (b_hi Xmm (x64_psrlq b0 (xmi_imm 32)))
1055
+ ;; al_bh = Al * Bh
1056
+ (al_bh Xmm (x64_pmuludq a0 b_hi))
1057
+ ;; aa_bb = ah_bl + al_bh
1058
+ (aa_bb Xmm (x64_paddq ah_bl al_bh))
1059
+ ;; aa_bb_shifted = aa_bb << 32
1060
+ (aa_bb_shifted Xmm (x64_psllq aa_bb (xmi_imm 32)))
1061
+ ;; al_bl = Al * Bl
1062
+ (al_bl Xmm (x64_pmuludq a0 b0)))
1063
+ ;; al_bl + aa_bb_shifted
1064
+ (x64_paddq al_bl aa_bb_shifted)))
1065
+
1066
+ ;; Special case for `i32x4.extmul_high_i16x8_s`.
1067
+ (rule 1 (lower (has_type (multi_lane 32 4)
1068
+ (imul (swiden_high (and (value_type (multi_lane 16 8))
1069
+ x))
1070
+ (swiden_high (and (value_type (multi_lane 16 8))
1071
+ y)))))
1072
+ (let ((x2 Xmm x)
1073
+ (y2 Xmm y)
1074
+ (lo Xmm (x64_pmullw x2 y2))
1075
+ (hi Xmm (x64_pmulhw x2 y2)))
1076
+ (x64_punpckhwd lo hi)))
1077
+
1078
+ ;; Special case for `i64x2.extmul_high_i32x4_s`.
1079
+ (rule 1 (lower (has_type (multi_lane 64 2)
1080
+ (imul (swiden_high (and (value_type (multi_lane 32 4))
1081
+ x))
1082
+ (swiden_high (and (value_type (multi_lane 32 4))
1083
+ y)))))
1084
+ (if-let $true (use_sse41))
1085
+ (let ((x2 Xmm (x64_pshufd x 0xFA))
1086
+ (y2 Xmm (x64_pshufd y 0xFA)))
1087
+ (x64_pmuldq x2 y2)))
1088
+
1089
+ ;; Special case for `i32x4.extmul_low_i16x8_s`.
1090
+ (rule 1 (lower (has_type (multi_lane 32 4)
1091
+ (imul (swiden_low (and (value_type (multi_lane 16 8))
1092
+ x))
1093
+ (swiden_low (and (value_type (multi_lane 16 8))
1094
+ y)))))
1095
+ (let ((x2 Xmm x)
1096
+ (y2 Xmm y)
1097
+ (lo Xmm (x64_pmullw x2 y2))
1098
+ (hi Xmm (x64_pmulhw x2 y2)))
1099
+ (x64_punpcklwd lo hi)))
1100
+
1101
+ ;; Special case for `i64x2.extmul_low_i32x4_s`.
1102
+ (rule 1 (lower (has_type (multi_lane 64 2)
1103
+ (imul (swiden_low (and (value_type (multi_lane 32 4))
1104
+ x))
1105
+ (swiden_low (and (value_type (multi_lane 32 4))
1106
+ y)))))
1107
+ (if-let $true (use_sse41))
1108
+ (let ((x2 Xmm (x64_pshufd x 0x50))
1109
+ (y2 Xmm (x64_pshufd y 0x50)))
1110
+ (x64_pmuldq x2 y2)))
1111
+
1112
+ ;; Special case for `i32x4.extmul_high_i16x8_u`.
1113
+ (rule 1 (lower (has_type (multi_lane 32 4)
1114
+ (imul (uwiden_high (and (value_type (multi_lane 16 8))
1115
+ x))
1116
+ (uwiden_high (and (value_type (multi_lane 16 8))
1117
+ y)))))
1118
+ (let ((x2 Xmm x)
1119
+ (y2 Xmm y)
1120
+ (lo Xmm (x64_pmullw x2 y2))
1121
+ (hi Xmm (x64_pmulhuw x2 y2)))
1122
+ (x64_punpckhwd lo hi)))
1123
+
1124
+ ;; Special case for `i64x2.extmul_high_i32x4_u`.
1125
+ (rule 1 (lower (has_type (multi_lane 64 2)
1126
+ (imul (uwiden_high (and (value_type (multi_lane 32 4))
1127
+ x))
1128
+ (uwiden_high (and (value_type (multi_lane 32 4))
1129
+ y)))))
1130
+ (let ((x2 Xmm (x64_pshufd x 0xFA))
1131
+ (y2 Xmm (x64_pshufd y 0xFA)))
1132
+ (x64_pmuludq x2 y2)))
1133
+
1134
+ ;; Special case for `i32x4.extmul_low_i16x8_u`.
1135
+ (rule 1 (lower (has_type (multi_lane 32 4)
1136
+ (imul (uwiden_low (and (value_type (multi_lane 16 8))
1137
+ x))
1138
+ (uwiden_low (and (value_type (multi_lane 16 8))
1139
+ y)))))
1140
+ (let ((x2 Xmm x)
1141
+ (y2 Xmm y)
1142
+ (lo Xmm (x64_pmullw x2 y2))
1143
+ (hi Xmm (x64_pmulhuw x2 y2)))
1144
+ (x64_punpcklwd lo hi)))
1145
+
1146
+ ;; Special case for `i64x2.extmul_low_i32x4_u`.
1147
+ (rule 1 (lower (has_type (multi_lane 64 2)
1148
+ (imul (uwiden_low (and (value_type (multi_lane 32 4))
1149
+ x))
1150
+ (uwiden_low (and (value_type (multi_lane 32 4))
1151
+ y)))))
1152
+ (let ((x2 Xmm (x64_pshufd x 0x50))
1153
+ (y2 Xmm (x64_pshufd y 0x50)))
1154
+ (x64_pmuludq x2 y2)))
1155
+
1156
+ ;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1157
+
1158
+ (rule (lower (has_type $I8X16 (iabs x)))
1159
+ (x64_pabsb x))
1160
+
1161
+ (rule (lower (has_type $I16X8 (iabs x)))
1162
+ (x64_pabsw x))
1163
+
1164
+ (rule (lower (has_type $I32X4 (iabs x)))
1165
+ (x64_pabsd x))
1166
+
1167
+ ;; When AVX512 is available, we can use a single `vpabsq` instruction.
1168
+ (rule 2 (lower (has_type $I64X2 (iabs x)))
1169
+ (if-let $true (use_avx512vl_simd))
1170
+ (if-let $true (use_avx512f_simd))
1171
+ (x64_vpabsq x))
1172
+
1173
+ ;; Otherwise, we use a separate register, `neg`, to contain the results of `0 -
1174
+ ;; x` and then blend in those results with `blendvpd` if the MSB of `neg` was
1175
+ ;; set to 1 (i.e. if `neg` was negative or, conversely, if `x` was originally
1176
+ ;; positive).
1177
+ (rule 1 (lower (has_type $I64X2 (iabs x)))
1178
+ (if-let $true (use_sse41))
1179
+ (let ((rx Xmm x)
1180
+ (neg Xmm (x64_psubq (imm $I64X2 0) rx)))
1181
+ (x64_blendvpd neg rx neg)))
1182
+
1183
+ ;; and if `blendvpd` isn't available then perform a shift/shuffle to generate a
1184
+ ;; mask of which lanes are negative, followed by flipping bits/sub to make both
1185
+ ;; positive.
1186
+ (rule (lower (has_type $I64X2 (iabs x)))
1187
+ (let ((x Xmm x)
1188
+ (signs Xmm (x64_psrad x (RegMemImm.Imm 31)))
1189
+ (signs Xmm (x64_pshufd signs 0b11_11_01_01))
1190
+ (xor_if_negative Xmm (x64_pxor x signs)))
1191
+ (x64_psubq xor_if_negative signs)))
1192
+
1193
+ ;; `i64` and smaller.
1194
+
1195
+ (rule -1 (lower (has_type (fits_in_64 ty) (iabs x)))
1196
+ (let ((src Gpr x)
1197
+ (neg ProducesFlags (x64_neg_paired ty src))
1198
+ ;; Manually extract the result from the neg, then ignore
1199
+ ;; it below, since we need to pass it into the cmove
1200
+ ;; before we pass the cmove to with_flags_reg.
1201
+ (neg_result Gpr (produces_flags_get_reg neg))
1202
+ ;; When the neg instruction sets the sign flag,
1203
+ ;; takes the original (non-negative) value.
1204
+ (cmove ConsumesFlags (cmove ty (CC.S) src neg_result)))
1205
+ (with_flags_reg (produces_flags_ignore neg) cmove)))
1206
+
1207
+ ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1208
+
1209
+ (rule (lower (has_type $F32 (fabs x)))
1210
+ (x64_andps x (imm $F32 0x7fffffff)))
1211
+
1212
+ (rule (lower (has_type $F64 (fabs x)))
1213
+ (x64_andpd x (imm $F64 0x7fffffffffffffff)))
1214
+
1215
+ ;; Special case for `f32x4.abs`.
1216
+ (rule (lower (has_type $F32X4 (fabs x)))
1217
+ (x64_andps x
1218
+ (x64_psrld (vector_all_ones) (xmi_imm 1))))
1219
+
1220
+ ;; Special case for `f64x2.abs`.
1221
+ (rule (lower (has_type $F64X2 (fabs x)))
1222
+ (x64_andpd x
1223
+ (x64_psrlq (vector_all_ones) (xmi_imm 1))))
1224
+
1225
+ ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1226
+
1227
+ (rule (lower (has_type $F32 (fneg x)))
1228
+ (x64_xorps x (imm $F32 0x80000000)))
1229
+
1230
+ (rule (lower (has_type $F64 (fneg x)))
1231
+ (x64_xorpd x (imm $F64 0x8000000000000000)))
1232
+
1233
+ (rule (lower (has_type $F32X4 (fneg x)))
1234
+ (x64_xorps x
1235
+ (x64_pslld (vector_all_ones) (xmi_imm 31))))
1236
+
1237
+ (rule (lower (has_type $F64X2 (fneg x)))
1238
+ (x64_xorpd x
1239
+ (x64_psllq (vector_all_ones) (xmi_imm 63))))
1240
+
1241
+ ;;;; Rules for `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1242
+
1243
+ (decl lower_bmask (Type Type ValueRegs) ValueRegs)
1244
+
1245
+ ;; Values that fit in a register
1246
+ ;;
1247
+ ;; Use the neg instruction on the input which sets the CF (carry) flag
1248
+ ;; to 0 if the input is 0 or 1 otherwise.
1249
+ ;; We then subtract the output register with itself, which always gives a 0,
1250
+ ;; however use the carry flag from the previous negate to generate a -1 if it
1251
+ ;; was nonzero.
1252
+ ;;
1253
+ ;; neg in_reg
1254
+ ;; sbb out_reg, out_reg
1255
+ (rule 0
1256
+ (lower_bmask (fits_in_64 out_ty) (fits_in_64 in_ty) val)
1257
+ (let ((reg Gpr (value_regs_get_gpr val 0))
1258
+ (out ValueRegs (with_flags
1259
+ (x64_neg_paired in_ty reg)
1260
+ (x64_sbb_paired out_ty reg reg))))
1261
+ ;; Extract only the output of the sbb instruction
1262
+ (value_reg (value_regs_get out 1))))
1263
+
1264
+
1265
+ ;; If the input type is I128 we can `or` the registers, and recurse to the general case.
1266
+ (rule 1
1267
+ (lower_bmask (fits_in_64 out_ty) $I128 val)
1268
+ (let ((lo Gpr (value_regs_get_gpr val 0))
1269
+ (hi Gpr (value_regs_get_gpr val 1))
1270
+ (mixed Gpr (x64_or $I64 lo hi)))
1271
+ (lower_bmask out_ty $I64 (value_reg mixed))))
1272
+
1273
+ ;; If the output type is I128 we just duplicate the result of the I64 lowering
1274
+ (rule 2
1275
+ (lower_bmask $I128 in_ty val)
1276
+ (let ((res ValueRegs (lower_bmask $I64 in_ty val))
1277
+ (res Gpr (value_regs_get_gpr res 0)))
1278
+ (value_regs res res)))
1279
+
1280
+
1281
+ ;; Call the lower_bmask rule that does all the procssing
1282
+ (rule (lower (has_type out_ty (bmask x @ (value_type in_ty))))
1283
+ (lower_bmask out_ty in_ty x))
1284
+
1285
+ ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1286
+
1287
+ ;; `i64` and smaller.
1288
+
1289
+ (rule -2 (lower (has_type ty (bnot x)))
1290
+ (if (ty_int_ref_scalar_64 ty))
1291
+ (x64_not ty x))
1292
+
1293
+
1294
+ ;; `i128`.
1295
+
1296
+ (decl i128_not (Value) ValueRegs)
1297
+ (rule (i128_not x)
1298
+ (let ((x_regs ValueRegs x)
1299
+ (x_lo Gpr (value_regs_get_gpr x_regs 0))
1300
+ (x_hi Gpr (value_regs_get_gpr x_regs 1)))
1301
+ (value_gprs (x64_not $I64 x_lo)
1302
+ (x64_not $I64 x_hi))))
1303
+
1304
+ (rule (lower (has_type $I128 (bnot x)))
1305
+ (i128_not x))
1306
+
1307
+ ;; f32 and f64
1308
+
1309
+ (rule -3 (lower (has_type (ty_scalar_float ty) (bnot x)))
1310
+ (x64_xor_vector ty x (vector_all_ones)))
1311
+
1312
+ ;; Special case for vector-types where bit-negation is an xor against an
1313
+ ;; all-one value
1314
+ (rule -1 (lower (has_type ty @ (multi_lane _bits _lanes) (bnot x)))
1315
+ (x64_xor_vector ty x (vector_all_ones)))
1316
+
1317
+ ;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1318
+
1319
+ (rule (lower (has_type ty @ (multi_lane _bits _lanes)
1320
+ (bitselect condition
1321
+ if_true
1322
+ if_false)))
1323
+ ;; a = and if_true, condition
1324
+ ;; b = and_not condition, if_false
1325
+ ;; or b, a
1326
+ (let ((cond_xmm Xmm condition)
1327
+ (a Xmm (sse_and ty if_true cond_xmm))
1328
+ (b Xmm (sse_and_not ty cond_xmm if_false)))
1329
+ (sse_or ty b a)))
1330
+
1331
+ ;; If every byte of the condition is guaranteed to be all ones or all zeroes,
1332
+ ;; we can use x64_blend.
1333
+ (rule 1 (lower (has_type ty @ (multi_lane _bits _lanes)
1334
+ (bitselect condition
1335
+ if_true
1336
+ if_false)))
1337
+ (if-let $true (use_sse41))
1338
+ (if (all_ones_or_all_zeros condition))
1339
+ (x64_blend ty
1340
+ condition
1341
+ if_true
1342
+ if_false))
1343
+
1344
+ (decl pure partial all_ones_or_all_zeros (Value) bool)
1345
+ (rule (all_ones_or_all_zeros (and (icmp _ _ _) (value_type (multi_lane _ _)))) $true)
1346
+ (rule (all_ones_or_all_zeros (and (fcmp _ _ _) (value_type (multi_lane _ _)))) $true)
1347
+ (rule (all_ones_or_all_zeros (vconst (vconst_all_ones_or_all_zeros))) $true)
1348
+
1349
+ (decl pure vconst_all_ones_or_all_zeros () Constant)
1350
+ (extern extractor vconst_all_ones_or_all_zeros vconst_all_ones_or_all_zeros)
1351
+
1352
+ ;;;; Rules for `x86_blendv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1353
+
1354
+ (rule (lower (has_type $I8X16
1355
+ (x86_blendv condition if_true if_false)))
1356
+ (if-let $true (use_sse41))
1357
+ (x64_pblendvb if_false if_true condition))
1358
+
1359
+ (rule (lower (has_type $I32X4
1360
+ (x86_blendv condition if_true if_false)))
1361
+ (if-let $true (use_sse41))
1362
+ (x64_blendvps if_false if_true condition))
1363
+
1364
+ (rule (lower (has_type $I64X2
1365
+ (x86_blendv condition if_true if_false)))
1366
+ (if-let $true (use_sse41))
1367
+ (x64_blendvpd if_false if_true condition))
1368
+
1369
+ ;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1370
+
1371
+ (rule (lower (insertlane vec @ (value_type ty) val (u8_from_uimm8 idx)))
1372
+ (vec_insert_lane ty vec val idx))
1373
+
1374
+ ;; Helper function used below for `insertlane` but also here for other
1375
+ ;; lowerings.
1376
+ ;;
1377
+ ;; Note that the `Type` used here is the type of vector the insertion is
1378
+ ;; happening into, or the type of the first `Reg` argument.
1379
+ (decl vec_insert_lane (Type Xmm RegMem u8) Xmm)
1380
+
1381
+ ;; i8x16.replace_lane
1382
+ (rule 1 (vec_insert_lane $I8X16 vec val idx)
1383
+ (if-let $true (use_sse41))
1384
+ (x64_pinsrb vec val idx))
1385
+
1386
+ ;; This lowering is particularly unoptimized and is mostly just here to work
1387
+ ;; rather than here to be fast. Requiring SSE 4.1 for the above lowering isn't
1388
+ ;; the end of the world hopefully as that's a pretty old instruction set, so
1389
+ ;; this is the "simplest" version that works on SSE2 for now.
1390
+ ;;
1391
+ ;; This lowering masks the original vector with a constant with all 1s except
1392
+ ;; for the "hole" where this value will get placed into, meaning the desired
1393
+ ;; lane is guaranteed as all 0s. Next the `val` is shuffled into this hole with
1394
+ ;; a few operations:
1395
+ ;;
1396
+ ;; 1. The `val` is zero-extended to 32-bits to guarantee the lower 32-bits
1397
+ ;; are all defined.
1398
+ ;; 2. An arithmetic shift-left is used with the low two bits of `n`, the
1399
+ ;; desired lane, to move the value into the right position within the 32-bit
1400
+ ;; register value.
1401
+ ;; 3. The 32-bit register is moved with `movd` into an XMM register
1402
+ ;; 4. The XMM register, where all lanes are 0 except for the first lane which
1403
+ ;; has the shifted value, is then shuffled with `pshufd` to move the
1404
+ ;; shifted value to the correct and final lane. This uses the upper two
1405
+ ;; bits of `n` to index the i32x4 lane that we're targeting.
1406
+ ;;
1407
+ ;; This all, laboriously, gets the `val` into the desired lane so it's then
1408
+ ;; `por`'d with the original vec-with-a-hole to produce the final result of the
1409
+ ;; insertion.
1410
+ (rule (vec_insert_lane $I8X16 vec val n)
1411
+ (let ((vec_with_hole Xmm (x64_pand vec (insert_i8x16_lane_hole n)))
1412
+ (val Gpr (x64_movzx (ExtMode.BL) val))
1413
+ (val Gpr (x64_shl $I32 val (Imm8Reg.Imm8 (u8_shl (u8_and n 3) 3))))
1414
+ (val Xmm (x64_movd_to_xmm val))
1415
+ (val_at_hole Xmm (x64_pshufd val (insert_i8x16_lane_pshufd_imm (u8_shr n 2)))))
1416
+ (x64_por vec_with_hole val_at_hole)))
1417
+
1418
+ (decl insert_i8x16_lane_hole (u8) VCodeConstant)
1419
+ (extern constructor insert_i8x16_lane_hole insert_i8x16_lane_hole)
1420
+ (decl insert_i8x16_lane_pshufd_imm (u8) u8)
1421
+ (rule (insert_i8x16_lane_pshufd_imm 0) 0b01_01_01_00)
1422
+ (rule (insert_i8x16_lane_pshufd_imm 1) 0b01_01_00_01)
1423
+ (rule (insert_i8x16_lane_pshufd_imm 2) 0b01_00_01_01)
1424
+ (rule (insert_i8x16_lane_pshufd_imm 3) 0b00_01_01_01)
1425
+
1426
+ ;; i16x8.replace_lane
1427
+ (rule (vec_insert_lane $I16X8 vec val idx)
1428
+ (x64_pinsrw vec val idx))
1429
+
1430
+ ;; i32x4.replace_lane
1431
+ (rule 1 (vec_insert_lane $I32X4 vec val idx)
1432
+ (if-let $true (use_sse41))
1433
+ (x64_pinsrd vec val idx))
1434
+
1435
+ (rule (vec_insert_lane $I32X4 vec val 0)
1436
+ (x64_movss_regmove vec (x64_movd_to_xmm val)))
1437
+
1438
+ ;; tmp = [ vec[1] vec[0] val[1] val[0] ]
1439
+ ;; result = [ vec[3] vec[2] tmp[0] tmp[2] ]
1440
+ (rule (vec_insert_lane $I32X4 vec val 1)
1441
+ (let ((val Xmm (x64_movd_to_xmm val))
1442
+ (vec Xmm vec))
1443
+ (x64_shufps (x64_punpcklqdq val vec) vec 0b11_10_00_10)))
1444
+
1445
+ ;; tmp = [ vec[0] vec[3] val[0] val[0] ]
1446
+ ;; result = [ tmp[2] tmp[0] vec[1] vec[0] ]
1447
+ (rule (vec_insert_lane $I32X4 vec val 2)
1448
+ (let ((val Xmm (x64_movd_to_xmm val))
1449
+ (vec Xmm vec))
1450
+ (x64_shufps vec (x64_shufps val vec 0b00_11_00_00) 0b10_00_01_00)))
1451
+
1452
+ ;; tmp = [ vec[3] vec[2] val[1] val[0] ]
1453
+ ;; result = [ tmp[0] tmp[2] vec[1] vec[0] ]
1454
+ (rule (vec_insert_lane $I32X4 vec val 3)
1455
+ (let ((val Xmm (x64_movd_to_xmm val))
1456
+ (vec Xmm vec))
1457
+ (x64_shufps vec (x64_shufps val vec 0b11_10_01_00) 0b00_10_01_00)))
1458
+
1459
+ ;; i64x2.replace_lane
1460
+ (rule 1 (vec_insert_lane $I64X2 vec val idx)
1461
+ (if-let $true (use_sse41))
1462
+ (x64_pinsrq vec val idx))
1463
+ (rule (vec_insert_lane $I64X2 vec val 0)
1464
+ (x64_movsd_regmove vec (x64_movq_to_xmm val)))
1465
+ (rule (vec_insert_lane $I64X2 vec val 1)
1466
+ (x64_punpcklqdq vec (x64_movq_to_xmm val)))
1467
+
1468
+ ;; f32x4.replace_lane
1469
+ (rule 1 (vec_insert_lane $F32X4 vec val idx)
1470
+ (if-let $true (use_sse41))
1471
+ (x64_insertps vec val (sse_insertps_lane_imm idx)))
1472
+
1473
+ ;; f32x4.replace_lane 0 - without insertps
1474
+ (rule (vec_insert_lane $F32X4 vec (RegMem.Reg val) 0)
1475
+ (x64_movss_regmove vec val))
1476
+
1477
+ ;; f32x4.replace_lane 1 - without insertps
1478
+ ;; tmp = [ vec[1] vec[0] val[1] val[0] ]
1479
+ ;; result = [ vec[3] vec[2] tmp[0] tmp[2] ]
1480
+ (rule (vec_insert_lane $F32X4 vec (RegMem.Reg val) 1)
1481
+ (let ((tmp Xmm (x64_movlhps val vec)))
1482
+ (x64_shufps tmp vec 0b11_10_00_10)))
1483
+
1484
+ ;; f32x4.replace_lane 2 - without insertps
1485
+ ;; tmp = [ vec[0] vec[3] val[0] val[0] ]
1486
+ ;; result = [ tmp[2] tmp[0] vec[1] vec[0] ]
1487
+ (rule (vec_insert_lane $F32X4 vec (RegMem.Reg val) 2)
1488
+ (let ((tmp Xmm (x64_shufps val vec 0b00_11_00_00)))
1489
+ (x64_shufps vec tmp 0b10_00_01_00)))
1490
+
1491
+ ;; f32x4.replace_lane 3 - without insertps
1492
+ ;; tmp = [ vec[3] vec[2] val[1] val[0] ]
1493
+ ;; result = [ tmp[0] tmp[2] vec[1] vec[0] ]
1494
+ (rule (vec_insert_lane $F32X4 vec (RegMem.Reg val) 3)
1495
+ (let ((tmp Xmm (x64_shufps val vec 0b11_10_01_00)))
1496
+ (x64_shufps vec tmp 0b00_10_01_00)))
1497
+
1498
+ ;; Recursively delegate to the above rules by loading from memory first.
1499
+ (rule (vec_insert_lane $F32X4 vec (RegMem.Mem addr) idx)
1500
+ (vec_insert_lane $F32X4 vec (x64_movss_load addr) idx))
1501
+
1502
+ ;; External rust code used to calculate the immediate value to `insertps`.
1503
+ (decl sse_insertps_lane_imm (u8) u8)
1504
+ (extern constructor sse_insertps_lane_imm sse_insertps_lane_imm)
1505
+
1506
+ ;; f64x2.replace_lane 0
1507
+ ;;
1508
+ ;; Here the `movsd` instruction is used specifically to specialize moving
1509
+ ;; into the fist lane where unlike above cases we're not using the lane
1510
+ ;; immediate as an immediate to the instruction itself.
1511
+ (rule (vec_insert_lane $F64X2 vec (RegMem.Reg val) 0)
1512
+ (x64_movsd_regmove vec val))
1513
+ (rule (vec_insert_lane $F64X2 vec (RegMem.Mem val) 0)
1514
+ (x64_movsd_regmove vec (x64_movsd_load val)))
1515
+
1516
+ ;; f64x2.replace_lane 1
1517
+ ;;
1518
+ ;; Here the `movlhps` instruction is used specifically to specialize moving
1519
+ ;; into the second lane where unlike above cases we're not using the lane
1520
+ ;; immediate as an immediate to the instruction itself.
1521
+ (rule (vec_insert_lane $F64X2 vec val 1)
1522
+ (x64_movlhps vec val))
1523
+
1524
+ ;;;; Rules for `smin`, `smax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1525
+
1526
+ ;; `i64` and smaller.
1527
+
1528
+ (decl cmp_and_choose (Type CC Value Value) ValueRegs)
1529
+ (rule (cmp_and_choose (fits_in_64 ty) cc x y)
1530
+ (let ((size OperandSize (raw_operand_size_of_type ty))
1531
+ ;; We need to put x and y in registers explicitly because
1532
+ ;; we use the values more than once. Hence, even if these
1533
+ ;; are "unique uses" at the CLIF level and would otherwise
1534
+ ;; allow for load-op merging, here we cannot do that.
1535
+ (x_reg Reg x)
1536
+ (y_reg Reg y))
1537
+ (with_flags_reg (x64_cmp size x_reg y_reg)
1538
+ (cmove ty cc y_reg x_reg))))
1539
+
1540
+ (rule -1 (lower (has_type (fits_in_64 ty) (umin x y)))
1541
+ (cmp_and_choose ty (CC.B) x y))
1542
+
1543
+ (rule -1 (lower (has_type (fits_in_64 ty) (umax x y)))
1544
+ (cmp_and_choose ty (CC.NB) x y))
1545
+
1546
+ (rule -1 (lower (has_type (fits_in_64 ty) (smin x y)))
1547
+ (cmp_and_choose ty (CC.L) x y))
1548
+
1549
+ (rule -1 (lower (has_type (fits_in_64 ty) (smax x y)))
1550
+ (cmp_and_choose ty (CC.NL) x y))
1551
+
1552
+ ;; SSE helpers for determining if single-instruction lowerings are available.
1553
+
1554
+ (decl pure has_pmins (Type) bool)
1555
+ (rule 1 (has_pmins $I16X8) $true)
1556
+ (rule 1 (has_pmins $I64X2) $false)
1557
+ (rule (has_pmins _) (use_sse41))
1558
+
1559
+ (decl pure has_pmaxs (Type) bool)
1560
+ (rule 1 (has_pmaxs $I16X8) $true)
1561
+ (rule 1 (has_pmaxs $I64X2) $false)
1562
+ (rule (has_pmaxs _) (use_sse41))
1563
+
1564
+ (decl pure has_pmaxu (Type) bool)
1565
+ (rule 1 (has_pmaxu $I8X16) $true)
1566
+ (rule 1 (has_pmaxu $I64X2) $false)
1567
+ (rule (has_pmaxu _) (use_sse41))
1568
+
1569
+ (decl pure has_pminu (Type) bool)
1570
+ (rule 1 (has_pminu $I8X16) $true)
1571
+ (rule 1 (has_pminu $I64X2) $false)
1572
+ (rule (has_pminu _) (use_sse41))
1573
+
1574
+ ;; SSE `smax`.
1575
+
1576
+ (rule (lower (has_type (ty_vec128 ty) (smax x y)))
1577
+ (lower_vec_smax ty x y))
1578
+
1579
+ (decl lower_vec_smax (Type Xmm Xmm) Xmm)
1580
+ (rule 1 (lower_vec_smax ty x y)
1581
+ (if-let $true (has_pmaxs ty))
1582
+ (x64_pmaxs ty x y))
1583
+
1584
+ (rule (lower_vec_smax ty x y)
1585
+ (let (
1586
+ (x Xmm x)
1587
+ (y Xmm y)
1588
+ (cmp Xmm (x64_pcmpgt ty x y))
1589
+ (x_is_max Xmm (x64_pand cmp x))
1590
+ (y_is_max Xmm (x64_pandn cmp y))
1591
+ )
1592
+ (x64_por x_is_max y_is_max)))
1593
+
1594
+ ;; SSE `smin`.
1595
+
1596
+ (rule 1 (lower (has_type (ty_vec128 ty) (smin x y)))
1597
+ (if-let $true (has_pmins ty))
1598
+ (x64_pmins ty x y))
1599
+
1600
+ (rule (lower (has_type (ty_vec128 ty) (smin x y)))
1601
+ (let (
1602
+ (x Xmm x)
1603
+ (y Xmm y)
1604
+ (cmp Xmm (x64_pcmpgt ty y x))
1605
+ (x_is_min Xmm (x64_pand cmp x))
1606
+ (y_is_min Xmm (x64_pandn cmp y))
1607
+ )
1608
+ (x64_por x_is_min y_is_min)))
1609
+
1610
+ ;; SSE `umax`.
1611
+
1612
+ (rule 2 (lower (has_type (ty_vec128 ty) (umax x y)))
1613
+ (if-let $true (has_pmaxu ty))
1614
+ (x64_pmaxu ty x y))
1615
+
1616
+ ;; If y < x then the saturating subtraction will be zero, otherwise when added
1617
+ ;; back to x it'll return y.
1618
+ (rule 1 (lower (has_type $I16X8 (umax x y)))
1619
+ (let ((x Xmm x))
1620
+ (x64_paddw x (x64_psubusw y x))))
1621
+
1622
+ ;; Flip the upper bits of each lane so the signed comparison has the same
1623
+ ;; result as a signed comparison, and then select the results with the output
1624
+ ;; mask. See `pcmpgt` lowering for info on flipping the upper bit.
1625
+ (rule (lower (has_type (ty_vec128 ty) (umax x y)))
1626
+ (let (
1627
+ (x Xmm x)
1628
+ (y Xmm y)
1629
+ (mask Xmm (flip_high_bit_mask ty))
1630
+ (x_masked Xmm (x64_pxor x mask))
1631
+ (y_masked Xmm (x64_pxor y mask))
1632
+ (cmp Xmm (x64_pcmpgt ty x_masked y_masked))
1633
+ (x_is_max Xmm (x64_pand cmp x))
1634
+ (y_is_max Xmm (x64_pandn cmp y))
1635
+ )
1636
+ (x64_por x_is_max y_is_max)))
1637
+
1638
+ (decl flip_high_bit_mask (Type) Xmm)
1639
+ (rule (flip_high_bit_mask $I16X8)
1640
+ (x64_movdqu_load (emit_u128_le_const 0x8000_8000_8000_8000_8000_8000_8000_8000)))
1641
+ (rule (flip_high_bit_mask $I32X4)
1642
+ (x64_movdqu_load (emit_u128_le_const 0x80000000_80000000_80000000_80000000)))
1643
+ (rule (flip_high_bit_mask $I64X2)
1644
+ (x64_movdqu_load (emit_u128_le_const 0x8000000000000000_8000000000000000)))
1645
+
1646
+ ;; SSE `umin`.
1647
+
1648
+ (rule 2 (lower (has_type (ty_vec128 ty) (umin x y)))
1649
+ (if-let $true (has_pminu ty))
1650
+ (x64_pminu ty x y))
1651
+
1652
+ ;; If x < y then the saturating subtraction will be 0. Otherwise if x > y then
1653
+ ;; the saturated result, when subtracted again, will go back to `y`.
1654
+ (rule 1 (lower (has_type $I16X8 (umin x y)))
1655
+ (let ((x Xmm x))
1656
+ (x64_psubw x (x64_psubusw x y))))
1657
+
1658
+ ;; Same as `umax`, and see `pcmpgt` for docs on flipping the upper bit.
1659
+ (rule (lower (has_type (ty_vec128 ty) (umin x y)))
1660
+ (let (
1661
+ (x Xmm x)
1662
+ (y Xmm y)
1663
+ (mask Xmm (flip_high_bit_mask ty))
1664
+ (x_masked Xmm (x64_pxor x mask))
1665
+ (y_masked Xmm (x64_pxor y mask))
1666
+ (cmp Xmm (x64_pcmpgt ty y_masked x_masked))
1667
+ (x_is_max Xmm (x64_pand cmp x))
1668
+ (y_is_max Xmm (x64_pandn cmp y))
1669
+ )
1670
+ (x64_por x_is_max y_is_max)))
1671
+
1672
+ ;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1673
+
1674
+ (rule (lower (trap code))
1675
+ (side_effect (x64_ud2 code)))
1676
+
1677
+ ;;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1678
+
1679
+ (rule (lower (has_type (fits_in_64 ty) (uadd_overflow_trap a b tc)))
1680
+ (with_flags
1681
+ (x64_add_with_flags_paired ty a b)
1682
+ (trap_if (CC.B) tc)))
1683
+
1684
+ ;; Handle lhs immediates/sinkable loads in addition to the automatic rhs
1685
+ ;; handling of above.
1686
+
1687
+ (rule 1 (lower (has_type (fits_in_64 ty)
1688
+ (uadd_overflow_trap (simm32_from_value a) b tc)))
1689
+ (with_flags
1690
+ (x64_add_with_flags_paired ty b a)
1691
+ (trap_if (CC.B) tc)))
1692
+
1693
+ (rule 2 (lower (has_type (fits_in_64 ty)
1694
+ (uadd_overflow_trap (sinkable_load a) b tc)))
1695
+ (with_flags
1696
+ (x64_add_with_flags_paired ty b a)
1697
+ (trap_if (CC.B) tc)))
1698
+
1699
+ ;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1700
+
1701
+ (rule (lower (resumable_trap code))
1702
+ (side_effect (x64_ud2 code)))
1703
+
1704
+ ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1705
+
1706
+ ;; N.B.: the Ret itself is generated by the ABI.
1707
+ (rule (lower (return args))
1708
+ (lower_return args))
1709
+
1710
+ ;;;; Rules for `icmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1711
+
1712
+ (rule -2 (lower (icmp cc a @ (value_type (fits_in_64 ty)) b))
1713
+ (lower_icmp_bool (emit_cmp cc a b)))
1714
+
1715
+ (rule -1 (lower (icmp cc a @ (value_type $I128) b))
1716
+ (lower_icmp_bool (emit_cmp cc a b)))
1717
+
1718
+ ;; Peephole optimization for `x < 0`, when x is a signed 64 bit value
1719
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThan) x @ (value_type $I64) (u64_from_iconst 0))))
1720
+ (x64_shr $I64 x (Imm8Reg.Imm8 63)))
1721
+
1722
+ ;; Peephole optimization for `0 > x`, when x is a signed 64 bit value
1723
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThan) (u64_from_iconst 0) x @ (value_type $I64))))
1724
+ (x64_shr $I64 x (Imm8Reg.Imm8 63)))
1725
+
1726
+ ;; Peephole optimization for `0 <= x`, when x is a signed 64 bit value
1727
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThanOrEqual) (u64_from_iconst 0) x @ (value_type $I64))))
1728
+ (x64_shr $I64 (x64_not $I64 x) (Imm8Reg.Imm8 63)))
1729
+
1730
+ ;; Peephole optimization for `x >= 0`, when x is a signed 64 bit value
1731
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThanOrEqual) x @ (value_type $I64) (u64_from_iconst 0))))
1732
+ (x64_shr $I64 (x64_not $I64 x) (Imm8Reg.Imm8 63)))
1733
+
1734
+ ;; Peephole optimization for `x < 0`, when x is a signed 32 bit value
1735
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThan) x @ (value_type $I32) (u64_from_iconst 0))))
1736
+ (x64_shr $I32 x (Imm8Reg.Imm8 31)))
1737
+
1738
+ ;; Peephole optimization for `0 > x`, when x is a signed 32 bit value
1739
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThan) (u64_from_iconst 0) x @ (value_type $I32))))
1740
+ (x64_shr $I32 x (Imm8Reg.Imm8 31)))
1741
+
1742
+ ;; Peephole optimization for `0 <= x`, when x is a signed 32 bit value
1743
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedLessThanOrEqual) (u64_from_iconst 0) x @ (value_type $I32))))
1744
+ (x64_shr $I32 (x64_not $I64 x) (Imm8Reg.Imm8 31)))
1745
+
1746
+ ;; Peephole optimization for `x >= 0`, when x is a signed 32 bit value
1747
+ (rule 2 (lower (has_type $I8 (icmp (IntCC.SignedGreaterThanOrEqual) x @ (value_type $I32) (u64_from_iconst 0))))
1748
+ (x64_shr $I32 (x64_not $I64 x) (Imm8Reg.Imm8 31)))
1749
+
1750
+ ;; For XMM-held values, we lower to `PCMP*` instructions, sometimes more than
1751
+ ;; one. To note: what is different here about the output values is that each
1752
+ ;; lane will be filled with all 1s or all 0s according to the comparison,
1753
+ ;; whereas for GPR-held values, the result will be simply 0 or 1 (upper bits
1754
+ ;; unset).
1755
+ (rule (lower (icmp (IntCC.Equal) a @ (value_type (ty_vec128 ty)) b))
1756
+ (x64_pcmpeq ty a b))
1757
+
1758
+ ;; To lower a not-equals comparison, we perform an equality comparison
1759
+ ;; (PCMPEQ*) and then invert the bits (PXOR with all 1s).
1760
+ (rule (lower (icmp (IntCC.NotEqual) a @ (value_type (ty_vec128 ty)) b))
1761
+ (let ((checked Xmm (x64_pcmpeq ty a b))
1762
+ (all_ones Xmm (vector_all_ones)))
1763
+ (x64_pxor checked all_ones)))
1764
+
1765
+ ;; SSE `sgt`
1766
+
1767
+ (rule (lower (icmp (IntCC.SignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1768
+ (x64_pcmpgt ty a b))
1769
+
1770
+ ;; SSE `slt`
1771
+
1772
+ (rule (lower (icmp (IntCC.SignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1773
+ (x64_pcmpgt ty b a))
1774
+
1775
+ ;; SSE `ugt`
1776
+
1777
+ ;; N.B.: we must manually prevent load coalescing operands; the
1778
+ ;; register allocator gets confused otherwise.
1779
+ (rule 1 (lower (icmp (IntCC.UnsignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1780
+ (if-let $true (has_pmaxu ty))
1781
+ (let ((a Xmm a)
1782
+ (b Xmm b)
1783
+ (max Xmm (x64_pmaxu ty a b))
1784
+ (eq Xmm (x64_pcmpeq ty max b)))
1785
+ (x64_pxor eq (vector_all_ones))))
1786
+
1787
+ ;; Flip the upper bit of each lane so the result of a signed comparison is the
1788
+ ;; same as the result of an unsigned comparison (see docs on `pcmpgt` for more)
1789
+ (rule (lower (icmp (IntCC.UnsignedGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1790
+ (let ((mask Xmm (flip_high_bit_mask ty))
1791
+ (a_masked Xmm (x64_pxor a mask))
1792
+ (b_masked Xmm (x64_pxor b mask)))
1793
+ (x64_pcmpgt ty a_masked b_masked)))
1794
+
1795
+ ;; SSE `ult`
1796
+
1797
+ (rule 1 (lower (icmp (IntCC.UnsignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1798
+ (if-let $true (has_pminu ty))
1799
+ ;; N.B.: see note above.
1800
+ (let ((a Xmm a)
1801
+ (b Xmm b)
1802
+ (min Xmm (x64_pminu ty a b))
1803
+ (eq Xmm (x64_pcmpeq ty min b)))
1804
+ (x64_pxor eq (vector_all_ones))))
1805
+
1806
+ ;; Flip the upper bit of `a` and `b` so the signed comparison result will
1807
+ ;; be the same as the unsigned comparison result (see docs on `pcmpgt` for more).
1808
+ (rule (lower (icmp (IntCC.UnsignedLessThan) a @ (value_type (ty_vec128 ty)) b))
1809
+ (let ((mask Xmm (flip_high_bit_mask ty))
1810
+ (a_masked Xmm (x64_pxor a mask))
1811
+ (b_masked Xmm (x64_pxor b mask)))
1812
+ (x64_pcmpgt ty b_masked a_masked)))
1813
+
1814
+ ;; SSE `sge`
1815
+
1816
+ ;; Use `pmaxs*` and compare the result to `a` to see if it's `>= b`.
1817
+ (rule 1 (lower (icmp (IntCC.SignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1818
+ (if-let $true (has_pmaxs ty))
1819
+ (x64_pcmpeq ty a (x64_pmaxs ty a b)))
1820
+
1821
+ ;; Without `pmaxs*` use a `pcmpgt*` with reversed operands and invert the
1822
+ ;; result.
1823
+ (rule (lower (icmp (IntCC.SignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1824
+ (x64_pxor (x64_pcmpgt ty b a) (vector_all_ones)))
1825
+
1826
+ ;; SSE `sle`
1827
+
1828
+ ;; With `pmins*` use that and compare the result to `a`.
1829
+ (rule 1 (lower (icmp (IntCC.SignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1830
+ (if-let $true (has_pmins ty))
1831
+ (x64_pcmpeq ty a (x64_pmins ty a b)))
1832
+
1833
+ ;; Without `pmins*` perform a greater-than test and invert the result.
1834
+ (rule (lower (icmp (IntCC.SignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1835
+ (x64_pxor (x64_pcmpgt ty a b) (vector_all_ones)))
1836
+
1837
+ ;; SSE `uge`
1838
+
1839
+ (rule 2 (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1840
+ (if-let $true (has_pmaxu ty))
1841
+ (x64_pcmpeq ty a (x64_pmaxu ty a b)))
1842
+
1843
+ ;; Perform a saturating subtract of `a` from `b` and if the result is zero then
1844
+ ;; `a` is greater or equal.
1845
+ (rule 1 (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type $I16X8) b))
1846
+ (x64_pcmpeqw (x64_psubusw b a) (xmm_zero $I16X8)))
1847
+
1848
+ ;; Flip the upper bit of each lane so the signed comparison is the same as
1849
+ ;; an unsigned one and then invert the result. See docs on `pcmpgt` for why
1850
+ ;; flipping the upper bit works.
1851
+ (rule (lower (icmp (IntCC.UnsignedGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1852
+ (let (
1853
+ (mask Xmm (flip_high_bit_mask ty))
1854
+ (a_masked Xmm (x64_pxor a mask))
1855
+ (b_masked Xmm (x64_pxor b mask))
1856
+ (cmp Xmm (x64_pcmpgt ty b_masked a_masked))
1857
+ )
1858
+ (x64_pxor cmp (vector_all_ones))))
1859
+
1860
+ ;; SSE `ule`
1861
+
1862
+ (rule 2 (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1863
+ (if-let $true (has_pminu ty))
1864
+ (x64_pcmpeq ty a (x64_pminu ty a b)))
1865
+
1866
+ ;; A saturating subtraction will produce zeros if `a` is less than `b`, so
1867
+ ;; compare that result to an all-zeros result to figure out lanes of `a` that
1868
+ ;; are <= to the lanes in `b`
1869
+ (rule 1 (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type $I16X8) b))
1870
+ (let ((zeros_if_a_is_min Xmm (x64_psubusw a b)))
1871
+ (x64_pcmpeqw zeros_if_a_is_min (xmm_zero $I8X16))))
1872
+
1873
+ ;; Flip the upper bit of each lane in `a` and `b` so a signed comparison
1874
+ ;; produces the same result as an unsigned comparison. Then test test for `gt`
1875
+ ;; and invert the result to get the `le` that is desired here. See docs on
1876
+ ;; `pcmpgt` for why flipping the upper bit works.
1877
+ (rule (lower (icmp (IntCC.UnsignedLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1878
+ (let (
1879
+ (mask Xmm (flip_high_bit_mask ty))
1880
+ (a_masked Xmm (x64_pxor a mask))
1881
+ (b_masked Xmm (x64_pxor b mask))
1882
+ (cmp Xmm (x64_pcmpgt ty a_masked b_masked))
1883
+ )
1884
+ (x64_pxor cmp (vector_all_ones))))
1885
+
1886
+ ;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1887
+
1888
+ ;; CLIF's `fcmp` instruction always operates on XMM registers--both scalar and
1889
+ ;; vector. For the scalar versions, we use the flag-setting behavior of the
1890
+ ;; `UCOMIS*` instruction to `SETcc` a 0 or 1 in a GPR register. Note that CLIF's
1891
+ ;; `select` uses the same kind of flag-setting behavior but chooses values other
1892
+ ;; than 0 or 1.
1893
+ ;;
1894
+ ;; Checking the result of `UCOMIS*` is unfortunately difficult in some cases
1895
+ ;; because we do not have `SETcc` instructions that explicitly check
1896
+ ;; simultaneously for the condition (i.e., `eq`, `le`, `gt`, etc.) *and*
1897
+ ;; orderedness. Instead, we must check the flags multiple times. The UCOMIS*
1898
+ ;; documentation (see Intel's Software Developer's Manual, volume 2, chapter 4)
1899
+ ;; is helpful:
1900
+ ;; - unordered assigns Z = 1, P = 1, C = 1
1901
+ ;; - greater than assigns Z = 0, P = 0, C = 0
1902
+ ;; - less than assigns Z = 0, P = 0, C = 1
1903
+ ;; - equal assigns Z = 1, P = 0, C = 0
1904
+
1905
+ (rule -1 (lower (fcmp cc a @ (value_type (ty_scalar_float ty)) b))
1906
+ (lower_fcmp_bool (emit_fcmp cc a b)))
1907
+
1908
+ ;; For vector lowerings, we use `CMPP*` instructions with a 3-bit operand that
1909
+ ;; determines the comparison to make. Note that comparisons that succeed will
1910
+ ;; fill the lane with 1s; comparisons that do not will fill the lane with 0s.
1911
+
1912
+ (rule (lower (fcmp (FloatCC.Equal) a @ (value_type (ty_vec128 ty)) b))
1913
+ (x64_cmpp ty a b (FcmpImm.Equal)))
1914
+ (rule (lower (fcmp (FloatCC.NotEqual) a @ (value_type (ty_vec128 ty)) b))
1915
+ (x64_cmpp ty a b (FcmpImm.NotEqual)))
1916
+ (rule (lower (fcmp (FloatCC.LessThan) a @ (value_type (ty_vec128 ty)) b))
1917
+ (x64_cmpp ty a b (FcmpImm.LessThan)))
1918
+ (rule (lower (fcmp (FloatCC.LessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1919
+ (x64_cmpp ty a b (FcmpImm.LessThanOrEqual)))
1920
+ (rule (lower (fcmp (FloatCC.Ordered) a @ (value_type (ty_vec128 ty)) b))
1921
+ (x64_cmpp ty a b (FcmpImm.Ordered)))
1922
+ (rule (lower (fcmp (FloatCC.Unordered) a @ (value_type (ty_vec128 ty)) b))
1923
+ (x64_cmpp ty a b (FcmpImm.Unordered)))
1924
+ (rule (lower (fcmp (FloatCC.UnorderedOrGreaterThan) a @ (value_type (ty_vec128 ty)) b))
1925
+ (x64_cmpp ty a b (FcmpImm.UnorderedOrGreaterThan)))
1926
+ (rule (lower (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1927
+ (x64_cmpp ty a b (FcmpImm.UnorderedOrGreaterThanOrEqual)))
1928
+
1929
+ ;; Some vector lowerings rely on flipping the operands and using a reversed
1930
+ ;; comparison code.
1931
+
1932
+ (rule (lower (fcmp (FloatCC.GreaterThan) a @ (value_type (ty_vec128 ty)) b))
1933
+ (x64_cmpp ty b a (FcmpImm.LessThan)))
1934
+ (rule (lower (fcmp (FloatCC.GreaterThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1935
+ (x64_cmpp ty b a (FcmpImm.LessThanOrEqual)))
1936
+ (rule (lower (fcmp (FloatCC.UnorderedOrLessThan) a @ (value_type (ty_vec128 ty)) b))
1937
+ (x64_cmpp ty b a (FcmpImm.UnorderedOrGreaterThan)))
1938
+ (rule (lower (fcmp (FloatCC.UnorderedOrLessThanOrEqual) a @ (value_type (ty_vec128 ty)) b))
1939
+ (x64_cmpp ty b a (FcmpImm.UnorderedOrGreaterThanOrEqual)))
1940
+
1941
+ ;; Some vector lowerings are simply not supported for certain codes:
1942
+ ;; - FloatCC::OrderedNotEqual
1943
+ ;; - FloatCC::UnorderedOrEqual
1944
+
1945
+ ;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1946
+
1947
+ ;; When a `select` has an `fcmp` as a condition then rely on `emit_fcmp` to
1948
+ ;; figure out how to perform the comparison.
1949
+ ;;
1950
+ ;; Note, though, that the `FloatCC.Equal` requires an "and" to happen for two
1951
+ ;; condition codes which isn't the easiest thing to lower to a `cmove`
1952
+ ;; instruction. For this reason a `select (fcmp eq ..) ..` is instead
1953
+ ;; flipped around to be `select (fcmp ne ..) ..` with all operands reversed.
1954
+ ;; This will produce a `FcmpCondResult.OrCondition` which is easier to codegen
1955
+ ;; for.
1956
+ (rule (lower (has_type ty (select (maybe_uextend (fcmp cc a b)) x y)))
1957
+ (lower_select_fcmp ty (emit_fcmp cc a b) x y))
1958
+ (rule 1 (lower (has_type ty (select (maybe_uextend (fcmp (FloatCC.Equal) a b)) x y)))
1959
+ (lower_select_fcmp ty (emit_fcmp (FloatCC.NotEqual) a b) y x))
1960
+
1961
+ (decl lower_select_fcmp (Type FcmpCondResult Value Value) InstOutput)
1962
+ (rule (lower_select_fcmp ty (FcmpCondResult.Condition flags cc) x y)
1963
+ (with_flags flags (cmove_from_values ty cc x y)))
1964
+ (rule (lower_select_fcmp ty (FcmpCondResult.OrCondition flags cc1 cc2) x y)
1965
+ (with_flags flags (cmove_or_from_values ty cc1 cc2 x y)))
1966
+
1967
+ ;; We also can lower `select`s that depend on an `icmp` test, but more simply
1968
+ ;; than the `fcmp` variants above. In these cases, we lower to a `CMP`
1969
+ ;; instruction plus a `CMOV`; recall that `cmove_from_values` here may emit more
1970
+ ;; than one instruction for certain types (e.g., XMM-held, I128).
1971
+
1972
+ (rule (lower (has_type ty (select (maybe_uextend (icmp cc a @ (value_type (fits_in_64 a_ty)) b)) x y)))
1973
+ (let ((size OperandSize (raw_operand_size_of_type a_ty)))
1974
+ (with_flags (x64_cmp size b a) (cmove_from_values ty cc x y))))
1975
+
1976
+ ;; Finally, we lower `select` from a condition value `c`. These rules are meant
1977
+ ;; to be the final, default lowerings if no other patterns matched above.
1978
+
1979
+ (rule -1 (lower (has_type ty (select c @ (value_type (fits_in_64 a_ty)) x y)))
1980
+ (let ((size OperandSize (raw_operand_size_of_type a_ty))
1981
+ ;; N.B.: disallow load-op fusion, see above. TODO:
1982
+ ;; https://github.com/bytecodealliance/wasmtime/issues/3953.
1983
+ (gpr_c Gpr (put_in_gpr c)))
1984
+ (with_flags (x64_test size gpr_c gpr_c) (cmove_from_values ty (CC.NZ) x y))))
1985
+
1986
+ (rule -2 (lower (has_type ty (select c @ (value_type $I128) x y)))
1987
+ (let ((cond_result IcmpCondResult (cmp_zero_i128 (CC.Z) c)))
1988
+ (select_icmp cond_result x y)))
1989
+
1990
+ ;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1991
+
1992
+ ;; If available, we can use a plain lzcnt instruction here. Note no
1993
+ ;; special handling is required for zero inputs, because the machine
1994
+ ;; instruction does what the CLIF expects for zero, i.e. it returns
1995
+ ;; zero.
1996
+ (rule 3 (lower (has_type (ty_32_or_64 ty) (clz src)))
1997
+ (if-let $true (use_lzcnt))
1998
+ (x64_lzcnt ty src))
1999
+
2000
+ (rule 2 (lower (has_type (ty_32_or_64 ty) (clz src)))
2001
+ (do_clz ty ty src))
2002
+
2003
+ (rule 1 (lower
2004
+ (has_type (ty_8_or_16 ty)
2005
+ (clz src)))
2006
+ (do_clz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
2007
+
2008
+ (rule 0 (lower
2009
+ (has_type $I128
2010
+ (clz src)))
2011
+ (let ((upper Gpr (do_clz $I64 $I64 (value_regs_get_gpr src 1)))
2012
+ (lower Gpr (x64_add $I64
2013
+ (do_clz $I64 $I64 (value_regs_get_gpr src 0))
2014
+ (RegMemImm.Imm 64)))
2015
+ (result_lo Gpr
2016
+ (with_flags_reg
2017
+ (x64_cmp_imm (OperandSize.Size64) 64 upper)
2018
+ (cmove $I64 (CC.NZ) upper lower))))
2019
+ (value_regs result_lo (imm $I64 0))))
2020
+
2021
+ ;; Implementation helper for clz; operates on 32 or 64-bit units.
2022
+ (decl do_clz (Type Type Gpr) Gpr)
2023
+ (rule (do_clz ty orig_ty src)
2024
+ (let ((highest_bit_index Reg (bsr_or_else ty src (imm_i64 $I64 -1)))
2025
+ (bits_minus_1 Reg (imm ty (u64_sub (ty_bits_u64 orig_ty) 1))))
2026
+ (x64_sub ty bits_minus_1 highest_bit_index)))
2027
+
2028
+ ;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2029
+
2030
+ ;; Analogous to `clz` cases above, but using mirror instructions
2031
+ ;; (tzcnt vs lzcnt, bsf vs bsr).
2032
+
2033
+ (rule 3 (lower (has_type (ty_32_or_64 ty) (ctz src)))
2034
+ (if-let $true (use_bmi1))
2035
+ (x64_tzcnt ty src))
2036
+
2037
+ (rule 2 (lower (has_type (ty_32_or_64 ty) (ctz src)))
2038
+ (do_ctz ty ty src))
2039
+
2040
+ (rule 1 (lower
2041
+ (has_type (ty_8_or_16 ty)
2042
+ (ctz src)))
2043
+ (do_ctz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
2044
+
2045
+ (rule 0 (lower
2046
+ (has_type $I128
2047
+ (ctz src)))
2048
+ (let ((lower Gpr (do_ctz $I64 $I64 (value_regs_get_gpr src 0)))
2049
+ (upper Gpr (x64_add $I64
2050
+ (do_ctz $I64 $I64 (value_regs_get_gpr src 1))
2051
+ (RegMemImm.Imm 64)))
2052
+ (result_lo Gpr
2053
+ (with_flags_reg
2054
+ (x64_cmp_imm (OperandSize.Size64) 64 lower)
2055
+ (cmove $I64 (CC.Z) upper lower))))
2056
+ (value_regs result_lo (imm $I64 0))))
2057
+
2058
+ (decl do_ctz (Type Type Gpr) Gpr)
2059
+ (rule (do_ctz ty orig_ty src)
2060
+ (bsf_or_else ty src (imm $I64 (ty_bits_u64 orig_ty))))
2061
+
2062
+ ;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2063
+
2064
+ (rule 3 (lower (has_type (ty_32_or_64 ty) (popcnt src)))
2065
+ (if-let $true (use_popcnt))
2066
+ (x64_popcnt ty src))
2067
+
2068
+ (rule 2 (lower (has_type (ty_8_or_16 ty) (popcnt src)))
2069
+ (if-let $true (use_popcnt))
2070
+ (x64_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
2071
+
2072
+ (rule 1 (lower (has_type $I128 (popcnt src)))
2073
+ (if-let $true (use_popcnt))
2074
+ (let ((lo_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 0)))
2075
+ (hi_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 1))))
2076
+ (value_regs (x64_add $I64 lo_count hi_count) (imm $I64 0))))
2077
+
2078
+ (rule -1 (lower
2079
+ (has_type (ty_32_or_64 ty)
2080
+ (popcnt src)))
2081
+ (do_popcnt ty src))
2082
+
2083
+ (rule -2 (lower
2084
+ (has_type (ty_8_or_16 ty)
2085
+ (popcnt src)))
2086
+ (do_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
2087
+
2088
+ (rule (lower
2089
+ (has_type $I128
2090
+ (popcnt src)))
2091
+ (let ((lo_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 0)))
2092
+ (hi_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 1))))
2093
+ (value_regs (x64_add $I64 lo_count hi_count) (imm $I64 0))))
2094
+
2095
+ ;; Implementation of popcount when we don't nave a native popcount
2096
+ ;; instruction.
2097
+ (decl do_popcnt (Type Gpr) Gpr)
2098
+ (rule (do_popcnt $I64 src)
2099
+ (let ((shifted1 Gpr (x64_shr $I64 src (Imm8Reg.Imm8 1)))
2100
+ (sevens Gpr (imm $I64 0x7777777777777777))
2101
+ (masked1 Gpr (x64_and $I64 shifted1 sevens))
2102
+ ;; diff1 := src - ((src >> 1) & 0b0111_0111_0111...)
2103
+ (diff1 Gpr (x64_sub $I64 src masked1))
2104
+ (shifted2 Gpr (x64_shr $I64 masked1 (Imm8Reg.Imm8 1)))
2105
+ (masked2 Gpr (x64_and $I64 shifted2 sevens))
2106
+ ;; diff2 := diff1 - ((diff1 >> 1) & 0b0111_0111_0111...)
2107
+ (diff2 Gpr (x64_sub $I64 diff1 masked2))
2108
+ (shifted3 Gpr (x64_shr $I64 masked2 (Imm8Reg.Imm8 1)))
2109
+ (masked3 Gpr (x64_and $I64 shifted3 sevens))
2110
+ ;; diff3 := diff2 - ((diff2 >> 1) & 0b0111_0111_0111...)
2111
+ ;;
2112
+ ;; At this point, each nibble of diff3 is the popcount of
2113
+ ;; that nibble. This works because at each step above, we
2114
+ ;; are basically subtracting floor(value / 2) from the
2115
+ ;; running value; the leftover remainder is 1 if the LSB
2116
+ ;; was 1. After three steps, we have (nibble / 8) -- 0 or
2117
+ ;; 1 for the MSB of the nibble -- plus three possible
2118
+ ;; additions for the three other bits.
2119
+ (diff3 Gpr (x64_sub $I64 diff2 masked3))
2120
+ ;; Add the two nibbles of each byte together.
2121
+ (sum1 Gpr (x64_add $I64
2122
+ (x64_shr $I64 diff3 (Imm8Reg.Imm8 4))
2123
+ diff3))
2124
+ ;; Mask the above sum to have the popcount for each byte
2125
+ ;; in the lower nibble of that byte.
2126
+ (ofof Gpr (imm $I64 0x0f0f0f0f0f0f0f0f))
2127
+ (masked4 Gpr (x64_and $I64 sum1 ofof))
2128
+ (ones Gpr (imm $I64 0x0101010101010101))
2129
+ ;; Use a multiply to sum all of the bytes' popcounts into
2130
+ ;; the top byte. Consider the binomial expansion for the
2131
+ ;; top byte: it is the sum of the bytes (masked4 >> 56) *
2132
+ ;; 0x01 + (masked4 >> 48) * 0x01 + (masked4 >> 40) * 0x01
2133
+ ;; + ... + (masked4 >> 0).
2134
+ (mul Gpr (x64_mul $I64 masked4 ones))
2135
+ ;; Now take that top byte and return it as the popcount.
2136
+ (final Gpr (x64_shr $I64 mul (Imm8Reg.Imm8 56))))
2137
+ final))
2138
+
2139
+ ;; This is the 32-bit version of the above; the steps for each nibble
2140
+ ;; are the same, we just use constants half as wide.
2141
+ (rule (do_popcnt $I32 src)
2142
+ (let ((shifted1 Gpr (x64_shr $I32 src (Imm8Reg.Imm8 1)))
2143
+ (sevens Gpr (imm $I32 0x77777777))
2144
+ (masked1 Gpr (x64_and $I32 shifted1 sevens))
2145
+ (diff1 Gpr (x64_sub $I32 src masked1))
2146
+ (shifted2 Gpr (x64_shr $I32 masked1 (Imm8Reg.Imm8 1)))
2147
+ (masked2 Gpr (x64_and $I32 shifted2 sevens))
2148
+ (diff2 Gpr (x64_sub $I32 diff1 masked2))
2149
+ (shifted3 Gpr (x64_shr $I32 masked2 (Imm8Reg.Imm8 1)))
2150
+ (masked3 Gpr (x64_and $I32 shifted3 sevens))
2151
+ (diff3 Gpr (x64_sub $I32 diff2 masked3))
2152
+ (sum1 Gpr (x64_add $I32
2153
+ (x64_shr $I32 diff3 (Imm8Reg.Imm8 4))
2154
+ diff3))
2155
+ (masked4 Gpr (x64_and $I32 sum1 (RegMemImm.Imm 0x0f0f0f0f)))
2156
+ (mul Gpr (x64_mul $I32 masked4 (RegMemImm.Imm 0x01010101)))
2157
+ (final Gpr (x64_shr $I32 mul (Imm8Reg.Imm8 24))))
2158
+ final))
2159
+
2160
+
2161
+ (rule 1 (lower (has_type $I8X16 (popcnt src)))
2162
+ (if-let $true (use_avx512vl_simd))
2163
+ (if-let $true (use_avx512bitalg_simd))
2164
+ (x64_vpopcntb src))
2165
+
2166
+
2167
+ ;; For SSE 4.2 we use Mula's algorithm (https://arxiv.org/pdf/1611.07612.pdf):
2168
+ ;;
2169
+ ;; __m128i count_bytes ( __m128i v) {
2170
+ ;; __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
2171
+ ;; __m128i low_mask = _mm_set1_epi8 (0x0f);
2172
+ ;; __m128i lo = _mm_and_si128 (v, low_mask);
2173
+ ;; __m128i hi = _mm_and_si128 (_mm_srli_epi16 (v, 4), low_mask);
2174
+ ;; __m128i cnt1 = _mm_shuffle_epi8 (lookup, lo);
2175
+ ;; __m128i cnt2 = _mm_shuffle_epi8 (lookup, hi);
2176
+ ;; return _mm_add_epi8 (cnt1, cnt2);
2177
+ ;; }
2178
+ ;;
2179
+ ;; Details of the above algorithm can be found in the reference noted above, but the basics
2180
+ ;; are to create a lookup table that pre populates the popcnt values for each number [0,15].
2181
+ ;; The algorithm uses shifts to isolate 4 bit sections of the vector, pshufb as part of the
2182
+ ;; lookup process, and adds together the results.
2183
+ ;;
2184
+ ;; __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
2185
+
2186
+ (decl popcount_4bit_table () VCodeConstant) ;; bits-per-nibble table `lookup` above
2187
+ (extern constructor popcount_4bit_table popcount_4bit_table)
2188
+
2189
+ (decl popcount_low_mask () VCodeConstant) ;; mask for low nibbles: 0x0f * 16
2190
+ (extern constructor popcount_low_mask popcount_low_mask)
2191
+
2192
+ (rule (lower (has_type $I8X16
2193
+ (popcnt src)))
2194
+ (let ((nibble_table_const VCodeConstant (popcount_4bit_table))
2195
+ (low_mask XmmMem (popcount_low_mask))
2196
+ (low_nibbles Xmm (sse_and $I8X16 src low_mask))
2197
+ ;; Note that this is a 16x8 shift, but that's OK; we mask
2198
+ ;; off anything that traverses from one byte to the next
2199
+ ;; with the low_mask below.
2200
+ (shifted_src Xmm (x64_psrlw src (xmi_imm 4)))
2201
+ (high_nibbles Xmm (sse_and $I8X16 shifted_src low_mask))
2202
+ (lookup Xmm (x64_xmm_load_const $I8X16 (popcount_4bit_table)))
2203
+ (bit_counts_low Xmm (x64_pshufb lookup low_nibbles))
2204
+ (bit_counts_high Xmm (x64_pshufb lookup high_nibbles)))
2205
+ (x64_paddb bit_counts_low bit_counts_high)))
2206
+
2207
+ ;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2208
+
2209
+ (rule (lower (has_type $I8 (bitrev src)))
2210
+ (do_bitrev8 $I32 src))
2211
+
2212
+ (rule (lower (has_type $I16 (bitrev src)))
2213
+ (do_bitrev16 $I32 src))
2214
+
2215
+ (rule (lower (has_type $I32 (bitrev src)))
2216
+ (do_bitrev32 $I32 src))
2217
+
2218
+ (rule (lower (has_type $I64 (bitrev src)))
2219
+ (do_bitrev64 $I64 src))
2220
+
2221
+ (rule (lower (has_type $I128 (bitrev src)))
2222
+ (value_regs
2223
+ (do_bitrev64 $I64 (value_regs_get_gpr src 1))
2224
+ (do_bitrev64 $I64 (value_regs_get_gpr src 0))))
2225
+
2226
+ (decl do_bitrev8 (Type Gpr) Gpr)
2227
+ (rule (do_bitrev8 ty src)
2228
+ (let ((tymask u64 (ty_mask ty))
2229
+ (mask1 Gpr (imm ty (u64_and tymask 0x5555555555555555)))
2230
+ (lo1 Gpr (x64_and ty src mask1))
2231
+ (hi1 Gpr (x64_and ty (x64_shr ty src (Imm8Reg.Imm8 1)) mask1))
2232
+ (swap1 Gpr (x64_or ty
2233
+ (x64_shl ty lo1 (Imm8Reg.Imm8 1))
2234
+ hi1))
2235
+ (mask2 Gpr (imm ty (u64_and tymask 0x3333333333333333)))
2236
+ (lo2 Gpr (x64_and ty swap1 mask2))
2237
+ (hi2 Gpr (x64_and ty (x64_shr ty swap1 (Imm8Reg.Imm8 2)) mask2))
2238
+ (swap2 Gpr (x64_or ty
2239
+ (x64_shl ty lo2 (Imm8Reg.Imm8 2))
2240
+ hi2))
2241
+ (mask4 Gpr (imm ty (u64_and tymask 0x0f0f0f0f0f0f0f0f)))
2242
+ (lo4 Gpr (x64_and ty swap2 mask4))
2243
+ (hi4 Gpr (x64_and ty (x64_shr ty swap2 (Imm8Reg.Imm8 4)) mask4))
2244
+ (swap4 Gpr (x64_or ty
2245
+ (x64_shl ty lo4 (Imm8Reg.Imm8 4))
2246
+ hi4)))
2247
+ swap4))
2248
+
2249
+ (decl do_bitrev16 (Type Gpr) Gpr)
2250
+ (rule (do_bitrev16 ty src)
2251
+ (let ((src_ Gpr (do_bitrev8 ty src))
2252
+ (tymask u64 (ty_mask ty))
2253
+ (mask8 Gpr (imm ty (u64_and tymask 0x00ff00ff00ff00ff)))
2254
+ (lo8 Gpr (x64_and ty src_ mask8))
2255
+ (hi8 Gpr (x64_and ty (x64_shr ty src_ (Imm8Reg.Imm8 8)) mask8))
2256
+ (swap8 Gpr (x64_or ty
2257
+ (x64_shl ty lo8 (Imm8Reg.Imm8 8))
2258
+ hi8)))
2259
+ swap8))
2260
+
2261
+ (decl do_bitrev32 (Type Gpr) Gpr)
2262
+ (rule (do_bitrev32 ty src)
2263
+ (let ((src_ Gpr (do_bitrev16 ty src))
2264
+ (tymask u64 (ty_mask ty))
2265
+ (mask16 Gpr (imm ty (u64_and tymask 0x0000ffff0000ffff)))
2266
+ (lo16 Gpr (x64_and ty src_ mask16))
2267
+ (hi16 Gpr (x64_and ty (x64_shr ty src_ (Imm8Reg.Imm8 16)) mask16))
2268
+ (swap16 Gpr (x64_or ty
2269
+ (x64_shl ty lo16 (Imm8Reg.Imm8 16))
2270
+ hi16)))
2271
+ swap16))
2272
+
2273
+ (decl do_bitrev64 (Type Gpr) Gpr)
2274
+ (rule (do_bitrev64 ty @ $I64 src)
2275
+ (let ((src_ Gpr (do_bitrev32 ty src))
2276
+ (mask32 Gpr (imm ty 0xffffffff))
2277
+ (lo32 Gpr (x64_and ty src_ mask32))
2278
+ (hi32 Gpr (x64_shr ty src_ (Imm8Reg.Imm8 32)))
2279
+ (swap32 Gpr (x64_or ty
2280
+ (x64_shl ty lo32 (Imm8Reg.Imm8 32))
2281
+ hi32)))
2282
+ swap32))
2283
+
2284
+ ;; Rules for `bswap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2285
+
2286
+ ;; x64 bswap instruction is only for 32- or 64-bit swaps
2287
+ ;; implement the 16-bit swap as a rotl by 8
2288
+ (rule (lower (has_type $I16 (bswap src)))
2289
+ (x64_rotl $I16 src (Imm8Reg.Imm8 8)))
2290
+
2291
+ (rule (lower (has_type $I32 (bswap src)))
2292
+ (x64_bswap $I32 src))
2293
+
2294
+ (rule (lower (has_type $I64 (bswap src)))
2295
+ (x64_bswap $I64 src))
2296
+
2297
+ (rule (lower (has_type $I128 (bswap src)))
2298
+ (value_regs
2299
+ (x64_bswap $I64 (value_regs_get_gpr src 1))
2300
+ (x64_bswap $I64 (value_regs_get_gpr src 0))))
2301
+
2302
+ ;; Rules for `is_null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2303
+
2304
+ ;; Null references are represented by the constant value `0`.
2305
+ (rule (lower (is_null src @ (value_type $R64)))
2306
+ (with_flags
2307
+ (x64_cmp_imm (OperandSize.Size64) 0 src)
2308
+ (x64_setcc (CC.Z))))
2309
+
2310
+ ;; Rules for `is_invalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2311
+
2312
+ ;; Invalid references are represented by the constant value `-1`.
2313
+ (rule (lower (is_invalid src @ (value_type $R64)))
2314
+ (with_flags
2315
+ (x64_cmp_imm (OperandSize.Size64) 0xffffffff src) ;; simm32 0xffff_ffff is sign-extended to -1.
2316
+ (x64_setcc (CC.Z))))
2317
+
2318
+
2319
+ ;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2320
+
2321
+ ;; I{8,16,32,64} -> I128.
2322
+ (rule (lower (has_type $I128 (uextend src)))
2323
+ (value_regs (extend_to_gpr src $I64 (ExtendKind.Zero)) (imm $I64 0)))
2324
+
2325
+ ;; I{8,16,32} -> I64.
2326
+ (rule (lower (has_type $I64 (uextend src)))
2327
+ (extend_to_gpr src $I64 (ExtendKind.Zero)))
2328
+
2329
+ ;; I{8,16} -> I32
2330
+ ;; I8 -> I16
2331
+ (rule -1 (lower (has_type (fits_in_32 _) (uextend src)))
2332
+ (extend_to_gpr src $I32 (ExtendKind.Zero)))
2333
+
2334
+ ;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2335
+
2336
+ ;; I{8,16,32} -> I128.
2337
+ ;;
2338
+ ;; Produce upper 64 bits sign-extended from lower 64: shift right by
2339
+ ;; 63 bits to spread the sign bit across the result.
2340
+ (rule (lower (has_type $I128 (sextend src)))
2341
+ (let ((lo Gpr (extend_to_gpr src $I64 (ExtendKind.Sign)))
2342
+ (hi Gpr (x64_sar $I64 lo (Imm8Reg.Imm8 63))))
2343
+ (value_regs lo hi)))
2344
+
2345
+ ;; I{8,16,32} -> I64.
2346
+ (rule (lower (has_type $I64 (sextend src)))
2347
+ (extend_to_gpr src $I64 (ExtendKind.Sign)))
2348
+
2349
+ ;; I{8,16} -> I32
2350
+ ;; I8 -> I16
2351
+ (rule -1 (lower (has_type (fits_in_32 _) (sextend src)))
2352
+ (extend_to_gpr src $I32 (ExtendKind.Sign)))
2353
+
2354
+ ;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2355
+
2356
+ ;; T -> T is always a no-op, even I128 -> I128.
2357
+ (rule (lower (has_type ty (ireduce src @ (value_type ty))))
2358
+ src)
2359
+
2360
+ ;; T -> I{64,32,16,8}: We can simply pass through the value: values
2361
+ ;; are always stored with high bits undefined, so we can just leave
2362
+ ;; them be.
2363
+ (rule 1 (lower (has_type (fits_in_64 ty) (ireduce src)))
2364
+ (value_regs_get_gpr src 0))
2365
+
2366
+ ;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2367
+
2368
+ (rule (lower (debugtrap))
2369
+ (side_effect (x64_hlt)))
2370
+
2371
+ ;; Rules for `x86_pmaddubsw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2372
+
2373
+ (rule (lower (has_type $I16X8 (x86_pmaddubsw x y)))
2374
+ (x64_pmaddubsw y x))
2375
+
2376
+ ;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2377
+
2378
+ (rule (lower (has_type $F32 (fadd x y)))
2379
+ (x64_addss x y))
2380
+ (rule (lower (has_type $F64 (fadd x y)))
2381
+ (x64_addsd x y))
2382
+ (rule (lower (has_type $F32X4 (fadd x y)))
2383
+ (x64_addps x y))
2384
+ (rule (lower (has_type $F64X2 (fadd x y)))
2385
+ (x64_addpd x y))
2386
+
2387
+ ;; The above rules automatically sink loads for rhs operands, so additionally
2388
+ ;; add rules for sinking loads with lhs operands.
2389
+ (rule 1 (lower (has_type $F32 (fadd (sinkable_load x) y)))
2390
+ (x64_addss y x))
2391
+ (rule 1 (lower (has_type $F64 (fadd (sinkable_load x) y)))
2392
+ (x64_addsd y x))
2393
+ (rule 1 (lower (has_type $F32X4 (fadd (sinkable_load x) y)))
2394
+ (x64_addps y x))
2395
+ (rule 1 (lower (has_type $F64X2 (fadd (sinkable_load x) y)))
2396
+ (x64_addpd y x))
2397
+
2398
+ ;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2399
+
2400
+ (rule (lower (has_type $F32 (fsub x y)))
2401
+ (x64_subss x y))
2402
+ (rule (lower (has_type $F64 (fsub x y)))
2403
+ (x64_subsd x y))
2404
+ (rule (lower (has_type $F32X4 (fsub x y)))
2405
+ (x64_subps x y))
2406
+ (rule (lower (has_type $F64X2 (fsub x y)))
2407
+ (x64_subpd x y))
2408
+
2409
+ ;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2410
+
2411
+ (rule (lower (has_type $F32 (fmul x y)))
2412
+ (x64_mulss x y))
2413
+ (rule (lower (has_type $F64 (fmul x y)))
2414
+ (x64_mulsd x y))
2415
+ (rule (lower (has_type $F32X4 (fmul x y)))
2416
+ (x64_mulps x y))
2417
+ (rule (lower (has_type $F64X2 (fmul x y)))
2418
+ (x64_mulpd x y))
2419
+
2420
+ ;; The above rules automatically sink loads for rhs operands, so additionally
2421
+ ;; add rules for sinking loads with lhs operands.
2422
+ (rule 1 (lower (has_type $F32 (fmul (sinkable_load x) y)))
2423
+ (x64_mulss y x))
2424
+ (rule 1 (lower (has_type $F64 (fmul (sinkable_load x) y)))
2425
+ (x64_mulsd y x))
2426
+ (rule 1 (lower (has_type $F32X4 (fmul (sinkable_load x) y)))
2427
+ (x64_mulps y x))
2428
+ (rule 1 (lower (has_type $F64X2 (fmul (sinkable_load x) y)))
2429
+ (x64_mulpd y x))
2430
+
2431
+ ;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2432
+
2433
+ (rule (lower (has_type $F32 (fdiv x y)))
2434
+ (x64_divss x y))
2435
+ (rule (lower (has_type $F64 (fdiv x y)))
2436
+ (x64_divsd x y))
2437
+ (rule (lower (has_type $F32X4 (fdiv x y)))
2438
+ (x64_divps x y))
2439
+ (rule (lower (has_type $F64X2 (fdiv x y)))
2440
+ (x64_divpd x y))
2441
+
2442
+ ;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2443
+ (rule (lower (has_type $F32 (sqrt x)))
2444
+ (x64_sqrtss x))
2445
+ (rule (lower (has_type $F64 (sqrt x)))
2446
+ (x64_sqrtsd x))
2447
+ (rule (lower (has_type $F32X4 (sqrt x)))
2448
+ (x64_sqrtps x))
2449
+ (rule (lower (has_type $F64X2 (sqrt x)))
2450
+ (x64_sqrtpd x))
2451
+
2452
+ ;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2453
+ (rule (lower (has_type $F64 (fpromote x)))
2454
+ (x64_cvtss2sd x))
2455
+
2456
+ ;; Rules for `fvpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2457
+ (rule (lower (has_type $F64X2 (fvpromote_low x)))
2458
+ (x64_cvtps2pd (put_in_xmm x)))
2459
+
2460
+ ;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2461
+ (rule (lower (has_type $F32 (fdemote x)))
2462
+ (x64_cvtsd2ss x))
2463
+
2464
+ ;; Rules for `fvdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2465
+ (rule (lower (has_type $F32X4 (fvdemote x)))
2466
+ (x64_cvtpd2ps x))
2467
+
2468
+ ;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2469
+
2470
+ (rule (lower (has_type $F32 (fmin x y)))
2471
+ (xmm_min_max_seq $F32 $true x y))
2472
+ (rule (lower (has_type $F64 (fmin x y)))
2473
+ (xmm_min_max_seq $F64 $true x y))
2474
+
2475
+ ;; Vector-typed version. We don't use single pseudoinstructions as
2476
+ ;; above, because we don't need to generate a mini-CFG. Instead, we
2477
+ ;; perform a branchless series of operations.
2478
+ ;;
2479
+ ;; We cannot simply use native min instructions (minps, minpd) because
2480
+ ;; NaN handling is different per CLIF semantics than on
2481
+ ;; x86. Specifically, if an argument is NaN, or the arguments are both
2482
+ ;; zero but of opposite signs, then the x86 instruction always
2483
+ ;; produces the second argument. However, per CLIF semantics, we
2484
+ ;; require that fmin(NaN, _) = fmin(_, NaN) = NaN, and fmin(+0, -0) =
2485
+ ;; fmin(-0, +0) = -0.
2486
+
2487
+ (rule (lower (has_type $F32X4 (fmin x y)))
2488
+ ;; Compute min(x, y) and min(y, x) with native
2489
+ ;; instructions. These will differ in one of the edge cases
2490
+ ;; above that we have to handle properly. (Conversely, if they
2491
+ ;; don't differ, then the native instruction's answer is the
2492
+ ;; right one per CLIF semantics.)
2493
+ (let ((min1 Xmm (x64_minps x y))
2494
+ (min2 Xmm (x64_minps y x))
2495
+ ;; Compute the OR of the two. Note that NaNs have an
2496
+ ;; exponent field of all-ones (0xFF for F32), so if either
2497
+ ;; result is a NaN, this OR will be. And if either is a
2498
+ ;; zero (which has an exponent of 0 and mantissa of 0),
2499
+ ;; this captures a sign-bit of 1 (negative) if either
2500
+ ;; input is negative.
2501
+ ;;
2502
+ ;; In the case where we don't have a +/-0 mismatch or
2503
+ ;; NaNs, then `min1` and `min2` are equal and `min_or` is
2504
+ ;; the correct minimum.
2505
+ (min_or Xmm (x64_orps min1 min2))
2506
+ ;; "compare unordered" produces a true mask (all ones) in
2507
+ ;; a given lane if the min is a NaN. We use this to
2508
+ ;; generate a mask to ensure quiet NaNs.
2509
+ (is_nan_mask Xmm (x64_cmpps min_or min2 (FcmpImm.Unordered)))
2510
+ ;; OR in the NaN mask.
2511
+ (min_or_2 Xmm (x64_orps min_or is_nan_mask))
2512
+ ;; Shift the NaN mask down so that it covers just the
2513
+ ;; fraction below the NaN signalling bit; we'll use this
2514
+ ;; to mask off non-canonical NaN payloads.
2515
+ ;;
2516
+ ;; All-ones for NaN, shifted down to leave 10 top bits (1
2517
+ ;; sign, 8 exponent, 1 QNaN bit that must remain set)
2518
+ ;; cleared.
2519
+ (nan_fraction_mask Xmm (x64_psrld is_nan_mask (xmi_imm 10)))
2520
+ ;; Do a NAND, so that we retain every bit not set in
2521
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2522
+ ;; we retain every bit) in non-NaN cases, and will have
2523
+ ;; ones (so we clear those bits) in NaN-payload bits
2524
+ ;; otherwise.
2525
+ (final Xmm (x64_andnps nan_fraction_mask min_or_2)))
2526
+ final))
2527
+
2528
+ ;; Likewise for F64 lanes, except that the right-shift is by 13 bits
2529
+ ;; (1 sign, 11 exponent, 1 QNaN bit).
2530
+ (rule (lower (has_type $F64X2 (fmin x y)))
2531
+ (let ((min1 Xmm (x64_minpd x y))
2532
+ (min2 Xmm (x64_minpd y x))
2533
+ (min_or Xmm (x64_orpd min1 min2))
2534
+ (is_nan_mask Xmm (x64_cmppd min1 min2 (FcmpImm.Unordered)))
2535
+ (min_or_2 Xmm (x64_orpd min_or is_nan_mask))
2536
+ (nan_fraction_mask Xmm (x64_psrlq is_nan_mask (xmi_imm 13)))
2537
+ (final Xmm (x64_andnpd nan_fraction_mask min_or_2)))
2538
+ final))
2539
+
2540
+ ;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2541
+
2542
+ (rule (lower (has_type $F32 (fmax x y)))
2543
+ (xmm_min_max_seq $F32 $false x y))
2544
+ (rule (lower (has_type $F64 (fmax x y)))
2545
+ (xmm_min_max_seq $F64 $false x y))
2546
+
2547
+ ;; The vector version of fmax here is a dual to the fmin sequence
2548
+ ;; above, almost, with a few differences.
2549
+
2550
+ (rule (lower (has_type $F32X4 (fmax x y)))
2551
+ ;; Compute max(x, y) and max(y, x) with native
2552
+ ;; instructions. These will differ in one of the edge cases
2553
+ ;; above that we have to handle properly. (Conversely, if they
2554
+ ;; don't differ, then the native instruction's answer is the
2555
+ ;; right one per CLIF semantics.)
2556
+ (let ((max1 Xmm (x64_maxps x y))
2557
+ (max2 Xmm (x64_maxps y x))
2558
+ ;; Compute the XOR of the two maxima. In the case
2559
+ ;; where we don't have a +/-0 mismatch or NaNs, then
2560
+ ;; `min1` and `min2` are equal and this XOR is zero.
2561
+ (max_xor Xmm (x64_xorps max1 max2))
2562
+ ;; OR the XOR into one of the original maxima. If they are
2563
+ ;; equal, this does nothing. If max2 was NaN, its exponent
2564
+ ;; bits were all-ones, so the xor's exponent bits were the
2565
+ ;; complement of max1, and the OR of max1 and max_xor has
2566
+ ;; an all-ones exponent (is a NaN). If max1 was NaN, then
2567
+ ;; its exponent bits were already all-ones, so the OR will
2568
+ ;; be a NaN as well.
2569
+ (max_blended_nan Xmm (x64_orps max1 max_xor))
2570
+ ;; Subtract the XOR. This ensures that if we had +0 and
2571
+ ;; -0, we end up with +0.
2572
+ (max_blended_nan_positive Xmm (x64_subps max_blended_nan max_xor))
2573
+ ;; "compare unordered" produces a true mask (all ones) in
2574
+ ;; a given lane if the min is a NaN. We use this to
2575
+ ;; generate a mask to ensure quiet NaNs.
2576
+ (is_nan_mask Xmm (x64_cmpps max_blended_nan max_blended_nan (FcmpImm.Unordered)))
2577
+ ;; Shift the NaN mask down so that it covers just the
2578
+ ;; fraction below the NaN signalling bit; we'll use this
2579
+ ;; to mask off non-canonical NaN payloads.
2580
+ ;;
2581
+ ;; All-ones for NaN, shifted down to leave 10 top bits (1
2582
+ ;; sign, 8 exponent, 1 QNaN bit that must remain set)
2583
+ ;; cleared.
2584
+ (nan_fraction_mask Xmm (x64_psrld is_nan_mask (xmi_imm 10)))
2585
+ ;; Do a NAND, so that we retain every bit not set in
2586
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2587
+ ;; we retain every bit) in non-NaN cases, and will have
2588
+ ;; ones (so we clear those bits) in NaN-payload bits
2589
+ ;; otherwise.
2590
+ (final Xmm (x64_andnps nan_fraction_mask max_blended_nan_positive)))
2591
+ final))
2592
+
2593
+ (rule (lower (has_type $F64X2 (fmax x y)))
2594
+ ;; Compute max(x, y) and max(y, x) with native
2595
+ ;; instructions. These will differ in one of the edge cases
2596
+ ;; above that we have to handle properly. (Conversely, if they
2597
+ ;; don't differ, then the native instruction's answer is the
2598
+ ;; right one per CLIF semantics.)
2599
+ (let ((max1 Xmm (x64_maxpd x y))
2600
+ (max2 Xmm (x64_maxpd y x))
2601
+ ;; Compute the XOR of the two maxima. In the case
2602
+ ;; where we don't have a +/-0 mismatch or NaNs, then
2603
+ ;; `min1` and `min2` are equal and this XOR is zero.
2604
+ (max_xor Xmm (x64_xorpd max1 max2))
2605
+ ;; OR the XOR into one of the original maxima. If they are
2606
+ ;; equal, this does nothing. If max2 was NaN, its exponent
2607
+ ;; bits were all-ones, so the xor's exponent bits were the
2608
+ ;; complement of max1, and the OR of max1 and max_xor has
2609
+ ;; an all-ones exponent (is a NaN). If max1 was NaN, then
2610
+ ;; its exponent bits were already all-ones, so the OR will
2611
+ ;; be a NaN as well.
2612
+ (max_blended_nan Xmm (x64_orpd max1 max_xor))
2613
+ ;; Subtract the XOR. This ensures that if we had +0 and
2614
+ ;; -0, we end up with +0.
2615
+ (max_blended_nan_positive Xmm (x64_subpd max_blended_nan max_xor))
2616
+ ;; `cmpps` with predicate index `3` is `cmpunordps`, or
2617
+ ;; "compare unordered": it produces a true mask (all ones)
2618
+ ;; in a given lane if the min is a NaN. We use this to
2619
+ ;; generate a mask to ensure quiet NaNs.
2620
+ (is_nan_mask Xmm (x64_cmppd max_blended_nan max_blended_nan (FcmpImm.Unordered)))
2621
+ ;; Shift the NaN mask down so that it covers just the
2622
+ ;; fraction below the NaN signalling bit; we'll use this
2623
+ ;; to mask off non-canonical NaN payloads.
2624
+ ;;
2625
+ ;; All-ones for NaN, shifted down to leave 13 top bits (1
2626
+ ;; sign, 11 exponent, 1 QNaN bit that must remain set)
2627
+ ;; cleared.
2628
+ (nan_fraction_mask Xmm (x64_psrlq is_nan_mask (xmi_imm 13)))
2629
+ ;; Do a NAND, so that we retain every bit not set in
2630
+ ;; `nan_fraction_mask`. This mask will be all zeroes (so
2631
+ ;; we retain every bit) in non-NaN cases, and will have
2632
+ ;; ones (so we clear those bits) in NaN-payload bits
2633
+ ;; otherwise.
2634
+ (final Xmm (x64_andnpd nan_fraction_mask max_blended_nan_positive)))
2635
+ final))
2636
+
2637
+ ;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2638
+
2639
+ (rule (lower (has_type $F32 (fmin_pseudo x y)))
2640
+ (x64_minss y x))
2641
+ (rule (lower (has_type $F64 (fmin_pseudo x y)))
2642
+ (x64_minsd y x))
2643
+ (rule (lower (has_type $F32X4 (fmin_pseudo x y)))
2644
+ (x64_minps y x))
2645
+ (rule (lower (has_type $F64X2 (fmin_pseudo x y)))
2646
+ (x64_minpd y x))
2647
+
2648
+ ;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2649
+
2650
+ (rule (lower (has_type $F32 (fmax_pseudo x y)))
2651
+ (x64_maxss y x))
2652
+ (rule (lower (has_type $F64 (fmax_pseudo x y)))
2653
+ (x64_maxsd y x))
2654
+ (rule (lower (has_type $F32X4 (fmax_pseudo x y)))
2655
+ (x64_maxps y x))
2656
+ (rule (lower (has_type $F64X2 (fmax_pseudo x y)))
2657
+ (x64_maxpd y x))
2658
+
2659
+ ;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2660
+
2661
+ ;; Base case for fma is to call out to one of two libcalls. For vectors they
2662
+ ;; need to be decomposed, handle each element individually, and then recomposed.
2663
+
2664
+ (rule (lower (has_type $F32 (fma x y z)))
2665
+ (libcall_3 (LibCall.FmaF32) x y z))
2666
+ (rule (lower (has_type $F64 (fma x y z)))
2667
+ (libcall_3 (LibCall.FmaF64) x y z))
2668
+
2669
+ (rule (lower (has_type $F32X4 (fma x y z)))
2670
+ (let (
2671
+ (x Xmm (put_in_xmm x))
2672
+ (y Xmm (put_in_xmm y))
2673
+ (z Xmm (put_in_xmm z))
2674
+ (x0 Xmm (libcall_3 (LibCall.FmaF32) x y z))
2675
+ (x1 Xmm (libcall_3 (LibCall.FmaF32)
2676
+ (x64_pshufd x 1)
2677
+ (x64_pshufd y 1)
2678
+ (x64_pshufd z 1)))
2679
+ (x2 Xmm (libcall_3 (LibCall.FmaF32)
2680
+ (x64_pshufd x 2)
2681
+ (x64_pshufd y 2)
2682
+ (x64_pshufd z 2)))
2683
+ (x3 Xmm (libcall_3 (LibCall.FmaF32)
2684
+ (x64_pshufd x 3)
2685
+ (x64_pshufd y 3)
2686
+ (x64_pshufd z 3)))
2687
+
2688
+ (tmp Xmm (vec_insert_lane $F32X4 x0 x1 1))
2689
+ (tmp Xmm (vec_insert_lane $F32X4 tmp x2 2))
2690
+ (tmp Xmm (vec_insert_lane $F32X4 tmp x3 3))
2691
+ )
2692
+ tmp))
2693
+ (rule (lower (has_type $F64X2 (fma x y z)))
2694
+ (let (
2695
+ (x Xmm (put_in_xmm x))
2696
+ (y Xmm (put_in_xmm y))
2697
+ (z Xmm (put_in_xmm z))
2698
+ (x0 Xmm (libcall_3 (LibCall.FmaF64) x y z))
2699
+ (x1 Xmm (libcall_3 (LibCall.FmaF64)
2700
+ (x64_pshufd x 0xee)
2701
+ (x64_pshufd y 0xee)
2702
+ (x64_pshufd z 0xee)))
2703
+ )
2704
+ (vec_insert_lane $F64X2 x0 x1 1)))
2705
+
2706
+
2707
+ ;; Special case for when the `fma` feature is active and a native instruction
2708
+ ;; can be used.
2709
+ (rule 1 (lower (has_type ty (fma x y z)))
2710
+ (if-let $true (use_fma))
2711
+ (fmadd ty x y z))
2712
+
2713
+ (decl fmadd (Type Value Value Value) Xmm)
2714
+ (decl fnmadd (Type Value Value Value) Xmm)
2715
+
2716
+ ;; Base case. Note that this will automatically sink a load with `z`, the value
2717
+ ;; to add.
2718
+ (rule (fmadd ty x y z) (x64_vfmadd213 ty x y z))
2719
+
2720
+ ;; Allow sinking loads with one of the two values being multiplied in addition
2721
+ ;; to the value being added. Note that both x and y can be sunk here due to
2722
+ ;; multiplication being commutative.
2723
+ (rule 1 (fmadd ty (sinkable_load x) y z) (x64_vfmadd132 ty y z x))
2724
+ (rule 2 (fmadd ty x (sinkable_load y) z) (x64_vfmadd132 ty x z y))
2725
+
2726
+ ;; If one of the values being multiplied is negated then use a `vfnmadd*`
2727
+ ;; instruction instead
2728
+ (rule 3 (fmadd ty (fneg x) y z) (fnmadd ty x y z))
2729
+ (rule 4 (fmadd ty x (fneg y) z) (fnmadd ty x y z))
2730
+
2731
+ (rule (fnmadd ty x y z) (x64_vfnmadd213 ty x y z))
2732
+ (rule 1 (fnmadd ty (sinkable_load x) y z) (x64_vfnmadd132 ty y z x))
2733
+ (rule 2 (fnmadd ty x (sinkable_load y) z) (x64_vfnmadd132 ty x z y))
2734
+
2735
+ ;; Like `fmadd` if one argument is negated switch which one is being codegen'd
2736
+ (rule 3 (fnmadd ty (fneg x) y z) (fmadd ty x y z))
2737
+ (rule 4 (fnmadd ty x (fneg y) z) (fmadd ty x y z))
2738
+
2739
+ ;; Rules for `load*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2740
+
2741
+ ;; In order to load a value from memory to a GPR register, we may need to extend
2742
+ ;; the loaded value from 8-, 16-, or 32-bits to this backend's expected GPR
2743
+ ;; width: 64 bits. Note that `ext_mode` will load 1-bit types (booleans) as
2744
+ ;; 8-bit loads.
2745
+ ;;
2746
+ ;; By default, we zero-extend all sub-64-bit loads to a GPR.
2747
+ (rule -4 (lower (has_type (and (fits_in_32 ty) (is_gpr_type _)) (load flags address offset)))
2748
+ (x64_movzx (ext_mode (ty_bits_u16 ty) 64) (to_amode flags address offset)))
2749
+ ;; But if we know that both the `from` and `to` are 64 bits, we simply load with
2750
+ ;; no extension.
2751
+ (rule -1 (lower (has_type (ty_int_ref_64 ty) (load flags address offset)))
2752
+ (x64_mov (to_amode flags address offset)))
2753
+ ;; Also, certain scalar loads have a specific `from` width and extension kind
2754
+ ;; (signed -> `sx`, zeroed -> `zx`). We overwrite the high bits of the 64-bit
2755
+ ;; GPR even if the `to` type is smaller (e.g., 16-bits).
2756
+ (rule (lower (has_type (is_gpr_type ty) (uload8 flags address offset)))
2757
+ (x64_movzx (ExtMode.BQ) (to_amode flags address offset)))
2758
+ (rule (lower (has_type (is_gpr_type ty) (sload8 flags address offset)))
2759
+ (x64_movsx (ExtMode.BQ) (to_amode flags address offset)))
2760
+ (rule (lower (has_type (is_gpr_type ty) (uload16 flags address offset)))
2761
+ (x64_movzx (ExtMode.WQ) (to_amode flags address offset)))
2762
+ (rule (lower (has_type (is_gpr_type ty) (sload16 flags address offset)))
2763
+ (x64_movsx (ExtMode.WQ) (to_amode flags address offset)))
2764
+ (rule (lower (has_type (is_gpr_type ty) (uload32 flags address offset)))
2765
+ (x64_movzx (ExtMode.LQ) (to_amode flags address offset)))
2766
+ (rule (lower (has_type (is_gpr_type ty) (sload32 flags address offset)))
2767
+ (x64_movsx (ExtMode.LQ) (to_amode flags address offset)))
2768
+
2769
+ ;; To load to XMM registers, we use the x64-specific instructions for each type.
2770
+ ;; For `$F32` and `$F64` this is important--we only want to load 32 or 64 bits.
2771
+ ;; But for the 128-bit types, this is not strictly necessary for performance but
2772
+ ;; might help with clarity during disassembly.
2773
+ (rule (lower (has_type $F32 (load flags address offset)))
2774
+ (x64_movss_load (to_amode flags address offset)))
2775
+ (rule (lower (has_type $F64 (load flags address offset)))
2776
+ (x64_movsd_load (to_amode flags address offset)))
2777
+ (rule (lower (has_type $F32X4 (load flags address offset)))
2778
+ (x64_movups_load (to_amode flags address offset)))
2779
+ (rule (lower (has_type $F64X2 (load flags address offset)))
2780
+ (x64_movupd_load (to_amode flags address offset)))
2781
+ (rule -2 (lower (has_type (ty_vec128 ty) (load flags address offset)))
2782
+ (x64_movdqu_load (to_amode flags address offset)))
2783
+
2784
+ ;; We can load an I128 by doing two 64-bit loads.
2785
+ (rule -3 (lower (has_type $I128
2786
+ (load flags address offset)))
2787
+ (let ((addr_lo Amode (to_amode flags address offset))
2788
+ (addr_hi Amode (amode_offset addr_lo 8))
2789
+ (value_lo Reg (x64_mov addr_lo))
2790
+ (value_hi Reg (x64_mov addr_hi)))
2791
+ (value_regs value_lo value_hi)))
2792
+
2793
+ ;; We also include widening vector loads; these sign- or zero-extend each lane
2794
+ ;; to the next wider width (e.g., 16x4 -> 32x4).
2795
+ (rule 1 (lower (has_type $I16X8 (sload8x8 flags address offset)))
2796
+ (if-let $true (use_sse41))
2797
+ (x64_pmovsxbw (to_amode flags address offset)))
2798
+ (rule 1 (lower (has_type $I16X8 (uload8x8 flags address offset)))
2799
+ (if-let $true (use_sse41))
2800
+ (x64_pmovzxbw (to_amode flags address offset)))
2801
+ (rule 1 (lower (has_type $I32X4 (sload16x4 flags address offset)))
2802
+ (if-let $true (use_sse41))
2803
+ (x64_pmovsxwd (to_amode flags address offset)))
2804
+ (rule 1 (lower (has_type $I32X4 (uload16x4 flags address offset)))
2805
+ (if-let $true (use_sse41))
2806
+ (x64_pmovzxwd (to_amode flags address offset)))
2807
+ (rule 1 (lower (has_type $I64X2 (sload32x2 flags address offset)))
2808
+ (if-let $true (use_sse41))
2809
+ (x64_pmovsxdq (to_amode flags address offset)))
2810
+ (rule 1 (lower (has_type $I64X2 (uload32x2 flags address offset)))
2811
+ (if-let $true (use_sse41))
2812
+ (x64_pmovzxdq (to_amode flags address offset)))
2813
+
2814
+ (rule (lower (has_type $I16X8 (sload8x8 flags address offset)))
2815
+ (lower_swiden_low $I16X8 (x64_movq_to_xmm (to_amode flags address offset))))
2816
+ (rule (lower (has_type $I16X8 (uload8x8 flags address offset)))
2817
+ (lower_uwiden_low $I16X8 (x64_movq_to_xmm (to_amode flags address offset))))
2818
+ (rule (lower (has_type $I32X4 (sload16x4 flags address offset)))
2819
+ (lower_swiden_low $I32X4 (x64_movq_to_xmm (to_amode flags address offset))))
2820
+ (rule (lower (has_type $I32X4 (uload16x4 flags address offset)))
2821
+ (lower_uwiden_low $I32X4 (x64_movq_to_xmm (to_amode flags address offset))))
2822
+ (rule (lower (has_type $I64X2 (sload32x2 flags address offset)))
2823
+ (lower_swiden_low $I64X2 (x64_movq_to_xmm (to_amode flags address offset))))
2824
+ (rule (lower (has_type $I64X2 (uload32x2 flags address offset)))
2825
+ (lower_uwiden_low $I64X2 (x64_movq_to_xmm (to_amode flags address offset))))
2826
+
2827
+ ;; Rules for `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2828
+
2829
+ ;; 8-, 16-, 32- and 64-bit GPR stores.
2830
+ (rule -2 (lower (store flags
2831
+ value @ (value_type (is_gpr_type ty))
2832
+ address
2833
+ offset))
2834
+ (side_effect
2835
+ (x64_movrm ty (to_amode flags address offset) value)))
2836
+
2837
+ ;; Explicit 8/16/32-bit opcodes.
2838
+ (rule (lower (istore8 flags value address offset))
2839
+ (side_effect
2840
+ (x64_movrm $I8 (to_amode flags address offset) value)))
2841
+ (rule (lower (istore16 flags value address offset))
2842
+ (side_effect
2843
+ (x64_movrm $I16 (to_amode flags address offset) value)))
2844
+ (rule (lower (istore32 flags value address offset))
2845
+ (side_effect
2846
+ (x64_movrm $I32 (to_amode flags address offset) value)))
2847
+
2848
+ ;; F32 stores of values in XMM registers.
2849
+ (rule 1 (lower (store flags
2850
+ value @ (value_type $F32)
2851
+ address
2852
+ offset))
2853
+ (side_effect
2854
+ (x64_movss_store (to_amode flags address offset) value)))
2855
+
2856
+ ;; F64 stores of values in XMM registers.
2857
+ (rule 1 (lower (store flags
2858
+ value @ (value_type $F64)
2859
+ address
2860
+ offset))
2861
+ (side_effect
2862
+ (x64_movsd_store (to_amode flags address offset) value)))
2863
+
2864
+ ;; Stores of F32X4 vectors.
2865
+ (rule 1 (lower (store flags
2866
+ value @ (value_type $F32X4)
2867
+ address
2868
+ offset))
2869
+ (side_effect
2870
+ (x64_movups_store (to_amode flags address offset) value)))
2871
+
2872
+ ;; Stores of F64X2 vectors.
2873
+ (rule 1 (lower (store flags
2874
+ value @ (value_type $F64X2)
2875
+ address
2876
+ offset))
2877
+ (side_effect
2878
+ (x64_movupd_store (to_amode flags address offset) value)))
2879
+
2880
+ ;; Stores of all other 128-bit vector types with integer lanes.
2881
+ (rule -1 (lower (store flags
2882
+ value @ (value_type (ty_vec128_int _))
2883
+ address
2884
+ offset))
2885
+ (side_effect
2886
+ (x64_movdqu_store (to_amode flags address offset) value)))
2887
+
2888
+ ;; Stores of I128 values: store the two 64-bit halves separately.
2889
+ (rule 0 (lower (store flags
2890
+ value @ (value_type $I128)
2891
+ address
2892
+ offset))
2893
+ (let ((value_reg ValueRegs value)
2894
+ (value_lo Gpr (value_regs_get_gpr value_reg 0))
2895
+ (value_hi Gpr (value_regs_get_gpr value_reg 1))
2896
+ (addr_lo Amode (to_amode flags address offset))
2897
+ (addr_hi Amode (amode_offset addr_lo 8)))
2898
+ (side_effect
2899
+ (side_effect_concat
2900
+ (x64_movrm $I64 addr_lo value_lo)
2901
+ (x64_movrm $I64 addr_hi value_hi)))))
2902
+
2903
+ ;; Slightly optimize the extraction of the first lane from a vector which is
2904
+ ;; stored in memory. In the case the first lane specifically is selected the
2905
+ ;; standard `movss` and `movsd` instructions can be used as-if we're storing a
2906
+ ;; f32 or f64 despite the source perhaps being an integer vector since the
2907
+ ;; result of the instruction is the same.
2908
+ (rule 2 (lower (store flags
2909
+ (has_type $F32 (extractlane value (u8_from_uimm8 0)))
2910
+ address
2911
+ offset))
2912
+ (side_effect
2913
+ (x64_movss_store (to_amode flags address offset) value)))
2914
+ (rule 2 (lower (store flags
2915
+ (has_type $F64 (extractlane value (u8_from_uimm8 0)))
2916
+ address
2917
+ offset))
2918
+ (side_effect
2919
+ (x64_movsd_store (to_amode flags address offset) value)))
2920
+ (rule 2 (lower (store flags
2921
+ (has_type $I8 (extractlane value (u8_from_uimm8 n)))
2922
+ address
2923
+ offset))
2924
+ (if-let $true (use_sse41))
2925
+ (side_effect
2926
+ (x64_pextrb_store (to_amode flags address offset) value n)))
2927
+ (rule 2 (lower (store flags
2928
+ (has_type $I16 (extractlane value (u8_from_uimm8 n)))
2929
+ address
2930
+ offset))
2931
+ (side_effect
2932
+ (x64_pextrw_store (to_amode flags address offset) value n)))
2933
+ (rule 2 (lower (store flags
2934
+ (has_type $I32 (extractlane value (u8_from_uimm8 n)))
2935
+ address
2936
+ offset))
2937
+ (if-let $true (use_sse41))
2938
+ (side_effect
2939
+ (x64_pextrd_store (to_amode flags address offset) value n)))
2940
+ (rule 2 (lower (store flags
2941
+ (has_type $I64 (extractlane value (u8_from_uimm8 n)))
2942
+ address
2943
+ offset))
2944
+ (if-let $true (use_sse41))
2945
+ (side_effect
2946
+ (x64_pextrq_store (to_amode flags address offset) value n)))
2947
+
2948
+ ;; Rules for `load*` + ALU op + `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2949
+
2950
+ ;; Add mem, reg
2951
+ (rule 3 (lower
2952
+ (store flags
2953
+ (has_type (ty_32_or_64 ty)
2954
+ (iadd (and
2955
+ (sinkable_load sink)
2956
+ (load flags addr offset))
2957
+ src2))
2958
+ addr
2959
+ offset))
2960
+ (let ((_ RegMemImm sink))
2961
+ (side_effect
2962
+ (x64_add_mem ty (to_amode flags addr offset) src2))))
2963
+
2964
+ ;; Add mem, reg with args swapped
2965
+ (rule 2 (lower
2966
+ (store flags
2967
+ (has_type (ty_32_or_64 ty)
2968
+ (iadd src2
2969
+ (and
2970
+ (sinkable_load sink)
2971
+ (load flags addr offset))))
2972
+ addr
2973
+ offset))
2974
+ (let ((_ RegMemImm sink))
2975
+ (side_effect
2976
+ (x64_add_mem ty (to_amode flags addr offset) src2))))
2977
+
2978
+ ;; Sub mem, reg
2979
+ (rule 2 (lower
2980
+ (store flags
2981
+ (has_type (ty_32_or_64 ty)
2982
+ (isub (and
2983
+ (sinkable_load sink)
2984
+ (load flags addr offset))
2985
+ src2))
2986
+ addr
2987
+ offset))
2988
+ (let ((_ RegMemImm sink))
2989
+ (side_effect
2990
+ (x64_sub_mem ty (to_amode flags addr offset) src2))))
2991
+
2992
+ ;; And mem, reg
2993
+ (rule 3 (lower
2994
+ (store flags
2995
+ (has_type (ty_32_or_64 ty)
2996
+ (band (and
2997
+ (sinkable_load sink)
2998
+ (load flags addr offset))
2999
+ src2))
3000
+ addr
3001
+ offset))
3002
+ (let ((_ RegMemImm sink))
3003
+ (side_effect
3004
+ (x64_and_mem ty (to_amode flags addr offset) src2))))
3005
+
3006
+ ;; And mem, reg with args swapped
3007
+ (rule 2 (lower
3008
+ (store flags
3009
+ (has_type (ty_32_or_64 ty)
3010
+ (band src2
3011
+ (and
3012
+ (sinkable_load sink)
3013
+ (load flags addr offset))))
3014
+ addr
3015
+ offset))
3016
+ (let ((_ RegMemImm sink))
3017
+ (side_effect
3018
+ (x64_and_mem ty (to_amode flags addr offset) src2))))
3019
+
3020
+ ;; Or mem, reg
3021
+ (rule 3 (lower
3022
+ (store flags
3023
+ (has_type (ty_32_or_64 ty)
3024
+ (bor (and
3025
+ (sinkable_load sink)
3026
+ (load flags addr offset))
3027
+ src2))
3028
+ addr
3029
+ offset))
3030
+ (let ((_ RegMemImm sink))
3031
+ (side_effect
3032
+ (x64_or_mem ty (to_amode flags addr offset) src2))))
3033
+
3034
+ ;; Or mem, reg with args swapped
3035
+ (rule 2 (lower
3036
+ (store flags
3037
+ (has_type (ty_32_or_64 ty)
3038
+ (bor src2
3039
+ (and
3040
+ (sinkable_load sink)
3041
+ (load flags addr offset))))
3042
+ addr
3043
+ offset))
3044
+ (let ((_ RegMemImm sink))
3045
+ (side_effect
3046
+ (x64_or_mem ty (to_amode flags addr offset) src2))))
3047
+
3048
+ ;; Xor mem, reg
3049
+ (rule 3 (lower
3050
+ (store flags
3051
+ (has_type (ty_32_or_64 ty)
3052
+ (bxor (and
3053
+ (sinkable_load sink)
3054
+ (load flags addr offset))
3055
+ src2))
3056
+ addr
3057
+ offset))
3058
+ (let ((_ RegMemImm sink))
3059
+ (side_effect
3060
+ (x64_xor_mem ty (to_amode flags addr offset) src2))))
3061
+
3062
+ ;; Xor mem, reg with args swapped
3063
+ (rule 2 (lower
3064
+ (store flags
3065
+ (has_type (ty_32_or_64 ty)
3066
+ (bxor src2
3067
+ (and
3068
+ (sinkable_load sink)
3069
+ (load flags addr offset))))
3070
+ addr
3071
+ offset))
3072
+ (let ((_ RegMemImm sink))
3073
+ (side_effect
3074
+ (x64_xor_mem ty (to_amode flags addr offset) src2))))
3075
+
3076
+ ;; Rules for `fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3077
+
3078
+ (rule (lower (fence))
3079
+ (side_effect (x64_mfence)))
3080
+
3081
+ ;; Rules for `func_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3082
+
3083
+ (rule (lower (func_addr (func_ref_data _ extname dist)))
3084
+ (load_ext_name extname 0 dist))
3085
+
3086
+ ;; Rules for `symbol_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3087
+
3088
+ (rule (lower (symbol_value (symbol_value_data extname dist offset)))
3089
+ (load_ext_name extname offset dist))
3090
+
3091
+ ;; Rules for `atomic_load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3092
+
3093
+ ;; This is a normal load. The x86-TSO memory model provides sufficient
3094
+ ;; sequencing to satisfy the CLIF synchronisation requirements for `AtomicLoad`
3095
+ ;; without the need for any fence instructions.
3096
+ ;;
3097
+ ;; As described in the `atomic_load` documentation, this lowering is only valid
3098
+ ;; for I8, I16, I32, and I64. The sub-64-bit types are zero extended, as with a
3099
+ ;; normal load.
3100
+ (rule 1 (lower (has_type $I64 (atomic_load flags address)))
3101
+ (x64_mov (to_amode flags address (zero_offset))))
3102
+ (rule (lower (has_type (and (fits_in_32 ty) (ty_int _)) (atomic_load flags address)))
3103
+ (x64_movzx (ext_mode (ty_bits_u16 ty) 64) (to_amode flags address (zero_offset))))
3104
+
3105
+ ;; Rules for `atomic_store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3106
+
3107
+ ;; This is a normal store followed by an `mfence` instruction. As described in
3108
+ ;; the `atomic_load` documentation, this lowering is only valid for I8, I16,
3109
+ ;; I32, and I64.
3110
+ (rule (lower (atomic_store flags
3111
+ value @ (value_type (and (fits_in_64 ty) (ty_int _)))
3112
+ address))
3113
+ (side_effect (side_effect_concat
3114
+ (x64_movrm ty (to_amode flags address (zero_offset)) value)
3115
+ (x64_mfence))))
3116
+
3117
+ ;; Rules for `atomic_cas` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3118
+
3119
+ (rule (lower (has_type (and (fits_in_64 ty) (ty_int _))
3120
+ (atomic_cas flags address expected replacement)))
3121
+ (x64_cmpxchg ty expected replacement (to_amode flags address (zero_offset))))
3122
+
3123
+ ;; Rules for `atomic_rmw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3124
+
3125
+ ;; This is a simple, general-case atomic update, based on a loop involving
3126
+ ;; `cmpxchg`. Note that we could do much better than this in the case where the
3127
+ ;; old value at the location (that is to say, the SSA `Value` computed by this
3128
+ ;; CLIF instruction) is not required. In that case, we could instead implement
3129
+ ;; this using a single `lock`-prefixed x64 read-modify-write instruction. Also,
3130
+ ;; even in the case where the old value is required, for the `add` and `sub`
3131
+ ;; cases, we can use the single instruction `lock xadd`. However, those
3132
+ ;; improvements have been left for another day. TODO: filed as
3133
+ ;; https://github.com/bytecodealliance/wasmtime/issues/2153.
3134
+
3135
+ (rule (lower (has_type (and (fits_in_64 ty) (ty_int _))
3136
+ (atomic_rmw flags op address input)))
3137
+ (x64_atomic_rmw_seq ty op (to_amode flags address (zero_offset)) input))
3138
+
3139
+ ;; Rules for `call` and `call_indirect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3140
+
3141
+ (rule (lower (call (func_ref_data sig_ref extname dist) inputs))
3142
+ (gen_call sig_ref extname dist inputs))
3143
+
3144
+ (rule (lower (call_indirect sig_ref val inputs))
3145
+ (gen_call_indirect sig_ref val inputs))
3146
+
3147
+ ;;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;
3148
+
3149
+ (rule (lower (get_frame_pointer))
3150
+ (x64_rbp))
3151
+
3152
+ (rule (lower (get_stack_pointer))
3153
+ (x64_rsp))
3154
+
3155
+ (rule (lower (get_return_address))
3156
+ (x64_load $I64
3157
+ (Amode.ImmReg 8 (x64_rbp) (mem_flags_trusted))
3158
+ (ExtKind.None)))
3159
+
3160
+ ;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3161
+
3162
+ (rule (lower_branch (jump _) (single_target target))
3163
+ (emit_side_effect (jmp_known target)))
3164
+
3165
+ ;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3166
+
3167
+ (rule 2 (lower_branch (brif (maybe_uextend (icmp cc a b)) _ _) (two_targets then else))
3168
+ (emit_side_effect (jmp_cond_icmp (emit_cmp cc a b) then else)))
3169
+
3170
+ (rule 2 (lower_branch (brif (maybe_uextend (fcmp cc a b)) _ _) (two_targets then else))
3171
+ (emit_side_effect (jmp_cond_fcmp (emit_fcmp cc a b) then else)))
3172
+
3173
+ (rule 1 (lower_branch (brif val @ (value_type $I128) _ _)
3174
+ (two_targets then else))
3175
+ (emit_side_effect (jmp_cond_icmp (cmp_zero_i128 (CC.Z) val) then else)))
3176
+
3177
+ (rule (lower_branch (brif val @ (value_type (ty_int_bool_or_ref)) _ _)
3178
+ (two_targets then else))
3179
+ (emit_side_effect (with_flags_side_effect
3180
+ (cmp_zero_int_bool_ref val)
3181
+ (jmp_cond (CC.NZ) then else))))
3182
+
3183
+
3184
+ ;; Compare an I128 value to zero, returning a flags result suitable for making a
3185
+ ;; jump decision. The comparison is implemented as `(hi == 0) && (low == 0)`,
3186
+ ;; and the result can be interpreted as follows
3187
+ ;; * CC.Z indicates that the value was non-zero, as one or both of the halves of
3188
+ ;; the value were non-zero
3189
+ ;; * CC.NZ indicates that both halves of the value were 0
3190
+ (decl cmp_zero_i128 (CC ValueRegs) IcmpCondResult)
3191
+ (rule (cmp_zero_i128 (cc_nz_or_z cc) val)
3192
+ (let ((lo Gpr (value_regs_get_gpr val 0))
3193
+ (hi Gpr (value_regs_get_gpr val 1))
3194
+ (lo_z Gpr (with_flags_reg (x64_cmp (OperandSize.Size64) (RegMemImm.Imm 0) lo)
3195
+ (x64_setcc (CC.Z))))
3196
+ (hi_z Gpr (with_flags_reg (x64_cmp (OperandSize.Size64) (RegMemImm.Imm 0) hi)
3197
+ (x64_setcc (CC.Z)))))
3198
+ (icmp_cond_result (x64_test (OperandSize.Size8) lo_z hi_z) cc)))
3199
+
3200
+
3201
+ (decl cmp_zero_int_bool_ref (Value) ProducesFlags)
3202
+ (rule (cmp_zero_int_bool_ref val @ (value_type ty))
3203
+ (let ((size OperandSize (raw_operand_size_of_type ty))
3204
+ (src Gpr val))
3205
+ (x64_test size src src)))
3206
+
3207
+ ;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3208
+
3209
+ (rule (lower_branch (br_table idx @ (value_type ty) _) (jump_table_targets default_target jt_targets))
3210
+ (let ((size OperandSize (raw_operand_size_of_type ty))
3211
+ (jt_size u32 (jump_table_size jt_targets))
3212
+ (size_reg Reg (imm ty (u32_as_u64 jt_size)))
3213
+ (idx_reg Gpr (extend_to_gpr idx $I64 (ExtendKind.Zero)))
3214
+ (clamped_idx Reg (with_flags_reg
3215
+ (x64_cmp size size_reg idx_reg)
3216
+ (cmove ty (CC.B) idx_reg size_reg))))
3217
+ (emit_side_effect (jmp_table_seq ty clamped_idx default_target jt_targets))))
3218
+
3219
+ ;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3220
+
3221
+ (rule (lower (select_spectre_guard (icmp cc a b) x y))
3222
+ (select_icmp (emit_cmp cc a b) x y))
3223
+
3224
+ (rule -1 (lower (has_type ty (select_spectre_guard c @ (value_type (fits_in_64 a_ty)) x y)))
3225
+ (let ((size OperandSize (raw_operand_size_of_type a_ty))
3226
+ (gpr_c Gpr (put_in_gpr c)))
3227
+ (with_flags (x64_test size gpr_c gpr_c) (cmove_from_values ty (CC.NZ) x y))))
3228
+
3229
+ (rule -2 (lower (has_type ty (select_spectre_guard c @ (value_type $I128) x y)))
3230
+ (let ((cond_result IcmpCondResult (cmp_zero_i128 (CC.Z) c)))
3231
+ (select_icmp cond_result x y)))
3232
+
3233
+ ;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3234
+
3235
+ (rule 2 (lower (has_type $F32 (fcvt_from_sint a @ (value_type $I8))))
3236
+ (x64_cvtsi2ss $I32 (extend_to_gpr a $I32 (ExtendKind.Sign))))
3237
+
3238
+ (rule 2 (lower (has_type $F32 (fcvt_from_sint a @ (value_type $I16))))
3239
+ (x64_cvtsi2ss $I32 (extend_to_gpr a $I32 (ExtendKind.Sign))))
3240
+
3241
+ (rule 1 (lower (has_type $F32 (fcvt_from_sint a @ (value_type (ty_int (fits_in_64 ty))))))
3242
+ (x64_cvtsi2ss ty a))
3243
+
3244
+ (rule 2 (lower (has_type $F64 (fcvt_from_sint a @ (value_type $I8))))
3245
+ (x64_cvtsi2sd $I32 (extend_to_gpr a $I32 (ExtendKind.Sign))))
3246
+
3247
+ (rule 2 (lower (has_type $F64 (fcvt_from_sint a @ (value_type $I16))))
3248
+ (x64_cvtsi2sd $I32 (extend_to_gpr a $I32 (ExtendKind.Sign))))
3249
+
3250
+ (rule 1 (lower (has_type $F64 (fcvt_from_sint a @ (value_type (ty_int (fits_in_64 ty))))))
3251
+ (x64_cvtsi2sd ty a))
3252
+
3253
+ (rule 0 (lower (fcvt_from_sint a @ (value_type $I32X4)))
3254
+ (x64_cvtdq2ps a))
3255
+
3256
+ ;; Rules for `fcvt_low_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3257
+
3258
+ (rule (lower (fcvt_low_from_sint a))
3259
+ (x64_cvtdq2pd a))
3260
+
3261
+ ;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3262
+
3263
+ (rule 1 (lower (has_type $F32 (fcvt_from_uint val @ (value_type (fits_in_32 (ty_int ty))))))
3264
+ (x64_cvtsi2ss $I64 (extend_to_gpr val $I64 (ExtendKind.Zero))))
3265
+
3266
+ (rule 1 (lower (has_type $F64 (fcvt_from_uint val @ (value_type (fits_in_32 (ty_int ty))))))
3267
+ (x64_cvtsi2sd $I64 (extend_to_gpr val $I64 (ExtendKind.Zero))))
3268
+
3269
+ (rule (lower (has_type ty (fcvt_from_uint val @ (value_type $I64))))
3270
+ (cvt_u64_to_float_seq ty val))
3271
+
3272
+ ;; Algorithm uses unpcklps to help create a float that is equivalent
3273
+ ;; 0x1.0p52 + double(src). 0x1.0p52 is unique because at this exponent
3274
+ ;; every value of the mantissa represents a corresponding uint32 number.
3275
+ ;; When we subtract 0x1.0p52 we are left with double(src).
3276
+ (rule 1 (lower (has_type $F64X2 (fcvt_from_uint (uwiden_low val @ (value_type $I32X4)))))
3277
+ (let ((uint_mask XmmMem (fcvt_uint_mask_const))
3278
+ (res Xmm (x64_unpcklps val uint_mask))
3279
+ (uint_mask_high XmmMem (fcvt_uint_mask_high_const)))
3280
+ (x64_subpd res uint_mask_high)))
3281
+
3282
+ ;; When AVX512VL and AVX512F are available,
3283
+ ;; `fcvt_from_uint` can be lowered to a single instruction.
3284
+ (rule 2 (lower (has_type $F32X4 (fcvt_from_uint src)))
3285
+ (if-let $true (use_avx512vl_simd))
3286
+ (if-let $true (use_avx512f_simd))
3287
+ (x64_vcvtudq2ps src))
3288
+
3289
+ ;; Converting packed unsigned integers to packed floats
3290
+ ;; requires a few steps. There is no single instruction
3291
+ ;; lowering for converting unsigned floats but there is for
3292
+ ;; converting packed signed integers to float (cvtdq2ps). In
3293
+ ;; the steps below we isolate the upper half (16 bits) and
3294
+ ;; lower half (16 bits) of each lane and then we convert
3295
+ ;; each half separately using cvtdq2ps meant for signed
3296
+ ;; integers. In order for this to work for the upper half
3297
+ ;; bits we must shift right by 1 (divide by 2) these bits in
3298
+ ;; order to ensure the most significant bit is 0 not signed,
3299
+ ;; and then after the conversion we double the value.
3300
+ ;; Finally we add the converted values where addition will
3301
+ ;; correctly round.
3302
+ ;;
3303
+ ;; Sequence:
3304
+ ;; -> A = 0xffffffff
3305
+ ;; -> Ah = 0xffff0000
3306
+ ;; -> Al = 0x0000ffff
3307
+ ;; -> Convert(Al) // Convert int to float
3308
+ ;; -> Ah = Ah >> 1 // Shift right 1 to assure Ah conversion isn't treated as signed
3309
+ ;; -> Convert(Ah) // Convert .. with no loss of significant digits from previous shift
3310
+ ;; -> Ah = Ah + Ah // Double Ah to account for shift right before the conversion.
3311
+ ;; -> dst = Ah + Al // Add the two floats together
3312
+ (rule 1 (lower (has_type $F32X4 (fcvt_from_uint val)))
3313
+ (let ((a Xmm val)
3314
+
3315
+ ;; get the low 16 bits
3316
+ (a_lo Xmm (x64_pslld a (xmi_imm 16)))
3317
+ (a_lo Xmm (x64_psrld a_lo (xmi_imm 16)))
3318
+
3319
+ ;; get the high 16 bits
3320
+ (a_hi Xmm (x64_psubd a a_lo))
3321
+
3322
+ ;; convert the low 16 bits
3323
+ (a_lo Xmm (x64_cvtdq2ps a_lo))
3324
+
3325
+ ;; shift the high bits by 1, convert, and double to get the correct
3326
+ ;; value
3327
+ (a_hi Xmm (x64_psrld a_hi (xmi_imm 1)))
3328
+ (a_hi Xmm (x64_cvtdq2ps a_hi))
3329
+ (a_hi Xmm (x64_addps a_hi a_hi)))
3330
+
3331
+ ;; add together the two converted values
3332
+ (x64_addps a_hi a_lo)))
3333
+
3334
+ ;; Rules for `fcvt_to_uint` and `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3335
+
3336
+ (rule (lower (has_type out_ty (fcvt_to_uint val @ (value_type (ty_scalar_float _)))))
3337
+ (cvt_float_to_uint_seq out_ty val $false))
3338
+
3339
+ (rule (lower (has_type out_ty (fcvt_to_uint_sat val @ (value_type (ty_scalar_float _)))))
3340
+ (cvt_float_to_uint_seq out_ty val $true))
3341
+
3342
+ (rule (lower (has_type out_ty (fcvt_to_sint val @ (value_type (ty_scalar_float _)))))
3343
+ (cvt_float_to_sint_seq out_ty val $false))
3344
+
3345
+ (rule (lower (has_type out_ty (fcvt_to_sint_sat val @ (value_type (ty_scalar_float _)))))
3346
+ (cvt_float_to_sint_seq out_ty val $true))
3347
+
3348
+ ;; The x64 backend currently only supports these two type combinations.
3349
+ (rule 1 (lower (has_type $I32X4 (fcvt_to_sint_sat val @ (value_type $F32X4))))
3350
+ (let ((src Xmm val)
3351
+
3352
+ ;; Sets tmp to zero if float is NaN
3353
+ (tmp Xmm (x64_cmpps src src (FcmpImm.Equal)))
3354
+ (dst Xmm (x64_andps src tmp))
3355
+
3356
+ ;; Sets top bit of tmp if float is positive
3357
+ ;; Setting up to set top bit on negative float values
3358
+ (tmp Xmm (x64_pxor tmp dst))
3359
+
3360
+ ;; Convert the packed float to packed doubleword.
3361
+ (dst Xmm (x64_cvttps2dq dst))
3362
+
3363
+ ;; Set top bit only if < 0
3364
+ (tmp Xmm (x64_pand dst tmp))
3365
+ (tmp Xmm (x64_psrad tmp (xmi_imm 31))))
3366
+
3367
+ ;; On overflow 0x80000000 is returned to a lane.
3368
+ ;; Below sets positive overflow lanes to 0x7FFFFFFF
3369
+ ;; Keeps negative overflow lanes as is.
3370
+ (x64_pxor tmp dst)))
3371
+
3372
+ ;; The algorithm for converting floats to unsigned ints is a little tricky. The
3373
+ ;; complication arises because we are converting from a signed 64-bit int with a positive
3374
+ ;; integer range from 1..INT_MAX (0x1..0x7FFFFFFF) to an unsigned integer with an extended
3375
+ ;; range from (INT_MAX+1)..UINT_MAX. It's this range from (INT_MAX+1)..UINT_MAX
3376
+ ;; (0x80000000..0xFFFFFFFF) that needs to be accounted for as a special case since our
3377
+ ;; conversion instruction (cvttps2dq) only converts as high as INT_MAX (0x7FFFFFFF), but
3378
+ ;; which conveniently setting underflows and overflows (smaller than MIN_INT or larger than
3379
+ ;; MAX_INT) to be INT_MAX+1 (0x80000000). Nothing that the range (INT_MAX+1)..UINT_MAX includes
3380
+ ;; precisely INT_MAX values we can correctly account for and convert every value in this range
3381
+ ;; if we simply subtract INT_MAX+1 before doing the cvttps2dq conversion. After the subtraction
3382
+ ;; every value originally (INT_MAX+1)..UINT_MAX is now the range (0..INT_MAX).
3383
+ ;; After the conversion we add INT_MAX+1 back to this converted value, noting again that
3384
+ ;; values we are trying to account for were already set to INT_MAX+1 during the original conversion.
3385
+ ;; We simply have to create a mask and make sure we are adding together only the lanes that need
3386
+ ;; to be accounted for. Digesting it all the steps then are:
3387
+ ;;
3388
+ ;; Step 1 - Account for NaN and negative floats by setting these src values to zero.
3389
+ ;; Step 2 - Make a copy (tmp1) of the src value since we need to convert twice for
3390
+ ;; reasons described above.
3391
+ ;; Step 3 - Convert the original src values. This will convert properly all floats up to INT_MAX
3392
+ ;; Step 4 - Subtract INT_MAX from the copy set (tmp1). Note, all zero and negative values are those
3393
+ ;; values that were originally in the range (0..INT_MAX). This will come in handy during
3394
+ ;; step 7 when we zero negative lanes.
3395
+ ;; Step 5 - Create a bit mask for tmp1 that will correspond to all lanes originally less than
3396
+ ;; UINT_MAX that are now less than INT_MAX thanks to the subtraction.
3397
+ ;; Step 6 - Convert the second set of values (tmp1)
3398
+ ;; Step 7 - Prep the converted second set by zeroing out negative lanes (these have already been
3399
+ ;; converted correctly with the first set) and by setting overflow lanes to 0x7FFFFFFF
3400
+ ;; as this will allow us to properly saturate overflow lanes when adding to 0x80000000
3401
+ ;; Step 8 - Add the orginal converted src and the converted tmp1 where float values originally less
3402
+ ;; than and equal to INT_MAX will be unchanged, float values originally between INT_MAX+1 and
3403
+ ;; UINT_MAX will add together (INT_MAX) + (SRC - INT_MAX), and float values originally
3404
+ ;; greater than UINT_MAX will be saturated to UINT_MAX (0xFFFFFFFF) after adding (0x8000000 + 0x7FFFFFFF).
3405
+ ;;
3406
+ ;;
3407
+ ;; The table below illustrates the result after each step where it matters for the converted set.
3408
+ ;; Note the original value range (original src set) is the final dst in Step 8:
3409
+ ;;
3410
+ ;; Original src set:
3411
+ ;; | Original Value Range | Step 1 | Step 3 | Step 8 |
3412
+ ;; | -FLT_MIN..FLT_MAX | 0.0..FLT_MAX | 0..INT_MAX(w/overflow) | 0..UINT_MAX(w/saturation) |
3413
+ ;;
3414
+ ;; Copied src set (tmp1):
3415
+ ;; | Step 2 | Step 4 |
3416
+ ;; | 0.0..FLT_MAX | (0.0-(INT_MAX+1))..(FLT_MAX-(INT_MAX+1)) |
3417
+ ;;
3418
+ ;; | Step 6 | Step 7 |
3419
+ ;; | (0-(INT_MAX+1))..(UINT_MAX-(INT_MAX+1))(w/overflow) | ((INT_MAX+1)-(INT_MAX+1))..(INT_MAX+1) |
3420
+ (rule 1 (lower (has_type $I32X4 (fcvt_to_uint_sat val @ (value_type $F32X4))))
3421
+ (let ((src Xmm val)
3422
+
3423
+ ;; Converting to unsigned int so if float src is negative or NaN
3424
+ ;; will first set to zero.
3425
+ (tmp2 Xmm (xmm_zero $F32X4))
3426
+ (dst Xmm (x64_maxps src tmp2))
3427
+
3428
+ ;; Set tmp2 to INT_MAX+1. It is important to note here that after it looks
3429
+ ;; like we are only converting INT_MAX (0x7FFFFFFF) but in fact because
3430
+ ;; single precision IEEE-754 floats can only accurately represent contingous
3431
+ ;; integers up to 2^23 and outside of this range it rounds to the closest
3432
+ ;; integer that it can represent. In the case of INT_MAX, this value gets
3433
+ ;; represented as 0x4f000000 which is the integer value (INT_MAX+1).
3434
+ (tmp2 Xmm (x64_pcmpeqd tmp2 tmp2))
3435
+ (tmp2 Xmm (x64_psrld tmp2 (xmi_imm 1)))
3436
+ (tmp2 Xmm (x64_cvtdq2ps tmp2))
3437
+
3438
+ ;; Make a copy of these lanes and then do the first conversion.
3439
+ ;; Overflow lanes greater than the maximum allowed signed value will
3440
+ ;; set to 0x80000000. Negative and NaN lanes will be 0x0
3441
+ (tmp1 Xmm dst)
3442
+ (dst Xmm (x64_cvttps2dq dst))
3443
+
3444
+ ;; Set lanes to src - max_signed_int
3445
+ (tmp1 Xmm (x64_subps tmp1 tmp2))
3446
+
3447
+ ;; Create mask for all positive lanes to saturate (i.e. greater than
3448
+ ;; or equal to the maxmimum allowable unsigned int).
3449
+ (tmp2 Xmm (x64_cmpps tmp2 tmp1 (FcmpImm.LessThanOrEqual)))
3450
+
3451
+ ;; Convert those set of lanes that have the max_signed_int factored out.
3452
+ (tmp1 Xmm (x64_cvttps2dq tmp1))
3453
+
3454
+ ;; Prepare converted lanes by zeroing negative lanes and prepping lanes
3455
+ ;; that have positive overflow (based on the mask) by setting these lanes
3456
+ ;; to 0x7FFFFFFF
3457
+ (tmp1 Xmm (x64_pxor tmp1 tmp2))
3458
+ (tmp2 Xmm (xmm_zero $I32X4))
3459
+ (tmp1 Xmm (lower_vec_smax $I32X4 tmp1 tmp2)))
3460
+
3461
+ ;; Add this second set of converted lanes to the original to properly handle
3462
+ ;; values greater than max signed int.
3463
+ (x64_paddd tmp1 dst)))
3464
+
3465
+ ;; Rules for `x86_cvtt2dq` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3466
+
3467
+ (rule (lower (has_type $I32X4 (x86_cvtt2dq val @ (value_type $F32X4))))
3468
+ (x64_cvttps2dq val))
3469
+
3470
+ ;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3471
+
3472
+ (rule (lower (has_type $I16X8 (iadd_pairwise x y)))
3473
+ (x64_phaddw x y))
3474
+
3475
+ (rule (lower (has_type $I32X4 (iadd_pairwise x y)))
3476
+ (x64_phaddd x y))
3477
+
3478
+ ;; special case for the `i16x8.extadd_pairwise_i8x16_s` wasm instruction
3479
+ (rule 1 (lower
3480
+ (has_type $I16X8 (iadd_pairwise
3481
+ (swiden_low val @ (value_type $I8X16))
3482
+ (swiden_high val))))
3483
+ (let ((mul_const Xmm (x64_xmm_load_const $I8X16 (iadd_pairwise_mul_const_16))))
3484
+ (x64_pmaddubsw mul_const val)))
3485
+
3486
+ ;; special case for the `i32x4.extadd_pairwise_i16x8_s` wasm instruction
3487
+ (rule 1 (lower
3488
+ (has_type $I32X4 (iadd_pairwise
3489
+ (swiden_low val @ (value_type $I16X8))
3490
+ (swiden_high val))))
3491
+ (let ((mul_const XmmMem (iadd_pairwise_mul_const_32)))
3492
+ (x64_pmaddwd val mul_const)))
3493
+
3494
+ ;; special case for the `i16x8.extadd_pairwise_i8x16_u` wasm instruction
3495
+ (rule 1 (lower
3496
+ (has_type $I16X8 (iadd_pairwise
3497
+ (uwiden_low val @ (value_type $I8X16))
3498
+ (uwiden_high val))))
3499
+ (let ((mul_const XmmMem (iadd_pairwise_mul_const_16)))
3500
+ (x64_pmaddubsw val mul_const)))
3501
+
3502
+ ;; special case for the `i32x4.extadd_pairwise_i16x8_u` wasm instruction
3503
+ (rule 1 (lower
3504
+ (has_type $I32X4 (iadd_pairwise
3505
+ (uwiden_low val @ (value_type $I16X8))
3506
+ (uwiden_high val))))
3507
+ (let ((xor_const XmmMem (iadd_pairwise_xor_const_32))
3508
+ (dst Xmm (x64_pxor val xor_const))
3509
+
3510
+ (madd_const XmmMem (iadd_pairwise_mul_const_32))
3511
+ (dst Xmm (x64_pmaddwd dst madd_const))
3512
+
3513
+ (addd_const XmmMem (iadd_pairwise_addd_const_32)))
3514
+ (x64_paddd dst addd_const)))
3515
+
3516
+ ;; special case for the `i32x4.dot_i16x8_s` wasm instruction
3517
+ (rule 1 (lower
3518
+ (has_type $I32X4 (iadd_pairwise
3519
+ (imul (swiden_low x) (swiden_low y))
3520
+ (imul (swiden_high x) (swiden_high y)))))
3521
+ (x64_pmaddwd x y))
3522
+
3523
+ ;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3524
+
3525
+ ;; With SSE4.1 use the `pmovsx*` instructions for this
3526
+ (rule 1 (lower (has_type $I16X8 (swiden_low val @ (value_type $I8X16))))
3527
+ (if-let $true (use_sse41))
3528
+ (x64_pmovsxbw val))
3529
+ (rule 1 (lower (has_type $I32X4 (swiden_low val @ (value_type $I16X8))))
3530
+ (if-let $true (use_sse41))
3531
+ (x64_pmovsxwd val))
3532
+ (rule 1 (lower (has_type $I64X2 (swiden_low val @ (value_type $I32X4))))
3533
+ (if-let $true (use_sse41))
3534
+ (x64_pmovsxdq val))
3535
+
3536
+ (rule (lower (has_type ty (swiden_low val))) (lower_swiden_low ty val))
3537
+
3538
+ (decl lower_swiden_low (Type Xmm) Xmm)
3539
+
3540
+ ;; Duplicate the low lanes next to each other, then perform a wider shift-right
3541
+ ;; by the low lane width to move the upper of each pair back into the lower lane
3542
+ ;; of each pair, achieving the widening of the lower lanes.
3543
+ (rule (lower_swiden_low $I16X8 val)
3544
+ (x64_psraw (x64_punpcklbw val val) (xmi_imm 8)))
3545
+ (rule (lower_swiden_low $I32X4 val)
3546
+ (x64_psrad (x64_punpcklwd val val) (xmi_imm 16)))
3547
+
3548
+ ;; Generate the sign-extended halves with a `val < 0` comparison (expressed
3549
+ ;; reversed here), then interleave the low 32-bit halves to create the full
3550
+ ;; 64-bit results.
3551
+ (rule (lower_swiden_low $I64X2 val)
3552
+ (let ((tmp Xmm (x64_pcmpgtd (xmm_zero $I32X4) val)))
3553
+ (x64_punpckldq val tmp)))
3554
+
3555
+ ;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3556
+
3557
+ ;; Similar to `swiden_low` with SSE4.1 except that the upper lanes are moved
3558
+ ;; to the lower lanes first.
3559
+ (rule 1 (lower (has_type $I16X8 (swiden_high val @ (value_type $I8X16))))
3560
+ (if-let $true (use_sse41))
3561
+ (let ((x Xmm val))
3562
+ (x64_pmovsxbw (x64_palignr x x 8))))
3563
+ (rule 1 (lower (has_type $I32X4 (swiden_high val @ (value_type $I16X8))))
3564
+ (if-let $true (use_sse41))
3565
+ (let ((x Xmm val))
3566
+ (x64_pmovsxwd (x64_palignr x x 8))))
3567
+ (rule 1 (lower (has_type $I64X2 (swiden_high val @ (value_type $I32X4))))
3568
+ (if-let $true (use_sse41))
3569
+ (x64_pmovsxdq (x64_pshufd val 0b11_10_11_10)))
3570
+
3571
+ ;; Similar to `swiden_low` versions but using `punpckh*` instructions to
3572
+ ;; pair the high lanes next to each other.
3573
+ (rule (lower (has_type $I16X8 (swiden_high val @ (value_type $I8X16))))
3574
+ (let ((val Xmm val))
3575
+ (x64_psraw (x64_punpckhbw val val) (xmi_imm 8))))
3576
+ (rule (lower (has_type $I32X4 (swiden_high val @ (value_type $I16X8))))
3577
+ (let ((val Xmm val))
3578
+ (x64_psrad (x64_punpckhwd val val) (xmi_imm 16))))
3579
+
3580
+ ;; Same as `swiden_low`, but `val` has its high lanes moved down.
3581
+ (rule (lower (has_type $I64X2 (swiden_high val @ (value_type $I32X4))))
3582
+ (let ((val Xmm (x64_pshufd val 0b00_00_11_10))
3583
+ (tmp Xmm (x64_pcmpgtd (xmm_zero $I32X4) val)))
3584
+ (x64_punpckldq val tmp)))
3585
+
3586
+ ;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3587
+
3588
+ ;; With SSE4.1 use the `pmovzx*` instructions for this
3589
+ (rule 1 (lower (has_type $I16X8 (uwiden_low val @ (value_type $I8X16))))
3590
+ (if-let $true (use_sse41))
3591
+ (x64_pmovzxbw val))
3592
+ (rule 1 (lower (has_type $I32X4 (uwiden_low val @ (value_type $I16X8))))
3593
+ (if-let $true (use_sse41))
3594
+ (x64_pmovzxwd val))
3595
+ (rule 1 (lower (has_type $I64X2 (uwiden_low val @ (value_type $I32X4))))
3596
+ (if-let $true (use_sse41))
3597
+ (x64_pmovzxdq val))
3598
+
3599
+ (rule (lower (has_type ty (uwiden_low val))) (lower_uwiden_low ty val))
3600
+
3601
+ ;; Interleave an all-zero register with the low lanes to produce zero-extended
3602
+ ;; results.
3603
+ (decl lower_uwiden_low (Type Xmm) Xmm)
3604
+ (rule (lower_uwiden_low $I16X8 val) (x64_punpcklbw val (xmm_zero $I8X16)))
3605
+ (rule (lower_uwiden_low $I32X4 val) (x64_punpcklwd val (xmm_zero $I8X16)))
3606
+ (rule (lower_uwiden_low $I64X2 val) (x64_unpcklps val (xmm_zero $F32X4)))
3607
+
3608
+ ;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3609
+
3610
+ ;; Same as `uwiden_high`, but interleaving high lanes instead.
3611
+ ;;
3612
+ ;; Note that according to `llvm-mca` at least these instructions are faster
3613
+ ;; than using `pmovzx*` in terms of cycles, even if SSE4.1 is available.
3614
+ (rule (lower (has_type $I16X8 (uwiden_high val @ (value_type $I8X16))))
3615
+ (x64_punpckhbw val (xmm_zero $I8X16)))
3616
+ (rule (lower (has_type $I32X4 (uwiden_high val @ (value_type $I16X8))))
3617
+ (x64_punpckhwd val (xmm_zero $I8X16)))
3618
+ (rule (lower (has_type $I64X2 (uwiden_high val @ (value_type $I32X4))))
3619
+ (x64_unpckhps val (xmm_zero $F32X4)))
3620
+
3621
+ ;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3622
+
3623
+ (rule (lower (has_type $I8X16 (snarrow a @ (value_type $I16X8) b)))
3624
+ (x64_packsswb a b))
3625
+
3626
+ (rule (lower (has_type $I16X8 (snarrow a @ (value_type $I32X4) b)))
3627
+ (x64_packssdw a b))
3628
+
3629
+ ;; We're missing a `snarrow` case for $I64X2
3630
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4734
3631
+
3632
+ ;; This rule is a special case for handling the translation of the wasm op
3633
+ ;; `i32x4.trunc_sat_f64x2_s_zero`. It can be removed once we have an
3634
+ ;; implementation of `snarrow` for `I64X2`.
3635
+ (rule (lower (has_type $I32X4 (snarrow (has_type $I64X2 (fcvt_to_sint_sat val))
3636
+ (vconst (u128_from_constant 0)))))
3637
+ (let ((a Xmm val)
3638
+
3639
+ ;; y = i32x4.trunc_sat_f64x2_s_zero(x) is lowered to:
3640
+ ;; MOVE xmm_tmp, xmm_x
3641
+ ;; CMPEQPD xmm_tmp, xmm_x
3642
+ ;; MOVE xmm_y, xmm_x
3643
+ ;; ANDPS xmm_tmp, [wasm_f64x2_splat(2147483647.0)]
3644
+ ;; MINPD xmm_y, xmm_tmp
3645
+ ;; CVTTPD2DQ xmm_y, xmm_y
3646
+
3647
+ (tmp1 Xmm (x64_cmppd a a (FcmpImm.Equal)))
3648
+ (umax_mask XmmMem (snarrow_umax_mask))
3649
+
3650
+ ;; ANDPD xmm_y, [wasm_f64x2_splat(2147483647.0)]
3651
+ (tmp1 Xmm (x64_andps tmp1 umax_mask))
3652
+ (dst Xmm (x64_minpd a tmp1)))
3653
+ (x64_cvttpd2dq dst)))
3654
+
3655
+ ;; This rule is a special case for handling the translation of the wasm op
3656
+ ;; `i32x4.relaxed_trunc_f64x2_s_zero`.
3657
+ (rule (lower (has_type $I32X4 (snarrow (has_type $I64X2 (x86_cvtt2dq val))
3658
+ (vconst (u128_from_constant 0)))))
3659
+ (x64_cvttpd2dq val))
3660
+
3661
+ ;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3662
+
3663
+ (rule (lower (has_type $I8X16 (unarrow a @ (value_type $I16X8) b)))
3664
+ (x64_packuswb a b))
3665
+
3666
+ (rule 1 (lower (has_type $I16X8 (unarrow a @ (value_type $I32X4) b)))
3667
+ (if-let $true (use_sse41))
3668
+ (x64_packusdw a b))
3669
+
3670
+ ;; For each input `a` and `b` take the four 32-bit lanes and compress them to
3671
+ ;; the low 64-bits of the vector as four 16-bit lanes. Then these are woven
3672
+ ;; into one final vector with a `punpcklqdq`.
3673
+ ;;
3674
+ ;; If this is performance sensitive then it's probably best to upgrade the CPU
3675
+ ;; to get the above single-instruction lowering.
3676
+ (rule (lower (has_type $I16X8 (unarrow a @ (value_type $I32X4) b)))
3677
+ (let (
3678
+ (a Xmm (unarrow_i32x4_lanes_to_low_u16_lanes a))
3679
+ (b Xmm (unarrow_i32x4_lanes_to_low_u16_lanes b))
3680
+ )
3681
+ (x64_punpcklqdq a b)))
3682
+
3683
+ (decl unarrow_i32x4_lanes_to_low_u16_lanes (Xmm) Xmm)
3684
+ (rule (unarrow_i32x4_lanes_to_low_u16_lanes val)
3685
+ (let (
3686
+ ;; First convert all negative values in `val` to zero lanes.
3687
+ (val_gt_zero Xmm (x64_pcmpgtd val (xmm_zero $I32X4)))
3688
+ (val Xmm (x64_pand val val_gt_zero))
3689
+
3690
+ ;; Next clamp all larger-than-u16-max lanes to u16::MAX.
3691
+ (max Xmm (x64_movdqu_load (emit_u128_le_const 0x0000ffff_0000ffff_0000ffff_0000ffff)))
3692
+ (cmp Xmm (x64_pcmpgtd max val))
3693
+ (valid_lanes Xmm (x64_pand val cmp))
3694
+ (clamped_lanes Xmm (x64_pandn cmp max))
3695
+ (val Xmm (x64_por valid_lanes clamped_lanes))
3696
+
3697
+ ;; Within each 64-bit half of the 32x4 vector move the first 16 bits
3698
+ ;; and the third 16 bits to the bottom of the half. Afterwards
3699
+ ;; for the 32x4 vector move the first and third lanes to the bottom
3700
+ ;; lanes, which finishes up the conversion here as all the lanes
3701
+ ;; are now converted to 16-bit values in the low 4 lanes.
3702
+ (val Xmm (x64_pshuflw val 0b00_00_10_00))
3703
+ (val Xmm (x64_pshufhw val 0b00_00_10_00))
3704
+ )
3705
+ (x64_pshufd val 0b00_00_10_00)))
3706
+
3707
+
3708
+ ;; We're missing a `unarrow` case for $I64X2
3709
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4734
3710
+
3711
+ ;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3712
+
3713
+ (rule (lower (has_type $I32 (bitcast _ src @ (value_type $F32))))
3714
+ (bitcast_xmm_to_gpr $F32 src))
3715
+
3716
+ (rule (lower (has_type $F32 (bitcast _ src @ (value_type $I32))))
3717
+ (bitcast_gpr_to_xmm $I32 src))
3718
+
3719
+ (rule (lower (has_type $I64 (bitcast _ src @ (value_type $F64))))
3720
+ (bitcast_xmm_to_gpr $F64 src))
3721
+
3722
+ (rule (lower (has_type $F64 (bitcast _ src @ (value_type $I64))))
3723
+ (bitcast_gpr_to_xmm $I64 src))
3724
+
3725
+ ;; Bitcast between types residing in GPR registers is a no-op.
3726
+ (rule 1 (lower (has_type (is_gpr_type _)
3727
+ (bitcast _ x @ (value_type (is_gpr_type _))))) x)
3728
+
3729
+ ;; Bitcast between types residing in XMM registers is a no-op.
3730
+ (rule 2 (lower (has_type (is_xmm_type _)
3731
+ (bitcast _ x @ (value_type (is_xmm_type _))))) x)
3732
+
3733
+ ;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3734
+
3735
+ (rule (lower (has_type $F32 (fcopysign a @ (value_type $F32) b)))
3736
+ (let ((sign_bit Xmm (imm $F32 0x80000000)))
3737
+ (x64_orps
3738
+ (x64_andnps sign_bit a)
3739
+ (x64_andps sign_bit b))))
3740
+
3741
+ (rule (lower (has_type $F64 (fcopysign a @ (value_type $F64) b)))
3742
+ (let ((sign_bit Xmm (imm $F64 0x8000000000000000)))
3743
+ (x64_orpd
3744
+ (x64_andnpd sign_bit a)
3745
+ (x64_andpd sign_bit b))))
3746
+
3747
+ ;; Helper for the `ceil`/`floor`/`nearest`/`trunc` instructions ;;;;;;;;;;;;;;;;
3748
+
3749
+ ;; Emits either a `round{ss,sd,ps,pd}` instruction, as appropriate, or generates
3750
+ ;; the appropriate libcall and sequence to call that.
3751
+ (decl x64_round (Type RegMem RoundImm) Xmm)
3752
+ (rule 1 (x64_round $F32 a imm)
3753
+ (if-let $true (use_sse41))
3754
+ (x64_roundss a imm))
3755
+ (rule 1 (x64_round $F64 a imm)
3756
+ (if-let $true (use_sse41))
3757
+ (x64_roundsd a imm))
3758
+ (rule 1 (x64_round $F32X4 a imm)
3759
+ (if-let $true (use_sse41))
3760
+ (x64_roundps a imm))
3761
+ (rule 1 (x64_round $F64X2 a imm)
3762
+ (if-let $true (use_sse41))
3763
+ (x64_roundpd a imm))
3764
+
3765
+ (rule (x64_round $F32 (RegMem.Reg a) imm) (libcall_1 (round_libcall $F32 imm) a))
3766
+ (rule (x64_round $F64 (RegMem.Reg a) imm) (libcall_1 (round_libcall $F64 imm) a))
3767
+ (rule (x64_round $F32X4 (RegMem.Reg a) imm)
3768
+ (let (
3769
+ (libcall LibCall (round_libcall $F32 imm))
3770
+ (result Xmm (libcall_1 libcall a))
3771
+ (a1 Xmm (libcall_1 libcall (x64_pshufd a 1)))
3772
+ (result Xmm (vec_insert_lane $F32X4 result a1 1))
3773
+ (a2 Xmm (libcall_1 libcall (x64_pshufd a 2)))
3774
+ (result Xmm (vec_insert_lane $F32X4 result a2 2))
3775
+ (a3 Xmm (libcall_1 libcall (x64_pshufd a 3)))
3776
+ (result Xmm (vec_insert_lane $F32X4 result a3 3))
3777
+ )
3778
+ result))
3779
+ (rule (x64_round $F64X2 (RegMem.Reg a) imm)
3780
+ (let (
3781
+ (libcall LibCall (round_libcall $F64 imm))
3782
+ (result Xmm (libcall_1 libcall a))
3783
+ (a1 Xmm (libcall_1 libcall (x64_pshufd a 0b00_00_11_10)))
3784
+ (result Xmm (vec_insert_lane $F64X2 result a1 1))
3785
+ )
3786
+ result))
3787
+ (rule (x64_round ty (RegMem.Mem addr) imm)
3788
+ (x64_round ty (RegMem.Reg (x64_load ty addr (ExtKind.ZeroExtend))) imm))
3789
+
3790
+ (decl round_libcall (Type RoundImm) LibCall)
3791
+ (rule (round_libcall $F32 (RoundImm.RoundUp)) (LibCall.CeilF32))
3792
+ (rule (round_libcall $F64 (RoundImm.RoundUp)) (LibCall.CeilF64))
3793
+ (rule (round_libcall $F32 (RoundImm.RoundDown)) (LibCall.FloorF32))
3794
+ (rule (round_libcall $F64 (RoundImm.RoundDown)) (LibCall.FloorF64))
3795
+ (rule (round_libcall $F32 (RoundImm.RoundNearest)) (LibCall.NearestF32))
3796
+ (rule (round_libcall $F64 (RoundImm.RoundNearest)) (LibCall.NearestF64))
3797
+ (rule (round_libcall $F32 (RoundImm.RoundZero)) (LibCall.TruncF32))
3798
+ (rule (round_libcall $F64 (RoundImm.RoundZero)) (LibCall.TruncF64))
3799
+
3800
+ ;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3801
+
3802
+ (rule (lower (ceil a @ (value_type ty)))
3803
+ (x64_round ty a (RoundImm.RoundUp)))
3804
+
3805
+ ;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3806
+
3807
+ (rule (lower (floor a @ (value_type ty)))
3808
+ (x64_round ty a (RoundImm.RoundDown)))
3809
+
3810
+ ;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3811
+
3812
+ (rule (lower (nearest a @ (value_type ty)))
3813
+ (x64_round ty a (RoundImm.RoundNearest)))
3814
+
3815
+ ;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3816
+
3817
+ (rule (lower (trunc a @ (value_type ty)))
3818
+ (x64_round ty a (RoundImm.RoundZero)))
3819
+
3820
+ ;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3821
+
3822
+ (rule (lower (stack_addr stack_slot offset))
3823
+ (stack_addr_impl stack_slot offset))
3824
+
3825
+ ;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3826
+
3827
+ ;; NB: a `RegMem` divisor, while allowed in the instruction encoding, isn't
3828
+ ;; used right now to prevent a possibly-trapping load getting folded into the
3829
+ ;; `div` instruction. Ideally non-trapping loads would get folded, however, or
3830
+ ;; alternatively Wasmtime/Cranelift would grow support for multiple traps on
3831
+ ;; a single opcode and the signal kind would differentiate at runtime.
3832
+
3833
+ ;; The inputs to the `div` instruction are different for 8-bit division so
3834
+ ;; it needs a special case here since the instruction being crafted has a
3835
+ ;; different shape.
3836
+ (rule 2 (lower (udiv a @ (value_type $I8) b))
3837
+ (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
3838
+ (put_in_gpr b)
3839
+ (DivSignedness.Unsigned)
3840
+ (TrapCode.IntegerDivisionByZero)))
3841
+
3842
+ ;; 16-to-64-bit division is all done with a similar instruction and the only
3843
+ ;; tricky requirement here is that when div traps are disallowed the divisor
3844
+ ;; must not be zero.
3845
+ (rule 1 (lower (udiv a @ (value_type (fits_in_64 ty)) b))
3846
+ (x64_div_quotient a
3847
+ (imm $I64 0)
3848
+ (put_in_gpr b)
3849
+ (raw_operand_size_of_type ty)
3850
+ (DivSignedness.Unsigned)
3851
+ (TrapCode.IntegerDivisionByZero)))
3852
+
3853
+ ;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3854
+
3855
+ (rule 2 (lower (sdiv a @ (value_type $I8) b))
3856
+ (x64_div8 (x64_sign_extend_data a (OperandSize.Size8))
3857
+ (nonzero_sdiv_divisor $I8 b)
3858
+ (DivSignedness.Signed)
3859
+ (TrapCode.IntegerOverflow)))
3860
+
3861
+ (rule 1 (lower (sdiv a @ (value_type (fits_in_64 ty)) b))
3862
+ (let (
3863
+ (a Gpr a)
3864
+ (size OperandSize (raw_operand_size_of_type ty))
3865
+ )
3866
+ (x64_div_quotient a
3867
+ (x64_sign_extend_data a size)
3868
+ (nonzero_sdiv_divisor ty b)
3869
+ size
3870
+ (DivSignedness.Signed)
3871
+ (TrapCode.IntegerOverflow))))
3872
+
3873
+ ;; Checks to make sure that the input `Value` is a non-zero value for `sdiv`.
3874
+ ;;
3875
+ ;; This is required to differentiate the divide-by-zero trap from the
3876
+ ;; integer-overflow trap, the two trapping conditions of signed division.
3877
+ (decl nonzero_sdiv_divisor (Type Value) Reg)
3878
+ (rule 1 (nonzero_sdiv_divisor ty (iconst imm))
3879
+ (if-let n (safe_divisor_from_imm64 ty imm))
3880
+ (imm ty n))
3881
+ (rule 0 (nonzero_sdiv_divisor ty val)
3882
+ (let (
3883
+ (val Reg val)
3884
+ (_ InstOutput (side_effect (with_flags_side_effect
3885
+ (x64_test (raw_operand_size_of_type ty) val val)
3886
+ (trap_if (CC.Z) (TrapCode.IntegerDivisionByZero)))))
3887
+ )
3888
+ val))
3889
+
3890
+ ;; Rules for `urem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3891
+
3892
+ ;; The remainder is in AH, so take the result of the division and right-shift
3893
+ ;; by 8.
3894
+ (rule 2 (lower (urem a @ (value_type $I8) b))
3895
+ (let (
3896
+ (result Gpr (x64_div8 (extend_to_gpr a $I32 (ExtendKind.Zero))
3897
+ (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
3898
+ (DivSignedness.Unsigned)
3899
+ (TrapCode.IntegerDivisionByZero)))
3900
+ )
3901
+ (x64_shr $I64 result (Imm8Reg.Imm8 8))))
3902
+
3903
+ (rule 1 (lower (urem a @ (value_type (fits_in_64 ty)) b))
3904
+ (x64_div_remainder a
3905
+ (imm $I64 0)
3906
+ (put_in_gpr b) ;; see `udiv` for why not `gpr_mem`
3907
+ (raw_operand_size_of_type ty)
3908
+ (DivSignedness.Unsigned)
3909
+ (TrapCode.IntegerDivisionByZero)))
3910
+
3911
+ ;; Rules for `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3912
+
3913
+ ;; Special-cases first for constant `srem` where the checks for 0 and -1 aren't
3914
+ ;; applicable.
3915
+ ;;
3916
+ ;; Note that like `urem` for i8 types the result is in AH so to get the result
3917
+ ;; it's right-shifted down.
3918
+ (rule 3 (lower (srem a @ (value_type $I8) (iconst imm)))
3919
+ (if-let n (safe_divisor_from_imm64 $I8 imm))
3920
+ (let (
3921
+ (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
3922
+ (result Gpr (x64_div8 a (imm $I8 n) (DivSignedness.Signed) (TrapCode.IntegerDivisionByZero)))
3923
+ )
3924
+ (x64_shr $I64 result (Imm8Reg.Imm8 8))))
3925
+
3926
+ ;; Same as the above rule but for 16-to-64 bit types.
3927
+ (rule 2 (lower (srem a @ (value_type ty) (iconst imm)))
3928
+ (if-let n (safe_divisor_from_imm64 ty imm))
3929
+ (let (
3930
+ (a Gpr a)
3931
+ (size OperandSize (raw_operand_size_of_type ty))
3932
+ )
3933
+ (x64_div_remainder a
3934
+ (x64_sign_extend_data a size)
3935
+ (imm ty n)
3936
+ size
3937
+ (DivSignedness.Signed)
3938
+ (TrapCode.IntegerDivisionByZero))))
3939
+
3940
+ (rule 1 (lower (srem a @ (value_type $I8) b))
3941
+ (let (
3942
+ (a Gpr (x64_sign_extend_data a (OperandSize.Size8)))
3943
+ )
3944
+ (x64_shr $I64 (x64_checked_srem_seq8 a b) (Imm8Reg.Imm8 8))))
3945
+
3946
+ (rule (lower (srem a @ (value_type ty) b))
3947
+ (let (
3948
+ (a Gpr a)
3949
+ (size OperandSize (raw_operand_size_of_type ty))
3950
+ (hi Gpr (x64_sign_extend_data a size))
3951
+ (tmp ValueRegs (x64_checked_srem_seq size a hi b))
3952
+ )
3953
+ (value_regs_get tmp 1)))
3954
+
3955
+ ;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3956
+
3957
+ (rule (lower (umulhi a @ (value_type $I16) b))
3958
+ (let ((res ValueRegs (mul_hi $I16 $false a b))
3959
+ (hi Gpr (value_regs_get_gpr res 1)))
3960
+ hi))
3961
+
3962
+ (rule (lower (umulhi a @ (value_type $I32) b))
3963
+ (let ((res ValueRegs (mul_hi $I32 $false a b))
3964
+ (hi Gpr (value_regs_get_gpr res 1)))
3965
+ hi))
3966
+
3967
+ (rule (lower (umulhi a @ (value_type $I64) b))
3968
+ (let ((res ValueRegs (mul_hi $I64 $false a b))
3969
+ (hi Gpr (value_regs_get_gpr res 1)))
3970
+ hi))
3971
+
3972
+ ;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3973
+
3974
+ (rule (lower (smulhi a @ (value_type $I16) b))
3975
+ (let ((res ValueRegs (mul_hi $I16 $true a b))
3976
+ (hi Gpr (value_regs_get_gpr res 1)))
3977
+ hi))
3978
+
3979
+ (rule (lower (smulhi a @ (value_type $I32) b))
3980
+ (let ((res ValueRegs (mul_hi $I32 $true a b))
3981
+ (hi Gpr (value_regs_get_gpr res 1)))
3982
+ hi))
3983
+
3984
+ (rule (lower (smulhi a @ (value_type $I64) b))
3985
+ (let ((res ValueRegs (mul_hi $I64 $true a b))
3986
+ (hi Gpr (value_regs_get_gpr res 1)))
3987
+ hi))
3988
+
3989
+ ;; Rules for `get_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3990
+
3991
+ (rule (lower (get_pinned_reg))
3992
+ (read_pinned_gpr))
3993
+
3994
+ ;; Rules for `set_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3995
+
3996
+ (rule (lower (set_pinned_reg a @ (value_type ty)))
3997
+ (side_effect (write_pinned_gpr a)))
3998
+
3999
+ ;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4000
+
4001
+ (rule (lower (has_type ty (vconst const)))
4002
+ ;; TODO use Inst::gen_constant() instead.
4003
+ (x64_xmm_load_const ty (const_to_vconst const)))
4004
+
4005
+ ;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4006
+
4007
+ ;; Special case for `pblendw` which takes an 8-bit immediate where each bit
4008
+ ;; indicates which lane of the two operands is chosen for the output. A bit of
4009
+ ;; 0 chooses the corresponding 16-it lane from `a` and a bit of 1 chooses the
4010
+ ;; corresponding 16-bit lane from `b`.
4011
+ (rule 14 (lower (shuffle a b (pblendw_imm n)))
4012
+ (if-let $true (use_sse41))
4013
+ (x64_pblendw a b n))
4014
+ (decl pblendw_imm (u8) Immediate)
4015
+ (extern extractor pblendw_imm pblendw_imm)
4016
+
4017
+ ;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
4018
+ ;; bytes", that's a `palignr` instruction. Note that the order of operands are
4019
+ ;; swapped in the instruction here. The `palignr` instruction uses the second
4020
+ ;; operand as the low-order bytes and the first operand as high-order bytes,
4021
+ ;; so put `a` second.
4022
+ (rule 13 (lower (shuffle a b (palignr_imm_from_immediate n)))
4023
+ (x64_palignr b a n))
4024
+ (decl palignr_imm_from_immediate (u8) Immediate)
4025
+ (extern extractor palignr_imm_from_immediate palignr_imm_from_immediate)
4026
+
4027
+ ;; Special case the `pshuf{l,h}w` instruction which shuffles four 16-bit
4028
+ ;; integers within one value, preserving the other four 16-bit integers in that
4029
+ ;; value (either the high or low half). The complicated logic is in the
4030
+ ;; extractors here implemented in Rust and note that there's two cases for each
4031
+ ;; instruction here to match when either the first or second shuffle operand is
4032
+ ;; used.
4033
+ (rule 12 (lower (shuffle x y (pshuflw_lhs_imm imm)))
4034
+ (x64_pshuflw x imm))
4035
+ (rule 11 (lower (shuffle x y (pshuflw_rhs_imm imm)))
4036
+ (x64_pshuflw y imm))
4037
+ (rule 10 (lower (shuffle x y (pshufhw_lhs_imm imm)))
4038
+ (x64_pshufhw x imm))
4039
+ (rule 9 (lower (shuffle x y (pshufhw_rhs_imm imm)))
4040
+ (x64_pshufhw y imm))
4041
+
4042
+ (decl pshuflw_lhs_imm (u8) Immediate)
4043
+ (extern extractor pshuflw_lhs_imm pshuflw_lhs_imm)
4044
+ (decl pshuflw_rhs_imm (u8) Immediate)
4045
+ (extern extractor pshuflw_rhs_imm pshuflw_rhs_imm)
4046
+ (decl pshufhw_lhs_imm (u8) Immediate)
4047
+ (extern extractor pshufhw_lhs_imm pshufhw_lhs_imm)
4048
+ (decl pshufhw_rhs_imm (u8) Immediate)
4049
+ (extern extractor pshufhw_rhs_imm pshufhw_rhs_imm)
4050
+
4051
+ ;; Special case for the `pshufd` instruction which will permute 32-bit values
4052
+ ;; within a single register. This is only applicable if the `imm` specified
4053
+ ;; selects 32-bit values from either `x` or `y`, but not both. This means
4054
+ ;; there's one rule for selecting from `x` and another rule for selecting from
4055
+ ;; `y`.
4056
+ (rule 8 (lower (shuffle x y (pshufd_lhs_imm imm)))
4057
+ (x64_pshufd x imm))
4058
+ (rule 7 (lower (shuffle x y (pshufd_rhs_imm imm)))
4059
+ (x64_pshufd y imm))
4060
+
4061
+ (decl pshufd_lhs_imm (u8) Immediate)
4062
+ (extern extractor pshufd_lhs_imm pshufd_lhs_imm)
4063
+ (decl pshufd_rhs_imm (u8) Immediate)
4064
+ (extern extractor pshufd_rhs_imm pshufd_rhs_imm)
4065
+
4066
+ ;; Special case for i8-level interleaving of upper/low bytes.
4067
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f0f_1e0e_1d0d_1c0c_1b0b_1a0a_1909_1808)))
4068
+ (x64_punpckhbw a b))
4069
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1707_1606_1505_1404_1303_1202_1101_1000)))
4070
+ (x64_punpcklbw a b))
4071
+
4072
+ ;; Special case for i16-level interleaving of upper/low bytes.
4073
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1d1c_0d0c_1b1a_0b0a_1918_0908)))
4074
+ (x64_punpckhwd a b))
4075
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1716_0706_1514_0504_1312_0302_1110_0100)))
4076
+ (x64_punpcklwd a b))
4077
+
4078
+ ;; Special case for i32-level interleaving of upper/low bytes.
4079
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_1b1a1918_0b0a0908)))
4080
+ (x64_punpckhdq a b))
4081
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x17161514_07060504_13121110_03020100)))
4082
+ (x64_punpckldq a b))
4083
+
4084
+ ;; Special case for i64-level interleaving of upper/low bytes.
4085
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c1b1a1918_0f0e0d0c0b0a0908)))
4086
+ (x64_punpckhqdq a b))
4087
+ (rule 6 (lower (shuffle a b (u128_from_immediate 0x1716151413121110_0706050403020100)))
4088
+ (x64_punpcklqdq a b))
4089
+
4090
+ ;; If the vector shift mask is all 0s then that means the first byte of the
4091
+ ;; first operand is broadcast to all bytes. Falling through would load an
4092
+ ;; all-zeros constant from a rip-relative location but it should be slightly
4093
+ ;; more efficient to execute the `pshufb` here-and-now with an xor'd-to-be-zero
4094
+ ;; register.
4095
+ (rule 6 (lower (shuffle a _ (u128_from_immediate 0)))
4096
+ (x64_pshufb a (xmm_zero $I8X16)))
4097
+
4098
+ ;; Special case for the `shufps` instruction which will select two 32-bit values
4099
+ ;; from the first operand and two 32-bit values from the second operand. Note
4100
+ ;; that there is a second case here as well for when the operands can be
4101
+ ;; swapped.
4102
+ ;;
4103
+ ;; Note that the priority of this instruction is currently lower than the above
4104
+ ;; special cases since `shufps` handles many of them and for now it's
4105
+ ;; hypothesized that the dedicated instructions are better than `shufps`.
4106
+ ;; Someone with more knowledge about x86 timings should perhaps reorder the
4107
+ ;; rules here eventually though.
4108
+ (rule 5 (lower (shuffle x y (shufps_imm imm)))
4109
+ (x64_shufps x y imm))
4110
+ (rule 4 (lower (shuffle x y (shufps_rev_imm imm)))
4111
+ (x64_shufps y x imm))
4112
+
4113
+ (decl shufps_imm(u8) Immediate)
4114
+ (extern extractor shufps_imm shufps_imm)
4115
+ (decl shufps_rev_imm(u8) Immediate)
4116
+ (extern extractor shufps_rev_imm shufps_rev_imm)
4117
+
4118
+
4119
+ ;; If `lhs` and `rhs` are the same we can use a single PSHUFB to shuffle the XMM
4120
+ ;; register. We statically build `constructed_mask` to zero out any unknown lane
4121
+ ;; indices (may not be completely necessary: verification could fail incorrect
4122
+ ;; mask values) and fix the indexes to all point to the `dst` vector.
4123
+ (rule 3 (lower (shuffle a a (vec_mask_from_immediate mask)))
4124
+ (x64_pshufb a (shuffle_0_31_mask mask)))
4125
+
4126
+ ;; For the case where the shuffle mask contains out-of-bounds values (values
4127
+ ;; greater than 31) we must mask off those resulting values in the result of
4128
+ ;; `vpermi2b`.
4129
+ (rule 2 (lower (shuffle a b (vec_mask_from_immediate (perm_from_mask_with_zeros mask zeros))))
4130
+ (if-let $true (use_avx512vl_simd))
4131
+ (if-let $true (use_avx512vbmi_simd))
4132
+ (x64_andps (x64_vpermi2b (x64_xmm_load_const $I8X16 mask) a b) zeros))
4133
+
4134
+ ;; However, if the shuffle mask contains no out-of-bounds values, we can use
4135
+ ;; `vpermi2b` without any masking.
4136
+ (rule 1 (lower (shuffle a b (vec_mask_from_immediate mask)))
4137
+ (if-let $true (use_avx512vl_simd))
4138
+ (if-let $true (use_avx512vbmi_simd))
4139
+ (x64_vpermi2b (x64_xmm_load_const $I8X16 (perm_from_mask mask)) a b))
4140
+
4141
+ ;; If `lhs` and `rhs` are different, we must shuffle each separately and then OR
4142
+ ;; them together. This is necessary due to PSHUFB semantics. As in the case
4143
+ ;; above, we build the `constructed_mask` for each case statically.
4144
+ (rule (lower (shuffle a b (vec_mask_from_immediate mask)))
4145
+ (x64_por
4146
+ (x64_pshufb a (shuffle_0_15_mask mask))
4147
+ (x64_pshufb b (shuffle_16_31_mask mask))))
4148
+
4149
+ ;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4150
+
4151
+ ;; SIMD swizzle; the following inefficient implementation is due to the Wasm
4152
+ ;; SIMD spec requiring mask indexes greater than 15 to have the same semantics
4153
+ ;; as a 0 index. For the spec discussion, see
4154
+ ;; https://github.com/WebAssembly/simd/issues/93. The CLIF semantics match the
4155
+ ;; Wasm SIMD semantics for this instruction. The instruction format maps to
4156
+ ;; variables like: %dst = swizzle %src, %mask
4157
+ (rule (lower (swizzle src mask))
4158
+ (let ((mask Xmm (x64_paddusb mask (swizzle_zero_mask))))
4159
+ (x64_pshufb src mask)))
4160
+
4161
+ ;; Rules for `x86_pshufb` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4162
+
4163
+ (rule (lower (x86_pshufb src mask))
4164
+ (x64_pshufb src mask))
4165
+
4166
+ ;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4167
+
4168
+ ;; Remove the extractlane instruction, leaving the float where it is. The upper
4169
+ ;; bits will remain unchanged; for correctness, this relies on Cranelift type
4170
+ ;; checking to avoid using those bits.
4171
+ (rule 3 (lower (has_type (ty_scalar_float _) (extractlane val 0)))
4172
+ val)
4173
+
4174
+ ;; `f32x4.extract_lane N` where `N != 0`
4175
+ (rule 1 (lower (extractlane val @ (value_type $F32X4) (u8_from_uimm8 lane)))
4176
+ (x64_pshufd val lane))
4177
+
4178
+ ;; `f64x2.extract_lane N` where `N != 0` (aka N == 1)
4179
+ (rule (lower (extractlane val @ (value_type $F64X2) 1))
4180
+ (x64_pshufd val 0b11_10_11_10))
4181
+
4182
+ ;; `i8x16.extract_lane N`
4183
+ ;;
4184
+ ;; Note that without SSE4.1 a 16-bit lane extraction is performed and then
4185
+ ;; the result is updated if the desired index is either odd or even.
4186
+ (rule 2 (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4187
+ (if-let $true (use_sse41))
4188
+ (x64_pextrb val lane))
4189
+ ;; extracting an odd lane has an extra shift-right
4190
+ (rule 1 (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4191
+ (if-let 1 (u8_and lane 1))
4192
+ (x64_shr $I16 (x64_pextrw val (u8_shr lane 1)) (Imm8Reg.Imm8 8)))
4193
+ ;; Extracting an even lane already has the desired lane in the lower bits. Note
4194
+ ;; that having arbitrary upper bits in the returned register should be ok since
4195
+ ;; all operators on the resulting `i8` type should work correctly regardless of
4196
+ ;; the bits in the rest of the register.
4197
+ (rule (lower (extractlane val @ (value_type ty @ $I8X16) (u8_from_uimm8 lane)))
4198
+ (if-let 0 (u8_and lane 1))
4199
+ (x64_pextrw val (u8_shr lane 1)))
4200
+
4201
+ ;; `i16x8.extract_lane N`
4202
+ (rule (lower (extractlane val @ (value_type ty @ $I16X8) (u8_from_uimm8 lane)))
4203
+ (x64_pextrw val lane))
4204
+
4205
+ ;; `i32x4.extract_lane N`
4206
+ (rule 2 (lower (extractlane val @ (value_type ty @ $I32X4) (u8_from_uimm8 lane)))
4207
+ (if-let $true (use_sse41))
4208
+ (x64_pextrd val lane))
4209
+ (rule 1 (lower (extractlane val @ (value_type $I32X4) 0))
4210
+ (x64_movd_to_gpr val))
4211
+ (rule (lower (extractlane val @ (value_type $I32X4) (u8_from_uimm8 n)))
4212
+ (x64_movd_to_gpr (x64_pshufd val n)))
4213
+
4214
+ ;; `i64x2.extract_lane N`
4215
+ (rule 1 (lower (extractlane val @ (value_type $I64X2) (u8_from_uimm8 lane)))
4216
+ (if-let $true (use_sse41))
4217
+ (x64_pextrq val lane))
4218
+ (rule (lower (extractlane val @ (value_type $I64X2) 0))
4219
+ (x64_movq_to_gpr val))
4220
+ (rule (lower (extractlane val @ (value_type $I64X2) 1))
4221
+ (x64_movq_to_gpr (x64_pshufd val 0b00_00_11_10)))
4222
+
4223
+ ;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4224
+
4225
+ ;; Case 1: when moving a scalar float, we simply move from one XMM register
4226
+ ;; to another, expecting the register allocator to elide this. Here we
4227
+ ;; assume that the upper bits of a scalar float have not been munged with
4228
+ ;; (the same assumption the old backend makes).
4229
+ (rule 1 (lower (scalar_to_vector src @ (value_type (ty_scalar_float _))))
4230
+ src)
4231
+
4232
+ ;; Case 2: when moving a scalar value of any other type, use MOVD to zero
4233
+ ;; the upper lanes.
4234
+ (rule (lower (scalar_to_vector src @ (value_type ty)))
4235
+ (bitcast_gpr_to_xmm ty src))
4236
+
4237
+ ;; Case 3: when presented with `load + scalar_to_vector`, coalesce into a single
4238
+ ;; MOVSS/MOVSD instruction.
4239
+ (rule 2 (lower (scalar_to_vector (and (sinkable_load src) (value_type (ty_32 _)))))
4240
+ (x64_movss_load src))
4241
+ (rule 3 (lower (scalar_to_vector (and (sinkable_load src) (value_type (ty_64 _)))))
4242
+ (x64_movsd_load src))
4243
+
4244
+ ;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4245
+
4246
+ ;; For all the splat rules below one of the goals is that splatting a value
4247
+ ;; doesn't end up accidentally depending on the previous value in a register.
4248
+ ;; This means that instructions are chosen to avoid false dependencies where
4249
+ ;; new values are created fresh or otherwise overwrite previous register
4250
+ ;; contents where possible.
4251
+ ;;
4252
+ ;; Additionally splats are specialized to special-case load-and-splat which
4253
+ ;; has a number of micro-optimizations available.
4254
+
4255
+ ;; i8x16 splats: use `vpbroadcastb` on AVX2 and otherwise `pshufb` broadcasts
4256
+ ;; with a mask of zero which is calculated with an xor-against-itself register.
4257
+ (rule 0 (lower (has_type $I8X16 (splat src)))
4258
+ (x64_pshufb (bitcast_gpr_to_xmm $I32 src) (xmm_zero $I8X16)))
4259
+ (rule 1 (lower (has_type $I8X16 (splat src)))
4260
+ (if-let $true (use_avx2_simd))
4261
+ (x64_vpbroadcastb (bitcast_gpr_to_xmm $I32 src)))
4262
+ (rule 2 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
4263
+ (if-let $true (use_sse41))
4264
+ (x64_pshufb (x64_pinsrb (xmm_uninit_value) addr 0) (xmm_zero $I8X16)))
4265
+ (rule 3 (lower (has_type $I8X16 (splat (sinkable_load_exact addr))))
4266
+ (if-let $true (use_avx2_simd))
4267
+ (x64_vpbroadcastb addr))
4268
+
4269
+ ;; i16x8 splats: use `vpbroadcastw` on AVX2 and otherwise a 16-bit value is
4270
+ ;; loaded into an xmm register, `pshuflw` broadcasts the low 16-bit lane
4271
+ ;; to the low four lanes, and `pshufd` broadcasts the low 32-bit lane (which
4272
+ ;; at that point is two of the 16-bit values we want to broadcast) to all the
4273
+ ;; lanes.
4274
+ (rule 0 (lower (has_type $I16X8 (splat src)))
4275
+ (x64_pshufd (x64_pshuflw (bitcast_gpr_to_xmm $I32 src) 0) 0))
4276
+ (rule 1 (lower (has_type $I16X8 (splat src)))
4277
+ (if-let $true (use_avx2_simd))
4278
+ (x64_vpbroadcastw (bitcast_gpr_to_xmm $I32 src)))
4279
+ (rule 2 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
4280
+ (x64_pshufd (x64_pshuflw (x64_pinsrw (xmm_uninit_value) addr 0) 0) 0))
4281
+ (rule 3 (lower (has_type $I16X8 (splat (sinkable_load_exact addr))))
4282
+ (if-let $true (use_avx2_simd))
4283
+ (x64_vpbroadcastw addr))
4284
+
4285
+ ;; i32x4.splat - use `vpbroadcastd` on AVX2 and otherwise `pshufd` can be
4286
+ ;; used to broadcast the low lane to all other lanes.
4287
+ ;;
4288
+ ;; Note that sinkable-load cases come later
4289
+ (rule 0 (lower (has_type $I32X4 (splat src)))
4290
+ (x64_pshufd (bitcast_gpr_to_xmm $I32 src) 0))
4291
+ (rule 1 (lower (has_type $I32X4 (splat src)))
4292
+ (if-let $true (use_avx2_simd))
4293
+ (x64_vpbroadcastd (bitcast_gpr_to_xmm $I32 src)))
4294
+
4295
+ ;; f32x4.splat - the source is already in an xmm register so `shufps` is all
4296
+ ;; that's necessary to complete the splat. This is specialized to `vbroadcastss`
4297
+ ;; on AVX2 to leverage that specific instruction for this operation.
4298
+ (rule 0 (lower (has_type $F32X4 (splat src)))
4299
+ (let ((tmp Xmm src))
4300
+ (x64_shufps src src 0)))
4301
+ (rule 1 (lower (has_type $F32X4 (splat src)))
4302
+ (if-let $true (use_avx2_simd))
4303
+ (x64_vbroadcastss src))
4304
+
4305
+ ;; t32x4.splat of a load - use a `movss` to load into an xmm register and then
4306
+ ;; `shufps` broadcasts to the other lanes. Note that this is used for both i32
4307
+ ;; and f32 splats.
4308
+ ;;
4309
+ ;; With AVX the `vbroadcastss` instruction suits this purpose precisely. Note
4310
+ ;; that the memory-operand encoding of `vbroadcastss` is usable with AVX, but
4311
+ ;; the register-based encoding is only available with AVX2. With the
4312
+ ;; `sinkable_load` extractor this should be guaranteed to use the memory-based
4313
+ ;; encoding hence the `use_avx_simd` test.
4314
+ (rule 4 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
4315
+ (let ((tmp Xmm (x64_movss_load addr)))
4316
+ (x64_shufps tmp tmp 0)))
4317
+ (rule 5 (lower (has_type (multi_lane 32 4) (splat (sinkable_load addr))))
4318
+ (if-let $true (use_avx_simd))
4319
+ (x64_vbroadcastss addr))
4320
+
4321
+ ;; t64x2.splat - use `movddup` which is exactly what we want and there's a
4322
+ ;; minor specialization for sinkable loads to avoid going through a gpr for i64
4323
+ ;; splats
4324
+ (rule 0 (lower (has_type $I64X2 (splat src)))
4325
+ (x64_movddup (bitcast_gpr_to_xmm $I64 src)))
4326
+ (rule 0 (lower (has_type $F64X2 (splat src)))
4327
+ (x64_movddup src))
4328
+ (rule 5 (lower (has_type (multi_lane 64 2) (splat (sinkable_load addr))))
4329
+ (x64_movddup addr))
4330
+
4331
+ ;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4332
+
4333
+ (rule 1 (lower (vany_true val))
4334
+ (if-let $true (use_sse41))
4335
+ (let ((val Xmm val))
4336
+ (with_flags (x64_ptest val val) (x64_setcc (CC.NZ)))))
4337
+
4338
+ ;; Any nonzero byte in `val` means that any lane is true. Compare `val` with a
4339
+ ;; zeroed register and extract the high bits to a gpr mask. If the mask is
4340
+ ;; 0xffff then every byte was equal to zero, so test if the comparison is
4341
+ ;; not-equal or NZ.
4342
+ (rule (lower (vany_true val))
4343
+ (let (
4344
+ (any_byte_zero Xmm (x64_pcmpeqb val (xmm_zero $I8X16)))
4345
+ (mask Gpr (x64_pmovmskb (OperandSize.Size32) any_byte_zero))
4346
+ )
4347
+ (with_flags (x64_cmp (OperandSize.Size32) (RegMemImm.Imm 0xffff) mask)
4348
+ (x64_setcc (CC.NZ)))))
4349
+
4350
+ ;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4351
+
4352
+ (rule 1 (lower (vall_true val @ (value_type ty)))
4353
+ (if-let $true (use_sse41))
4354
+ (let ((src Xmm val)
4355
+ (zeros Xmm (xmm_zero ty))
4356
+ (cmp Xmm (x64_pcmpeq (vec_int_type ty) src zeros)))
4357
+ (with_flags (x64_ptest cmp cmp) (x64_setcc (CC.Z)))))
4358
+
4359
+ ;; Perform an appropriately-sized lane-wise comparison with zero. If the
4360
+ ;; result is all 0s then all of them are true because nothing was equal to
4361
+ ;; zero.
4362
+ (rule (lower (vall_true val @ (value_type ty)))
4363
+ (let ((lanes_with_zero Xmm (x64_pcmpeq (vec_int_type ty) val (xmm_zero ty)))
4364
+ (mask Gpr (x64_pmovmskb (OperandSize.Size32) lanes_with_zero)))
4365
+ (with_flags (x64_test (OperandSize.Size32) mask mask)
4366
+ (x64_setcc (CC.Z)))))
4367
+
4368
+ ;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4369
+
4370
+ ;; The Intel specification allows using both 32-bit and 64-bit GPRs as
4371
+ ;; destination for the "move mask" instructions. This is controlled by the REX.R
4372
+ ;; bit: "In 64-bit mode, the instruction can access additional registers when
4373
+ ;; used with a REX.R prefix. The default operand size is 64-bit in 64-bit mode"
4374
+ ;; (PMOVMSKB in IA Software Development Manual, vol. 2). This being the case, we
4375
+ ;; will always clear REX.W since its use is unnecessary (`OperandSize` is used
4376
+ ;; for setting/clearing REX.W) as we need at most 16 bits of output for
4377
+ ;; `vhigh_bits`.
4378
+
4379
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 8 16))))
4380
+ (x64_pmovmskb (OperandSize.Size32) val))
4381
+
4382
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 32 4))))
4383
+ (x64_movmskps (OperandSize.Size32) val))
4384
+
4385
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 64 2))))
4386
+ (x64_movmskpd (OperandSize.Size32) val))
4387
+
4388
+ ;; There is no x86 instruction for extracting the high bit of 16-bit lanes so
4389
+ ;; here we:
4390
+ ;; - duplicate the 16-bit lanes of `src` into 8-bit lanes:
4391
+ ;; PACKSSWB([x1, x2, ...], [x1, x2, ...]) = [x1', x2', ..., x1', x2', ...]
4392
+ ;; - use PMOVMSKB to gather the high bits; now we have duplicates, though
4393
+ ;; - shift away the bottom 8 high bits to remove the duplicates.
4394
+ (rule (lower (vhigh_bits val @ (value_type (multi_lane 16 8))))
4395
+ (let ((src Xmm val)
4396
+ (tmp Xmm (x64_packsswb src src))
4397
+ (tmp Gpr (x64_pmovmskb (OperandSize.Size32) tmp)))
4398
+ (x64_shr $I64 tmp (Imm8Reg.Imm8 8))))
4399
+
4400
+ ;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4401
+
4402
+ (rule (lower (iconcat lo @ (value_type $I64) hi))
4403
+ (value_regs lo hi))
4404
+
4405
+ ;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4406
+
4407
+ (rule (lower (isplit val @ (value_type $I128)))
4408
+ (let ((regs ValueRegs val)
4409
+ (lo Reg (value_regs_get regs 0))
4410
+ (hi Reg (value_regs_get regs 1)))
4411
+ (output_pair lo hi)))
4412
+
4413
+ ;; Rules for `tls_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4414
+
4415
+ (rule (lower (has_type (tls_model (TlsModel.ElfGd)) (tls_value (symbol_value_data name _ _))))
4416
+ (elf_tls_get_addr name))
4417
+
4418
+ (rule (lower (has_type (tls_model (TlsModel.Macho)) (tls_value (symbol_value_data name _ _))))
4419
+ (macho_tls_get_addr name))
4420
+
4421
+ (rule (lower (has_type (tls_model (TlsModel.Coff)) (tls_value (symbol_value_data name _ _))))
4422
+ (coff_tls_get_addr name))
4423
+
4424
+ ;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4425
+
4426
+ (rule (lower (sqmul_round_sat qx @ (value_type $I16X8) qy))
4427
+ (let ((src1 Xmm qx)
4428
+ (src2 Xmm qy)
4429
+
4430
+ (mask XmmMem (sqmul_round_sat_mask))
4431
+ (dst Xmm (x64_pmulhrsw src1 src2))
4432
+ (cmp Xmm (x64_pcmpeqw dst mask)))
4433
+ (x64_pxor dst cmp)))
4434
+
4435
+ ;; Rules for `x86_pmulhrsw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4436
+
4437
+ (rule (lower (x86_pmulhrsw qx @ (value_type $I16X8) qy))
4438
+ (x64_pmulhrsw qx qy))
4439
+
4440
+ ;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4441
+
4442
+ ;; TODO: currently we only lower a special case of `uunarrow` needed to support
4443
+ ;; the translation of wasm's i32x4.trunc_sat_f64x2_u_zero operation.
4444
+ ;; https://github.com/bytecodealliance/wasmtime/issues/4791
4445
+ ;;
4446
+ ;; y = i32x4.trunc_sat_f64x2_u_zero(x) is lowered to:
4447
+ ;; MOVAPD xmm_y, xmm_x
4448
+ ;; XORPD xmm_tmp, xmm_tmp
4449
+ ;; MAXPD xmm_y, xmm_tmp
4450
+ ;; MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
4451
+ ;; ROUNDPD xmm_y, xmm_y, 0x0B
4452
+ ;; ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
4453
+ ;; SHUFPS xmm_y, xmm_xmp, 0x88
4454
+ (rule (lower (uunarrow (fcvt_to_uint_sat src @ (value_type $F64X2))
4455
+ (vconst (u128_from_constant 0))))
4456
+ (let ((src Xmm src)
4457
+
4458
+ ;; MOVAPD xmm_y, xmm_x
4459
+ ;; XORPD xmm_tmp, xmm_tmp
4460
+ (zeros Xmm (xmm_zero $F64X2))
4461
+ (dst Xmm (x64_maxpd src zeros))
4462
+
4463
+ (umax_mask XmmMem (uunarrow_umax_mask))
4464
+
4465
+ ;; MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
4466
+ (dst Xmm (x64_minpd dst umax_mask))
4467
+
4468
+ ;; ROUNDPD xmm_y, xmm_y, 0x0B
4469
+ (dst Xmm (x64_round $F64X2 dst (RoundImm.RoundZero)))
4470
+
4471
+ ;; ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
4472
+ (uint_mask XmmMem (uunarrow_uint_mask))
4473
+ (dst Xmm (x64_addpd dst uint_mask)))
4474
+
4475
+ ;; SHUFPS xmm_y, xmm_xmp, 0x88
4476
+ (x64_shufps dst zeros 0x88)))
4477
+
4478
+ ;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4479
+
4480
+ (rule (lower (nop))
4481
+ (invalid_reg))