wasmtime 9.0.4 → 10.0.1

data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/lower.rs

@@ -1,328 +0,0 @@
-//! Lowering rules for X64.
-
-// ISLE integration glue.
-pub(super) mod isle;
-
-use crate::ir::{types, ExternalName, Inst as IRInst, LibCall, Opcode, Type};
-use crate::isa::x64::abi::*;
-use crate::isa::x64::inst::args::*;
-use crate::isa::x64::inst::*;
-use crate::isa::{x64::X64Backend, CallConv};
-use crate::machinst::abi::SmallInstVec;
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::result::CodegenResult;
-use crate::settings::Flags;
-use smallvec::smallvec;
-use target_lexicon::Triple;
-
-//=============================================================================
-// Helpers for instruction lowering.
-
-fn is_int_or_ref_ty(ty: Type) -> bool {
-    match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
-        types::R32 => panic!("shouldn't have 32-bits refs on x64"),
-        _ => false,
-    }
-}
-
-/// Returns whether the given specified `input` is a result produced by an instruction with Opcode
-/// `op`.
-// TODO investigate failures with checking against the result index.
-fn matches_input(ctx: &mut Lower<Inst>, input: InsnInput, op: Opcode) -> Option<IRInst> {
-    let inputs = ctx.get_input_as_source_or_const(input.insn, input.input);
-    inputs.inst.as_inst().and_then(|(src_inst, _)| {
-        let data = ctx.data(src_inst);
-        if data.opcode() == op {
-            return Some(src_inst);
-        }
-        None
-    })
-}
-
-/// Put the given input into possibly multiple registers, and mark it as used (side-effect).
-fn put_input_in_regs(ctx: &mut Lower<Inst>, spec: InsnInput) -> ValueRegs<Reg> {
-    let ty = ctx.input_ty(spec.insn, spec.input);
-    let input = ctx.get_input_as_source_or_const(spec.insn, spec.input);
-
-    if let Some(c) = input.constant {
-        // Generate constants fresh at each use to minimize long-range register pressure.
-        let from_bits = ty_bits(ty);
-        let (size, c) = if from_bits < 64 {
-            (OperandSize::Size32, c & ((1u64 << from_bits) - 1))
-        } else {
-            (OperandSize::Size64, c)
-        };
-        assert!(is_int_or_ref_ty(ty)); // Only used for addresses.
-        let cst_copy = ctx.alloc_tmp(ty);
-        ctx.emit(Inst::imm(size, c, cst_copy.only_reg().unwrap()));
-        non_writable_value_regs(cst_copy)
-    } else {
-        ctx.put_input_in_regs(spec.insn, spec.input)
-    }
-}
-
-/// Put the given input into a register, and mark it as used (side-effect).
-fn put_input_in_reg(ctx: &mut Lower<Inst>, spec: InsnInput) -> Reg {
-    put_input_in_regs(ctx, spec)
-        .only_reg()
-        .expect("Multi-register value not expected")
-}
-
-enum MergeableLoadSize {
-    /// The load size performed by a sinkable load merging operation is
-    /// precisely the size necessary for the type in question.
-    Exact,
-
-    /// Narrower-than-32-bit values are handled by ALU insts that are at least
-    /// 32 bits wide, which is normally OK as we ignore upper buts; but, if we
-    /// generate, e.g., a direct-from-memory 32-bit add for a byte value and
-    /// the byte is the last byte in a page, the extra data that we load is
-    /// incorrectly accessed. So we only allow loads to merge for
-    /// 32-bit-and-above widths.
-    Min32,
-}
-
-/// Determines whether a load operation (indicated by `src_insn`) can be merged
-/// into the current lowering point. If so, returns the address-base source (as
-/// an `InsnInput`) and an offset from that address from which to perform the
-/// load.
-fn is_mergeable_load(
-    ctx: &mut Lower<Inst>,
-    src_insn: IRInst,
-    size: MergeableLoadSize,
-) -> Option<(InsnInput, i32)> {
-    let insn_data = ctx.data(src_insn);
-    let inputs = ctx.num_inputs(src_insn);
-    if inputs != 1 {
-        return None;
-    }
-
-    // If this type is too small to get a merged load, don't merge the load.
-    let load_ty = ctx.output_ty(src_insn, 0);
-    if ty_bits(load_ty) < 32 {
-        match size {
-            MergeableLoadSize::Exact => {}
-            MergeableLoadSize::Min32 => return None,
-        }
-    }
-
-    // Just testing the opcode is enough, because the width will always match if
-    // the type does (and the type should match if the CLIF is properly
-    // constructed).
-    if insn_data.opcode() == Opcode::Load {
-        let offset = insn_data
-            .load_store_offset()
-            .expect("load should have offset");
-        Some((
-            InsnInput {
-                insn: src_insn,
-                input: 0,
-            },
-            offset,
-        ))
-    } else {
-        None
-    }
-}
-
-fn input_to_imm(ctx: &mut Lower<Inst>, spec: InsnInput) -> Option<u64> {
-    ctx.get_input_as_source_or_const(spec.insn, spec.input)
-        .constant
-}
-
-fn emit_vm_call(
-    ctx: &mut Lower<Inst>,
-    flags: &Flags,
-    triple: &Triple,
-    libcall: LibCall,
-    inputs: &[Reg],
-    outputs: &[Writable<Reg>],
-) -> CodegenResult<()> {
-    let extname = ExternalName::LibCall(libcall);
-
-    let dist = if flags.use_colocated_libcalls() {
-        RelocDistance::Near
-    } else {
-        RelocDistance::Far
-    };
-
-    // TODO avoid recreating signatures for every single Libcall function.
-    let call_conv = CallConv::for_libcall(flags, CallConv::triple_default(triple));
-    let sig = libcall.signature(call_conv, types::I64);
-    let caller_conv = ctx.abi().call_conv(ctx.sigs());
-
-    if !ctx.sigs().have_abi_sig_for_signature(&sig) {
-        ctx.sigs_mut()
-            .make_abi_sig_from_ir_signature::<X64ABIMachineSpec>(sig.clone(), flags)?;
-    }
-
-    let mut abi =
-        X64Caller::from_libcall(ctx.sigs(), &sig, &extname, dist, caller_conv, flags.clone())?;
-
-    abi.emit_stack_pre_adjust(ctx);
-
-    assert_eq!(inputs.len(), abi.num_args(ctx.sigs()));
-
-    for (i, input) in inputs.iter().enumerate() {
-        for inst in abi.gen_arg(ctx, i, ValueRegs::one(*input)) {
-            ctx.emit(inst);
-        }
-    }
-
-    let mut retval_insts: SmallInstVec<_> = smallvec![];
-    for (i, output) in outputs.iter().enumerate() {
-        retval_insts.extend(abi.gen_retval(ctx, i, ValueRegs::one(*output)).into_iter());
-    }
-    abi.emit_call(ctx);
-    for inst in retval_insts {
-        ctx.emit(inst);
-    }
-    abi.emit_stack_post_adjust(ctx);
-
-    Ok(())
-}
-
-/// Returns whether the given input is a shift by a constant value less or equal than 3.
-/// The goal is to embed it within an address mode.
-fn matches_small_constant_shift(ctx: &mut Lower<Inst>, spec: InsnInput) -> Option<(InsnInput, u8)> {
-    matches_input(ctx, spec, Opcode::Ishl).and_then(|shift| {
-        match input_to_imm(
-            ctx,
-            InsnInput {
-                insn: shift,
-                input: 1,
-            },
-        ) {
-            Some(shift_amt) if shift_amt <= 3 => Some((
-                InsnInput {
-                    insn: shift,
-                    input: 0,
-                },
-                shift_amt as u8,
-            )),
-            _ => None,
-        }
-    })
-}
-
-/// Lowers an instruction to one of the x86 addressing modes.
-///
-/// Note: the 32-bit offset in Cranelift has to be sign-extended, which maps x86's behavior.
-fn lower_to_amode(ctx: &mut Lower<Inst>, spec: InsnInput, offset: i32) -> Amode {
-    let flags = ctx
-        .memflags(spec.insn)
-        .expect("Instruction with amode should have memflags");
-
-    // We now either have an add that we must materialize, or some other input; as well as the
-    // final offset.
-    if let Some(add) = matches_input(ctx, spec, Opcode::Iadd) {
-        debug_assert_eq!(ctx.output_ty(add, 0), types::I64);
-        let add_inputs = &[
-            InsnInput {
-                insn: add,
-                input: 0,
-            },
-            InsnInput {
-                insn: add,
-                input: 1,
-            },
-        ];
-
-        // TODO heap_addr legalization generates a uext64 *after* the shift, so these optimizations
-        // aren't happening in the wasm case. We could do better, given some range analysis.
-        let (base, index, shift) = if let Some((shift_input, shift_amt)) =
-            matches_small_constant_shift(ctx, add_inputs[0])
-        {
-            (
-                put_input_in_reg(ctx, add_inputs[1]),
-                put_input_in_reg(ctx, shift_input),
-                shift_amt,
-            )
-        } else if let Some((shift_input, shift_amt)) =
-            matches_small_constant_shift(ctx, add_inputs[1])
-        {
-            (
-                put_input_in_reg(ctx, add_inputs[0]),
-                put_input_in_reg(ctx, shift_input),
-                shift_amt,
-            )
-        } else {
-            for i in 0..=1 {
-                // Try to pierce through uextend.
-                if let Some(uextend) = matches_input(
-                    ctx,
-                    InsnInput {
-                        insn: add,
-                        input: i,
-                    },
-                    Opcode::Uextend,
-                ) {
-                    if let Some(cst) = ctx.get_input_as_source_or_const(uextend, 0).constant {
-                        // Zero the upper bits.
-                        let input_size = ctx.input_ty(uextend, 0).bits() as u64;
-                        let shift: u64 = 64 - input_size;
-                        let uext_cst: u64 = (cst << shift) >> shift;
-
-                        let final_offset = (offset as i64).wrapping_add(uext_cst as i64);
-                        if low32_will_sign_extend_to_64(final_offset as u64) {
-                            let base = put_input_in_reg(ctx, add_inputs[1 - i]);
-                            return Amode::imm_reg(final_offset as u32, base).with_flags(flags);
-                        }
-                    }
-                }
-
-                // If it's a constant, add it directly!
-                if let Some(cst) = ctx.get_input_as_source_or_const(add, i).constant {
-                    let final_offset = (offset as i64).wrapping_add(cst as i64);
-                    if low32_will_sign_extend_to_64(final_offset as u64) {
-                        let base = put_input_in_reg(ctx, add_inputs[1 - i]);
-                        return Amode::imm_reg(final_offset as u32, base).with_flags(flags);
-                    }
-                }
-            }
-
-            (
-                put_input_in_reg(ctx, add_inputs[0]),
-                put_input_in_reg(ctx, add_inputs[1]),
-                0,
-            )
-        };
-
-        return Amode::imm_reg_reg_shift(
-            offset as u32,
-            Gpr::new(base).unwrap(),
-            Gpr::new(index).unwrap(),
-            shift,
-        )
-        .with_flags(flags);
-    }
-
-    let input = put_input_in_reg(ctx, spec);
-    Amode::imm_reg(offset as u32, input).with_flags(flags)
-}
-
-//=============================================================================
-// Lowering-backend trait implementation.
-
-impl LowerBackend for X64Backend {
-    type MInst = Inst;
-
-    fn lower(&self, ctx: &mut Lower<Inst>, ir_inst: IRInst) -> Option<InstOutput> {
-        isle::lower(ctx, self, ir_inst)
-    }
-
-    fn lower_branch(
-        &self,
-        ctx: &mut Lower<Inst>,
-        ir_inst: IRInst,
-        targets: &[MachLabel],
-    ) -> Option<()> {
-        isle::lower_branch(ctx, self, ir_inst, targets)
-    }
-
-    fn maybe_pinned_reg(&self) -> Option<Reg> {
-        Some(regs::pinned_reg())
-    }
-}

data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/mod.rs

@@ -1,250 +0,0 @@
-//! X86_64-bit Instruction Set Architecture.
-
-pub use self::inst::{args, CallInfo, EmitInfo, EmitState, Inst};
-
-use super::{OwnedTargetIsa, TargetIsa};
-use crate::dominator_tree::DominatorTree;
-use crate::ir::{Function, Type};
-#[cfg(feature = "unwind")]
-use crate::isa::unwind::systemv;
-use crate::isa::x64::{inst::regs::create_reg_env_systemv, settings as x64_settings};
-use crate::isa::{Builder as IsaBuilder, FunctionAlignment};
-use crate::machinst::{
-    compile, CompiledCode, CompiledCodeStencil, MachInst, MachTextSectionBuilder, Reg, SigSet,
-    TextSectionBuilder, VCode,
-};
-use crate::result::{CodegenError, CodegenResult};
-use crate::settings::{self as shared_settings, Flags};
-use alloc::{boxed::Box, vec::Vec};
-use core::fmt;
-use cranelift_control::ControlPlane;
-use regalloc2::MachineEnv;
-use target_lexicon::Triple;
-
-mod abi;
-pub mod encoding;
-mod inst;
-mod lower;
-pub mod settings;
-
-/// An X64 backend.
-pub(crate) struct X64Backend {
-    triple: Triple,
-    flags: Flags,
-    x64_flags: x64_settings::Flags,
-    reg_env: MachineEnv,
-}
-
-impl X64Backend {
-    /// Create a new X64 backend with the given (shared) flags.
-    fn new_with_flags(triple: Triple, flags: Flags, x64_flags: x64_settings::Flags) -> Self {
-        let reg_env = create_reg_env_systemv(&flags);
-        Self {
-            triple,
-            flags,
-            x64_flags,
-            reg_env,
-        }
-    }
-
-    fn compile_vcode(
-        &self,
-        func: &Function,
-        domtree: &DominatorTree,
-        ctrl_plane: &mut ControlPlane,
-    ) -> CodegenResult<(VCode<inst::Inst>, regalloc2::Output)> {
-        // This performs lowering to VCode, register-allocates the code, computes
-        // block layout and finalizes branches. The result is ready for binary emission.
-        let emit_info = EmitInfo::new(self.flags.clone(), self.x64_flags.clone());
-        let sigs = SigSet::new::<abi::X64ABIMachineSpec>(func, &self.flags)?;
-        let abi = abi::X64Callee::new(func, self, &self.x64_flags, &sigs)?;
-        compile::compile::<Self>(func, domtree, self, abi, emit_info, sigs, ctrl_plane)
-    }
-}
-
-impl TargetIsa for X64Backend {
-    fn compile_function(
-        &self,
-        func: &Function,
-        domtree: &DominatorTree,
-        want_disasm: bool,
-        ctrl_plane: &mut ControlPlane,
-    ) -> CodegenResult<CompiledCodeStencil> {
-        let (vcode, regalloc_result) = self.compile_vcode(func, domtree, ctrl_plane)?;
-
-        let emit_result = vcode.emit(
-            &regalloc_result,
-            want_disasm,
-            self.flags.machine_code_cfg_info(),
-            ctrl_plane,
-        );
-        let frame_size = emit_result.frame_size;
-        let value_labels_ranges = emit_result.value_labels_ranges;
-        let buffer = emit_result.buffer.finish(ctrl_plane);
-        let sized_stackslot_offsets = emit_result.sized_stackslot_offsets;
-        let dynamic_stackslot_offsets = emit_result.dynamic_stackslot_offsets;
-
-        if let Some(disasm) = emit_result.disasm.as_ref() {
-            log::trace!("disassembly:\n{}", disasm);
-        }
-
-        Ok(CompiledCodeStencil {
-            buffer,
-            frame_size,
-            vcode: emit_result.disasm,
-            value_labels_ranges,
-            sized_stackslot_offsets,
-            dynamic_stackslot_offsets,
-            bb_starts: emit_result.bb_offsets,
-            bb_edges: emit_result.bb_edges,
-            alignment: emit_result.alignment,
-        })
-    }
-
-    fn flags(&self) -> &Flags {
-        &self.flags
-    }
-
-    fn machine_env(&self) -> &MachineEnv {
-        &self.reg_env
-    }
-
-    fn isa_flags(&self) -> Vec<shared_settings::Value> {
-        self.x64_flags.iter().collect()
-    }
-
-    fn dynamic_vector_bytes(&self, _dyn_ty: Type) -> u32 {
-        16
-    }
-
-    fn name(&self) -> &'static str {
-        "x64"
-    }
-
-    fn triple(&self) -> &Triple {
-        &self.triple
-    }
-
-    #[cfg(feature = "unwind")]
-    fn emit_unwind_info(
-        &self,
-        result: &CompiledCode,
-        kind: crate::machinst::UnwindInfoKind,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
-        use crate::isa::unwind::UnwindInfo;
-        use crate::machinst::UnwindInfoKind;
-        Ok(match kind {
-            UnwindInfoKind::SystemV => {
-                let mapper = self::inst::unwind::systemv::RegisterMapper;
-                Some(UnwindInfo::SystemV(
-                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
-                        &result.buffer.unwind_info[..],
-                        result.buffer.data().len(),
-                        &mapper,
-                    )?,
-                ))
-            }
-            UnwindInfoKind::Windows => Some(UnwindInfo::WindowsX64(
-                crate::isa::unwind::winx64::create_unwind_info_from_insts::<
-                    self::inst::unwind::winx64::RegisterMapper,
-                >(&result.buffer.unwind_info[..])?,
-            )),
-            _ => None,
-        })
-    }
-
-    #[cfg(feature = "unwind")]
-    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
-        Some(inst::unwind::systemv::create_cie())
-    }
-
-    #[cfg(feature = "unwind")]
-    fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
-        inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
-    }
-
-    fn text_section_builder(&self, num_funcs: usize) -> Box<dyn TextSectionBuilder> {
-        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
-    }
-
-    fn function_alignment(&self) -> FunctionAlignment {
-        Inst::function_alignment()
-    }
-
-    #[cfg(feature = "disas")]
-    fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
-        use capstone::prelude::*;
-        Capstone::new()
-            .x86()
-            .mode(arch::x86::ArchMode::Mode64)
-            .syntax(arch::x86::ArchSyntax::Att)
-            .build()
-    }
-
-    fn has_native_fma(&self) -> bool {
-        self.x64_flags.use_fma()
-    }
-}
-
-impl fmt::Display for X64Backend {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.debug_struct("MachBackend")
-            .field("name", &self.name())
-            .field("triple", &self.triple())
-            .field("flags", &format!("{}", self.flags()))
-            .finish()
-    }
-}
-
-/// Create a new `isa::Builder`.
-pub(crate) fn isa_builder(triple: Triple) -> IsaBuilder {
-    IsaBuilder {
-        triple,
-        setup: x64_settings::builder(),
-        constructor: isa_constructor,
-    }
-}
-
-fn isa_constructor(
-    triple: Triple,
-    shared_flags: Flags,
-    builder: &shared_settings::Builder,
-) -> CodegenResult<OwnedTargetIsa> {
-    let isa_flags = x64_settings::Flags::new(&shared_flags, builder);
-
-    // Check for compatibility between flags and ISA level
-    // requested. In particular, SIMD support requires SSE4.2.
-    if !cfg!(miri) && shared_flags.enable_simd() {
-        if !isa_flags.has_sse3() || !isa_flags.has_ssse3() || !isa_flags.has_sse41() {
-            return Err(CodegenError::Unsupported(
-                "SIMD support requires SSE3, SSSE3, and SSE4.1 on x86_64.".into(),
-            ));
-        }
-    }
-
-    let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags);
-    Ok(backend.wrapped())
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::settings;
-    use crate::settings::Configurable;
-
-    // Check that feature tests for SIMD work correctly.
-    #[test]
-    fn simd_required_features() {
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("enable_simd", "true").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let mut isa_builder = crate::isa::lookup_by_name("x86_64").unwrap();
-        isa_builder.set("has_sse3", "false").unwrap();
-        isa_builder.set("has_ssse3", "false").unwrap();
-        isa_builder.set("has_sse41", "false").unwrap();
-        assert!(matches!(
-            isa_builder.finish(shared_flags),
-            Err(CodegenError::Unsupported(_)),
-        ));
-    }
-}