wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,2915 @@
1
+ ;; Instruction formats.
2
+ (type MInst
3
+ (enum
4
+ ;; A no-op of zero size.
5
+ (Nop0)
6
+ (Nop4)
7
+
8
+ ;; load immediate
9
+ (Lui
10
+ (rd WritableReg)
11
+ (imm Imm20))
12
+
13
+ (LoadConst32
14
+ (rd WritableReg)
15
+ (imm u32))
16
+
17
+ (LoadConst64
18
+ (rd WritableReg)
19
+ (imm u64))
20
+
21
+ (Auipc
22
+ (rd WritableReg)
23
+ (imm Imm20))
24
+
25
+ ;; An ALU operation with one register sources and a register destination.
26
+ (FpuRR
27
+ (alu_op FpuOPRR)
28
+ (frm OptionFloatRoundingMode)
29
+ (rd WritableReg)
30
+ (rs Reg))
31
+
32
+
33
+ ;; An ALU operation with two register sources and a register destination.
34
+ (AluRRR
35
+ (alu_op AluOPRRR)
36
+ (rd WritableReg)
37
+ (rs1 Reg)
38
+ (rs2 Reg))
39
+
40
+ ;; An ALU operation with two register sources and a register destination.
41
+ (FpuRRR
42
+ (alu_op FpuOPRRR)
43
+ (frm OptionFloatRoundingMode)
44
+ (rd WritableReg)
45
+ (rs1 Reg)
46
+ (rs2 Reg))
47
+
48
+ ;; An ALU operation with three register sources and a register destination.
49
+ (FpuRRRR
50
+ (alu_op FpuOPRRRR)
51
+ (frm OptionFloatRoundingMode)
52
+ (rd WritableReg)
53
+ (rs1 Reg)
54
+ (rs2 Reg)
55
+ (rs3 Reg))
56
+
57
+ ;; An ALU operation with a register source and an immediate-12 source, and a register
58
+ ;; destination.
59
+ (AluRRImm12
60
+ (alu_op AluOPRRI)
61
+ (rd WritableReg)
62
+ (rs Reg)
63
+ (imm12 Imm12))
64
+
65
+ ;; An load
66
+ (Load
67
+ (rd WritableReg)
68
+ (op LoadOP)
69
+ (flags MemFlags)
70
+ (from AMode))
71
+ ;; An Store
72
+ (Store
73
+ (to AMode)
74
+ (op StoreOP)
75
+ (flags MemFlags)
76
+ (src Reg))
77
+
78
+ ;; A pseudo-instruction that captures register arguments in vregs.
79
+ (Args
80
+ (args VecArgPair))
81
+
82
+ (Ret (rets VecRetPair)
83
+ (stack_bytes_to_pop u32))
84
+
85
+ (Extend
86
+ (rd WritableReg)
87
+ (rn Reg)
88
+ (signed bool)
89
+ (from_bits u8)
90
+ (to_bits u8))
91
+
92
+ (AdjustSp
93
+ (amount i64))
94
+ (Call
95
+ (info BoxCallInfo))
96
+
97
+ ;; A machine indirect-call instruction.
98
+ (CallInd
99
+ (info BoxCallIndInfo))
100
+
101
+ (TrapIf
102
+ (test Reg)
103
+ (trap_code TrapCode))
104
+
105
+ ;; use a simple compare to decide to cause trap or not.
106
+ (TrapIfC
107
+ (rs1 Reg)
108
+ (rs2 Reg)
109
+ (cc IntCC)
110
+ (trap_code TrapCode))
111
+
112
+ (Jal
113
+ ;; (rd WritableReg) don't use
114
+ (dest BranchTarget))
115
+
116
+ (CondBr
117
+ (taken BranchTarget)
118
+ (not_taken BranchTarget)
119
+ (kind IntegerCompare))
120
+
121
+ ;; Load an inline symbol reference.
122
+ (LoadExtName
123
+ (rd WritableReg)
124
+ (name BoxExternalName)
125
+ (offset i64))
126
+
127
+ ;; Load address referenced by `mem` into `rd`.
128
+ (LoadAddr
129
+ (rd WritableReg)
130
+ (mem AMode))
131
+
132
+ ;; Marker, no-op in generated code: SP "virtual offset" is adjusted. This
133
+ ;; controls how AMode::NominalSPOffset args are lowered.
134
+ (VirtualSPOffsetAdj
135
+ (amount i64))
136
+
137
+ ;; A MOV instruction. These are encoded as OrR's (AluRRR form) but we
138
+ ;; keep them separate at the `Inst` level for better pretty-printing
139
+ ;; and faster `is_move()` logic.
140
+ (Mov
141
+ (rd WritableReg)
142
+ (rm Reg)
143
+ (ty Type))
144
+
145
+ ;; A MOV instruction, but where the source register is a non-allocatable
146
+ ;; PReg. It's important that the register be non-allocatable, as regalloc2
147
+ ;; will not see it as used.
148
+ (MovFromPReg
149
+ (rd WritableReg)
150
+ (rm PReg))
151
+
152
+ (Fence
153
+ (pred FenceReq)
154
+ (succ FenceReq))
155
+
156
+ (FenceI)
157
+
158
+ (ECall)
159
+
160
+ (EBreak)
161
+
162
+ ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
163
+ ;; runtime.
164
+ (Udf
165
+ (trap_code TrapCode))
166
+ ;; a jump and link register operation
167
+ (Jalr
168
+ ;;Plain unconditional jumps (assembler pseudo-op J) are encoded as a JAL with rd=x0.
169
+ (rd WritableReg)
170
+ (base Reg)
171
+ (offset Imm12))
172
+
173
+ ;; atomic operations.
174
+ (Atomic
175
+ (op AtomicOP)
176
+ (rd WritableReg)
177
+ (addr Reg)
178
+ (src Reg)
179
+ (amo AMO))
180
+ ;; an atomic store
181
+ (AtomicStore
182
+ (src Reg)
183
+ (ty Type)
184
+ (p Reg))
185
+ ;; an atomic load.
186
+ (AtomicLoad
187
+ (rd WritableReg)
188
+ (ty Type)
189
+ (p Reg))
190
+
191
+ ;; an atomic nand need using loop to implement.
192
+ (AtomicRmwLoop
193
+ (offset Reg)
194
+ (op AtomicRmwOp)
195
+ (dst WritableReg)
196
+ (ty Type)
197
+ (p Reg)
198
+ (x Reg)
199
+ (t0 WritableReg))
200
+
201
+ ;; select x or y base on condition
202
+ (Select
203
+ (dst VecWritableReg)
204
+ (ty Type)
205
+ (condition Reg)
206
+ (x ValueRegs)
207
+ (y ValueRegs))
208
+
209
+ (BrTable
210
+ (index Reg)
211
+ (tmp1 WritableReg)
212
+ (tmp2 WritableReg)
213
+ (targets VecBranchTarget))
214
+
215
+ ;; atomic compare and set operation
216
+ (AtomicCas
217
+ (offset Reg)
218
+ (t0 WritableReg)
219
+ (dst WritableReg)
220
+ (e Reg)
221
+ (addr Reg)
222
+ (v Reg)
223
+ (ty Type))
224
+ ;; select x or y base on op_code
225
+ (IntSelect
226
+ (op IntSelectOP)
227
+ (dst VecWritableReg)
228
+ (x ValueRegs)
229
+ (y ValueRegs)
230
+ (ty Type))
231
+ ;; an integer compare.
232
+ (Icmp
233
+ (cc IntCC)
234
+ (rd WritableReg)
235
+ (a ValueRegs)
236
+ (b ValueRegs)
237
+ (ty Type))
238
+ ;; select a reg base on condition.
239
+ ;; very useful because in lowering stage we can not have condition branch.
240
+ (SelectReg
241
+ (rd WritableReg)
242
+ (rs1 Reg)
243
+ (rs2 Reg)
244
+ (condition IntegerCompare))
245
+ ;;
246
+ (FcvtToInt
247
+ (is_sat bool)
248
+ (rd WritableReg)
249
+ (tmp WritableReg) ;; a float register to load bounds.
250
+ (rs Reg)
251
+ (is_signed bool)
252
+ (in_type Type)
253
+ (out_type Type))
254
+
255
+ (RawData (data VecU8))
256
+
257
+ ;; An unwind pseudo-instruction.
258
+ (Unwind
259
+ (inst UnwindInst))
260
+
261
+ ;; A dummy use, useful to keep a value alive.
262
+ (DummyUse
263
+ (reg Reg))
264
+ ;;;
265
+ (FloatRound
266
+ (op FloatRoundOP)
267
+ (rd WritableReg)
268
+ (int_tmp WritableReg)
269
+ (f_tmp WritableReg)
270
+ (rs Reg)
271
+ (ty Type))
272
+ ;;;; FMax
273
+ (FloatSelect
274
+ (op FloatSelectOP)
275
+ (rd WritableReg)
276
+ ;; a integer register
277
+ (tmp WritableReg)
278
+ (rs1 Reg)
279
+ (rs2 Reg)
280
+ (ty Type))
281
+ (FloatSelectPseudo
282
+ (op FloatSelectOP)
283
+ (rd WritableReg)
284
+ ;; a integer register
285
+ (tmp WritableReg)
286
+ (rs1 Reg)
287
+ (rs2 Reg)
288
+ (ty Type))
289
+
290
+ ;; popcnt if target doesn't support extension B
291
+ ;; use iteration to implement.
292
+ (Popcnt
293
+ (sum WritableReg)
294
+ (step WritableReg)
295
+ (tmp WritableReg)
296
+ (rs Reg)
297
+ (ty Type))
298
+
299
+ ;;; counting leading or trailing zeros.
300
+ (Cltz
301
+ ;; leading or trailing.
302
+ (leading bool)
303
+ (sum WritableReg)
304
+ (step WritableReg)
305
+ (tmp WritableReg)
306
+ (rs Reg)
307
+ (ty Type))
308
+ ;; Byte-reverse register
309
+ (Rev8
310
+ (rs Reg)
311
+ (step WritableReg)
312
+ (tmp WritableReg)
313
+ (rd WritableReg))
314
+ ;;
315
+ (Brev8
316
+ (rs Reg)
317
+ (ty Type)
318
+ (step WritableReg)
319
+ (tmp WritableReg)
320
+ (tmp2 WritableReg)
321
+ (rd WritableReg))
322
+ (StackProbeLoop
323
+ (guard_size u32)
324
+ (probe_count u32)
325
+ (tmp WritableReg))
326
+
327
+ (VecAluRRR
328
+ (op VecAluOpRRR)
329
+ (vd WritableReg)
330
+ (vs2 Reg)
331
+ (vs1 Reg)
332
+ (mask VecOpMasking)
333
+ (vstate VState))
334
+
335
+ (VecAluRRImm5
336
+ (op VecAluOpRRImm5)
337
+ (vd WritableReg)
338
+ (vs2 Reg)
339
+ (imm Imm5)
340
+ (mask VecOpMasking)
341
+ (vstate VState))
342
+
343
+ (VecAluRR
344
+ (op VecAluOpRR)
345
+ (vd WritableReg)
346
+ (vs Reg)
347
+ (mask VecOpMasking)
348
+ (vstate VState))
349
+
350
+ (VecAluRImm5
351
+ (op VecAluOpRImm5)
352
+ (vd WritableReg)
353
+ (imm Imm5)
354
+ (mask VecOpMasking)
355
+ (vstate VState))
356
+
357
+ (VecSetState
358
+ (rd WritableReg)
359
+ (vstate VState))
360
+
361
+ (VecLoad
362
+ (eew VecElementWidth)
363
+ (to WritableReg)
364
+ (from VecAMode)
365
+ (flags MemFlags)
366
+ (mask VecOpMasking)
367
+ (vstate VState))
368
+
369
+ (VecStore
370
+ (eew VecElementWidth)
371
+ (to VecAMode)
372
+ (from Reg)
373
+ (flags MemFlags)
374
+ (mask VecOpMasking)
375
+ (vstate VState))
376
+ ))
377
+
378
+
379
+ (type FloatSelectOP (enum
380
+ (Max)
381
+ (Min)
382
+ ))
383
+
384
+ (type FloatRoundOP (enum
385
+ (Nearest)
386
+ (Ceil)
387
+ (Floor)
388
+ (Trunc)
389
+ ))
390
+
391
+ (type IntSelectOP (enum
392
+ (Smax)
393
+ (Umax)
394
+ (Smin)
395
+ (Umin)
396
+ ))
397
+
398
+ (type AtomicOP (enum
399
+ (LrW)
400
+ (ScW)
401
+ (AmoswapW)
402
+ (AmoaddW)
403
+ (AmoxorW)
404
+ (AmoandW)
405
+ (AmoorW)
406
+ (AmominW)
407
+ (AmomaxW)
408
+ (AmominuW)
409
+ (AmomaxuW)
410
+ (LrD)
411
+ (ScD)
412
+ (AmoswapD)
413
+ (AmoaddD)
414
+ (AmoxorD)
415
+ (AmoandD)
416
+ (AmoorD)
417
+ (AmominD)
418
+ (AmomaxD)
419
+ (AmominuD)
420
+ (AmomaxuD)
421
+ ))
422
+
423
+ (type FpuOPRRRR (enum
424
+ ;; float32
425
+ (FmaddS)
426
+ (FmsubS)
427
+ (FnmsubS)
428
+ (FnmaddS)
429
+ ;; float64
430
+ (FmaddD)
431
+ (FmsubD)
432
+ (FnmsubD)
433
+ (FnmaddD)
434
+ ))
435
+
436
+ (type FClassResult (enum
437
+ ;;0 rs1 is −∞.
438
+ (NegInfinite)
439
+ ;; 1 rs1 is a negative normal number.
440
+ (NegNormal)
441
+ ;; 2 rs1 is a negative subnormal number.
442
+ (NegSubNormal)
443
+ ;; 3 rs1 is −0.
444
+ (NegZero)
445
+ ;; 4 rs1 is +0.
446
+ (PosZero)
447
+ ;; 5 rs1 is a positive subnormal number.
448
+ (PosSubNormal)
449
+ ;; 6 rs1 is a positive normal number.
450
+ (PosNormal)
451
+ ;; 7 rs1 is +∞.
452
+ (PosInfinite)
453
+ ;; 8 rs1 is a signaling NaN.
454
+ (SNaN)
455
+ ;; 9 rs1 is a quiet NaN.
456
+ (QNaN)
457
+ ))
458
+
459
+ (type FpuOPRR (enum
460
+ ;; RV32F Standard Extension
461
+ (FsqrtS)
462
+ (FcvtWS)
463
+ (FcvtWuS)
464
+ (FmvXW)
465
+ (FclassS)
466
+ (FcvtSw)
467
+ (FcvtSwU)
468
+ (FmvWX)
469
+
470
+
471
+ ;; RV64F Standard Extension (in addition to RV32F)
472
+ (FcvtLS)
473
+ (FcvtLuS)
474
+ (FcvtSL)
475
+ (FcvtSLU)
476
+
477
+
478
+ ;; RV64D Standard Extension (in addition to RV32D)
479
+ (FcvtLD)
480
+ (FcvtLuD)
481
+ (FmvXD)
482
+ (FcvtDL)
483
+ (FcvtDLu)
484
+ (FmvDX)
485
+
486
+ ;; RV32D Standard Extension
487
+ (FsqrtD)
488
+ (FcvtSD)
489
+ (FcvtDS)
490
+ (FclassD)
491
+ (FcvtWD)
492
+ (FcvtWuD)
493
+ (FcvtDW)
494
+ (FcvtDWU)
495
+ ;; bitmapip
496
+
497
+ ))
498
+
499
+ (type LoadOP (enum
500
+ (Lb)
501
+ (Lh)
502
+ (Lw)
503
+ (Lbu)
504
+ (Lhu)
505
+ (Lwu)
506
+ (Ld)
507
+ (Flw)
508
+ (Fld)
509
+ ))
510
+
511
+ (type StoreOP (enum
512
+ (Sb)
513
+ (Sh)
514
+ (Sw)
515
+ (Sd)
516
+ (Fsw)
517
+ (Fsd)
518
+ ))
519
+
520
+ (type AluOPRRR (enum
521
+ ;; base set
522
+ (Add)
523
+ (Sub)
524
+ (Sll)
525
+ (Slt)
526
+ (SltU)
527
+ (Sgt)
528
+ (Sgtu)
529
+ (Xor)
530
+ (Srl)
531
+ (Sra)
532
+ (Or)
533
+ (And)
534
+
535
+ ;; RV64I Base Instruction Set (in addition to RV32I)
536
+ (Addw)
537
+ (Subw)
538
+ (Sllw)
539
+ (Srlw)
540
+ (Sraw)
541
+
542
+
543
+ ;;RV32M Standard Extension
544
+ (Mul)
545
+ (Mulh)
546
+ (Mulhsu)
547
+ (Mulhu)
548
+ (Div)
549
+ (DivU)
550
+ (Rem)
551
+ (RemU)
552
+
553
+ ;; RV64M Standard Extension (in addition to RV32M)
554
+ (Mulw)
555
+ (Divw)
556
+ (Divuw)
557
+ (Remw)
558
+ (Remuw)
559
+
560
+ ;; Zba: Address Generation Instructions
561
+ (Adduw)
562
+ (Sh1add)
563
+ (Sh1adduw)
564
+ (Sh2add)
565
+ (Sh2adduw)
566
+ (Sh3add)
567
+ (Sh3adduw)
568
+
569
+ ;; Zbb: Bit Manipulation Instructions
570
+ (Andn)
571
+ (Orn)
572
+ (Xnor)
573
+ (Max)
574
+ (Maxu)
575
+ (Min)
576
+ (Minu)
577
+ (Rol)
578
+ (Rolw)
579
+ (Ror)
580
+ (Rorw)
581
+
582
+ ;; Zbs: Single-bit instructions
583
+ (Bclr)
584
+ (Bext)
585
+ (Binv)
586
+ (Bset)
587
+
588
+ ;; Zbc: Carry-less multiplication
589
+ (Clmul)
590
+ (Clmulh)
591
+ (Clmulr)
592
+
593
+ ;; Zbkb: Bit-manipulation for Cryptography
594
+ (Pack)
595
+ (Packw)
596
+ (Packh)
597
+ ))
598
+
599
+
600
+ (type FpuOPRRR (enum
601
+ ;; RV32F Standard Extension
602
+ (FaddS)
603
+ (FsubS)
604
+ (FmulS)
605
+ (FdivS)
606
+
607
+ (FsgnjS)
608
+ (FsgnjnS)
609
+ (FsgnjxS)
610
+ (FminS)
611
+ (FmaxS)
612
+ (FeqS)
613
+ (FltS)
614
+ (FleS)
615
+
616
+ ;; RV32D Standard Extension
617
+ (FaddD)
618
+ (FsubD)
619
+ (FmulD)
620
+ (FdivD)
621
+ (FsgnjD)
622
+ (FsgnjnD)
623
+ (FsgnjxD)
624
+ (FminD)
625
+ (FmaxD)
626
+ (FeqD)
627
+ (FltD)
628
+ (FleD)
629
+ ))
630
+
631
+
632
+
633
+ (type AluOPRRI (enum
634
+ ;; Base ISA
635
+ (Addi)
636
+ (Slti)
637
+ (SltiU)
638
+ (Xori)
639
+ (Ori)
640
+ (Andi)
641
+ (Slli)
642
+ (Srli)
643
+ (Srai)
644
+ (Addiw)
645
+ (Slliw)
646
+ (SrliW)
647
+ (Sraiw)
648
+
649
+ ;; Zba: Address Generation Instructions
650
+ (SlliUw)
651
+
652
+ ;; Zbb: Bit Manipulation Instructions
653
+ (Clz)
654
+ (Clzw)
655
+ (Ctz)
656
+ (Ctzw)
657
+ (Cpop)
658
+ (Cpopw)
659
+ (Sextb)
660
+ (Sexth)
661
+ (Zexth)
662
+ (Rori)
663
+ (Roriw)
664
+ (Rev8)
665
+ (Brev8)
666
+ (Orcb)
667
+
668
+ ;; Zbs: Single-bit instructions
669
+ (Bclri)
670
+ (Bexti)
671
+ (Binvi)
672
+ (Bseti)
673
+ ))
674
+
675
+
676
+ (type FRM (enum
677
+ ;; Round to Nearest, ties to Even
678
+ (RNE)
679
+ ;; Round towards Zero
680
+ (RTZ)
681
+ ;; Round Down (towards −∞)
682
+ (RDN)
683
+ ;; Round Up (towards +∞)
684
+ (RUP)
685
+ ;; Round to Nearest, ties to Max Magnitude
686
+ (RMM)
687
+ ;; In instruction’s rm field, selects dynamic rounding mode;
688
+ ;;In Rounding Mode register, Invalid.
689
+ (Fcsr)
690
+ ))
691
+
692
+ (type FFlagsException (enum
693
+ ;; Invalid Operation
694
+ (NV)
695
+ ;; Divide by Zero
696
+ (DZ)
697
+ ;; Overflow
698
+ (OF)
699
+ ;; Underflow
700
+ (UF)
701
+ ;; Inexact
702
+ (NX)
703
+ ))
704
+
705
+ ;;;; input output read write
706
+ ;;;; SI SO SR SW
707
+ ;;;; PI PO PR PW
708
+ ;;;; lowest four bit are used.
709
+ (type FenceReq (primitive u8))
710
+
711
+ (type VecBranchTarget (primitive VecBranchTarget))
712
+ (type BoxCallInfo (primitive BoxCallInfo))
713
+ (type BoxCallIndInfo (primitive BoxCallIndInfo))
714
+ (type IntegerCompare (primitive IntegerCompare))
715
+ (type AMode (primitive AMode))
716
+ (type OptionReg (primitive OptionReg))
717
+ (type OptionImm12 (primitive OptionImm12))
718
+ (type OptionUimm5 (primitive OptionUimm5))
719
+ (type Imm12 (primitive Imm12))
720
+ (type UImm5 (primitive UImm5))
721
+ (type Imm5 (primitive Imm5))
722
+ (type Imm20 (primitive Imm20))
723
+ (type Imm3 (primitive Imm3))
724
+ (type BranchTarget (primitive BranchTarget))
725
+ (type OptionFloatRoundingMode (primitive OptionFloatRoundingMode))
726
+ (type VecU8 (primitive VecU8))
727
+ (type AMO (primitive AMO))
728
+ (type VecMachLabel extern (enum))
729
+
730
+
731
+ ;;;; Newtypes for Different Register Classes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
732
+
733
+ (type XReg (primitive XReg))
734
+ (type WritableXReg (primitive WritableXReg))
735
+ (type FReg (primitive FReg))
736
+ (type WritableFReg (primitive WritableFReg))
737
+ (type VReg (primitive VReg))
738
+ (type WritableVReg (primitive WritableVReg))
739
+
740
+ ;; Construct a new `XReg` from a `Reg`.
741
+ ;;
742
+ ;; Asserts that the register has a Integer RegClass.
743
+ (decl xreg_new (Reg) XReg)
744
+ (extern constructor xreg_new xreg_new)
745
+ (convert Reg XReg xreg_new)
746
+
747
+ ;; Construct a new `WritableXReg` from a `WritableReg`.
748
+ ;;
749
+ ;; Asserts that the register has a Integer RegClass.
750
+ (decl writable_xreg_new (WritableReg) WritableXReg)
751
+ (extern constructor writable_xreg_new writable_xreg_new)
752
+ (convert WritableReg WritableXReg writable_xreg_new)
753
+
754
+ ;; Put a value into a XReg.
755
+ ;;
756
+ ;; Asserts that the value goes into a XReg.
757
+ (decl put_in_xreg (Value) XReg)
758
+ (rule (put_in_xreg val) (xreg_new (put_in_reg val)))
759
+ (convert Value XReg put_in_xreg)
760
+
761
+ ;; Construct an `InstOutput` out of a single XReg register.
762
+ (decl output_xreg (XReg) InstOutput)
763
+ (rule (output_xreg x) (output_reg x))
764
+ (convert XReg InstOutput output_xreg)
765
+
766
+ ;; Convert a `WritableXReg` to an `XReg`.
767
+ (decl pure writable_xreg_to_xreg (WritableXReg) XReg)
768
+ (extern constructor writable_xreg_to_xreg writable_xreg_to_xreg)
769
+ (convert WritableXReg XReg writable_xreg_to_xreg)
770
+
771
+ ;; Convert a `WritableXReg` to an `WritableReg`.
772
+ (decl pure writable_xreg_to_writable_reg (WritableXReg) WritableReg)
773
+ (extern constructor writable_xreg_to_writable_reg writable_xreg_to_writable_reg)
774
+ (convert WritableXReg WritableReg writable_xreg_to_writable_reg)
775
+
776
+ ;; Convert a `WritableXReg` to an `Reg`.
777
+ (decl pure writable_xreg_to_reg (WritableXReg) Reg)
778
+ (rule (writable_xreg_to_reg x) (writable_xreg_to_writable_reg x))
779
+ (convert WritableXReg Reg writable_xreg_to_reg)
780
+
781
+ ;; Convert an `XReg` to a `Reg`.
782
+ (decl pure xreg_to_reg (XReg) Reg)
783
+ (extern constructor xreg_to_reg xreg_to_reg)
784
+ (convert XReg Reg xreg_to_reg)
785
+
786
+ ;; Convert a `XReg` to a `ValueRegs`.
787
+ (decl xreg_to_value_regs (XReg) ValueRegs)
788
+ (rule (xreg_to_value_regs x) (value_reg x))
789
+ (convert XReg ValueRegs xreg_to_reg)
790
+
791
+ ;; Convert a `WritableXReg` to a `ValueRegs`.
792
+ (decl writable_xreg_to_value_regs (WritableXReg) ValueRegs)
793
+ (rule (writable_xreg_to_value_regs x) (value_reg x))
794
+ (convert WritableXReg ValueRegs writable_xreg_to_value_regs)
795
+
796
+ ;; Allocates a new `WritableXReg`.
797
+ (decl temp_writable_xreg () WritableXReg)
798
+ (rule (temp_writable_xreg) (temp_writable_reg $I64))
799
+
800
+
801
+ ;; Construct a new `FReg` from a `Reg`.
802
+ ;;
803
+ ;; Asserts that the register has a Float RegClass.
804
+ (decl freg_new (Reg) FReg)
805
+ (extern constructor freg_new freg_new)
806
+ (convert Reg FReg freg_new)
807
+
808
+ ;; Construct a new `WritableFReg` from a `WritableReg`.
809
+ ;;
810
+ ;; Asserts that the register has a Float RegClass.
811
+ (decl writable_freg_new (WritableReg) WritableFReg)
812
+ (extern constructor writable_freg_new writable_freg_new)
813
+ (convert WritableReg WritableFReg writable_freg_new)
814
+
815
+ ;; Put a value into a FReg.
816
+ ;;
817
+ ;; Asserts that the value goes into a FReg.
818
+ (decl put_in_freg (Value) FReg)
819
+ (rule (put_in_freg val) (freg_new (put_in_reg val)))
820
+ (convert Value FReg put_in_freg)
821
+
822
+ ;; Construct an `InstOutput` out of a single FReg register.
823
+ (decl output_freg (FReg) InstOutput)
824
+ (rule (output_freg x) (output_reg x))
825
+ (convert FReg InstOutput output_freg)
826
+
827
+ ;; Convert a `WritableFReg` to an `FReg`.
828
+ (decl pure writable_freg_to_freg (WritableFReg) FReg)
829
+ (extern constructor writable_freg_to_freg writable_freg_to_freg)
830
+ (convert WritableFReg FReg writable_freg_to_freg)
831
+
832
+ ;; Convert a `WritableFReg` to an `WritableReg`.
833
+ (decl pure writable_freg_to_writable_reg (WritableFReg) WritableReg)
834
+ (extern constructor writable_freg_to_writable_reg writable_freg_to_writable_reg)
835
+ (convert WritableFReg WritableReg writable_freg_to_writable_reg)
836
+
837
+ ;; Convert a `WritableFReg` to an `Reg`.
838
+ (decl pure writable_freg_to_reg (WritableFReg) Reg)
839
+ (rule (writable_freg_to_reg x) (writable_freg_to_writable_reg x))
840
+ (convert WritableFReg Reg writable_freg_to_reg)
841
+
842
+ ;; Convert an `FReg` to a `Reg`.
843
+ (decl pure freg_to_reg (FReg) Reg)
844
+ (extern constructor freg_to_reg freg_to_reg)
845
+ (convert FReg Reg freg_to_reg)
846
+
847
+ ;; Convert a `FReg` to a `ValueRegs`.
848
+ (decl freg_to_value_regs (FReg) ValueRegs)
849
+ (rule (freg_to_value_regs x) (value_reg x))
850
+ (convert FReg ValueRegs xreg_to_reg)
851
+
852
+ ;; Convert a `WritableFReg` to a `ValueRegs`.
853
+ (decl writable_freg_to_value_regs (WritableFReg) ValueRegs)
854
+ (rule (writable_freg_to_value_regs x) (value_reg x))
855
+ (convert WritableFReg ValueRegs writable_freg_to_value_regs)
856
+
857
+ ;; Allocates a new `WritableFReg`.
858
+ (decl temp_writable_freg () WritableFReg)
859
+ (rule (temp_writable_freg) (temp_writable_reg $F64))
860
+
861
+
862
+
863
+ ;; Construct a new `VReg` from a `Reg`.
864
+ ;;
865
+ ;; Asserts that the register has a Vector RegClass.
866
+ (decl vreg_new (Reg) VReg)
867
+ (extern constructor vreg_new vreg_new)
868
+ (convert Reg VReg vreg_new)
869
+
870
+ ;; Construct a new `WritableVReg` from a `WritableReg`.
871
+ ;;
872
+ ;; Asserts that the register has a Vector RegClass.
873
+ (decl writable_vreg_new (WritableReg) WritableVReg)
874
+ (extern constructor writable_vreg_new writable_vreg_new)
875
+ (convert WritableReg WritableVReg writable_vreg_new)
876
+
877
+ ;; Put a value into a VReg.
878
+ ;;
879
+ ;; Asserts that the value goes into a VReg.
880
+ (decl put_in_vreg (Value) VReg)
881
+ (rule (put_in_vreg val) (vreg_new (put_in_reg val)))
882
+ (convert Value VReg put_in_vreg)
883
+
884
+ ;; Construct an `InstOutput` out of a single VReg register.
885
+ (decl output_vreg (VReg) InstOutput)
886
+ (rule (output_vreg x) (output_reg x))
887
+ (convert VReg InstOutput output_vreg)
888
+
889
+ ;; Convert a `WritableVReg` to an `VReg`.
890
+ (decl pure writable_vreg_to_vreg (WritableVReg) VReg)
891
+ (extern constructor writable_vreg_to_vreg writable_vreg_to_vreg)
892
+ (convert WritableVReg VReg writable_vreg_to_vreg)
893
+
894
+ ;; Convert a `WritableVReg` to an `WritableReg`.
895
+ (decl pure writable_vreg_to_writable_reg (WritableVReg) WritableReg)
896
+ (extern constructor writable_vreg_to_writable_reg writable_vreg_to_writable_reg)
897
+ (convert WritableVReg WritableReg writable_vreg_to_writable_reg)
898
+
899
+ ;; Convert a `WritableVReg` to an `Reg`.
900
+ (decl pure writable_vreg_to_reg (WritableVReg) Reg)
901
+ (rule (writable_vreg_to_reg x) (writable_vreg_to_writable_reg x))
902
+ (convert WritableVReg Reg writable_vreg_to_reg)
903
+
904
+ ;; Convert an `VReg` to a `Reg`.
905
+ (decl pure vreg_to_reg (VReg) Reg)
906
+ (extern constructor vreg_to_reg vreg_to_reg)
907
+ (convert VReg Reg vreg_to_reg)
908
+
909
+ ;; Convert a `VReg` to a `ValueRegs`.
910
+ (decl vreg_to_value_regs (VReg) ValueRegs)
911
+ (rule (vreg_to_value_regs x) (value_reg x))
912
+ (convert VReg ValueRegs xreg_to_reg)
913
+
914
+ ;; Convert a `WritableVReg` to a `ValueRegs`.
915
+ (decl writable_vreg_to_value_regs (WritableVReg) ValueRegs)
916
+ (rule (writable_vreg_to_value_regs x) (value_reg x))
917
+ (convert WritableVReg ValueRegs writable_vreg_to_value_regs)
918
+
919
+ ;; Allocates a new `WritableVReg`.
920
+ (decl temp_writable_vreg () WritableVReg)
921
+ (rule (temp_writable_vreg) (temp_writable_reg $I8X16))
922
+
923
+
924
+ ;; Converters
925
+
926
+ (convert u8 i32 u8_as_i32)
927
+ (decl u8_as_i32 (u8) i32)
928
+ (extern constructor u8_as_i32 u8_as_i32)
929
+
930
+ ;; ISA Extension helpers
931
+
932
+ (decl pure has_v () bool)
933
+ (extern constructor has_v has_v)
934
+
935
+ (decl pure has_zbkb () bool)
936
+ (extern constructor has_zbkb has_zbkb)
937
+
938
+ (decl pure has_zba () bool)
939
+ (extern constructor has_zba has_zba)
940
+
941
+ (decl pure has_zbb () bool)
942
+ (extern constructor has_zbb has_zbb)
943
+
944
+ (decl pure has_zbc () bool)
945
+ (extern constructor has_zbc has_zbc)
946
+
947
+ (decl pure has_zbs () bool)
948
+ (extern constructor has_zbs has_zbs)
949
+
950
+ (decl gen_float_round (FloatRoundOP Reg Type) Reg)
951
+ (rule
952
+ (gen_float_round op rs ty)
953
+ (let
954
+ ((rd WritableReg (temp_writable_reg ty))
955
+ (tmp WritableXReg (temp_writable_xreg))
956
+ (tmp2 WritableFReg (temp_writable_freg))
957
+ (_ Unit (emit (MInst.FloatRound op rd tmp tmp2 rs ty))))
958
+ (writable_reg_to_reg rd)))
959
+
960
+ (decl gen_float_select_pseudo (FloatSelectOP Reg Reg Type) Reg)
961
+ (rule
962
+ (gen_float_select_pseudo op x y ty)
963
+ (let
964
+ ((rd WritableReg (temp_writable_reg ty))
965
+ (tmp WritableXReg (temp_writable_xreg))
966
+ (_ Unit (emit (MInst.FloatSelectPseudo op rd tmp x y ty))))
967
+ (writable_reg_to_reg rd)))
968
+
969
+ (decl gen_float_select (FloatSelectOP Reg Reg Type) Reg)
970
+ (rule
971
+ (gen_float_select op x y ty)
972
+ (let
973
+ ((rd WritableReg (temp_writable_reg ty))
974
+ (tmp WritableXReg (temp_writable_xreg))
975
+ (_ Unit (emit (MInst.FloatSelect op rd tmp x y ty))))
976
+ (writable_reg_to_reg rd)))
977
+
978
+
979
+ ;;;; Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
980
+
981
+ ;; RV32I Base Integer Instruction Set
982
+
983
+ ;; Helper for emitting the `add` instruction.
984
+ ;; rd ← rs1 + rs2
985
+ (decl rv_add (XReg XReg) XReg)
986
+ (rule (rv_add rs1 rs2)
987
+ (alu_rrr (AluOPRRR.Add) rs1 rs2))
988
+
989
+ ;; Helper for emitting the `addi` ("Add Immediate") instruction.
990
+ ;; rd ← rs1 + sext(imm)
991
+ (decl rv_addi (XReg Imm12) XReg)
992
+ (rule (rv_addi rs1 imm)
993
+ (alu_rr_imm12 (AluOPRRI.Addi) rs1 imm))
994
+
995
+ ;; Helper for emitting the `sub` instruction.
996
+ ;; rd ← rs1 - rs2
997
+ (decl rv_sub (XReg XReg) XReg)
998
+ (rule (rv_sub rs1 rs2)
999
+ (alu_rrr (AluOPRRR.Sub) rs1 rs2))
1000
+
1001
+ ;; Helper for emitting the `neg` instruction.
1002
+ ;; This instruction is a mnemonic for `sub rd, zero, rs1`.
1003
+ (decl rv_neg (XReg) XReg)
1004
+ (rule (rv_neg rs1)
1005
+ (alu_rrr (AluOPRRR.Sub) (zero_reg) rs1))
1006
+
1007
+ ;; Helper for emitting the `sll` ("Shift Left Logical") instruction.
1008
+ ;; rd ← rs1 << rs2
1009
+ (decl rv_sll (XReg XReg) XReg)
1010
+ (rule (rv_sll rs1 rs2)
1011
+ (alu_rrr (AluOPRRR.Sll) rs1 rs2))
1012
+
1013
+ ;; Helper for emitting the `slli` ("Shift Left Logical Immediate") instruction.
1014
+ ;; rd ← rs1 << uext(imm)
1015
+ (decl rv_slli (XReg Imm12) XReg)
1016
+ (rule (rv_slli rs1 imm)
1017
+ (alu_rr_imm12 (AluOPRRI.Slli) rs1 imm))
1018
+
1019
+ ;; Helper for emitting the `srl` ("Shift Right Logical") instruction.
1020
+ ;; rd ← rs1 >> rs2
1021
+ (decl rv_srl (XReg XReg) XReg)
1022
+ (rule (rv_srl rs1 rs2)
1023
+ (alu_rrr (AluOPRRR.Srl) rs1 rs2))
1024
+
1025
+ ;; Helper for emitting the `srli` ("Shift Right Logical Immediate") instruction.
1026
+ ;; rd ← rs1 >> uext(imm)
1027
+ (decl rv_srli (XReg Imm12) XReg)
1028
+ (rule (rv_srli rs1 imm)
1029
+ (alu_rr_imm12 (AluOPRRI.Srli) rs1 imm))
1030
+
1031
+ ;; Helper for emitting the `sra` ("Shift Right Arithmetic") instruction.
1032
+ ;; rd ← rs1 >> rs2
1033
+ (decl rv_sra (XReg XReg) XReg)
1034
+ (rule (rv_sra rs1 rs2)
1035
+ (alu_rrr (AluOPRRR.Sra) rs1 rs2))
1036
+
1037
+ ;; Helper for emitting the `srai` ("Shift Right Arithmetic Immediate") instruction.
1038
+ ;; rd ← rs1 >> uext(imm)
1039
+ (decl rv_srai (XReg Imm12) XReg)
1040
+ (rule (rv_srai rs1 imm)
1041
+ (alu_rr_imm12 (AluOPRRI.Srai) rs1 imm))
1042
+
1043
+ ;; Helper for emitting the `or` instruction.
1044
+ ;; rd ← rs1 ∨ rs2
1045
+ (decl rv_or (XReg XReg) XReg)
1046
+ (rule (rv_or rs1 rs2)
1047
+ (alu_rrr (AluOPRRR.Or) rs1 rs2))
1048
+
1049
+ ;; Helper for emitting the `ori` ("Or Immediate") instruction.
1050
+ ;; rd ← rs1 ∨ uext(imm)
1051
+ (decl rv_ori (XReg Imm12) XReg)
1052
+ (rule (rv_ori rs1 imm)
1053
+ (alu_rr_imm12 (AluOPRRI.Ori) rs1 imm))
1054
+
1055
+ ;; Helper for emitting the `xor` instruction.
1056
+ ;; rd ← rs1 ⊕ rs2
1057
+ (decl rv_xor (XReg XReg) XReg)
1058
+ (rule (rv_xor rs1 rs2)
1059
+ (alu_rrr (AluOPRRR.Xor) rs1 rs2))
1060
+
1061
+ ;; Helper for emitting the `xori` ("Exlusive Or Immediate") instruction.
1062
+ ;; rd ← rs1 ⊕ uext(imm)
1063
+ (decl rv_xori (XReg Imm12) XReg)
1064
+ (rule (rv_xori rs1 imm)
1065
+ (alu_rr_imm12 (AluOPRRI.Xori) rs1 imm))
1066
+
1067
+ ;; Helper for emitting the `not` instruction.
1068
+ ;; This instruction is a mnemonic for `xori rd, rs1, -1`.
1069
+ (decl rv_not (XReg) XReg)
1070
+ (rule (rv_not rs1)
1071
+ (rv_xori rs1 (imm12_const -1)))
1072
+
1073
+ ;; Helper for emitting the `and` instruction.
1074
+ ;; rd ← rs1 ∧ rs2
1075
+ (decl rv_and (XReg XReg) XReg)
1076
+ (rule (rv_and rs1 rs2)
1077
+ (alu_rrr (AluOPRRR.And) rs1 rs2))
1078
+
1079
+ ;; Helper for emitting the `andi` ("And Immediate") instruction.
1080
+ ;; rd ← rs1 ∧ uext(imm)
1081
+ (decl rv_andi (XReg Imm12) XReg)
1082
+ (rule (rv_andi rs1 imm)
1083
+ (alu_rr_imm12 (AluOPRRI.Andi) rs1 imm))
1084
+
1085
+ ;; Helper for emitting the `sltu` ("Set Less Than Unsigned") instruction.
1086
+ ;; rd ← rs1 < rs2
1087
+ (decl rv_sltu (XReg XReg) XReg)
1088
+ (rule (rv_sltu rs1 rs2)
1089
+ (alu_rrr (AluOPRRR.SltU) rs1 rs2))
1090
+
1091
+ ;; Helper for emitting the `snez` instruction.
1092
+ ;; This instruction is a mnemonic for `sltu rd, zero, rs`.
1093
+ (decl rv_snez (XReg) XReg)
1094
+ (rule (rv_snez rs1)
1095
+ (rv_sltu (zero_reg) rs1))
1096
+
1097
+ ;; Helper for emiting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
1098
+ ;; rd ← rs1 < imm
1099
+ (decl rv_sltiu (XReg Imm12) XReg)
1100
+ (rule (rv_sltiu rs1 imm)
1101
+ (alu_rr_imm12 (AluOPRRI.SltiU) rs1 imm))
1102
+
1103
+ ;; Helper for emitting the `seqz` instruction.
1104
+ ;; This instruction is a mnemonic for `sltiu rd, rs, 1`.
1105
+ (decl rv_seqz (XReg) XReg)
1106
+ (rule (rv_seqz rs1)
1107
+ (rv_sltiu rs1 (imm12_const 1)))
1108
+
1109
+
1110
+ ;; RV64I Base Integer Instruction Set
1111
+ ;; Unlike RV32I instructions these are only present in the 64bit ISA
1112
+
1113
+ ;; Helper for emitting the `addw` ("Add Word") instruction.
1114
+ ;; rd ← sext32(rs1) + sext32(rs2)
1115
+ (decl rv_addw (XReg XReg) XReg)
1116
+ (rule (rv_addw rs1 rs2)
1117
+ (alu_rrr (AluOPRRR.Addw) rs1 rs2))
1118
+
1119
+ ;; Helper for emitting the `addiw` ("Add Word Immediate") instruction.
1120
+ ;; rd ← sext32(rs1) + imm
1121
+ (decl rv_addiw (XReg Imm12) XReg)
1122
+ (rule (rv_addiw rs1 imm)
1123
+ (alu_rr_imm12 (AluOPRRI.Addiw) rs1 imm))
1124
+
1125
+ ;; Helper for emitting the `sext.w` ("Sign Extend Word") instruction.
1126
+ ;; This instruction is a mnemonic for `addiw rd, rs, zero`.
1127
+ (decl rv_sextw (XReg) XReg)
1128
+ (rule (rv_sextw rs1)
1129
+ (rv_addiw rs1 (imm12_const 0)))
1130
+
1131
+ ;; Helper for emitting the `subw` ("Subtract Word") instruction.
1132
+ ;; rd ← sext32(rs1) - sext32(rs2)
1133
+ (decl rv_subw (XReg XReg) XReg)
1134
+ (rule (rv_subw rs1 rs2)
1135
+ (alu_rrr (AluOPRRR.Subw) rs1 rs2))
1136
+
1137
+ ;; Helper for emitting the `sllw` ("Shift Left Logical Word") instruction.
1138
+ ;; rd ← sext32(uext32(rs1) << rs2)
1139
+ (decl rv_sllw (XReg XReg) XReg)
1140
+ (rule (rv_sllw rs1 rs2)
1141
+ (alu_rrr (AluOPRRR.Sllw) rs1 rs2))
1142
+
1143
+ ;; Helper for emitting the `slliw` ("Shift Left Logical Immediate Word") instruction.
1144
+ ;; rd ← sext32(uext32(rs1) << imm)
1145
+ (decl rv_slliw (XReg Imm12) XReg)
1146
+ (rule (rv_slliw rs1 imm)
1147
+ (alu_rr_imm12 (AluOPRRI.Slliw) rs1 imm))
1148
+
1149
+ ;; Helper for emitting the `srlw` ("Shift Right Logical Word") instruction.
1150
+ ;; rd ← sext32(uext32(rs1) >> rs2)
1151
+ (decl rv_srlw (XReg XReg) XReg)
1152
+ (rule (rv_srlw rs1 rs2)
1153
+ (alu_rrr (AluOPRRR.Srlw) rs1 rs2))
1154
+
1155
+ ;; Helper for emitting the `srliw` ("Shift Right Logical Immediate Word") instruction.
1156
+ ;; rd ← sext32(uext32(rs1) >> imm)
1157
+ (decl rv_srliw (XReg Imm12) XReg)
1158
+ (rule (rv_srliw rs1 imm)
1159
+ (alu_rr_imm12 (AluOPRRI.SrliW) rs1 imm))
1160
+
1161
+ ;; Helper for emitting the `sraw` ("Shift Right Arithmetic Word") instruction.
1162
+ ;; rd ← sext32(rs1 >> rs2)
1163
+ (decl rv_sraw (XReg XReg) XReg)
1164
+ (rule (rv_sraw rs1 rs2)
1165
+ (alu_rrr (AluOPRRR.Sraw) rs1 rs2))
1166
+
1167
+ ;; Helper for emitting the `sraiw` ("Shift Right Arithmetic Immediate Word") instruction.
1168
+ ;; rd ← sext32(rs1 >> imm)
1169
+ (decl rv_sraiw (XReg Imm12) XReg)
1170
+ (rule (rv_sraiw rs1 imm)
1171
+ (alu_rr_imm12 (AluOPRRI.Sraiw) rs1 imm))
1172
+
1173
+
1174
+ ;; RV32M Extension
1175
+ ;; TODO: Enable these instructions only when we have the M extension
1176
+
1177
+ ;; Helper for emitting the `mul` instruction.
1178
+ ;; rd ← rs1 × rs2
1179
+ (decl rv_mul (XReg XReg) XReg)
1180
+ (rule (rv_mul rs1 rs2)
1181
+ (alu_rrr (AluOPRRR.Mul) rs1 rs2))
1182
+
1183
+ ;; Helper for emitting the `mulh` ("Multiply High Signed Signed") instruction.
1184
+ ;; rd ← (sext(rs1) × sext(rs2)) » xlen
1185
+ (decl rv_mulh (XReg XReg) XReg)
1186
+ (rule (rv_mulh rs1 rs2)
1187
+ (alu_rrr (AluOPRRR.Mulh) rs1 rs2))
1188
+
1189
+ ;; Helper for emitting the `mulhu` ("Multiply High Unsigned Unsigned") instruction.
1190
+ ;; rd ← (uext(rs1) × uext(rs2)) » xlen
1191
+ (decl rv_mulhu (XReg XReg) XReg)
1192
+ (rule (rv_mulhu rs1 rs2)
1193
+ (alu_rrr (AluOPRRR.Mulhu) rs1 rs2))
1194
+
1195
+ ;; Helper for emitting the `div` instruction.
1196
+ ;; rd ← rs1 ÷ rs2
1197
+ (decl rv_div (XReg XReg) XReg)
1198
+ (rule (rv_div rs1 rs2)
1199
+ (alu_rrr (AluOPRRR.Div) rs1 rs2))
1200
+
1201
+ ;; Helper for emitting the `divu` ("Divide Unsigned") instruction.
1202
+ ;; rd ← rs1 ÷ rs2
1203
+ (decl rv_divu (XReg XReg) XReg)
1204
+ (rule (rv_divu rs1 rs2)
1205
+ (alu_rrr (AluOPRRR.DivU) rs1 rs2))
1206
+
1207
+ ;; Helper for emitting the `rem` instruction.
1208
+ ;; rd ← rs1 mod rs2
1209
+ (decl rv_rem (XReg XReg) XReg)
1210
+ (rule (rv_rem rs1 rs2)
1211
+ (alu_rrr (AluOPRRR.Rem) rs1 rs2))
1212
+
1213
+ ;; Helper for emitting the `remu` ("Remainder Unsigned") instruction.
1214
+ ;; rd ← rs1 mod rs2
1215
+ (decl rv_remu (XReg XReg) XReg)
1216
+ (rule (rv_remu rs1 rs2)
1217
+ (alu_rrr (AluOPRRR.RemU) rs1 rs2))
1218
+
1219
+
1220
+
1221
+ ;; RV64M Extension
1222
+ ;; TODO: Enable these instructions only when we have the M extension
1223
+
1224
+ ;; Helper for emitting the `mulw` ("Multiply Word") instruction.
1225
+ ;; rd ← uext32(rs1) × uext32(rs2)
1226
+ (decl rv_mulw (XReg XReg) XReg)
1227
+ (rule (rv_mulw rs1 rs2)
1228
+ (alu_rrr (AluOPRRR.Mulw) rs1 rs2))
1229
+
1230
+ ;; Helper for emitting the `divw` ("Divide Word") instruction.
1231
+ ;; rd ← sext32(rs1) ÷ sext32(rs2)
1232
+ (decl rv_divw (XReg XReg) XReg)
1233
+ (rule (rv_divw rs1 rs2)
1234
+ (alu_rrr (AluOPRRR.Divw) rs1 rs2))
1235
+
1236
+ ;; Helper for emitting the `divuw` ("Divide Unsigned Word") instruction.
1237
+ ;; rd ← uext32(rs1) ÷ uext32(rs2)
1238
+ (decl rv_divuw (XReg XReg) XReg)
1239
+ (rule (rv_divuw rs1 rs2)
1240
+ (alu_rrr (AluOPRRR.Divuw) rs1 rs2))
1241
+
1242
+ ;; Helper for emitting the `remw` ("Remainder Word") instruction.
1243
+ ;; rd ← sext32(rs1) mod sext32(rs2)
1244
+ (decl rv_remw (XReg XReg) XReg)
1245
+ (rule (rv_remw rs1 rs2)
1246
+ (alu_rrr (AluOPRRR.Remw) rs1 rs2))
1247
+
1248
+ ;; Helper for emitting the `remuw` ("Remainder Unsigned Word") instruction.
1249
+ ;; rd ← uext32(rs1) mod uext32(rs2)
1250
+ (decl rv_remuw (XReg XReg) XReg)
1251
+ (rule (rv_remuw rs1 rs2)
1252
+ (alu_rrr (AluOPRRR.Remuw) rs1 rs2))
1253
+
1254
+
1255
+ ;; F and D Extensions
1256
+ ;; TODO: Enable these instructions only when we have the F or D extensions
1257
+
1258
+ ;; Helper for emitting the `fadd` instruction.
1259
+ (decl rv_fadd (Type FReg FReg) FReg)
1260
+ (rule (rv_fadd $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FaddS) $F32 rs1 rs2))
1261
+ (rule (rv_fadd $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FaddD) $F64 rs1 rs2))
1262
+
1263
+ ;; Helper for emitting the `fsub` instruction.
1264
+ (decl rv_fsub (Type FReg FReg) FReg)
1265
+ (rule (rv_fsub $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsubS) $F32 rs1 rs2))
1266
+ (rule (rv_fsub $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsubD) $F64 rs1 rs2))
1267
+
1268
+ ;; Helper for emitting the `fmul` instruction.
1269
+ (decl rv_fmul (Type FReg FReg) FReg)
1270
+ (rule (rv_fmul $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FmulS) $F32 rs1 rs2))
1271
+ (rule (rv_fmul $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FmulD) $F64 rs1 rs2))
1272
+
1273
+ ;; Helper for emitting the `fdiv` instruction.
1274
+ (decl rv_fdiv (Type FReg FReg) FReg)
1275
+ (rule (rv_fdiv $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FdivS) $F32 rs1 rs2))
1276
+ (rule (rv_fdiv $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FdivD) $F64 rs1 rs2))
1277
+
1278
+ ;; Helper for emitting the `fsqrt` instruction.
1279
+ (decl rv_fsqrt (Type FReg) FReg)
1280
+ (rule (rv_fsqrt $F32 rs1) (fpu_rr (FpuOPRR.FsqrtS) $F32 rs1))
1281
+ (rule (rv_fsqrt $F64 rs1) (fpu_rr (FpuOPRR.FsqrtD) $F64 rs1))
1282
+
1283
+ ;; Helper for emitting the `fmadd` instruction.
1284
+ (decl rv_fmadd (Type FReg FReg FReg) FReg)
1285
+ (rule (rv_fmadd $F32 rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddS) $F32 rs1 rs2 rs3))
1286
+ (rule (rv_fmadd $F64 rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddD) $F64 rs1 rs2 rs3))
1287
+
1288
+ ;; Helper for emitting the `fmv.x.w` instruction.
1289
+ (decl rv_fmvxw (FReg) XReg)
1290
+ (rule (rv_fmvxw r) (fpu_rr (FpuOPRR.FmvXW) $I32 r))
1291
+
1292
+ ;; Helper for emitting the `fmv.x.d` instruction.
1293
+ (decl rv_fmvxd (FReg) XReg)
1294
+ (rule (rv_fmvxd r) (fpu_rr (FpuOPRR.FmvXD) $I64 r))
1295
+
1296
+ ;; Helper for emitting the `fmv.w.x` instruction.
1297
+ (decl rv_fmvwx (XReg) FReg)
1298
+ (rule (rv_fmvwx r) (fpu_rr (FpuOPRR.FmvWX) $F32 r))
1299
+
1300
+ ;; Helper for emitting the `fmv.d.x` instruction.
1301
+ (decl rv_fmvdx (XReg) FReg)
1302
+ (rule (rv_fmvdx r) (fpu_rr (FpuOPRR.FmvDX) $F64 r))
1303
+
1304
+ ;; Helper for emitting the `fcvt.d.s` ("Float Convert Double to Single") instruction.
1305
+ (decl rv_fcvtds (FReg) FReg)
1306
+ (rule (rv_fcvtds rs1) (fpu_rr (FpuOPRR.FcvtDS) $F32 rs1))
1307
+
1308
+ ;; Helper for emitting the `fcvt.s.d` ("Float Convert Single to Double") instruction.
1309
+ (decl rv_fcvtsd (FReg) FReg)
1310
+ (rule (rv_fcvtsd rs1) (fpu_rr (FpuOPRR.FcvtSD) $F64 rs1))
1311
+
1312
+ ;; Helper for emitting the `fsgnj` ("Floating Point Sign Injection") instruction.
1313
+ ;; The output of this instruction is `rs1` with the sign bit from `rs2`
1314
+ ;; This implements the `copysign` operation
1315
+ (decl rv_fsgnj (Type FReg FReg) FReg)
1316
+ (rule (rv_fsgnj $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjS) $F32 rs1 rs2))
1317
+ (rule (rv_fsgnj $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjD) $F64 rs1 rs2))
1318
+
1319
+ ;; Helper for emitting the `fsgnjn` ("Floating Point Sign Injection Negated") instruction.
1320
+ ;; The output of this instruction is `rs1` with the negated sign bit from `rs2`
1321
+ ;; When `rs1 == rs2` this implements the `neg` operation
1322
+ (decl rv_fsgnjn (Type FReg FReg) FReg)
1323
+ (rule (rv_fsgnjn $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnS) $F32 rs1 rs2))
1324
+ (rule (rv_fsgnjn $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnD) $F64 rs1 rs2))
1325
+
1326
+ ;; Helper for emitting the `fneg` ("Floating Point Negate") instruction.
1327
+ ;; This instruction is a mnemonic for `fsgnjn rd, rs1, rs1`
1328
+ (decl rv_fneg (Type FReg) FReg)
1329
+ (rule (rv_fneg ty rs1) (rv_fsgnjn ty rs1 rs1))
1330
+
1331
+ ;; Helper for emitting the `fsgnjx` ("Floating Point Sign Injection Exclusive") instruction.
1332
+ ;; The output of this instruction is `rs1` with the XOR of the sign bits from `rs1` and `rs2`.
1333
+ ;; When `rs1 == rs2` this implements `fabs`
1334
+ (decl rv_fsgnjx (Type FReg FReg) FReg)
1335
+ (rule (rv_fsgnjx $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxS) $F32 rs1 rs2))
1336
+ (rule (rv_fsgnjx $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxD) $F64 rs1 rs2))
1337
+
1338
+ ;; Helper for emitting the `fabs` ("Floating Point Absolute") instruction.
1339
+ ;; This instruction is a mnemonic for `fsgnjx rd, rs1, rs1`
1340
+ (decl rv_fabs (Type FReg) FReg)
1341
+ (rule (rv_fabs ty rs1) (rv_fsgnjx ty rs1 rs1))
1342
+
1343
+ ;; Helper for emitting the `feq` ("Float Equal") instruction.
1344
+ (decl rv_feq (Type FReg FReg) XReg)
1345
+ (rule (rv_feq $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqS) $I64 rs1 rs2))
1346
+ (rule (rv_feq $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqD) $I64 rs1 rs2))
1347
+
1348
+ ;; Helper for emitting the `flt` ("Float Less Than") instruction.
1349
+ (decl rv_flt (Type FReg FReg) XReg)
1350
+ (rule (rv_flt $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FltS) $I64 rs1 rs2))
1351
+ (rule (rv_flt $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FltD) $I64 rs1 rs2))
1352
+
1353
+ ;; Helper for emitting the `fle` ("Float Less Than or Equal") instruction.
1354
+ (decl rv_fle (Type FReg FReg) XReg)
1355
+ (rule (rv_fle $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FleS) $I64 rs1 rs2))
1356
+ (rule (rv_fle $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FleD) $I64 rs1 rs2))
1357
+
1358
+ ;; Helper for emitting the `fgt` ("Float Greater Than") instruction.
1359
+ ;; Note: The arguments are reversed
1360
+ (decl rv_fgt (Type FReg FReg) XReg)
1361
+ (rule (rv_fgt ty rs1 rs2) (rv_flt ty rs2 rs1))
1362
+
1363
+ ;; Helper for emitting the `fge` ("Float Greater Than or Equal") instruction.
1364
+ ;; Note: The arguments are reversed
1365
+ (decl rv_fge (Type FReg FReg) XReg)
1366
+ (rule (rv_fge ty rs1 rs2) (rv_fle ty rs2 rs1))
1367
+
1368
+
1369
+ ;; `Zba` Extension Instructions
1370
+
1371
+ ;; Helper for emitting the `adduw` ("Add Unsigned Word") instruction.
1372
+ ;; rd ← uext32(rs1) + uext32(rs2)
1373
+ (decl rv_adduw (XReg XReg) XReg)
1374
+ (rule (rv_adduw rs1 rs2)
1375
+ (alu_rrr (AluOPRRR.Adduw) rs1 rs2))
1376
+
1377
+ ;; Helper for emitting the `zext.w` ("Zero Extend Word") instruction.
1378
+ ;; This instruction is a mnemonic for `adduw rd, rs1, zero`.
1379
+ ;; rd ← uext32(rs1)
1380
+ (decl rv_zextw (XReg) XReg)
1381
+ (rule (rv_zextw rs1)
1382
+ (rv_adduw rs1 (zero_reg)))
1383
+
1384
+ ;; Helper for emitting the `slli.uw` ("Shift Left Logical Immediate Unsigned Word") instruction.
1385
+ ;; rd ← uext32(rs1) << imm
1386
+ (decl rv_slliuw (XReg Imm12) XReg)
1387
+ (rule (rv_slliuw rs1 imm)
1388
+ (alu_rr_imm12 (AluOPRRI.SlliUw) rs1 imm))
1389
+
1390
+
1391
+ ;; `Zbb` Extension Instructions
1392
+
1393
+ ;; Helper for emitting the `andn` ("And Negated") instruction.
1394
+ ;; rd ← rs1 ∧ ~(rs2)
1395
+ (decl rv_andn (XReg XReg) XReg)
1396
+ (rule (rv_andn rs1 rs2)
1397
+ (alu_rrr (AluOPRRR.Andn) rs1 rs2))
1398
+
1399
+ ;; Helper for emitting the `orn` ("Or Negated") instruction.
1400
+ ;; rd ← rs1 ∨ ~(rs2)
1401
+ (decl rv_orn (XReg XReg) XReg)
1402
+ (rule (rv_orn rs1 rs2)
1403
+ (alu_rrr (AluOPRRR.Orn) rs1 rs2))
1404
+
1405
+ ;; Helper for emitting the `clz` ("Count Leading Zero Bits") instruction.
1406
+ (decl rv_clz (XReg) XReg)
1407
+ (rule (rv_clz rs1)
1408
+ (alu_rr_funct12 (AluOPRRI.Clz) rs1))
1409
+
1410
+ ;; Helper for emitting the `clzw` ("Count Leading Zero Bits in Word") instruction.
1411
+ (decl rv_clzw (XReg) XReg)
1412
+ (rule (rv_clzw rs1)
1413
+ (alu_rr_funct12 (AluOPRRI.Clzw) rs1))
1414
+
1415
+ ;; Helper for emitting the `ctz` ("Count Trailing Zero Bits") instruction.
1416
+ (decl rv_ctz (XReg) XReg)
1417
+ (rule (rv_ctz rs1)
1418
+ (alu_rr_funct12 (AluOPRRI.Ctz) rs1))
1419
+
1420
+ ;; Helper for emitting the `ctzw` ("Count Trailing Zero Bits in Word") instruction.
1421
+ (decl rv_ctzw (XReg) XReg)
1422
+ (rule (rv_ctzw rs1)
1423
+ (alu_rr_funct12 (AluOPRRI.Ctzw) rs1))
1424
+
1425
+ ;; Helper for emitting the `cpop` ("Count Population") instruction.
1426
+ (decl rv_cpop (XReg) XReg)
1427
+ (rule (rv_cpop rs1)
1428
+ (alu_rr_funct12 (AluOPRRI.Cpop) rs1))
1429
+
1430
+ ;; Helper for emitting the `max` instruction.
1431
+ (decl rv_max (XReg XReg) XReg)
1432
+ (rule (rv_max rs1 rs2)
1433
+ (alu_rrr (AluOPRRR.Max) rs1 rs2))
1434
+
1435
+ ;; Helper for emitting the `sext.b` instruction.
1436
+ (decl rv_sextb (XReg) XReg)
1437
+ (rule (rv_sextb rs1)
1438
+ (alu_rr_imm12 (AluOPRRI.Sextb) rs1 (imm12_const 0)))
1439
+
1440
+ ;; Helper for emitting the `sext.h` instruction.
1441
+ (decl rv_sexth (XReg) XReg)
1442
+ (rule (rv_sexth rs1)
1443
+ (alu_rr_imm12 (AluOPRRI.Sexth) rs1 (imm12_const 0)))
1444
+
1445
+ ;; Helper for emitting the `zext.h` instruction.
1446
+ (decl rv_zexth (XReg) XReg)
1447
+ (rule (rv_zexth rs1)
1448
+ (alu_rr_imm12 (AluOPRRI.Zexth) rs1 (imm12_const 0)))
1449
+
1450
+ ;; Helper for emitting the `rol` ("Rotate Left") instruction.
1451
+ (decl rv_rol (XReg XReg) XReg)
1452
+ (rule (rv_rol rs1 rs2)
1453
+ (alu_rrr (AluOPRRR.Rol) rs1 rs2))
1454
+
1455
+ ;; Helper for emitting the `rolw` ("Rotate Left Word") instruction.
1456
+ (decl rv_rolw (XReg XReg) XReg)
1457
+ (rule (rv_rolw rs1 rs2)
1458
+ (alu_rrr (AluOPRRR.Rolw) rs1 rs2))
1459
+
1460
+ ;; Helper for emitting the `ror` ("Rotate Right") instruction.
1461
+ (decl rv_ror (XReg XReg) XReg)
1462
+ (rule (rv_ror rs1 rs2)
1463
+ (alu_rrr (AluOPRRR.Ror) rs1 rs2))
1464
+
1465
+ ;; Helper for emitting the `rorw` ("Rotate Right Word") instruction.
1466
+ (decl rv_rorw (XReg XReg) XReg)
1467
+ (rule (rv_rorw rs1 rs2)
1468
+ (alu_rrr (AluOPRRR.Rorw) rs1 rs2))
1469
+
1470
+ ;; Helper for emitting the `rev8` ("Byte Reverse") instruction.
1471
+ (decl rv_rev8 (XReg) XReg)
1472
+ (rule (rv_rev8 rs1)
1473
+ (alu_rr_funct12 (AluOPRRI.Rev8) rs1))
1474
+
1475
+ ;; Helper for emitting the `brev8` ("Bit Reverse Inside Bytes") instruction.
1476
+ ;; TODO: This instruction is mentioned in some older versions of the
1477
+ ;; spec, but has since disappeared, we should follow up on this.
1478
+ ;; It probably was renamed to `rev.b` which seems to be the closest match.
1479
+ (decl rv_brev8 (XReg) XReg)
1480
+ (rule (rv_brev8 rs1)
1481
+ (alu_rr_funct12 (AluOPRRI.Brev8) rs1))
1482
+
1483
+ ;; Helper for emitting the `bseti` ("Single-Bit Set Immediate") instruction.
1484
+ (decl rv_bseti (XReg Imm12) XReg)
1485
+ (rule (rv_bseti rs1 imm)
1486
+ (alu_rr_imm12 (AluOPRRI.Bseti) rs1 imm))
1487
+
1488
+
1489
+ ;; `Zbkb` Extension Instructions
1490
+
1491
+ ;; Helper for emitting the `pack` ("Pack low halves of registers") instruction.
1492
+ (decl rv_pack (XReg XReg) XReg)
1493
+ (rule (rv_pack rs1 rs2)
1494
+ (alu_rrr (AluOPRRR.Pack) rs1 rs2))
1495
+
1496
+ ;; Helper for emitting the `packw` ("Pack low 16-bits of registers") instruction.
1497
+ (decl rv_packw (XReg XReg) XReg)
1498
+ (rule (rv_packw rs1 rs2)
1499
+ (alu_rrr (AluOPRRR.Packw) rs1 rs2))
1500
+
1501
+
1502
+
1503
+
1504
+ ;; Generate a mask for the bit-width of the given type
1505
+ (decl pure shift_mask (Type) u64)
1506
+ (rule (shift_mask ty) (u64_sub (ty_bits (lane_type ty)) 1))
1507
+
1508
+ ;; for load immediate
1509
+ (decl imm (Type u64) Reg)
1510
+ (extern constructor imm imm)
1511
+
1512
+ ;; Imm12 Rules
1513
+
1514
+ (decl pure imm12_zero () Imm12)
1515
+ (rule
1516
+ (imm12_zero)
1517
+ (imm12_const 0))
1518
+
1519
+ (decl pure imm12_const (i32) Imm12)
1520
+ (extern constructor imm12_const imm12_const)
1521
+
1522
+ (decl load_imm12 (i32) Reg)
1523
+ (rule
1524
+ (load_imm12 x)
1525
+ (rv_addi (zero_reg) (imm12_const x)))
1526
+
1527
+ ;; for load immediate
1528
+ (decl imm_from_bits (u64) Imm12)
1529
+ (extern constructor imm_from_bits imm_from_bits)
1530
+
1531
+ (decl imm_from_neg_bits (i64) Imm12)
1532
+ (extern constructor imm_from_neg_bits imm_from_neg_bits)
1533
+
1534
+ (decl imm12_const_add (i32 i32) Imm12)
1535
+ (extern constructor imm12_const_add imm12_const_add)
1536
+
1537
+ (decl imm12_and (Imm12 u64) Imm12)
1538
+ (extern constructor imm12_and imm12_and)
1539
+
1540
+ ;; Helper for get negative of Imm12
1541
+ (decl neg_imm12 (Imm12) Imm12)
1542
+ (extern constructor neg_imm12 neg_imm12)
1543
+
1544
+ ;; Imm12 Extractors
1545
+
1546
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1547
+ (decl imm12_from_value (Imm12) Value)
1548
+ (extractor
1549
+ (imm12_from_value n)
1550
+ (def_inst (iconst (u64_from_imm64 (imm12_from_u64 n)))))
1551
+
1552
+ (decl imm12_from_u64 (Imm12) u64)
1553
+ (extern extractor imm12_from_u64 imm12_from_u64)
1554
+
1555
+ (decl pure partial u64_to_imm12 (u64) Imm12)
1556
+ (rule (u64_to_imm12 (imm12_from_u64 n)) n)
1557
+
1558
+
1559
+ ;; Imm5 Extractors
1560
+
1561
+ (decl imm5_from_u64 (Imm5) u64)
1562
+ (extern extractor imm5_from_u64 imm5_from_u64)
1563
+
1564
+ ;; Construct a Imm5 from an i8
1565
+ (decl pure partial imm5_from_i8 (i8) Imm5)
1566
+ (extern constructor imm5_from_i8 imm5_from_i8)
1567
+
1568
+ ;; Extractor that matches a `Value` equivalent to a replicated Imm5 on all lanes.
1569
+ ;; TODO: Try matching vconst here as well
1570
+ (decl replicated_imm5 (Imm5) Value)
1571
+ (extractor (replicated_imm5 n)
1572
+ (def_inst (splat (iconst (u64_from_imm64 (imm5_from_u64 n))))))
1573
+
1574
+ ;; UImm5 Helpers
1575
+
1576
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `UImm5`.
1577
+ (decl uimm5_from_value (UImm5) Value)
1578
+ (extractor (uimm5_from_value n)
1579
+ (iconst (u64_from_imm64 (uimm5_from_u64 n))))
1580
+
1581
+ ;; Extract a `UImm5` from an `u8`.
1582
+ (decl pure partial uimm5_from_u8 (UImm5) u8)
1583
+ (extern extractor uimm5_from_u8 uimm5_from_u8)
1584
+
1585
+ ;; Extract a `UImm5` from an `u64`.
1586
+ (decl pure partial uimm5_from_u64 (UImm5) u64)
1587
+ (extern extractor uimm5_from_u64 uimm5_from_u64)
1588
+
1589
+ (decl uimm5_bitcast_to_imm5 (UImm5) Imm5)
1590
+ (extern constructor uimm5_bitcast_to_imm5 uimm5_bitcast_to_imm5)
1591
+
1592
+ ;; Float Helpers
1593
+
1594
+ (decl gen_default_frm () OptionFloatRoundingMode)
1595
+ (extern constructor gen_default_frm gen_default_frm)
1596
+
1597
+ ;; Helper for emitting `MInst.FpuRR` instructions.
1598
+ (decl fpu_rr (FpuOPRR Type Reg) Reg)
1599
+ (rule (fpu_rr op ty src)
1600
+ (let ((dst WritableReg (temp_writable_reg ty))
1601
+ (_ Unit (emit (MInst.FpuRR op (gen_default_frm) dst src))))
1602
+ dst))
1603
+
1604
+ ;; Helper for emitting `MInst.AluRRR` instructions.
1605
+ (decl alu_rrr (AluOPRRR Reg Reg) Reg)
1606
+ (rule (alu_rrr op src1 src2)
1607
+ (let ((dst WritableXReg (temp_writable_xreg))
1608
+ (_ Unit (emit (MInst.AluRRR op dst src1 src2))))
1609
+ dst))
1610
+
1611
+
1612
+ (decl pack_float_rounding_mode (FRM) OptionFloatRoundingMode)
1613
+ (extern constructor pack_float_rounding_mode pack_float_rounding_mode)
1614
+
1615
+ ;; Helper for emitting `MInst.AluRRR` instructions.
1616
+ (decl fpu_rrr (FpuOPRRR Type Reg Reg) Reg)
1617
+ (rule (fpu_rrr op ty src1 src2)
1618
+ (let ((dst WritableReg (temp_writable_reg ty))
1619
+ (_ Unit (emit (MInst.FpuRRR op (gen_default_frm) dst src1 src2))))
1620
+ dst))
1621
+
1622
+
1623
+ ;; Helper for emitting `MInst.FpuRRRR` instructions.
1624
+ (decl fpu_rrrr (FpuOPRRRR Type Reg Reg Reg) Reg)
1625
+ (rule (fpu_rrrr op ty src1 src2 src3)
1626
+ (let ((dst WritableReg (temp_writable_reg ty))
1627
+ (_ Unit (emit (MInst.FpuRRRR op (gen_default_frm) dst src1 src2 src3))))
1628
+ dst))
1629
+
1630
+
1631
+ ;; Helper for emitting `MInst.AluRRImm12` instructions.
1632
+ (decl alu_rr_imm12 (AluOPRRI Reg Imm12) Reg)
1633
+ (rule (alu_rr_imm12 op src imm)
1634
+ (let ((dst WritableXReg (temp_writable_xreg))
1635
+ (_ Unit (emit (MInst.AluRRImm12 op dst src imm))))
1636
+ dst))
1637
+
1638
+ ;; some instruction use imm12 as funct12.
1639
+ ;; so we don't need the imm12 paramter.
1640
+ (decl alu_rr_funct12 (AluOPRRI Reg) Reg)
1641
+ (rule (alu_rr_funct12 op src)
1642
+ (let ((dst WritableXReg (temp_writable_xreg))
1643
+ (_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
1644
+ dst))
1645
+
1646
+ (decl select_addi (Type) AluOPRRI)
1647
+ (rule 1 (select_addi (fits_in_32 ty)) (AluOPRRI.Addiw))
1648
+ (rule (select_addi (fits_in_64 ty)) (AluOPRRI.Addi))
1649
+
1650
+
1651
+ (decl gen_bnot (Type ValueRegs) ValueRegs)
1652
+ (rule 2 (gen_bnot (ty_scalar_float ty) x)
1653
+ (let ((val FReg (value_regs_get x 0))
1654
+ (x_val XReg (move_f_to_x val ty))
1655
+ (inverted XReg (rv_not x_val))
1656
+ (res FReg (move_x_to_f inverted (float_int_of_same_size ty))))
1657
+ (value_reg res)))
1658
+
1659
+ (rule 1 (gen_bnot $I128 x)
1660
+ (let ((lo XReg (rv_not (value_regs_get x 0)))
1661
+ (hi XReg (rv_not (value_regs_get x 1))))
1662
+ (value_regs lo hi)))
1663
+
1664
+ (rule 0 (gen_bnot (ty_int_ref_scalar_64 _) x)
1665
+ (rv_not (value_regs_get x 0)))
1666
+
1667
+
1668
+ (decl gen_and (Type ValueRegs ValueRegs) ValueRegs)
1669
+ (rule 1 (gen_and $I128 x y)
1670
+ (value_regs
1671
+ (rv_and (value_regs_get x 0) (value_regs_get y 0))
1672
+ (rv_and (value_regs_get x 1) (value_regs_get y 1))))
1673
+
1674
+ (rule 0 (gen_and (fits_in_64 _) x y)
1675
+ (rv_and (value_regs_get x 0) (value_regs_get y 0)))
1676
+
1677
+
1678
+ (decl gen_andi (XReg u64) XReg)
1679
+ (rule 1 (gen_andi x (imm12_from_u64 y))
1680
+ (rv_andi x y))
1681
+
1682
+ (rule 0 (gen_andi x y)
1683
+ (rv_and x (imm $I64 y)))
1684
+
1685
+
1686
+ (decl gen_or (Type ValueRegs ValueRegs) ValueRegs)
1687
+ (rule 1 (gen_or $I128 x y)
1688
+ (value_regs
1689
+ (rv_or (value_regs_get x 0) (value_regs_get y 0))
1690
+ (rv_or (value_regs_get x 1) (value_regs_get y 1))))
1691
+
1692
+ (rule 0 (gen_or (fits_in_64 _) x y)
1693
+ (rv_or (value_regs_get x 0) (value_regs_get y 0)))
1694
+
1695
+
1696
+ (decl lower_bit_reverse (Reg Type) Reg)
1697
+
1698
+ (rule
1699
+ (lower_bit_reverse r $I8)
1700
+ (gen_brev8 r $I8))
1701
+
1702
+ (rule
1703
+ (lower_bit_reverse r $I16)
1704
+ (let
1705
+ ((tmp XReg (gen_brev8 r $I16))
1706
+ (tmp2 XReg (gen_rev8 tmp))
1707
+ (result XReg (rv_srli tmp2 (imm12_const 48))))
1708
+ result))
1709
+
1710
+ (rule
1711
+ (lower_bit_reverse r $I32)
1712
+ (let
1713
+ ((tmp XReg (gen_brev8 r $I32))
1714
+ (tmp2 XReg (gen_rev8 tmp))
1715
+ (result XReg (rv_srli tmp2 (imm12_const 32))))
1716
+ result))
1717
+
1718
+ (rule
1719
+ (lower_bit_reverse r $I64)
1720
+ (let
1721
+ ((tmp XReg (gen_rev8 r)))
1722
+ (gen_brev8 tmp $I64)))
1723
+
1724
+
1725
+ (decl lower_ctz (Type Reg) Reg)
1726
+ (rule (lower_ctz ty x)
1727
+ (gen_cltz $false x ty))
1728
+
1729
+ (rule 1 (lower_ctz (fits_in_16 ty) x)
1730
+ (if-let $true (has_zbb))
1731
+ (let ((tmp Reg (gen_bseti x (ty_bits ty))))
1732
+ (rv_ctzw tmp)))
1733
+
1734
+ (rule 2 (lower_ctz $I32 x)
1735
+ (if-let $true (has_zbb))
1736
+ (rv_ctzw x))
1737
+
1738
+ (rule 2 (lower_ctz $I64 x)
1739
+ (if-let $true (has_zbb))
1740
+ (rv_ctz x))
1741
+
1742
+ ;; Count trailing zeros from a i128 bit value.
1743
+ ;; We count both halves separately and conditionally add them if it makes sense.
1744
+ (decl lower_ctz_128 (ValueRegs) ValueRegs)
1745
+ (rule (lower_ctz_128 x)
1746
+ (let ((x_lo XReg (value_regs_get x 0))
1747
+ (x_hi XReg (value_regs_get x 1))
1748
+ ;; Count both halves
1749
+ (high XReg (lower_ctz $I64 x_hi))
1750
+ (low XReg (lower_ctz $I64 x_lo))
1751
+ ;; Only add the top half if the bottom is zero
1752
+ (high XReg (gen_select_reg (IntCC.Equal) x_lo (zero_reg) high (zero_reg)))
1753
+ (result XReg (rv_add low high)))
1754
+ (extend result (ExtendOp.Zero) $I64 $I128)))
1755
+
1756
+ (decl lower_clz (Type XReg) XReg)
1757
+ (rule (lower_clz ty rs)
1758
+ (gen_cltz $true rs ty))
1759
+
1760
+ (rule 1 (lower_clz (fits_in_16 ty) r)
1761
+ (if-let $true (has_zbb))
1762
+ (let ((tmp XReg (zext r ty $I64))
1763
+ (count XReg (rv_clz tmp))
1764
+ ;; We always do the operation on the full 64-bit register, so subtract 64 from the result.
1765
+ (result XReg (rv_addi count (imm12_const_add (ty_bits ty) -64))))
1766
+ result))
1767
+
1768
+ (rule 2 (lower_clz $I32 r)
1769
+ (if-let $true (has_zbb))
1770
+ (rv_clzw r))
1771
+
1772
+ (rule 2 (lower_clz $I64 r)
1773
+ (if-let $true (has_zbb))
1774
+ (rv_clz r))
1775
+
1776
+
1777
+ ;; Count leading zeros from a i128 bit value.
1778
+ ;; We count both halves separately and conditionally add them if it makes sense.
1779
+ (decl lower_clz_i128 (ValueRegs) ValueRegs)
1780
+ (rule (lower_clz_i128 x)
1781
+ (let ((x_lo XReg (value_regs_get x 0))
1782
+ (x_hi XReg (value_regs_get x 1))
1783
+ ;; Count both halves
1784
+ (high XReg (lower_clz $I64 x_hi))
1785
+ (low XReg (lower_clz $I64 x_lo))
1786
+ ;; Only add the bottom zeros if the top half is zero
1787
+ (low XReg (gen_select_reg (IntCC.Equal) x_hi (zero_reg) low (zero_reg)))
1788
+ (result XReg (rv_add high low)))
1789
+ (extend result (ExtendOp.Zero) $I64 $I128)))
1790
+
1791
+
1792
+ (decl lower_cls (Type XReg) XReg)
1793
+ (rule (lower_cls ty r)
1794
+ (let ((tmp XReg (sext r ty $I64))
1795
+ (tmp2 XReg (gen_select_reg (IntCC.SignedLessThan) tmp (zero_reg) (rv_not tmp) tmp))
1796
+ (tmp3 XReg (lower_clz ty tmp2)))
1797
+ (rv_addi tmp3 (imm12_const -1))))
1798
+
1799
+ ;; If the sign bit is set, we count the leading zeros of the inverted value.
1800
+ ;; Otherwise we can just count the leading zeros of the original value.
1801
+ ;; Subtract 1 since the sign bit does not count.
1802
+ (decl lower_cls_i128 (ValueRegs) ValueRegs)
1803
+ (rule (lower_cls_i128 x)
1804
+ (let ((low XReg (value_regs_get x 0))
1805
+ (high XReg (value_regs_get x 1))
1806
+ (low XReg (gen_select_reg (IntCC.SignedLessThan) high (zero_reg) (rv_not low) low))
1807
+ (high XReg (gen_select_reg (IntCC.SignedLessThan) high (zero_reg) (rv_not high) high))
1808
+ (tmp ValueRegs (lower_clz_i128 (value_regs low high)))
1809
+ (count XReg (value_regs_get tmp 0))
1810
+ (result XReg (rv_addi count (imm12_const -1))))
1811
+ (extend result (ExtendOp.Zero) $I64 $I128)))
1812
+
1813
+
1814
+ (decl gen_cltz (bool XReg Type) XReg)
1815
+ (rule (gen_cltz leading rs ty)
1816
+ (let ((tmp WritableXReg (temp_writable_xreg))
1817
+ (step WritableXReg (temp_writable_xreg))
1818
+ (sum WritableXReg (temp_writable_xreg))
1819
+ (_ Unit (emit (MInst.Cltz leading sum step tmp rs ty))))
1820
+ sum))
1821
+
1822
+
1823
+ ;; Extends an integer if it is smaller than 64 bits.
1824
+ (decl ext_int_if_need (bool ValueRegs Type) ValueRegs)
1825
+ ;;; For values smaller than 64 bits, we need to extend them to 64 bits
1826
+ (rule 0 (ext_int_if_need $true val (fits_in_32 (ty_int ty)))
1827
+ (extend val (ExtendOp.Signed) ty $I64))
1828
+ (rule 0 (ext_int_if_need $false val (fits_in_32 (ty_int ty)))
1829
+ (extend val (ExtendOp.Zero) ty $I64))
1830
+ ;; If the value is larger than one machine register, we don't need to do anything
1831
+ (rule 1 (ext_int_if_need _ r $I64) r)
1832
+ (rule 2 (ext_int_if_need _ r $I128) r)
1833
+
1834
+
1835
+ ;; Performs a zero extension of the given value
1836
+ (decl zext (XReg Type Type) XReg)
1837
+ (rule (zext val from_ty (fits_in_64 to_ty)) (value_regs_get (extend val (ExtendOp.Zero) from_ty to_ty) 0))
1838
+
1839
+ ;; Performs a signed extension of the given value
1840
+ (decl sext (XReg Type Type) XReg)
1841
+ (rule (sext val from_ty (fits_in_64 to_ty)) (value_regs_get (extend val (ExtendOp.Signed) from_ty to_ty) 0))
1842
+
1843
+ (type ExtendOp
1844
+ (enum
1845
+ (Zero)
1846
+ (Signed)))
1847
+
1848
+ ;; Performs either a sign or zero extension of the given value
1849
+ (decl extend (ValueRegs ExtendOp Type Type) ValueRegs)
1850
+
1851
+ ;;; Generic Rules Extending to I64
1852
+ (decl pure extend_shift_op (ExtendOp) AluOPRRI)
1853
+ (rule (extend_shift_op (ExtendOp.Zero)) (AluOPRRI.Srli))
1854
+ (rule (extend_shift_op (ExtendOp.Signed)) (AluOPRRI.Srai))
1855
+
1856
+ ;; In the most generic case, we shift left and then shift right.
1857
+ ;; The type of right shift is determined by the extend op.
1858
+ (rule 0 (extend val extend_op (fits_in_32 from_ty) (fits_in_64 to_ty))
1859
+ (let ((val XReg (value_regs_get val 0))
1860
+ (shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits from_ty))))
1861
+ (left XReg (rv_slli val shift))
1862
+ (shift_op AluOPRRI (extend_shift_op extend_op))
1863
+ (right XReg (alu_rr_imm12 shift_op left shift)))
1864
+ right))
1865
+
1866
+ ;; If we are zero extending a U8 we can use a `andi` instruction.
1867
+ (rule 1 (extend val (ExtendOp.Zero) $I8 (fits_in_64 to_ty))
1868
+ (let ((val XReg (value_regs_get val 0)))
1869
+ (rv_andi val (imm12_const 255))))
1870
+
1871
+ ;; When signed extending from 32 to 64 bits we can use a
1872
+ ;; `addiw val 0`. Also known as a `sext.w`
1873
+ (rule 1 (extend val (ExtendOp.Signed) $I32 $I64)
1874
+ (let ((val XReg (value_regs_get val 0)))
1875
+ (rv_sextw val)))
1876
+
1877
+
1878
+ ;; No point in trying to use `packh` here to zero extend 8 bit values
1879
+ ;; since we can just use `andi` instead which is part of the base ISA.
1880
+
1881
+ ;; If we have the `zbkb` extension `packw` can be used to zero extend 16 bit values
1882
+ (rule 1 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
1883
+ (if-let $true (has_zbkb))
1884
+ (let ((val XReg (value_regs_get val 0)))
1885
+ (rv_packw val (zero_reg))))
1886
+
1887
+ ;; If we have the `zbkb` extension `pack` can be used to zero extend 32 bit registers
1888
+ (rule 1 (extend val (ExtendOp.Zero) $I32 $I64)
1889
+ (if-let $true (has_zbkb))
1890
+ (let ((val XReg (value_regs_get val 0)))
1891
+ (rv_pack val (zero_reg))))
1892
+
1893
+
1894
+ ;; If we have the `zbb` extension we can use the dedicated `sext.b` instruction.
1895
+ (rule 1 (extend val (ExtendOp.Signed) $I8 (fits_in_64 _))
1896
+ (if-let $true (has_zbb))
1897
+ (let ((val XReg (value_regs_get val 0)))
1898
+ (rv_sextb val)))
1899
+
1900
+ ;; If we have the `zbb` extension we can use the dedicated `sext.h` instruction.
1901
+ (rule 1 (extend val (ExtendOp.Signed) $I16 (fits_in_64 _))
1902
+ (if-let $true (has_zbb))
1903
+ (let ((val XReg (value_regs_get val 0)))
1904
+ (rv_sexth val)))
1905
+
1906
+ ;; If we have the `zbb` extension we can use the dedicated `zext.h` instruction.
1907
+ (rule 2 (extend val (ExtendOp.Zero) $I16 (fits_in_64 _))
1908
+ (if-let $true (has_zbb))
1909
+ (let ((val XReg (value_regs_get val 0)))
1910
+ (rv_zexth val)))
1911
+
1912
+ ;; With `zba` we have a `zext.w` instruction
1913
+ (rule 2 (extend val (ExtendOp.Zero) $I32 $I64)
1914
+ (if-let $true (has_zba))
1915
+ (let ((val XReg (value_regs_get val 0)))
1916
+ (rv_zextw val)))
1917
+
1918
+ ;;; Signed rules extending to I128
1919
+ ;; Extend the bottom part, and extract the sign bit from the bottom as the top
1920
+ (rule 3 (extend val (ExtendOp.Signed) (fits_in_64 from_ty) $I128)
1921
+ (let ((val XReg (value_regs_get val 0))
1922
+ (low XReg (sext val from_ty $I64))
1923
+ (high XReg (rv_srai low (imm12_const 63))))
1924
+ (value_regs low high)))
1925
+
1926
+ ;;; Unsigned rules extending to I128
1927
+ ;; Extend the bottom register to I64 and then just zero out the top half.
1928
+ (rule 3 (extend val (ExtendOp.Zero) (fits_in_64 from_ty) $I128)
1929
+ (let ((val XReg (value_regs_get val 0))
1930
+ (low XReg (zext val from_ty $I64))
1931
+ (high XReg (load_u64_constant 0)))
1932
+ (value_regs low high)))
1933
+
1934
+ ;; Catch all rule for ignoring extensions of the same type.
1935
+ (rule 4 (extend val _ ty ty) val)
1936
+
1937
+
1938
+
1939
+ (decl lower_b128_binary (AluOPRRR ValueRegs ValueRegs) ValueRegs)
1940
+ (rule
1941
+ (lower_b128_binary op a b)
1942
+ (let
1943
+ ( ;; low part.
1944
+ (low XReg (alu_rrr op (value_regs_get a 0) (value_regs_get b 0)))
1945
+ ;; high part.
1946
+ (high XReg (alu_rrr op (value_regs_get a 1) (value_regs_get b 1))))
1947
+ (value_regs low high)))
1948
+
1949
+ (decl lower_umlhi (Type XReg XReg) XReg)
1950
+ (rule 1 (lower_umlhi $I64 rs1 rs2)
1951
+ (rv_mulhu rs1 rs2))
1952
+
1953
+ (rule (lower_umlhi ty rs1 rs2)
1954
+ (let
1955
+ ((tmp XReg (rv_mul (zext rs1 ty $I64) (zext rs2 ty $I64))))
1956
+ (rv_srli tmp (imm12_const (ty_bits ty)))))
1957
+
1958
+ (decl lower_smlhi (Type XReg XReg) XReg)
1959
+ (rule 1
1960
+ (lower_smlhi $I64 rs1 rs2)
1961
+ (rv_mulh rs1 rs2))
1962
+
1963
+ (rule
1964
+ (lower_smlhi ty rs1 rs2)
1965
+ (let
1966
+ ((tmp XReg (rv_mul rs1 rs2)))
1967
+ (rv_srli tmp (imm12_const (ty_bits ty)))))
1968
+
1969
+
1970
+ (decl lower_rotl (Type XReg XReg) XReg)
1971
+
1972
+ (rule 1
1973
+ (lower_rotl $I64 rs amount)
1974
+ (if-let $true (has_zbb))
1975
+ (rv_rol rs amount))
1976
+
1977
+ (rule
1978
+ (lower_rotl $I64 rs amount)
1979
+ (if-let $false (has_zbb))
1980
+ (lower_rotl_shift $I64 rs amount))
1981
+
1982
+ (rule 1
1983
+ (lower_rotl $I32 rs amount)
1984
+ (if-let $true (has_zbb))
1985
+ (rv_rolw rs amount))
1986
+
1987
+ (rule
1988
+ (lower_rotl $I32 rs amount)
1989
+ (if-let $false (has_zbb))
1990
+ (lower_rotl_shift $I32 rs amount))
1991
+
1992
+ (rule -1
1993
+ (lower_rotl ty rs amount)
1994
+ (lower_rotl_shift ty rs amount))
1995
+
1996
+ ;;; using shift to implement rotl.
1997
+ (decl lower_rotl_shift (Type XReg XReg) XReg)
1998
+
1999
+ ;;; for I8 and I16 ...
2000
+ (rule
2001
+ (lower_rotl_shift ty rs amount)
2002
+ (let
2003
+ ((x ValueRegs (gen_shamt ty amount))
2004
+ (shamt Reg (value_regs_get x 0))
2005
+ (len_sub_shamt Reg (value_regs_get x 1))
2006
+ ;;
2007
+ (part1 Reg (rv_sll rs shamt))
2008
+ ;;
2009
+ (part2 Reg (rv_srl rs len_sub_shamt))
2010
+ (part3 Reg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) part2)))
2011
+ (rv_or part1 part3)))
2012
+
2013
+
2014
+ ;;;; construct shift amount.rotl on i128 will use shift to implement. So can call this function.
2015
+ ;;;; this will return shift amount and (ty_bits - "shift amount")
2016
+ ;;;; if ty_bits is greater than 64 like i128, then shmat will fallback to 64.because We are 64 bit platform.
2017
+ (decl gen_shamt (Type XReg) ValueRegs)
2018
+ (extern constructor gen_shamt gen_shamt)
2019
+
2020
+ (decl lower_rotr (Type XReg XReg) XReg)
2021
+
2022
+ (rule 1
2023
+ (lower_rotr $I64 rs amount)
2024
+ (if-let $true (has_zbb))
2025
+ (rv_ror rs amount))
2026
+ (rule
2027
+ (lower_rotr $I64 rs amount)
2028
+ (if-let $false (has_zbb))
2029
+ (lower_rotr_shift $I64 rs amount))
2030
+
2031
+ (rule 1
2032
+ (lower_rotr $I32 rs amount)
2033
+ (if-let $true (has_zbb))
2034
+ (rv_rorw rs amount))
2035
+
2036
+ (rule
2037
+ (lower_rotr $I32 rs amount)
2038
+ (if-let $false (has_zbb))
2039
+ (lower_rotr_shift $I32 rs amount))
2040
+
2041
+ (rule -1
2042
+ (lower_rotr ty rs amount)
2043
+ (lower_rotr_shift ty rs amount))
2044
+
2045
+ (decl lower_rotr_shift (Type XReg XReg) XReg)
2046
+
2047
+ ;;;
2048
+ (rule
2049
+ (lower_rotr_shift ty rs amount)
2050
+ (let
2051
+ ((x ValueRegs (gen_shamt ty amount))
2052
+ (shamt XReg (value_regs_get x 0))
2053
+ (len_sub_shamt XReg (value_regs_get x 1))
2054
+ ;;
2055
+ (part1 XReg (rv_srl rs shamt))
2056
+ ;;
2057
+ (part2 XReg (rv_sll rs len_sub_shamt))
2058
+ ;;
2059
+ (part3 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) part2)))
2060
+ (rv_or part1 part3)))
2061
+
2062
+
2063
+
2064
+ ;; bseti: Set a single bit in a register, indexed by a constant.
2065
+ (decl gen_bseti (Reg u64) Reg)
2066
+ (rule (gen_bseti val bit)
2067
+ (if-let $false (has_zbs))
2068
+ (if-let $false (u64_le bit 12))
2069
+ (let ((const XReg (load_u64_constant (u64_shl 1 bit))))
2070
+ (rv_or val const)))
2071
+
2072
+ (rule (gen_bseti val bit)
2073
+ (if-let $false (has_zbs))
2074
+ (if-let $true (u64_le bit 12))
2075
+ (rv_ori val (imm12_const (u64_as_i32 (u64_shl 1 bit)))))
2076
+
2077
+ (rule (gen_bseti val bit)
2078
+ (if-let $true (has_zbs))
2079
+ (rv_bseti val (imm12_const (u64_as_i32 bit))))
2080
+
2081
+
2082
+ (decl gen_popcnt (Reg Type) Reg)
2083
+ (rule
2084
+ (gen_popcnt rs ty)
2085
+ (let
2086
+ ((tmp WritableXReg (temp_writable_xreg))
2087
+ (step WritableXReg (temp_writable_xreg))
2088
+ (sum WritableXReg (temp_writable_xreg))
2089
+ (_ Unit (emit (MInst.Popcnt sum step tmp rs ty))))
2090
+ (writable_reg_to_reg sum)))
2091
+
2092
+ (decl lower_popcnt (XReg Type) XReg)
2093
+ (rule 1 (lower_popcnt rs ty)
2094
+ (if-let $true (has_zbb))
2095
+ (rv_cpop (zext rs ty $I64)))
2096
+
2097
+ (rule (lower_popcnt rs ty)
2098
+ (if-let $false (has_zbb))
2099
+ (gen_popcnt rs ty))
2100
+
2101
+ (decl lower_popcnt_i128 (ValueRegs) ValueRegs)
2102
+ (rule
2103
+ (lower_popcnt_i128 a)
2104
+ (let
2105
+ ( ;; low part.
2106
+ (low XReg (lower_popcnt (value_regs_get a 0) $I64))
2107
+ ;; high part.
2108
+ (high XReg (lower_popcnt (value_regs_get a 1) $I64))
2109
+ ;; add toghter.
2110
+ (result XReg (rv_add low high)))
2111
+ (value_regs result (load_u64_constant 0))))
2112
+
2113
+ (decl lower_i128_rotl (ValueRegs ValueRegs) ValueRegs)
2114
+ (rule
2115
+ (lower_i128_rotl x y)
2116
+ (let
2117
+ ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
2118
+ (shamt XReg (value_regs_get tmp 0))
2119
+ (len_sub_shamt XReg (value_regs_get tmp 1))
2120
+ ;;
2121
+ (low_part1 XReg (rv_sll (value_regs_get x 0) shamt))
2122
+ (low_part2 XReg (rv_srl (value_regs_get x 1) len_sub_shamt))
2123
+ ;;; if shamt == 0 low_part2 will overflow we should zero instead.
2124
+ (low_part3 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part2))
2125
+ (low XReg (rv_or low_part1 low_part3))
2126
+ ;;
2127
+ (high_part1 XReg (rv_sll (value_regs_get x 1) shamt))
2128
+ (high_part2 XReg (rv_srl (value_regs_get x 0) len_sub_shamt))
2129
+ (high_part3 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) high_part2))
2130
+ (high XReg (rv_or high_part1 high_part3))
2131
+ ;;
2132
+ (const64 XReg (load_u64_constant 64))
2133
+ (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
2134
+ ;; right now we only rotate less than 64 bits.
2135
+ ;; if shamt is greater than or equal 64 , we should switch low and high.
2136
+ (value_regs
2137
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
2138
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 low high)
2139
+ )))
2140
+
2141
+
2142
+ (decl lower_i128_rotr (ValueRegs ValueRegs) ValueRegs)
2143
+ (rule
2144
+ (lower_i128_rotr x y)
2145
+ (let
2146
+ ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
2147
+ (shamt XReg (value_regs_get tmp 0))
2148
+ (len_sub_shamt XReg (value_regs_get tmp 1))
2149
+ ;;
2150
+ (low_part1 XReg (rv_srl (value_regs_get x 0) shamt))
2151
+ (low_part2 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
2152
+ ;;; if shamt == 0 low_part2 will overflow we should zero instead.
2153
+ (low_part3 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part2))
2154
+ (low XReg (rv_or low_part1 low_part3))
2155
+ ;;
2156
+ (high_part1 XReg (rv_srl (value_regs_get x 1) shamt))
2157
+ (high_part2 XReg (rv_sll (value_regs_get x 0) len_sub_shamt))
2158
+ (high_part3 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) high_part2))
2159
+ (high XReg (rv_or high_part1 high_part3))
2160
+
2161
+ ;;
2162
+ (const64 XReg (load_u64_constant 64))
2163
+ (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
2164
+ ;; right now we only rotate less than 64 bits.
2165
+ ;; if shamt is greater than or equal 64 , we should switch low and high.
2166
+ (value_regs
2167
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
2168
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 low high)
2169
+ )))
2170
+
2171
+ (decl gen_amode (Reg Offset32 Type) AMode)
2172
+ (extern constructor gen_amode gen_amode)
2173
+
2174
+ ;; Generates a AMode that points to a constant in the constant pool.
2175
+ (decl gen_const_amode (VCodeConstant) AMode)
2176
+ (extern constructor gen_const_amode gen_const_amode)
2177
+
2178
+ (decl offset32_imm (i32) Offset32)
2179
+ (extern constructor offset32_imm offset32_imm)
2180
+
2181
+ ;; helper function to load from memory.
2182
+ (decl gen_load (Reg Offset32 LoadOP MemFlags Type) Reg)
2183
+ (rule
2184
+ (gen_load p offset op flags ty)
2185
+ (let
2186
+ ((tmp WritableReg (temp_writable_reg ty))
2187
+ (_ Unit (emit (MInst.Load tmp op flags (gen_amode p offset $I64)))))
2188
+ tmp))
2189
+
2190
+ (decl gen_load_128 (Reg Offset32 MemFlags) ValueRegs)
2191
+ (rule
2192
+ (gen_load_128 p offset flags)
2193
+ (let
2194
+ ((low Reg (gen_load p offset (LoadOP.Ld) flags $I64))
2195
+ (high Reg (gen_load p (offset32_add offset 8) (LoadOP.Ld) flags $I64)))
2196
+ (value_regs low high)))
2197
+
2198
+ (decl default_memflags () MemFlags)
2199
+ (extern constructor default_memflags default_memflags)
2200
+
2201
+ (decl offset32_add (Offset32 i64) Offset32)
2202
+ (extern constructor offset32_add offset32_add)
2203
+
2204
+ ;; helper function to store to memory.
2205
+ (decl gen_store (Reg Offset32 StoreOP MemFlags Reg) InstOutput)
2206
+ (rule
2207
+ (gen_store base offset op flags src)
2208
+ (side_effect (SideEffectNoResult.Inst (MInst.Store (gen_amode base offset $I64) op flags src)))
2209
+ )
2210
+
2211
+ (decl gen_store_128 (Reg Offset32 MemFlags ValueRegs) InstOutput)
2212
+ (rule
2213
+ (gen_store_128 p offset flags src)
2214
+ (side_effect
2215
+ (SideEffectNoResult.Inst2
2216
+ (MInst.Store (gen_amode p offset $I64) (StoreOP.Sd) flags (value_regs_get src 0))
2217
+ (MInst.Store (gen_amode p (offset32_add offset 8) $I64) (StoreOP.Sd) flags (value_regs_get src 1)))))
2218
+
2219
+ (decl valid_atomic_transaction (Type) Type)
2220
+ (extern extractor valid_atomic_transaction valid_atomic_transaction)
2221
+
2222
+ ;;helper function.
2223
+ ;;construct an atomic instruction.
2224
+ (decl gen_atomic (AtomicOP Reg Reg AMO) Reg)
2225
+ (rule
2226
+ (gen_atomic op addr src amo)
2227
+ (let
2228
+ ((tmp WritableXReg (temp_writable_xreg))
2229
+ (_ Unit (emit (MInst.Atomic op tmp addr src amo))))
2230
+ tmp))
2231
+
2232
+ ;; helper function
2233
+ (decl get_atomic_rmw_op (Type AtomicRmwOp) AtomicOP)
2234
+ (rule
2235
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Add))
2236
+ (AtomicOP.AmoaddW))
2237
+ (rule
2238
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Add))
2239
+ (AtomicOP.AmoaddD))
2240
+
2241
+ (rule
2242
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.And))
2243
+ (AtomicOP.AmoandW))
2244
+
2245
+ (rule
2246
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.And))
2247
+ (AtomicOP.AmoandD))
2248
+
2249
+ (rule
2250
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Or))
2251
+ (AtomicOP.AmoorW))
2252
+
2253
+ (rule
2254
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Or))
2255
+ (AtomicOP.AmoorD))
2256
+
2257
+ (rule
2258
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smax))
2259
+ (AtomicOP.AmomaxW))
2260
+
2261
+ (rule
2262
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smax))
2263
+ (AtomicOP.AmomaxD))
2264
+
2265
+ (rule
2266
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smin))
2267
+ (AtomicOP.AmominW))
2268
+
2269
+ (rule
2270
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smin))
2271
+ (AtomicOP.AmominD))
2272
+
2273
+ (rule
2274
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umax))
2275
+ (AtomicOP.AmomaxuW)
2276
+ )
2277
+
2278
+ (rule
2279
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umax))
2280
+ (AtomicOP.AmomaxuD))
2281
+
2282
+ (rule
2283
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umin))
2284
+ (AtomicOP.AmominuW))
2285
+
2286
+ (rule
2287
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umin))
2288
+ (AtomicOP.AmominuD))
2289
+
2290
+ (rule
2291
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xchg))
2292
+ (AtomicOP.AmoswapW))
2293
+
2294
+ (rule
2295
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xchg))
2296
+ (AtomicOP.AmoswapD))
2297
+
2298
+ (rule
2299
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xor))
2300
+ (AtomicOP.AmoxorW))
2301
+
2302
+ (rule
2303
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xor))
2304
+ (AtomicOP.AmoxorD))
2305
+
2306
+ (decl atomic_amo () AMO)
2307
+ (extern constructor atomic_amo atomic_amo)
2308
+
2309
+
2310
+ (decl gen_atomic_load (Reg Type) Reg)
2311
+ (rule
2312
+ (gen_atomic_load p ty)
2313
+ (let
2314
+ ((tmp WritableXReg (temp_writable_xreg))
2315
+ (_ Unit (emit (MInst.AtomicLoad tmp ty p))))
2316
+ (writable_reg_to_reg tmp)))
2317
+
2318
+ ;;;
2319
+ (decl gen_atomic_store (Reg Type Reg) InstOutput)
2320
+ (rule
2321
+ (gen_atomic_store p ty src)
2322
+ (side_effect (SideEffectNoResult.Inst (MInst.AtomicStore src ty p)))
2323
+ )
2324
+
2325
+
2326
+ (decl gen_stack_addr (StackSlot Offset32) Reg)
2327
+ (extern constructor gen_stack_addr gen_stack_addr)
2328
+
2329
+ ;;
2330
+ (decl gen_select (Type Reg ValueRegs ValueRegs) ValueRegs)
2331
+ (rule
2332
+ (gen_select ty c x y)
2333
+ (let
2334
+ ((dst VecWritableReg (alloc_vec_writable ty))
2335
+ ;;
2336
+ (reuslt VecWritableReg (vec_writable_clone dst))
2337
+ (_ Unit (emit (MInst.Select dst ty c x y))))
2338
+ (vec_writable_to_regs reuslt)))
2339
+
2340
+ ;; Parameters are "intcc compare_a compare_b rs1 rs2".
2341
+ (decl gen_select_reg (IntCC XReg XReg Reg Reg) Reg)
2342
+ (extern constructor gen_select_reg gen_select_reg)
2343
+
2344
+ ;; load a constant into reg.
2345
+ (decl load_u64_constant (u64) Reg)
2346
+ (extern constructor load_u64_constant load_u64_constant)
2347
+
2348
+ ;;; clone WritableReg
2349
+ ;;; if not rust compiler will complain about use moved value.
2350
+ (decl vec_writable_clone (VecWritableReg) VecWritableReg)
2351
+ (extern constructor vec_writable_clone vec_writable_clone)
2352
+
2353
+ (decl vec_writable_to_regs (VecWritableReg) ValueRegs)
2354
+ (extern constructor vec_writable_to_regs vec_writable_to_regs)
2355
+
2356
+ (decl alloc_vec_writable (Type) VecWritableReg)
2357
+ (extern constructor alloc_vec_writable alloc_vec_writable)
2358
+
2359
+ (decl gen_int_select (Type IntSelectOP ValueRegs ValueRegs) ValueRegs)
2360
+ (rule
2361
+ (gen_int_select ty op x y)
2362
+ (let
2363
+ ( ;;;
2364
+ (dst VecWritableReg (alloc_vec_writable ty))
2365
+ ;;;
2366
+ (_ Unit (emit (MInst.IntSelect op (vec_writable_clone dst) x y ty))))
2367
+ (vec_writable_to_regs dst)))
2368
+
2369
+ (decl udf (TrapCode) InstOutput)
2370
+ (rule
2371
+ (udf code)
2372
+ (side_effect (SideEffectNoResult.Inst (MInst.Udf code))))
2373
+
2374
+ (decl load_op (Type) LoadOP)
2375
+ (extern constructor load_op load_op)
2376
+
2377
+ (decl store_op (Type) StoreOP)
2378
+ (extern constructor store_op store_op)
2379
+
2380
+ ;; bool is "is_signed"
2381
+ (decl int_load_op (bool u8) LoadOP)
2382
+ (rule
2383
+ (int_load_op $false 8)
2384
+ (LoadOP.Lbu))
2385
+
2386
+ (rule
2387
+ (int_load_op $true 8)
2388
+ (LoadOP.Lb))
2389
+
2390
+ (rule
2391
+ (int_load_op $false 16)
2392
+ (LoadOP.Lhu))
2393
+ (rule
2394
+ (int_load_op $true 16)
2395
+ (LoadOP.Lh))
2396
+ (rule
2397
+ (int_load_op $false 32)
2398
+ (LoadOP.Lwu))
2399
+ (rule
2400
+ (int_load_op $true 32)
2401
+ (LoadOP.Lw))
2402
+
2403
+ (rule
2404
+ (int_load_op _ 64)
2405
+ (LoadOP.Ld))
2406
+
2407
+ ;;;; load extern name
2408
+ (decl load_ext_name (ExternalName i64) Reg)
2409
+ (extern constructor load_ext_name load_ext_name)
2410
+
2411
+ (decl int_convert_2_float_op (Type bool Type) FpuOPRR)
2412
+ (extern constructor int_convert_2_float_op int_convert_2_float_op)
2413
+
2414
+ ;;;;
2415
+ (decl gen_fcvt_int (bool FReg bool Type Type) XReg)
2416
+ (rule
2417
+ (gen_fcvt_int is_sat rs is_signed in_type out_type)
2418
+ (let
2419
+ ((result WritableReg (temp_writable_reg out_type))
2420
+ (tmp WritableFReg (temp_writable_freg))
2421
+ (_ Unit (emit (MInst.FcvtToInt is_sat result tmp rs is_signed in_type out_type))))
2422
+ (writable_reg_to_reg result)))
2423
+
2424
+ ;;; some float binary operation
2425
+ ;;; 1. need move into x reister.
2426
+ ;;; 2. do the operation.
2427
+ ;;; 3. move back.
2428
+ (decl lower_float_binary (AluOPRRR FReg FReg Type) FReg)
2429
+ (rule
2430
+ (lower_float_binary op rs1 rs2 ty)
2431
+ (let ((x_rs1 XReg (move_f_to_x rs1 ty))
2432
+ (x_rs2 XReg (move_f_to_x rs2 ty))
2433
+ (tmp XReg (alu_rrr op x_rs1 x_rs2)))
2434
+ (move_x_to_f tmp (float_int_of_same_size ty))))
2435
+
2436
+
2437
+ ;;; lower icmp
2438
+ (decl lower_icmp (IntCC ValueRegs ValueRegs Type) Reg)
2439
+ (rule 1 (lower_icmp cc x y ty)
2440
+ (if (signed_cond_code cc))
2441
+ (gen_icmp cc (ext_int_if_need $true x ty) (ext_int_if_need $true y ty) ty))
2442
+ (rule (lower_icmp cc x y ty)
2443
+ (gen_icmp cc (ext_int_if_need $false x ty) (ext_int_if_need $false y ty) ty))
2444
+
2445
+
2446
+ (decl i128_sub (ValueRegs ValueRegs) ValueRegs)
2447
+ (rule
2448
+ (i128_sub x y )
2449
+ (let
2450
+ (;; low part.
2451
+ (low XReg (rv_sub (value_regs_get x 0) (value_regs_get y 0)))
2452
+ ;; compute borrow.
2453
+ (borrow XReg (rv_sltu (value_regs_get x 0) low))
2454
+ ;;
2455
+ (high_tmp XReg (rv_sub (value_regs_get x 1) (value_regs_get y 1)))
2456
+ ;;
2457
+ (high XReg (rv_sub high_tmp borrow)))
2458
+ (value_regs low high)))
2459
+
2460
+
2461
+ ;;; Returns the sum in the first register, and the overflow test in the second.
2462
+ (decl lower_uadd_overflow (XReg XReg Type) ValueRegs)
2463
+
2464
+ (rule 1
2465
+ (lower_uadd_overflow x y $I64)
2466
+ (let ((tmp XReg (rv_add x y))
2467
+ (test XReg (gen_icmp (IntCC.UnsignedLessThan) tmp x $I64)))
2468
+ (value_regs tmp test)))
2469
+
2470
+ (rule
2471
+ (lower_uadd_overflow x y (fits_in_32 ty))
2472
+ (let ((tmp_x XReg (zext x ty $I64))
2473
+ (tmp_y XReg (zext y ty $I64))
2474
+ (sum XReg (rv_add tmp_x tmp_y))
2475
+ (test XReg (rv_srli sum (imm12_const (ty_bits ty)))))
2476
+ (value_regs sum test)))
2477
+
2478
+ (decl label_to_br_target (MachLabel) BranchTarget)
2479
+ (extern constructor label_to_br_target label_to_br_target)
2480
+
2481
+ (decl gen_jump (MachLabel) MInst)
2482
+ (rule
2483
+ (gen_jump v)
2484
+ (MInst.Jal (label_to_br_target v)))
2485
+
2486
+ (decl vec_label_get (VecMachLabel u8) MachLabel )
2487
+ (extern constructor vec_label_get vec_label_get)
2488
+
2489
+ (decl partial lower_branch (Inst VecMachLabel) Unit)
2490
+ (rule (lower_branch (jump _) targets )
2491
+ (emit_side_effect (SideEffectNoResult.Inst (gen_jump (vec_label_get targets 0)))))
2492
+
2493
+ ;;; cc a b targets Type
2494
+ (decl lower_br_icmp (IntCC ValueRegs ValueRegs VecMachLabel Type) Unit)
2495
+ (extern constructor lower_br_icmp lower_br_icmp)
2496
+
2497
+ ;; int scalar zero regs.
2498
+ (decl int_zero_reg (Type) ValueRegs)
2499
+ (extern constructor int_zero_reg int_zero_reg)
2500
+
2501
+ (decl lower_cond_br (IntCC ValueRegs VecMachLabel Type) Unit)
2502
+ (extern constructor lower_cond_br lower_cond_br)
2503
+
2504
+ (decl intcc_to_extend_op (IntCC) ExtendOp)
2505
+ (extern constructor intcc_to_extend_op intcc_to_extend_op)
2506
+
2507
+ ;; Normalize a value for comparision.
2508
+ ;;
2509
+ ;; This ensures that types smaller than a register don't accidentally
2510
+ ;; pass undefined high bits when being compared as a full register.
2511
+ (decl normalize_cmp_value (Type ValueRegs ExtendOp) ValueRegs)
2512
+
2513
+ (rule 1 (normalize_cmp_value (fits_in_32 ity) r op)
2514
+ (extend r op ity $I64))
2515
+
2516
+ (rule (normalize_cmp_value $I64 r _) r)
2517
+ (rule (normalize_cmp_value $I128 r _) r)
2518
+
2519
+ (decl normalize_fcvt_from_int (XReg Type ExtendOp) XReg)
2520
+ (rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op)
2521
+ (value_regs_get (extend r op ty $I64) 0))
2522
+ (rule 1 (normalize_fcvt_from_int r _ _)
2523
+ r)
2524
+
2525
+ ;; Convert a truthy value, possibly of more than one register (an
2526
+ ;; I128), to one register. If narrower than 64 bits, must have already
2527
+ ;; been masked (e.g. by `normalize_cmp_value`).
2528
+ (decl truthy_to_reg (Type ValueRegs) XReg)
2529
+ (rule 1 (truthy_to_reg (fits_in_64 _) regs)
2530
+ (value_regs_get regs 0))
2531
+ (rule 0 (truthy_to_reg $I128 regs)
2532
+ (let ((lo XReg (value_regs_get regs 0))
2533
+ (hi XReg (value_regs_get regs 1)))
2534
+ (rv_or lo hi)))
2535
+
2536
+ ;; Default behavior for branching based on an input value.
2537
+ (rule
2538
+ (lower_branch (brif v @ (value_type ty) _ _) targets)
2539
+ (lower_cond_br (IntCC.NotEqual) (normalize_cmp_value ty v (ExtendOp.Zero)) targets ty))
2540
+
2541
+ ;; Special case for SI128 to reify the comparison value and branch on it.
2542
+ (rule 2
2543
+ (lower_branch (brif v @ (value_type $I128) _ _) targets)
2544
+ (let ((zero ValueRegs (value_regs (zero_reg) (zero_reg)))
2545
+ (cmp XReg (gen_icmp (IntCC.NotEqual) v zero $I128)))
2546
+ (lower_cond_br (IntCC.NotEqual) cmp targets $I64)))
2547
+
2548
+ ;; Branching on the result of an icmp
2549
+ (rule 1
2550
+ (lower_branch (brif (maybe_uextend (icmp cc a @ (value_type ty) b)) _ _) targets)
2551
+ (lower_br_icmp cc a b targets ty))
2552
+
2553
+ ;; Branching on the result of an fcmp
2554
+ (rule 1
2555
+ (lower_branch (brif (maybe_uextend (fcmp cc a @ (value_type ty) b)) _ _) targets)
2556
+ (if-let $true (floatcc_unordered cc))
2557
+ (let ((then BranchTarget (label_to_br_target (vec_label_get targets 0)))
2558
+ (else BranchTarget (label_to_br_target (vec_label_get targets 1))))
2559
+ (emit_side_effect (cond_br (emit_fcmp (floatcc_inverse cc) ty a b) else then))))
2560
+
2561
+ (rule 1
2562
+ (lower_branch (brif (maybe_uextend (fcmp cc a @ (value_type ty) b)) _ _) targets)
2563
+ (if-let $false (floatcc_unordered cc))
2564
+ (let ((then BranchTarget (label_to_br_target (vec_label_get targets 0)))
2565
+ (else BranchTarget (label_to_br_target (vec_label_get targets 1))))
2566
+ (emit_side_effect (cond_br (emit_fcmp cc ty a b) then else))))
2567
+
2568
+ ;;;
2569
+ (decl lower_br_table (Reg VecMachLabel) Unit)
2570
+ (extern constructor lower_br_table lower_br_table)
2571
+
2572
+ (rule
2573
+ (lower_branch (br_table index _) targets)
2574
+ (lower_br_table index targets))
2575
+
2576
+ (decl load_ra () Reg)
2577
+ (extern constructor load_ra load_ra)
2578
+
2579
+
2580
+ ;; Generates a bitcast instruction.
2581
+ ;; Args are: src, src_ty, dst_ty
2582
+ (decl gen_bitcast (Reg Type Type) Reg)
2583
+ (rule 1 (gen_bitcast r $F32 $I32) (rv_fmvxw r))
2584
+ (rule 1 (gen_bitcast r $F64 $I64) (rv_fmvxd r))
2585
+ (rule 1 (gen_bitcast r $I32 $F32) (rv_fmvwx r))
2586
+ (rule 1 (gen_bitcast r $I64 $F64) (rv_fmvdx r))
2587
+ (rule (gen_bitcast r _ _) r)
2588
+
2589
+ (decl move_f_to_x (FReg Type) XReg)
2590
+ (rule (move_f_to_x r $F32) (gen_bitcast r $F32 $I32))
2591
+ (rule (move_f_to_x r $F64) (gen_bitcast r $F64 $I64))
2592
+
2593
+ (decl move_x_to_f (XReg Type) FReg)
2594
+ (rule (move_x_to_f r $I32) (gen_bitcast r $I32 $F32))
2595
+ (rule (move_x_to_f r $I64) (gen_bitcast r $I64 $F64))
2596
+
2597
+ (decl float_int_of_same_size (Type) Type)
2598
+ (rule (float_int_of_same_size $F32) $I32)
2599
+ (rule (float_int_of_same_size $F64) $I64)
2600
+
2601
+
2602
+ (decl gen_rev8 (XReg) XReg)
2603
+ (rule 1
2604
+ (gen_rev8 rs)
2605
+ (if-let $true (has_zbb))
2606
+ (rv_rev8 rs))
2607
+
2608
+ (rule
2609
+ (gen_rev8 rs)
2610
+ (if-let $false (has_zbb))
2611
+ (let
2612
+ ((rd WritableXReg (temp_writable_xreg))
2613
+ (tmp WritableXReg (temp_writable_xreg))
2614
+ (step WritableXReg (temp_writable_xreg))
2615
+ (_ Unit (emit (MInst.Rev8 rs step tmp rd))))
2616
+ (writable_reg_to_reg rd)))
2617
+
2618
+
2619
+ (decl gen_brev8 (Reg Type) Reg)
2620
+ (rule 1
2621
+ (gen_brev8 rs _)
2622
+ (if-let $true (has_zbkb))
2623
+ (rv_brev8 rs))
2624
+ (rule
2625
+ (gen_brev8 rs ty)
2626
+ (if-let $false (has_zbkb))
2627
+ (let
2628
+ ((tmp WritableXReg (temp_writable_xreg))
2629
+ (tmp2 WritableXReg (temp_writable_xreg))
2630
+ (step WritableXReg (temp_writable_xreg))
2631
+ (rd WritableXReg (temp_writable_xreg))
2632
+ (_ Unit (emit (MInst.Brev8 rs ty step tmp tmp2 rd))))
2633
+ (writable_reg_to_reg rd)))
2634
+
2635
+ ;; Negates x
2636
+ ;; Equivalent to 0 - x
2637
+ (decl neg (Type ValueRegs) ValueRegs)
2638
+ (rule 1 (neg (fits_in_64 (ty_int ty)) val)
2639
+ (value_reg
2640
+ (rv_neg (value_regs_get val 0))))
2641
+
2642
+ (rule 2 (neg $I128 val)
2643
+ (i128_sub (value_regs_zero) val))
2644
+
2645
+
2646
+ ;; Selects the greatest of two registers as signed values.
2647
+ (decl max (Type XReg XReg) XReg)
2648
+ (rule (max (fits_in_64 (ty_int ty)) x y)
2649
+ (if-let $true (has_zbb))
2650
+ (rv_max x y))
2651
+
2652
+ (rule (max (fits_in_64 (ty_int ty)) x y)
2653
+ (if-let $false (has_zbb))
2654
+ (gen_select_reg (IntCC.SignedGreaterThan) x y x y))
2655
+
2656
+
2657
+ (decl lower_iabs (Type XReg) XReg)
2658
+
2659
+ ; I64 and lower
2660
+ ; Generate the following code:
2661
+ ; sext.{b,h,w} a0, a0
2662
+ ; neg a1, a0
2663
+ ; max a0, a0, a1
2664
+ (rule (lower_iabs (fits_in_64 ty) val)
2665
+ (let ((extended XReg (sext val ty $I64))
2666
+ (negated XReg (rv_neg extended)))
2667
+ (max $I64 extended negated)))
2668
+
2669
+ (decl gen_trapif (XReg TrapCode) InstOutput)
2670
+ (rule
2671
+ (gen_trapif test trap_code)
2672
+ (side_effect (SideEffectNoResult.Inst (MInst.TrapIf test trap_code))))
2673
+
2674
+ (decl gen_trapifc (IntCC XReg XReg TrapCode) InstOutput)
2675
+ (rule
2676
+ (gen_trapifc cc a b trap_code)
2677
+ (side_effect (SideEffectNoResult.Inst (MInst.TrapIfC a b cc trap_code))))
2678
+
2679
+ (decl shift_int_to_most_significant (XReg Type) XReg)
2680
+ (extern constructor shift_int_to_most_significant shift_int_to_most_significant)
2681
+
2682
+ ;;; generate div overflow.
2683
+ (decl gen_div_overflow (XReg XReg Type) InstOutput)
2684
+ (rule
2685
+ (gen_div_overflow rs1 rs2 ty)
2686
+ (let
2687
+ ((r_const_neg_1 XReg (load_imm12 -1))
2688
+ (r_const_min XReg (rv_slli (load_imm12 1) (imm12_const 63)))
2689
+ (tmp_rs1 XReg (shift_int_to_most_significant rs1 ty))
2690
+ (t1 XReg (gen_icmp (IntCC.Equal) r_const_neg_1 rs2 ty))
2691
+ (t2 XReg (gen_icmp (IntCC.Equal) r_const_min tmp_rs1 ty))
2692
+ (test XReg (rv_and t1 t2)))
2693
+ (gen_trapif test (TrapCode.IntegerOverflow))))
2694
+
2695
+ (decl gen_div_by_zero (XReg) InstOutput)
2696
+ (rule
2697
+ (gen_div_by_zero r)
2698
+ (gen_trapifc (IntCC.Equal) (zero_reg) r (TrapCode.IntegerDivisionByZero)))
2699
+
2700
+ ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2701
+
2702
+ (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
2703
+ (extern constructor gen_call gen_call)
2704
+
2705
+ (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
2706
+ (extern constructor gen_call_indirect gen_call_indirect)
2707
+
2708
+ ;;; this is trying to imitate aarch64 `madd` instruction.
2709
+ (decl madd (XReg XReg XReg) XReg)
2710
+ (rule
2711
+ (madd n m a)
2712
+ (let
2713
+ ((t XReg (rv_mul n m)))
2714
+ (rv_add t a)))
2715
+
2716
+ ;;;; Helpers for bmask ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2717
+
2718
+ (decl lower_bmask (Type Type ValueRegs) ValueRegs)
2719
+
2720
+ ;; Produces -1 if the 64-bit value is non-zero, and 0 otherwise.
2721
+ ;; If the type is smaller than 64 bits, we need to mask off the
2722
+ ;; high bits.
2723
+ (rule
2724
+ 0
2725
+ (lower_bmask (fits_in_64 _) (fits_in_64 in_ty) val)
2726
+ (let ((input XReg (truthy_to_reg in_ty (normalize_cmp_value in_ty val (ExtendOp.Zero))))
2727
+ (non_zero XReg (rv_snez input)))
2728
+ (value_reg (rv_neg non_zero))))
2729
+
2730
+ ;; Bitwise-or the two registers that make up the 128-bit value, then recurse as
2731
+ ;; though it was a 64-bit value.
2732
+ (rule
2733
+ 1
2734
+ (lower_bmask (fits_in_64 ty) $I128 val)
2735
+ (let ((lo XReg (value_regs_get val 0))
2736
+ (hi XReg (value_regs_get val 1))
2737
+ (combined XReg (rv_or lo hi)))
2738
+ (lower_bmask ty $I64 (value_reg combined))))
2739
+
2740
+ ;; Conversion of one 64-bit value to a 128-bit one. Duplicate the result of the
2741
+ ;; bmask of the 64-bit value into both result registers of the i128.
2742
+ (rule
2743
+ 2
2744
+ (lower_bmask $I128 (fits_in_64 in_ty) val)
2745
+ (let ((res ValueRegs (lower_bmask $I64 in_ty val)))
2746
+ (value_regs (value_regs_get res 0) (value_regs_get res 0))))
2747
+
2748
+ ;; Conversion of one 64-bit value to a 128-bit one. Duplicate the result of
2749
+ ;; bmasking the 128-bit value to a 64-bit value into both registers of the
2750
+ ;; 128-bit result.
2751
+ (rule
2752
+ 3
2753
+ (lower_bmask $I128 $I128 val)
2754
+ (let ((res ValueRegs (lower_bmask $I64 $I128 val)))
2755
+ (value_regs (value_regs_get res 0) (value_regs_get res 0))))
2756
+
2757
+
2758
+ ;;;; Helpers for physical registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2759
+
2760
+ (decl gen_mov_from_preg (PReg) Reg)
2761
+
2762
+ (rule
2763
+ (gen_mov_from_preg rm)
2764
+ (let ((rd WritableXReg (temp_writable_xreg))
2765
+ (_ Unit (emit (MInst.MovFromPReg rd rm))))
2766
+ rd))
2767
+
2768
+ (decl fp_reg () PReg)
2769
+ (extern constructor fp_reg fp_reg)
2770
+
2771
+ (decl sp_reg () PReg)
2772
+ (extern constructor sp_reg sp_reg)
2773
+
2774
+ ;; Helper for creating the zero register.
2775
+ (decl zero_reg () Reg)
2776
+ (extern constructor zero_reg zero_reg)
2777
+
2778
+ (decl value_regs_zero () ValueRegs)
2779
+ (rule (value_regs_zero)
2780
+ (value_regs (imm $I64 0) (imm $I64 0)))
2781
+
2782
+ (decl writable_zero_reg () WritableReg)
2783
+ (extern constructor writable_zero_reg writable_zero_reg)
2784
+
2785
+
2786
+ ;;;; Helpers for floating point comparisons ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2787
+
2788
+ (decl not (XReg) XReg)
2789
+ (rule (not x) (rv_xori x (imm_from_bits 1)))
2790
+
2791
+ (decl is_not_nan (Type FReg) XReg)
2792
+ (rule (is_not_nan ty a) (rv_feq ty a a))
2793
+
2794
+ (decl ordered (Type FReg FReg) XReg)
2795
+ (rule (ordered ty a b) (rv_and (is_not_nan ty a) (is_not_nan ty b)))
2796
+
2797
+ (type CmpResult (enum
2798
+ (Result
2799
+ (result XReg)
2800
+ (invert bool))))
2801
+
2802
+ ;; Wrapper for the common case when constructing comparison results. It assumes
2803
+ ;; that the result isn't negated.
2804
+ (decl cmp_result (XReg) CmpResult)
2805
+ (rule (cmp_result result) (CmpResult.Result result $false))
2806
+
2807
+ ;; Wrapper for the case where it's more convenient to construct the negated
2808
+ ;; version of the comparison.
2809
+ (decl cmp_result_invert (XReg) CmpResult)
2810
+ (rule (cmp_result_invert result) (CmpResult.Result result $true))
2811
+
2812
+ ;; Consume a CmpResult, producing a branch on its result.
2813
+ (decl cond_br (CmpResult BranchTarget BranchTarget) SideEffectNoResult)
2814
+ (rule (cond_br cmp then else)
2815
+ (SideEffectNoResult.Inst
2816
+ (MInst.CondBr then else (cmp_integer_compare cmp))))
2817
+
2818
+ ;; Construct an IntegerCompare value.
2819
+ (decl int_compare (IntCC XReg XReg) IntegerCompare)
2820
+ (extern constructor int_compare int_compare)
2821
+
2822
+ ;; Convert a comparison into a branch test.
2823
+ (decl cmp_integer_compare (CmpResult) IntegerCompare)
2824
+
2825
+ (rule
2826
+ (cmp_integer_compare (CmpResult.Result res $false))
2827
+ (int_compare (IntCC.NotEqual) res (zero_reg)))
2828
+
2829
+ (rule
2830
+ (cmp_integer_compare (CmpResult.Result res $true))
2831
+ (int_compare (IntCC.Equal) res (zero_reg)))
2832
+
2833
+ ;; Convert a comparison into a boolean value.
2834
+ (decl cmp_value (CmpResult) XReg)
2835
+ (rule (cmp_value (CmpResult.Result res $false)) res)
2836
+ (rule (cmp_value (CmpResult.Result res $true)) (not res))
2837
+
2838
+ ;; Compare two floating point numbers and return a zero/non-zero result.
2839
+ (decl emit_fcmp (FloatCC Type FReg FReg) CmpResult)
2840
+
2841
+ ;; a is not nan && b is not nan
2842
+ (rule
2843
+ (emit_fcmp (FloatCC.Ordered) ty a b)
2844
+ (cmp_result (ordered ty a b)))
2845
+
2846
+ ;; a is nan || b is nan
2847
+ ;; == !(a is not nan && b is not nan)
2848
+ (rule
2849
+ (emit_fcmp (FloatCC.Unordered) ty a b)
2850
+ (cmp_result_invert (ordered ty a b)))
2851
+
2852
+ ;; a == b
2853
+ (rule
2854
+ (emit_fcmp (FloatCC.Equal) ty a b)
2855
+ (cmp_result (rv_feq ty a b)))
2856
+
2857
+ ;; a != b
2858
+ ;; == !(a == b)
2859
+ (rule
2860
+ (emit_fcmp (FloatCC.NotEqual) ty a b)
2861
+ (cmp_result_invert (rv_feq ty a b)))
2862
+
2863
+ ;; a < b || a > b
2864
+ (rule
2865
+ (emit_fcmp (FloatCC.OrderedNotEqual) ty a b)
2866
+ (cmp_result (rv_or (rv_flt ty a b) (rv_fgt ty a b))))
2867
+
2868
+ ;; !(ordered a b) || a == b
2869
+ (rule
2870
+ (emit_fcmp (FloatCC.UnorderedOrEqual) ty a b)
2871
+ (cmp_result (rv_or (not (ordered ty a b)) (rv_feq ty a b))))
2872
+
2873
+ ;; a < b
2874
+ (rule
2875
+ (emit_fcmp (FloatCC.LessThan) ty a b)
2876
+ (cmp_result (rv_flt ty a b)))
2877
+
2878
+ ;; a <= b
2879
+ (rule
2880
+ (emit_fcmp (FloatCC.LessThanOrEqual) ty a b)
2881
+ (cmp_result (rv_fle ty a b)))
2882
+
2883
+ ;; a > b
2884
+ (rule
2885
+ (emit_fcmp (FloatCC.GreaterThan) ty a b)
2886
+ (cmp_result (rv_fgt ty a b)))
2887
+
2888
+ ;; a >= b
2889
+ (rule
2890
+ (emit_fcmp (FloatCC.GreaterThanOrEqual) ty a b)
2891
+ (cmp_result (rv_fge ty a b)))
2892
+
2893
+ ;; !(ordered a b) || a < b
2894
+ ;; == !(ordered a b && a >= b)
2895
+ (rule
2896
+ (emit_fcmp (FloatCC.UnorderedOrLessThan) ty a b)
2897
+ (cmp_result_invert (rv_and (ordered ty a b) (rv_fge ty a b))))
2898
+
2899
+ ;; !(ordered a b) || a <= b
2900
+ ;; == !(ordered a b && a > b)
2901
+ (rule
2902
+ (emit_fcmp (FloatCC.UnorderedOrLessThanOrEqual) ty a b)
2903
+ (cmp_result_invert (rv_and (ordered ty a b) (rv_fgt ty a b))))
2904
+
2905
+ ;; !(ordered a b) || a > b
2906
+ ;; == !(ordered a b && a <= b)
2907
+ (rule
2908
+ (emit_fcmp (FloatCC.UnorderedOrGreaterThan) ty a b)
2909
+ (cmp_result_invert (rv_and (ordered ty a b) (rv_fle ty a b))))
2910
+
2911
+ ;; !(ordered a b) || a >= b
2912
+ ;; == !(ordered a b && a < b)
2913
+ (rule
2914
+ (emit_fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) ty a b)
2915
+ (cmp_result_invert (rv_and (ordered ty a b) (rv_flt ty a b))))