wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,3426 @@
1
+ //! This module defines s390x-specific machine instruction types.
2
+
3
+ use crate::binemit::{Addend, CodeOffset, Reloc};
4
+ use crate::ir::{types, ExternalName, Opcode, Type};
5
+ use crate::isa::s390x::abi::S390xMachineDeps;
6
+ use crate::isa::{CallConv, FunctionAlignment};
7
+ use crate::machinst::*;
8
+ use crate::{settings, CodegenError, CodegenResult};
9
+ use alloc::boxed::Box;
10
+ use alloc::vec::Vec;
11
+ use regalloc2::{PRegSet, VReg};
12
+ use smallvec::SmallVec;
13
+ use std::fmt::Write;
14
+ use std::string::{String, ToString};
15
+ pub mod regs;
16
+ pub use self::regs::*;
17
+ pub mod imms;
18
+ pub use self::imms::*;
19
+ pub mod args;
20
+ pub use self::args::*;
21
+ pub mod emit;
22
+ pub use self::emit::*;
23
+ pub mod unwind;
24
+
25
+ #[cfg(test)]
26
+ mod emit_tests;
27
+
28
+ //=============================================================================
29
+ // Instructions (top level): definition
30
+
31
+ pub use crate::isa::s390x::lower::isle::generated_code::{
32
+ ALUOp, CmpOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuRoundOp, LaneOrder, MInst as Inst,
33
+ RxSBGOp, ShiftOp, SymbolReloc, UnaryOp, VecBinaryOp, VecFloatCmpOp, VecIntCmpOp, VecShiftOp,
34
+ VecUnaryOp,
35
+ };
36
+
37
+ /// Additional information for (direct) Call instructions, left out of line to lower the size of
38
+ /// the Inst enum.
39
+ #[derive(Clone, Debug)]
40
+ pub struct CallInfo {
41
+ pub dest: ExternalName,
42
+ pub uses: CallArgList,
43
+ pub defs: CallRetList,
44
+ pub clobbers: PRegSet,
45
+ pub opcode: Opcode,
46
+ pub caller_callconv: CallConv,
47
+ pub callee_callconv: CallConv,
48
+ pub tls_symbol: Option<SymbolReloc>,
49
+ }
50
+
51
+ /// Additional information for CallInd instructions, left out of line to lower the size of the Inst
52
+ /// enum.
53
+ #[derive(Clone, Debug)]
54
+ pub struct CallIndInfo {
55
+ pub rn: Reg,
56
+ pub uses: CallArgList,
57
+ pub defs: CallRetList,
58
+ pub clobbers: PRegSet,
59
+ pub opcode: Opcode,
60
+ pub caller_callconv: CallConv,
61
+ pub callee_callconv: CallConv,
62
+ }
63
+
64
+ #[test]
65
+ fn inst_size_test() {
66
+ // This test will help with unintentionally growing the size
67
+ // of the Inst enum.
68
+ //
69
+ // TODO(#5879): see if we can make `VecRetPair` a box slice to get back to
70
+ // 32 here.
71
+ let expected_size = if cfg!(target_arch = "aarch64") || cfg!(target_arch = "riscv64") {
72
+ 48
73
+ } else {
74
+ 40
75
+ };
76
+ assert_eq!(expected_size, std::mem::size_of::<Inst>());
77
+ }
78
+
79
+ /// A register pair. Enum so it can be destructured in ISLE.
80
+ #[derive(Clone, Copy, Debug)]
81
+ pub struct RegPair {
82
+ pub hi: Reg,
83
+ pub lo: Reg,
84
+ }
85
+
86
+ /// A writable register pair. Enum so it can be destructured in ISLE.
87
+ #[derive(Clone, Copy, Debug)]
88
+ pub struct WritableRegPair {
89
+ pub hi: Writable<Reg>,
90
+ pub lo: Writable<Reg>,
91
+ }
92
+
93
+ impl WritableRegPair {
94
+ pub fn to_regpair(&self) -> RegPair {
95
+ RegPair {
96
+ hi: self.hi.to_reg(),
97
+ lo: self.lo.to_reg(),
98
+ }
99
+ }
100
+ }
101
+
102
+ /// Supported instruction sets
103
+ #[allow(non_camel_case_types)]
104
+ #[derive(Debug)]
105
+ pub(crate) enum InstructionSet {
106
+ /// Baseline ISA for cranelift is z14.
107
+ Base,
108
+ /// Miscellaneous-Instruction-Extensions Facility 2 (z15)
109
+ MIE2,
110
+ /// Vector-Enhancements Facility 2 (z15)
111
+ VXRS_EXT2,
112
+ }
113
+
114
+ impl Inst {
115
+ /// Retrieve the ISA feature set in which the instruction is available.
116
+ fn available_in_isa(&self) -> InstructionSet {
117
+ match self {
118
+ // These instructions are part of the baseline ISA for cranelift (z14)
119
+ Inst::Nop0
120
+ | Inst::Nop2
121
+ | Inst::AluRRSImm16 { .. }
122
+ | Inst::AluRR { .. }
123
+ | Inst::AluRX { .. }
124
+ | Inst::AluRSImm16 { .. }
125
+ | Inst::AluRSImm32 { .. }
126
+ | Inst::AluRUImm32 { .. }
127
+ | Inst::AluRUImm16Shifted { .. }
128
+ | Inst::AluRUImm32Shifted { .. }
129
+ | Inst::ShiftRR { .. }
130
+ | Inst::RxSBG { .. }
131
+ | Inst::RxSBGTest { .. }
132
+ | Inst::SMulWide { .. }
133
+ | Inst::UMulWide { .. }
134
+ | Inst::SDivMod32 { .. }
135
+ | Inst::SDivMod64 { .. }
136
+ | Inst::UDivMod32 { .. }
137
+ | Inst::UDivMod64 { .. }
138
+ | Inst::Flogr { .. }
139
+ | Inst::CmpRR { .. }
140
+ | Inst::CmpRX { .. }
141
+ | Inst::CmpRSImm16 { .. }
142
+ | Inst::CmpRSImm32 { .. }
143
+ | Inst::CmpRUImm32 { .. }
144
+ | Inst::CmpTrapRR { .. }
145
+ | Inst::CmpTrapRSImm16 { .. }
146
+ | Inst::CmpTrapRUImm16 { .. }
147
+ | Inst::AtomicRmw { .. }
148
+ | Inst::AtomicCas32 { .. }
149
+ | Inst::AtomicCas64 { .. }
150
+ | Inst::Fence
151
+ | Inst::Load32 { .. }
152
+ | Inst::Load32ZExt8 { .. }
153
+ | Inst::Load32SExt8 { .. }
154
+ | Inst::Load32ZExt16 { .. }
155
+ | Inst::Load32SExt16 { .. }
156
+ | Inst::Load64 { .. }
157
+ | Inst::Load64ZExt8 { .. }
158
+ | Inst::Load64SExt8 { .. }
159
+ | Inst::Load64ZExt16 { .. }
160
+ | Inst::Load64SExt16 { .. }
161
+ | Inst::Load64ZExt32 { .. }
162
+ | Inst::Load64SExt32 { .. }
163
+ | Inst::LoadRev16 { .. }
164
+ | Inst::LoadRev32 { .. }
165
+ | Inst::LoadRev64 { .. }
166
+ | Inst::Store8 { .. }
167
+ | Inst::Store16 { .. }
168
+ | Inst::Store32 { .. }
169
+ | Inst::Store64 { .. }
170
+ | Inst::StoreImm8 { .. }
171
+ | Inst::StoreImm16 { .. }
172
+ | Inst::StoreImm32SExt16 { .. }
173
+ | Inst::StoreImm64SExt16 { .. }
174
+ | Inst::StoreRev16 { .. }
175
+ | Inst::StoreRev32 { .. }
176
+ | Inst::StoreRev64 { .. }
177
+ | Inst::Mvc { .. }
178
+ | Inst::LoadMultiple64 { .. }
179
+ | Inst::StoreMultiple64 { .. }
180
+ | Inst::Mov32 { .. }
181
+ | Inst::Mov64 { .. }
182
+ | Inst::MovPReg { .. }
183
+ | Inst::Mov32Imm { .. }
184
+ | Inst::Mov32SImm16 { .. }
185
+ | Inst::Mov64SImm16 { .. }
186
+ | Inst::Mov64SImm32 { .. }
187
+ | Inst::Mov64UImm16Shifted { .. }
188
+ | Inst::Mov64UImm32Shifted { .. }
189
+ | Inst::Insert64UImm16Shifted { .. }
190
+ | Inst::Insert64UImm32Shifted { .. }
191
+ | Inst::LoadAR { .. }
192
+ | Inst::InsertAR { .. }
193
+ | Inst::Extend { .. }
194
+ | Inst::CMov32 { .. }
195
+ | Inst::CMov64 { .. }
196
+ | Inst::CMov32SImm16 { .. }
197
+ | Inst::CMov64SImm16 { .. }
198
+ | Inst::FpuMove32 { .. }
199
+ | Inst::FpuMove64 { .. }
200
+ | Inst::FpuCMov32 { .. }
201
+ | Inst::FpuCMov64 { .. }
202
+ | Inst::FpuRR { .. }
203
+ | Inst::FpuRRR { .. }
204
+ | Inst::FpuRRRR { .. }
205
+ | Inst::FpuCmp32 { .. }
206
+ | Inst::FpuCmp64 { .. }
207
+ | Inst::LoadFpuConst32 { .. }
208
+ | Inst::LoadFpuConst64 { .. }
209
+ | Inst::VecRRR { .. }
210
+ | Inst::VecRR { .. }
211
+ | Inst::VecShiftRR { .. }
212
+ | Inst::VecSelect { .. }
213
+ | Inst::VecPermute { .. }
214
+ | Inst::VecPermuteDWImm { .. }
215
+ | Inst::VecIntCmp { .. }
216
+ | Inst::VecIntCmpS { .. }
217
+ | Inst::VecFloatCmp { .. }
218
+ | Inst::VecFloatCmpS { .. }
219
+ | Inst::VecInt128SCmpHi { .. }
220
+ | Inst::VecInt128UCmpHi { .. }
221
+ | Inst::VecLoad { .. }
222
+ | Inst::VecStore { .. }
223
+ | Inst::VecLoadReplicate { .. }
224
+ | Inst::VecMov { .. }
225
+ | Inst::VecCMov { .. }
226
+ | Inst::MovToVec128 { .. }
227
+ | Inst::VecLoadConst { .. }
228
+ | Inst::VecLoadConstReplicate { .. }
229
+ | Inst::VecImmByteMask { .. }
230
+ | Inst::VecImmBitMask { .. }
231
+ | Inst::VecImmReplicate { .. }
232
+ | Inst::VecLoadLane { .. }
233
+ | Inst::VecLoadLaneUndef { .. }
234
+ | Inst::VecStoreLane { .. }
235
+ | Inst::VecInsertLane { .. }
236
+ | Inst::VecInsertLaneUndef { .. }
237
+ | Inst::VecExtractLane { .. }
238
+ | Inst::VecInsertLaneImm { .. }
239
+ | Inst::VecReplicateLane { .. }
240
+ | Inst::Call { .. }
241
+ | Inst::CallInd { .. }
242
+ | Inst::Args { .. }
243
+ | Inst::Ret { .. }
244
+ | Inst::Jump { .. }
245
+ | Inst::CondBr { .. }
246
+ | Inst::TrapIf { .. }
247
+ | Inst::OneWayCondBr { .. }
248
+ | Inst::IndirectBr { .. }
249
+ | Inst::Debugtrap
250
+ | Inst::Trap { .. }
251
+ | Inst::JTSequence { .. }
252
+ | Inst::LoadSymbolReloc { .. }
253
+ | Inst::LoadAddr { .. }
254
+ | Inst::Loop { .. }
255
+ | Inst::CondBreak { .. }
256
+ | Inst::VirtualSPOffsetAdj { .. }
257
+ | Inst::Unwind { .. } => InstructionSet::Base,
258
+
259
+ // These depend on the opcode
260
+ Inst::AluRRR { alu_op, .. } => match alu_op {
261
+ ALUOp::NotAnd32 | ALUOp::NotAnd64 => InstructionSet::MIE2,
262
+ ALUOp::NotOrr32 | ALUOp::NotOrr64 => InstructionSet::MIE2,
263
+ ALUOp::NotXor32 | ALUOp::NotXor64 => InstructionSet::MIE2,
264
+ ALUOp::AndNot32 | ALUOp::AndNot64 => InstructionSet::MIE2,
265
+ ALUOp::OrrNot32 | ALUOp::OrrNot64 => InstructionSet::MIE2,
266
+ _ => InstructionSet::Base,
267
+ },
268
+ Inst::UnaryRR { op, .. } => match op {
269
+ UnaryOp::PopcntReg => InstructionSet::MIE2,
270
+ _ => InstructionSet::Base,
271
+ },
272
+ Inst::FpuRound { op, .. } => match op {
273
+ FpuRoundOp::ToSInt32 | FpuRoundOp::FromSInt32 => InstructionSet::VXRS_EXT2,
274
+ FpuRoundOp::ToUInt32 | FpuRoundOp::FromUInt32 => InstructionSet::VXRS_EXT2,
275
+ FpuRoundOp::ToSInt32x4 | FpuRoundOp::FromSInt32x4 => InstructionSet::VXRS_EXT2,
276
+ FpuRoundOp::ToUInt32x4 | FpuRoundOp::FromUInt32x4 => InstructionSet::VXRS_EXT2,
277
+ _ => InstructionSet::Base,
278
+ },
279
+
280
+ // These are all part of VXRS_EXT2
281
+ Inst::VecLoadRev { .. }
282
+ | Inst::VecLoadByte16Rev { .. }
283
+ | Inst::VecLoadByte32Rev { .. }
284
+ | Inst::VecLoadByte64Rev { .. }
285
+ | Inst::VecLoadElt16Rev { .. }
286
+ | Inst::VecLoadElt32Rev { .. }
287
+ | Inst::VecLoadElt64Rev { .. }
288
+ | Inst::VecStoreRev { .. }
289
+ | Inst::VecStoreByte16Rev { .. }
290
+ | Inst::VecStoreByte32Rev { .. }
291
+ | Inst::VecStoreByte64Rev { .. }
292
+ | Inst::VecStoreElt16Rev { .. }
293
+ | Inst::VecStoreElt32Rev { .. }
294
+ | Inst::VecStoreElt64Rev { .. }
295
+ | Inst::VecLoadReplicateRev { .. }
296
+ | Inst::VecLoadLaneRev { .. }
297
+ | Inst::VecLoadLaneRevUndef { .. }
298
+ | Inst::VecStoreLaneRev { .. } => InstructionSet::VXRS_EXT2,
299
+
300
+ Inst::DummyUse { .. } => InstructionSet::Base,
301
+ }
302
+ }
303
+
304
+ /// Create a 128-bit move instruction.
305
+ pub fn mov128(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
306
+ assert!(to_reg.to_reg().class() == RegClass::Float);
307
+ assert!(from_reg.class() == RegClass::Float);
308
+ Inst::VecMov {
309
+ rd: to_reg,
310
+ rn: from_reg,
311
+ }
312
+ }
313
+
314
+ /// Create a 64-bit move instruction.
315
+ pub fn mov64(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
316
+ assert!(to_reg.to_reg().class() == from_reg.class());
317
+ if from_reg.class() == RegClass::Int {
318
+ Inst::Mov64 {
319
+ rd: to_reg,
320
+ rm: from_reg,
321
+ }
322
+ } else {
323
+ Inst::FpuMove64 {
324
+ rd: to_reg,
325
+ rn: from_reg,
326
+ }
327
+ }
328
+ }
329
+
330
+ /// Create a 32-bit move instruction.
331
+ pub fn mov32(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
332
+ if from_reg.class() == RegClass::Int {
333
+ Inst::Mov32 {
334
+ rd: to_reg,
335
+ rm: from_reg,
336
+ }
337
+ } else {
338
+ Inst::FpuMove32 {
339
+ rd: to_reg,
340
+ rn: from_reg,
341
+ }
342
+ }
343
+ }
344
+
345
+ /// Generic constructor for a load (zero-extending where appropriate).
346
+ pub fn gen_load(into_reg: Writable<Reg>, mem: MemArg, ty: Type) -> Inst {
347
+ match ty {
348
+ types::I8 => Inst::Load64ZExt8 { rd: into_reg, mem },
349
+ types::I16 => Inst::Load64ZExt16 { rd: into_reg, mem },
350
+ types::I32 => Inst::Load64ZExt32 { rd: into_reg, mem },
351
+ types::I64 | types::R64 => Inst::Load64 { rd: into_reg, mem },
352
+ types::F32 => Inst::VecLoadLaneUndef {
353
+ size: 32,
354
+ rd: into_reg,
355
+ mem,
356
+ lane_imm: 0,
357
+ },
358
+ types::F64 => Inst::VecLoadLaneUndef {
359
+ size: 64,
360
+ rd: into_reg,
361
+ mem,
362
+ lane_imm: 0,
363
+ },
364
+ _ if ty.is_vector() && ty.bits() == 128 => Inst::VecLoad { rd: into_reg, mem },
365
+ types::I128 => Inst::VecLoad { rd: into_reg, mem },
366
+ _ => unimplemented!("gen_load({})", ty),
367
+ }
368
+ }
369
+
370
+ /// Generic constructor for a store.
371
+ pub fn gen_store(mem: MemArg, from_reg: Reg, ty: Type) -> Inst {
372
+ match ty {
373
+ types::I8 => Inst::Store8 { rd: from_reg, mem },
374
+ types::I16 => Inst::Store16 { rd: from_reg, mem },
375
+ types::I32 => Inst::Store32 { rd: from_reg, mem },
376
+ types::I64 | types::R64 => Inst::Store64 { rd: from_reg, mem },
377
+ types::F32 => Inst::VecStoreLane {
378
+ size: 32,
379
+ rd: from_reg,
380
+ mem,
381
+ lane_imm: 0,
382
+ },
383
+ types::F64 => Inst::VecStoreLane {
384
+ size: 64,
385
+ rd: from_reg,
386
+ mem,
387
+ lane_imm: 0,
388
+ },
389
+ _ if ty.is_vector() && ty.bits() == 128 => Inst::VecStore { rd: from_reg, mem },
390
+ types::I128 => Inst::VecStore { rd: from_reg, mem },
391
+ _ => unimplemented!("gen_store({})", ty),
392
+ }
393
+ }
394
+ }
395
+
396
+ //=============================================================================
397
+ // Instructions: get_regs
398
+
399
+ fn memarg_operands<F: Fn(VReg) -> VReg>(memarg: &MemArg, collector: &mut OperandCollector<'_, F>) {
400
+ match memarg {
401
+ &MemArg::BXD12 { base, index, .. } | &MemArg::BXD20 { base, index, .. } => {
402
+ collector.reg_use(base);
403
+ collector.reg_use(index);
404
+ }
405
+ &MemArg::Label { .. } | &MemArg::Symbol { .. } => {}
406
+ &MemArg::RegOffset { reg, .. } => {
407
+ collector.reg_use(reg);
408
+ }
409
+ &MemArg::InitialSPOffset { .. } | &MemArg::NominalSPOffset { .. } => {}
410
+ }
411
+ // mem_finalize might require %r1 to hold (part of) the address.
412
+ // Conservatively assume this will always be necessary here.
413
+ collector.reg_early_def(writable_gpr(1));
414
+ }
415
+
416
+ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCollector<'_, F>) {
417
+ match inst {
418
+ &Inst::AluRRR { rd, rn, rm, .. } => {
419
+ collector.reg_def(rd);
420
+ collector.reg_use(rn);
421
+ collector.reg_use(rm);
422
+ }
423
+ &Inst::AluRRSImm16 { rd, rn, .. } => {
424
+ collector.reg_def(rd);
425
+ collector.reg_use(rn);
426
+ }
427
+ &Inst::AluRR { rd, ri, rm, .. } => {
428
+ collector.reg_reuse_def(rd, 1);
429
+ collector.reg_use(ri);
430
+ collector.reg_use(rm);
431
+ }
432
+ &Inst::AluRX {
433
+ rd, ri, ref mem, ..
434
+ } => {
435
+ collector.reg_reuse_def(rd, 1);
436
+ collector.reg_use(ri);
437
+ memarg_operands(mem, collector);
438
+ }
439
+ &Inst::AluRSImm16 { rd, ri, .. } => {
440
+ collector.reg_reuse_def(rd, 1);
441
+ collector.reg_use(ri);
442
+ }
443
+ &Inst::AluRSImm32 { rd, ri, .. } => {
444
+ collector.reg_reuse_def(rd, 1);
445
+ collector.reg_use(ri);
446
+ }
447
+ &Inst::AluRUImm32 { rd, ri, .. } => {
448
+ collector.reg_reuse_def(rd, 1);
449
+ collector.reg_use(ri);
450
+ }
451
+ &Inst::AluRUImm16Shifted { rd, ri, .. } => {
452
+ collector.reg_reuse_def(rd, 1);
453
+ collector.reg_use(ri);
454
+ }
455
+ &Inst::AluRUImm32Shifted { rd, ri, .. } => {
456
+ collector.reg_reuse_def(rd, 1);
457
+ collector.reg_use(ri);
458
+ }
459
+ &Inst::SMulWide { rd, rn, rm } => {
460
+ collector.reg_use(rn);
461
+ collector.reg_use(rm);
462
+ // FIXME: The pair is hard-coded as %r2/%r3 because regalloc cannot handle pairs. If
463
+ // that changes, all the hard-coded uses of %r2/%r3 can be changed.
464
+ collector.reg_fixed_def(rd.hi, gpr(2));
465
+ collector.reg_fixed_def(rd.lo, gpr(3));
466
+ }
467
+ &Inst::UMulWide { rd, ri, rn } => {
468
+ collector.reg_use(rn);
469
+ collector.reg_fixed_def(rd.hi, gpr(2));
470
+ collector.reg_fixed_def(rd.lo, gpr(3));
471
+ collector.reg_fixed_use(ri, gpr(3));
472
+ }
473
+ &Inst::SDivMod32 { rd, ri, rn } | &Inst::SDivMod64 { rd, ri, rn } => {
474
+ collector.reg_use(rn);
475
+ collector.reg_fixed_def(rd.hi, gpr(2));
476
+ collector.reg_fixed_def(rd.lo, gpr(3));
477
+ collector.reg_fixed_use(ri, gpr(3));
478
+ }
479
+ &Inst::UDivMod32 { rd, ri, rn } | &Inst::UDivMod64 { rd, ri, rn } => {
480
+ collector.reg_use(rn);
481
+ collector.reg_fixed_def(rd.hi, gpr(2));
482
+ collector.reg_fixed_def(rd.lo, gpr(3));
483
+ collector.reg_fixed_use(ri.hi, gpr(2));
484
+ collector.reg_fixed_use(ri.lo, gpr(3));
485
+ }
486
+ &Inst::Flogr { rd, rn } => {
487
+ collector.reg_use(rn);
488
+ collector.reg_fixed_def(rd.hi, gpr(2));
489
+ collector.reg_fixed_def(rd.lo, gpr(3));
490
+ }
491
+ &Inst::ShiftRR {
492
+ rd, rn, shift_reg, ..
493
+ } => {
494
+ collector.reg_def(rd);
495
+ collector.reg_use(rn);
496
+ if shift_reg != zero_reg() {
497
+ collector.reg_use(shift_reg);
498
+ }
499
+ }
500
+ &Inst::RxSBG { rd, ri, rn, .. } => {
501
+ collector.reg_reuse_def(rd, 1);
502
+ collector.reg_use(ri);
503
+ collector.reg_use(rn);
504
+ }
505
+ &Inst::RxSBGTest { rd, rn, .. } => {
506
+ collector.reg_use(rd);
507
+ collector.reg_use(rn);
508
+ }
509
+ &Inst::UnaryRR { rd, rn, .. } => {
510
+ collector.reg_def(rd);
511
+ collector.reg_use(rn);
512
+ }
513
+ &Inst::CmpRR { rn, rm, .. } => {
514
+ collector.reg_use(rn);
515
+ collector.reg_use(rm);
516
+ }
517
+ &Inst::CmpRX { rn, ref mem, .. } => {
518
+ collector.reg_use(rn);
519
+ memarg_operands(mem, collector);
520
+ }
521
+ &Inst::CmpRSImm16 { rn, .. } => {
522
+ collector.reg_use(rn);
523
+ }
524
+ &Inst::CmpRSImm32 { rn, .. } => {
525
+ collector.reg_use(rn);
526
+ }
527
+ &Inst::CmpRUImm32 { rn, .. } => {
528
+ collector.reg_use(rn);
529
+ }
530
+ &Inst::CmpTrapRR { rn, rm, .. } => {
531
+ collector.reg_use(rn);
532
+ collector.reg_use(rm);
533
+ }
534
+ &Inst::CmpTrapRSImm16 { rn, .. } => {
535
+ collector.reg_use(rn);
536
+ }
537
+ &Inst::CmpTrapRUImm16 { rn, .. } => {
538
+ collector.reg_use(rn);
539
+ }
540
+ &Inst::AtomicRmw {
541
+ rd, rn, ref mem, ..
542
+ } => {
543
+ collector.reg_def(rd);
544
+ collector.reg_use(rn);
545
+ memarg_operands(mem, collector);
546
+ }
547
+ &Inst::AtomicCas32 {
548
+ rd,
549
+ ri,
550
+ rn,
551
+ ref mem,
552
+ ..
553
+ }
554
+ | &Inst::AtomicCas64 {
555
+ rd,
556
+ ri,
557
+ rn,
558
+ ref mem,
559
+ ..
560
+ } => {
561
+ collector.reg_reuse_def(rd, 1);
562
+ collector.reg_use(ri);
563
+ collector.reg_use(rn);
564
+ memarg_operands(mem, collector);
565
+ }
566
+ &Inst::Fence => {}
567
+ &Inst::Load32 { rd, ref mem, .. }
568
+ | &Inst::Load32ZExt8 { rd, ref mem, .. }
569
+ | &Inst::Load32SExt8 { rd, ref mem, .. }
570
+ | &Inst::Load32ZExt16 { rd, ref mem, .. }
571
+ | &Inst::Load32SExt16 { rd, ref mem, .. }
572
+ | &Inst::Load64 { rd, ref mem, .. }
573
+ | &Inst::Load64ZExt8 { rd, ref mem, .. }
574
+ | &Inst::Load64SExt8 { rd, ref mem, .. }
575
+ | &Inst::Load64ZExt16 { rd, ref mem, .. }
576
+ | &Inst::Load64SExt16 { rd, ref mem, .. }
577
+ | &Inst::Load64ZExt32 { rd, ref mem, .. }
578
+ | &Inst::Load64SExt32 { rd, ref mem, .. }
579
+ | &Inst::LoadRev16 { rd, ref mem, .. }
580
+ | &Inst::LoadRev32 { rd, ref mem, .. }
581
+ | &Inst::LoadRev64 { rd, ref mem, .. } => {
582
+ collector.reg_def(rd);
583
+ memarg_operands(mem, collector);
584
+ }
585
+ &Inst::Store8 { rd, ref mem, .. }
586
+ | &Inst::Store16 { rd, ref mem, .. }
587
+ | &Inst::Store32 { rd, ref mem, .. }
588
+ | &Inst::Store64 { rd, ref mem, .. }
589
+ | &Inst::StoreRev16 { rd, ref mem, .. }
590
+ | &Inst::StoreRev32 { rd, ref mem, .. }
591
+ | &Inst::StoreRev64 { rd, ref mem, .. } => {
592
+ collector.reg_use(rd);
593
+ memarg_operands(mem, collector);
594
+ }
595
+ &Inst::StoreImm8 { ref mem, .. }
596
+ | &Inst::StoreImm16 { ref mem, .. }
597
+ | &Inst::StoreImm32SExt16 { ref mem, .. }
598
+ | &Inst::StoreImm64SExt16 { ref mem, .. } => {
599
+ memarg_operands(mem, collector);
600
+ }
601
+ &Inst::Mvc {
602
+ ref dst, ref src, ..
603
+ } => {
604
+ collector.reg_use(dst.base);
605
+ collector.reg_use(src.base);
606
+ }
607
+ &Inst::LoadMultiple64 {
608
+ rt, rt2, ref mem, ..
609
+ } => {
610
+ memarg_operands(mem, collector);
611
+ let first_regnum = rt.to_reg().to_real_reg().unwrap().hw_enc();
612
+ let last_regnum = rt2.to_reg().to_real_reg().unwrap().hw_enc();
613
+ for regnum in first_regnum..last_regnum + 1 {
614
+ collector.reg_def(writable_gpr(regnum));
615
+ }
616
+ }
617
+ &Inst::StoreMultiple64 {
618
+ rt, rt2, ref mem, ..
619
+ } => {
620
+ memarg_operands(mem, collector);
621
+ let first_regnum = rt.to_real_reg().unwrap().hw_enc();
622
+ let last_regnum = rt2.to_real_reg().unwrap().hw_enc();
623
+ for regnum in first_regnum..last_regnum + 1 {
624
+ collector.reg_use(gpr(regnum));
625
+ }
626
+ }
627
+ &Inst::Mov64 { rd, rm } => {
628
+ collector.reg_def(rd);
629
+ collector.reg_use(rm);
630
+ }
631
+ &Inst::MovPReg { rd, rm } => {
632
+ debug_assert!([regs::gpr(0), regs::gpr(14), regs::gpr(15)].contains(&rm.into()));
633
+ debug_assert!(rd.to_reg().is_virtual());
634
+ collector.reg_def(rd);
635
+ }
636
+ &Inst::Mov32 { rd, rm } => {
637
+ collector.reg_def(rd);
638
+ collector.reg_use(rm);
639
+ }
640
+ &Inst::Mov32Imm { rd, .. }
641
+ | &Inst::Mov32SImm16 { rd, .. }
642
+ | &Inst::Mov64SImm16 { rd, .. }
643
+ | &Inst::Mov64SImm32 { rd, .. }
644
+ | &Inst::Mov64UImm16Shifted { rd, .. }
645
+ | &Inst::Mov64UImm32Shifted { rd, .. } => {
646
+ collector.reg_def(rd);
647
+ }
648
+ &Inst::CMov32 { rd, ri, rm, .. } | &Inst::CMov64 { rd, ri, rm, .. } => {
649
+ collector.reg_reuse_def(rd, 1);
650
+ collector.reg_use(ri);
651
+ collector.reg_use(rm);
652
+ }
653
+ &Inst::CMov32SImm16 { rd, ri, .. } | &Inst::CMov64SImm16 { rd, ri, .. } => {
654
+ collector.reg_reuse_def(rd, 1);
655
+ collector.reg_use(ri);
656
+ }
657
+ &Inst::Insert64UImm16Shifted { rd, ri, .. }
658
+ | &Inst::Insert64UImm32Shifted { rd, ri, .. } => {
659
+ collector.reg_reuse_def(rd, 1);
660
+ collector.reg_use(ri);
661
+ }
662
+ &Inst::LoadAR { rd, .. } => {
663
+ collector.reg_def(rd);
664
+ }
665
+ &Inst::InsertAR { rd, ri, .. } => {
666
+ collector.reg_reuse_def(rd, 1);
667
+ collector.reg_use(ri);
668
+ }
669
+ &Inst::FpuMove32 { rd, rn } | &Inst::FpuMove64 { rd, rn } => {
670
+ collector.reg_def(rd);
671
+ collector.reg_use(rn);
672
+ }
673
+ &Inst::FpuCMov32 { rd, ri, rm, .. } | &Inst::FpuCMov64 { rd, ri, rm, .. } => {
674
+ collector.reg_reuse_def(rd, 1);
675
+ collector.reg_use(ri);
676
+ collector.reg_use(rm);
677
+ }
678
+ &Inst::FpuRR { rd, rn, .. } => {
679
+ collector.reg_def(rd);
680
+ collector.reg_use(rn);
681
+ }
682
+ &Inst::FpuRRR { rd, rn, rm, .. } => {
683
+ collector.reg_def(rd);
684
+ collector.reg_use(rn);
685
+ collector.reg_use(rm);
686
+ }
687
+ &Inst::FpuRRRR { rd, rn, rm, ra, .. } => {
688
+ collector.reg_def(rd);
689
+ collector.reg_use(rn);
690
+ collector.reg_use(rm);
691
+ collector.reg_use(ra);
692
+ }
693
+ &Inst::FpuCmp32 { rn, rm } | &Inst::FpuCmp64 { rn, rm } => {
694
+ collector.reg_use(rn);
695
+ collector.reg_use(rm);
696
+ }
697
+ &Inst::LoadFpuConst32 { rd, .. } | &Inst::LoadFpuConst64 { rd, .. } => {
698
+ collector.reg_def(rd);
699
+ collector.reg_def(writable_gpr(1));
700
+ }
701
+ &Inst::FpuRound { rd, rn, .. } => {
702
+ collector.reg_def(rd);
703
+ collector.reg_use(rn);
704
+ }
705
+ &Inst::VecRRR { rd, rn, rm, .. } => {
706
+ collector.reg_def(rd);
707
+ collector.reg_use(rn);
708
+ collector.reg_use(rm);
709
+ }
710
+ &Inst::VecRR { rd, rn, .. } => {
711
+ collector.reg_def(rd);
712
+ collector.reg_use(rn);
713
+ }
714
+ &Inst::VecShiftRR {
715
+ rd, rn, shift_reg, ..
716
+ } => {
717
+ collector.reg_def(rd);
718
+ collector.reg_use(rn);
719
+ if shift_reg != zero_reg() {
720
+ collector.reg_use(shift_reg);
721
+ }
722
+ }
723
+ &Inst::VecSelect { rd, rn, rm, ra, .. } => {
724
+ collector.reg_def(rd);
725
+ collector.reg_use(rn);
726
+ collector.reg_use(rm);
727
+ collector.reg_use(ra);
728
+ }
729
+ &Inst::VecPermute { rd, rn, rm, ra, .. } => {
730
+ collector.reg_def(rd);
731
+ collector.reg_use(rn);
732
+ collector.reg_use(rm);
733
+ collector.reg_use(ra);
734
+ }
735
+ &Inst::VecPermuteDWImm { rd, rn, rm, .. } => {
736
+ collector.reg_def(rd);
737
+ collector.reg_use(rn);
738
+ collector.reg_use(rm);
739
+ }
740
+ &Inst::VecIntCmp { rd, rn, rm, .. } | &Inst::VecIntCmpS { rd, rn, rm, .. } => {
741
+ collector.reg_def(rd);
742
+ collector.reg_use(rn);
743
+ collector.reg_use(rm);
744
+ }
745
+ &Inst::VecFloatCmp { rd, rn, rm, .. } | &Inst::VecFloatCmpS { rd, rn, rm, .. } => {
746
+ collector.reg_def(rd);
747
+ collector.reg_use(rn);
748
+ collector.reg_use(rm);
749
+ }
750
+ &Inst::VecInt128SCmpHi { tmp, rn, rm, .. } | &Inst::VecInt128UCmpHi { tmp, rn, rm, .. } => {
751
+ collector.reg_def(tmp);
752
+ collector.reg_use(rn);
753
+ collector.reg_use(rm);
754
+ }
755
+ &Inst::VecLoad { rd, ref mem, .. } => {
756
+ collector.reg_def(rd);
757
+ memarg_operands(mem, collector);
758
+ }
759
+ &Inst::VecLoadRev { rd, ref mem, .. } => {
760
+ collector.reg_def(rd);
761
+ memarg_operands(mem, collector);
762
+ }
763
+ &Inst::VecLoadByte16Rev { rd, ref mem, .. } => {
764
+ collector.reg_def(rd);
765
+ memarg_operands(mem, collector);
766
+ }
767
+ &Inst::VecLoadByte32Rev { rd, ref mem, .. } => {
768
+ collector.reg_def(rd);
769
+ memarg_operands(mem, collector);
770
+ }
771
+ &Inst::VecLoadByte64Rev { rd, ref mem, .. } => {
772
+ collector.reg_def(rd);
773
+ memarg_operands(mem, collector);
774
+ }
775
+ &Inst::VecLoadElt16Rev { rd, ref mem, .. } => {
776
+ collector.reg_def(rd);
777
+ memarg_operands(mem, collector);
778
+ }
779
+ &Inst::VecLoadElt32Rev { rd, ref mem, .. } => {
780
+ collector.reg_def(rd);
781
+ memarg_operands(mem, collector);
782
+ }
783
+ &Inst::VecLoadElt64Rev { rd, ref mem, .. } => {
784
+ collector.reg_def(rd);
785
+ memarg_operands(mem, collector);
786
+ }
787
+ &Inst::VecStore { rd, ref mem, .. } => {
788
+ collector.reg_use(rd);
789
+ memarg_operands(mem, collector);
790
+ }
791
+ &Inst::VecStoreRev { rd, ref mem, .. } => {
792
+ collector.reg_use(rd);
793
+ memarg_operands(mem, collector);
794
+ }
795
+ &Inst::VecStoreByte16Rev { rd, ref mem, .. } => {
796
+ collector.reg_use(rd);
797
+ memarg_operands(mem, collector);
798
+ }
799
+ &Inst::VecStoreByte32Rev { rd, ref mem, .. } => {
800
+ collector.reg_use(rd);
801
+ memarg_operands(mem, collector);
802
+ }
803
+ &Inst::VecStoreByte64Rev { rd, ref mem, .. } => {
804
+ collector.reg_use(rd);
805
+ memarg_operands(mem, collector);
806
+ }
807
+ &Inst::VecStoreElt16Rev { rd, ref mem, .. } => {
808
+ collector.reg_use(rd);
809
+ memarg_operands(mem, collector);
810
+ }
811
+ &Inst::VecStoreElt32Rev { rd, ref mem, .. } => {
812
+ collector.reg_use(rd);
813
+ memarg_operands(mem, collector);
814
+ }
815
+ &Inst::VecStoreElt64Rev { rd, ref mem, .. } => {
816
+ collector.reg_use(rd);
817
+ memarg_operands(mem, collector);
818
+ }
819
+ &Inst::VecLoadReplicate { rd, ref mem, .. } => {
820
+ collector.reg_def(rd);
821
+ memarg_operands(mem, collector);
822
+ }
823
+ &Inst::VecLoadReplicateRev { rd, ref mem, .. } => {
824
+ collector.reg_def(rd);
825
+ memarg_operands(mem, collector);
826
+ }
827
+ &Inst::VecMov { rd, rn } => {
828
+ collector.reg_def(rd);
829
+ collector.reg_use(rn);
830
+ }
831
+ &Inst::VecCMov { rd, ri, rm, .. } => {
832
+ collector.reg_reuse_def(rd, 1);
833
+ collector.reg_use(ri);
834
+ collector.reg_use(rm);
835
+ }
836
+ &Inst::MovToVec128 { rd, rn, rm } => {
837
+ collector.reg_def(rd);
838
+ collector.reg_use(rn);
839
+ collector.reg_use(rm);
840
+ }
841
+ &Inst::VecLoadConst { rd, .. } | &Inst::VecLoadConstReplicate { rd, .. } => {
842
+ collector.reg_def(rd);
843
+ collector.reg_def(writable_gpr(1));
844
+ }
845
+ &Inst::VecImmByteMask { rd, .. } => {
846
+ collector.reg_def(rd);
847
+ }
848
+ &Inst::VecImmBitMask { rd, .. } => {
849
+ collector.reg_def(rd);
850
+ }
851
+ &Inst::VecImmReplicate { rd, .. } => {
852
+ collector.reg_def(rd);
853
+ }
854
+ &Inst::VecLoadLane {
855
+ rd, ri, ref mem, ..
856
+ } => {
857
+ collector.reg_reuse_def(rd, 1);
858
+ collector.reg_use(ri);
859
+ memarg_operands(mem, collector);
860
+ }
861
+ &Inst::VecLoadLaneUndef { rd, ref mem, .. } => {
862
+ collector.reg_def(rd);
863
+ memarg_operands(mem, collector);
864
+ }
865
+ &Inst::VecStoreLaneRev { rd, ref mem, .. } => {
866
+ collector.reg_use(rd);
867
+ memarg_operands(mem, collector);
868
+ }
869
+ &Inst::VecLoadLaneRevUndef { rd, ref mem, .. } => {
870
+ collector.reg_def(rd);
871
+ memarg_operands(mem, collector);
872
+ }
873
+ &Inst::VecStoreLane { rd, ref mem, .. } => {
874
+ collector.reg_use(rd);
875
+ memarg_operands(mem, collector);
876
+ }
877
+ &Inst::VecLoadLaneRev {
878
+ rd, ri, ref mem, ..
879
+ } => {
880
+ collector.reg_reuse_def(rd, 1);
881
+ collector.reg_use(ri);
882
+ memarg_operands(mem, collector);
883
+ }
884
+ &Inst::VecInsertLane {
885
+ rd,
886
+ ri,
887
+ rn,
888
+ lane_reg,
889
+ ..
890
+ } => {
891
+ collector.reg_reuse_def(rd, 1);
892
+ collector.reg_use(ri);
893
+ collector.reg_use(rn);
894
+ if lane_reg != zero_reg() {
895
+ collector.reg_use(lane_reg);
896
+ }
897
+ }
898
+ &Inst::VecInsertLaneUndef {
899
+ rd, rn, lane_reg, ..
900
+ } => {
901
+ collector.reg_def(rd);
902
+ collector.reg_use(rn);
903
+ if lane_reg != zero_reg() {
904
+ collector.reg_use(lane_reg);
905
+ }
906
+ }
907
+ &Inst::VecExtractLane {
908
+ rd, rn, lane_reg, ..
909
+ } => {
910
+ collector.reg_def(rd);
911
+ collector.reg_use(rn);
912
+ if lane_reg != zero_reg() {
913
+ collector.reg_use(lane_reg);
914
+ }
915
+ }
916
+ &Inst::VecInsertLaneImm { rd, ri, .. } => {
917
+ collector.reg_reuse_def(rd, 1);
918
+ collector.reg_use(ri);
919
+ }
920
+ &Inst::VecReplicateLane { rd, rn, .. } => {
921
+ collector.reg_def(rd);
922
+ collector.reg_use(rn);
923
+ }
924
+ &Inst::Extend { rd, rn, .. } => {
925
+ collector.reg_def(rd);
926
+ collector.reg_use(rn);
927
+ }
928
+ &Inst::Call { link, ref info } => {
929
+ for u in &info.uses {
930
+ collector.reg_fixed_use(u.vreg, u.preg);
931
+ }
932
+ for d in &info.defs {
933
+ collector.reg_fixed_def(d.vreg, d.preg);
934
+ }
935
+ let mut clobbers = info.clobbers.clone();
936
+ clobbers.add(link.to_reg().to_real_reg().unwrap().into());
937
+ collector.reg_clobbers(clobbers);
938
+ }
939
+ &Inst::CallInd { link, ref info } => {
940
+ collector.reg_use(info.rn);
941
+ for u in &info.uses {
942
+ collector.reg_fixed_use(u.vreg, u.preg);
943
+ }
944
+ for d in &info.defs {
945
+ collector.reg_fixed_def(d.vreg, d.preg);
946
+ }
947
+ let mut clobbers = info.clobbers.clone();
948
+ clobbers.add(link.to_reg().to_real_reg().unwrap().into());
949
+ collector.reg_clobbers(clobbers);
950
+ }
951
+ &Inst::Args { ref args } => {
952
+ for arg in args {
953
+ collector.reg_fixed_def(arg.vreg, arg.preg);
954
+ }
955
+ }
956
+ &Inst::Ret { ref rets, .. } => {
957
+ // NOTE: we explicitly don't mark the link register as used here, as the use is only in
958
+ // the epilog where callee-save registers are restored.
959
+ for ret in rets {
960
+ collector.reg_fixed_use(ret.vreg, ret.preg);
961
+ }
962
+ }
963
+ &Inst::Jump { .. } => {}
964
+ &Inst::IndirectBr { rn, .. } => {
965
+ collector.reg_use(rn);
966
+ }
967
+ &Inst::CondBr { .. } | &Inst::OneWayCondBr { .. } => {}
968
+ &Inst::Nop0 | Inst::Nop2 => {}
969
+ &Inst::Debugtrap => {}
970
+ &Inst::Trap { .. } => {}
971
+ &Inst::TrapIf { .. } => {}
972
+ &Inst::JTSequence { ridx, .. } => {
973
+ collector.reg_use(ridx);
974
+ collector.reg_early_def(writable_gpr(1));
975
+ }
976
+ &Inst::LoadSymbolReloc { rd, .. } => {
977
+ collector.reg_def(rd);
978
+ collector.reg_def(writable_gpr(1));
979
+ }
980
+ &Inst::LoadAddr { rd, ref mem } => {
981
+ collector.reg_def(rd);
982
+ memarg_operands(mem, collector);
983
+ }
984
+ &Inst::Loop { ref body, .. } => {
985
+ for inst in body.iter() {
986
+ s390x_get_operands(inst, collector);
987
+ }
988
+
989
+ // `reuse_def` constraints can't be permitted in a Loop instruction because the operand
990
+ // index will always be relative to the Loop instruction, not the individual
991
+ // instruction in the loop body. However, fixed-nonallocatable registers used with
992
+ // instructions that would have emitted `reuse_def` constraints are fine.
993
+ debug_assert!(collector.no_reuse_def());
994
+ }
995
+ &Inst::CondBreak { .. } => {}
996
+ &Inst::VirtualSPOffsetAdj { .. } => {}
997
+ &Inst::Unwind { .. } => {}
998
+ &Inst::DummyUse { reg } => {
999
+ collector.reg_use(reg);
1000
+ }
1001
+ }
1002
+ }
1003
+
1004
+ //=============================================================================
1005
+ // Instructions: misc functions and external interface
1006
+
1007
+ impl MachInst for Inst {
1008
+ type ABIMachineSpec = S390xMachineDeps;
1009
+ type LabelUse = LabelUse;
1010
+ const TRAP_OPCODE: &'static [u8] = &[0, 0];
1011
+
1012
+ fn get_operands<F: Fn(VReg) -> VReg>(&self, collector: &mut OperandCollector<'_, F>) {
1013
+ s390x_get_operands(self, collector);
1014
+ }
1015
+
1016
+ fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
1017
+ match self {
1018
+ &Inst::Mov32 { rd, rm } => Some((rd, rm)),
1019
+ &Inst::Mov64 { rd, rm } => Some((rd, rm)),
1020
+ &Inst::FpuMove32 { rd, rn } => Some((rd, rn)),
1021
+ &Inst::FpuMove64 { rd, rn } => Some((rd, rn)),
1022
+ &Inst::VecMov { rd, rn } => Some((rd, rn)),
1023
+ _ => None,
1024
+ }
1025
+ }
1026
+
1027
+ fn is_included_in_clobbers(&self) -> bool {
1028
+ // We exclude call instructions from the clobber-set when they are calls
1029
+ // from caller to callee with the same ABI. Such calls cannot possibly
1030
+ // force any new registers to be saved in the prologue, because anything
1031
+ // that the callee clobbers, the caller is also allowed to clobber. This
1032
+ // both saves work and enables us to more precisely follow the
1033
+ // half-caller-save, half-callee-save SysV ABI for some vector
1034
+ // registers.
1035
+ match self {
1036
+ &Inst::Args { .. } => false,
1037
+ &Inst::Call { ref info, .. } => info.caller_callconv != info.callee_callconv,
1038
+ &Inst::CallInd { ref info, .. } => info.caller_callconv != info.callee_callconv,
1039
+ _ => true,
1040
+ }
1041
+ }
1042
+
1043
+ fn is_trap(&self) -> bool {
1044
+ match self {
1045
+ Self::Trap { .. } => true,
1046
+ _ => false,
1047
+ }
1048
+ }
1049
+
1050
+ fn is_args(&self) -> bool {
1051
+ match self {
1052
+ Self::Args { .. } => true,
1053
+ _ => false,
1054
+ }
1055
+ }
1056
+
1057
+ fn is_term(&self) -> MachTerminator {
1058
+ match self {
1059
+ &Inst::Ret { .. } => MachTerminator::Ret,
1060
+ &Inst::Jump { .. } => MachTerminator::Uncond,
1061
+ &Inst::CondBr { .. } => MachTerminator::Cond,
1062
+ &Inst::OneWayCondBr { .. } => {
1063
+ // Explicitly invisible to CFG processing.
1064
+ MachTerminator::None
1065
+ }
1066
+ &Inst::IndirectBr { .. } => MachTerminator::Indirect,
1067
+ &Inst::JTSequence { .. } => MachTerminator::Indirect,
1068
+ _ => MachTerminator::None,
1069
+ }
1070
+ }
1071
+
1072
+ fn is_safepoint(&self) -> bool {
1073
+ match self {
1074
+ &Inst::Call { .. }
1075
+ | &Inst::CallInd { .. }
1076
+ | &Inst::Trap { .. }
1077
+ | Inst::TrapIf { .. }
1078
+ | &Inst::CmpTrapRR { .. }
1079
+ | &Inst::CmpTrapRSImm16 { .. }
1080
+ | &Inst::CmpTrapRUImm16 { .. } => true,
1081
+ _ => false,
1082
+ }
1083
+ }
1084
+
1085
+ fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
1086
+ assert!(ty.bits() <= 128);
1087
+ if ty.bits() <= 32 {
1088
+ Inst::mov32(to_reg, from_reg)
1089
+ } else if ty.bits() <= 64 {
1090
+ Inst::mov64(to_reg, from_reg)
1091
+ } else {
1092
+ Inst::mov128(to_reg, from_reg)
1093
+ }
1094
+ }
1095
+
1096
+ fn gen_nop(preferred_size: usize) -> Inst {
1097
+ if preferred_size == 0 {
1098
+ Inst::Nop0
1099
+ } else {
1100
+ // We can't give a NOP (or any insn) < 2 bytes.
1101
+ assert!(preferred_size >= 2);
1102
+ Inst::Nop2
1103
+ }
1104
+ }
1105
+
1106
+ fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
1107
+ match ty {
1108
+ types::I8 => Ok((&[RegClass::Int], &[types::I8])),
1109
+ types::I16 => Ok((&[RegClass::Int], &[types::I16])),
1110
+ types::I32 => Ok((&[RegClass::Int], &[types::I32])),
1111
+ types::I64 => Ok((&[RegClass::Int], &[types::I64])),
1112
+ types::R32 => panic!("32-bit reftype pointer should never be seen on s390x"),
1113
+ types::R64 => Ok((&[RegClass::Int], &[types::R64])),
1114
+ types::F32 => Ok((&[RegClass::Float], &[types::F32])),
1115
+ types::F64 => Ok((&[RegClass::Float], &[types::F64])),
1116
+ types::I128 => Ok((&[RegClass::Float], &[types::I128])),
1117
+ _ if ty.is_vector() && ty.bits() == 128 => Ok((&[RegClass::Float], &[types::I8X16])),
1118
+ _ => Err(CodegenError::Unsupported(format!(
1119
+ "Unexpected SSA-value type: {}",
1120
+ ty
1121
+ ))),
1122
+ }
1123
+ }
1124
+
1125
+ fn canonical_type_for_rc(rc: RegClass) -> Type {
1126
+ match rc {
1127
+ RegClass::Int => types::I64,
1128
+ RegClass::Float => types::I8X16,
1129
+ RegClass::Vector => unreachable!(),
1130
+ }
1131
+ }
1132
+
1133
+ fn gen_jump(target: MachLabel) -> Inst {
1134
+ Inst::Jump { dest: target }
1135
+ }
1136
+
1137
+ fn worst_case_size() -> CodeOffset {
1138
+ // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
1139
+ // an 8-instruction sequence (saturating int-to-float conversions) with three embedded
1140
+ // 64-bit f64 constants.
1141
+ //
1142
+ // Note that inline jump-tables handle island/pool insertion separately, so we do not need
1143
+ // to account for them here (otherwise the worst case would be 2^31 * 4, clearly not
1144
+ // feasible for other reasons).
1145
+ 44
1146
+ }
1147
+
1148
+ fn ref_type_regclass(_: &settings::Flags) -> RegClass {
1149
+ RegClass::Int
1150
+ }
1151
+
1152
+ fn gen_dummy_use(reg: Reg) -> Inst {
1153
+ Inst::DummyUse { reg }
1154
+ }
1155
+
1156
+ fn function_alignment() -> FunctionAlignment {
1157
+ FunctionAlignment {
1158
+ minimum: 4,
1159
+ preferred: 4,
1160
+ }
1161
+ }
1162
+ }
1163
+
1164
+ //=============================================================================
1165
+ // Pretty-printing of instructions.
1166
+
1167
+ fn mem_finalize_for_show(mem: &MemArg, state: &EmitState, mi: MemInstType) -> (String, MemArg) {
1168
+ let (mem_insts, mem) = mem_finalize(mem, state, mi);
1169
+ let mut mem_str = mem_insts
1170
+ .into_iter()
1171
+ .map(|inst| {
1172
+ inst.print_with_state(&mut EmitState::default(), &mut AllocationConsumer::new(&[]))
1173
+ })
1174
+ .collect::<Vec<_>>()
1175
+ .join(" ; ");
1176
+ if !mem_str.is_empty() {
1177
+ mem_str += " ; ";
1178
+ }
1179
+
1180
+ (mem_str, mem)
1181
+ }
1182
+
1183
+ impl Inst {
1184
+ fn print_with_state(
1185
+ &self,
1186
+ state: &mut EmitState,
1187
+ allocs: &mut AllocationConsumer<'_>,
1188
+ ) -> String {
1189
+ // N.B.: order of consumption of `allocs` must match the order
1190
+ // in `s390x_get_operands()`.
1191
+
1192
+ let mut empty_allocs = AllocationConsumer::new(&[]);
1193
+
1194
+ match self {
1195
+ &Inst::Nop0 => "nop-zero-len".to_string(),
1196
+ &Inst::Nop2 => "nop".to_string(),
1197
+ &Inst::AluRRR { alu_op, rd, rn, rm } => {
1198
+ let rd = allocs.next_writable(rd);
1199
+ let rn = allocs.next(rn);
1200
+ let rm = allocs.next(rm);
1201
+
1202
+ let (op, have_rr) = match alu_op {
1203
+ ALUOp::Add32 => ("ark", true),
1204
+ ALUOp::Add64 => ("agrk", true),
1205
+ ALUOp::AddLogical32 => ("alrk", true),
1206
+ ALUOp::AddLogical64 => ("algrk", true),
1207
+ ALUOp::Sub32 => ("srk", true),
1208
+ ALUOp::Sub64 => ("sgrk", true),
1209
+ ALUOp::SubLogical32 => ("slrk", true),
1210
+ ALUOp::SubLogical64 => ("slgrk", true),
1211
+ ALUOp::Mul32 => ("msrkc", true),
1212
+ ALUOp::Mul64 => ("msgrkc", true),
1213
+ ALUOp::And32 => ("nrk", true),
1214
+ ALUOp::And64 => ("ngrk", true),
1215
+ ALUOp::Orr32 => ("ork", true),
1216
+ ALUOp::Orr64 => ("ogrk", true),
1217
+ ALUOp::Xor32 => ("xrk", true),
1218
+ ALUOp::Xor64 => ("xgrk", true),
1219
+ ALUOp::NotAnd32 => ("nnrk", false),
1220
+ ALUOp::NotAnd64 => ("nngrk", false),
1221
+ ALUOp::NotOrr32 => ("nork", false),
1222
+ ALUOp::NotOrr64 => ("nogrk", false),
1223
+ ALUOp::NotXor32 => ("nxrk", false),
1224
+ ALUOp::NotXor64 => ("nxgrk", false),
1225
+ ALUOp::AndNot32 => ("ncrk", false),
1226
+ ALUOp::AndNot64 => ("ncgrk", false),
1227
+ ALUOp::OrrNot32 => ("ocrk", false),
1228
+ ALUOp::OrrNot64 => ("ocgrk", false),
1229
+ _ => unreachable!(),
1230
+ };
1231
+ if have_rr && rd.to_reg() == rn {
1232
+ let inst = Inst::AluRR {
1233
+ alu_op,
1234
+ rd,
1235
+ ri: rd.to_reg(),
1236
+ rm,
1237
+ };
1238
+ return inst.print_with_state(state, &mut empty_allocs);
1239
+ }
1240
+ let rd = pretty_print_reg(rd.to_reg(), &mut empty_allocs);
1241
+ let rn = pretty_print_reg(rn, &mut empty_allocs);
1242
+ let rm = pretty_print_reg(rm, &mut empty_allocs);
1243
+ format!("{} {}, {}, {}", op, rd, rn, rm)
1244
+ }
1245
+ &Inst::AluRRSImm16 {
1246
+ alu_op,
1247
+ rd,
1248
+ rn,
1249
+ imm,
1250
+ } => {
1251
+ let rd = allocs.next_writable(rd);
1252
+ let rn = allocs.next(rn);
1253
+
1254
+ if rd.to_reg() == rn {
1255
+ let inst = Inst::AluRSImm16 {
1256
+ alu_op,
1257
+ rd,
1258
+ ri: rd.to_reg(),
1259
+ imm,
1260
+ };
1261
+ return inst.print_with_state(state, &mut empty_allocs);
1262
+ }
1263
+ let op = match alu_op {
1264
+ ALUOp::Add32 => "ahik",
1265
+ ALUOp::Add64 => "aghik",
1266
+ _ => unreachable!(),
1267
+ };
1268
+ let rd = pretty_print_reg(rd.to_reg(), &mut empty_allocs);
1269
+ let rn = pretty_print_reg(rn, &mut empty_allocs);
1270
+ format!("{} {}, {}, {}", op, rd, rn, imm)
1271
+ }
1272
+ &Inst::AluRR { alu_op, rd, ri, rm } => {
1273
+ let op = match alu_op {
1274
+ ALUOp::Add32 => "ar",
1275
+ ALUOp::Add64 => "agr",
1276
+ ALUOp::Add64Ext32 => "agfr",
1277
+ ALUOp::AddLogical32 => "alr",
1278
+ ALUOp::AddLogical64 => "algr",
1279
+ ALUOp::AddLogical64Ext32 => "algfr",
1280
+ ALUOp::Sub32 => "sr",
1281
+ ALUOp::Sub64 => "sgr",
1282
+ ALUOp::Sub64Ext32 => "sgfr",
1283
+ ALUOp::SubLogical32 => "slr",
1284
+ ALUOp::SubLogical64 => "slgr",
1285
+ ALUOp::SubLogical64Ext32 => "slgfr",
1286
+ ALUOp::Mul32 => "msr",
1287
+ ALUOp::Mul64 => "msgr",
1288
+ ALUOp::Mul64Ext32 => "msgfr",
1289
+ ALUOp::And32 => "nr",
1290
+ ALUOp::And64 => "ngr",
1291
+ ALUOp::Orr32 => "or",
1292
+ ALUOp::Orr64 => "ogr",
1293
+ ALUOp::Xor32 => "xr",
1294
+ ALUOp::Xor64 => "xgr",
1295
+ _ => unreachable!(),
1296
+ };
1297
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1298
+ let rm = pretty_print_reg(rm, allocs);
1299
+ format!("{} {}, {}", op, rd, rm)
1300
+ }
1301
+ &Inst::AluRX {
1302
+ alu_op,
1303
+ rd,
1304
+ ri,
1305
+ ref mem,
1306
+ } => {
1307
+ let (opcode_rx, opcode_rxy) = match alu_op {
1308
+ ALUOp::Add32 => (Some("a"), Some("ay")),
1309
+ ALUOp::Add32Ext16 => (Some("ah"), Some("ahy")),
1310
+ ALUOp::Add64 => (None, Some("ag")),
1311
+ ALUOp::Add64Ext16 => (None, Some("agh")),
1312
+ ALUOp::Add64Ext32 => (None, Some("agf")),
1313
+ ALUOp::AddLogical32 => (Some("al"), Some("aly")),
1314
+ ALUOp::AddLogical64 => (None, Some("alg")),
1315
+ ALUOp::AddLogical64Ext32 => (None, Some("algf")),
1316
+ ALUOp::Sub32 => (Some("s"), Some("sy")),
1317
+ ALUOp::Sub32Ext16 => (Some("sh"), Some("shy")),
1318
+ ALUOp::Sub64 => (None, Some("sg")),
1319
+ ALUOp::Sub64Ext16 => (None, Some("sgh")),
1320
+ ALUOp::Sub64Ext32 => (None, Some("sgf")),
1321
+ ALUOp::SubLogical32 => (Some("sl"), Some("sly")),
1322
+ ALUOp::SubLogical64 => (None, Some("slg")),
1323
+ ALUOp::SubLogical64Ext32 => (None, Some("slgf")),
1324
+ ALUOp::Mul32 => (Some("ms"), Some("msy")),
1325
+ ALUOp::Mul32Ext16 => (Some("mh"), Some("mhy")),
1326
+ ALUOp::Mul64 => (None, Some("msg")),
1327
+ ALUOp::Mul64Ext16 => (None, Some("mgh")),
1328
+ ALUOp::Mul64Ext32 => (None, Some("msgf")),
1329
+ ALUOp::And32 => (Some("n"), Some("ny")),
1330
+ ALUOp::And64 => (None, Some("ng")),
1331
+ ALUOp::Orr32 => (Some("o"), Some("oy")),
1332
+ ALUOp::Orr64 => (None, Some("og")),
1333
+ ALUOp::Xor32 => (Some("x"), Some("xy")),
1334
+ ALUOp::Xor64 => (None, Some("xg")),
1335
+ _ => unreachable!(),
1336
+ };
1337
+
1338
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1339
+ let mem = mem.with_allocs(allocs);
1340
+ let (mem_str, mem) = mem_finalize_for_show(
1341
+ &mem,
1342
+ state,
1343
+ MemInstType {
1344
+ have_d12: opcode_rx.is_some(),
1345
+ have_d20: opcode_rxy.is_some(),
1346
+ have_pcrel: false,
1347
+ have_unaligned_pcrel: false,
1348
+ have_index: true,
1349
+ },
1350
+ );
1351
+ let op = match &mem {
1352
+ &MemArg::BXD12 { .. } => opcode_rx,
1353
+ &MemArg::BXD20 { .. } => opcode_rxy,
1354
+ _ => unreachable!(),
1355
+ };
1356
+ let mem = mem.pretty_print_default();
1357
+
1358
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
1359
+ }
1360
+ &Inst::AluRSImm16 {
1361
+ alu_op,
1362
+ rd,
1363
+ ri,
1364
+ imm,
1365
+ } => {
1366
+ let op = match alu_op {
1367
+ ALUOp::Add32 => "ahi",
1368
+ ALUOp::Add64 => "aghi",
1369
+ ALUOp::Mul32 => "mhi",
1370
+ ALUOp::Mul64 => "mghi",
1371
+ _ => unreachable!(),
1372
+ };
1373
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1374
+ format!("{} {}, {}", op, rd, imm)
1375
+ }
1376
+ &Inst::AluRSImm32 {
1377
+ alu_op,
1378
+ rd,
1379
+ ri,
1380
+ imm,
1381
+ } => {
1382
+ let op = match alu_op {
1383
+ ALUOp::Add32 => "afi",
1384
+ ALUOp::Add64 => "agfi",
1385
+ ALUOp::Mul32 => "msfi",
1386
+ ALUOp::Mul64 => "msgfi",
1387
+ _ => unreachable!(),
1388
+ };
1389
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1390
+ format!("{} {}, {}", op, rd, imm)
1391
+ }
1392
+ &Inst::AluRUImm32 {
1393
+ alu_op,
1394
+ rd,
1395
+ ri,
1396
+ imm,
1397
+ } => {
1398
+ let op = match alu_op {
1399
+ ALUOp::AddLogical32 => "alfi",
1400
+ ALUOp::AddLogical64 => "algfi",
1401
+ ALUOp::SubLogical32 => "slfi",
1402
+ ALUOp::SubLogical64 => "slgfi",
1403
+ _ => unreachable!(),
1404
+ };
1405
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1406
+ format!("{} {}, {}", op, rd, imm)
1407
+ }
1408
+ &Inst::AluRUImm16Shifted {
1409
+ alu_op,
1410
+ rd,
1411
+ ri,
1412
+ imm,
1413
+ } => {
1414
+ let op = match (alu_op, imm.shift) {
1415
+ (ALUOp::And32, 0) => "nill",
1416
+ (ALUOp::And32, 1) => "nilh",
1417
+ (ALUOp::And64, 0) => "nill",
1418
+ (ALUOp::And64, 1) => "nilh",
1419
+ (ALUOp::And64, 2) => "nihl",
1420
+ (ALUOp::And64, 3) => "nihh",
1421
+ (ALUOp::Orr32, 0) => "oill",
1422
+ (ALUOp::Orr32, 1) => "oilh",
1423
+ (ALUOp::Orr64, 0) => "oill",
1424
+ (ALUOp::Orr64, 1) => "oilh",
1425
+ (ALUOp::Orr64, 2) => "oihl",
1426
+ (ALUOp::Orr64, 3) => "oihh",
1427
+ _ => unreachable!(),
1428
+ };
1429
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1430
+ format!("{} {}, {}", op, rd, imm.bits)
1431
+ }
1432
+ &Inst::AluRUImm32Shifted {
1433
+ alu_op,
1434
+ rd,
1435
+ ri,
1436
+ imm,
1437
+ } => {
1438
+ let op = match (alu_op, imm.shift) {
1439
+ (ALUOp::And32, 0) => "nilf",
1440
+ (ALUOp::And64, 0) => "nilf",
1441
+ (ALUOp::And64, 1) => "nihf",
1442
+ (ALUOp::Orr32, 0) => "oilf",
1443
+ (ALUOp::Orr64, 0) => "oilf",
1444
+ (ALUOp::Orr64, 1) => "oihf",
1445
+ (ALUOp::Xor32, 0) => "xilf",
1446
+ (ALUOp::Xor64, 0) => "xilf",
1447
+ (ALUOp::Xor64, 1) => "xihf",
1448
+ _ => unreachable!(),
1449
+ };
1450
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1451
+ format!("{} {}, {}", op, rd, imm.bits)
1452
+ }
1453
+ &Inst::SMulWide { rd, rn, rm } => {
1454
+ let op = "mgrk";
1455
+ let rn = pretty_print_reg(rn, allocs);
1456
+ let rm = pretty_print_reg(rm, allocs);
1457
+ let rd = pretty_print_regpair(rd.to_regpair(), allocs);
1458
+ format!("{} {}, {}, {}", op, rd, rn, rm)
1459
+ }
1460
+ &Inst::UMulWide { rd, ri, rn } => {
1461
+ let op = "mlgr";
1462
+ let rn = pretty_print_reg(rn, allocs);
1463
+ let rd = pretty_print_regpair_mod_lo(rd, ri, allocs);
1464
+ format!("{} {}, {}", op, rd, rn)
1465
+ }
1466
+ &Inst::SDivMod32 { rd, ri, rn } => {
1467
+ let op = "dsgfr";
1468
+ let rn = pretty_print_reg(rn, allocs);
1469
+ let rd = pretty_print_regpair_mod_lo(rd, ri, allocs);
1470
+ format!("{} {}, {}", op, rd, rn)
1471
+ }
1472
+ &Inst::SDivMod64 { rd, ri, rn } => {
1473
+ let op = "dsgr";
1474
+ let rn = pretty_print_reg(rn, allocs);
1475
+ let rd = pretty_print_regpair_mod_lo(rd, ri, allocs);
1476
+ format!("{} {}, {}", op, rd, rn)
1477
+ }
1478
+ &Inst::UDivMod32 { rd, ri, rn } => {
1479
+ let op = "dlr";
1480
+ let rn = pretty_print_reg(rn, allocs);
1481
+ let rd = pretty_print_regpair_mod(rd, ri, allocs);
1482
+ format!("{} {}, {}", op, rd, rn)
1483
+ }
1484
+ &Inst::UDivMod64 { rd, ri, rn } => {
1485
+ let op = "dlgr";
1486
+ let rn = pretty_print_reg(rn, allocs);
1487
+ let rd = pretty_print_regpair_mod(rd, ri, allocs);
1488
+ format!("{} {}, {}", op, rd, rn)
1489
+ }
1490
+ &Inst::Flogr { rd, rn } => {
1491
+ let op = "flogr";
1492
+ let rn = pretty_print_reg(rn, allocs);
1493
+ let rd = pretty_print_regpair(rd.to_regpair(), allocs);
1494
+ format!("{} {}, {}", op, rd, rn)
1495
+ }
1496
+ &Inst::ShiftRR {
1497
+ shift_op,
1498
+ rd,
1499
+ rn,
1500
+ shift_imm,
1501
+ shift_reg,
1502
+ } => {
1503
+ let op = match shift_op {
1504
+ ShiftOp::RotL32 => "rll",
1505
+ ShiftOp::RotL64 => "rllg",
1506
+ ShiftOp::LShL32 => "sllk",
1507
+ ShiftOp::LShL64 => "sllg",
1508
+ ShiftOp::LShR32 => "srlk",
1509
+ ShiftOp::LShR64 => "srlg",
1510
+ ShiftOp::AShR32 => "srak",
1511
+ ShiftOp::AShR64 => "srag",
1512
+ };
1513
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1514
+ let rn = pretty_print_reg(rn, allocs);
1515
+ let shift_reg = if shift_reg != zero_reg() {
1516
+ format!("({})", pretty_print_reg(shift_reg, allocs))
1517
+ } else {
1518
+ "".to_string()
1519
+ };
1520
+ format!("{} {}, {}, {}{}", op, rd, rn, shift_imm, shift_reg)
1521
+ }
1522
+ &Inst::RxSBG {
1523
+ op,
1524
+ rd,
1525
+ ri,
1526
+ rn,
1527
+ start_bit,
1528
+ end_bit,
1529
+ rotate_amt,
1530
+ } => {
1531
+ let op = match op {
1532
+ RxSBGOp::Insert => "risbgn",
1533
+ RxSBGOp::And => "rnsbg",
1534
+ RxSBGOp::Or => "rosbg",
1535
+ RxSBGOp::Xor => "rxsbg",
1536
+ };
1537
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1538
+ let rn = pretty_print_reg(rn, allocs);
1539
+ format!(
1540
+ "{} {}, {}, {}, {}, {}",
1541
+ op,
1542
+ rd,
1543
+ rn,
1544
+ start_bit,
1545
+ end_bit,
1546
+ (rotate_amt as u8) & 63
1547
+ )
1548
+ }
1549
+ &Inst::RxSBGTest {
1550
+ op,
1551
+ rd,
1552
+ rn,
1553
+ start_bit,
1554
+ end_bit,
1555
+ rotate_amt,
1556
+ } => {
1557
+ let op = match op {
1558
+ RxSBGOp::And => "rnsbg",
1559
+ RxSBGOp::Or => "rosbg",
1560
+ RxSBGOp::Xor => "rxsbg",
1561
+ _ => unreachable!(),
1562
+ };
1563
+ let rd = pretty_print_reg(rd, allocs);
1564
+ let rn = pretty_print_reg(rn, allocs);
1565
+ format!(
1566
+ "{} {}, {}, {}, {}, {}",
1567
+ op,
1568
+ rd,
1569
+ rn,
1570
+ start_bit | 0x80,
1571
+ end_bit,
1572
+ (rotate_amt as u8) & 63
1573
+ )
1574
+ }
1575
+ &Inst::UnaryRR { op, rd, rn } => {
1576
+ let (op, extra) = match op {
1577
+ UnaryOp::Abs32 => ("lpr", ""),
1578
+ UnaryOp::Abs64 => ("lpgr", ""),
1579
+ UnaryOp::Abs64Ext32 => ("lpgfr", ""),
1580
+ UnaryOp::Neg32 => ("lcr", ""),
1581
+ UnaryOp::Neg64 => ("lcgr", ""),
1582
+ UnaryOp::Neg64Ext32 => ("lcgfr", ""),
1583
+ UnaryOp::PopcntByte => ("popcnt", ""),
1584
+ UnaryOp::PopcntReg => ("popcnt", ", 8"),
1585
+ UnaryOp::BSwap32 => ("lrvr", ""),
1586
+ UnaryOp::BSwap64 => ("lrvgr", ""),
1587
+ };
1588
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1589
+ let rn = pretty_print_reg(rn, allocs);
1590
+ format!("{} {}, {}{}", op, rd, rn, extra)
1591
+ }
1592
+ &Inst::CmpRR { op, rn, rm } => {
1593
+ let op = match op {
1594
+ CmpOp::CmpS32 => "cr",
1595
+ CmpOp::CmpS64 => "cgr",
1596
+ CmpOp::CmpS64Ext32 => "cgfr",
1597
+ CmpOp::CmpL32 => "clr",
1598
+ CmpOp::CmpL64 => "clgr",
1599
+ CmpOp::CmpL64Ext32 => "clgfr",
1600
+ _ => unreachable!(),
1601
+ };
1602
+ let rn = pretty_print_reg(rn, allocs);
1603
+ let rm = pretty_print_reg(rm, allocs);
1604
+ format!("{} {}, {}", op, rn, rm)
1605
+ }
1606
+ &Inst::CmpRX { op, rn, ref mem } => {
1607
+ let (opcode_rx, opcode_rxy, opcode_ril) = match op {
1608
+ CmpOp::CmpS32 => (Some("c"), Some("cy"), Some("crl")),
1609
+ CmpOp::CmpS32Ext16 => (Some("ch"), Some("chy"), Some("chrl")),
1610
+ CmpOp::CmpS64 => (None, Some("cg"), Some("cgrl")),
1611
+ CmpOp::CmpS64Ext16 => (None, Some("cgh"), Some("cghrl")),
1612
+ CmpOp::CmpS64Ext32 => (None, Some("cgf"), Some("cgfrl")),
1613
+ CmpOp::CmpL32 => (Some("cl"), Some("cly"), Some("clrl")),
1614
+ CmpOp::CmpL32Ext16 => (None, None, Some("clhrl")),
1615
+ CmpOp::CmpL64 => (None, Some("clg"), Some("clgrl")),
1616
+ CmpOp::CmpL64Ext16 => (None, None, Some("clghrl")),
1617
+ CmpOp::CmpL64Ext32 => (None, Some("clgf"), Some("clgfrl")),
1618
+ };
1619
+
1620
+ let rn = pretty_print_reg(rn, allocs);
1621
+ let mem = mem.with_allocs(allocs);
1622
+ let (mem_str, mem) = mem_finalize_for_show(
1623
+ &mem,
1624
+ state,
1625
+ MemInstType {
1626
+ have_d12: opcode_rx.is_some(),
1627
+ have_d20: opcode_rxy.is_some(),
1628
+ have_pcrel: opcode_ril.is_some(),
1629
+ have_unaligned_pcrel: false,
1630
+ have_index: true,
1631
+ },
1632
+ );
1633
+ let op = match &mem {
1634
+ &MemArg::BXD12 { .. } => opcode_rx,
1635
+ &MemArg::BXD20 { .. } => opcode_rxy,
1636
+ &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
1637
+ _ => unreachable!(),
1638
+ };
1639
+ let mem = mem.pretty_print_default();
1640
+
1641
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rn, mem)
1642
+ }
1643
+ &Inst::CmpRSImm16 { op, rn, imm } => {
1644
+ let op = match op {
1645
+ CmpOp::CmpS32 => "chi",
1646
+ CmpOp::CmpS64 => "cghi",
1647
+ _ => unreachable!(),
1648
+ };
1649
+ let rn = pretty_print_reg(rn, allocs);
1650
+ format!("{} {}, {}", op, rn, imm)
1651
+ }
1652
+ &Inst::CmpRSImm32 { op, rn, imm } => {
1653
+ let op = match op {
1654
+ CmpOp::CmpS32 => "cfi",
1655
+ CmpOp::CmpS64 => "cgfi",
1656
+ _ => unreachable!(),
1657
+ };
1658
+ let rn = pretty_print_reg(rn, allocs);
1659
+ format!("{} {}, {}", op, rn, imm)
1660
+ }
1661
+ &Inst::CmpRUImm32 { op, rn, imm } => {
1662
+ let op = match op {
1663
+ CmpOp::CmpL32 => "clfi",
1664
+ CmpOp::CmpL64 => "clgfi",
1665
+ _ => unreachable!(),
1666
+ };
1667
+ let rn = pretty_print_reg(rn, allocs);
1668
+ format!("{} {}, {}", op, rn, imm)
1669
+ }
1670
+ &Inst::CmpTrapRR {
1671
+ op, rn, rm, cond, ..
1672
+ } => {
1673
+ let op = match op {
1674
+ CmpOp::CmpS32 => "crt",
1675
+ CmpOp::CmpS64 => "cgrt",
1676
+ CmpOp::CmpL32 => "clrt",
1677
+ CmpOp::CmpL64 => "clgrt",
1678
+ _ => unreachable!(),
1679
+ };
1680
+ let rn = pretty_print_reg(rn, allocs);
1681
+ let rm = pretty_print_reg(rm, allocs);
1682
+ let cond = cond.pretty_print_default();
1683
+ format!("{}{} {}, {}", op, cond, rn, rm)
1684
+ }
1685
+ &Inst::CmpTrapRSImm16 {
1686
+ op, rn, imm, cond, ..
1687
+ } => {
1688
+ let op = match op {
1689
+ CmpOp::CmpS32 => "cit",
1690
+ CmpOp::CmpS64 => "cgit",
1691
+ _ => unreachable!(),
1692
+ };
1693
+ let rn = pretty_print_reg(rn, allocs);
1694
+ let cond = cond.pretty_print_default();
1695
+ format!("{}{} {}, {}", op, cond, rn, imm)
1696
+ }
1697
+ &Inst::CmpTrapRUImm16 {
1698
+ op, rn, imm, cond, ..
1699
+ } => {
1700
+ let op = match op {
1701
+ CmpOp::CmpL32 => "clfit",
1702
+ CmpOp::CmpL64 => "clgit",
1703
+ _ => unreachable!(),
1704
+ };
1705
+ let rn = pretty_print_reg(rn, allocs);
1706
+ let cond = cond.pretty_print_default();
1707
+ format!("{}{} {}, {}", op, cond, rn, imm)
1708
+ }
1709
+ &Inst::AtomicRmw {
1710
+ alu_op,
1711
+ rd,
1712
+ rn,
1713
+ ref mem,
1714
+ } => {
1715
+ let op = match alu_op {
1716
+ ALUOp::Add32 => "laa",
1717
+ ALUOp::Add64 => "laag",
1718
+ ALUOp::AddLogical32 => "laal",
1719
+ ALUOp::AddLogical64 => "laalg",
1720
+ ALUOp::And32 => "lan",
1721
+ ALUOp::And64 => "lang",
1722
+ ALUOp::Orr32 => "lao",
1723
+ ALUOp::Orr64 => "laog",
1724
+ ALUOp::Xor32 => "lax",
1725
+ ALUOp::Xor64 => "laxg",
1726
+ _ => unreachable!(),
1727
+ };
1728
+
1729
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1730
+ let rn = pretty_print_reg(rn, allocs);
1731
+ let mem = mem.with_allocs(allocs);
1732
+ let (mem_str, mem) = mem_finalize_for_show(
1733
+ &mem,
1734
+ state,
1735
+ MemInstType {
1736
+ have_d12: false,
1737
+ have_d20: true,
1738
+ have_pcrel: false,
1739
+ have_unaligned_pcrel: false,
1740
+ have_index: false,
1741
+ },
1742
+ );
1743
+ let mem = mem.pretty_print_default();
1744
+ format!("{}{} {}, {}, {}", mem_str, op, rd, rn, mem)
1745
+ }
1746
+ &Inst::AtomicCas32 {
1747
+ rd,
1748
+ ri,
1749
+ rn,
1750
+ ref mem,
1751
+ }
1752
+ | &Inst::AtomicCas64 {
1753
+ rd,
1754
+ ri,
1755
+ rn,
1756
+ ref mem,
1757
+ } => {
1758
+ let (opcode_rs, opcode_rsy) = match self {
1759
+ &Inst::AtomicCas32 { .. } => (Some("cs"), Some("csy")),
1760
+ &Inst::AtomicCas64 { .. } => (None, Some("csg")),
1761
+ _ => unreachable!(),
1762
+ };
1763
+
1764
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
1765
+ let rn = pretty_print_reg(rn, allocs);
1766
+ let mem = mem.with_allocs(allocs);
1767
+ let (mem_str, mem) = mem_finalize_for_show(
1768
+ &mem,
1769
+ state,
1770
+ MemInstType {
1771
+ have_d12: opcode_rs.is_some(),
1772
+ have_d20: opcode_rsy.is_some(),
1773
+ have_pcrel: false,
1774
+ have_unaligned_pcrel: false,
1775
+ have_index: false,
1776
+ },
1777
+ );
1778
+ let op = match &mem {
1779
+ &MemArg::BXD12 { .. } => opcode_rs,
1780
+ &MemArg::BXD20 { .. } => opcode_rsy,
1781
+ _ => unreachable!(),
1782
+ };
1783
+ let mem = mem.pretty_print_default();
1784
+
1785
+ format!("{}{} {}, {}, {}", mem_str, op.unwrap(), rd, rn, mem)
1786
+ }
1787
+ &Inst::Fence => "bcr 14, 0".to_string(),
1788
+ &Inst::Load32 { rd, ref mem }
1789
+ | &Inst::Load32ZExt8 { rd, ref mem }
1790
+ | &Inst::Load32SExt8 { rd, ref mem }
1791
+ | &Inst::Load32ZExt16 { rd, ref mem }
1792
+ | &Inst::Load32SExt16 { rd, ref mem }
1793
+ | &Inst::Load64 { rd, ref mem }
1794
+ | &Inst::Load64ZExt8 { rd, ref mem }
1795
+ | &Inst::Load64SExt8 { rd, ref mem }
1796
+ | &Inst::Load64ZExt16 { rd, ref mem }
1797
+ | &Inst::Load64SExt16 { rd, ref mem }
1798
+ | &Inst::Load64ZExt32 { rd, ref mem }
1799
+ | &Inst::Load64SExt32 { rd, ref mem }
1800
+ | &Inst::LoadRev16 { rd, ref mem }
1801
+ | &Inst::LoadRev32 { rd, ref mem }
1802
+ | &Inst::LoadRev64 { rd, ref mem } => {
1803
+ let (opcode_rx, opcode_rxy, opcode_ril) = match self {
1804
+ &Inst::Load32 { .. } => (Some("l"), Some("ly"), Some("lrl")),
1805
+ &Inst::Load32ZExt8 { .. } => (None, Some("llc"), None),
1806
+ &Inst::Load32SExt8 { .. } => (None, Some("lb"), None),
1807
+ &Inst::Load32ZExt16 { .. } => (None, Some("llh"), Some("llhrl")),
1808
+ &Inst::Load32SExt16 { .. } => (Some("lh"), Some("lhy"), Some("lhrl")),
1809
+ &Inst::Load64 { .. } => (None, Some("lg"), Some("lgrl")),
1810
+ &Inst::Load64ZExt8 { .. } => (None, Some("llgc"), None),
1811
+ &Inst::Load64SExt8 { .. } => (None, Some("lgb"), None),
1812
+ &Inst::Load64ZExt16 { .. } => (None, Some("llgh"), Some("llghrl")),
1813
+ &Inst::Load64SExt16 { .. } => (None, Some("lgh"), Some("lghrl")),
1814
+ &Inst::Load64ZExt32 { .. } => (None, Some("llgf"), Some("llgfrl")),
1815
+ &Inst::Load64SExt32 { .. } => (None, Some("lgf"), Some("lgfrl")),
1816
+ &Inst::LoadRev16 { .. } => (None, Some("lrvh"), None),
1817
+ &Inst::LoadRev32 { .. } => (None, Some("lrv"), None),
1818
+ &Inst::LoadRev64 { .. } => (None, Some("lrvg"), None),
1819
+ _ => unreachable!(),
1820
+ };
1821
+
1822
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1823
+ let mem = mem.with_allocs(allocs);
1824
+ let (mem_str, mem) = mem_finalize_for_show(
1825
+ &mem,
1826
+ state,
1827
+ MemInstType {
1828
+ have_d12: opcode_rx.is_some(),
1829
+ have_d20: opcode_rxy.is_some(),
1830
+ have_pcrel: opcode_ril.is_some(),
1831
+ have_unaligned_pcrel: false,
1832
+ have_index: true,
1833
+ },
1834
+ );
1835
+ let op = match &mem {
1836
+ &MemArg::BXD12 { .. } => opcode_rx,
1837
+ &MemArg::BXD20 { .. } => opcode_rxy,
1838
+ &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
1839
+ _ => unreachable!(),
1840
+ };
1841
+ let mem = mem.pretty_print_default();
1842
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
1843
+ }
1844
+ &Inst::Store8 { rd, ref mem }
1845
+ | &Inst::Store16 { rd, ref mem }
1846
+ | &Inst::Store32 { rd, ref mem }
1847
+ | &Inst::Store64 { rd, ref mem }
1848
+ | &Inst::StoreRev16 { rd, ref mem }
1849
+ | &Inst::StoreRev32 { rd, ref mem }
1850
+ | &Inst::StoreRev64 { rd, ref mem } => {
1851
+ let (opcode_rx, opcode_rxy, opcode_ril) = match self {
1852
+ &Inst::Store8 { .. } => (Some("stc"), Some("stcy"), None),
1853
+ &Inst::Store16 { .. } => (Some("sth"), Some("sthy"), Some("sthrl")),
1854
+ &Inst::Store32 { .. } => (Some("st"), Some("sty"), Some("strl")),
1855
+ &Inst::Store64 { .. } => (None, Some("stg"), Some("stgrl")),
1856
+ &Inst::StoreRev16 { .. } => (None, Some("strvh"), None),
1857
+ &Inst::StoreRev32 { .. } => (None, Some("strv"), None),
1858
+ &Inst::StoreRev64 { .. } => (None, Some("strvg"), None),
1859
+ _ => unreachable!(),
1860
+ };
1861
+
1862
+ let rd = pretty_print_reg(rd, allocs);
1863
+ let mem = mem.with_allocs(allocs);
1864
+ let (mem_str, mem) = mem_finalize_for_show(
1865
+ &mem,
1866
+ state,
1867
+ MemInstType {
1868
+ have_d12: opcode_rx.is_some(),
1869
+ have_d20: opcode_rxy.is_some(),
1870
+ have_pcrel: opcode_ril.is_some(),
1871
+ have_unaligned_pcrel: false,
1872
+ have_index: true,
1873
+ },
1874
+ );
1875
+ let op = match &mem {
1876
+ &MemArg::BXD12 { .. } => opcode_rx,
1877
+ &MemArg::BXD20 { .. } => opcode_rxy,
1878
+ &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
1879
+ _ => unreachable!(),
1880
+ };
1881
+ let mem = mem.pretty_print_default();
1882
+
1883
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
1884
+ }
1885
+ &Inst::StoreImm8 { imm, ref mem } => {
1886
+ let mem = mem.with_allocs(allocs);
1887
+ let (mem_str, mem) = mem_finalize_for_show(
1888
+ &mem,
1889
+ state,
1890
+ MemInstType {
1891
+ have_d12: true,
1892
+ have_d20: true,
1893
+ have_pcrel: false,
1894
+ have_unaligned_pcrel: false,
1895
+ have_index: false,
1896
+ },
1897
+ );
1898
+ let op = match &mem {
1899
+ &MemArg::BXD12 { .. } => "mvi",
1900
+ &MemArg::BXD20 { .. } => "mviy",
1901
+ _ => unreachable!(),
1902
+ };
1903
+ let mem = mem.pretty_print_default();
1904
+
1905
+ format!("{}{} {}, {}", mem_str, op, mem, imm)
1906
+ }
1907
+ &Inst::StoreImm16 { imm, ref mem }
1908
+ | &Inst::StoreImm32SExt16 { imm, ref mem }
1909
+ | &Inst::StoreImm64SExt16 { imm, ref mem } => {
1910
+ let mem = mem.with_allocs(allocs);
1911
+ let (mem_str, mem) = mem_finalize_for_show(
1912
+ &mem,
1913
+ state,
1914
+ MemInstType {
1915
+ have_d12: false,
1916
+ have_d20: true,
1917
+ have_pcrel: false,
1918
+ have_unaligned_pcrel: false,
1919
+ have_index: false,
1920
+ },
1921
+ );
1922
+ let op = match self {
1923
+ &Inst::StoreImm16 { .. } => "mvhhi",
1924
+ &Inst::StoreImm32SExt16 { .. } => "mvhi",
1925
+ &Inst::StoreImm64SExt16 { .. } => "mvghi",
1926
+ _ => unreachable!(),
1927
+ };
1928
+ let mem = mem.pretty_print_default();
1929
+
1930
+ format!("{}{} {}, {}", mem_str, op, mem, imm)
1931
+ }
1932
+ &Inst::Mvc {
1933
+ ref dst,
1934
+ ref src,
1935
+ len_minus_one,
1936
+ } => {
1937
+ let dst = dst.with_allocs(allocs);
1938
+ let src = src.with_allocs(allocs);
1939
+ format!(
1940
+ "mvc {}({},{}), {}({})",
1941
+ dst.disp.pretty_print_default(),
1942
+ len_minus_one,
1943
+ show_reg(dst.base),
1944
+ src.disp.pretty_print_default(),
1945
+ show_reg(src.base)
1946
+ )
1947
+ }
1948
+ &Inst::LoadMultiple64 { rt, rt2, ref mem } => {
1949
+ let mem = mem.with_allocs(allocs);
1950
+ let (mem_str, mem) = mem_finalize_for_show(
1951
+ &mem,
1952
+ state,
1953
+ MemInstType {
1954
+ have_d12: false,
1955
+ have_d20: true,
1956
+ have_pcrel: false,
1957
+ have_unaligned_pcrel: false,
1958
+ have_index: false,
1959
+ },
1960
+ );
1961
+ let rt = pretty_print_reg(rt.to_reg(), &mut empty_allocs);
1962
+ let rt2 = pretty_print_reg(rt2.to_reg(), &mut empty_allocs);
1963
+ let mem = mem.pretty_print_default();
1964
+ format!("{}lmg {}, {}, {}", mem_str, rt, rt2, mem)
1965
+ }
1966
+ &Inst::StoreMultiple64 { rt, rt2, ref mem } => {
1967
+ let mem = mem.with_allocs(allocs);
1968
+ let (mem_str, mem) = mem_finalize_for_show(
1969
+ &mem,
1970
+ state,
1971
+ MemInstType {
1972
+ have_d12: false,
1973
+ have_d20: true,
1974
+ have_pcrel: false,
1975
+ have_unaligned_pcrel: false,
1976
+ have_index: false,
1977
+ },
1978
+ );
1979
+ let rt = pretty_print_reg(rt, &mut empty_allocs);
1980
+ let rt2 = pretty_print_reg(rt2, &mut empty_allocs);
1981
+ let mem = mem.pretty_print_default();
1982
+ format!("{}stmg {}, {}, {}", mem_str, rt, rt2, mem)
1983
+ }
1984
+ &Inst::Mov64 { rd, rm } => {
1985
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1986
+ let rm = pretty_print_reg(rm, allocs);
1987
+ format!("lgr {}, {}", rd, rm)
1988
+ }
1989
+ &Inst::MovPReg { rd, rm } => {
1990
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1991
+ let rm = show_reg(rm.into());
1992
+ format!("lgr {}, {}", rd, rm)
1993
+ }
1994
+ &Inst::Mov32 { rd, rm } => {
1995
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
1996
+ let rm = pretty_print_reg(rm, allocs);
1997
+ format!("lr {}, {}", rd, rm)
1998
+ }
1999
+ &Inst::Mov32Imm { rd, ref imm } => {
2000
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2001
+ format!("iilf {}, {}", rd, imm)
2002
+ }
2003
+ &Inst::Mov32SImm16 { rd, ref imm } => {
2004
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2005
+ format!("lhi {}, {}", rd, imm)
2006
+ }
2007
+ &Inst::Mov64SImm16 { rd, ref imm } => {
2008
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2009
+ format!("lghi {}, {}", rd, imm)
2010
+ }
2011
+ &Inst::Mov64SImm32 { rd, ref imm } => {
2012
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2013
+ format!("lgfi {}, {}", rd, imm)
2014
+ }
2015
+ &Inst::Mov64UImm16Shifted { rd, ref imm } => {
2016
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2017
+ let op = match imm.shift {
2018
+ 0 => "llill",
2019
+ 1 => "llilh",
2020
+ 2 => "llihl",
2021
+ 3 => "llihh",
2022
+ _ => unreachable!(),
2023
+ };
2024
+ format!("{} {}, {}", op, rd, imm.bits)
2025
+ }
2026
+ &Inst::Mov64UImm32Shifted { rd, ref imm } => {
2027
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2028
+ let op = match imm.shift {
2029
+ 0 => "llilf",
2030
+ 1 => "llihf",
2031
+ _ => unreachable!(),
2032
+ };
2033
+ format!("{} {}, {}", op, rd, imm.bits)
2034
+ }
2035
+ &Inst::Insert64UImm16Shifted { rd, ri, ref imm } => {
2036
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2037
+ let op = match imm.shift {
2038
+ 0 => "iill",
2039
+ 1 => "iilh",
2040
+ 2 => "iihl",
2041
+ 3 => "iihh",
2042
+ _ => unreachable!(),
2043
+ };
2044
+ format!("{} {}, {}", op, rd, imm.bits)
2045
+ }
2046
+ &Inst::Insert64UImm32Shifted { rd, ri, ref imm } => {
2047
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2048
+ let op = match imm.shift {
2049
+ 0 => "iilf",
2050
+ 1 => "iihf",
2051
+ _ => unreachable!(),
2052
+ };
2053
+ format!("{} {}, {}", op, rd, imm.bits)
2054
+ }
2055
+ &Inst::LoadAR { rd, ar } => {
2056
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2057
+ format!("ear {}, %a{}", rd, ar)
2058
+ }
2059
+ &Inst::InsertAR { rd, ri, ar } => {
2060
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2061
+ format!("ear {}, %a{}", rd, ar)
2062
+ }
2063
+ &Inst::CMov32 { rd, cond, ri, rm } => {
2064
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2065
+ let rm = pretty_print_reg(rm, allocs);
2066
+ let cond = cond.pretty_print_default();
2067
+ format!("locr{} {}, {}", cond, rd, rm)
2068
+ }
2069
+ &Inst::CMov64 { rd, cond, ri, rm } => {
2070
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2071
+ let rm = pretty_print_reg(rm, allocs);
2072
+ let cond = cond.pretty_print_default();
2073
+ format!("locgr{} {}, {}", cond, rd, rm)
2074
+ }
2075
+ &Inst::CMov32SImm16 {
2076
+ rd,
2077
+ cond,
2078
+ ri,
2079
+ ref imm,
2080
+ } => {
2081
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2082
+ let cond = cond.pretty_print_default();
2083
+ format!("lochi{} {}, {}", cond, rd, imm)
2084
+ }
2085
+ &Inst::CMov64SImm16 {
2086
+ rd,
2087
+ cond,
2088
+ ri,
2089
+ ref imm,
2090
+ } => {
2091
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2092
+ let cond = cond.pretty_print_default();
2093
+ format!("locghi{} {}, {}", cond, rd, imm)
2094
+ }
2095
+ &Inst::FpuMove32 { rd, rn } => {
2096
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2097
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2098
+ if rd_fpr.is_some() && rn_fpr.is_some() {
2099
+ format!("ler {}, {}", rd_fpr.unwrap(), rn_fpr.unwrap())
2100
+ } else {
2101
+ format!("vlr {}, {}", rd, rn)
2102
+ }
2103
+ }
2104
+ &Inst::FpuMove64 { rd, rn } => {
2105
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2106
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2107
+ if rd_fpr.is_some() && rn_fpr.is_some() {
2108
+ format!("ldr {}, {}", rd_fpr.unwrap(), rn_fpr.unwrap())
2109
+ } else {
2110
+ format!("vlr {}, {}", rd, rn)
2111
+ }
2112
+ }
2113
+ &Inst::FpuCMov32 { rd, cond, ri, rm } => {
2114
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2115
+ let _ri = allocs.next(ri);
2116
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2117
+ if rd_fpr.is_some() && rm_fpr.is_some() {
2118
+ let cond = cond.invert().pretty_print_default();
2119
+ format!("j{} 6 ; ler {}, {}", cond, rd_fpr.unwrap(), rm_fpr.unwrap())
2120
+ } else {
2121
+ let cond = cond.invert().pretty_print_default();
2122
+ format!("j{} 10 ; vlr {}, {}", cond, rd, rm)
2123
+ }
2124
+ }
2125
+ &Inst::FpuCMov64 { rd, cond, ri, rm } => {
2126
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2127
+ let _ri = allocs.next(ri);
2128
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2129
+ if rd_fpr.is_some() && rm_fpr.is_some() {
2130
+ let cond = cond.invert().pretty_print_default();
2131
+ format!("j{} 6 ; ldr {}, {}", cond, rd_fpr.unwrap(), rm_fpr.unwrap())
2132
+ } else {
2133
+ let cond = cond.invert().pretty_print_default();
2134
+ format!("j{} 10 ; vlr {}, {}", cond, rd, rm)
2135
+ }
2136
+ }
2137
+ &Inst::FpuRR { fpu_op, rd, rn } => {
2138
+ let (op, op_fpr) = match fpu_op {
2139
+ FPUOp1::Abs32 => ("wflpsb", Some("lpebr")),
2140
+ FPUOp1::Abs64 => ("wflpdb", Some("lpdbr")),
2141
+ FPUOp1::Abs32x4 => ("vflpsb", None),
2142
+ FPUOp1::Abs64x2 => ("vflpdb", None),
2143
+ FPUOp1::Neg32 => ("wflcsb", Some("lcebr")),
2144
+ FPUOp1::Neg64 => ("wflcdb", Some("lcdbr")),
2145
+ FPUOp1::Neg32x4 => ("vflcsb", None),
2146
+ FPUOp1::Neg64x2 => ("vflcdb", None),
2147
+ FPUOp1::NegAbs32 => ("wflnsb", Some("lnebr")),
2148
+ FPUOp1::NegAbs64 => ("wflndb", Some("lndbr")),
2149
+ FPUOp1::NegAbs32x4 => ("vflnsb", None),
2150
+ FPUOp1::NegAbs64x2 => ("vflndb", None),
2151
+ FPUOp1::Sqrt32 => ("wfsqsb", Some("sqebr")),
2152
+ FPUOp1::Sqrt64 => ("wfsqdb", Some("sqdbr")),
2153
+ FPUOp1::Sqrt32x4 => ("vfsqsb", None),
2154
+ FPUOp1::Sqrt64x2 => ("vfsqdb", None),
2155
+ FPUOp1::Cvt32To64 => ("wldeb", Some("ldebr")),
2156
+ FPUOp1::Cvt32x4To64x2 => ("vldeb", None),
2157
+ };
2158
+
2159
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2160
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2161
+ if op_fpr.is_some() && rd_fpr.is_some() && rn_fpr.is_some() {
2162
+ format!(
2163
+ "{} {}, {}",
2164
+ op_fpr.unwrap(),
2165
+ rd_fpr.unwrap(),
2166
+ rn_fpr.unwrap()
2167
+ )
2168
+ } else if op.starts_with('w') {
2169
+ format!("{} {}, {}", op, rd_fpr.unwrap_or(rd), rn_fpr.unwrap_or(rn))
2170
+ } else {
2171
+ format!("{} {}, {}", op, rd, rn)
2172
+ }
2173
+ }
2174
+ &Inst::FpuRRR { fpu_op, rd, rn, rm } => {
2175
+ let (op, opt_m6, op_fpr) = match fpu_op {
2176
+ FPUOp2::Add32 => ("wfasb", "", Some("aebr")),
2177
+ FPUOp2::Add64 => ("wfadb", "", Some("adbr")),
2178
+ FPUOp2::Add32x4 => ("vfasb", "", None),
2179
+ FPUOp2::Add64x2 => ("vfadb", "", None),
2180
+ FPUOp2::Sub32 => ("wfssb", "", Some("sebr")),
2181
+ FPUOp2::Sub64 => ("wfsdb", "", Some("sdbr")),
2182
+ FPUOp2::Sub32x4 => ("vfssb", "", None),
2183
+ FPUOp2::Sub64x2 => ("vfsdb", "", None),
2184
+ FPUOp2::Mul32 => ("wfmsb", "", Some("meebr")),
2185
+ FPUOp2::Mul64 => ("wfmdb", "", Some("mdbr")),
2186
+ FPUOp2::Mul32x4 => ("vfmsb", "", None),
2187
+ FPUOp2::Mul64x2 => ("vfmdb", "", None),
2188
+ FPUOp2::Div32 => ("wfdsb", "", Some("debr")),
2189
+ FPUOp2::Div64 => ("wfddb", "", Some("ddbr")),
2190
+ FPUOp2::Div32x4 => ("vfdsb", "", None),
2191
+ FPUOp2::Div64x2 => ("vfddb", "", None),
2192
+ FPUOp2::Max32 => ("wfmaxsb", ", 1", None),
2193
+ FPUOp2::Max64 => ("wfmaxdb", ", 1", None),
2194
+ FPUOp2::Max32x4 => ("vfmaxsb", ", 1", None),
2195
+ FPUOp2::Max64x2 => ("vfmaxdb", ", 1", None),
2196
+ FPUOp2::Min32 => ("wfminsb", ", 1", None),
2197
+ FPUOp2::Min64 => ("wfmindb", ", 1", None),
2198
+ FPUOp2::Min32x4 => ("vfminsb", ", 1", None),
2199
+ FPUOp2::Min64x2 => ("vfmindb", ", 1", None),
2200
+ FPUOp2::MaxPseudo32 => ("wfmaxsb", ", 3", None),
2201
+ FPUOp2::MaxPseudo64 => ("wfmaxdb", ", 3", None),
2202
+ FPUOp2::MaxPseudo32x4 => ("vfmaxsb", ", 3", None),
2203
+ FPUOp2::MaxPseudo64x2 => ("vfmaxdb", ", 3", None),
2204
+ FPUOp2::MinPseudo32 => ("wfminsb", ", 3", None),
2205
+ FPUOp2::MinPseudo64 => ("wfmindb", ", 3", None),
2206
+ FPUOp2::MinPseudo32x4 => ("vfminsb", ", 3", None),
2207
+ FPUOp2::MinPseudo64x2 => ("vfmindb", ", 3", None),
2208
+ };
2209
+
2210
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2211
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2212
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2213
+ if op_fpr.is_some() && rd == rn && rd_fpr.is_some() && rm_fpr.is_some() {
2214
+ format!(
2215
+ "{} {}, {}",
2216
+ op_fpr.unwrap(),
2217
+ rd_fpr.unwrap(),
2218
+ rm_fpr.unwrap()
2219
+ )
2220
+ } else if op.starts_with('w') {
2221
+ format!(
2222
+ "{} {}, {}, {}{}",
2223
+ op,
2224
+ rd_fpr.unwrap_or(rd),
2225
+ rn_fpr.unwrap_or(rn),
2226
+ rm_fpr.unwrap_or(rm),
2227
+ opt_m6
2228
+ )
2229
+ } else {
2230
+ format!("{} {}, {}, {}{}", op, rd, rn, rm, opt_m6)
2231
+ }
2232
+ }
2233
+ &Inst::FpuRRRR {
2234
+ fpu_op,
2235
+ rd,
2236
+ rn,
2237
+ rm,
2238
+ ra,
2239
+ } => {
2240
+ let (op, op_fpr) = match fpu_op {
2241
+ FPUOp3::MAdd32 => ("wfmasb", Some("maebr")),
2242
+ FPUOp3::MAdd64 => ("wfmadb", Some("madbr")),
2243
+ FPUOp3::MAdd32x4 => ("vfmasb", None),
2244
+ FPUOp3::MAdd64x2 => ("vfmadb", None),
2245
+ FPUOp3::MSub32 => ("wfmssb", Some("msebr")),
2246
+ FPUOp3::MSub64 => ("wfmsdb", Some("msdbr")),
2247
+ FPUOp3::MSub32x4 => ("vfmssb", None),
2248
+ FPUOp3::MSub64x2 => ("vfmsdb", None),
2249
+ };
2250
+
2251
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2252
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2253
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2254
+ let (ra, ra_fpr) = pretty_print_fpr(ra, allocs);
2255
+ if op_fpr.is_some()
2256
+ && rd == ra
2257
+ && rd_fpr.is_some()
2258
+ && rn_fpr.is_some()
2259
+ && rm_fpr.is_some()
2260
+ {
2261
+ format!(
2262
+ "{} {}, {}, {}",
2263
+ op_fpr.unwrap(),
2264
+ rd_fpr.unwrap(),
2265
+ rn_fpr.unwrap(),
2266
+ rm_fpr.unwrap()
2267
+ )
2268
+ } else if op.starts_with('w') {
2269
+ format!(
2270
+ "{} {}, {}, {}, {}",
2271
+ op,
2272
+ rd_fpr.unwrap_or(rd),
2273
+ rn_fpr.unwrap_or(rn),
2274
+ rm_fpr.unwrap_or(rm),
2275
+ ra_fpr.unwrap_or(ra)
2276
+ )
2277
+ } else {
2278
+ format!("{} {}, {}, {}, {}", op, rd, rn, rm, ra)
2279
+ }
2280
+ }
2281
+ &Inst::FpuCmp32 { rn, rm } => {
2282
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2283
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2284
+ if rn_fpr.is_some() && rm_fpr.is_some() {
2285
+ format!("cebr {}, {}", rn_fpr.unwrap(), rm_fpr.unwrap())
2286
+ } else {
2287
+ format!("wfcsb {}, {}", rn_fpr.unwrap_or(rn), rm_fpr.unwrap_or(rm))
2288
+ }
2289
+ }
2290
+ &Inst::FpuCmp64 { rn, rm } => {
2291
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2292
+ let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
2293
+ if rn_fpr.is_some() && rm_fpr.is_some() {
2294
+ format!("cdbr {}, {}", rn_fpr.unwrap(), rm_fpr.unwrap())
2295
+ } else {
2296
+ format!("wfcdb {}, {}", rn_fpr.unwrap_or(rn), rm_fpr.unwrap_or(rm))
2297
+ }
2298
+ }
2299
+ &Inst::LoadFpuConst32 { rd, const_data } => {
2300
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2301
+ let tmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
2302
+ if rd_fpr.is_some() {
2303
+ format!(
2304
+ "bras {}, 8 ; data.f32 {} ; le {}, 0({})",
2305
+ tmp,
2306
+ f32::from_bits(const_data),
2307
+ rd_fpr.unwrap(),
2308
+ tmp
2309
+ )
2310
+ } else {
2311
+ format!(
2312
+ "bras {}, 8 ; data.f32 {} ; vlef {}, 0({}), 0",
2313
+ tmp,
2314
+ f32::from_bits(const_data),
2315
+ rd,
2316
+ tmp
2317
+ )
2318
+ }
2319
+ }
2320
+ &Inst::LoadFpuConst64 { rd, const_data } => {
2321
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2322
+ let tmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
2323
+ if rd_fpr.is_some() {
2324
+ format!(
2325
+ "bras {}, 12 ; data.f64 {} ; ld {}, 0({})",
2326
+ tmp,
2327
+ f64::from_bits(const_data),
2328
+ rd_fpr.unwrap(),
2329
+ tmp
2330
+ )
2331
+ } else {
2332
+ format!(
2333
+ "bras {}, 12 ; data.f64 {} ; vleg {}, 0({}), 0",
2334
+ tmp,
2335
+ f64::from_bits(const_data),
2336
+ rd,
2337
+ tmp
2338
+ )
2339
+ }
2340
+ }
2341
+ &Inst::FpuRound { op, mode, rd, rn } => {
2342
+ let mode = match mode {
2343
+ FpuRoundMode::Current => 0,
2344
+ FpuRoundMode::ToNearest => 1,
2345
+ FpuRoundMode::ShorterPrecision => 3,
2346
+ FpuRoundMode::ToNearestTiesToEven => 4,
2347
+ FpuRoundMode::ToZero => 5,
2348
+ FpuRoundMode::ToPosInfinity => 6,
2349
+ FpuRoundMode::ToNegInfinity => 7,
2350
+ };
2351
+ let (opcode, opcode_fpr) = match op {
2352
+ FpuRoundOp::Cvt64To32 => ("wledb", Some("ledbra")),
2353
+ FpuRoundOp::Cvt64x2To32x4 => ("vledb", None),
2354
+ FpuRoundOp::Round32 => ("wfisb", Some("fiebr")),
2355
+ FpuRoundOp::Round64 => ("wfidb", Some("fidbr")),
2356
+ FpuRoundOp::Round32x4 => ("vfisb", None),
2357
+ FpuRoundOp::Round64x2 => ("vfidb", None),
2358
+ FpuRoundOp::ToSInt32 => ("wcfeb", None),
2359
+ FpuRoundOp::ToSInt64 => ("wcgdb", None),
2360
+ FpuRoundOp::ToUInt32 => ("wclfeb", None),
2361
+ FpuRoundOp::ToUInt64 => ("wclgdb", None),
2362
+ FpuRoundOp::ToSInt32x4 => ("vcfeb", None),
2363
+ FpuRoundOp::ToSInt64x2 => ("vcgdb", None),
2364
+ FpuRoundOp::ToUInt32x4 => ("vclfeb", None),
2365
+ FpuRoundOp::ToUInt64x2 => ("vclgdb", None),
2366
+ FpuRoundOp::FromSInt32 => ("wcefb", None),
2367
+ FpuRoundOp::FromSInt64 => ("wcdgb", None),
2368
+ FpuRoundOp::FromUInt32 => ("wcelfb", None),
2369
+ FpuRoundOp::FromUInt64 => ("wcdlgb", None),
2370
+ FpuRoundOp::FromSInt32x4 => ("vcefb", None),
2371
+ FpuRoundOp::FromSInt64x2 => ("vcdgb", None),
2372
+ FpuRoundOp::FromUInt32x4 => ("vcelfb", None),
2373
+ FpuRoundOp::FromUInt64x2 => ("vcdlgb", None),
2374
+ };
2375
+
2376
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2377
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
2378
+ if opcode_fpr.is_some() && rd_fpr.is_some() && rn_fpr.is_some() {
2379
+ format!(
2380
+ "{} {}, {}, {}{}",
2381
+ opcode_fpr.unwrap(),
2382
+ rd_fpr.unwrap(),
2383
+ mode,
2384
+ rn_fpr.unwrap(),
2385
+ if opcode_fpr.unwrap().ends_with('a') {
2386
+ ", 0"
2387
+ } else {
2388
+ ""
2389
+ }
2390
+ )
2391
+ } else if opcode.starts_with('w') {
2392
+ format!(
2393
+ "{} {}, {}, 0, {}",
2394
+ opcode,
2395
+ rd_fpr.unwrap_or(rd),
2396
+ rn_fpr.unwrap_or(rn),
2397
+ mode
2398
+ )
2399
+ } else {
2400
+ format!("{} {}, {}, 0, {}", opcode, rd, rn, mode)
2401
+ }
2402
+ }
2403
+ &Inst::VecRRR { op, rd, rn, rm } => {
2404
+ let op = match op {
2405
+ VecBinaryOp::Add8x16 => "vab",
2406
+ VecBinaryOp::Add16x8 => "vah",
2407
+ VecBinaryOp::Add32x4 => "vaf",
2408
+ VecBinaryOp::Add64x2 => "vag",
2409
+ VecBinaryOp::Add128 => "vaq",
2410
+ VecBinaryOp::Sub8x16 => "vsb",
2411
+ VecBinaryOp::Sub16x8 => "vsh",
2412
+ VecBinaryOp::Sub32x4 => "vsf",
2413
+ VecBinaryOp::Sub64x2 => "vsg",
2414
+ VecBinaryOp::Sub128 => "vsq",
2415
+ VecBinaryOp::Mul8x16 => "vmlb",
2416
+ VecBinaryOp::Mul16x8 => "vmlhw",
2417
+ VecBinaryOp::Mul32x4 => "vmlf",
2418
+ VecBinaryOp::UMulHi8x16 => "vmlhb",
2419
+ VecBinaryOp::UMulHi16x8 => "vmlhh",
2420
+ VecBinaryOp::UMulHi32x4 => "vmlhf",
2421
+ VecBinaryOp::SMulHi8x16 => "vmhb",
2422
+ VecBinaryOp::SMulHi16x8 => "vmhh",
2423
+ VecBinaryOp::SMulHi32x4 => "vmhf",
2424
+ VecBinaryOp::UMulEven8x16 => "vmleb",
2425
+ VecBinaryOp::UMulEven16x8 => "vmleh",
2426
+ VecBinaryOp::UMulEven32x4 => "vmlef",
2427
+ VecBinaryOp::SMulEven8x16 => "vmeb",
2428
+ VecBinaryOp::SMulEven16x8 => "vmeh",
2429
+ VecBinaryOp::SMulEven32x4 => "vmef",
2430
+ VecBinaryOp::UMulOdd8x16 => "vmlob",
2431
+ VecBinaryOp::UMulOdd16x8 => "vmloh",
2432
+ VecBinaryOp::UMulOdd32x4 => "vmlof",
2433
+ VecBinaryOp::SMulOdd8x16 => "vmob",
2434
+ VecBinaryOp::SMulOdd16x8 => "vmoh",
2435
+ VecBinaryOp::SMulOdd32x4 => "vmof",
2436
+ VecBinaryOp::UMax8x16 => "vmxlb",
2437
+ VecBinaryOp::UMax16x8 => "vmxlh",
2438
+ VecBinaryOp::UMax32x4 => "vmxlf",
2439
+ VecBinaryOp::UMax64x2 => "vmxlg",
2440
+ VecBinaryOp::SMax8x16 => "vmxb",
2441
+ VecBinaryOp::SMax16x8 => "vmxh",
2442
+ VecBinaryOp::SMax32x4 => "vmxf",
2443
+ VecBinaryOp::SMax64x2 => "vmxg",
2444
+ VecBinaryOp::UMin8x16 => "vmnlb",
2445
+ VecBinaryOp::UMin16x8 => "vmnlh",
2446
+ VecBinaryOp::UMin32x4 => "vmnlf",
2447
+ VecBinaryOp::UMin64x2 => "vmnlg",
2448
+ VecBinaryOp::SMin8x16 => "vmnb",
2449
+ VecBinaryOp::SMin16x8 => "vmnh",
2450
+ VecBinaryOp::SMin32x4 => "vmnf",
2451
+ VecBinaryOp::SMin64x2 => "vmng",
2452
+ VecBinaryOp::UAvg8x16 => "vavglb",
2453
+ VecBinaryOp::UAvg16x8 => "vavglh",
2454
+ VecBinaryOp::UAvg32x4 => "vavglf",
2455
+ VecBinaryOp::UAvg64x2 => "vavglg",
2456
+ VecBinaryOp::SAvg8x16 => "vavgb",
2457
+ VecBinaryOp::SAvg16x8 => "vavgh",
2458
+ VecBinaryOp::SAvg32x4 => "vavgf",
2459
+ VecBinaryOp::SAvg64x2 => "vavgg",
2460
+ VecBinaryOp::And128 => "vn",
2461
+ VecBinaryOp::Orr128 => "vo",
2462
+ VecBinaryOp::Xor128 => "vx",
2463
+ VecBinaryOp::NotAnd128 => "vnn",
2464
+ VecBinaryOp::NotOrr128 => "vno",
2465
+ VecBinaryOp::NotXor128 => "vnx",
2466
+ VecBinaryOp::AndNot128 => "vnc",
2467
+ VecBinaryOp::OrrNot128 => "voc",
2468
+ VecBinaryOp::BitPermute128 => "vbperm",
2469
+ VecBinaryOp::LShLByByte128 => "vslb",
2470
+ VecBinaryOp::LShRByByte128 => "vsrlb",
2471
+ VecBinaryOp::AShRByByte128 => "vsrab",
2472
+ VecBinaryOp::LShLByBit128 => "vsl",
2473
+ VecBinaryOp::LShRByBit128 => "vsrl",
2474
+ VecBinaryOp::AShRByBit128 => "vsra",
2475
+ VecBinaryOp::Pack16x8 => "vpkh",
2476
+ VecBinaryOp::Pack32x4 => "vpkf",
2477
+ VecBinaryOp::Pack64x2 => "vpkg",
2478
+ VecBinaryOp::PackUSat16x8 => "vpklsh",
2479
+ VecBinaryOp::PackUSat32x4 => "vpklsf",
2480
+ VecBinaryOp::PackUSat64x2 => "vpklsg",
2481
+ VecBinaryOp::PackSSat16x8 => "vpksh",
2482
+ VecBinaryOp::PackSSat32x4 => "vpksf",
2483
+ VecBinaryOp::PackSSat64x2 => "vpksg",
2484
+ VecBinaryOp::MergeLow8x16 => "vmrlb",
2485
+ VecBinaryOp::MergeLow16x8 => "vmrlh",
2486
+ VecBinaryOp::MergeLow32x4 => "vmrlf",
2487
+ VecBinaryOp::MergeLow64x2 => "vmrlg",
2488
+ VecBinaryOp::MergeHigh8x16 => "vmrhb",
2489
+ VecBinaryOp::MergeHigh16x8 => "vmrhh",
2490
+ VecBinaryOp::MergeHigh32x4 => "vmrhf",
2491
+ VecBinaryOp::MergeHigh64x2 => "vmrhg",
2492
+ };
2493
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2494
+ let rn = pretty_print_reg(rn, allocs);
2495
+ let rm = pretty_print_reg(rm, allocs);
2496
+ format!("{} {}, {}, {}", op, rd, rn, rm)
2497
+ }
2498
+ &Inst::VecRR { op, rd, rn } => {
2499
+ let op = match op {
2500
+ VecUnaryOp::Abs8x16 => "vlpb",
2501
+ VecUnaryOp::Abs16x8 => "vlph",
2502
+ VecUnaryOp::Abs32x4 => "vlpf",
2503
+ VecUnaryOp::Abs64x2 => "vlpg",
2504
+ VecUnaryOp::Neg8x16 => "vlcb",
2505
+ VecUnaryOp::Neg16x8 => "vlch",
2506
+ VecUnaryOp::Neg32x4 => "vlcf",
2507
+ VecUnaryOp::Neg64x2 => "vlcg",
2508
+ VecUnaryOp::Popcnt8x16 => "vpopctb",
2509
+ VecUnaryOp::Popcnt16x8 => "vpopcth",
2510
+ VecUnaryOp::Popcnt32x4 => "vpopctf",
2511
+ VecUnaryOp::Popcnt64x2 => "vpopctg",
2512
+ VecUnaryOp::Clz8x16 => "vclzb",
2513
+ VecUnaryOp::Clz16x8 => "vclzh",
2514
+ VecUnaryOp::Clz32x4 => "vclzf",
2515
+ VecUnaryOp::Clz64x2 => "vclzg",
2516
+ VecUnaryOp::Ctz8x16 => "vctzb",
2517
+ VecUnaryOp::Ctz16x8 => "vctzh",
2518
+ VecUnaryOp::Ctz32x4 => "vctzf",
2519
+ VecUnaryOp::Ctz64x2 => "vctzg",
2520
+ VecUnaryOp::UnpackULow8x16 => "vupllb",
2521
+ VecUnaryOp::UnpackULow16x8 => "vupllh",
2522
+ VecUnaryOp::UnpackULow32x4 => "vupllf",
2523
+ VecUnaryOp::UnpackUHigh8x16 => "vuplhb",
2524
+ VecUnaryOp::UnpackUHigh16x8 => "vuplhh",
2525
+ VecUnaryOp::UnpackUHigh32x4 => "vuplhf",
2526
+ VecUnaryOp::UnpackSLow8x16 => "vuplb",
2527
+ VecUnaryOp::UnpackSLow16x8 => "vuplh",
2528
+ VecUnaryOp::UnpackSLow32x4 => "vuplf",
2529
+ VecUnaryOp::UnpackSHigh8x16 => "vuphb",
2530
+ VecUnaryOp::UnpackSHigh16x8 => "vuphh",
2531
+ VecUnaryOp::UnpackSHigh32x4 => "vuphf",
2532
+ };
2533
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2534
+ let rn = pretty_print_reg(rn, allocs);
2535
+ format!("{} {}, {}", op, rd, rn)
2536
+ }
2537
+ &Inst::VecShiftRR {
2538
+ shift_op,
2539
+ rd,
2540
+ rn,
2541
+ shift_imm,
2542
+ shift_reg,
2543
+ } => {
2544
+ let op = match shift_op {
2545
+ VecShiftOp::RotL8x16 => "verllb",
2546
+ VecShiftOp::RotL16x8 => "verllh",
2547
+ VecShiftOp::RotL32x4 => "verllf",
2548
+ VecShiftOp::RotL64x2 => "verllg",
2549
+ VecShiftOp::LShL8x16 => "veslb",
2550
+ VecShiftOp::LShL16x8 => "veslh",
2551
+ VecShiftOp::LShL32x4 => "veslf",
2552
+ VecShiftOp::LShL64x2 => "veslg",
2553
+ VecShiftOp::LShR8x16 => "vesrlb",
2554
+ VecShiftOp::LShR16x8 => "vesrlh",
2555
+ VecShiftOp::LShR32x4 => "vesrlf",
2556
+ VecShiftOp::LShR64x2 => "vesrlg",
2557
+ VecShiftOp::AShR8x16 => "vesrab",
2558
+ VecShiftOp::AShR16x8 => "vesrah",
2559
+ VecShiftOp::AShR32x4 => "vesraf",
2560
+ VecShiftOp::AShR64x2 => "vesrag",
2561
+ };
2562
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2563
+ let rn = pretty_print_reg(rn, allocs);
2564
+ let shift_reg = if shift_reg != zero_reg() {
2565
+ format!("({})", pretty_print_reg(shift_reg, allocs))
2566
+ } else {
2567
+ "".to_string()
2568
+ };
2569
+ format!("{} {}, {}, {}{}", op, rd, rn, shift_imm, shift_reg)
2570
+ }
2571
+ &Inst::VecSelect { rd, rn, rm, ra } => {
2572
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2573
+ let rn = pretty_print_reg(rn, allocs);
2574
+ let rm = pretty_print_reg(rm, allocs);
2575
+ let ra = pretty_print_reg(ra, allocs);
2576
+ format!("vsel {}, {}, {}, {}", rd, rn, rm, ra)
2577
+ }
2578
+ &Inst::VecPermute { rd, rn, rm, ra } => {
2579
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2580
+ let rn = pretty_print_reg(rn, allocs);
2581
+ let rm = pretty_print_reg(rm, allocs);
2582
+ let ra = pretty_print_reg(ra, allocs);
2583
+ format!("vperm {}, {}, {}, {}", rd, rn, rm, ra)
2584
+ }
2585
+ &Inst::VecPermuteDWImm {
2586
+ rd,
2587
+ rn,
2588
+ rm,
2589
+ idx1,
2590
+ idx2,
2591
+ } => {
2592
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2593
+ let rn = pretty_print_reg(rn, allocs);
2594
+ let rm = pretty_print_reg(rm, allocs);
2595
+ let m4 = (idx1 & 1) * 4 + (idx2 & 1);
2596
+ format!("vpdi {}, {}, {}, {}", rd, rn, rm, m4)
2597
+ }
2598
+ &Inst::VecIntCmp { op, rd, rn, rm } | &Inst::VecIntCmpS { op, rd, rn, rm } => {
2599
+ let op = match op {
2600
+ VecIntCmpOp::CmpEq8x16 => "vceqb",
2601
+ VecIntCmpOp::CmpEq16x8 => "vceqh",
2602
+ VecIntCmpOp::CmpEq32x4 => "vceqf",
2603
+ VecIntCmpOp::CmpEq64x2 => "vceqg",
2604
+ VecIntCmpOp::SCmpHi8x16 => "vchb",
2605
+ VecIntCmpOp::SCmpHi16x8 => "vchh",
2606
+ VecIntCmpOp::SCmpHi32x4 => "vchf",
2607
+ VecIntCmpOp::SCmpHi64x2 => "vchg",
2608
+ VecIntCmpOp::UCmpHi8x16 => "vchlb",
2609
+ VecIntCmpOp::UCmpHi16x8 => "vchlh",
2610
+ VecIntCmpOp::UCmpHi32x4 => "vchlf",
2611
+ VecIntCmpOp::UCmpHi64x2 => "vchlg",
2612
+ };
2613
+ let s = match self {
2614
+ &Inst::VecIntCmp { .. } => "",
2615
+ &Inst::VecIntCmpS { .. } => "s",
2616
+ _ => unreachable!(),
2617
+ };
2618
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2619
+ let rn = pretty_print_reg(rn, allocs);
2620
+ let rm = pretty_print_reg(rm, allocs);
2621
+ format!("{}{} {}, {}, {}", op, s, rd, rn, rm)
2622
+ }
2623
+ &Inst::VecFloatCmp { op, rd, rn, rm } | &Inst::VecFloatCmpS { op, rd, rn, rm } => {
2624
+ let op = match op {
2625
+ VecFloatCmpOp::CmpEq32x4 => "vfcesb",
2626
+ VecFloatCmpOp::CmpEq64x2 => "vfcedb",
2627
+ VecFloatCmpOp::CmpHi32x4 => "vfchsb",
2628
+ VecFloatCmpOp::CmpHi64x2 => "vfchdb",
2629
+ VecFloatCmpOp::CmpHiEq32x4 => "vfchesb",
2630
+ VecFloatCmpOp::CmpHiEq64x2 => "vfchedb",
2631
+ };
2632
+ let s = match self {
2633
+ &Inst::VecFloatCmp { .. } => "",
2634
+ &Inst::VecFloatCmpS { .. } => "s",
2635
+ _ => unreachable!(),
2636
+ };
2637
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2638
+ let rn = pretty_print_reg(rn, allocs);
2639
+ let rm = pretty_print_reg(rm, allocs);
2640
+ format!("{}{} {}, {}, {}", op, s, rd, rn, rm)
2641
+ }
2642
+ &Inst::VecInt128SCmpHi { tmp, rn, rm } | &Inst::VecInt128UCmpHi { tmp, rn, rm } => {
2643
+ let op = match self {
2644
+ &Inst::VecInt128SCmpHi { .. } => "vecg",
2645
+ &Inst::VecInt128UCmpHi { .. } => "veclg",
2646
+ _ => unreachable!(),
2647
+ };
2648
+ let tmp = pretty_print_reg(tmp.to_reg(), allocs);
2649
+ let rn = pretty_print_reg(rn, allocs);
2650
+ let rm = pretty_print_reg(rm, allocs);
2651
+ format!(
2652
+ "{} {}, {} ; jne 10 ; vchlgs {}, {}, {}",
2653
+ op, rm, rn, tmp, rn, rm
2654
+ )
2655
+ }
2656
+ &Inst::VecLoad { rd, ref mem }
2657
+ | &Inst::VecLoadRev { rd, ref mem }
2658
+ | &Inst::VecLoadByte16Rev { rd, ref mem }
2659
+ | &Inst::VecLoadByte32Rev { rd, ref mem }
2660
+ | &Inst::VecLoadByte64Rev { rd, ref mem }
2661
+ | &Inst::VecLoadElt16Rev { rd, ref mem }
2662
+ | &Inst::VecLoadElt32Rev { rd, ref mem }
2663
+ | &Inst::VecLoadElt64Rev { rd, ref mem } => {
2664
+ let opcode = match self {
2665
+ &Inst::VecLoad { .. } => "vl",
2666
+ &Inst::VecLoadRev { .. } => "vlbrq",
2667
+ &Inst::VecLoadByte16Rev { .. } => "vlbrh",
2668
+ &Inst::VecLoadByte32Rev { .. } => "vlbrf",
2669
+ &Inst::VecLoadByte64Rev { .. } => "vlbrg",
2670
+ &Inst::VecLoadElt16Rev { .. } => "vlerh",
2671
+ &Inst::VecLoadElt32Rev { .. } => "vlerf",
2672
+ &Inst::VecLoadElt64Rev { .. } => "vlerg",
2673
+ _ => unreachable!(),
2674
+ };
2675
+
2676
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2677
+ let mem = mem.with_allocs(allocs);
2678
+ let (mem_str, mem) = mem_finalize_for_show(
2679
+ &mem,
2680
+ state,
2681
+ MemInstType {
2682
+ have_d12: true,
2683
+ have_d20: false,
2684
+ have_pcrel: false,
2685
+ have_unaligned_pcrel: false,
2686
+ have_index: true,
2687
+ },
2688
+ );
2689
+ let mem = mem.pretty_print_default();
2690
+ format!("{}{} {}, {}", mem_str, opcode, rd, mem)
2691
+ }
2692
+ &Inst::VecStore { rd, ref mem }
2693
+ | &Inst::VecStoreRev { rd, ref mem }
2694
+ | &Inst::VecStoreByte16Rev { rd, ref mem }
2695
+ | &Inst::VecStoreByte32Rev { rd, ref mem }
2696
+ | &Inst::VecStoreByte64Rev { rd, ref mem }
2697
+ | &Inst::VecStoreElt16Rev { rd, ref mem }
2698
+ | &Inst::VecStoreElt32Rev { rd, ref mem }
2699
+ | &Inst::VecStoreElt64Rev { rd, ref mem } => {
2700
+ let opcode = match self {
2701
+ &Inst::VecStore { .. } => "vst",
2702
+ &Inst::VecStoreRev { .. } => "vstbrq",
2703
+ &Inst::VecStoreByte16Rev { .. } => "vstbrh",
2704
+ &Inst::VecStoreByte32Rev { .. } => "vstbrf",
2705
+ &Inst::VecStoreByte64Rev { .. } => "vstbrg",
2706
+ &Inst::VecStoreElt16Rev { .. } => "vsterh",
2707
+ &Inst::VecStoreElt32Rev { .. } => "vsterf",
2708
+ &Inst::VecStoreElt64Rev { .. } => "vsterg",
2709
+ _ => unreachable!(),
2710
+ };
2711
+
2712
+ let rd = pretty_print_reg(rd, allocs);
2713
+ let mem = mem.with_allocs(allocs);
2714
+ let (mem_str, mem) = mem_finalize_for_show(
2715
+ &mem,
2716
+ state,
2717
+ MemInstType {
2718
+ have_d12: true,
2719
+ have_d20: false,
2720
+ have_pcrel: false,
2721
+ have_unaligned_pcrel: false,
2722
+ have_index: true,
2723
+ },
2724
+ );
2725
+ let mem = mem.pretty_print_default();
2726
+ format!("{}{} {}, {}", mem_str, opcode, rd, mem)
2727
+ }
2728
+ &Inst::VecLoadReplicate { size, rd, ref mem }
2729
+ | &Inst::VecLoadReplicateRev { size, rd, ref mem } => {
2730
+ let opcode = match (self, size) {
2731
+ (&Inst::VecLoadReplicate { .. }, 8) => "vlrepb",
2732
+ (&Inst::VecLoadReplicate { .. }, 16) => "vlreph",
2733
+ (&Inst::VecLoadReplicate { .. }, 32) => "vlrepf",
2734
+ (&Inst::VecLoadReplicate { .. }, 64) => "vlrepg",
2735
+ (&Inst::VecLoadReplicateRev { .. }, 16) => "vlbrreph",
2736
+ (&Inst::VecLoadReplicateRev { .. }, 32) => "vlbrrepf",
2737
+ (&Inst::VecLoadReplicateRev { .. }, 64) => "vlbrrepg",
2738
+ _ => unreachable!(),
2739
+ };
2740
+
2741
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2742
+ let mem = mem.with_allocs(allocs);
2743
+ let (mem_str, mem) = mem_finalize_for_show(
2744
+ &mem,
2745
+ state,
2746
+ MemInstType {
2747
+ have_d12: true,
2748
+ have_d20: false,
2749
+ have_pcrel: false,
2750
+ have_unaligned_pcrel: false,
2751
+ have_index: true,
2752
+ },
2753
+ );
2754
+ let mem = mem.pretty_print_default();
2755
+ format!("{}{} {}, {}", mem_str, opcode, rd, mem)
2756
+ }
2757
+ &Inst::VecMov { rd, rn } => {
2758
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2759
+ let rn = pretty_print_reg(rn, allocs);
2760
+ format!("vlr {}, {}", rd, rn)
2761
+ }
2762
+ &Inst::VecCMov { rd, cond, ri, rm } => {
2763
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
2764
+ let rm = pretty_print_reg(rm, allocs);
2765
+ let cond = cond.invert().pretty_print_default();
2766
+ format!("j{} 10 ; vlr {}, {}", cond, rd, rm)
2767
+ }
2768
+ &Inst::MovToVec128 { rd, rn, rm } => {
2769
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2770
+ let rn = pretty_print_reg(rn, allocs);
2771
+ let rm = pretty_print_reg(rm, allocs);
2772
+ format!("vlvgp {}, {}, {}", rd, rn, rm)
2773
+ }
2774
+ &Inst::VecLoadConst { rd, const_data } => {
2775
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2776
+ let tmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
2777
+ format!(
2778
+ "bras {}, 20 ; data.u128 0x{:032x} ; vl {}, 0({})",
2779
+ tmp, const_data, rd, tmp
2780
+ )
2781
+ }
2782
+ &Inst::VecLoadConstReplicate {
2783
+ size,
2784
+ rd,
2785
+ const_data,
2786
+ } => {
2787
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2788
+ let tmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
2789
+ let (opcode, data) = match size {
2790
+ 32 => ("vlrepf", format!("0x{:08x}", const_data as u32)),
2791
+ 64 => ("vlrepg", format!("0x{:016x}", const_data)),
2792
+ _ => unreachable!(),
2793
+ };
2794
+ format!(
2795
+ "bras {}, {} ; data.u{} {} ; {} {}, 0({})",
2796
+ tmp,
2797
+ 4 + size / 8,
2798
+ size,
2799
+ data,
2800
+ opcode,
2801
+ rd,
2802
+ tmp
2803
+ )
2804
+ }
2805
+ &Inst::VecImmByteMask { rd, mask } => {
2806
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2807
+ format!("vgbm {}, {}", rd, mask)
2808
+ }
2809
+ &Inst::VecImmBitMask {
2810
+ size,
2811
+ rd,
2812
+ start_bit,
2813
+ end_bit,
2814
+ } => {
2815
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2816
+ let op = match size {
2817
+ 8 => "vgmb",
2818
+ 16 => "vgmh",
2819
+ 32 => "vgmf",
2820
+ 64 => "vgmg",
2821
+ _ => unreachable!(),
2822
+ };
2823
+ format!("{} {}, {}, {}", op, rd, start_bit, end_bit)
2824
+ }
2825
+ &Inst::VecImmReplicate { size, rd, imm } => {
2826
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
2827
+ let op = match size {
2828
+ 8 => "vrepib",
2829
+ 16 => "vrepih",
2830
+ 32 => "vrepif",
2831
+ 64 => "vrepig",
2832
+ _ => unreachable!(),
2833
+ };
2834
+ format!("{} {}, {}", op, rd, imm)
2835
+ }
2836
+ &Inst::VecLoadLane {
2837
+ size,
2838
+ rd,
2839
+ ri,
2840
+ ref mem,
2841
+ lane_imm,
2842
+ }
2843
+ | &Inst::VecLoadLaneRev {
2844
+ size,
2845
+ rd,
2846
+ ri,
2847
+ ref mem,
2848
+ lane_imm,
2849
+ } => {
2850
+ let opcode_vrx = match (self, size) {
2851
+ (&Inst::VecLoadLane { .. }, 8) => "vleb",
2852
+ (&Inst::VecLoadLane { .. }, 16) => "vleh",
2853
+ (&Inst::VecLoadLane { .. }, 32) => "vlef",
2854
+ (&Inst::VecLoadLane { .. }, 64) => "vleg",
2855
+ (&Inst::VecLoadLaneRev { .. }, 16) => "vlebrh",
2856
+ (&Inst::VecLoadLaneRev { .. }, 32) => "vlebrf",
2857
+ (&Inst::VecLoadLaneRev { .. }, 64) => "vlebrg",
2858
+ _ => unreachable!(),
2859
+ };
2860
+
2861
+ let (rd, _) = pretty_print_fpr(rd.to_reg(), allocs);
2862
+ let _ri = allocs.next(ri);
2863
+ let mem = mem.with_allocs(allocs);
2864
+ let (mem_str, mem) = mem_finalize_for_show(
2865
+ &mem,
2866
+ state,
2867
+ MemInstType {
2868
+ have_d12: true,
2869
+ have_d20: false,
2870
+ have_pcrel: false,
2871
+ have_unaligned_pcrel: false,
2872
+ have_index: true,
2873
+ },
2874
+ );
2875
+ let mem = mem.pretty_print_default();
2876
+ format!("{}{} {}, {}, {}", mem_str, opcode_vrx, rd, mem, lane_imm)
2877
+ }
2878
+ &Inst::VecLoadLaneUndef {
2879
+ size,
2880
+ rd,
2881
+ ref mem,
2882
+ lane_imm,
2883
+ }
2884
+ | &Inst::VecLoadLaneRevUndef {
2885
+ size,
2886
+ rd,
2887
+ ref mem,
2888
+ lane_imm,
2889
+ } => {
2890
+ let (opcode_vrx, opcode_rx, opcode_rxy) = match (self, size) {
2891
+ (&Inst::VecLoadLaneUndef { .. }, 8) => ("vleb", None, None),
2892
+ (&Inst::VecLoadLaneUndef { .. }, 16) => ("vleh", None, None),
2893
+ (&Inst::VecLoadLaneUndef { .. }, 32) => ("vlef", Some("le"), Some("ley")),
2894
+ (&Inst::VecLoadLaneUndef { .. }, 64) => ("vleg", Some("ld"), Some("ldy")),
2895
+ (&Inst::VecLoadLaneRevUndef { .. }, 16) => ("vlebrh", None, None),
2896
+ (&Inst::VecLoadLaneRevUndef { .. }, 32) => ("vlebrf", None, None),
2897
+ (&Inst::VecLoadLaneRevUndef { .. }, 64) => ("vlebrg", None, None),
2898
+ _ => unreachable!(),
2899
+ };
2900
+
2901
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
2902
+ let mem = mem.with_allocs(allocs);
2903
+ if lane_imm == 0 && rd_fpr.is_some() && opcode_rx.is_some() {
2904
+ let (mem_str, mem) = mem_finalize_for_show(
2905
+ &mem,
2906
+ state,
2907
+ MemInstType {
2908
+ have_d12: true,
2909
+ have_d20: true,
2910
+ have_pcrel: false,
2911
+ have_unaligned_pcrel: false,
2912
+ have_index: true,
2913
+ },
2914
+ );
2915
+ let op = match &mem {
2916
+ &MemArg::BXD12 { .. } => opcode_rx,
2917
+ &MemArg::BXD20 { .. } => opcode_rxy,
2918
+ _ => unreachable!(),
2919
+ };
2920
+ let mem = mem.pretty_print_default();
2921
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rd_fpr.unwrap(), mem)
2922
+ } else {
2923
+ let (mem_str, mem) = mem_finalize_for_show(
2924
+ &mem,
2925
+ state,
2926
+ MemInstType {
2927
+ have_d12: true,
2928
+ have_d20: false,
2929
+ have_pcrel: false,
2930
+ have_unaligned_pcrel: false,
2931
+ have_index: true,
2932
+ },
2933
+ );
2934
+ let mem = mem.pretty_print_default();
2935
+ format!("{}{} {}, {}, {}", mem_str, opcode_vrx, rd, mem, lane_imm)
2936
+ }
2937
+ }
2938
+ &Inst::VecStoreLane {
2939
+ size,
2940
+ rd,
2941
+ ref mem,
2942
+ lane_imm,
2943
+ }
2944
+ | &Inst::VecStoreLaneRev {
2945
+ size,
2946
+ rd,
2947
+ ref mem,
2948
+ lane_imm,
2949
+ } => {
2950
+ let (opcode_vrx, opcode_rx, opcode_rxy) = match (self, size) {
2951
+ (&Inst::VecStoreLane { .. }, 8) => ("vsteb", None, None),
2952
+ (&Inst::VecStoreLane { .. }, 16) => ("vsteh", None, None),
2953
+ (&Inst::VecStoreLane { .. }, 32) => ("vstef", Some("ste"), Some("stey")),
2954
+ (&Inst::VecStoreLane { .. }, 64) => ("vsteg", Some("std"), Some("stdy")),
2955
+ (&Inst::VecStoreLaneRev { .. }, 16) => ("vstebrh", None, None),
2956
+ (&Inst::VecStoreLaneRev { .. }, 32) => ("vstebrf", None, None),
2957
+ (&Inst::VecStoreLaneRev { .. }, 64) => ("vstebrg", None, None),
2958
+ _ => unreachable!(),
2959
+ };
2960
+
2961
+ let (rd, rd_fpr) = pretty_print_fpr(rd, allocs);
2962
+ let mem = mem.with_allocs(allocs);
2963
+ if lane_imm == 0 && rd_fpr.is_some() && opcode_rx.is_some() {
2964
+ let (mem_str, mem) = mem_finalize_for_show(
2965
+ &mem,
2966
+ state,
2967
+ MemInstType {
2968
+ have_d12: true,
2969
+ have_d20: true,
2970
+ have_pcrel: false,
2971
+ have_unaligned_pcrel: false,
2972
+ have_index: true,
2973
+ },
2974
+ );
2975
+ let op = match &mem {
2976
+ &MemArg::BXD12 { .. } => opcode_rx,
2977
+ &MemArg::BXD20 { .. } => opcode_rxy,
2978
+ _ => unreachable!(),
2979
+ };
2980
+ let mem = mem.pretty_print_default();
2981
+ format!("{}{} {}, {}", mem_str, op.unwrap(), rd_fpr.unwrap(), mem)
2982
+ } else {
2983
+ let (mem_str, mem) = mem_finalize_for_show(
2984
+ &mem,
2985
+ state,
2986
+ MemInstType {
2987
+ have_d12: true,
2988
+ have_d20: false,
2989
+ have_pcrel: false,
2990
+ have_unaligned_pcrel: false,
2991
+ have_index: true,
2992
+ },
2993
+ );
2994
+ let mem = mem.pretty_print_default();
2995
+ format!("{}{} {}, {}, {}", mem_str, opcode_vrx, rd, mem, lane_imm,)
2996
+ }
2997
+ }
2998
+ &Inst::VecInsertLane {
2999
+ size,
3000
+ rd,
3001
+ ri,
3002
+ rn,
3003
+ lane_imm,
3004
+ lane_reg,
3005
+ } => {
3006
+ let op = match size {
3007
+ 8 => "vlvgb",
3008
+ 16 => "vlvgh",
3009
+ 32 => "vlvgf",
3010
+ 64 => "vlvgg",
3011
+ _ => unreachable!(),
3012
+ };
3013
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
3014
+ let rn = pretty_print_reg(rn, allocs);
3015
+ let lane_reg = if lane_reg != zero_reg() {
3016
+ format!("({})", pretty_print_reg(lane_reg, allocs))
3017
+ } else {
3018
+ "".to_string()
3019
+ };
3020
+ format!("{} {}, {}, {}{}", op, rd, rn, lane_imm, lane_reg)
3021
+ }
3022
+ &Inst::VecInsertLaneUndef {
3023
+ size,
3024
+ rd,
3025
+ rn,
3026
+ lane_imm,
3027
+ lane_reg,
3028
+ } => {
3029
+ let (opcode_vrs, opcode_rre) = match size {
3030
+ 8 => ("vlvgb", None),
3031
+ 16 => ("vlvgh", None),
3032
+ 32 => ("vlvgf", None),
3033
+ 64 => ("vlvgg", Some("ldgr")),
3034
+ _ => unreachable!(),
3035
+ };
3036
+ let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
3037
+ let rn = pretty_print_reg(rn, allocs);
3038
+ let lane_reg = if lane_reg != zero_reg() {
3039
+ format!("({})", pretty_print_reg(lane_reg, allocs))
3040
+ } else {
3041
+ "".to_string()
3042
+ };
3043
+ if opcode_rre.is_some() && lane_imm == 0 && lane_reg.is_empty() && rd_fpr.is_some()
3044
+ {
3045
+ format!("{} {}, {}", opcode_rre.unwrap(), rd_fpr.unwrap(), rn)
3046
+ } else {
3047
+ format!("{} {}, {}, {}{}", opcode_vrs, rd, rn, lane_imm, lane_reg)
3048
+ }
3049
+ }
3050
+ &Inst::VecExtractLane {
3051
+ size,
3052
+ rd,
3053
+ rn,
3054
+ lane_imm,
3055
+ lane_reg,
3056
+ } => {
3057
+ let (opcode_vrs, opcode_rre) = match size {
3058
+ 8 => ("vlgvb", None),
3059
+ 16 => ("vlgvh", None),
3060
+ 32 => ("vlgvf", None),
3061
+ 64 => ("vlgvg", Some("lgdr")),
3062
+ _ => unreachable!(),
3063
+ };
3064
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
3065
+ let (rn, rn_fpr) = pretty_print_fpr(rn, allocs);
3066
+ let lane_reg = if lane_reg != zero_reg() {
3067
+ format!("({})", pretty_print_reg(lane_reg, allocs))
3068
+ } else {
3069
+ "".to_string()
3070
+ };
3071
+ if opcode_rre.is_some() && lane_imm == 0 && lane_reg.is_empty() && rn_fpr.is_some()
3072
+ {
3073
+ format!("{} {}, {}", opcode_rre.unwrap(), rd, rn_fpr.unwrap())
3074
+ } else {
3075
+ format!("{} {}, {}, {}{}", opcode_vrs, rd, rn, lane_imm, lane_reg)
3076
+ }
3077
+ }
3078
+ &Inst::VecInsertLaneImm {
3079
+ size,
3080
+ rd,
3081
+ ri,
3082
+ imm,
3083
+ lane_imm,
3084
+ } => {
3085
+ let op = match size {
3086
+ 8 => "vleib",
3087
+ 16 => "vleih",
3088
+ 32 => "vleif",
3089
+ 64 => "vleig",
3090
+ _ => unreachable!(),
3091
+ };
3092
+ let rd = pretty_print_reg_mod(rd, ri, allocs);
3093
+ format!("{} {}, {}, {}", op, rd, imm, lane_imm)
3094
+ }
3095
+ &Inst::VecReplicateLane {
3096
+ size,
3097
+ rd,
3098
+ rn,
3099
+ lane_imm,
3100
+ } => {
3101
+ let op = match size {
3102
+ 8 => "vrepb",
3103
+ 16 => "vreph",
3104
+ 32 => "vrepf",
3105
+ 64 => "vrepg",
3106
+ _ => unreachable!(),
3107
+ };
3108
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
3109
+ let rn = pretty_print_reg(rn, allocs);
3110
+ format!("{} {}, {}, {}", op, rd, rn, lane_imm)
3111
+ }
3112
+ &Inst::Extend {
3113
+ rd,
3114
+ rn,
3115
+ signed,
3116
+ from_bits,
3117
+ to_bits,
3118
+ } => {
3119
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
3120
+ let rn = pretty_print_reg(rn, allocs);
3121
+ let op = match (signed, from_bits, to_bits) {
3122
+ (_, 1, 32) => "llcr",
3123
+ (_, 1, 64) => "llgcr",
3124
+ (false, 8, 32) => "llcr",
3125
+ (false, 8, 64) => "llgcr",
3126
+ (true, 8, 32) => "lbr",
3127
+ (true, 8, 64) => "lgbr",
3128
+ (false, 16, 32) => "llhr",
3129
+ (false, 16, 64) => "llghr",
3130
+ (true, 16, 32) => "lhr",
3131
+ (true, 16, 64) => "lghr",
3132
+ (false, 32, 64) => "llgfr",
3133
+ (true, 32, 64) => "lgfr",
3134
+ _ => panic!("Unsupported Extend case: {:?}", self),
3135
+ };
3136
+ format!("{} {}, {}", op, rd, rn)
3137
+ }
3138
+ &Inst::Call { link, ref info, .. } => {
3139
+ let link = link.to_reg();
3140
+ let tls_symbol = match &info.tls_symbol {
3141
+ None => "".to_string(),
3142
+ Some(SymbolReloc::TlsGd { name }) => {
3143
+ format!(":tls_gdcall:{}", name.display(None))
3144
+ }
3145
+ _ => unreachable!(),
3146
+ };
3147
+ debug_assert_eq!(link, gpr(14));
3148
+ format!(
3149
+ "brasl {}, {}{}",
3150
+ show_reg(link),
3151
+ info.dest.display(None),
3152
+ tls_symbol
3153
+ )
3154
+ }
3155
+ &Inst::CallInd { link, ref info, .. } => {
3156
+ let link = link.to_reg();
3157
+ let rn = pretty_print_reg(info.rn, allocs);
3158
+ debug_assert_eq!(link, gpr(14));
3159
+ format!("basr {}, {}", show_reg(link), rn)
3160
+ }
3161
+ &Inst::Args { ref args } => {
3162
+ let mut s = "args".to_string();
3163
+ for arg in args {
3164
+ let preg = pretty_print_reg(arg.preg, &mut empty_allocs);
3165
+ let def = pretty_print_reg(arg.vreg.to_reg(), allocs);
3166
+ write!(&mut s, " {}={}", def, preg).unwrap();
3167
+ }
3168
+ s
3169
+ }
3170
+ &Inst::Ret {
3171
+ link,
3172
+ ref rets,
3173
+ stack_bytes_to_pop,
3174
+ } => {
3175
+ debug_assert_eq!(link, gpr(14));
3176
+ let link = show_reg(link);
3177
+ let mut s = if stack_bytes_to_pop == 0 {
3178
+ format!("br {link}")
3179
+ } else {
3180
+ let stack_reg = show_reg(stack_reg());
3181
+ format!("aghi {stack_reg}, {stack_bytes_to_pop} ; br {link}")
3182
+ };
3183
+ for ret in rets {
3184
+ let preg = pretty_print_reg(ret.preg, &mut empty_allocs);
3185
+ let vreg = pretty_print_reg(ret.vreg, allocs);
3186
+ write!(&mut s, " {}={}", vreg, preg).unwrap();
3187
+ }
3188
+ s
3189
+ }
3190
+ &Inst::Jump { dest } => {
3191
+ let dest = dest.to_string();
3192
+ format!("jg {}", dest)
3193
+ }
3194
+ &Inst::IndirectBr { rn, .. } => {
3195
+ let rn = pretty_print_reg(rn, allocs);
3196
+ format!("br {}", rn)
3197
+ }
3198
+ &Inst::CondBr {
3199
+ taken,
3200
+ not_taken,
3201
+ cond,
3202
+ } => {
3203
+ let taken = taken.to_string();
3204
+ let not_taken = not_taken.to_string();
3205
+ let cond = cond.pretty_print_default();
3206
+ format!("jg{} {} ; jg {}", cond, taken, not_taken)
3207
+ }
3208
+ &Inst::OneWayCondBr { target, cond } => {
3209
+ let target = target.to_string();
3210
+ let cond = cond.pretty_print_default();
3211
+ format!("jg{} {}", cond, target)
3212
+ }
3213
+ &Inst::Debugtrap => ".word 0x0001 # debugtrap".to_string(),
3214
+ &Inst::Trap { trap_code } => {
3215
+ format!(".word 0x0000 # trap={}", trap_code)
3216
+ }
3217
+ &Inst::TrapIf { cond, trap_code } => {
3218
+ let cond = cond.pretty_print_default();
3219
+ format!("jg{} .+2 # trap={}", cond, trap_code)
3220
+ }
3221
+ &Inst::JTSequence { ridx, ref targets } => {
3222
+ let ridx = pretty_print_reg(ridx, allocs);
3223
+ let rtmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
3224
+ // The first entry is the default target, which is not emitted
3225
+ // into the jump table, so we skip it here. It is only in the
3226
+ // list so MachTerminator will see the potential target.
3227
+ let jt_entries: String = targets
3228
+ .iter()
3229
+ .skip(1)
3230
+ .map(|label| format!(" {}", label.to_string()))
3231
+ .collect();
3232
+ format!(
3233
+ concat!(
3234
+ "larl {}, 14 ; ",
3235
+ "agf {}, 0({}, {}) ; ",
3236
+ "br {} ; ",
3237
+ "jt_entries{}"
3238
+ ),
3239
+ rtmp, rtmp, rtmp, ridx, rtmp, jt_entries,
3240
+ )
3241
+ }
3242
+ &Inst::LoadSymbolReloc {
3243
+ rd,
3244
+ ref symbol_reloc,
3245
+ } => {
3246
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
3247
+ let tmp = pretty_print_reg(writable_spilltmp_reg().to_reg(), &mut empty_allocs);
3248
+ let symbol = match &**symbol_reloc {
3249
+ SymbolReloc::Absolute { name, offset } => {
3250
+ format!("{} + {}", name.display(None), offset)
3251
+ }
3252
+ SymbolReloc::TlsGd { name } => format!("{}@tlsgd", name.display(None)),
3253
+ };
3254
+ format!("bras {}, 12 ; data {} ; lg {}, 0({})", tmp, symbol, rd, tmp)
3255
+ }
3256
+ &Inst::LoadAddr { rd, ref mem } => {
3257
+ let rd = pretty_print_reg(rd.to_reg(), allocs);
3258
+ let mem = mem.with_allocs(allocs);
3259
+ let (mem_str, mem) = mem_finalize_for_show(
3260
+ &mem,
3261
+ state,
3262
+ MemInstType {
3263
+ have_d12: true,
3264
+ have_d20: true,
3265
+ have_pcrel: true,
3266
+ have_unaligned_pcrel: true,
3267
+ have_index: true,
3268
+ },
3269
+ );
3270
+ let op = match &mem {
3271
+ &MemArg::BXD12 { .. } => "la",
3272
+ &MemArg::BXD20 { .. } => "lay",
3273
+ &MemArg::Label { .. } | &MemArg::Symbol { .. } => "larl",
3274
+ _ => unreachable!(),
3275
+ };
3276
+ let mem = mem.pretty_print_default();
3277
+
3278
+ format!("{}{} {}, {}", mem_str, op, rd, mem)
3279
+ }
3280
+ &Inst::Loop { ref body, cond } => {
3281
+ let body = body
3282
+ .into_iter()
3283
+ .map(|inst| inst.print_with_state(state, allocs))
3284
+ .collect::<Vec<_>>()
3285
+ .join(" ; ");
3286
+ let cond = cond.pretty_print_default();
3287
+ format!("0: {} ; jg{} 0b ; 1:", body, cond)
3288
+ }
3289
+ &Inst::CondBreak { cond } => {
3290
+ let cond = cond.pretty_print_default();
3291
+ format!("jg{} 1f", cond)
3292
+ }
3293
+ &Inst::VirtualSPOffsetAdj { offset } => {
3294
+ state.virtual_sp_offset += offset;
3295
+ format!("virtual_sp_offset_adjust {}", offset)
3296
+ }
3297
+ &Inst::Unwind { ref inst } => {
3298
+ format!("unwind {:?}", inst)
3299
+ }
3300
+ &Inst::DummyUse { reg } => {
3301
+ let reg = pretty_print_reg(reg, allocs);
3302
+ format!("dummy_use {}", reg)
3303
+ }
3304
+ }
3305
+ }
3306
+ }
3307
+
3308
+ //=============================================================================
3309
+ // Label fixups and jump veneers.
3310
+
3311
+ /// Different forms of label references for different instruction formats.
3312
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
3313
+ pub enum LabelUse {
3314
+ #[allow(dead_code)]
3315
+ /// RI-format branch. 16-bit signed offset. PC-relative, offset is imm << 1.
3316
+ BranchRI,
3317
+ /// RIL-format branch. 32-bit signed offset. PC-relative, offset is imm << 1.
3318
+ BranchRIL,
3319
+ /// 32-bit PC relative constant offset (from address of constant itself),
3320
+ /// signed. Used in jump tables.
3321
+ PCRel32,
3322
+ /// 32-bit PC relative constant offset (from address of call instruction),
3323
+ /// signed. Offset is imm << 1. Used for call relocations.
3324
+ PCRel32Dbl,
3325
+ }
3326
+
3327
+ impl MachInstLabelUse for LabelUse {
3328
+ /// Alignment for veneer code.
3329
+ const ALIGN: CodeOffset = 2;
3330
+
3331
+ /// Maximum PC-relative range (positive), inclusive.
3332
+ fn max_pos_range(self) -> CodeOffset {
3333
+ match self {
3334
+ // 16-bit signed immediate, left-shifted by 1.
3335
+ LabelUse::BranchRI => ((1 << 15) - 1) << 1,
3336
+ // 32-bit signed immediate, left-shifted by 1.
3337
+ LabelUse::BranchRIL => 0xffff_fffe,
3338
+ // 32-bit signed immediate.
3339
+ LabelUse::PCRel32 => 0x7fff_ffff,
3340
+ // 32-bit signed immediate, left-shifted by 1, offset by 2.
3341
+ LabelUse::PCRel32Dbl => 0xffff_fffc,
3342
+ }
3343
+ }
3344
+
3345
+ /// Maximum PC-relative range (negative).
3346
+ fn max_neg_range(self) -> CodeOffset {
3347
+ match self {
3348
+ // 16-bit signed immediate, left-shifted by 1.
3349
+ LabelUse::BranchRI => (1 << 15) << 1,
3350
+ // 32-bit signed immediate, left-shifted by 1.
3351
+ // NOTE: This should be 4GB, but CodeOffset is only u32.
3352
+ LabelUse::BranchRIL => 0xffff_ffff,
3353
+ // 32-bit signed immediate.
3354
+ LabelUse::PCRel32 => 0x8000_0000,
3355
+ // 32-bit signed immediate, left-shifted by 1, offset by 2.
3356
+ // NOTE: This should be 4GB + 2, but CodeOffset is only u32.
3357
+ LabelUse::PCRel32Dbl => 0xffff_ffff,
3358
+ }
3359
+ }
3360
+
3361
+ /// Size of window into code needed to do the patch.
3362
+ fn patch_size(self) -> CodeOffset {
3363
+ match self {
3364
+ LabelUse::BranchRI => 4,
3365
+ LabelUse::BranchRIL => 6,
3366
+ LabelUse::PCRel32 => 4,
3367
+ LabelUse::PCRel32Dbl => 4,
3368
+ }
3369
+ }
3370
+
3371
+ /// Perform the patch.
3372
+ fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
3373
+ let pc_rel = (label_offset as i64) - (use_offset as i64);
3374
+ debug_assert!(pc_rel <= self.max_pos_range() as i64);
3375
+ debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
3376
+ debug_assert!(pc_rel & 1 == 0);
3377
+ let pc_rel_shifted = pc_rel >> 1;
3378
+
3379
+ match self {
3380
+ LabelUse::BranchRI => {
3381
+ buffer[2..4].clone_from_slice(&u16::to_be_bytes(pc_rel_shifted as u16));
3382
+ }
3383
+ LabelUse::BranchRIL => {
3384
+ buffer[2..6].clone_from_slice(&u32::to_be_bytes(pc_rel_shifted as u32));
3385
+ }
3386
+ LabelUse::PCRel32 => {
3387
+ let insn_word = u32::from_be_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
3388
+ let insn_word = insn_word.wrapping_add(pc_rel as u32);
3389
+ buffer[0..4].clone_from_slice(&u32::to_be_bytes(insn_word));
3390
+ }
3391
+ LabelUse::PCRel32Dbl => {
3392
+ let insn_word = u32::from_be_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
3393
+ let insn_word = insn_word.wrapping_add((pc_rel_shifted + 1) as u32);
3394
+ buffer[0..4].clone_from_slice(&u32::to_be_bytes(insn_word));
3395
+ }
3396
+ }
3397
+ }
3398
+
3399
+ /// Is a veneer supported for this label reference type?
3400
+ fn supports_veneer(self) -> bool {
3401
+ false
3402
+ }
3403
+
3404
+ /// How large is the veneer, if supported?
3405
+ fn veneer_size(self) -> CodeOffset {
3406
+ 0
3407
+ }
3408
+
3409
+ /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
3410
+ /// an offset and label-use for the veneer's use of the original label.
3411
+ fn generate_veneer(
3412
+ self,
3413
+ _buffer: &mut [u8],
3414
+ _veneer_offset: CodeOffset,
3415
+ ) -> (CodeOffset, LabelUse) {
3416
+ unreachable!();
3417
+ }
3418
+
3419
+ fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
3420
+ match (reloc, addend) {
3421
+ (Reloc::S390xPCRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
3422
+ (Reloc::S390xPLTRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
3423
+ _ => None,
3424
+ }
3425
+ }
3426
+ }