wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,1963 @@
1
+ //! This module defines riscv64-specific machine instruction types.
2
+
3
+ // Some variants are not constructed, but we still want them as options in the future.
4
+ #![allow(dead_code)]
5
+ #![allow(non_camel_case_types)]
6
+
7
+ use super::lower::isle::generated_code::{VecAMode, VecElementWidth, VecOpMasking};
8
+ use crate::binemit::{Addend, CodeOffset, Reloc};
9
+ pub use crate::ir::condcodes::IntCC;
10
+ use crate::ir::types::{self, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
11
+
12
+ pub use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, Type, ValueLabel};
13
+ use crate::isa::{CallConv, FunctionAlignment};
14
+ use crate::machinst::*;
15
+ use crate::{settings, CodegenError, CodegenResult};
16
+
17
+ pub use crate::ir::condcodes::FloatCC;
18
+
19
+ use alloc::vec::Vec;
20
+ use regalloc2::{PRegSet, RegClass, VReg};
21
+ use smallvec::{smallvec, SmallVec};
22
+ use std::boxed::Box;
23
+ use std::fmt::Write;
24
+ use std::string::{String, ToString};
25
+
26
+ pub mod regs;
27
+ pub use self::regs::*;
28
+ pub mod imms;
29
+ pub use self::imms::*;
30
+ pub mod args;
31
+ pub use self::args::*;
32
+ pub mod emit;
33
+ pub use self::emit::*;
34
+ pub mod vector;
35
+ pub use self::vector::*;
36
+ pub mod encode;
37
+ pub use self::encode::*;
38
+ pub mod unwind;
39
+
40
+ use crate::isa::riscv64::abi::Riscv64MachineDeps;
41
+
42
+ #[cfg(test)]
43
+ mod emit_tests;
44
+
45
+ use std::fmt::{Display, Formatter};
46
+
47
+ pub(crate) type OptionReg = Option<Reg>;
48
+ pub(crate) type OptionImm12 = Option<Imm12>;
49
+ pub(crate) type VecBranchTarget = Vec<BranchTarget>;
50
+ pub(crate) type OptionUimm5 = Option<UImm5>;
51
+ pub(crate) type OptionFloatRoundingMode = Option<FRM>;
52
+ pub(crate) type VecU8 = Vec<u8>;
53
+ pub(crate) type VecWritableReg = Vec<Writable<Reg>>;
54
+ //=============================================================================
55
+ // Instructions (top level): definition
56
+
57
+ pub use crate::isa::riscv64::lower::isle::generated_code::{
58
+ AluOPRRI, AluOPRRR, AtomicOP, FClassResult, FFlagsException, FloatRoundOP, FloatSelectOP,
59
+ FpuOPRR, FpuOPRRR, FpuOPRRRR, IntSelectOP, LoadOP, MInst as Inst, StoreOP, FRM,
60
+ };
61
+ use crate::isa::riscv64::lower::isle::generated_code::{MInst, VecAluOpRRImm5, VecAluOpRRR};
62
+
63
+ type BoxCallInfo = Box<CallInfo>;
64
+ type BoxCallIndInfo = Box<CallIndInfo>;
65
+
66
+ /// Additional information for (direct) Call instructions, left out of line to lower the size of
67
+ /// the Inst enum.
68
+ #[derive(Clone, Debug)]
69
+ pub struct CallInfo {
70
+ pub dest: ExternalName,
71
+ pub uses: CallArgList,
72
+ pub defs: CallRetList,
73
+ pub opcode: Opcode,
74
+ pub caller_callconv: CallConv,
75
+ pub callee_callconv: CallConv,
76
+ pub clobbers: PRegSet,
77
+ }
78
+
79
+ /// Additional information for CallInd instructions, left out of line to lower the size of the Inst
80
+ /// enum.
81
+ #[derive(Clone, Debug)]
82
+ pub struct CallIndInfo {
83
+ pub rn: Reg,
84
+ pub uses: CallArgList,
85
+ pub defs: CallRetList,
86
+ pub opcode: Opcode,
87
+ pub caller_callconv: CallConv,
88
+ pub callee_callconv: CallConv,
89
+ pub clobbers: PRegSet,
90
+ }
91
+
92
+ /// A branch target. Either unresolved (basic-block index) or resolved (offset
93
+ /// from end of current instruction).
94
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
95
+ pub enum BranchTarget {
96
+ /// An unresolved reference to a Label, as passed into
97
+ /// `lower_branch_group()`.
98
+ Label(MachLabel),
99
+ /// A fixed PC offset.
100
+ ResolvedOffset(i32),
101
+ }
102
+
103
+ impl BranchTarget {
104
+ /// Return the target's label, if it is a label-based target.
105
+ pub(crate) fn as_label(self) -> Option<MachLabel> {
106
+ match self {
107
+ BranchTarget::Label(l) => Some(l),
108
+ _ => None,
109
+ }
110
+ }
111
+ /// offset zero.
112
+ #[inline]
113
+ pub(crate) fn zero() -> Self {
114
+ Self::ResolvedOffset(0)
115
+ }
116
+ #[inline]
117
+ pub(crate) fn offset(off: i32) -> Self {
118
+ Self::ResolvedOffset(off)
119
+ }
120
+ #[inline]
121
+ pub(crate) fn is_zero(self) -> bool {
122
+ match self {
123
+ BranchTarget::Label(_) => false,
124
+ BranchTarget::ResolvedOffset(off) => off == 0,
125
+ }
126
+ }
127
+ #[inline]
128
+ pub(crate) fn as_offset(self) -> Option<i32> {
129
+ match self {
130
+ BranchTarget::Label(_) => None,
131
+ BranchTarget::ResolvedOffset(off) => Some(off),
132
+ }
133
+ }
134
+ }
135
+
136
+ impl Display for BranchTarget {
137
+ fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
138
+ match self {
139
+ BranchTarget::Label(l) => write!(f, "{}", l.to_string()),
140
+ BranchTarget::ResolvedOffset(off) => write!(f, "{}", off),
141
+ }
142
+ }
143
+ }
144
+
145
+ pub(crate) fn enc_auipc(rd: Writable<Reg>, imm: Imm20) -> u32 {
146
+ let x = 0b0010111 | reg_to_gpr_num(rd.to_reg()) << 7 | imm.as_u32() << 12;
147
+ x
148
+ }
149
+
150
+ pub(crate) fn enc_jalr(rd: Writable<Reg>, base: Reg, offset: Imm12) -> u32 {
151
+ let x = 0b1100111
152
+ | reg_to_gpr_num(rd.to_reg()) << 7
153
+ | 0b000 << 12
154
+ | reg_to_gpr_num(base) << 15
155
+ | offset.as_u32() << 20;
156
+ x
157
+ }
158
+
159
+ /// rd and src must have the same length.
160
+ pub(crate) fn gen_moves(rd: &[Writable<Reg>], src: &[Reg]) -> SmallInstVec<Inst> {
161
+ assert!(rd.len() == src.len());
162
+ assert!(rd.len() > 0);
163
+ let mut insts = SmallInstVec::new();
164
+ for (dst, src) in rd.iter().zip(src.iter()) {
165
+ let ty = Inst::canonical_type_for_rc(dst.to_reg().class());
166
+ insts.push(Inst::gen_move(*dst, *src, ty));
167
+ }
168
+ insts
169
+ }
170
+
171
+ impl Inst {
172
+ const INSTRUCTION_SIZE: i32 = 4;
173
+
174
+ #[inline]
175
+ pub(crate) fn load_imm12(rd: Writable<Reg>, imm: Imm12) -> Inst {
176
+ Inst::AluRRImm12 {
177
+ alu_op: AluOPRRI::Addi,
178
+ rd,
179
+ rs: zero_reg(),
180
+ imm12: imm,
181
+ }
182
+ }
183
+
184
+ /// Immediates can be loaded using lui and addi instructions.
185
+ fn load_const_imm<F: FnMut(Type) -> Writable<Reg>>(
186
+ rd: Writable<Reg>,
187
+ value: u64,
188
+ alloc_tmp: &mut F,
189
+ ) -> Option<SmallInstVec<Inst>> {
190
+ Inst::generate_imm(value, |imm20, imm12| {
191
+ let mut insts = SmallVec::new();
192
+
193
+ let rs = if let Some(imm) = imm20 {
194
+ let rd = if imm12.is_some() { alloc_tmp(I64) } else { rd };
195
+ insts.push(Inst::Lui { rd, imm });
196
+ rd.to_reg()
197
+ } else {
198
+ zero_reg()
199
+ };
200
+
201
+ if let Some(imm12) = imm12 {
202
+ insts.push(Inst::AluRRImm12 {
203
+ alu_op: AluOPRRI::Addi,
204
+ rd,
205
+ rs,
206
+ imm12,
207
+ })
208
+ }
209
+
210
+ insts
211
+ })
212
+ }
213
+
214
+ pub(crate) fn load_constant_u32<F: FnMut(Type) -> Writable<Reg>>(
215
+ rd: Writable<Reg>,
216
+ value: u64,
217
+ alloc_tmp: &mut F,
218
+ ) -> SmallInstVec<Inst> {
219
+ let insts = Inst::load_const_imm(rd, value, alloc_tmp);
220
+ insts.unwrap_or_else(|| {
221
+ smallvec![Inst::LoadConst32 {
222
+ rd,
223
+ imm: value as u32
224
+ }]
225
+ })
226
+ }
227
+
228
+ pub fn load_constant_u64<F: FnMut(Type) -> Writable<Reg>>(
229
+ rd: Writable<Reg>,
230
+ value: u64,
231
+ alloc_tmp: &mut F,
232
+ ) -> SmallInstVec<Inst> {
233
+ let insts = Inst::load_const_imm(rd, value, alloc_tmp);
234
+ insts.unwrap_or_else(|| smallvec![Inst::LoadConst64 { rd, imm: value }])
235
+ }
236
+
237
+ pub(crate) fn construct_auipc_and_jalr(
238
+ link: Option<Writable<Reg>>,
239
+ tmp: Writable<Reg>,
240
+ offset: i64,
241
+ ) -> [Inst; 2] {
242
+ Inst::generate_imm(offset as u64, |imm20, imm12| {
243
+ let a = Inst::Auipc {
244
+ rd: tmp,
245
+ imm: imm20.unwrap_or_default(),
246
+ };
247
+ let b = Inst::Jalr {
248
+ rd: link.unwrap_or(writable_zero_reg()),
249
+ base: tmp.to_reg(),
250
+ offset: imm12.unwrap_or_default(),
251
+ };
252
+ [a, b]
253
+ })
254
+ .expect("code range is too big.")
255
+ }
256
+
257
+ /// Create instructions that load a 32-bit floating-point constant.
258
+ pub fn load_fp_constant32<F: FnMut(Type) -> Writable<Reg>>(
259
+ rd: Writable<Reg>,
260
+ const_data: u32,
261
+ mut alloc_tmp: F,
262
+ ) -> SmallVec<[Inst; 4]> {
263
+ let mut insts = SmallVec::new();
264
+ let tmp = alloc_tmp(I64);
265
+ insts.extend(Self::load_constant_u32(
266
+ tmp,
267
+ const_data as u64,
268
+ &mut alloc_tmp,
269
+ ));
270
+ insts.push(Inst::FpuRR {
271
+ frm: None,
272
+ alu_op: FpuOPRR::move_x_to_f_op(F32),
273
+ rd,
274
+ rs: tmp.to_reg(),
275
+ });
276
+ insts
277
+ }
278
+
279
+ /// Create instructions that load a 64-bit floating-point constant.
280
+ pub fn load_fp_constant64<F: FnMut(Type) -> Writable<Reg>>(
281
+ rd: Writable<Reg>,
282
+ const_data: u64,
283
+ mut alloc_tmp: F,
284
+ ) -> SmallVec<[Inst; 4]> {
285
+ let mut insts = SmallInstVec::new();
286
+ let tmp = alloc_tmp(I64);
287
+ insts.extend(Self::load_constant_u64(tmp, const_data, &mut alloc_tmp));
288
+ insts.push(Inst::FpuRR {
289
+ frm: None,
290
+ alu_op: FpuOPRR::move_x_to_f_op(F64),
291
+ rd,
292
+ rs: tmp.to_reg(),
293
+ });
294
+ insts
295
+ }
296
+
297
+ /// Generic constructor for a load (zero-extending where appropriate).
298
+ pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
299
+ if ty.is_vector() {
300
+ Inst::VecLoad {
301
+ eew: VecElementWidth::from_type(ty),
302
+ to: into_reg,
303
+ from: VecAMode::UnitStride { base: mem },
304
+ flags,
305
+ mask: VecOpMasking::Disabled,
306
+ vstate: VState::from_type(ty),
307
+ }
308
+ } else {
309
+ Inst::Load {
310
+ rd: into_reg,
311
+ op: LoadOP::from_type(ty),
312
+ from: mem,
313
+ flags,
314
+ }
315
+ }
316
+ }
317
+
318
+ /// Generic constructor for a store.
319
+ pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
320
+ if ty.is_vector() {
321
+ Inst::VecStore {
322
+ eew: VecElementWidth::from_type(ty),
323
+ to: VecAMode::UnitStride { base: mem },
324
+ from: from_reg,
325
+ flags,
326
+ mask: VecOpMasking::Disabled,
327
+ vstate: VState::from_type(ty),
328
+ }
329
+ } else {
330
+ Inst::Store {
331
+ src: from_reg,
332
+ op: StoreOP::from_type(ty),
333
+ to: mem,
334
+ flags,
335
+ }
336
+ }
337
+ }
338
+ }
339
+
340
+ //=============================================================================
341
+
342
+ fn vec_mask_operands<F: Fn(VReg) -> VReg>(
343
+ mask: &VecOpMasking,
344
+ collector: &mut OperandCollector<'_, F>,
345
+ ) {
346
+ match mask {
347
+ VecOpMasking::Enabled { reg } => {
348
+ collector.reg_fixed_use(*reg, pv_reg(0).into());
349
+ }
350
+ VecOpMasking::Disabled => {}
351
+ }
352
+ }
353
+
354
+ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCollector<'_, F>) {
355
+ match inst {
356
+ &Inst::Nop0 => {}
357
+ &Inst::Nop4 => {}
358
+ &Inst::BrTable {
359
+ index, tmp1, tmp2, ..
360
+ } => {
361
+ collector.reg_use(index);
362
+ collector.reg_early_def(tmp1);
363
+ collector.reg_early_def(tmp2);
364
+ }
365
+ &Inst::Auipc { rd, .. } => collector.reg_def(rd),
366
+ &Inst::Lui { rd, .. } => collector.reg_def(rd),
367
+ &Inst::LoadConst32 { rd, .. } => collector.reg_def(rd),
368
+ &Inst::LoadConst64 { rd, .. } => collector.reg_def(rd),
369
+ &Inst::AluRRR { rd, rs1, rs2, .. } => {
370
+ collector.reg_use(rs1);
371
+ collector.reg_use(rs2);
372
+ collector.reg_def(rd);
373
+ }
374
+ &Inst::FpuRRR { rd, rs1, rs2, .. } => {
375
+ collector.reg_use(rs1);
376
+ collector.reg_use(rs2);
377
+ collector.reg_def(rd);
378
+ }
379
+ &Inst::AluRRImm12 { rd, rs, .. } => {
380
+ collector.reg_use(rs);
381
+ collector.reg_def(rd);
382
+ }
383
+ &Inst::Load { rd, from, .. } => {
384
+ if let Some(r) = from.get_allocatable_register() {
385
+ collector.reg_use(r);
386
+ }
387
+ collector.reg_def(rd);
388
+ }
389
+ &Inst::Store { to, src, .. } => {
390
+ if let Some(r) = to.get_allocatable_register() {
391
+ collector.reg_use(r);
392
+ }
393
+ collector.reg_use(src);
394
+ }
395
+
396
+ &Inst::Args { ref args } => {
397
+ for arg in args {
398
+ collector.reg_fixed_def(arg.vreg, arg.preg);
399
+ }
400
+ }
401
+ &Inst::Ret { ref rets, .. } => {
402
+ for ret in rets {
403
+ collector.reg_fixed_use(ret.vreg, ret.preg);
404
+ }
405
+ }
406
+
407
+ &Inst::Extend { rd, rn, .. } => {
408
+ collector.reg_use(rn);
409
+ collector.reg_def(rd);
410
+ }
411
+ &Inst::AdjustSp { .. } => {}
412
+ &Inst::Call { ref info } => {
413
+ for u in &info.uses {
414
+ collector.reg_fixed_use(u.vreg, u.preg);
415
+ }
416
+ for d in &info.defs {
417
+ collector.reg_fixed_def(d.vreg, d.preg);
418
+ }
419
+ collector.reg_clobbers(info.clobbers);
420
+ }
421
+ &Inst::CallInd { ref info } => {
422
+ collector.reg_use(info.rn);
423
+ for u in &info.uses {
424
+ collector.reg_fixed_use(u.vreg, u.preg);
425
+ }
426
+ for d in &info.defs {
427
+ collector.reg_fixed_def(d.vreg, d.preg);
428
+ }
429
+ collector.reg_clobbers(info.clobbers);
430
+ }
431
+ &Inst::TrapIf { test, .. } => {
432
+ collector.reg_use(test);
433
+ }
434
+ &Inst::Jal { .. } => {}
435
+ &Inst::CondBr { kind, .. } => {
436
+ collector.reg_use(kind.rs1);
437
+ collector.reg_use(kind.rs2);
438
+ }
439
+ &Inst::LoadExtName { rd, .. } => {
440
+ collector.reg_def(rd);
441
+ }
442
+ &Inst::LoadAddr { rd, mem } => {
443
+ if let Some(r) = mem.get_allocatable_register() {
444
+ collector.reg_use(r);
445
+ }
446
+ collector.reg_early_def(rd);
447
+ }
448
+
449
+ &Inst::VirtualSPOffsetAdj { .. } => {}
450
+ &Inst::Mov { rd, rm, .. } => {
451
+ collector.reg_use(rm);
452
+ collector.reg_def(rd);
453
+ }
454
+ &Inst::MovFromPReg { rd, rm } => {
455
+ debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
456
+ collector.reg_def(rd);
457
+ }
458
+ &Inst::Fence { .. } => {}
459
+ &Inst::FenceI => {}
460
+ &Inst::ECall => {}
461
+ &Inst::EBreak => {}
462
+ &Inst::Udf { .. } => {}
463
+ &Inst::FpuRR { rd, rs, .. } => {
464
+ collector.reg_use(rs);
465
+ collector.reg_def(rd);
466
+ }
467
+ &Inst::FpuRRRR {
468
+ rd, rs1, rs2, rs3, ..
469
+ } => {
470
+ collector.reg_uses(&[rs1, rs2, rs3]);
471
+ collector.reg_def(rd);
472
+ }
473
+
474
+ &Inst::Jalr { rd, base, .. } => {
475
+ collector.reg_use(base);
476
+ collector.reg_def(rd);
477
+ }
478
+ &Inst::Atomic { rd, addr, src, .. } => {
479
+ collector.reg_use(addr);
480
+ collector.reg_use(src);
481
+ collector.reg_def(rd);
482
+ }
483
+ &Inst::Select {
484
+ ref dst,
485
+ condition,
486
+ x,
487
+ y,
488
+ ..
489
+ } => {
490
+ collector.reg_use(condition);
491
+ collector.reg_uses(x.regs());
492
+ collector.reg_uses(y.regs());
493
+ for d in dst.iter() {
494
+ collector.reg_early_def(d.clone());
495
+ }
496
+ }
497
+ &Inst::AtomicCas {
498
+ offset,
499
+ t0,
500
+ dst,
501
+ e,
502
+ addr,
503
+ v,
504
+ ..
505
+ } => {
506
+ collector.reg_uses(&[offset, e, addr, v]);
507
+ collector.reg_early_def(t0);
508
+ collector.reg_early_def(dst);
509
+ }
510
+ &Inst::IntSelect {
511
+ ref dst,
512
+ ref x,
513
+ ref y,
514
+ ..
515
+ } => {
516
+ collector.reg_uses(x.regs());
517
+ collector.reg_uses(y.regs());
518
+ for d in dst.iter() {
519
+ collector.reg_early_def(d.clone());
520
+ }
521
+ }
522
+
523
+ &Inst::Icmp { rd, a, b, .. } => {
524
+ collector.reg_uses(a.regs());
525
+ collector.reg_uses(b.regs());
526
+ collector.reg_def(rd);
527
+ }
528
+
529
+ &Inst::SelectReg {
530
+ rd,
531
+ rs1,
532
+ rs2,
533
+ condition,
534
+ } => {
535
+ collector.reg_use(condition.rs1);
536
+ collector.reg_use(condition.rs2);
537
+ collector.reg_use(rs1);
538
+ collector.reg_use(rs2);
539
+ collector.reg_def(rd);
540
+ }
541
+ &Inst::FcvtToInt { rd, rs, tmp, .. } => {
542
+ collector.reg_use(rs);
543
+ collector.reg_early_def(tmp);
544
+ collector.reg_early_def(rd);
545
+ }
546
+ &Inst::RawData { .. } => {}
547
+ &Inst::AtomicStore { src, p, .. } => {
548
+ collector.reg_use(src);
549
+ collector.reg_use(p);
550
+ }
551
+ &Inst::AtomicLoad { rd, p, .. } => {
552
+ collector.reg_use(p);
553
+ collector.reg_def(rd);
554
+ }
555
+ &Inst::AtomicRmwLoop {
556
+ offset,
557
+ dst,
558
+ p,
559
+ x,
560
+ t0,
561
+ ..
562
+ } => {
563
+ collector.reg_uses(&[offset, p, x]);
564
+ collector.reg_early_def(t0);
565
+ collector.reg_early_def(dst);
566
+ }
567
+ &Inst::TrapIfC { rs1, rs2, .. } => {
568
+ collector.reg_use(rs1);
569
+ collector.reg_use(rs2);
570
+ }
571
+ &Inst::Unwind { .. } => {}
572
+ &Inst::DummyUse { reg } => {
573
+ collector.reg_use(reg);
574
+ }
575
+ &Inst::FloatRound {
576
+ rd,
577
+ int_tmp,
578
+ f_tmp,
579
+ rs,
580
+ ..
581
+ } => {
582
+ collector.reg_use(rs);
583
+ collector.reg_early_def(int_tmp);
584
+ collector.reg_early_def(f_tmp);
585
+ collector.reg_early_def(rd);
586
+ }
587
+ &Inst::FloatSelect {
588
+ rd, tmp, rs1, rs2, ..
589
+ } => {
590
+ collector.reg_uses(&[rs1, rs2]);
591
+ collector.reg_early_def(tmp);
592
+ collector.reg_early_def(rd);
593
+ }
594
+ &Inst::FloatSelectPseudo {
595
+ rd, tmp, rs1, rs2, ..
596
+ } => {
597
+ collector.reg_uses(&[rs1, rs2]);
598
+ collector.reg_early_def(tmp);
599
+ collector.reg_early_def(rd);
600
+ }
601
+ &Inst::Popcnt {
602
+ sum, step, rs, tmp, ..
603
+ } => {
604
+ collector.reg_use(rs);
605
+ collector.reg_early_def(tmp);
606
+ collector.reg_early_def(step);
607
+ collector.reg_early_def(sum);
608
+ }
609
+ &Inst::Rev8 { rs, rd, tmp, step } => {
610
+ collector.reg_use(rs);
611
+ collector.reg_early_def(tmp);
612
+ collector.reg_early_def(step);
613
+ collector.reg_early_def(rd);
614
+ }
615
+ &Inst::Cltz {
616
+ sum, step, tmp, rs, ..
617
+ } => {
618
+ collector.reg_use(rs);
619
+ collector.reg_early_def(tmp);
620
+ collector.reg_early_def(step);
621
+ collector.reg_early_def(sum);
622
+ }
623
+ &Inst::Brev8 {
624
+ rs,
625
+ rd,
626
+ step,
627
+ tmp,
628
+ tmp2,
629
+ ..
630
+ } => {
631
+ collector.reg_use(rs);
632
+ collector.reg_early_def(step);
633
+ collector.reg_early_def(tmp);
634
+ collector.reg_early_def(tmp2);
635
+ collector.reg_early_def(rd);
636
+ }
637
+ &Inst::StackProbeLoop { .. } => {
638
+ // StackProbeLoop has a tmp register and StackProbeLoop used at gen_prologue.
639
+ // t3 will do the job. (t3 is caller-save register and not used directly by compiler like writable_spilltmp_reg)
640
+ // gen_prologue is called at emit stage.
641
+ // no need let reg alloc know.
642
+ }
643
+ &Inst::VecAluRRR {
644
+ op,
645
+ vd,
646
+ vs1,
647
+ vs2,
648
+ ref mask,
649
+ ..
650
+ } => {
651
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
652
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
653
+ debug_assert_eq!(vs1.class(), op.vs1_regclass());
654
+
655
+ collector.reg_use(vs1);
656
+ collector.reg_use(vs2);
657
+ collector.reg_def(vd);
658
+ vec_mask_operands(mask, collector);
659
+ }
660
+ &Inst::VecAluRRImm5 {
661
+ vd, vs2, ref mask, ..
662
+ } => {
663
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
664
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
665
+
666
+ collector.reg_use(vs2);
667
+ collector.reg_def(vd);
668
+ vec_mask_operands(mask, collector);
669
+ }
670
+ &Inst::VecAluRR {
671
+ op,
672
+ vd,
673
+ vs,
674
+ ref mask,
675
+ ..
676
+ } => {
677
+ debug_assert_eq!(vd.to_reg().class(), op.dst_regclass());
678
+ debug_assert_eq!(vs.class(), op.src_regclass());
679
+
680
+ collector.reg_use(vs);
681
+ collector.reg_def(vd);
682
+ vec_mask_operands(mask, collector);
683
+ }
684
+ &Inst::VecAluRImm5 { vd, ref mask, .. } => {
685
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
686
+
687
+ collector.reg_def(vd);
688
+ vec_mask_operands(mask, collector);
689
+ }
690
+ &Inst::VecSetState { rd, .. } => {
691
+ collector.reg_def(rd);
692
+ }
693
+ &Inst::VecLoad {
694
+ to,
695
+ ref from,
696
+ ref mask,
697
+ ..
698
+ } => {
699
+ if let Some(r) = from.get_allocatable_register() {
700
+ collector.reg_use(r);
701
+ }
702
+ collector.reg_def(to);
703
+ vec_mask_operands(mask, collector);
704
+ }
705
+ &Inst::VecStore {
706
+ ref to,
707
+ from,
708
+ ref mask,
709
+ ..
710
+ } => {
711
+ if let Some(r) = to.get_allocatable_register() {
712
+ collector.reg_use(r);
713
+ }
714
+ collector.reg_use(from);
715
+ vec_mask_operands(mask, collector);
716
+ }
717
+ }
718
+ }
719
+
720
+ impl MachInst for Inst {
721
+ type LabelUse = LabelUse;
722
+ type ABIMachineSpec = Riscv64MachineDeps;
723
+
724
+ // https://github.com/riscv/riscv-isa-manual/issues/850
725
+ // all zero will cause invalid opcode.
726
+ const TRAP_OPCODE: &'static [u8] = &[0; 4];
727
+
728
+ fn gen_dummy_use(reg: Reg) -> Self {
729
+ Inst::DummyUse { reg }
730
+ }
731
+
732
+ fn canonical_type_for_rc(rc: RegClass) -> Type {
733
+ match rc {
734
+ regalloc2::RegClass::Int => I64,
735
+ regalloc2::RegClass::Float => F64,
736
+ regalloc2::RegClass::Vector => I8X16,
737
+ }
738
+ }
739
+
740
+ fn is_safepoint(&self) -> bool {
741
+ match self {
742
+ &Inst::Call { .. }
743
+ | &Inst::CallInd { .. }
744
+ | &Inst::TrapIf { .. }
745
+ | &Inst::Udf { .. } => true,
746
+ _ => false,
747
+ }
748
+ }
749
+
750
+ fn get_operands<F: Fn(VReg) -> VReg>(&self, collector: &mut OperandCollector<'_, F>) {
751
+ riscv64_get_operands(self, collector);
752
+ }
753
+
754
+ fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
755
+ match self {
756
+ Inst::Mov { rd, rm, .. } => Some((rd.clone(), rm.clone())),
757
+ _ => None,
758
+ }
759
+ }
760
+
761
+ fn is_included_in_clobbers(&self) -> bool {
762
+ match self {
763
+ &Inst::Args { .. } => false,
764
+ _ => true,
765
+ }
766
+ }
767
+
768
+ fn is_trap(&self) -> bool {
769
+ match self {
770
+ Self::Udf { .. } => true,
771
+ _ => false,
772
+ }
773
+ }
774
+
775
+ fn is_args(&self) -> bool {
776
+ match self {
777
+ Self::Args { .. } => true,
778
+ _ => false,
779
+ }
780
+ }
781
+
782
+ fn is_term(&self) -> MachTerminator {
783
+ match self {
784
+ &Inst::Jal { .. } => MachTerminator::Uncond,
785
+ &Inst::CondBr { .. } => MachTerminator::Cond,
786
+ &Inst::Jalr { .. } => MachTerminator::Uncond,
787
+ &Inst::Ret { .. } => MachTerminator::Ret,
788
+ &Inst::BrTable { .. } => MachTerminator::Indirect,
789
+ _ => MachTerminator::None,
790
+ }
791
+ }
792
+
793
+ fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
794
+ let x = Inst::Mov {
795
+ rd: to_reg,
796
+ rm: from_reg,
797
+ ty,
798
+ };
799
+ x
800
+ }
801
+
802
+ fn gen_nop(preferred_size: usize) -> Inst {
803
+ if preferred_size == 0 {
804
+ return Inst::Nop0;
805
+ }
806
+ // We can't give a NOP (or any insn) < 4 bytes.
807
+ assert!(preferred_size >= 4);
808
+ Inst::Nop4
809
+ }
810
+
811
+ fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
812
+ match ty {
813
+ I8 => Ok((&[RegClass::Int], &[I8])),
814
+ I16 => Ok((&[RegClass::Int], &[I16])),
815
+ I32 => Ok((&[RegClass::Int], &[I32])),
816
+ I64 => Ok((&[RegClass::Int], &[I64])),
817
+ R32 => panic!("32-bit reftype pointer should never be seen on riscv64"),
818
+ R64 => Ok((&[RegClass::Int], &[R64])),
819
+ F32 => Ok((&[RegClass::Float], &[F32])),
820
+ F64 => Ok((&[RegClass::Float], &[F64])),
821
+ I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
822
+ _ if ty.is_vector() => {
823
+ debug_assert!(ty.bits() <= 512);
824
+
825
+ // Here we only need to return a SIMD type with the same size as `ty`.
826
+ // We use these types for spills and reloads, so prefer types with lanes <= 31
827
+ // since that fits in the immediate field of `vsetivli`.
828
+ const SIMD_TYPES: [[Type; 1]; 6] = [
829
+ [types::I8X2],
830
+ [types::I8X4],
831
+ [types::I8X8],
832
+ [types::I8X16],
833
+ [types::I16X16],
834
+ [types::I32X16],
835
+ ];
836
+ let idx = (ty.bytes().ilog2() - 1) as usize;
837
+ let ty = &SIMD_TYPES[idx][..];
838
+
839
+ Ok((&[RegClass::Vector], ty))
840
+ }
841
+ _ => Err(CodegenError::Unsupported(format!(
842
+ "Unexpected SSA-value type: {}",
843
+ ty
844
+ ))),
845
+ }
846
+ }
847
+
848
+ fn gen_jump(target: MachLabel) -> Inst {
849
+ Inst::Jal {
850
+ dest: BranchTarget::Label(target),
851
+ }
852
+ }
853
+
854
+ fn worst_case_size() -> CodeOffset {
855
+ // calculate by test function riscv64_worst_case_instruction_size()
856
+ 116
857
+ }
858
+
859
+ fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {
860
+ RegClass::Int
861
+ }
862
+
863
+ fn function_alignment() -> FunctionAlignment {
864
+ FunctionAlignment {
865
+ minimum: 4,
866
+ preferred: 4,
867
+ }
868
+ }
869
+ }
870
+
871
+ //=============================================================================
872
+ // Pretty-printing of instructions.
873
+ pub fn reg_name(reg: Reg) -> String {
874
+ match reg.to_real_reg() {
875
+ Some(real) => match real.class() {
876
+ RegClass::Int => match real.hw_enc() {
877
+ 0 => "zero".into(),
878
+ 1 => "ra".into(),
879
+ 2 => "sp".into(),
880
+ 3 => "gp".into(),
881
+ 4 => "tp".into(),
882
+ 5 => "t0".into(),
883
+ 6..=7 => format!("t{}", real.hw_enc() - 5),
884
+ 8 => "fp".into(),
885
+ 9 => "s1".into(),
886
+ 10..=17 => format!("a{}", real.hw_enc() - 10),
887
+ 18..=27 => format!("s{}", real.hw_enc() - 16),
888
+ 28..=31 => format!("t{}", real.hw_enc() - 25),
889
+ _ => unreachable!(),
890
+ },
891
+ RegClass::Float => match real.hw_enc() {
892
+ 0..=7 => format!("ft{}", real.hw_enc() - 0),
893
+ 8..=9 => format!("fs{}", real.hw_enc() - 8),
894
+ 10..=17 => format!("fa{}", real.hw_enc() - 10),
895
+ 18..=27 => format!("fs{}", real.hw_enc() - 16),
896
+ 28..=31 => format!("ft{}", real.hw_enc() - 20),
897
+ _ => unreachable!(),
898
+ },
899
+ RegClass::Vector => format!("v{}", real.hw_enc()),
900
+ },
901
+ None => {
902
+ format!("{:?}", reg)
903
+ }
904
+ }
905
+ }
906
+
907
+ impl Inst {
908
+ fn print_with_state(
909
+ &self,
910
+ _state: &mut EmitState,
911
+ allocs: &mut AllocationConsumer<'_>,
912
+ ) -> String {
913
+ let format_reg = |reg: Reg, allocs: &mut AllocationConsumer<'_>| -> String {
914
+ let reg = allocs.next(reg);
915
+ reg_name(reg)
916
+ };
917
+
918
+ let format_vec_amode = |amode: &VecAMode, allocs: &mut AllocationConsumer<'_>| -> String {
919
+ match amode {
920
+ VecAMode::UnitStride { base } => base.to_string_with_alloc(allocs),
921
+ }
922
+ };
923
+
924
+ let format_mask = |mask: &VecOpMasking, allocs: &mut AllocationConsumer<'_>| -> String {
925
+ match mask {
926
+ VecOpMasking::Enabled { reg } => format!(",{}.t", format_reg(*reg, allocs)),
927
+ VecOpMasking::Disabled => format!(""),
928
+ }
929
+ };
930
+
931
+ let format_regs = |regs: &[Reg], allocs: &mut AllocationConsumer<'_>| -> String {
932
+ let mut x = if regs.len() > 1 {
933
+ String::from("[")
934
+ } else {
935
+ String::default()
936
+ };
937
+ regs.iter().for_each(|i| {
938
+ x.push_str(format_reg(i.clone(), allocs).as_str());
939
+ if *i != *regs.last().unwrap() {
940
+ x.push_str(",");
941
+ }
942
+ });
943
+ if regs.len() > 1 {
944
+ x.push_str("]");
945
+ }
946
+ x
947
+ };
948
+ let format_labels = |labels: &[MachLabel]| -> String {
949
+ if labels.len() == 0 {
950
+ return String::from("[_]");
951
+ }
952
+ let mut x = String::from("[");
953
+ labels.iter().for_each(|l| {
954
+ x.push_str(
955
+ format!(
956
+ "{:?}{}",
957
+ l,
958
+ if l != labels.last().unwrap() { "," } else { "" },
959
+ )
960
+ .as_str(),
961
+ );
962
+ });
963
+ x.push_str("]");
964
+ x
965
+ };
966
+
967
+ fn format_frm(rounding_mode: Option<FRM>) -> String {
968
+ if let Some(r) = rounding_mode {
969
+ format!(",{}", r.to_static_str(),)
970
+ } else {
971
+ "".into()
972
+ }
973
+ }
974
+
975
+ match self {
976
+ &Inst::Nop0 => {
977
+ format!("##zero length nop")
978
+ }
979
+ &Inst::Nop4 => {
980
+ format!("##fixed 4-size nop")
981
+ }
982
+ &Inst::StackProbeLoop {
983
+ guard_size,
984
+ probe_count,
985
+ tmp,
986
+ } => {
987
+ let tmp = format_reg(tmp.to_reg(), allocs);
988
+ format!(
989
+ "inline_stack_probe##guard_size={} probe_count={} tmp={}",
990
+ guard_size, probe_count, tmp
991
+ )
992
+ }
993
+ &Inst::FloatRound {
994
+ op,
995
+ rd,
996
+ int_tmp,
997
+ f_tmp,
998
+ rs,
999
+ ty,
1000
+ } => {
1001
+ let rs = format_reg(rs, allocs);
1002
+ let int_tmp = format_reg(int_tmp.to_reg(), allocs);
1003
+ let f_tmp = format_reg(f_tmp.to_reg(), allocs);
1004
+ let rd = format_reg(rd.to_reg(), allocs);
1005
+ format!(
1006
+ "{} {},{}##int_tmp={} f_tmp={} ty={}",
1007
+ op.op_name(),
1008
+ rd,
1009
+ rs,
1010
+ int_tmp,
1011
+ f_tmp,
1012
+ ty
1013
+ )
1014
+ }
1015
+ &Inst::FloatSelectPseudo {
1016
+ op,
1017
+ rd,
1018
+ tmp,
1019
+ rs1,
1020
+ rs2,
1021
+ ty,
1022
+ } => {
1023
+ let rs1 = format_reg(rs1, allocs);
1024
+ let rs2 = format_reg(rs2, allocs);
1025
+ let tmp = format_reg(tmp.to_reg(), allocs);
1026
+ let rd = format_reg(rd.to_reg(), allocs);
1027
+ format!(
1028
+ "f{}.{}.pseudo {},{},{}##tmp={} ty={}",
1029
+ op.op_name(),
1030
+ if ty == F32 { "s" } else { "d" },
1031
+ rd,
1032
+ rs1,
1033
+ rs2,
1034
+ tmp,
1035
+ ty
1036
+ )
1037
+ }
1038
+ &Inst::FloatSelect {
1039
+ op,
1040
+ rd,
1041
+ tmp,
1042
+ rs1,
1043
+ rs2,
1044
+ ty,
1045
+ } => {
1046
+ let rs1 = format_reg(rs1, allocs);
1047
+ let rs2 = format_reg(rs2, allocs);
1048
+ let tmp = format_reg(tmp.to_reg(), allocs);
1049
+ let rd = format_reg(rd.to_reg(), allocs);
1050
+ format!(
1051
+ "f{}.{} {},{},{}##tmp={} ty={}",
1052
+ op.op_name(),
1053
+ if ty == F32 { "s" } else { "d" },
1054
+ rd,
1055
+ rs1,
1056
+ rs2,
1057
+ tmp,
1058
+ ty
1059
+ )
1060
+ }
1061
+ &Inst::AtomicStore { src, ty, p } => {
1062
+ let src = format_reg(src, allocs);
1063
+ let p = format_reg(p, allocs);
1064
+ format!("atomic_store.{} {},({})", ty, src, p)
1065
+ }
1066
+ &Inst::DummyUse { reg } => {
1067
+ let reg = format_reg(reg, allocs);
1068
+ format!("dummy_use {}", reg)
1069
+ }
1070
+
1071
+ &Inst::AtomicLoad { rd, ty, p } => {
1072
+ let p = format_reg(p, allocs);
1073
+ let rd = format_reg(rd.to_reg(), allocs);
1074
+ format!("atomic_load.{} {},({})", ty, rd, p)
1075
+ }
1076
+ &Inst::AtomicRmwLoop {
1077
+ offset,
1078
+ op,
1079
+ dst,
1080
+ ty,
1081
+ p,
1082
+ x,
1083
+ t0,
1084
+ } => {
1085
+ let offset = format_reg(offset, allocs);
1086
+ let p = format_reg(p, allocs);
1087
+ let x = format_reg(x, allocs);
1088
+ let t0 = format_reg(t0.to_reg(), allocs);
1089
+ let dst = format_reg(dst.to_reg(), allocs);
1090
+ format!(
1091
+ "atomic_rmw.{} {} {},{},({})##t0={} offset={}",
1092
+ ty, op, dst, x, p, t0, offset
1093
+ )
1094
+ }
1095
+
1096
+ &Inst::RawData { ref data } => match data.len() {
1097
+ 4 => {
1098
+ let mut bytes = [0; 4];
1099
+ for i in 0..bytes.len() {
1100
+ bytes[i] = data[i];
1101
+ }
1102
+ format!(".4byte 0x{:x}", u32::from_le_bytes(bytes))
1103
+ }
1104
+ 8 => {
1105
+ let mut bytes = [0; 8];
1106
+ for i in 0..bytes.len() {
1107
+ bytes[i] = data[i];
1108
+ }
1109
+ format!(".8byte 0x{:x}", u64::from_le_bytes(bytes))
1110
+ }
1111
+ _ => {
1112
+ format!(".data {:?}", data)
1113
+ }
1114
+ },
1115
+ &Inst::Unwind { ref inst } => {
1116
+ format!("unwind {:?}", inst)
1117
+ }
1118
+ &Inst::Brev8 {
1119
+ rs,
1120
+ ty,
1121
+ step,
1122
+ tmp,
1123
+ tmp2,
1124
+ rd,
1125
+ } => {
1126
+ let rs = format_reg(rs, allocs);
1127
+ let step = format_reg(step.to_reg(), allocs);
1128
+ let tmp = format_reg(tmp.to_reg(), allocs);
1129
+ let tmp2 = format_reg(tmp2.to_reg(), allocs);
1130
+ let rd = format_reg(rd.to_reg(), allocs);
1131
+ format!(
1132
+ "brev8 {},{}##tmp={} tmp2={} step={} ty={}",
1133
+ rd, rs, tmp, tmp2, step, ty
1134
+ )
1135
+ }
1136
+ &Inst::Popcnt {
1137
+ sum,
1138
+ step,
1139
+ rs,
1140
+ tmp,
1141
+ ty,
1142
+ } => {
1143
+ let rs = format_reg(rs, allocs);
1144
+ let tmp = format_reg(tmp.to_reg(), allocs);
1145
+ let step = format_reg(step.to_reg(), allocs);
1146
+ let sum = format_reg(sum.to_reg(), allocs);
1147
+ format!("popcnt {},{}##ty={} tmp={} step={}", sum, rs, ty, tmp, step)
1148
+ }
1149
+ &Inst::Rev8 { rs, rd, tmp, step } => {
1150
+ let rs = format_reg(rs, allocs);
1151
+ let tmp = format_reg(tmp.to_reg(), allocs);
1152
+ let step = format_reg(step.to_reg(), allocs);
1153
+ let rd = format_reg(rd.to_reg(), allocs);
1154
+ format!("rev8 {},{}##step={} tmp={}", rd, rs, step, tmp)
1155
+ }
1156
+ &Inst::Cltz {
1157
+ sum,
1158
+ step,
1159
+ rs,
1160
+ tmp,
1161
+ ty,
1162
+ leading,
1163
+ } => {
1164
+ let rs = format_reg(rs, allocs);
1165
+ let tmp = format_reg(tmp.to_reg(), allocs);
1166
+ let step = format_reg(step.to_reg(), allocs);
1167
+ let sum = format_reg(sum.to_reg(), allocs);
1168
+ format!(
1169
+ "{} {},{}##ty={} tmp={} step={}",
1170
+ if leading { "clz" } else { "ctz" },
1171
+ sum,
1172
+ rs,
1173
+ ty,
1174
+ tmp,
1175
+ step
1176
+ )
1177
+ }
1178
+ &Inst::FcvtToInt {
1179
+ is_sat,
1180
+ rd,
1181
+ rs,
1182
+ is_signed,
1183
+ in_type,
1184
+ out_type,
1185
+ tmp,
1186
+ } => {
1187
+ let rs = format_reg(rs, allocs);
1188
+ let tmp = format_reg(tmp.to_reg(), allocs);
1189
+ let rd = format_reg(rd.to_reg(), allocs);
1190
+ format!(
1191
+ "fcvt_to_{}int{}.{} {},{}##in_ty={} tmp={}",
1192
+ if is_signed { "s" } else { "u" },
1193
+ if is_sat { "_sat" } else { "" },
1194
+ out_type,
1195
+ rd,
1196
+ rs,
1197
+ in_type,
1198
+ tmp
1199
+ )
1200
+ }
1201
+ &Inst::SelectReg {
1202
+ rd,
1203
+ rs1,
1204
+ rs2,
1205
+ ref condition,
1206
+ } => {
1207
+ let c_rs1 = format_reg(condition.rs1, allocs);
1208
+ let c_rs2 = format_reg(condition.rs2, allocs);
1209
+ let rs1 = format_reg(rs1, allocs);
1210
+ let rs2 = format_reg(rs2, allocs);
1211
+ let rd = format_reg(rd.to_reg(), allocs);
1212
+ format!(
1213
+ "select_reg {},{},{}##condition={}",
1214
+ rd,
1215
+ rs1,
1216
+ rs2,
1217
+ format!("({} {} {})", c_rs1, condition.kind.to_static_str(), c_rs2),
1218
+ )
1219
+ }
1220
+ &Inst::AtomicCas {
1221
+ offset,
1222
+ t0,
1223
+ dst,
1224
+ e,
1225
+ addr,
1226
+ v,
1227
+ ty,
1228
+ } => {
1229
+ let offset = format_reg(offset, allocs);
1230
+ let e = format_reg(e, allocs);
1231
+ let addr = format_reg(addr, allocs);
1232
+ let v = format_reg(v, allocs);
1233
+ let t0 = format_reg(t0.to_reg(), allocs);
1234
+ let dst = format_reg(dst.to_reg(), allocs);
1235
+ format!(
1236
+ "atomic_cas.{} {},{},{},({})##t0={} offset={}",
1237
+ ty, dst, e, v, addr, t0, offset,
1238
+ )
1239
+ }
1240
+ &Inst::Icmp { cc, rd, a, b, ty } => {
1241
+ let a = format_regs(a.regs(), allocs);
1242
+ let b = format_regs(b.regs(), allocs);
1243
+ let rd = format_reg(rd.to_reg(), allocs);
1244
+ format!("{} {},{},{}##ty={}", cc.to_static_str(), rd, a, b, ty)
1245
+ }
1246
+ &Inst::IntSelect {
1247
+ op,
1248
+ ref dst,
1249
+ x,
1250
+ y,
1251
+ ty,
1252
+ } => {
1253
+ let x = format_regs(x.regs(), allocs);
1254
+ let y = format_regs(y.regs(), allocs);
1255
+ let dst: Vec<_> = dst.iter().map(|r| r.to_reg()).collect();
1256
+ let dst = format_regs(&dst[..], allocs);
1257
+ format!("{} {},{},{}##ty={}", op.op_name(), dst, x, y, ty,)
1258
+ }
1259
+ &Inst::BrTable {
1260
+ index,
1261
+ tmp1,
1262
+ tmp2,
1263
+ ref targets,
1264
+ } => {
1265
+ let targets: Vec<_> = targets.iter().map(|x| x.as_label().unwrap()).collect();
1266
+ format!(
1267
+ "{} {},{}##tmp1={},tmp2={}",
1268
+ "br_table",
1269
+ format_reg(index, allocs),
1270
+ format_labels(&targets[..]),
1271
+ format_reg(tmp1.to_reg(), allocs),
1272
+ format_reg(tmp2.to_reg(), allocs),
1273
+ )
1274
+ }
1275
+ &Inst::Auipc { rd, imm } => {
1276
+ format!(
1277
+ "{} {},{}",
1278
+ "auipc",
1279
+ format_reg(rd.to_reg(), allocs),
1280
+ imm.bits
1281
+ )
1282
+ }
1283
+ &Inst::Jalr { rd, base, offset } => {
1284
+ let base = format_reg(base, allocs);
1285
+ let rd = format_reg(rd.to_reg(), allocs);
1286
+ format!("{} {},{}({})", "jalr", rd, offset.bits, base)
1287
+ }
1288
+ &Inst::Lui { rd, ref imm } => {
1289
+ format!("{} {},{}", "lui", format_reg(rd.to_reg(), allocs), imm.bits)
1290
+ }
1291
+ &Inst::LoadConst32 { rd, imm } => {
1292
+ let rd = format_reg(rd.to_reg(), allocs);
1293
+ let mut buf = String::new();
1294
+ write!(&mut buf, "auipc {},0; ", rd).unwrap();
1295
+ write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
1296
+ write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 4).unwrap();
1297
+ write!(&mut buf, ".4byte 0x{:x}", imm).unwrap();
1298
+ buf
1299
+ }
1300
+ &Inst::LoadConst64 { rd, imm } => {
1301
+ let rd = format_reg(rd.to_reg(), allocs);
1302
+ let mut buf = String::new();
1303
+ write!(&mut buf, "auipc {},0; ", rd).unwrap();
1304
+ write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
1305
+ write!(&mut buf, "j {}; ", Inst::INSTRUCTION_SIZE + 8).unwrap();
1306
+ write!(&mut buf, ".8byte 0x{:x}", imm).unwrap();
1307
+ buf
1308
+ }
1309
+ &Inst::AluRRR {
1310
+ alu_op,
1311
+ rd,
1312
+ rs1,
1313
+ rs2,
1314
+ } => {
1315
+ let rs1_s = format_reg(rs1, allocs);
1316
+ let rs2_s = format_reg(rs2, allocs);
1317
+ let rd_s = format_reg(rd.to_reg(), allocs);
1318
+ match alu_op {
1319
+ AluOPRRR::Adduw if rs2 == zero_reg() => {
1320
+ format!("zext.w {},{}", rd_s, rs1_s)
1321
+ }
1322
+ _ => {
1323
+ format!("{} {},{},{}", alu_op.op_name(), rd_s, rs1_s, rs2_s)
1324
+ }
1325
+ }
1326
+ }
1327
+ &Inst::FpuRR {
1328
+ frm,
1329
+ alu_op,
1330
+ rd,
1331
+ rs,
1332
+ } => {
1333
+ let rs = format_reg(rs, allocs);
1334
+ let rd = format_reg(rd.to_reg(), allocs);
1335
+ format!("{} {},{}{}", alu_op.op_name(), rd, rs, format_frm(frm))
1336
+ }
1337
+ &Inst::FpuRRR {
1338
+ alu_op,
1339
+ rd,
1340
+ rs1,
1341
+ rs2,
1342
+ frm,
1343
+ } => {
1344
+ let rs1 = format_reg(rs1, allocs);
1345
+ let rs2 = format_reg(rs2, allocs);
1346
+ let rd = format_reg(rd.to_reg(), allocs);
1347
+ let rs1_is_rs2 = rs1 == rs2;
1348
+ if rs1_is_rs2 && alu_op.is_copy_sign() {
1349
+ // this is move instruction.
1350
+ format!(
1351
+ "fmv.{} {},{}",
1352
+ if alu_op.is_32() { "s" } else { "d" },
1353
+ rd,
1354
+ rs1
1355
+ )
1356
+ } else if rs1_is_rs2 && alu_op.is_copy_neg_sign() {
1357
+ format!(
1358
+ "fneg.{} {},{}",
1359
+ if alu_op.is_32() { "s" } else { "d" },
1360
+ rd,
1361
+ rs1
1362
+ )
1363
+ } else if rs1_is_rs2 && alu_op.is_copy_xor_sign() {
1364
+ format!(
1365
+ "fabs.{} {},{}",
1366
+ if alu_op.is_32() { "s" } else { "d" },
1367
+ rd,
1368
+ rs1
1369
+ )
1370
+ } else {
1371
+ format!(
1372
+ "{} {},{},{}{}",
1373
+ alu_op.op_name(),
1374
+ rd,
1375
+ rs1,
1376
+ rs2,
1377
+ format_frm(frm)
1378
+ )
1379
+ }
1380
+ }
1381
+ &Inst::FpuRRRR {
1382
+ alu_op,
1383
+ rd,
1384
+ rs1,
1385
+ rs2,
1386
+ rs3,
1387
+ frm,
1388
+ } => {
1389
+ let rs1 = format_reg(rs1, allocs);
1390
+ let rs2 = format_reg(rs2, allocs);
1391
+ let rs3 = format_reg(rs3, allocs);
1392
+ let rd = format_reg(rd.to_reg(), allocs);
1393
+ format!(
1394
+ "{} {},{},{},{}{}",
1395
+ alu_op.op_name(),
1396
+ rd,
1397
+ rs1,
1398
+ rs2,
1399
+ rs3,
1400
+ format_frm(frm)
1401
+ )
1402
+ }
1403
+ &Inst::AluRRImm12 {
1404
+ alu_op,
1405
+ rd,
1406
+ rs,
1407
+ ref imm12,
1408
+ } => {
1409
+ let rs_s = format_reg(rs, allocs);
1410
+ let rd = format_reg(rd.to_reg(), allocs);
1411
+
1412
+ // Some of these special cases are better known as
1413
+ // their pseudo-instruction version, so prefer printing those.
1414
+ match (alu_op, rs, imm12) {
1415
+ (AluOPRRI::Addi, rs, _) if rs == zero_reg() => {
1416
+ return format!("li {},{}", rd, imm12.as_i16());
1417
+ }
1418
+ (AluOPRRI::Addiw, _, imm12) if imm12.as_i16() == 0 => {
1419
+ return format!("sext.w {},{}", rd, rs_s);
1420
+ }
1421
+ (AluOPRRI::Xori, _, imm12) if imm12.as_i16() == -1 => {
1422
+ return format!("not {},{}", rd, rs_s);
1423
+ }
1424
+ (AluOPRRI::SltiU, _, imm12) if imm12.as_i16() == 1 => {
1425
+ return format!("seqz {},{}", rd, rs_s);
1426
+ }
1427
+ (alu_op, _, _) if alu_op.option_funct12().is_some() => {
1428
+ format!("{} {},{}", alu_op.op_name(), rd, rs_s)
1429
+ }
1430
+ (alu_op, _, imm12) => {
1431
+ format!("{} {},{},{}", alu_op.op_name(), rd, rs_s, imm12.as_i16())
1432
+ }
1433
+ }
1434
+ }
1435
+ &Inst::Load {
1436
+ rd,
1437
+ op,
1438
+ from,
1439
+ flags: _flags,
1440
+ } => {
1441
+ let base = from.to_string_with_alloc(allocs);
1442
+ let rd = format_reg(rd.to_reg(), allocs);
1443
+ format!("{} {},{}", op.op_name(), rd, base,)
1444
+ }
1445
+ &Inst::Store {
1446
+ to,
1447
+ src,
1448
+ op,
1449
+ flags: _flags,
1450
+ } => {
1451
+ let base = to.to_string_with_alloc(allocs);
1452
+ let src = format_reg(src, allocs);
1453
+ format!("{} {},{}", op.op_name(), src, base,)
1454
+ }
1455
+ &Inst::Args { ref args } => {
1456
+ let mut s = "args".to_string();
1457
+ let mut empty_allocs = AllocationConsumer::default();
1458
+ for arg in args {
1459
+ let preg = format_reg(arg.preg, &mut empty_allocs);
1460
+ let def = format_reg(arg.vreg.to_reg(), allocs);
1461
+ write!(&mut s, " {}={}", def, preg).unwrap();
1462
+ }
1463
+ s
1464
+ }
1465
+ &Inst::Ret {
1466
+ ref rets,
1467
+ stack_bytes_to_pop,
1468
+ } => {
1469
+ let mut s = if stack_bytes_to_pop == 0 {
1470
+ "ret".to_string()
1471
+ } else {
1472
+ format!("add sp, sp, #{stack_bytes_to_pop} ; ret")
1473
+ };
1474
+
1475
+ let mut empty_allocs = AllocationConsumer::default();
1476
+ for ret in rets {
1477
+ let preg = format_reg(ret.preg, &mut empty_allocs);
1478
+ let vreg = format_reg(ret.vreg, allocs);
1479
+ write!(&mut s, " {vreg}={preg}").unwrap();
1480
+ }
1481
+ s
1482
+ }
1483
+
1484
+ &MInst::Extend {
1485
+ rd,
1486
+ rn,
1487
+ signed,
1488
+ from_bits,
1489
+ ..
1490
+ } => {
1491
+ let rn = format_reg(rn, allocs);
1492
+ let rd = format_reg(rd.to_reg(), allocs);
1493
+ return if signed == false && from_bits == 8 {
1494
+ format!("andi {rd},{rn}")
1495
+ } else {
1496
+ let op = if signed { "srai" } else { "srli" };
1497
+ let shift_bits = (64 - from_bits) as i16;
1498
+ format!("slli {rd},{rn},{shift_bits}; {op} {rd},{rd},{shift_bits}")
1499
+ };
1500
+ }
1501
+ &MInst::AdjustSp { amount } => {
1502
+ format!("{} sp,{:+}", "add", amount)
1503
+ }
1504
+ &MInst::Call { ref info } => format!("call {}", info.dest.display(None)),
1505
+ &MInst::CallInd { ref info } => {
1506
+ let rd = format_reg(info.rn, allocs);
1507
+ format!("callind {}", rd)
1508
+ }
1509
+ &MInst::TrapIf { test, trap_code } => {
1510
+ format!("trap_if {},{}", format_reg(test, allocs), trap_code,)
1511
+ }
1512
+ &MInst::TrapIfC {
1513
+ rs1,
1514
+ rs2,
1515
+ cc,
1516
+ trap_code,
1517
+ } => {
1518
+ let rs1 = format_reg(rs1, allocs);
1519
+ let rs2 = format_reg(rs2, allocs);
1520
+ format!("trap_ifc {}##({} {} {})", trap_code, rs1, cc, rs2)
1521
+ }
1522
+ &MInst::Jal { dest, .. } => {
1523
+ format!("{} {}", "j", dest)
1524
+ }
1525
+ &MInst::CondBr {
1526
+ taken,
1527
+ not_taken,
1528
+ kind,
1529
+ ..
1530
+ } => {
1531
+ let rs1 = format_reg(kind.rs1, allocs);
1532
+ let rs2 = format_reg(kind.rs2, allocs);
1533
+ if not_taken.is_zero() && taken.as_label().is_none() {
1534
+ let off = taken.as_offset().unwrap();
1535
+ format!("{} {},{},{}", kind.op_name(), rs1, rs2, off)
1536
+ } else {
1537
+ let x = format!(
1538
+ "{} {},{},taken({}),not_taken({})",
1539
+ kind.op_name(),
1540
+ rs1,
1541
+ rs2,
1542
+ taken,
1543
+ not_taken
1544
+ );
1545
+ x
1546
+ }
1547
+ }
1548
+ &MInst::Atomic {
1549
+ op,
1550
+ rd,
1551
+ addr,
1552
+ src,
1553
+ amo,
1554
+ } => {
1555
+ let op_name = op.op_name(amo);
1556
+ let addr = format_reg(addr, allocs);
1557
+ let src = format_reg(src, allocs);
1558
+ let rd = format_reg(rd.to_reg(), allocs);
1559
+ if op.is_load() {
1560
+ format!("{} {},({})", op_name, rd, addr)
1561
+ } else {
1562
+ format!("{} {},{},({})", op_name, rd, src, addr)
1563
+ }
1564
+ }
1565
+ &MInst::LoadExtName {
1566
+ rd,
1567
+ ref name,
1568
+ offset,
1569
+ } => {
1570
+ let rd = format_reg(rd.to_reg(), allocs);
1571
+ format!("load_sym {},{}{:+}", rd, name.display(None), offset)
1572
+ }
1573
+ &MInst::LoadAddr { ref rd, ref mem } => {
1574
+ let rs = mem.to_string_with_alloc(allocs);
1575
+ let rd = format_reg(rd.to_reg(), allocs);
1576
+ format!("load_addr {},{}", rd, rs)
1577
+ }
1578
+ &MInst::VirtualSPOffsetAdj { amount } => {
1579
+ format!("virtual_sp_offset_adj {:+}", amount)
1580
+ }
1581
+ &MInst::Mov { rd, rm, ty } => {
1582
+ let rd = format_reg(rd.to_reg(), allocs);
1583
+ let rm = format_reg(rm, allocs);
1584
+ let v = if ty == F32 {
1585
+ "fmv.s"
1586
+ } else if ty == F64 {
1587
+ "fmv.d"
1588
+ } else {
1589
+ "mv"
1590
+ };
1591
+ format!("{} {},{}", v, rd, rm)
1592
+ }
1593
+ &MInst::MovFromPReg { rd, rm } => {
1594
+ let rd = format_reg(rd.to_reg(), allocs);
1595
+ debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
1596
+ let rm = reg_name(Reg::from(rm));
1597
+ format!("mv {},{}", rd, rm)
1598
+ }
1599
+ &MInst::Fence { pred, succ } => {
1600
+ format!(
1601
+ "fence {},{}",
1602
+ Inst::fence_req_to_string(pred),
1603
+ Inst::fence_req_to_string(succ),
1604
+ )
1605
+ }
1606
+ &MInst::FenceI => "fence.i".into(),
1607
+ &MInst::Select {
1608
+ ref dst,
1609
+ condition,
1610
+ ref x,
1611
+ ref y,
1612
+ ty,
1613
+ } => {
1614
+ let condition = format_reg(condition, allocs);
1615
+ let x = format_regs(x.regs(), allocs);
1616
+ let y = format_regs(y.regs(), allocs);
1617
+ let dst: Vec<_> = dst.clone().into_iter().map(|r| r.to_reg()).collect();
1618
+ let dst = format_regs(&dst[..], allocs);
1619
+ format!("select_{} {},{},{}##condition={}", ty, dst, x, y, condition)
1620
+ }
1621
+ &MInst::Udf { trap_code } => format!("udf##trap_code={}", trap_code),
1622
+ &MInst::EBreak {} => String::from("ebreak"),
1623
+ &MInst::ECall {} => String::from("ecall"),
1624
+ &Inst::VecAluRRR {
1625
+ op,
1626
+ vd,
1627
+ vs1,
1628
+ vs2,
1629
+ ref mask,
1630
+ ref vstate,
1631
+ } => {
1632
+ let vs1_s = format_reg(vs1, allocs);
1633
+ let vs2_s = format_reg(vs2, allocs);
1634
+ let vd_s = format_reg(vd.to_reg(), allocs);
1635
+ let mask = format_mask(mask, allocs);
1636
+
1637
+ // Note: vs2 and vs1 here are opposite to the standard scalar ordering.
1638
+ // This is noted in Section 10.1 of the RISC-V Vector spec.
1639
+ match (op, vs2, vs1) {
1640
+ (VecAluOpRRR::VrsubVX, _, vs1) if vs1 == zero_reg() => {
1641
+ format!("vneg.v {vd_s},{vs2_s}{mask} {vstate}")
1642
+ }
1643
+ (VecAluOpRRR::VfsgnjnVV, vs2, vs1) if vs2 == vs1 => {
1644
+ format!("vfneg.v {vd_s},{vs2_s}{mask} {vstate}")
1645
+ }
1646
+ _ => format!("{op} {vd_s},{vs2_s},{vs1_s}{mask} {vstate}"),
1647
+ }
1648
+ }
1649
+ &Inst::VecAluRRImm5 {
1650
+ op,
1651
+ vd,
1652
+ imm,
1653
+ vs2,
1654
+ ref mask,
1655
+ ref vstate,
1656
+ } => {
1657
+ let vs2_s = format_reg(vs2, allocs);
1658
+ let vd_s = format_reg(vd.to_reg(), allocs);
1659
+ let mask = format_mask(mask, allocs);
1660
+
1661
+ // Some opcodes interpret the immediate as unsigned, lets show the
1662
+ // correct number here.
1663
+ let imm_s = if op.imm_is_unsigned() {
1664
+ format!("{}", imm.bits())
1665
+ } else {
1666
+ format!("{}", imm)
1667
+ };
1668
+
1669
+ match (op, imm) {
1670
+ (VecAluOpRRImm5::VxorVI, imm) if imm == Imm5::maybe_from_i8(-1).unwrap() => {
1671
+ format!("vnot.v {vd_s},{vs2_s}{mask} {vstate}")
1672
+ }
1673
+ _ => format!("{op} {vd_s},{vs2_s},{imm_s}{mask} {vstate}"),
1674
+ }
1675
+ }
1676
+ &Inst::VecAluRR {
1677
+ op,
1678
+ vd,
1679
+ vs,
1680
+ ref mask,
1681
+ ref vstate,
1682
+ } => {
1683
+ let vs_s = format_reg(vs, allocs);
1684
+ let vd_s = format_reg(vd.to_reg(), allocs);
1685
+ let mask = format_mask(mask, allocs);
1686
+
1687
+ format!("{op} {vd_s},{vs_s}{mask} {vstate}")
1688
+ }
1689
+ &Inst::VecAluRImm5 {
1690
+ op,
1691
+ vd,
1692
+ imm,
1693
+ ref mask,
1694
+ ref vstate,
1695
+ } => {
1696
+ let vd_s = format_reg(vd.to_reg(), allocs);
1697
+ let mask = format_mask(mask, allocs);
1698
+
1699
+ format!("{op} {vd_s},{imm}{mask} {vstate}")
1700
+ }
1701
+ &Inst::VecSetState { rd, ref vstate } => {
1702
+ let rd_s = format_reg(rd.to_reg(), allocs);
1703
+ assert!(vstate.avl.is_static());
1704
+ format!("vsetivli {}, {}, {}", rd_s, vstate.avl, vstate.vtype)
1705
+ }
1706
+ Inst::VecLoad {
1707
+ eew,
1708
+ to,
1709
+ from,
1710
+ ref mask,
1711
+ ref vstate,
1712
+ ..
1713
+ } => {
1714
+ let base = format_vec_amode(from, allocs);
1715
+ let vd = format_reg(to.to_reg(), allocs);
1716
+ let mask = format_mask(mask, allocs);
1717
+
1718
+ format!("vl{eew}.v {vd},{base}{mask} {vstate}")
1719
+ }
1720
+ Inst::VecStore {
1721
+ eew,
1722
+ to,
1723
+ from,
1724
+ ref mask,
1725
+ ref vstate,
1726
+ ..
1727
+ } => {
1728
+ let dst = format_vec_amode(to, allocs);
1729
+ let vs3 = format_reg(*from, allocs);
1730
+ let mask = format_mask(mask, allocs);
1731
+
1732
+ format!("vs{eew}.v {vs3},{dst}{mask} {vstate}")
1733
+ }
1734
+ }
1735
+ }
1736
+ }
1737
+
1738
+ /// Different forms of label references for different instruction formats.
1739
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1740
+ pub enum LabelUse {
1741
+ /// 20-bit branch offset (unconditional branches). PC-rel, offset is
1742
+ /// imm << 1. Immediate is 20 signed bits. Use in Jal instructions.
1743
+ Jal20,
1744
+
1745
+ /// The unconditional jump instructions all use PC-relative
1746
+ /// addressing to help support position independent code. The JALR
1747
+ /// instruction was defined to enable a two-instruction sequence to
1748
+ /// jump anywhere in a 32-bit absolute address range. A LUI
1749
+ /// instruction can first load rs1 with the upper 20 bits of a
1750
+ /// target address, then JALR can add in the lower bits. Similarly,
1751
+ /// AUIPC then JALR can jump anywhere in a 32-bit pc-relative
1752
+ /// address range.
1753
+ PCRel32,
1754
+
1755
+ /// All branch instructions use the B-type instruction format. The
1756
+ /// 12-bit B-immediate encodes signed offsets in multiples of 2, and
1757
+ /// is added to the current pc to give the target address. The
1758
+ /// conditional branch range is ±4 KiB.
1759
+ B12,
1760
+
1761
+ /// Equivalent to the `R_RISCV_PCREL_HI20` relocation, Allows setting
1762
+ /// the immediate field of an `auipc` instruction.
1763
+ PCRelHi20,
1764
+
1765
+ /// Similar to the `R_RISCV_PCREL_LO12_I` relocation but pointing to
1766
+ /// the final address, instead of the `PCREL_HI20` label. Allows setting
1767
+ /// the immediate field of I Type instructions such as `addi` or `lw`.
1768
+ ///
1769
+ /// Since we currently don't support offsets in labels, this relocation has
1770
+ /// an implicit offset of 4.
1771
+ PCRelLo12I,
1772
+ }
1773
+
1774
+ impl MachInstLabelUse for LabelUse {
1775
+ /// Alignment for veneer code. Every Riscv64 instruction must be
1776
+ /// 4-byte-aligned.
1777
+ const ALIGN: CodeOffset = 4;
1778
+
1779
+ /// Maximum PC-relative range (positive), inclusive.
1780
+ fn max_pos_range(self) -> CodeOffset {
1781
+ match self {
1782
+ LabelUse::Jal20 => ((1 << 19) - 1) * 2,
1783
+ LabelUse::PCRelLo12I | LabelUse::PCRelHi20 | LabelUse::PCRel32 => {
1784
+ Inst::imm_max() as CodeOffset
1785
+ }
1786
+ LabelUse::B12 => ((1 << 11) - 1) * 2,
1787
+ }
1788
+ }
1789
+
1790
+ /// Maximum PC-relative range (negative).
1791
+ fn max_neg_range(self) -> CodeOffset {
1792
+ match self {
1793
+ LabelUse::PCRel32 => Inst::imm_min().abs() as CodeOffset,
1794
+ _ => self.max_pos_range() + 2,
1795
+ }
1796
+ }
1797
+
1798
+ /// Size of window into code needed to do the patch.
1799
+ fn patch_size(self) -> CodeOffset {
1800
+ match self {
1801
+ LabelUse::Jal20 | LabelUse::B12 | LabelUse::PCRelHi20 | LabelUse::PCRelLo12I => 4,
1802
+ LabelUse::PCRel32 => 8,
1803
+ }
1804
+ }
1805
+
1806
+ /// Perform the patch.
1807
+ fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
1808
+ assert!(use_offset % 4 == 0);
1809
+ assert!(label_offset % 4 == 0);
1810
+ let offset = (label_offset as i64) - (use_offset as i64);
1811
+
1812
+ // re-check range
1813
+ assert!(
1814
+ offset >= -(self.max_neg_range() as i64) && offset <= (self.max_pos_range() as i64),
1815
+ "{:?} offset '{}' use_offset:'{}' label_offset:'{}' must not exceed max range.",
1816
+ self,
1817
+ offset,
1818
+ use_offset,
1819
+ label_offset,
1820
+ );
1821
+ self.patch_raw_offset(buffer, offset);
1822
+ }
1823
+
1824
+ /// Is a veneer supported for this label reference type?
1825
+ fn supports_veneer(self) -> bool {
1826
+ match self {
1827
+ Self::Jal20 | Self::B12 => true,
1828
+ _ => false,
1829
+ }
1830
+ }
1831
+
1832
+ /// How large is the veneer, if supported?
1833
+ fn veneer_size(self) -> CodeOffset {
1834
+ match self {
1835
+ Self::B12 | Self::Jal20 => 8,
1836
+ _ => unreachable!(),
1837
+ }
1838
+ }
1839
+
1840
+ /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
1841
+ /// an offset and label-use for the veneer's use of the original label.
1842
+ fn generate_veneer(
1843
+ self,
1844
+ buffer: &mut [u8],
1845
+ veneer_offset: CodeOffset,
1846
+ ) -> (CodeOffset, LabelUse) {
1847
+ let base = writable_spilltmp_reg();
1848
+ {
1849
+ let x = enc_auipc(base, Imm20::from_bits(0)).to_le_bytes();
1850
+ buffer[0] = x[0];
1851
+ buffer[1] = x[1];
1852
+ buffer[2] = x[2];
1853
+ buffer[3] = x[3];
1854
+ }
1855
+ {
1856
+ let x = enc_jalr(writable_zero_reg(), base.to_reg(), Imm12::from_bits(0)).to_le_bytes();
1857
+ buffer[4] = x[0];
1858
+ buffer[5] = x[1];
1859
+ buffer[6] = x[2];
1860
+ buffer[7] = x[3];
1861
+ }
1862
+ (veneer_offset, Self::PCRel32)
1863
+ }
1864
+
1865
+ fn from_reloc(reloc: Reloc, addend: Addend) -> Option<LabelUse> {
1866
+ match (reloc, addend) {
1867
+ (Reloc::RiscvCall, _) => Some(Self::PCRel32),
1868
+ _ => None,
1869
+ }
1870
+ }
1871
+ }
1872
+
1873
+ impl LabelUse {
1874
+ fn offset_in_range(self, offset: i64) -> bool {
1875
+ let min = -(self.max_neg_range() as i64);
1876
+ let max = self.max_pos_range() as i64;
1877
+ offset >= min && offset <= max
1878
+ }
1879
+
1880
+ fn patch_raw_offset(self, buffer: &mut [u8], offset: i64) {
1881
+ let insn = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
1882
+ match self {
1883
+ LabelUse::Jal20 => {
1884
+ let offset = offset as u32;
1885
+ let v = ((offset >> 12 & 0b1111_1111) << 12)
1886
+ | ((offset >> 11 & 0b1) << 20)
1887
+ | ((offset >> 1 & 0b11_1111_1111) << 21)
1888
+ | ((offset >> 20 & 0b1) << 31);
1889
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn | v));
1890
+ }
1891
+ LabelUse::PCRel32 => {
1892
+ let insn2 = u32::from_le_bytes([buffer[4], buffer[5], buffer[6], buffer[7]]);
1893
+ Inst::generate_imm(offset as u64, |imm20, imm12| {
1894
+ let imm20 = imm20.unwrap_or_default();
1895
+ let imm12 = imm12.unwrap_or_default();
1896
+ // Encode the OR-ed-in value with zero_reg(). The
1897
+ // register parameter must be in the original
1898
+ // encoded instruction and or'ing in zeroes does not
1899
+ // change it.
1900
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(
1901
+ insn | enc_auipc(writable_zero_reg(), imm20),
1902
+ ));
1903
+ buffer[4..8].clone_from_slice(&u32::to_le_bytes(
1904
+ insn2 | enc_jalr(writable_zero_reg(), zero_reg(), imm12),
1905
+ ));
1906
+ })
1907
+ // expect make sure we handled.
1908
+ .expect("we have check the range before,this is a compiler error.");
1909
+ }
1910
+
1911
+ LabelUse::B12 => {
1912
+ let offset = offset as u32;
1913
+ let v = ((offset >> 11 & 0b1) << 7)
1914
+ | ((offset >> 1 & 0b1111) << 8)
1915
+ | ((offset >> 5 & 0b11_1111) << 25)
1916
+ | ((offset >> 12 & 0b1) << 31);
1917
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn | v));
1918
+ }
1919
+
1920
+ LabelUse::PCRelHi20 => {
1921
+ // See https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
1922
+ //
1923
+ // We need to add 0x800 to ensure that we land at the next page as soon as it goes out of range for the
1924
+ // Lo12 relocation. That relocation is signed and has a maximum range of -2048..2047. So when we get an
1925
+ // offset of 2048, we need to land at the next page and subtract instead.
1926
+ let offset = offset as u32;
1927
+ let hi20 = offset.wrapping_add(0x800) >> 12;
1928
+ let insn = (insn & 0xFFF) | (hi20 << 12);
1929
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
1930
+ }
1931
+
1932
+ LabelUse::PCRelLo12I => {
1933
+ // `offset` is the offset from the current instruction to the target address.
1934
+ //
1935
+ // However we are trying to compute the offset to the target address from the previous instruction.
1936
+ // The previous instruction should be the one that contains the PCRelHi20 relocation and
1937
+ // stores/references the program counter (`auipc` usually).
1938
+ //
1939
+ // Since we are trying to compute the offset from the previous instruction, we can
1940
+ // represent it as offset = target_address - (current_instruction_address - 4)
1941
+ // which is equivalent to offset = target_address - current_instruction_address + 4.
1942
+ //
1943
+ // Thus we need to add 4 to the offset here.
1944
+ let lo12 = (offset + 4) as u32 & 0xFFF;
1945
+ let insn = (insn & 0xFFFFF) | (lo12 << 20);
1946
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
1947
+ }
1948
+ }
1949
+ }
1950
+ }
1951
+
1952
+ #[cfg(test)]
1953
+ mod test {
1954
+ use super::*;
1955
+ #[test]
1956
+ fn label_use_max_range() {
1957
+ assert!(LabelUse::B12.max_neg_range() == LabelUse::B12.max_pos_range() + 2);
1958
+ assert!(LabelUse::Jal20.max_neg_range() == LabelUse::Jal20.max_pos_range() + 2);
1959
+ assert!(LabelUse::PCRel32.max_pos_range() == (Inst::imm_max() as CodeOffset));
1960
+ assert!(LabelUse::PCRel32.max_neg_range() == (Inst::imm_min().abs() as CodeOffset));
1961
+ assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2);
1962
+ }
1963
+ }