wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,1409 @@
1
+ ;; riscv64 instruction selection and CLIF-to-MachInst lowering.
2
+
3
+ ;; The main lowering constructor term: takes a clif `Inst` and returns the
4
+ ;; register(s) within which the lowered instruction's result values live.
5
+ (decl partial lower (Inst) InstOutput)
6
+
7
+ ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8
+
9
+ (rule (lower (has_type ty (iconst (u64_from_imm64 n))))
10
+ (imm ty n))
11
+
12
+ ;; ;;;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13
+
14
+ (rule (lower (has_type (ty_vec_fits_in_register ty) (vconst n)))
15
+ (vec_load
16
+ (element_width_from_type ty)
17
+ (VecAMode.UnitStride (gen_const_amode (const_to_vconst n)))
18
+ (mem_flags_trusted)
19
+ (unmasked)
20
+ ty))
21
+
22
+ ;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
23
+
24
+ (rule (lower (f32const (u32_from_ieee32 n)))
25
+ (imm $F32 n))
26
+
27
+ ;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
28
+
29
+ (rule (lower (f64const (u64_from_ieee64 n)))
30
+ (imm $F64 n))
31
+
32
+ ;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
33
+
34
+ (rule (lower (has_type ty (null)))
35
+ (imm ty 0))
36
+
37
+
38
+ ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
39
+
40
+ ;; Base case, simply adding things in registers.
41
+ (rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (iadd x y)))
42
+ (rv_add x y))
43
+
44
+ ;; Special cases for when one operand is an immediate that fits in 12 bits.
45
+ (rule 1 (lower (has_type (ty_int_ref_scalar_64 ty) (iadd x (imm12_from_value y))))
46
+ (alu_rr_imm12 (select_addi ty) x y))
47
+
48
+ (rule 2 (lower (has_type (ty_int_ref_scalar_64 ty) (iadd (imm12_from_value x) y)))
49
+ (alu_rr_imm12 (select_addi ty) y x))
50
+
51
+ ;; Special case when one of the operands is uextended
52
+ ;; Needs `Zba`
53
+ (rule 3 (lower (has_type $I64 (iadd x (uextend y @ (value_type $I32)))))
54
+ (if-let $true (has_zba))
55
+ (rv_adduw y x))
56
+
57
+ (rule 4 (lower (has_type $I64 (iadd (uextend x @ (value_type $I32)) y)))
58
+ (if-let $true (has_zba))
59
+ (rv_adduw x y))
60
+
61
+ ;; Add with const shift. We have a few of these instructions with `Zba`.
62
+ (decl pure partial match_shnadd (Imm64) AluOPRRR)
63
+ (rule (match_shnadd (u64_from_imm64 1)) (AluOPRRR.Sh1add))
64
+ (rule (match_shnadd (u64_from_imm64 2)) (AluOPRRR.Sh2add))
65
+ (rule (match_shnadd (u64_from_imm64 3)) (AluOPRRR.Sh3add))
66
+
67
+ (rule 3 (lower (has_type $I64 (iadd x (ishl y (maybe_uextend (iconst n))))))
68
+ (if-let $true (has_zba))
69
+ (if-let shnadd (match_shnadd n))
70
+ (alu_rrr shnadd y x))
71
+
72
+ (rule 4 (lower (has_type $I64 (iadd (ishl x (maybe_uextend (iconst n))) y)))
73
+ (if-let $true (has_zba))
74
+ (if-let shnadd (match_shnadd n))
75
+ (alu_rrr shnadd x y))
76
+
77
+
78
+ ;; Add with uextended const shift. We have a few of these instructions with `Zba`.
79
+ ;;
80
+ ;; !!! Important !!!
81
+ ;; These rules only work for (ishl (uextend _) _) and not for (uextend (ishl _ _))!
82
+ ;; Getting this wrong means a potential misscalculation of the shift amount.
83
+ ;; Additionaly we can only ensure that this is correct if the uextend is 32 to 64 bits.
84
+ (decl pure partial match_shnadd_uw (Imm64) AluOPRRR)
85
+ (rule (match_shnadd_uw (u64_from_imm64 1)) (AluOPRRR.Sh1adduw))
86
+ (rule (match_shnadd_uw (u64_from_imm64 2)) (AluOPRRR.Sh2adduw))
87
+ (rule (match_shnadd_uw (u64_from_imm64 3)) (AluOPRRR.Sh3adduw))
88
+
89
+ (rule 5 (lower (has_type $I64 (iadd x (ishl (uextend y @ (value_type $I32)) (maybe_uextend (iconst n))))))
90
+ (if-let $true (has_zba))
91
+ (if-let shnadd_uw (match_shnadd_uw n))
92
+ (alu_rrr shnadd_uw y x))
93
+
94
+ (rule 6 (lower (has_type $I64 (iadd (ishl (uextend x @ (value_type $I32)) (maybe_uextend (iconst n))) y)))
95
+ (if-let $true (has_zba))
96
+ (if-let shnadd_uw (match_shnadd_uw n))
97
+ (alu_rrr shnadd_uw x y))
98
+
99
+ ;; I128 cases
100
+ (rule 7 (lower (has_type $I128 (iadd x y)))
101
+ (let ((low XReg (rv_add (value_regs_get x 0) (value_regs_get y 0)))
102
+ ;; compute carry.
103
+ (carry XReg (rv_sltu low (value_regs_get y 0)))
104
+ ;;
105
+ (high_tmp XReg (rv_add (value_regs_get x 1) (value_regs_get y 1)))
106
+ ;; add carry.
107
+ (high XReg (rv_add high_tmp carry)))
108
+ (value_regs low high)))
109
+
110
+ ;; SIMD Vectors
111
+ (rule 8 (lower (has_type (ty_vec_fits_in_register ty) (iadd x y)))
112
+ (rv_vadd_vv x y (unmasked) ty))
113
+
114
+ (rule 9 (lower (has_type (ty_vec_fits_in_register ty) (iadd x (splat y))))
115
+ (rv_vadd_vx x y (unmasked) ty))
116
+
117
+ (rule 10 (lower (has_type (ty_vec_fits_in_register ty) (iadd (splat x) y)))
118
+ (rv_vadd_vx y x (unmasked) ty))
119
+
120
+ (rule 11 (lower (has_type (ty_vec_fits_in_register ty) (iadd x (replicated_imm5 y))))
121
+ (rv_vadd_vi x y (unmasked) ty))
122
+
123
+ (rule 12 (lower (has_type (ty_vec_fits_in_register ty) (iadd (replicated_imm5 x) y)))
124
+ (rv_vadd_vi y x (unmasked) ty))
125
+
126
+ ;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;
127
+ (rule
128
+ (lower (has_type (fits_in_64 ty) (uadd_overflow_trap x y tc)))
129
+ (let ((res ValueRegs (lower_uadd_overflow x y ty))
130
+ (_ InstOutput (gen_trapif (value_regs_get res 1) tc)))
131
+ (value_regs_get res 0)))
132
+
133
+
134
+ ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
135
+ ;; Base case, simply subtracting things in registers.
136
+
137
+ (rule (lower (has_type (ty_int_ref_scalar_64 ty) (isub x y)))
138
+ (rv_sub x y))
139
+
140
+ (rule 1 (lower (has_type (fits_in_32 (ty_int ty)) (isub x y)))
141
+ (rv_subw x y))
142
+
143
+ (rule 2 (lower (has_type $I128 (isub x y)))
144
+ (i128_sub x y))
145
+
146
+ ;; SIMD Vectors
147
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (isub x y)))
148
+ (rv_vsub_vv x y (unmasked) ty))
149
+
150
+ (rule 4 (lower (has_type (ty_vec_fits_in_register ty) (isub x (splat y))))
151
+ (rv_vsub_vx x y (unmasked) ty))
152
+
153
+ (rule 5 (lower (has_type (ty_vec_fits_in_register ty) (isub (splat x) y)))
154
+ (rv_vrsub_vx y x (unmasked) ty))
155
+
156
+ (rule 6 (lower (has_type (ty_vec_fits_in_register ty) (isub (replicated_imm5 x) y)))
157
+ (rv_vrsub_vi y x (unmasked) ty))
158
+
159
+
160
+ ;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
161
+
162
+ (rule (lower (has_type (ty_int ty) (ineg val)))
163
+ (neg ty val))
164
+
165
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (ineg x)))
166
+ (rv_vneg_v x (unmasked) ty))
167
+
168
+
169
+ ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
170
+
171
+ (rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (imul x y)))
172
+ (rv_mul x y))
173
+
174
+ (rule 1 (lower (has_type (fits_in_32 (ty_int ty)) (imul x y)))
175
+ (rv_mulw x y))
176
+
177
+ ;; for I128
178
+ (rule 2 (lower (has_type $I128 (imul x y)))
179
+ (let
180
+ ((x_regs ValueRegs x)
181
+ (x_lo XReg (value_regs_get x_regs 0))
182
+ (x_hi XReg (value_regs_get x_regs 1))
183
+
184
+ ;; Get the high/low registers for `y`.
185
+ (y_regs ValueRegs y)
186
+ (y_lo XReg (value_regs_get y_regs 0))
187
+ (y_hi XReg (value_regs_get y_regs 1))
188
+
189
+ ;; 128bit mul formula:
190
+ ;; dst_lo = x_lo * y_lo
191
+ ;; dst_hi = mulhu(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
192
+ ;;
193
+ ;; We can convert the above formula into the following
194
+ ;; mulhu dst_hi, x_lo, y_lo
195
+ ;; madd dst_hi, x_lo, y_hi, dst_hi
196
+ ;; madd dst_hi, x_hi, y_lo, dst_hi
197
+ ;; madd dst_lo, x_lo, y_lo, zero
198
+ (dst_hi1 XReg (rv_mulhu x_lo y_lo))
199
+ (dst_hi2 XReg (madd x_lo y_hi dst_hi1))
200
+ (dst_hi XReg (madd x_hi y_lo dst_hi2))
201
+ (dst_lo XReg (madd x_lo y_lo (zero_reg))))
202
+ (value_regs dst_lo dst_hi)))
203
+
204
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (imul x y)))
205
+ (rv_vmul_vv x y (unmasked) ty))
206
+
207
+ ;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
208
+ (rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (smulhi x y)))
209
+ (lower_smlhi ty (sext x ty $I64) (sext y ty $I64)))
210
+
211
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smulhi x y)))
212
+ (rv_vmulh_vv x y (unmasked) ty))
213
+
214
+ ;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215
+ (rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (umulhi x y)))
216
+ (lower_umlhi ty (zext x ty $I64) (zext y ty $I64)))
217
+
218
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umulhi x y)))
219
+ (rv_vmulhu_vv x y (unmasked) ty))
220
+
221
+ ;;;; Rules for `div` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
222
+
223
+ (rule -1 (lower (has_type (fits_in_32 ty) (udiv x y)))
224
+ (let
225
+ ((y2 XReg (zext y ty $I64))
226
+ (_ InstOutput (gen_div_by_zero y2)))
227
+ (rv_divuw (zext x ty $I64) y2)))
228
+
229
+ (rule -1 (lower (has_type (fits_in_32 ty) (sdiv x y)))
230
+ (let
231
+ ((a XReg (sext x ty $I64))
232
+ (b XReg (sext y ty $I64))
233
+ (_ InstOutput (gen_div_overflow a b ty))
234
+ (_ InstOutput (gen_div_by_zero b)))
235
+ (rv_divw a b)))
236
+
237
+ (rule (lower (has_type $I64 (sdiv x y)))
238
+ (let
239
+ ((_ InstOutput (gen_div_overflow x y $I64))
240
+ (_ InstOutput (gen_div_by_zero y)) )
241
+ (rv_div x y)))
242
+
243
+ (rule (lower (has_type $I64 (udiv x y)))
244
+ (let
245
+ ((_ InstOutput (gen_div_by_zero y)))
246
+ (rv_divu x y)))
247
+
248
+ ;;;; Rules for `rem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
249
+
250
+ (rule -1 (lower (has_type (fits_in_16 ty) (urem x y)))
251
+ (let
252
+ ((y2 XReg (zext y ty $I64))
253
+ (_ InstOutput (gen_div_by_zero y2)))
254
+ (rv_remuw (zext x ty $I64) y2)))
255
+
256
+ (rule -1 (lower (has_type (fits_in_16 ty) (srem x y)))
257
+ (let
258
+ ((y2 XReg (sext y ty $I64))
259
+ (_ InstOutput (gen_div_by_zero y2)))
260
+ (rv_remw (sext x ty $I64) y2)))
261
+
262
+ (rule (lower (has_type $I32 (srem x y)))
263
+ (let
264
+ ((y2 XReg (sext y $I32 $I64))
265
+ (_ InstOutput (gen_div_by_zero y2)))
266
+ (rv_remw x y2)))
267
+
268
+ (rule (lower (has_type $I32 (urem x y)))
269
+ (let
270
+ ((y2 XReg (zext y $I32 $I64))
271
+ (_ InstOutput (gen_div_by_zero y2)))
272
+ (rv_remuw x y2)))
273
+
274
+ (rule (lower (has_type $I64 (srem x y)))
275
+ (let
276
+ ((_ InstOutput (gen_div_by_zero y)))
277
+ (rv_rem x y)))
278
+
279
+ (rule (lower (has_type $I64 (urem x y)))
280
+ (let
281
+ ((_ InstOutput (gen_div_by_zero y)))
282
+ (rv_remu x y)))
283
+
284
+ ;;;; Rules for `and` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
285
+ (rule 0 (lower (has_type (ty_int ty) (band x y)))
286
+ (gen_and ty x y))
287
+
288
+ ;; Special cases for when one operand is an immediate that fits in 12 bits.
289
+ (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (band x (imm12_from_value y))))
290
+ (rv_andi x y))
291
+
292
+ (rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (band (imm12_from_value x) y)))
293
+ (rv_andi y x))
294
+
295
+ (rule 3 (lower (has_type (ty_scalar_float ty) (band x y)))
296
+ (lower_float_binary (AluOPRRR.And) x y ty))
297
+
298
+ ;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
299
+ ;; by Cranelift's `band_not` instruction that is legalized into the simpler
300
+ ;; forms early on.
301
+
302
+ (rule 4 (lower (has_type (fits_in_64 (ty_int ty)) (band x (bnot y))))
303
+ (if-let $true (has_zbb))
304
+ (rv_andn x y))
305
+
306
+ (rule 5 (lower (has_type (fits_in_64 (ty_int ty)) (band (bnot y) x)))
307
+ (if-let $true (has_zbb))
308
+ (rv_andn x y))
309
+
310
+ (rule 6 (lower (has_type $I128 (band x (bnot y))))
311
+ (if-let $true (has_zbb))
312
+ (let ((low XReg (rv_andn (value_regs_get x 0) (value_regs_get y 0)))
313
+ (high XReg (rv_andn (value_regs_get x 1) (value_regs_get y 1))))
314
+ (value_regs low high)))
315
+
316
+ (rule 7 (lower (has_type $I128 (band (bnot y) x)))
317
+ (if-let $true (has_zbb))
318
+ (let ((low XReg (rv_andn (value_regs_get x 0) (value_regs_get y 0)))
319
+ (high XReg (rv_andn (value_regs_get x 1) (value_regs_get y 1))))
320
+ (value_regs low high)))
321
+
322
+ (rule 8 (lower (has_type (ty_vec_fits_in_register ty) (band x y)))
323
+ (rv_vand_vv x y (unmasked) ty))
324
+
325
+ (rule 9 (lower (has_type (ty_vec_fits_in_register ty) (band x (splat y))))
326
+ (if (ty_vector_not_float ty))
327
+ (rv_vand_vx x y (unmasked) ty))
328
+
329
+ (rule 10 (lower (has_type (ty_vec_fits_in_register ty) (band (splat x) y)))
330
+ (if (ty_vector_not_float ty))
331
+ (rv_vand_vx y x (unmasked) ty))
332
+
333
+ (rule 11 (lower (has_type (ty_vec_fits_in_register ty) (band x (replicated_imm5 y))))
334
+ (rv_vand_vi x y (unmasked) ty))
335
+
336
+ (rule 12 (lower (has_type (ty_vec_fits_in_register ty) (band (replicated_imm5 x) y)))
337
+ (rv_vand_vi y x (unmasked) ty))
338
+
339
+
340
+ ;;;; Rules for `or` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
341
+ (rule 0 (lower (has_type (ty_int ty) (bor x y)))
342
+ (gen_or ty x y))
343
+
344
+ ;; Special cases for when one operand is an immediate that fits in 12 bits.
345
+ (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bor x (imm12_from_value y))))
346
+ (rv_ori x y))
347
+
348
+ (rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (bor (imm12_from_value x) y)))
349
+ (rv_ori y x))
350
+
351
+ (rule 3 (lower (has_type (ty_scalar_float ty) (bor x y)))
352
+ (lower_float_binary (AluOPRRR.Or) x y ty))
353
+
354
+ ;; Specialized lowerings for `(bor x (bnot y))` which is additionally produced
355
+ ;; by Cranelift's `bor_not` instruction that is legalized into the simpler
356
+ ;; forms early on.
357
+
358
+ (rule 4 (lower (has_type (fits_in_64 (ty_int ty)) (bor x (bnot y))))
359
+ (if-let $true (has_zbb))
360
+ (rv_orn x y))
361
+
362
+ (rule 5 (lower (has_type (fits_in_64 (ty_int ty)) (bor (bnot y) x)))
363
+ (if-let $true (has_zbb))
364
+ (rv_orn x y))
365
+
366
+ (rule 6 (lower (has_type $I128 (bor x (bnot y))))
367
+ (if-let $true (has_zbb))
368
+ (let ((low XReg (rv_orn (value_regs_get x 0) (value_regs_get y 0)))
369
+ (high XReg (rv_orn (value_regs_get x 1) (value_regs_get y 1))))
370
+ (value_regs low high)))
371
+
372
+ (rule 7 (lower (has_type $I128 (bor (bnot y) x)))
373
+ (if-let $true (has_zbb))
374
+ (let ((low XReg (rv_orn (value_regs_get x 0) (value_regs_get y 0)))
375
+ (high XReg (rv_orn (value_regs_get x 1) (value_regs_get y 1))))
376
+ (value_regs low high)))
377
+
378
+ (rule 8 (lower (has_type (ty_vec_fits_in_register ty) (bor x y)))
379
+ (rv_vor_vv x y (unmasked) ty))
380
+
381
+ (rule 9 (lower (has_type (ty_vec_fits_in_register ty) (bor x (splat y))))
382
+ (if (ty_vector_not_float ty))
383
+ (rv_vor_vx x y (unmasked) ty))
384
+
385
+ (rule 10 (lower (has_type (ty_vec_fits_in_register ty) (bor (splat x) y)))
386
+ (if (ty_vector_not_float ty))
387
+ (rv_vor_vx y x (unmasked) ty))
388
+
389
+ (rule 11 (lower (has_type (ty_vec_fits_in_register ty) (bor x (replicated_imm5 y))))
390
+ (rv_vor_vi x y (unmasked) ty))
391
+
392
+ (rule 12 (lower (has_type (ty_vec_fits_in_register ty) (bor (replicated_imm5 x) y)))
393
+ (rv_vor_vi y x (unmasked) ty))
394
+
395
+
396
+ ;;;; Rules for `xor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
397
+ (rule 0 (lower (has_type (fits_in_64 (ty_int ty)) (bxor x y)))
398
+ (rv_xor x y))
399
+
400
+ ;; Special cases for when one operand is an immediate that fits in 12 bits.
401
+ (rule 1 (lower (has_type (fits_in_64 (ty_int ty)) (bxor x (imm12_from_value y))))
402
+ (rv_xori x y))
403
+
404
+ (rule 2 (lower (has_type (fits_in_64 (ty_int ty)) (bxor (imm12_from_value x) y)))
405
+ (rv_xori y x))
406
+
407
+ (rule 3 (lower (has_type $I128 (bxor x y)))
408
+ (lower_b128_binary (AluOPRRR.Xor) x y))
409
+
410
+ (rule 4 (lower (has_type (ty_scalar_float ty) (bxor x y)))
411
+ (lower_float_binary (AluOPRRR.Xor) x y ty))
412
+
413
+ (rule 5 (lower (has_type (ty_vec_fits_in_register ty) (bxor x y)))
414
+ (rv_vxor_vv x y (unmasked) ty))
415
+
416
+ (rule 6 (lower (has_type (ty_vec_fits_in_register ty) (bxor x (splat y))))
417
+ (if (ty_vector_not_float ty))
418
+ (rv_vxor_vx x y (unmasked) ty))
419
+
420
+ (rule 7 (lower (has_type (ty_vec_fits_in_register ty) (bxor (splat x) y)))
421
+ (if (ty_vector_not_float ty))
422
+ (rv_vxor_vx y x (unmasked) ty))
423
+
424
+ (rule 8 (lower (has_type (ty_vec_fits_in_register ty) (bxor x (replicated_imm5 y))))
425
+ (rv_vxor_vi x y (unmasked) ty))
426
+
427
+ (rule 9 (lower (has_type (ty_vec_fits_in_register ty) (bxor (replicated_imm5 x) y)))
428
+ (rv_vxor_vi y x (unmasked) ty))
429
+
430
+
431
+ ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
432
+ (rule 0 (lower (has_type (ty_scalar ty) (bnot x)))
433
+ (gen_bnot ty x))
434
+
435
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (bnot x)))
436
+ (rv_vnot_v x (unmasked) ty))
437
+
438
+ ;;;; Rules for `bit_reverse` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
439
+ (rule (lower (has_type (fits_in_64 (ty_int ty)) (bitrev x)))
440
+ (lower_bit_reverse x ty))
441
+
442
+ (rule 1 (lower (has_type $I128 (bitrev x)))
443
+ (let ((val ValueRegs x)
444
+ (lo_rev XReg (lower_bit_reverse (value_regs_get val 0) $I64))
445
+ (hi_rev XReg (lower_bit_reverse (value_regs_get val 1) $I64)))
446
+ (value_regs hi_rev lo_rev)))
447
+
448
+
449
+ ;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
450
+ (rule (lower (has_type (fits_in_64 ty) (ctz x)))
451
+ (lower_ctz ty x))
452
+
453
+ (rule 1 (lower (has_type $I128 (ctz x)))
454
+ (lower_ctz_128 x))
455
+
456
+ ;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
457
+ (rule (lower (has_type (fits_in_64 ty) (clz x)))
458
+ (lower_clz ty x))
459
+
460
+ (rule 1 (lower (has_type $I128 (clz x)))
461
+ (lower_clz_i128 x))
462
+
463
+ ;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
464
+ (rule (lower (has_type (fits_in_64 ty) (cls x)))
465
+ (lower_cls ty x))
466
+
467
+ (rule 1 (lower (has_type $I128 (cls x)))
468
+ (lower_cls_i128 x))
469
+
470
+ ;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
471
+ (rule (lower (has_type out_ty (uextend val @ (value_type in_ty))))
472
+ (extend val (ExtendOp.Zero) in_ty out_ty))
473
+
474
+ ;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
475
+ (rule (lower (has_type out_ty (sextend val @ (value_type in_ty))))
476
+ (extend val (ExtendOp.Signed) in_ty out_ty))
477
+
478
+ ;; The instructions below are present in RV64I and sign-extend the result to 64 bits.
479
+
480
+ (rule 1 (lower (has_type $I64 (sextend (has_type $I32 (iadd x y)))))
481
+ (rv_addw x y))
482
+
483
+ (rule 1 (lower (has_type $I64 (sextend (has_type $I32 (isub x y)))))
484
+ (rv_subw x y))
485
+
486
+ (rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ishl x y)))))
487
+ (rv_sllw x (value_regs_get y 0)))
488
+
489
+ (rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ushr x y)))))
490
+ (rv_srlw x (value_regs_get y 0)))
491
+
492
+ (rule 1 (lower (has_type $I64 (sextend (has_type $I32 (sshr x y)))))
493
+ (rv_sraw x (value_regs_get y 0)))
494
+
495
+
496
+ (rule 2 (lower (has_type $I64 (sextend (has_type $I32 (iadd x (imm12_from_value y))))))
497
+ (rv_addiw x y))
498
+
499
+ (rule 3 (lower (has_type $I64 (sextend (has_type $I32 (iadd (imm12_from_value x) y)))))
500
+ (rv_addiw y x))
501
+
502
+ (rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ishl x (imm12_from_value y))))))
503
+ (rv_slliw x y))
504
+
505
+ (rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ushr x (imm12_from_value y))))))
506
+ (rv_srliw x y))
507
+
508
+ (rule 2 (lower (has_type $I64 (sextend (has_type $I32 (sshr x (imm12_from_value y))))))
509
+ (rv_sraiw x y))
510
+
511
+ ;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
512
+ (rule (lower (has_type (fits_in_64 ty) (popcnt x)))
513
+ (lower_popcnt x ty))
514
+ (rule 1 (lower (has_type $I128 (popcnt x)))
515
+ (lower_popcnt_i128 x))
516
+
517
+ ;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
518
+
519
+ ;; 8/16 bit types need a mask on the shift amount
520
+ (rule 0 (lower (has_type (ty_int (ty_8_or_16 ty)) (ishl x y)))
521
+ (if-let mask (u64_to_imm12 (shift_mask ty)))
522
+ (rv_sllw x (rv_andi (value_regs_get y 0) mask)))
523
+
524
+ ;; Using the 32bit version of `sll` automatically masks the shift amount.
525
+ (rule 1 (lower (has_type $I32 (ishl x y)))
526
+ (rv_sllw x (value_regs_get y 0)))
527
+
528
+ ;; Similarly, the 64bit version does the right thing.
529
+ (rule 1 (lower (has_type $I64 (ishl x y)))
530
+ (rv_sll x (value_regs_get y 0)))
531
+
532
+ ;; If the shift amount is known. We can mask it and encode it in the instruction.
533
+ (rule 2 (lower (has_type (int_fits_in_32 ty) (ishl x (maybe_uextend (imm12_from_value y)))))
534
+ (rv_slliw x (imm12_and y (shift_mask ty))))
535
+
536
+ ;; We technically don't need to mask the shift amount here. The instruction
537
+ ;; does the right thing. But it's neater when pretty printing it.
538
+ (rule 3 (lower (has_type ty @ $I64 (ishl x (maybe_uextend (imm12_from_value y)))))
539
+ (rv_slli x (imm12_and y (shift_mask ty))))
540
+
541
+ ;; With `Zba` we have a shift that zero extends the LHS argument.
542
+ (rule 4 (lower (has_type $I64 (ishl (uextend x @ (value_type $I32)) (maybe_uextend (imm12_from_value y)))))
543
+ (if-let $true (has_zba))
544
+ (rv_slliuw x y))
545
+
546
+ ;; I128 cases
547
+ (rule 4 (lower (has_type $I128 (ishl x y)))
548
+ (let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
549
+ (shamt XReg (value_regs_get tmp 0))
550
+ (len_sub_shamt XReg (value_regs_get tmp 1))
551
+ ;;
552
+ (low XReg (rv_sll (value_regs_get x 0) shamt))
553
+ ;; high part.
554
+ (high_part1 XReg (rv_srl (value_regs_get x 0) len_sub_shamt))
555
+ (high_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) high_part1))
556
+ ;;
557
+ (high_part3 XReg (rv_sll (value_regs_get x 1) shamt))
558
+ (high XReg (rv_or high_part2 high_part3))
559
+ ;;
560
+ (const64 XReg (load_u64_constant 64))
561
+ (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
562
+ (value_regs
563
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 (zero_reg) low)
564
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 low high))))
565
+
566
+ ;; SIMD Cases
567
+ ;; We don't need to mask anything since it is done by the instruction according to SEW.
568
+
569
+ (rule 5 (lower (has_type (ty_vec_fits_in_register ty) (ishl x y)))
570
+ (rv_vsll_vx x (value_regs_get y 0) (unmasked) ty))
571
+
572
+ (rule 6 (lower (has_type (ty_vec_fits_in_register ty) (ishl x (maybe_uextend (uimm5_from_value y)))))
573
+ (rv_vsll_vi x y (unmasked) ty))
574
+
575
+ ;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
576
+
577
+ ;; 8/16 bit types need a mask on the shift amount, and the LHS needs to be
578
+ ;; zero extended.
579
+ (rule 0 (lower (has_type (ty_int (fits_in_16 ty)) (ushr x y)))
580
+ (if-let mask (u64_to_imm12 (shift_mask ty)))
581
+ (rv_srlw (zext x ty $I64) (rv_andi (value_regs_get y 0) mask)))
582
+
583
+ ;; Using the 32bit version of `srl` automatically masks the shift amount.
584
+ (rule 1 (lower (has_type $I32 (ushr x y)))
585
+ (rv_srlw x (value_regs_get y 0)))
586
+
587
+ ;; Similarly, the 64bit version does the right thing.
588
+ (rule 1 (lower (has_type $I64 (ushr x y)))
589
+ (rv_srl x (value_regs_get y 0)))
590
+
591
+ ;; When the RHS is known we can just encode it in the instruction.
592
+ (rule 2 (lower (has_type (ty_int (fits_in_16 ty)) (ushr x (maybe_uextend (imm12_from_value y)))))
593
+ (rv_srliw (zext x ty $I64) (imm12_and y (shift_mask ty))))
594
+
595
+ (rule 3 (lower (has_type $I32 (ushr x (maybe_uextend (imm12_from_value y)))))
596
+ (rv_srliw x y))
597
+
598
+ (rule 3 (lower (has_type $I64 (ushr x (maybe_uextend (imm12_from_value y)))))
599
+ (rv_srli x y))
600
+
601
+ (rule 3 (lower (has_type $I128 (ushr x y)))
602
+ (let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
603
+ (shamt XReg (value_regs_get tmp 0))
604
+ (len_sub_shamt XReg (value_regs_get tmp 1))
605
+ ;; low part.
606
+ (low_part1 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
607
+ (low_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part1))
608
+ ;;
609
+ (low_part3 XReg (rv_srl (value_regs_get x 0) shamt))
610
+ (low XReg (rv_or low_part2 low_part3))
611
+ ;;
612
+ (const64 XReg (load_u64_constant 64))
613
+ ;;
614
+ (high XReg (rv_srl (value_regs_get x 1) shamt))
615
+ (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
616
+ (value_regs
617
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
618
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 (zero_reg) high))))
619
+
620
+ ;; SIMD Cases
621
+ ;; We don't need to mask or extend anything since it is done by the instruction according to SEW.
622
+
623
+ (rule 4 (lower (has_type (ty_vec_fits_in_register ty) (ushr x y)))
624
+ (rv_vsrl_vx x (value_regs_get y 0) (unmasked) ty))
625
+
626
+ (rule 5 (lower (has_type (ty_vec_fits_in_register ty) (ushr x (maybe_uextend (uimm5_from_value y)))))
627
+ (rv_vsrl_vi x y (unmasked) ty))
628
+
629
+ ;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
630
+
631
+ ;; 8/16 bit types need a mask on the shift amount, and the LHS needs to be
632
+ ;; zero extended.
633
+ (rule 0 (lower (has_type (ty_int (fits_in_16 ty)) (sshr x y)))
634
+ (if-let mask (u64_to_imm12 (shift_mask ty)))
635
+ (rv_sraw (sext x ty $I64) (rv_andi (value_regs_get y 0) mask)))
636
+
637
+ ;; Using the 32bit version of `sra` automatically masks the shift amount.
638
+ (rule 1 (lower (has_type $I32 (sshr x y)))
639
+ (rv_sraw x (value_regs_get y 0)))
640
+
641
+ ;; Similarly, the 64bit version does the right thing.
642
+ (rule 1 (lower (has_type $I64 (sshr x y)))
643
+ (rv_sra x (value_regs_get y 0)))
644
+
645
+ ;; When the RHS is known we can just encode it in the instruction.
646
+ (rule 2 (lower (has_type (ty_int (fits_in_16 ty)) (sshr x (maybe_uextend (imm12_from_value y)))))
647
+ (rv_sraiw (sext x ty $I64) (imm12_and y (shift_mask ty))))
648
+
649
+ (rule 3 (lower (has_type $I32 (sshr x (maybe_uextend (imm12_from_value y)))))
650
+ (rv_sraiw x y))
651
+
652
+ (rule 3 (lower (has_type $I64 (sshr x (maybe_uextend (imm12_from_value y)))))
653
+ (rv_srai x y))
654
+
655
+ (rule 3 (lower (has_type $I128 (sshr x y)))
656
+ (let ((tmp ValueRegs (gen_shamt $I128 (value_regs_get y 0)))
657
+ (shamt XReg (value_regs_get tmp 0))
658
+ (len_sub_shamt XReg (value_regs_get tmp 1))
659
+ ;; low part.
660
+ (low_part1 XReg (rv_sll (value_regs_get x 1) len_sub_shamt))
661
+ (low_part2 XReg (gen_select_reg (IntCC.Equal) shamt (zero_reg) (zero_reg) low_part1))
662
+ ;;
663
+ (low_part3 XReg (rv_srl (value_regs_get x 0) shamt))
664
+ (low XReg (rv_or low_part2 low_part3))
665
+ ;;
666
+ (const64 XReg (load_u64_constant 64))
667
+ ;;
668
+ (high XReg (rv_sra (value_regs_get x 1) shamt))
669
+ ;;
670
+ (const_neg_1 XReg (load_imm12 -1))
671
+ ;;
672
+ (high_replacement XReg (gen_select_reg (IntCC.SignedLessThan) (value_regs_get x 1) (zero_reg) const_neg_1 (zero_reg)))
673
+ (const64 XReg (load_u64_constant 64))
674
+ (shamt_128 XReg (rv_andi (value_regs_get y 0) (imm12_const 127))))
675
+ (value_regs
676
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high low)
677
+ (gen_select_reg (IntCC.UnsignedGreaterThanOrEqual) shamt_128 const64 high_replacement high))))
678
+
679
+ ;; SIMD Cases
680
+ ;; We don't need to mask or extend anything since it is done by the instruction according to SEW.
681
+
682
+ (rule 4 (lower (has_type (ty_vec_fits_in_register ty) (sshr x y)))
683
+ (rv_vsra_vx x (value_regs_get y 0) (unmasked) ty))
684
+
685
+ (rule 5 (lower (has_type (ty_vec_fits_in_register ty) (sshr x (maybe_uextend (uimm5_from_value y)))))
686
+ (rv_vsra_vi x y (unmasked) ty))
687
+
688
+
689
+ ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
690
+ (rule (lower (has_type (fits_in_64 ty) (rotl x y)))
691
+ (lower_rotl ty (zext x ty $I64) (value_regs_get y 0)))
692
+
693
+ (rule 1 (lower (has_type $I128 (rotl x y)))
694
+ (lower_i128_rotl x y))
695
+
696
+ ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
697
+ (rule (lower (has_type (fits_in_64 ty) (rotr x y)))
698
+ (lower_rotr ty (zext x ty $I64) (value_regs_get y 0)))
699
+
700
+ (rule 1 (lower (has_type $I128 (rotr x y)))
701
+ (lower_i128_rotr x y))
702
+
703
+
704
+ ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
705
+ (rule (lower (has_type ty (fabs x)))
706
+ (rv_fabs ty x))
707
+
708
+ ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
709
+ (rule 0 (lower (has_type (ty_scalar_float ty) (fneg x)))
710
+ (rv_fneg ty x))
711
+
712
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fneg x)))
713
+ (rv_vfneg_v x (unmasked) ty))
714
+
715
+ ;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
716
+ (rule (lower (has_type ty (fcopysign x y)))
717
+ (rv_fsgnj ty x y))
718
+
719
+ ;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
720
+ (rule (lower (has_type ty (fma x y z)))
721
+ (rv_fmadd ty x y z))
722
+
723
+
724
+ ;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
725
+ (rule 0 (lower (has_type (ty_scalar_float ty) (sqrt x)))
726
+ (rv_fsqrt ty x))
727
+
728
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (sqrt x)))
729
+ (rv_vfsqrt_v x (unmasked) ty))
730
+
731
+ ;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
732
+ (rule -1
733
+ ;;
734
+ (lower
735
+ (has_type (valid_atomic_transaction ty) (atomic_rmw flags op addr x)))
736
+ (gen_atomic (get_atomic_rmw_op ty op) addr x (atomic_amo)))
737
+
738
+ ;;; for I8 and I16
739
+ (rule 1
740
+ (lower
741
+ (has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags op addr x)))
742
+ (gen_atomic_rmw_loop op ty addr x))
743
+
744
+ ;;;special for I8 and I16 max min etc.
745
+ ;;;because I need uextend or sextend the value.
746
+ (rule 2
747
+ (lower
748
+ (has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $true) addr x)))
749
+ (gen_atomic_rmw_loop op ty addr (sext x ty $I64)))
750
+
751
+
752
+ (rule 2
753
+ ;;
754
+ (lower
755
+ (has_type (valid_atomic_transaction (fits_in_16 ty)) (atomic_rmw flags (is_atomic_rmw_max_etc op $false) addr x)))
756
+ ;;
757
+ (gen_atomic_rmw_loop op ty addr (zext x ty $I64)))
758
+
759
+ ;;;;; Rules for `AtomicRmwOp.Sub`
760
+ (rule
761
+ (lower
762
+ (has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Sub) addr x)))
763
+ (let
764
+ ((tmp WritableReg (temp_writable_reg ty))
765
+ (x2 Reg (rv_neg x)))
766
+ (gen_atomic (get_atomic_rmw_op ty (AtomicRmwOp.Add)) addr x2 (atomic_amo))))
767
+
768
+ (decl gen_atomic_rmw_loop (AtomicRmwOp Type XReg XReg) XReg)
769
+ (rule
770
+ (gen_atomic_rmw_loop op ty addr x)
771
+ (let
772
+ ((dst WritableXReg (temp_writable_xreg))
773
+ (t0 WritableXReg (temp_writable_xreg))
774
+ (_ Unit (emit (MInst.AtomicRmwLoop (gen_atomic_offset addr ty) op dst ty (gen_atomic_p addr ty) x t0))))
775
+ (writable_reg_to_reg dst)))
776
+
777
+ ;;;;; Rules for `AtomicRmwOp.Nand`
778
+ (rule
779
+ (lower
780
+ (has_type (valid_atomic_transaction ty) (atomic_rmw flags (AtomicRmwOp.Nand) addr x)))
781
+ (gen_atomic_rmw_loop (AtomicRmwOp.Nand) ty addr x))
782
+
783
+ (decl is_atomic_rmw_max_etc (AtomicRmwOp bool) AtomicRmwOp)
784
+ (extern extractor is_atomic_rmw_max_etc is_atomic_rmw_max_etc)
785
+
786
+ ;;;;; Rules for `atomic load`;;;;;;;;;;;;;;;;;
787
+ (rule
788
+ (lower (has_type (valid_atomic_transaction ty) (atomic_load flags p)))
789
+ (gen_atomic_load p ty))
790
+
791
+
792
+ ;;;;; Rules for `atomic store`;;;;;;;;;;;;;;;;;
793
+ (rule
794
+ (lower (atomic_store flags src @ (value_type (valid_atomic_transaction ty)) p))
795
+ (gen_atomic_store p ty src))
796
+
797
+ (decl gen_atomic_offset (XReg Type) XReg)
798
+ (rule 1 (gen_atomic_offset p (fits_in_16 ty))
799
+ (rv_slli (rv_andi p (imm12_const 3)) (imm12_const 3)))
800
+
801
+ (rule (gen_atomic_offset p _)
802
+ (zero_reg))
803
+
804
+ (decl gen_atomic_p (XReg Type) XReg)
805
+ (rule 1 (gen_atomic_p p (fits_in_16 ty))
806
+ (rv_andi p (imm12_const -4)))
807
+
808
+ (rule (gen_atomic_p p _)
809
+ p)
810
+
811
+
812
+ ;;;;; Rules for `atomic cas`;;;;;;;;;;;;;;;;;
813
+ (rule
814
+ (lower (has_type (valid_atomic_transaction ty) (atomic_cas flags p e x)))
815
+ (let
816
+ ((t0 WritableReg (temp_writable_reg ty))
817
+ (dst WritableReg (temp_writable_reg ty))
818
+ (_ Unit (emit (MInst.AtomicCas (gen_atomic_offset p ty) t0 dst (zext e ty $I64) (gen_atomic_p p ty) x ty))))
819
+ (writable_reg_to_reg dst)))
820
+
821
+ ;;;;; Rules for `ireduce`;;;;;;;;;;;;;;;;;
822
+ (rule
823
+ (lower (has_type ty (ireduce x)))
824
+ (value_regs_get x 0))
825
+
826
+ ;;;;; Rules for `fpromote`;;;;;;;;;;;;;;;;;
827
+ (rule (lower (fpromote x))
828
+ (rv_fcvtds x))
829
+
830
+ ;;;;; Rules for `fdemote`;;;;;;;;;;;;;;;;;;
831
+ (rule (lower (fdemote x))
832
+ (rv_fcvtsd x))
833
+
834
+
835
+ ;;;;; Rules for for float arithmetic
836
+
837
+
838
+ ;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
839
+
840
+ (rule 0 (lower (has_type (ty_scalar_float ty) (fadd x y)))
841
+ (rv_fadd ty x y))
842
+
843
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fadd x y)))
844
+ (rv_vfadd_vv x y (unmasked) ty))
845
+
846
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fadd x (splat y))))
847
+ (rv_vfadd_vf x y (unmasked) ty))
848
+
849
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fadd (splat x) y)))
850
+ (rv_vfadd_vf y x (unmasked) ty))
851
+
852
+
853
+ ;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
854
+ (rule 0 (lower (has_type (ty_scalar_float ty) (fsub x y)))
855
+ (rv_fsub ty x y))
856
+
857
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fsub x y)))
858
+ (rv_vfsub_vv x y (unmasked) ty))
859
+
860
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fsub x (splat y))))
861
+ (rv_vfsub_vf x y (unmasked) ty))
862
+
863
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fsub (splat x) y)))
864
+ (rv_vfrsub_vf y x (unmasked) ty))
865
+
866
+ ;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
867
+ (rule 0 (lower (has_type (ty_scalar_float ty) (fmul x y)))
868
+ (rv_fmul ty x y))
869
+
870
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fmul x y)))
871
+ (rv_vfmul_vv x y (unmasked) ty))
872
+
873
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fmul x (splat y))))
874
+ (rv_vfmul_vf x y (unmasked) ty))
875
+
876
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fmul (splat x) y)))
877
+ (rv_vfmul_vf y x (unmasked) ty))
878
+
879
+
880
+ ;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
881
+ (rule 0 (lower (has_type (ty_scalar_float ty) (fdiv x y)))
882
+ (rv_fdiv ty x y))
883
+
884
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (fdiv x y)))
885
+ (rv_vfdiv_vv x y (unmasked) ty))
886
+
887
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (fdiv x (splat y))))
888
+ (rv_vfdiv_vf x y (unmasked) ty))
889
+
890
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (fdiv (splat x) y)))
891
+ (rv_vfrdiv_vf y x (unmasked) ty))
892
+
893
+ ;;;; Rules for `fmin/fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
894
+
895
+ (rule
896
+ (lower (has_type ty (fmin x y)))
897
+ (gen_float_select (FloatSelectOP.Min) x y ty))
898
+
899
+ (rule
900
+ (lower (has_type ty (fmin_pseudo x y)))
901
+ (gen_float_select_pseudo (FloatSelectOP.Min) x y ty))
902
+
903
+ (rule
904
+ (lower (has_type ty (fmax x y)))
905
+ (gen_float_select (FloatSelectOP.Max) x y ty))
906
+
907
+ (rule
908
+ (lower (has_type ty (fmax_pseudo x y)))
909
+ (gen_float_select_pseudo (FloatSelectOP.Max) x y ty))
910
+
911
+ ;;;;; Rules for `stack_addr`;;;;;;;;;
912
+ (rule
913
+ (lower (stack_addr ss offset))
914
+ (gen_stack_addr ss offset))
915
+
916
+ ;;;;; Rules for `is_null`;;;;;;;;;
917
+
918
+ ;; Null references are represented by the constant value `0`.
919
+ (rule (lower (is_null v))
920
+ (rv_seqz v))
921
+
922
+ ;;;;; Rules for `is_invalid`;;;;;;;;;
923
+
924
+ ;; Invalid references are represented by the constant value `-1`.
925
+ (rule (lower (is_invalid v))
926
+ (rv_seqz (rv_addi v (imm12_const 1))))
927
+
928
+ ;;;;; Rules for `select`;;;;;;;;;
929
+ (rule
930
+ (lower (has_type ty (select c @ (value_type cty) x y)))
931
+ (gen_select ty (truthy_to_reg cty (normalize_cmp_value cty c (ExtendOp.Zero))) x y))
932
+
933
+ (rule 1
934
+ (lower (has_type (fits_in_64 ty) (select (icmp cc a b @ (value_type (fits_in_64 in_ty))) x y)))
935
+ (let ((a XReg (truthy_to_reg in_ty (normalize_cmp_value in_ty a (intcc_to_extend_op cc))))
936
+ (b XReg (truthy_to_reg in_ty (normalize_cmp_value in_ty b (intcc_to_extend_op cc)))))
937
+ (gen_select_reg cc a b x y)))
938
+
939
+ ;;;;; Rules for `bitselect`;;;;;;;;;
940
+
941
+ ;; Do a (c & x) | (~c & y) operation.
942
+ (rule 0 (lower (has_type (ty_int_ref_scalar_64 ty) (bitselect c x y)))
943
+ (let ((tmp_x XReg (rv_and c x))
944
+ (c_inverse XReg (rv_not c))
945
+ (tmp_y XReg (rv_and c_inverse y)))
946
+ (rv_or tmp_x tmp_y)))
947
+
948
+ ;; For vectors, we also do the same operation.
949
+ ;; We can technically use any type in the bitwise operations, but prefer
950
+ ;; using the type of the inputs so that we avoid emitting unnecessary
951
+ ;; `vsetvl` instructions. It's likeley that the vector unit is already
952
+ ;; configured for that type.
953
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (bitselect c x y)))
954
+ (let ((tmp_x VReg (rv_vand_vv c x (unmasked) ty))
955
+ (c_inverse VReg (rv_vnot_v c (unmasked) ty))
956
+ (tmp_y VReg (rv_vand_vv c_inverse y (unmasked) ty)))
957
+ (rv_vor_vv tmp_x tmp_y (unmasked) ty)))
958
+
959
+ ;;;;; Rules for `isplit`;;;;;;;;;
960
+ (rule
961
+ (lower (isplit x))
962
+ (let
963
+ ((t1 XReg (value_regs_get x 0))
964
+ (t2 XReg (value_regs_get x 1)))
965
+ (output_pair t1 t2)))
966
+
967
+ ;;;;; Rules for `iconcat`;;;;;;;;;
968
+ (rule
969
+ (lower (has_type $I128 (iconcat x y)))
970
+ (let
971
+ ((t1 XReg x)
972
+ (t2 XReg y))
973
+ (value_regs t1 t2)))
974
+
975
+
976
+ ;;;;; Rules for `smax`;;;;;;;;;
977
+
978
+ (rule 0 (lower (has_type (ty_int ty) (smax x y)))
979
+ (gen_int_select ty (IntSelectOP.Smax) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
980
+
981
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smax x y)))
982
+ (rv_vmax_vv x y (unmasked) ty))
983
+
984
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smax x (splat y))))
985
+ (rv_vmax_vx x y (unmasked) ty))
986
+
987
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (smax (splat x) y)))
988
+ (rv_vmax_vx y x (unmasked) ty))
989
+
990
+ ;;;;; Rules for `smin`;;;;;;;;;
991
+
992
+ (rule 0 (lower (has_type (ty_int ty) (smin x y)))
993
+ (gen_int_select ty (IntSelectOP.Smin) (ext_int_if_need $true x ty) (ext_int_if_need $true y ty)))
994
+
995
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (smin x y)))
996
+ (rv_vmin_vv x y (unmasked) ty))
997
+
998
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (smin x (splat y))))
999
+ (rv_vmin_vx x y (unmasked) ty))
1000
+
1001
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (smin (splat x) y)))
1002
+ (rv_vmin_vx y x (unmasked) ty))
1003
+
1004
+ ;;;;; Rules for `umax`;;;;;;;;;
1005
+
1006
+ (rule 0 (lower (has_type (ty_int ty) (umax x y)))
1007
+ (gen_int_select ty (IntSelectOP.Umax) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
1008
+
1009
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umax x y)))
1010
+ (rv_vmaxu_vv x y (unmasked) ty))
1011
+
1012
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umax x (splat y))))
1013
+ (rv_vmaxu_vx x y (unmasked) ty))
1014
+
1015
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (umax (splat x) y)))
1016
+ (rv_vmaxu_vx y x (unmasked) ty))
1017
+
1018
+ ;;;;; Rules for `umin`;;;;;;;;;
1019
+
1020
+ (rule 0 (lower (has_type (ty_int ty) (umin x y)))
1021
+ (gen_int_select ty (IntSelectOP.Umin) (ext_int_if_need $false x ty) (ext_int_if_need $false y ty)))
1022
+
1023
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (umin x y)))
1024
+ (rv_vminu_vv x y (unmasked) ty))
1025
+
1026
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (umin x (splat y))))
1027
+ (rv_vminu_vx x y (unmasked) ty))
1028
+
1029
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (umin (splat x) y)))
1030
+ (rv_vminu_vx y x (unmasked) ty))
1031
+
1032
+
1033
+ ;;;;; Rules for `debugtrap`;;;;;;;;;
1034
+ (rule
1035
+ (lower (debugtrap))
1036
+ (side_effect (SideEffectNoResult.Inst (MInst.EBreak))))
1037
+
1038
+ ;;;;; Rules for `fence`;;;;;;;;;
1039
+ (rule
1040
+ (lower (fence))
1041
+ (side_effect (SideEffectNoResult.Inst (MInst.Fence 15 15))))
1042
+
1043
+ ;;;;; Rules for `trap`;;;;;;;;;
1044
+ (rule
1045
+ (lower (trap code))
1046
+ (udf code))
1047
+
1048
+ ;;;;; Rules for `resumable_trap`;;;;;;;;;
1049
+ (rule
1050
+ (lower (resumable_trap code))
1051
+ (udf code))
1052
+
1053
+ ;;;;; Rules for `uload8`;;;;;;;;;
1054
+ (rule
1055
+ (lower (uload8 flags p @ (value_type (ty_addr64 _)) offset))
1056
+ (gen_load p offset (int_load_op $false 8) flags $I64))
1057
+ ;;;;; Rules for `sload8`;;;;;;;;;
1058
+ (rule
1059
+ (lower (sload8 flags p @ (value_type (ty_addr64 _)) offset))
1060
+ (gen_load p offset (int_load_op $true 8) flags $I64))
1061
+ ;;;;; Rules for `uload16`;;;;;;;;;
1062
+ (rule
1063
+ (lower (uload16 flags p @ (value_type (ty_addr64 _)) offset))
1064
+ (gen_load p offset (int_load_op $false 16) flags $I64))
1065
+
1066
+ ;;;;; Rules for `iload16`;;;;;;;;;
1067
+ (rule
1068
+ (lower (sload16 flags p @ (value_type (ty_addr64 _)) offset))
1069
+ (gen_load p offset (int_load_op $true 16) flags $I64))
1070
+
1071
+ ;;;;; Rules for `uload32`;;;;;;;;;
1072
+ (rule
1073
+ (lower (uload32 flags p @ (value_type (ty_addr64 _)) offset))
1074
+ (gen_load p offset (int_load_op $false 32) flags $I64))
1075
+
1076
+ ;;;;; Rules for `iload16`;;;;;;;;;
1077
+ (rule
1078
+ (lower (sload32 flags p @ (value_type (ty_addr64 _)) offset))
1079
+ (gen_load p offset (int_load_op $true 32) flags $I64))
1080
+
1081
+ (rule
1082
+ (lower (has_type ty (load flags p @ (value_type (ty_addr64 _)) offset)))
1083
+ (gen_load p offset (load_op ty) flags ty)
1084
+ )
1085
+ ;;;; for I128
1086
+ (rule 1
1087
+ (lower (has_type $I128 (load flags p @ (value_type (ty_addr64 _)) offset)))
1088
+ (gen_load_128 p offset flags))
1089
+
1090
+ (rule 2
1091
+ (lower (has_type (ty_vec_fits_in_register ty) (load flags p @ (value_type (ty_addr64 _)) offset)))
1092
+ (let ((eew VecElementWidth (element_width_from_type ty)))
1093
+ (vec_load eew (VecAMode.UnitStride (gen_amode p offset $I64)) flags (unmasked) ty)))
1094
+
1095
+ ;;;;; Rules for `istore8`;;;;;;;;;
1096
+ (rule
1097
+ (lower (istore8 flags x p @ (value_type (ty_addr64 _)) offset))
1098
+ (gen_store p offset (StoreOP.Sb) flags x))
1099
+ ;;;;; Rules for `istore16`;;;;;;;;;
1100
+ (rule
1101
+ (lower (istore16 flags x p @ (value_type (ty_addr64 _)) offset))
1102
+ (gen_store p offset (StoreOP.Sh) flags x))
1103
+
1104
+ ;;;;; Rules for `istore32`;;;;;;;;;
1105
+ (rule
1106
+ (lower (istore32 flags x p @ (value_type (ty_addr64 _)) offset))
1107
+ (gen_store p offset (StoreOP.Sw) flags x))
1108
+
1109
+ ;;;;; Rules for `store`;;;;;;;;;
1110
+ (rule
1111
+ (lower (store flags x @ (value_type ty) p @ (value_type (ty_addr64 _)) offset))
1112
+ (gen_store p offset (store_op ty) flags x))
1113
+
1114
+ ;;; special for I128
1115
+ (rule 1
1116
+ (lower (store flags x @ (value_type $I128 ) p @ (value_type (ty_addr64 _)) offset))
1117
+ (gen_store_128 p offset flags x))
1118
+
1119
+ (rule 2
1120
+ (lower (store flags x @ (value_type (ty_vec_fits_in_register ty)) p @ (value_type (ty_addr64 _)) offset))
1121
+ (let ((eew VecElementWidth (element_width_from_type ty)))
1122
+ (vec_store eew (VecAMode.UnitStride (gen_amode p offset $I64)) x flags (unmasked) ty)))
1123
+
1124
+ (decl gen_icmp (IntCC ValueRegs ValueRegs Type) XReg)
1125
+ (rule
1126
+ (gen_icmp cc x y ty)
1127
+ (let
1128
+ ((result WritableXReg (temp_writable_xreg))
1129
+ (_ Unit (emit (MInst.Icmp cc result x y ty))))
1130
+ result))
1131
+
1132
+ ;;;;; Rules for `icmp`;;;;;;;;;
1133
+ (rule
1134
+ (lower (icmp cc x @ (value_type ty) y))
1135
+ (lower_icmp cc x y ty))
1136
+
1137
+ ;;;;; Rules for `fcmp`;;;;;;;;;
1138
+ (rule
1139
+ (lower (fcmp cc x @ (value_type ty) y))
1140
+ (cmp_value (emit_fcmp cc ty x y)))
1141
+
1142
+ ;;;;; Rules for `func_addr`;;;;;;;;;
1143
+ (rule
1144
+ (lower (func_addr (func_ref_data _ name _)))
1145
+ (load_ext_name name 0))
1146
+
1147
+ ;;;;; Rules for `fcvt_to_uint`;;;;;;;;;
1148
+ (rule
1149
+ (lower (has_type to (fcvt_to_uint v @ (value_type from))))
1150
+ (gen_fcvt_int $false v $false from to))
1151
+
1152
+ ;;;;; Rules for `fcvt_to_sint`;;;;;;;;;
1153
+ (rule
1154
+ (lower (has_type to (fcvt_to_sint v @ (value_type from))))
1155
+ (gen_fcvt_int $false v $true from to))
1156
+
1157
+ ;;;;; Rules for `fcvt_to_sint_sat`;;;;;;;;;
1158
+ (rule
1159
+ (lower (has_type to (fcvt_to_sint_sat v @ (value_type from))))
1160
+ (gen_fcvt_int $true v $true from to))
1161
+
1162
+ ;;;;; Rules for `fcvt_to_uint_sat`;;;;;;;;;
1163
+ (rule
1164
+ (lower (has_type to (fcvt_to_uint_sat v @ (value_type from))))
1165
+ (gen_fcvt_int $true v $false from to))
1166
+
1167
+ ;;;;; Rules for `fcvt_from_sint`;;;;;;;;;
1168
+ (rule
1169
+ (lower (has_type to (fcvt_from_sint v @ (value_type from_ty))))
1170
+ (let ((float_op FpuOPRR (int_convert_2_float_op from_ty $true to))
1171
+ (value XReg (normalize_fcvt_from_int v from_ty (ExtendOp.Signed))))
1172
+ (fpu_rr float_op to value)))
1173
+
1174
+ ;;;;; Rules for `fcvt_from_uint`;;;;;;;;;
1175
+ (rule
1176
+ (lower (has_type to (fcvt_from_uint v @ (value_type from_ty))))
1177
+ (let ((float_op FpuOPRR (int_convert_2_float_op from_ty $false to))
1178
+ (value XReg (normalize_fcvt_from_int v from_ty (ExtendOp.Zero))))
1179
+ (fpu_rr float_op to value)))
1180
+
1181
+ ;;;;; Rules for `symbol_value`;;;;;;;;;
1182
+ (rule
1183
+ (lower (symbol_value (symbol_value_data name _ offset)))
1184
+ (load_ext_name name offset)
1185
+ )
1186
+ ;;;;; Rules for `bitcast`;;;;;;;;;
1187
+ (rule
1188
+ (lower (has_type out_ty (bitcast _ v @ (value_type in_ty))))
1189
+ (gen_bitcast v in_ty out_ty))
1190
+
1191
+ ;;;;; Rules for `ceil`;;;;;;;;;
1192
+ (rule
1193
+ (lower (has_type ty (ceil x)))
1194
+ (gen_float_round (FloatRoundOP.Ceil) x ty)
1195
+ )
1196
+
1197
+ ;;;;; Rules for `floor`;;;;;;;;;
1198
+ (rule
1199
+ (lower (has_type ty (floor x)))
1200
+ (gen_float_round (FloatRoundOP.Floor) x ty))
1201
+ ;;;;; Rules for `trunc`;;;;;;;;;
1202
+ (rule
1203
+ (lower (has_type ty (trunc x)))
1204
+ (gen_float_round (FloatRoundOP.Trunc) x ty))
1205
+
1206
+ ;;;;; Rules for `nearest`;;;;;;;;;
1207
+ (rule
1208
+ (lower (has_type ty (nearest x)))
1209
+ (gen_float_round (FloatRoundOP.Nearest) x ty))
1210
+
1211
+
1212
+ ;;;;; Rules for `select_spectre_guard`;;;;;;;;;
1213
+
1214
+ ;; SelectSpectreGuard is equivalent to Select, but we should not use a branch based
1215
+ ;; lowering for it. Instead we use a conditional move based lowering.
1216
+ ;;
1217
+ ;; We don't have cmov's in RISC-V either, but we can emulate those using bitwise
1218
+ ;; operations, which is what we do below.
1219
+ (rule (lower (has_type ty (select_spectre_guard cmp @ (value_type cmp_ty) x @ (value_type arg_ty) y)))
1220
+ (let (;; Build a mask that is 0 or -1 depending on the input comparision value.
1221
+ ;; `lower_bmask` handles normalizing the input.
1222
+ (mask ValueRegs (lower_bmask arg_ty cmp_ty cmp))
1223
+ ;; Using the mask above we can select either `x` or `y` by
1224
+ ;; performing a bitwise `and` on both sides and then merging them
1225
+ ;; together. We know that only the bits of one of the sides will be selected.
1226
+ ;; TODO: We can use `andn` here if we have `Zbb`
1227
+ (lhs ValueRegs (gen_and arg_ty x mask))
1228
+ (rhs ValueRegs (gen_and arg_ty y (gen_bnot arg_ty mask))))
1229
+ (gen_or arg_ty lhs rhs)))
1230
+
1231
+ ;;;;; Rules for `bmask`;;;;;;;;;
1232
+ (rule
1233
+ (lower (has_type oty (bmask x @ (value_type ity))))
1234
+ (lower_bmask oty ity x))
1235
+
1236
+ ;; N.B.: the Ret itself is generated by the ABI.
1237
+ (rule (lower (return args))
1238
+ (lower_return args))
1239
+
1240
+
1241
+ ;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;;
1242
+
1243
+ (rule (lower (get_frame_pointer))
1244
+ (gen_mov_from_preg (fp_reg)))
1245
+
1246
+ (rule (lower (get_stack_pointer))
1247
+ (gen_mov_from_preg (sp_reg)))
1248
+
1249
+ (rule (lower (get_return_address))
1250
+ (load_ra))
1251
+
1252
+ ;;; Rules for `iabs` ;;;;;;;;;;;;;
1253
+ (rule
1254
+ (lower (has_type (fits_in_64 ty) (iabs x)))
1255
+ (lower_iabs ty x))
1256
+
1257
+ ;;;; Rules for calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1258
+
1259
+ (rule (lower (call (func_ref_data sig_ref extname dist) inputs))
1260
+ (gen_call sig_ref extname dist inputs))
1261
+
1262
+ (rule (lower (call_indirect sig_ref val inputs))
1263
+ (gen_call_indirect sig_ref val inputs))
1264
+
1265
+ ;;;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1266
+
1267
+ (rule (lower (extractlane x @ (value_type ty) (u8_from_uimm8 idx)))
1268
+ (gen_extractlane ty x idx))
1269
+
1270
+ ;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1271
+
1272
+ ;; We can insert a lane by using a masked splat from an X register.
1273
+ ;; Build a mask that is only enabled in the lane we want to insert.
1274
+ ;; Then use a masked splat (vmerge) to insert the value.
1275
+ (rule 0 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
1276
+ val @ (value_type (ty_int _))
1277
+ (u8_from_uimm8 lane)))
1278
+ (let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
1279
+ (rv_vmerge_vxm vec val mask ty)))
1280
+
1281
+ ;; Similar to above, but using the float variants of the instructions.
1282
+ (rule 1 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
1283
+ val @ (value_type (ty_scalar_float _))
1284
+ (u8_from_uimm8 lane)))
1285
+ (let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
1286
+ (rv_vfmerge_vfm vec val mask ty)))
1287
+
1288
+ ;; If we are inserting from an Imm5 const we can use the immediate
1289
+ ;; variant of vmerge.
1290
+ (rule 2 (lower (insertlane vec @ (value_type (ty_vec_fits_in_register ty))
1291
+ (iconst (u64_from_imm64 (imm5_from_u64 imm)))
1292
+ (u8_from_uimm8 lane)))
1293
+ (let ((mask VReg (gen_vec_mask (u64_shl 1 lane))))
1294
+ (rv_vmerge_vim vec imm mask ty)))
1295
+
1296
+ ;;;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1297
+
1298
+ (rule 0 (lower (has_type ty (splat n @ (value_type (ty_scalar_float _)))))
1299
+ (rv_vfmv_vf n ty))
1300
+
1301
+ (rule 1 (lower (has_type ty (splat n @ (value_type (ty_int_ref_scalar_64 _)))))
1302
+ (rv_vmv_vx n ty))
1303
+
1304
+ (rule 2 (lower (has_type ty (splat (iconst (u64_from_imm64 (imm5_from_u64 imm))))))
1305
+ (rv_vmv_vi imm ty))
1306
+
1307
+ ;; TODO: We can splat out more patterns by using for example a vmv.v.i i8x16 for
1308
+ ;; a i64x2 const with a compatible bit pattern. The AArch64 Backend does something
1309
+ ;; similar in its splat rules.
1310
+ ;; TODO: Look through bitcasts when splatting out registers. We can use
1311
+ ;; `vmv.v.x` in a `(splat.f32x4 (bitcast.f32 val))`. And vice versa for integers.
1312
+
1313
+ ;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1314
+
1315
+ (rule 0 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x y)))
1316
+ (rv_vsaddu_vv x y (unmasked) ty))
1317
+
1318
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x (splat y))))
1319
+ (rv_vsaddu_vx x y (unmasked) ty))
1320
+
1321
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat (splat x) y)))
1322
+ (rv_vsaddu_vx y x (unmasked) ty))
1323
+
1324
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat x (replicated_imm5 y))))
1325
+ (rv_vsaddu_vi x y (unmasked) ty))
1326
+
1327
+ (rule 4 (lower (has_type (ty_vec_fits_in_register ty) (uadd_sat (replicated_imm5 x) y)))
1328
+ (rv_vsaddu_vi y x (unmasked) ty))
1329
+
1330
+ ;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1331
+
1332
+ (rule 0 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x y)))
1333
+ (rv_vsadd_vv x y (unmasked) ty))
1334
+
1335
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x (splat y))))
1336
+ (rv_vsadd_vx x y (unmasked) ty))
1337
+
1338
+ (rule 2 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat (splat x) y)))
1339
+ (rv_vsadd_vx y x (unmasked) ty))
1340
+
1341
+ (rule 3 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat x (replicated_imm5 y))))
1342
+ (rv_vsadd_vi x y (unmasked) ty))
1343
+
1344
+ (rule 4 (lower (has_type (ty_vec_fits_in_register ty) (sadd_sat (replicated_imm5 x) y)))
1345
+ (rv_vsadd_vi y x (unmasked) ty))
1346
+
1347
+ ;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1348
+
1349
+ (rule 0 (lower (has_type (ty_vec_fits_in_register ty) (usub_sat x y)))
1350
+ (rv_vssubu_vv x y (unmasked) ty))
1351
+
1352
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (usub_sat x (splat y))))
1353
+ (rv_vssubu_vx x y (unmasked) ty))
1354
+
1355
+ ;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1356
+
1357
+ (rule 0 (lower (has_type (ty_vec_fits_in_register ty) (ssub_sat x y)))
1358
+ (rv_vssub_vv x y (unmasked) ty))
1359
+
1360
+ (rule 1 (lower (has_type (ty_vec_fits_in_register ty) (ssub_sat x (splat y))))
1361
+ (rv_vssub_vx x y (unmasked) ty))
1362
+
1363
+ ;;;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1364
+
1365
+ ;; Here we do a Vector Reduce operation. Get the unsigned minimum value of any
1366
+ ;; lane in the vector. The fixed input to the reduce operation is a 1.
1367
+ ;; This way, if any lane is 0, the result will be 0. Otherwise, the result will
1368
+ ;; be a 1.
1369
+ ;; The reduce operation leaves the result in the lowest lane, we then move it
1370
+ ;; into the destination X register.
1371
+ (rule (lower (vall_true x @ (value_type (ty_vec_fits_in_register ty))))
1372
+ (if-let one (imm5_from_i8 1))
1373
+ ;; We don't need to broadcast the immediate into all lanes, only into lane 0.
1374
+ ;; I did it this way since it uses one less instruction than with a vmv.s.x.
1375
+ (let ((fixed VReg (rv_vmv_vi one ty))
1376
+ (min VReg (rv_vredminu_vs x fixed (unmasked) ty)))
1377
+ (rv_vmv_xs min ty)))
1378
+
1379
+
1380
+ ;;;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1381
+
1382
+ ;; Here we do a Vector Reduce operation. Get the unsigned maximum value of the
1383
+ ;; input vector register. Move the max to an X register, and do a `snez` on it
1384
+ ;; to ensure its either 1 or 0.
1385
+ (rule (lower (vany_true x @ (value_type (ty_vec_fits_in_register ty))))
1386
+ (let ((max VReg (rv_vredmaxu_vs x x (unmasked) ty))
1387
+ (x_max XReg (rv_vmv_xs max ty)))
1388
+ (rv_snez x_max)))
1389
+
1390
+
1391
+ ;;;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1392
+
1393
+ ;; To check if the MSB of a lane is set, we do a `vmslt` with zero, this sets
1394
+ ;; the mask bit to 1 if the value is negative (MSB 1) and 0 if not. We can then
1395
+ ;; just move that mask to an X Register.
1396
+ ;;
1397
+ ;; We must ensure that the move to the X register has a SEW with enough bits
1398
+ ;; to hold the full mask. Additionally, in some cases (e.g. i64x2) we are going
1399
+ ;; to read some tail bits. These are undefined, so we need to further mask them
1400
+ ;; off.
1401
+ (rule (lower (vhigh_bits x @ (value_type (ty_vec_fits_in_register ty))))
1402
+ (let ((mask VReg (rv_vmslt_vx x (zero_reg) (unmasked) ty))
1403
+ ;; Here we only need I64X1, but emit an AVL of 2 since it
1404
+ ;; saves one vector state change in the case of I64X2.
1405
+ ;;
1406
+ ;; TODO: For types that have more lanes than element bits, we can
1407
+ ;; use the original type as a VState and avoid a state change.
1408
+ (x_mask XReg (rv_vmv_xs mask (vstate_from_type $I64X2))))
1409
+ (gen_andi x_mask (ty_lane_mask ty))))