wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,2763 +0,0 @@
1
- //! This module defines x86_64-specific machine instruction types.
2
-
3
- use crate::binemit::{Addend, CodeOffset, Reloc, StackMap};
4
- use crate::ir::{types, ExternalName, LibCall, Opcode, RelSourceLoc, TrapCode, Type};
5
- use crate::isa::x64::abi::X64ABIMachineSpec;
6
- use crate::isa::x64::inst::regs::{pretty_print_reg, show_ireg_sized};
7
- use crate::isa::x64::settings as x64_settings;
8
- use crate::isa::{CallConv, FunctionAlignment};
9
- use crate::{machinst::*, trace};
10
- use crate::{settings, CodegenError, CodegenResult};
11
- use alloc::boxed::Box;
12
- use alloc::vec::Vec;
13
- use cranelift_control::ControlPlane;
14
- use regalloc2::{Allocation, PRegSet, VReg};
15
- use smallvec::{smallvec, SmallVec};
16
- use std::fmt;
17
- use std::string::{String, ToString};
18
-
19
- pub mod args;
20
- mod emit;
21
- #[cfg(test)]
22
- mod emit_tests;
23
- pub mod regs;
24
- pub mod unwind;
25
-
26
- use args::*;
27
-
28
- //=============================================================================
29
- // Instructions (top level): definition
30
-
31
- // `Inst` is defined inside ISLE as `MInst`. We publicly re-export it here.
32
- pub use super::lower::isle::generated_code::MInst as Inst;
33
-
34
- /// Out-of-line data for calls, to keep the size of `Inst` down.
35
- #[derive(Clone, Debug)]
36
- pub struct CallInfo {
37
- /// Register uses of this call.
38
- pub uses: CallArgList,
39
- /// Register defs of this call.
40
- pub defs: CallRetList,
41
- /// Registers clobbered by this call, as per its calling convention.
42
- pub clobbers: PRegSet,
43
- /// The opcode of this call.
44
- pub opcode: Opcode,
45
- }
46
-
47
- #[test]
48
- #[cfg(target_pointer_width = "64")]
49
- fn inst_size_test() {
50
- // This test will help with unintentionally growing the size
51
- // of the Inst enum.
52
- assert_eq!(40, std::mem::size_of::<Inst>());
53
- }
54
-
55
- pub(crate) fn low32_will_sign_extend_to_64(x: u64) -> bool {
56
- let xs = x as i64;
57
- xs == ((xs << 32) >> 32)
58
- }
59
-
60
- impl Inst {
61
- /// Retrieve a list of ISA feature sets in which the instruction is available. An empty list
62
- /// indicates that the instruction is available in the baseline feature set (i.e. SSE2 and
63
- /// below); more than one `InstructionSet` in the list indicates that the instruction is present
64
- /// *any* of the included ISA feature sets.
65
- fn available_in_any_isa(&self) -> SmallVec<[InstructionSet; 2]> {
66
- match self {
67
- // These instructions are part of SSE2, which is a basic requirement in Cranelift, and
68
- // don't have to be checked.
69
- Inst::AluRmiR { .. }
70
- | Inst::AluRM { .. }
71
- | Inst::AtomicRmwSeq { .. }
72
- | Inst::Bswap { .. }
73
- | Inst::CallKnown { .. }
74
- | Inst::CallUnknown { .. }
75
- | Inst::CheckedSRemSeq { .. }
76
- | Inst::CheckedSRemSeq8 { .. }
77
- | Inst::Cmove { .. }
78
- | Inst::CmpRmiR { .. }
79
- | Inst::CvtFloatToSintSeq { .. }
80
- | Inst::CvtFloatToUintSeq { .. }
81
- | Inst::CvtUint64ToFloatSeq { .. }
82
- | Inst::Div { .. }
83
- | Inst::Div8 { .. }
84
- | Inst::Fence { .. }
85
- | Inst::Hlt
86
- | Inst::Imm { .. }
87
- | Inst::JmpCond { .. }
88
- | Inst::JmpIf { .. }
89
- | Inst::JmpKnown { .. }
90
- | Inst::JmpTableSeq { .. }
91
- | Inst::JmpUnknown { .. }
92
- | Inst::LoadEffectiveAddress { .. }
93
- | Inst::LoadExtName { .. }
94
- | Inst::LockCmpxchg { .. }
95
- | Inst::Mov64MR { .. }
96
- | Inst::MovImmM { .. }
97
- | Inst::MovRM { .. }
98
- | Inst::MovRR { .. }
99
- | Inst::MovFromPReg { .. }
100
- | Inst::MovToPReg { .. }
101
- | Inst::MovsxRmR { .. }
102
- | Inst::MovzxRmR { .. }
103
- | Inst::MulHi { .. }
104
- | Inst::UMulLo { .. }
105
- | Inst::Neg { .. }
106
- | Inst::Not { .. }
107
- | Inst::Nop { .. }
108
- | Inst::Pop64 { .. }
109
- | Inst::Push64 { .. }
110
- | Inst::StackProbeLoop { .. }
111
- | Inst::Args { .. }
112
- | Inst::Ret { .. }
113
- | Inst::Setcc { .. }
114
- | Inst::ShiftR { .. }
115
- | Inst::SignExtendData { .. }
116
- | Inst::TrapIf { .. }
117
- | Inst::TrapIfAnd { .. }
118
- | Inst::TrapIfOr { .. }
119
- | Inst::Ud2 { .. }
120
- | Inst::VirtualSPOffsetAdj { .. }
121
- | Inst::XmmCmove { .. }
122
- | Inst::XmmCmpRmR { .. }
123
- | Inst::XmmMinMaxSeq { .. }
124
- | Inst::XmmUninitializedValue { .. }
125
- | Inst::ElfTlsGetAddr { .. }
126
- | Inst::MachOTlsGetAddr { .. }
127
- | Inst::CoffTlsGetAddr { .. }
128
- | Inst::Unwind { .. }
129
- | Inst::DummyUse { .. }
130
- | Inst::AluConstOp { .. } => smallvec![],
131
-
132
- Inst::AluRmRVex { op, .. } => op.available_from(),
133
- Inst::UnaryRmR { op, .. } => op.available_from(),
134
-
135
- // These use dynamic SSE opcodes.
136
- Inst::GprToXmm { op, .. }
137
- | Inst::XmmMovRM { op, .. }
138
- | Inst::XmmMovRMImm { op, .. }
139
- | Inst::XmmRmiReg { opcode: op, .. }
140
- | Inst::XmmRmR { op, .. }
141
- | Inst::XmmRmRUnaligned { op, .. }
142
- | Inst::XmmRmRBlend { op, .. }
143
- | Inst::XmmRmRImm { op, .. }
144
- | Inst::XmmToGpr { op, .. }
145
- | Inst::XmmToGprImm { op, .. }
146
- | Inst::XmmUnaryRmRImm { op, .. }
147
- | Inst::XmmUnaryRmRUnaligned { op, .. }
148
- | Inst::XmmUnaryRmR { op, .. } => smallvec![op.available_from()],
149
-
150
- Inst::XmmUnaryRmREvex { op, .. }
151
- | Inst::XmmRmREvex { op, .. }
152
- | Inst::XmmRmREvex3 { op, .. } => op.available_from(),
153
-
154
- Inst::XmmRmiRVex { op, .. }
155
- | Inst::XmmRmRVex3 { op, .. }
156
- | Inst::XmmRmRImmVex { op, .. }
157
- | Inst::XmmRmRBlendVex { op, .. }
158
- | Inst::XmmVexPinsr { op, .. }
159
- | Inst::XmmUnaryRmRVex { op, .. }
160
- | Inst::XmmUnaryRmRImmVex { op, .. }
161
- | Inst::XmmMovRMVex { op, .. }
162
- | Inst::XmmMovRMImmVex { op, .. }
163
- | Inst::XmmToGprImmVex { op, .. }
164
- | Inst::XmmToGprVex { op, .. }
165
- | Inst::GprToXmmVex { op, .. } => op.available_from(),
166
- }
167
- }
168
- }
169
-
170
- // Handy constructors for Insts.
171
-
172
- impl Inst {
173
- pub(crate) fn nop(len: u8) -> Self {
174
- debug_assert!(len <= 15);
175
- Self::Nop { len }
176
- }
177
-
178
- pub(crate) fn alu_rmi_r(
179
- size: OperandSize,
180
- op: AluRmiROpcode,
181
- src: RegMemImm,
182
- dst: Writable<Reg>,
183
- ) -> Self {
184
- src.assert_regclass_is(RegClass::Int);
185
- debug_assert!(dst.to_reg().class() == RegClass::Int);
186
- Self::AluRmiR {
187
- size,
188
- op,
189
- src1: Gpr::new(dst.to_reg()).unwrap(),
190
- src2: GprMemImm::new(src).unwrap(),
191
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
192
- }
193
- }
194
-
195
- #[allow(dead_code)]
196
- pub(crate) fn unary_rm_r(
197
- size: OperandSize,
198
- op: UnaryRmROpcode,
199
- src: RegMem,
200
- dst: Writable<Reg>,
201
- ) -> Self {
202
- src.assert_regclass_is(RegClass::Int);
203
- debug_assert!(dst.to_reg().class() == RegClass::Int);
204
- debug_assert!(size.is_one_of(&[
205
- OperandSize::Size16,
206
- OperandSize::Size32,
207
- OperandSize::Size64
208
- ]));
209
- Self::UnaryRmR {
210
- size,
211
- op,
212
- src: GprMem::new(src).unwrap(),
213
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
214
- }
215
- }
216
-
217
- pub(crate) fn not(size: OperandSize, src: Writable<Reg>) -> Inst {
218
- debug_assert_eq!(src.to_reg().class(), RegClass::Int);
219
- Inst::Not {
220
- size,
221
- src: Gpr::new(src.to_reg()).unwrap(),
222
- dst: WritableGpr::from_writable_reg(src).unwrap(),
223
- }
224
- }
225
-
226
- pub(crate) fn div(
227
- size: OperandSize,
228
- sign: DivSignedness,
229
- trap: TrapCode,
230
- divisor: RegMem,
231
- dividend_lo: Gpr,
232
- dividend_hi: Gpr,
233
- dst_quotient: WritableGpr,
234
- dst_remainder: WritableGpr,
235
- ) -> Inst {
236
- divisor.assert_regclass_is(RegClass::Int);
237
- Inst::Div {
238
- size,
239
- sign,
240
- trap,
241
- divisor: GprMem::new(divisor).unwrap(),
242
- dividend_lo,
243
- dividend_hi,
244
- dst_quotient,
245
- dst_remainder,
246
- }
247
- }
248
-
249
- pub(crate) fn div8(
250
- sign: DivSignedness,
251
- trap: TrapCode,
252
- divisor: RegMem,
253
- dividend: Gpr,
254
- dst: WritableGpr,
255
- ) -> Inst {
256
- divisor.assert_regclass_is(RegClass::Int);
257
- Inst::Div8 {
258
- sign,
259
- trap,
260
- divisor: GprMem::new(divisor).unwrap(),
261
- dividend,
262
- dst,
263
- }
264
- }
265
-
266
- pub(crate) fn imm(dst_size: OperandSize, simm64: u64, dst: Writable<Reg>) -> Inst {
267
- debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
268
- debug_assert!(dst.to_reg().class() == RegClass::Int);
269
- // Try to generate a 32-bit immediate when the upper high bits are zeroed (which matches
270
- // the semantics of movl).
271
- let dst_size = match dst_size {
272
- OperandSize::Size64 if simm64 > u32::max_value() as u64 => OperandSize::Size64,
273
- _ => OperandSize::Size32,
274
- };
275
- Inst::Imm {
276
- dst_size,
277
- simm64,
278
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
279
- }
280
- }
281
-
282
- pub(crate) fn mov_r_r(size: OperandSize, src: Reg, dst: Writable<Reg>) -> Inst {
283
- debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
284
- debug_assert!(src.class() == RegClass::Int);
285
- debug_assert!(dst.to_reg().class() == RegClass::Int);
286
- let src = Gpr::new(src).unwrap();
287
- let dst = WritableGpr::from_writable_reg(dst).unwrap();
288
- Inst::MovRR { size, src, dst }
289
- }
290
-
291
- /// Convenient helper for unary float operations.
292
- pub(crate) fn xmm_unary_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Inst {
293
- src.assert_regclass_is(RegClass::Float);
294
- debug_assert!(dst.to_reg().class() == RegClass::Float);
295
- Inst::XmmUnaryRmR {
296
- op,
297
- src: XmmMemAligned::new(src).unwrap(),
298
- dst: WritableXmm::from_writable_reg(dst).unwrap(),
299
- }
300
- }
301
-
302
- pub(crate) fn xmm_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Self {
303
- src.assert_regclass_is(RegClass::Float);
304
- debug_assert!(dst.to_reg().class() == RegClass::Float);
305
- Inst::XmmRmR {
306
- op,
307
- src1: Xmm::new(dst.to_reg()).unwrap(),
308
- src2: XmmMemAligned::new(src).unwrap(),
309
- dst: WritableXmm::from_writable_reg(dst).unwrap(),
310
- }
311
- }
312
-
313
- #[cfg(test)]
314
- pub(crate) fn xmm_rmr_vex3(op: AvxOpcode, src3: RegMem, src2: Reg, dst: Writable<Reg>) -> Self {
315
- src3.assert_regclass_is(RegClass::Float);
316
- debug_assert!(src2.class() == RegClass::Float);
317
- debug_assert!(dst.to_reg().class() == RegClass::Float);
318
- Inst::XmmRmRVex3 {
319
- op,
320
- src3: XmmMem::new(src3).unwrap(),
321
- src2: Xmm::new(src2).unwrap(),
322
- src1: Xmm::new(dst.to_reg()).unwrap(),
323
- dst: WritableXmm::from_writable_reg(dst).unwrap(),
324
- }
325
- }
326
-
327
- pub(crate) fn xmm_mov_r_m(op: SseOpcode, src: Reg, dst: impl Into<SyntheticAmode>) -> Inst {
328
- debug_assert!(src.class() == RegClass::Float);
329
- Inst::XmmMovRM {
330
- op,
331
- src: Xmm::new(src).unwrap(),
332
- dst: dst.into(),
333
- }
334
- }
335
-
336
- pub(crate) fn xmm_to_gpr(
337
- op: SseOpcode,
338
- src: Reg,
339
- dst: Writable<Reg>,
340
- dst_size: OperandSize,
341
- ) -> Inst {
342
- debug_assert!(src.class() == RegClass::Float);
343
- debug_assert!(dst.to_reg().class() == RegClass::Int);
344
- debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
345
- Inst::XmmToGpr {
346
- op,
347
- src: Xmm::new(src).unwrap(),
348
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
349
- dst_size,
350
- }
351
- }
352
-
353
- pub(crate) fn gpr_to_xmm(
354
- op: SseOpcode,
355
- src: RegMem,
356
- src_size: OperandSize,
357
- dst: Writable<Reg>,
358
- ) -> Inst {
359
- src.assert_regclass_is(RegClass::Int);
360
- debug_assert!(src_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
361
- debug_assert!(dst.to_reg().class() == RegClass::Float);
362
- Inst::GprToXmm {
363
- op,
364
- src: GprMem::new(src).unwrap(),
365
- dst: WritableXmm::from_writable_reg(dst).unwrap(),
366
- src_size,
367
- }
368
- }
369
-
370
- pub(crate) fn xmm_cmp_rm_r(op: SseOpcode, src: RegMem, dst: Reg) -> Inst {
371
- src.assert_regclass_is(RegClass::Float);
372
- debug_assert!(dst.class() == RegClass::Float);
373
- let src = XmmMemAligned::new(src).unwrap();
374
- let dst = Xmm::new(dst).unwrap();
375
- Inst::XmmCmpRmR { op, src, dst }
376
- }
377
-
378
- #[allow(dead_code)]
379
- pub(crate) fn xmm_min_max_seq(
380
- size: OperandSize,
381
- is_min: bool,
382
- lhs: Reg,
383
- rhs: Reg,
384
- dst: Writable<Reg>,
385
- ) -> Inst {
386
- debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
387
- debug_assert_eq!(lhs.class(), RegClass::Float);
388
- debug_assert_eq!(rhs.class(), RegClass::Float);
389
- debug_assert_eq!(dst.to_reg().class(), RegClass::Float);
390
- Inst::XmmMinMaxSeq {
391
- size,
392
- is_min,
393
- lhs: Xmm::new(lhs).unwrap(),
394
- rhs: Xmm::new(rhs).unwrap(),
395
- dst: WritableXmm::from_writable_reg(dst).unwrap(),
396
- }
397
- }
398
-
399
- pub(crate) fn movzx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable<Reg>) -> Inst {
400
- src.assert_regclass_is(RegClass::Int);
401
- debug_assert!(dst.to_reg().class() == RegClass::Int);
402
- let src = GprMem::new(src).unwrap();
403
- let dst = WritableGpr::from_writable_reg(dst).unwrap();
404
- Inst::MovzxRmR { ext_mode, src, dst }
405
- }
406
-
407
- pub(crate) fn movsx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable<Reg>) -> Inst {
408
- src.assert_regclass_is(RegClass::Int);
409
- debug_assert!(dst.to_reg().class() == RegClass::Int);
410
- let src = GprMem::new(src).unwrap();
411
- let dst = WritableGpr::from_writable_reg(dst).unwrap();
412
- Inst::MovsxRmR { ext_mode, src, dst }
413
- }
414
-
415
- pub(crate) fn mov64_m_r(src: impl Into<SyntheticAmode>, dst: Writable<Reg>) -> Inst {
416
- debug_assert!(dst.to_reg().class() == RegClass::Int);
417
- Inst::Mov64MR {
418
- src: src.into(),
419
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
420
- }
421
- }
422
-
423
- pub(crate) fn mov_r_m(size: OperandSize, src: Reg, dst: impl Into<SyntheticAmode>) -> Inst {
424
- debug_assert!(src.class() == RegClass::Int);
425
- Inst::MovRM {
426
- size,
427
- src: Gpr::new(src).unwrap(),
428
- dst: dst.into(),
429
- }
430
- }
431
-
432
- pub(crate) fn lea(addr: impl Into<SyntheticAmode>, dst: Writable<Reg>) -> Inst {
433
- debug_assert!(dst.to_reg().class() == RegClass::Int);
434
- Inst::LoadEffectiveAddress {
435
- addr: addr.into(),
436
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
437
- }
438
- }
439
-
440
- pub(crate) fn shift_r(
441
- size: OperandSize,
442
- kind: ShiftKind,
443
- num_bits: Imm8Gpr,
444
- src: Reg,
445
- dst: Writable<Reg>,
446
- ) -> Inst {
447
- if let Imm8Reg::Imm8 { imm: num_bits } = num_bits.clone().to_imm8_reg() {
448
- debug_assert!(num_bits < size.to_bits());
449
- }
450
- debug_assert!(dst.to_reg().class() == RegClass::Int);
451
- Inst::ShiftR {
452
- size,
453
- kind,
454
- src: Gpr::new(src).unwrap(),
455
- num_bits,
456
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
457
- }
458
- }
459
-
460
- /// Does a comparison of dst - src for operands of size `size`, as stated by the machine
461
- /// instruction semantics. Be careful with the order of parameters!
462
- pub(crate) fn cmp_rmi_r(size: OperandSize, src: RegMemImm, dst: Reg) -> Inst {
463
- src.assert_regclass_is(RegClass::Int);
464
- debug_assert_eq!(dst.class(), RegClass::Int);
465
- Inst::CmpRmiR {
466
- size,
467
- src: GprMemImm::new(src).unwrap(),
468
- dst: Gpr::new(dst).unwrap(),
469
- opcode: CmpOpcode::Cmp,
470
- }
471
- }
472
-
473
- pub(crate) fn trap(trap_code: TrapCode) -> Inst {
474
- Inst::Ud2 { trap_code }
475
- }
476
-
477
- pub(crate) fn trap_if(cc: CC, trap_code: TrapCode) -> Inst {
478
- Inst::TrapIf { cc, trap_code }
479
- }
480
-
481
- pub(crate) fn cmove(size: OperandSize, cc: CC, src: RegMem, dst: Writable<Reg>) -> Inst {
482
- debug_assert!(size.is_one_of(&[
483
- OperandSize::Size16,
484
- OperandSize::Size32,
485
- OperandSize::Size64
486
- ]));
487
- debug_assert!(dst.to_reg().class() == RegClass::Int);
488
- Inst::Cmove {
489
- size,
490
- cc,
491
- consequent: GprMem::new(src).unwrap(),
492
- alternative: Gpr::new(dst.to_reg()).unwrap(),
493
- dst: WritableGpr::from_writable_reg(dst).unwrap(),
494
- }
495
- }
496
-
497
- pub(crate) fn push64(src: RegMemImm) -> Inst {
498
- src.assert_regclass_is(RegClass::Int);
499
- let src = GprMemImm::new(src).unwrap();
500
- Inst::Push64 { src }
501
- }
502
-
503
- pub(crate) fn pop64(dst: Writable<Reg>) -> Inst {
504
- debug_assert!(dst.to_reg().class() == RegClass::Int);
505
- let dst = WritableGpr::from_writable_reg(dst).unwrap();
506
- Inst::Pop64 { dst }
507
- }
508
-
509
- pub(crate) fn call_known(
510
- dest: ExternalName,
511
- uses: CallArgList,
512
- defs: CallRetList,
513
- clobbers: PRegSet,
514
- opcode: Opcode,
515
- ) -> Inst {
516
- Inst::CallKnown {
517
- dest,
518
- info: Box::new(CallInfo {
519
- uses,
520
- defs,
521
- clobbers,
522
- opcode,
523
- }),
524
- }
525
- }
526
-
527
- pub(crate) fn call_unknown(
528
- dest: RegMem,
529
- uses: CallArgList,
530
- defs: CallRetList,
531
- clobbers: PRegSet,
532
- opcode: Opcode,
533
- ) -> Inst {
534
- dest.assert_regclass_is(RegClass::Int);
535
- Inst::CallUnknown {
536
- dest,
537
- info: Box::new(CallInfo {
538
- uses,
539
- defs,
540
- clobbers,
541
- opcode,
542
- }),
543
- }
544
- }
545
-
546
- pub(crate) fn ret(rets: Vec<RetPair>) -> Inst {
547
- Inst::Ret { rets }
548
- }
549
-
550
- pub(crate) fn jmp_known(dst: MachLabel) -> Inst {
551
- Inst::JmpKnown { dst }
552
- }
553
-
554
- pub(crate) fn jmp_unknown(target: RegMem) -> Inst {
555
- target.assert_regclass_is(RegClass::Int);
556
- Inst::JmpUnknown { target }
557
- }
558
-
559
- /// Choose which instruction to use for loading a register value from memory. For loads smaller
560
- /// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
561
- /// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
562
- pub(crate) fn load(
563
- ty: Type,
564
- from_addr: impl Into<SyntheticAmode>,
565
- to_reg: Writable<Reg>,
566
- ext_kind: ExtKind,
567
- ) -> Inst {
568
- let rc = to_reg.to_reg().class();
569
- match rc {
570
- RegClass::Int => {
571
- let ext_mode = match ty.bytes() {
572
- 1 => Some(ExtMode::BQ),
573
- 2 => Some(ExtMode::WQ),
574
- 4 => Some(ExtMode::LQ),
575
- 8 => None,
576
- _ => unreachable!("the type should never use a scalar load: {}", ty),
577
- };
578
- if let Some(ext_mode) = ext_mode {
579
- // Values smaller than 64 bits must be extended in some way.
580
- match ext_kind {
581
- ExtKind::SignExtend => {
582
- Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
583
- }
584
- ExtKind::ZeroExtend => {
585
- Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
586
- }
587
- ExtKind::None => panic!(
588
- "expected an extension kind for extension mode: {:?}",
589
- ext_mode
590
- ),
591
- }
592
- } else {
593
- // 64-bit values can be moved directly.
594
- Inst::mov64_m_r(from_addr, to_reg)
595
- }
596
- }
597
- RegClass::Float => {
598
- let opcode = match ty {
599
- types::F32 => SseOpcode::Movss,
600
- types::F64 => SseOpcode::Movsd,
601
- types::F32X4 => SseOpcode::Movups,
602
- types::F64X2 => SseOpcode::Movupd,
603
- _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
604
- _ => unimplemented!("unable to load type: {}", ty),
605
- };
606
- Inst::xmm_unary_rm_r(opcode, RegMem::mem(from_addr), to_reg)
607
- }
608
- RegClass::Vector => unreachable!(),
609
- }
610
- }
611
-
612
- /// Choose which instruction to use for storing a register value to memory.
613
- pub(crate) fn store(ty: Type, from_reg: Reg, to_addr: impl Into<SyntheticAmode>) -> Inst {
614
- let rc = from_reg.class();
615
- match rc {
616
- RegClass::Int => Inst::mov_r_m(OperandSize::from_ty(ty), from_reg, to_addr),
617
- RegClass::Float => {
618
- let opcode = match ty {
619
- types::F32 => SseOpcode::Movss,
620
- types::F64 => SseOpcode::Movsd,
621
- types::F32X4 => SseOpcode::Movups,
622
- types::F64X2 => SseOpcode::Movupd,
623
- _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
624
- _ => unimplemented!("unable to store type: {}", ty),
625
- };
626
- Inst::xmm_mov_r_m(opcode, from_reg, to_addr)
627
- }
628
- RegClass::Vector => unreachable!(),
629
- }
630
- }
631
- }
632
-
633
- //=============================================================================
634
- // Instructions: printing
635
-
636
- impl PrettyPrint for Inst {
637
- fn pretty_print(&self, _size: u8, allocs: &mut AllocationConsumer<'_>) -> String {
638
- fn ljustify(s: String) -> String {
639
- let w = 7;
640
- if s.len() >= w {
641
- s
642
- } else {
643
- let need = usize::min(w, w - s.len());
644
- s + &format!("{nil: <width$}", nil = "", width = need)
645
- }
646
- }
647
-
648
- fn ljustify2(s1: String, s2: String) -> String {
649
- ljustify(s1 + &s2)
650
- }
651
-
652
- fn suffix_lq(size: OperandSize) -> String {
653
- match size {
654
- OperandSize::Size32 => "l",
655
- OperandSize::Size64 => "q",
656
- _ => unreachable!(),
657
- }
658
- .to_string()
659
- }
660
-
661
- #[allow(dead_code)]
662
- fn suffix_lqb(size: OperandSize) -> String {
663
- match size {
664
- OperandSize::Size32 => "l",
665
- OperandSize::Size64 => "q",
666
- _ => unreachable!(),
667
- }
668
- .to_string()
669
- }
670
-
671
- fn suffix_bwlq(size: OperandSize) -> String {
672
- match size {
673
- OperandSize::Size8 => "b".to_string(),
674
- OperandSize::Size16 => "w".to_string(),
675
- OperandSize::Size32 => "l".to_string(),
676
- OperandSize::Size64 => "q".to_string(),
677
- }
678
- }
679
-
680
- match self {
681
- Inst::Nop { len } => format!("{} len={}", ljustify("nop".to_string()), len),
682
-
683
- Inst::AluRmiR {
684
- size,
685
- op,
686
- src1,
687
- src2,
688
- dst,
689
- } => {
690
- let size_bytes = size.to_bytes();
691
- let src1 = pretty_print_reg(src1.to_reg(), size_bytes, allocs);
692
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size_bytes, allocs);
693
- let src2 = src2.pretty_print(size_bytes, allocs);
694
- format!(
695
- "{} {}, {}, {}",
696
- ljustify2(op.to_string(), suffix_bwlq(*size)),
697
- src1,
698
- src2,
699
- dst
700
- )
701
- }
702
- Inst::AluConstOp { op, dst, size } => {
703
- let size_bytes = size.to_bytes();
704
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size_bytes, allocs);
705
- format!(
706
- "{} {dst}, {dst}, {dst}",
707
- ljustify2(op.to_string(), suffix_lqb(*size)),
708
- )
709
- }
710
- Inst::AluRM {
711
- size,
712
- op,
713
- src1_dst,
714
- src2,
715
- } => {
716
- let size_bytes = size.to_bytes();
717
- let src2 = pretty_print_reg(src2.to_reg(), size_bytes, allocs);
718
- let src1_dst = src1_dst.pretty_print(size_bytes, allocs);
719
- format!(
720
- "{} {}, {}",
721
- ljustify2(op.to_string(), suffix_bwlq(*size)),
722
- src2,
723
- src1_dst,
724
- )
725
- }
726
- Inst::AluRmRVex {
727
- size,
728
- op,
729
- src1,
730
- src2,
731
- dst,
732
- } => {
733
- let size_bytes = size.to_bytes();
734
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
735
- let src1 = pretty_print_reg(src1.to_reg(), size_bytes, allocs);
736
- let src2 = pretty_print_reg(src2.to_reg(), size_bytes, allocs);
737
- format!(
738
- "{} {}, {}, {}",
739
- ljustify2(op.to_string(), String::new()),
740
- src2,
741
- src1,
742
- dst,
743
- )
744
- }
745
- Inst::UnaryRmR { src, dst, op, size } => {
746
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
747
- let src = src.pretty_print(size.to_bytes(), allocs);
748
- format!(
749
- "{} {}, {}",
750
- ljustify2(op.to_string(), suffix_bwlq(*size)),
751
- src,
752
- dst,
753
- )
754
- }
755
-
756
- Inst::Not { size, src, dst } => {
757
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
758
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
759
- format!(
760
- "{} {}, {}",
761
- ljustify2("not".to_string(), suffix_bwlq(*size)),
762
- src,
763
- dst,
764
- )
765
- }
766
-
767
- Inst::Neg { size, src, dst } => {
768
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
769
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
770
- format!(
771
- "{} {}, {}",
772
- ljustify2("neg".to_string(), suffix_bwlq(*size)),
773
- src,
774
- dst,
775
- )
776
- }
777
-
778
- Inst::Div {
779
- size,
780
- sign,
781
- trap,
782
- divisor,
783
- dividend_lo,
784
- dividend_hi,
785
- dst_quotient,
786
- dst_remainder,
787
- } => {
788
- let divisor = divisor.pretty_print(size.to_bytes(), allocs);
789
- let dividend_lo = pretty_print_reg(dividend_lo.to_reg(), size.to_bytes(), allocs);
790
- let dividend_hi = pretty_print_reg(dividend_hi.to_reg(), size.to_bytes(), allocs);
791
- let dst_quotient =
792
- pretty_print_reg(dst_quotient.to_reg().to_reg(), size.to_bytes(), allocs);
793
- let dst_remainder =
794
- pretty_print_reg(dst_remainder.to_reg().to_reg(), size.to_bytes(), allocs);
795
- format!(
796
- "{} {}, {}, {}, {}, {} ; trap={trap}",
797
- ljustify(match sign {
798
- DivSignedness::Signed => "idiv".to_string(),
799
- DivSignedness::Unsigned => "div".to_string(),
800
- }),
801
- dividend_lo,
802
- dividend_hi,
803
- divisor,
804
- dst_quotient,
805
- dst_remainder,
806
- )
807
- }
808
-
809
- Inst::Div8 {
810
- sign,
811
- trap,
812
- divisor,
813
- dividend,
814
- dst,
815
- } => {
816
- let divisor = divisor.pretty_print(1, allocs);
817
- let dividend = pretty_print_reg(dividend.to_reg(), 1, allocs);
818
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 1, allocs);
819
- format!(
820
- "{} {dividend}, {divisor}, {dst} ; trap={trap}",
821
- ljustify(match sign {
822
- DivSignedness::Signed => "idiv".to_string(),
823
- DivSignedness::Unsigned => "div".to_string(),
824
- }),
825
- )
826
- }
827
-
828
- Inst::MulHi {
829
- size,
830
- signed,
831
- src1,
832
- src2,
833
- dst_lo,
834
- dst_hi,
835
- } => {
836
- let src1 = pretty_print_reg(src1.to_reg(), size.to_bytes(), allocs);
837
- let dst_lo = pretty_print_reg(dst_lo.to_reg().to_reg(), size.to_bytes(), allocs);
838
- let dst_hi = pretty_print_reg(dst_hi.to_reg().to_reg(), size.to_bytes(), allocs);
839
- let src2 = src2.pretty_print(size.to_bytes(), allocs);
840
- format!(
841
- "{} {}, {}, {}, {}",
842
- ljustify(if *signed {
843
- "imul".to_string()
844
- } else {
845
- "mul".to_string()
846
- }),
847
- src1,
848
- src2,
849
- dst_lo,
850
- dst_hi,
851
- )
852
- }
853
-
854
- Inst::UMulLo {
855
- size,
856
- src1,
857
- src2,
858
- dst,
859
- } => {
860
- let src1 = pretty_print_reg(src1.to_reg(), size.to_bytes(), allocs);
861
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
862
- let src2 = src2.pretty_print(size.to_bytes(), allocs);
863
- format!(
864
- "{} {}, {}, {}",
865
- ljustify2("mul".to_string(), suffix_bwlq(*size)),
866
- src1,
867
- src2,
868
- dst,
869
- )
870
- }
871
-
872
- Inst::CheckedSRemSeq {
873
- size,
874
- divisor,
875
- dividend_lo,
876
- dividend_hi,
877
- dst_quotient,
878
- dst_remainder,
879
- } => {
880
- let divisor = pretty_print_reg(divisor.to_reg(), size.to_bytes(), allocs);
881
- let dividend_lo = pretty_print_reg(dividend_lo.to_reg(), size.to_bytes(), allocs);
882
- let dividend_hi = pretty_print_reg(dividend_hi.to_reg(), size.to_bytes(), allocs);
883
- let dst_quotient =
884
- pretty_print_reg(dst_quotient.to_reg().to_reg(), size.to_bytes(), allocs);
885
- let dst_remainder =
886
- pretty_print_reg(dst_remainder.to_reg().to_reg(), size.to_bytes(), allocs);
887
- format!(
888
- "checked_srem_seq {dividend_lo}, {dividend_hi}, \
889
- {divisor}, {dst_quotient}, {dst_remainder}",
890
- )
891
- }
892
-
893
- Inst::CheckedSRemSeq8 {
894
- divisor,
895
- dividend,
896
- dst,
897
- } => {
898
- let divisor = pretty_print_reg(divisor.to_reg(), 1, allocs);
899
- let dividend = pretty_print_reg(dividend.to_reg(), 1, allocs);
900
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 1, allocs);
901
- format!("checked_srem_seq {dividend}, {divisor}, {dst}")
902
- }
903
-
904
- Inst::SignExtendData { size, src, dst } => {
905
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
906
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
907
- format!(
908
- "{} {}, {}",
909
- match size {
910
- OperandSize::Size8 => "cbw",
911
- OperandSize::Size16 => "cwd",
912
- OperandSize::Size32 => "cdq",
913
- OperandSize::Size64 => "cqo",
914
- },
915
- src,
916
- dst,
917
- )
918
- }
919
-
920
- Inst::XmmUnaryRmR { op, src, dst, .. } => {
921
- let dst = pretty_print_reg(dst.to_reg().to_reg(), op.src_size(), allocs);
922
- let src = src.pretty_print(op.src_size(), allocs);
923
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
924
- }
925
-
926
- Inst::XmmUnaryRmRUnaligned { op, src, dst, .. } => {
927
- let dst = pretty_print_reg(dst.to_reg().to_reg(), op.src_size(), allocs);
928
- let src = src.pretty_print(op.src_size(), allocs);
929
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
930
- }
931
-
932
- Inst::XmmUnaryRmRImm {
933
- op, src, dst, imm, ..
934
- } => {
935
- let dst = pretty_print_reg(dst.to_reg().to_reg(), op.src_size(), allocs);
936
- let src = src.pretty_print(op.src_size(), allocs);
937
- format!("{} ${}, {}, {}", ljustify(op.to_string()), imm, src, dst)
938
- }
939
-
940
- Inst::XmmUnaryRmRVex { op, src, dst, .. } => {
941
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
942
- let src = src.pretty_print(8, allocs);
943
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
944
- }
945
-
946
- Inst::XmmUnaryRmRImmVex {
947
- op, src, dst, imm, ..
948
- } => {
949
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
950
- let src = src.pretty_print(8, allocs);
951
- format!("{} ${imm}, {}, {}", ljustify(op.to_string()), src, dst)
952
- }
953
-
954
- Inst::XmmUnaryRmREvex { op, src, dst, .. } => {
955
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
956
- let src = src.pretty_print(8, allocs);
957
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
958
- }
959
-
960
- Inst::XmmMovRM { op, src, dst, .. } => {
961
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
962
- let dst = dst.pretty_print(8, allocs);
963
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
964
- }
965
-
966
- Inst::XmmMovRMVex { op, src, dst, .. } => {
967
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
968
- let dst = dst.pretty_print(8, allocs);
969
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
970
- }
971
-
972
- Inst::XmmMovRMImm {
973
- op, src, dst, imm, ..
974
- } => {
975
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
976
- let dst = dst.pretty_print(8, allocs);
977
- format!("{} ${imm}, {}, {}", ljustify(op.to_string()), src, dst)
978
- }
979
-
980
- Inst::XmmMovRMImmVex {
981
- op, src, dst, imm, ..
982
- } => {
983
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
984
- let dst = dst.pretty_print(8, allocs);
985
- format!("{} ${imm}, {}, {}", ljustify(op.to_string()), src, dst)
986
- }
987
-
988
- Inst::XmmRmR {
989
- op,
990
- src1,
991
- src2,
992
- dst,
993
- ..
994
- } => {
995
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
996
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
997
- let src2 = src2.pretty_print(8, allocs);
998
- format!("{} {}, {}, {}", ljustify(op.to_string()), src1, src2, dst)
999
- }
1000
-
1001
- Inst::XmmRmRUnaligned {
1002
- op,
1003
- src1,
1004
- src2,
1005
- dst,
1006
- ..
1007
- } => {
1008
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1009
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1010
- let src2 = src2.pretty_print(8, allocs);
1011
- format!("{} {}, {}, {}", ljustify(op.to_string()), src1, src2, dst)
1012
- }
1013
-
1014
- Inst::XmmRmRBlend {
1015
- op,
1016
- src1,
1017
- src2,
1018
- mask,
1019
- dst,
1020
- } => {
1021
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1022
- let mask = allocs.next(mask.to_reg());
1023
- let mask = if mask.is_virtual() {
1024
- format!(" <{}>", show_ireg_sized(mask, 8))
1025
- } else {
1026
- debug_assert_eq!(mask, regs::xmm0());
1027
- String::new()
1028
- };
1029
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1030
- let src2 = src2.pretty_print(8, allocs);
1031
- format!(
1032
- "{} {}, {}, {}{}",
1033
- ljustify(op.to_string()),
1034
- src1,
1035
- src2,
1036
- dst,
1037
- mask
1038
- )
1039
- }
1040
-
1041
- Inst::XmmRmiRVex {
1042
- op,
1043
- src1,
1044
- src2,
1045
- dst,
1046
- ..
1047
- } => {
1048
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1049
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1050
- let src2 = src2.pretty_print(8, allocs);
1051
-
1052
- format!("{} {}, {}, {}", ljustify(op.to_string()), src1, src2, dst)
1053
- }
1054
-
1055
- Inst::XmmRmRImmVex {
1056
- op,
1057
- src1,
1058
- src2,
1059
- dst,
1060
- imm,
1061
- ..
1062
- } => {
1063
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1064
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1065
- let src2 = src2.pretty_print(8, allocs);
1066
-
1067
- format!("{} ${imm}, {src1}, {src2}, {dst}", ljustify(op.to_string()))
1068
- }
1069
-
1070
- Inst::XmmVexPinsr {
1071
- op,
1072
- src1,
1073
- src2,
1074
- dst,
1075
- imm,
1076
- ..
1077
- } => {
1078
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1079
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1080
- let src2 = src2.pretty_print(8, allocs);
1081
-
1082
- format!("{} ${imm}, {src1}, {src2}, {dst}", ljustify(op.to_string()))
1083
- }
1084
-
1085
- Inst::XmmRmRVex3 {
1086
- op,
1087
- src1,
1088
- src2,
1089
- src3,
1090
- dst,
1091
- ..
1092
- } => {
1093
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1094
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1095
- let src2 = pretty_print_reg(src2.to_reg(), 8, allocs);
1096
- let src3 = src3.pretty_print(8, allocs);
1097
-
1098
- format!(
1099
- "{} {}, {}, {}, {}",
1100
- ljustify(op.to_string()),
1101
- src1,
1102
- src2,
1103
- src3,
1104
- dst
1105
- )
1106
- }
1107
-
1108
- Inst::XmmRmRBlendVex {
1109
- op,
1110
- src1,
1111
- src2,
1112
- mask,
1113
- dst,
1114
- ..
1115
- } => {
1116
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1117
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1118
- let src2 = src2.pretty_print(8, allocs);
1119
- let mask = pretty_print_reg(mask.to_reg(), 8, allocs);
1120
-
1121
- format!("{} {src1}, {src2}, {mask}, {dst}", ljustify(op.to_string()))
1122
- }
1123
-
1124
- Inst::XmmRmREvex {
1125
- op,
1126
- src1,
1127
- src2,
1128
- dst,
1129
- ..
1130
- } => {
1131
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1132
- let src2 = pretty_print_reg(src2.to_reg(), 8, allocs);
1133
- let src1 = src1.pretty_print(8, allocs);
1134
- format!("{} {}, {}, {}", ljustify(op.to_string()), src1, src2, dst)
1135
- }
1136
-
1137
- Inst::XmmRmREvex3 {
1138
- op,
1139
- src1,
1140
- src2,
1141
- src3,
1142
- dst,
1143
- ..
1144
- } => {
1145
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1146
- let src2 = pretty_print_reg(src2.to_reg(), 8, allocs);
1147
- let src3 = pretty_print_reg(src3.to_reg(), 8, allocs);
1148
- let src1 = src1.pretty_print(8, allocs);
1149
- format!(
1150
- "{} {}, {}, {}, {}",
1151
- ljustify(op.to_string()),
1152
- src1,
1153
- src2,
1154
- src3,
1155
- dst
1156
- )
1157
- }
1158
-
1159
- Inst::XmmMinMaxSeq {
1160
- lhs,
1161
- rhs,
1162
- dst,
1163
- is_min,
1164
- size,
1165
- } => {
1166
- let rhs = pretty_print_reg(rhs.to_reg(), 8, allocs);
1167
- let lhs = pretty_print_reg(lhs.to_reg(), 8, allocs);
1168
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1169
- format!(
1170
- "{} {}, {}, {}",
1171
- ljustify2(
1172
- if *is_min {
1173
- "xmm min seq ".to_string()
1174
- } else {
1175
- "xmm max seq ".to_string()
1176
- },
1177
- format!("f{}", size.to_bits())
1178
- ),
1179
- lhs,
1180
- rhs,
1181
- dst
1182
- )
1183
- }
1184
-
1185
- Inst::XmmRmRImm {
1186
- op,
1187
- src1,
1188
- src2,
1189
- dst,
1190
- imm,
1191
- size,
1192
- ..
1193
- } => {
1194
- let src1 = pretty_print_reg(*src1, 8, allocs);
1195
- let dst = pretty_print_reg(dst.to_reg(), 8, allocs);
1196
- let src2 = src2.pretty_print(8, allocs);
1197
- format!(
1198
- "{} ${imm}, {src1}, {src2}, {dst}",
1199
- ljustify(format!(
1200
- "{}{}",
1201
- op.to_string(),
1202
- if *size == OperandSize::Size64 {
1203
- ".w"
1204
- } else {
1205
- ""
1206
- }
1207
- )),
1208
- )
1209
- }
1210
-
1211
- Inst::XmmUninitializedValue { dst } => {
1212
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1213
- format!("{} {}", ljustify("uninit".into()), dst)
1214
- }
1215
-
1216
- Inst::XmmToGpr {
1217
- op,
1218
- src,
1219
- dst,
1220
- dst_size,
1221
- } => {
1222
- let dst_size = dst_size.to_bytes();
1223
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1224
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size, allocs);
1225
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
1226
- }
1227
-
1228
- Inst::XmmToGprVex {
1229
- op,
1230
- src,
1231
- dst,
1232
- dst_size,
1233
- } => {
1234
- let dst_size = dst_size.to_bytes();
1235
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1236
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size, allocs);
1237
- format!("{} {src}, {dst}", ljustify(op.to_string()))
1238
- }
1239
-
1240
- Inst::XmmToGprImm { op, src, dst, imm } => {
1241
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1242
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1243
- format!("{} ${imm}, {}, {}", ljustify(op.to_string()), src, dst)
1244
- }
1245
-
1246
- Inst::XmmToGprImmVex { op, src, dst, imm } => {
1247
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1248
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1249
- format!("{} ${imm}, {}, {}", ljustify(op.to_string()), src, dst)
1250
- }
1251
-
1252
- Inst::GprToXmm {
1253
- op,
1254
- src,
1255
- src_size,
1256
- dst,
1257
- } => {
1258
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1259
- let src = src.pretty_print(src_size.to_bytes(), allocs);
1260
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
1261
- }
1262
-
1263
- Inst::GprToXmmVex {
1264
- op,
1265
- src,
1266
- src_size,
1267
- dst,
1268
- } => {
1269
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1270
- let src = src.pretty_print(src_size.to_bytes(), allocs);
1271
- format!("{} {src}, {dst}", ljustify(op.to_string()))
1272
- }
1273
-
1274
- Inst::XmmCmpRmR { op, src, dst } => {
1275
- let dst = pretty_print_reg(dst.to_reg(), 8, allocs);
1276
- let src = src.pretty_print(8, allocs);
1277
- format!("{} {}, {}", ljustify(op.to_string()), src, dst)
1278
- }
1279
-
1280
- Inst::CvtUint64ToFloatSeq {
1281
- src,
1282
- dst,
1283
- dst_size,
1284
- tmp_gpr1,
1285
- tmp_gpr2,
1286
- ..
1287
- } => {
1288
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1289
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size.to_bytes(), allocs);
1290
- let tmp_gpr1 = pretty_print_reg(tmp_gpr1.to_reg().to_reg(), 8, allocs);
1291
- let tmp_gpr2 = pretty_print_reg(tmp_gpr2.to_reg().to_reg(), 8, allocs);
1292
- format!(
1293
- "{} {}, {}, {}, {}",
1294
- ljustify(format!(
1295
- "u64_to_{}_seq",
1296
- if *dst_size == OperandSize::Size64 {
1297
- "f64"
1298
- } else {
1299
- "f32"
1300
- }
1301
- )),
1302
- src,
1303
- dst,
1304
- tmp_gpr1,
1305
- tmp_gpr2
1306
- )
1307
- }
1308
-
1309
- Inst::CvtFloatToSintSeq {
1310
- src,
1311
- dst,
1312
- src_size,
1313
- dst_size,
1314
- tmp_xmm,
1315
- tmp_gpr,
1316
- is_saturating,
1317
- } => {
1318
- let src = pretty_print_reg(src.to_reg(), src_size.to_bytes(), allocs);
1319
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size.to_bytes(), allocs);
1320
- let tmp_gpr = pretty_print_reg(tmp_gpr.to_reg().to_reg(), 8, allocs);
1321
- let tmp_xmm = pretty_print_reg(tmp_xmm.to_reg().to_reg(), 8, allocs);
1322
- format!(
1323
- "{} {}, {}, {}, {}",
1324
- ljustify(format!(
1325
- "cvt_float{}_to_sint{}{}_seq",
1326
- src_size.to_bits(),
1327
- dst_size.to_bits(),
1328
- if *is_saturating { "_sat" } else { "" },
1329
- )),
1330
- src,
1331
- dst,
1332
- tmp_gpr,
1333
- tmp_xmm,
1334
- )
1335
- }
1336
-
1337
- Inst::CvtFloatToUintSeq {
1338
- src,
1339
- dst,
1340
- src_size,
1341
- dst_size,
1342
- tmp_gpr,
1343
- tmp_xmm,
1344
- tmp_xmm2,
1345
- is_saturating,
1346
- } => {
1347
- let src = pretty_print_reg(src.to_reg(), src_size.to_bytes(), allocs);
1348
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size.to_bytes(), allocs);
1349
- let tmp_gpr = pretty_print_reg(tmp_gpr.to_reg().to_reg(), 8, allocs);
1350
- let tmp_xmm = pretty_print_reg(tmp_xmm.to_reg().to_reg(), 8, allocs);
1351
- let tmp_xmm2 = pretty_print_reg(tmp_xmm2.to_reg().to_reg(), 8, allocs);
1352
- format!(
1353
- "{} {}, {}, {}, {}, {}",
1354
- ljustify(format!(
1355
- "cvt_float{}_to_uint{}{}_seq",
1356
- src_size.to_bits(),
1357
- dst_size.to_bits(),
1358
- if *is_saturating { "_sat" } else { "" },
1359
- )),
1360
- src,
1361
- dst,
1362
- tmp_gpr,
1363
- tmp_xmm,
1364
- tmp_xmm2,
1365
- )
1366
- }
1367
-
1368
- Inst::Imm {
1369
- dst_size,
1370
- simm64,
1371
- dst,
1372
- } => {
1373
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size.to_bytes(), allocs);
1374
- if *dst_size == OperandSize::Size64 {
1375
- format!(
1376
- "{} ${}, {}",
1377
- ljustify("movabsq".to_string()),
1378
- *simm64 as i64,
1379
- dst,
1380
- )
1381
- } else {
1382
- format!(
1383
- "{} ${}, {}",
1384
- ljustify("movl".to_string()),
1385
- (*simm64 as u32) as i32,
1386
- dst,
1387
- )
1388
- }
1389
- }
1390
-
1391
- Inst::MovImmM { size, simm64, dst } => {
1392
- let dst = dst.pretty_print(size.to_bytes(), allocs);
1393
- let suffix = suffix_bwlq(*size);
1394
- let instruction = ljustify2("mov".to_string(), suffix);
1395
-
1396
- match *size {
1397
- OperandSize::Size8 => {
1398
- format!("{} ${}, {}", instruction, (*simm64 as u8) as i8, dst)
1399
- }
1400
- OperandSize::Size16 => {
1401
- format!("{} ${}, {}", instruction, (*simm64 as u16) as i16, dst)
1402
- }
1403
- OperandSize::Size32 => {
1404
- format!("{} ${}, {}", instruction, (*simm64 as u32) as i32, dst)
1405
- }
1406
- OperandSize::Size64 => format!("{} ${}, {}", instruction, *simm64 as i64, dst),
1407
- }
1408
- }
1409
-
1410
- Inst::MovRR { size, src, dst } => {
1411
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
1412
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
1413
- format!(
1414
- "{} {}, {}",
1415
- ljustify2("mov".to_string(), suffix_lq(*size)),
1416
- src,
1417
- dst
1418
- )
1419
- }
1420
-
1421
- Inst::MovFromPReg { src, dst } => {
1422
- allocs.next_fixed_nonallocatable(*src);
1423
- let src: Reg = (*src).into();
1424
- let src = regs::show_ireg_sized(src, 8);
1425
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1426
- format!("{} {}, {}", ljustify("movq".to_string()), src, dst)
1427
- }
1428
-
1429
- Inst::MovToPReg { src, dst } => {
1430
- let src = pretty_print_reg(src.to_reg(), 8, allocs);
1431
- allocs.next_fixed_nonallocatable(*dst);
1432
- let dst: Reg = (*dst).into();
1433
- let dst = regs::show_ireg_sized(dst, 8);
1434
- format!("{} {}, {}", ljustify("movq".to_string()), src, dst)
1435
- }
1436
-
1437
- Inst::MovzxRmR {
1438
- ext_mode, src, dst, ..
1439
- } => {
1440
- let dst_size = if *ext_mode == ExtMode::LQ {
1441
- 4
1442
- } else {
1443
- ext_mode.dst_size()
1444
- };
1445
- let dst = pretty_print_reg(dst.to_reg().to_reg(), dst_size, allocs);
1446
- let src = src.pretty_print(ext_mode.src_size(), allocs);
1447
- if *ext_mode == ExtMode::LQ {
1448
- format!("{} {}, {}", ljustify("movl".to_string()), src, dst)
1449
- } else {
1450
- format!(
1451
- "{} {}, {}",
1452
- ljustify2("movz".to_string(), ext_mode.to_string()),
1453
- src,
1454
- dst,
1455
- )
1456
- }
1457
- }
1458
-
1459
- Inst::Mov64MR { src, dst, .. } => {
1460
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1461
- let src = src.pretty_print(8, allocs);
1462
- format!("{} {}, {}", ljustify("movq".to_string()), src, dst)
1463
- }
1464
-
1465
- Inst::LoadEffectiveAddress { addr, dst } => {
1466
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1467
- let addr = addr.pretty_print(8, allocs);
1468
- format!("{} {}, {}", ljustify("lea".to_string()), addr, dst)
1469
- }
1470
-
1471
- Inst::MovsxRmR {
1472
- ext_mode, src, dst, ..
1473
- } => {
1474
- let dst = pretty_print_reg(dst.to_reg().to_reg(), ext_mode.dst_size(), allocs);
1475
- let src = src.pretty_print(ext_mode.src_size(), allocs);
1476
- format!(
1477
- "{} {}, {}",
1478
- ljustify2("movs".to_string(), ext_mode.to_string()),
1479
- src,
1480
- dst
1481
- )
1482
- }
1483
-
1484
- Inst::MovRM { size, src, dst, .. } => {
1485
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
1486
- let dst = dst.pretty_print(size.to_bytes(), allocs);
1487
- format!(
1488
- "{} {}, {}",
1489
- ljustify2("mov".to_string(), suffix_bwlq(*size)),
1490
- src,
1491
- dst
1492
- )
1493
- }
1494
-
1495
- Inst::ShiftR {
1496
- size,
1497
- kind,
1498
- num_bits,
1499
- src,
1500
- dst,
1501
- ..
1502
- } => {
1503
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
1504
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
1505
- match num_bits.clone().to_imm8_reg() {
1506
- Imm8Reg::Reg { reg } => {
1507
- let reg = pretty_print_reg(reg, 1, allocs);
1508
- format!(
1509
- "{} {}, {}, {}",
1510
- ljustify2(kind.to_string(), suffix_bwlq(*size)),
1511
- reg,
1512
- src,
1513
- dst,
1514
- )
1515
- }
1516
-
1517
- Imm8Reg::Imm8 { imm: num_bits } => format!(
1518
- "{} ${}, {}, {}",
1519
- ljustify2(kind.to_string(), suffix_bwlq(*size)),
1520
- num_bits,
1521
- src,
1522
- dst,
1523
- ),
1524
- }
1525
- }
1526
-
1527
- Inst::XmmRmiReg {
1528
- opcode,
1529
- src1,
1530
- src2,
1531
- dst,
1532
- ..
1533
- } => {
1534
- let src1 = pretty_print_reg(src1.to_reg(), 8, allocs);
1535
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1536
- let src2 = src2.pretty_print(8, allocs);
1537
- format!(
1538
- "{} {}, {}, {}",
1539
- ljustify(opcode.to_string()),
1540
- src1,
1541
- src2,
1542
- dst,
1543
- )
1544
- }
1545
-
1546
- Inst::CmpRmiR {
1547
- size,
1548
- src,
1549
- dst,
1550
- opcode,
1551
- } => {
1552
- let dst = pretty_print_reg(dst.to_reg(), size.to_bytes(), allocs);
1553
- let src = src.pretty_print(size.to_bytes(), allocs);
1554
- let op = match opcode {
1555
- CmpOpcode::Cmp => "cmp",
1556
- CmpOpcode::Test => "test",
1557
- };
1558
- format!(
1559
- "{} {}, {}",
1560
- ljustify2(op.to_string(), suffix_bwlq(*size)),
1561
- src,
1562
- dst,
1563
- )
1564
- }
1565
-
1566
- Inst::Setcc { cc, dst } => {
1567
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 1, allocs);
1568
- format!("{} {}", ljustify2("set".to_string(), cc.to_string()), dst)
1569
- }
1570
-
1571
- Inst::Bswap { size, src, dst } => {
1572
- let src = pretty_print_reg(src.to_reg(), size.to_bytes(), allocs);
1573
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
1574
- format!(
1575
- "{} {}, {}",
1576
- ljustify2("bswap".to_string(), suffix_bwlq(*size)),
1577
- src,
1578
- dst
1579
- )
1580
- }
1581
-
1582
- Inst::Cmove {
1583
- size,
1584
- cc,
1585
- consequent,
1586
- alternative,
1587
- dst,
1588
- } => {
1589
- let alternative = pretty_print_reg(alternative.to_reg(), size.to_bytes(), allocs);
1590
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size.to_bytes(), allocs);
1591
- let consequent = consequent.pretty_print(size.to_bytes(), allocs);
1592
- format!(
1593
- "{} {}, {}, {}",
1594
- ljustify(format!("cmov{}{}", cc.to_string(), suffix_bwlq(*size))),
1595
- consequent,
1596
- alternative,
1597
- dst,
1598
- )
1599
- }
1600
-
1601
- Inst::XmmCmove {
1602
- ty,
1603
- cc,
1604
- consequent,
1605
- alternative,
1606
- dst,
1607
- ..
1608
- } => {
1609
- let size = u8::try_from(ty.bytes()).unwrap();
1610
- let alternative = pretty_print_reg(alternative.to_reg(), size, allocs);
1611
- let dst = pretty_print_reg(dst.to_reg().to_reg(), size, allocs);
1612
- let consequent = consequent.pretty_print(size, allocs);
1613
- let suffix = match *ty {
1614
- types::F64 => "sd",
1615
- types::F32 => "ss",
1616
- types::F32X4 => "aps",
1617
- types::F64X2 => "apd",
1618
- _ => "dqa",
1619
- };
1620
- format!(
1621
- "mov{suffix} {alternative}, {dst}; \
1622
- j{} $next; \
1623
- mov{suffix} {consequent}, {dst}; \
1624
- $next:",
1625
- cc.invert().to_string(),
1626
- )
1627
- }
1628
-
1629
- Inst::Push64 { src } => {
1630
- let src = src.pretty_print(8, allocs);
1631
- format!("{} {}", ljustify("pushq".to_string()), src)
1632
- }
1633
-
1634
- Inst::StackProbeLoop {
1635
- tmp,
1636
- frame_size,
1637
- guard_size,
1638
- } => {
1639
- let tmp = pretty_print_reg(tmp.to_reg(), 8, allocs);
1640
- format!(
1641
- "{} {}, frame_size={}, guard_size={}",
1642
- ljustify("stack_probe_loop".to_string()),
1643
- tmp,
1644
- frame_size,
1645
- guard_size
1646
- )
1647
- }
1648
-
1649
- Inst::Pop64 { dst } => {
1650
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1651
- format!("{} {}", ljustify("popq".to_string()), dst)
1652
- }
1653
-
1654
- Inst::CallKnown { dest, .. } => {
1655
- format!("{} {:?}", ljustify("call".to_string()), dest)
1656
- }
1657
-
1658
- Inst::CallUnknown { dest, .. } => {
1659
- let dest = dest.pretty_print(8, allocs);
1660
- format!("{} *{}", ljustify("call".to_string()), dest)
1661
- }
1662
-
1663
- Inst::Args { args } => {
1664
- let mut s = "args".to_string();
1665
- for arg in args {
1666
- use std::fmt::Write;
1667
- let preg = regs::show_reg(arg.preg);
1668
- let def = pretty_print_reg(arg.vreg.to_reg(), 8, allocs);
1669
- write!(&mut s, " {}={}", def, preg).unwrap();
1670
- }
1671
- s
1672
- }
1673
-
1674
- Inst::Ret { rets } => {
1675
- let mut s = "ret".to_string();
1676
- for ret in rets {
1677
- use std::fmt::Write;
1678
- let preg = regs::show_reg(ret.preg);
1679
- let vreg = pretty_print_reg(ret.vreg, 8, allocs);
1680
- write!(&mut s, " {}={}", vreg, preg).unwrap();
1681
- }
1682
- s
1683
- }
1684
-
1685
- Inst::JmpKnown { dst } => {
1686
- format!("{} {}", ljustify("jmp".to_string()), dst.to_string())
1687
- }
1688
-
1689
- Inst::JmpIf { cc, taken } => format!(
1690
- "{} {}",
1691
- ljustify2("j".to_string(), cc.to_string()),
1692
- taken.to_string(),
1693
- ),
1694
-
1695
- Inst::JmpCond {
1696
- cc,
1697
- taken,
1698
- not_taken,
1699
- } => format!(
1700
- "{} {}; j {}",
1701
- ljustify2("j".to_string(), cc.to_string()),
1702
- taken.to_string(),
1703
- not_taken.to_string()
1704
- ),
1705
-
1706
- Inst::JmpTableSeq {
1707
- idx, tmp1, tmp2, ..
1708
- } => {
1709
- let idx = pretty_print_reg(*idx, 8, allocs);
1710
- let tmp1 = pretty_print_reg(tmp1.to_reg(), 8, allocs);
1711
- let tmp2 = pretty_print_reg(tmp2.to_reg(), 8, allocs);
1712
- format!(
1713
- "{} {}, {}, {}",
1714
- ljustify("br_table".into()),
1715
- idx,
1716
- tmp1,
1717
- tmp2
1718
- )
1719
- }
1720
-
1721
- Inst::JmpUnknown { target } => {
1722
- let target = target.pretty_print(8, allocs);
1723
- format!("{} *{}", ljustify("jmp".to_string()), target)
1724
- }
1725
-
1726
- Inst::TrapIf { cc, trap_code, .. } => {
1727
- format!("j{cc} #trap={trap_code}")
1728
- }
1729
-
1730
- Inst::TrapIfAnd {
1731
- cc1,
1732
- cc2,
1733
- trap_code,
1734
- ..
1735
- } => {
1736
- format!(
1737
- "trap_if_and {}, {}, {}",
1738
- cc1.invert().to_string(),
1739
- cc2.invert().to_string(),
1740
- trap_code
1741
- )
1742
- }
1743
-
1744
- Inst::TrapIfOr {
1745
- cc1,
1746
- cc2,
1747
- trap_code,
1748
- ..
1749
- } => {
1750
- format!(
1751
- "trap_if_or {}, {}, {}",
1752
- cc1.to_string(),
1753
- cc2.invert().to_string(),
1754
- trap_code
1755
- )
1756
- }
1757
-
1758
- Inst::LoadExtName {
1759
- dst, name, offset, ..
1760
- } => {
1761
- let dst = pretty_print_reg(dst.to_reg(), 8, allocs);
1762
- format!(
1763
- "{} {}+{}, {}",
1764
- ljustify("load_ext_name".into()),
1765
- name.display(None),
1766
- offset,
1767
- dst,
1768
- )
1769
- }
1770
-
1771
- Inst::LockCmpxchg {
1772
- ty,
1773
- replacement,
1774
- expected,
1775
- mem,
1776
- dst_old,
1777
- ..
1778
- } => {
1779
- let size = ty.bytes() as u8;
1780
- let replacement = pretty_print_reg(*replacement, size, allocs);
1781
- let expected = pretty_print_reg(*expected, size, allocs);
1782
- let dst_old = pretty_print_reg(dst_old.to_reg(), size, allocs);
1783
- let mem = mem.pretty_print(size, allocs);
1784
- format!(
1785
- "lock cmpxchg{} {}, {}, expected={}, dst_old={}",
1786
- suffix_bwlq(OperandSize::from_bytes(size as u32)),
1787
- replacement,
1788
- mem,
1789
- expected,
1790
- dst_old,
1791
- )
1792
- }
1793
-
1794
- Inst::AtomicRmwSeq { ty, op, .. } => {
1795
- format!(
1796
- "atomically {{ {}_bits_at_[%r9]) {:?}= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }}",
1797
- ty.bits(), op)
1798
- }
1799
-
1800
- Inst::Fence { kind } => match kind {
1801
- FenceKind::MFence => "mfence".to_string(),
1802
- FenceKind::LFence => "lfence".to_string(),
1803
- FenceKind::SFence => "sfence".to_string(),
1804
- },
1805
-
1806
- Inst::VirtualSPOffsetAdj { offset } => format!("virtual_sp_offset_adjust {}", offset),
1807
-
1808
- Inst::Hlt => "hlt".into(),
1809
-
1810
- Inst::Ud2 { trap_code } => format!("ud2 {}", trap_code),
1811
-
1812
- Inst::ElfTlsGetAddr { ref symbol, dst } => {
1813
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1814
- format!("{} = elf_tls_get_addr {:?}", dst, symbol)
1815
- }
1816
-
1817
- Inst::MachOTlsGetAddr { ref symbol, dst } => {
1818
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1819
- format!("{} = macho_tls_get_addr {:?}", dst, symbol)
1820
- }
1821
-
1822
- Inst::CoffTlsGetAddr {
1823
- ref symbol,
1824
- dst,
1825
- tmp,
1826
- } => {
1827
- use std::fmt::Write;
1828
-
1829
- let dst = pretty_print_reg(dst.to_reg().to_reg(), 8, allocs);
1830
- let tmp = allocs.next(tmp.to_reg().to_reg());
1831
-
1832
- let mut s = format!("{} = coff_tls_get_addr {:?}", dst, symbol);
1833
- if tmp.is_virtual() {
1834
- write!(&mut s, ", {}", show_ireg_sized(tmp, 8)).unwrap();
1835
- };
1836
-
1837
- s
1838
- }
1839
-
1840
- Inst::Unwind { inst } => {
1841
- format!("unwind {:?}", inst)
1842
- }
1843
-
1844
- Inst::DummyUse { reg } => {
1845
- let reg = pretty_print_reg(*reg, 8, allocs);
1846
- format!("dummy_use {}", reg)
1847
- }
1848
- }
1849
- }
1850
- }
1851
-
1852
- impl fmt::Debug for Inst {
1853
- fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
1854
- write!(
1855
- fmt,
1856
- "{}",
1857
- self.pretty_print_inst(&[], &mut Default::default())
1858
- )
1859
- }
1860
- }
1861
-
1862
- fn x64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCollector<'_, F>) {
1863
- // FIXME: remove all remaining `mod` operands here to get to pure
1864
- // SSA.
1865
-
1866
- // Note: because we need to statically know the indices of each
1867
- // reg in the operands list in order to fetch its allocation
1868
- // later, we put the variable-operand-count bits (the RegMem,
1869
- // RegMemImm, etc args) last. regalloc2 doesn't care what order
1870
- // the operands come in; they can be freely reordered.
1871
-
1872
- // N.B.: we MUST keep the below in careful sync with (i) emission,
1873
- // in `emit.rs`, and (ii) pretty-printing, in the `pretty_print`
1874
- // method above.
1875
- match inst {
1876
- Inst::AluRmiR {
1877
- size,
1878
- op,
1879
- src1,
1880
- src2,
1881
- dst,
1882
- ..
1883
- } => {
1884
- if *size == OperandSize::Size8 && *op == AluRmiROpcode::Mul {
1885
- // 8-bit imul has RAX as a fixed input/output
1886
- collector.reg_fixed_use(src1.to_reg(), regs::rax());
1887
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
1888
- src2.get_operands(collector);
1889
- } else {
1890
- collector.reg_use(src1.to_reg());
1891
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
1892
- src2.get_operands(collector);
1893
- }
1894
- }
1895
- Inst::AluConstOp { dst, .. } => collector.reg_def(dst.to_writable_reg()),
1896
- Inst::AluRM { src1_dst, src2, .. } => {
1897
- collector.reg_use(src2.to_reg());
1898
- src1_dst.get_operands(collector);
1899
- }
1900
- Inst::AluRmRVex {
1901
- src1, src2, dst, ..
1902
- } => {
1903
- collector.reg_def(dst.to_writable_reg());
1904
- collector.reg_use(src1.to_reg());
1905
- collector.reg_use(src2.to_reg());
1906
- }
1907
- Inst::Not { src, dst, .. } => {
1908
- collector.reg_use(src.to_reg());
1909
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
1910
- }
1911
- Inst::Neg { src, dst, .. } => {
1912
- collector.reg_use(src.to_reg());
1913
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
1914
- }
1915
- Inst::Div {
1916
- dividend_lo,
1917
- dividend_hi,
1918
- dst_quotient,
1919
- dst_remainder,
1920
- ..
1921
- }
1922
- | Inst::CheckedSRemSeq {
1923
- dividend_lo,
1924
- dividend_hi,
1925
- dst_quotient,
1926
- dst_remainder,
1927
- ..
1928
- } => {
1929
- match inst {
1930
- Inst::Div { divisor, .. } => divisor.get_operands(collector),
1931
- Inst::CheckedSRemSeq { divisor, .. } => collector.reg_use(divisor.to_reg()),
1932
- _ => {}
1933
- }
1934
- collector.reg_fixed_use(dividend_lo.to_reg(), regs::rax());
1935
- collector.reg_fixed_use(dividend_hi.to_reg(), regs::rdx());
1936
- collector.reg_fixed_def(dst_quotient.to_writable_reg(), regs::rax());
1937
- collector.reg_fixed_def(dst_remainder.to_writable_reg(), regs::rdx());
1938
- }
1939
- Inst::Div8 { dividend, dst, .. } | Inst::CheckedSRemSeq8 { dividend, dst, .. } => {
1940
- match inst {
1941
- Inst::Div8 { divisor, .. } => divisor.get_operands(collector),
1942
- Inst::CheckedSRemSeq8 { divisor, .. } => collector.reg_use(divisor.to_reg()),
1943
- _ => {}
1944
- }
1945
- collector.reg_fixed_use(dividend.to_reg(), regs::rax());
1946
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
1947
- }
1948
- Inst::MulHi {
1949
- src1,
1950
- src2,
1951
- dst_lo,
1952
- dst_hi,
1953
- ..
1954
- } => {
1955
- collector.reg_fixed_use(src1.to_reg(), regs::rax());
1956
- collector.reg_fixed_def(dst_lo.to_writable_reg(), regs::rax());
1957
- collector.reg_fixed_def(dst_hi.to_writable_reg(), regs::rdx());
1958
- src2.get_operands(collector);
1959
- }
1960
- Inst::UMulLo {
1961
- size,
1962
- src1,
1963
- src2,
1964
- dst,
1965
- ..
1966
- } => {
1967
- collector.reg_fixed_use(src1.to_reg(), regs::rax());
1968
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
1969
- if *size != OperandSize::Size8 {
1970
- collector.reg_clobbers(PRegSet::empty().with(regs::gpr_preg(regs::ENC_RDX)));
1971
- }
1972
- src2.get_operands(collector);
1973
- }
1974
- Inst::SignExtendData { size, src, dst } => {
1975
- match size {
1976
- OperandSize::Size8 => {
1977
- // Note `rax` on both src and dest: 8->16 extend
1978
- // does AL -> AX.
1979
- collector.reg_fixed_use(src.to_reg(), regs::rax());
1980
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
1981
- }
1982
- _ => {
1983
- // All other widths do RAX -> RDX (AX -> DX:AX,
1984
- // EAX -> EDX:EAX).
1985
- collector.reg_fixed_use(src.to_reg(), regs::rax());
1986
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rdx());
1987
- }
1988
- }
1989
- }
1990
- Inst::UnaryRmR { src, dst, .. } => {
1991
- collector.reg_def(dst.to_writable_reg());
1992
- src.get_operands(collector);
1993
- }
1994
- Inst::XmmUnaryRmR { src, dst, .. } | Inst::XmmUnaryRmRImm { src, dst, .. } => {
1995
- collector.reg_def(dst.to_writable_reg());
1996
- src.get_operands(collector);
1997
- }
1998
- Inst::XmmUnaryRmREvex { src, dst, .. }
1999
- | Inst::XmmUnaryRmRUnaligned { src, dst, .. }
2000
- | Inst::XmmUnaryRmRVex { src, dst, .. }
2001
- | Inst::XmmUnaryRmRImmVex { src, dst, .. } => {
2002
- collector.reg_def(dst.to_writable_reg());
2003
- src.get_operands(collector);
2004
- }
2005
- Inst::XmmRmR {
2006
- src1, src2, dst, ..
2007
- } => {
2008
- collector.reg_use(src1.to_reg());
2009
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2010
- src2.get_operands(collector);
2011
- }
2012
- Inst::XmmRmRUnaligned {
2013
- src1, src2, dst, ..
2014
- } => {
2015
- collector.reg_use(src1.to_reg());
2016
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2017
- src2.get_operands(collector);
2018
- }
2019
- Inst::XmmRmRBlend {
2020
- src1,
2021
- src2,
2022
- mask,
2023
- dst,
2024
- op,
2025
- } => {
2026
- assert!(
2027
- *op == SseOpcode::Blendvpd
2028
- || *op == SseOpcode::Blendvps
2029
- || *op == SseOpcode::Pblendvb
2030
- );
2031
- collector.reg_use(src1.to_reg());
2032
- collector.reg_fixed_use(mask.to_reg(), regs::xmm0());
2033
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2034
- src2.get_operands(collector);
2035
- }
2036
- Inst::XmmRmiRVex {
2037
- src1, src2, dst, ..
2038
- } => {
2039
- collector.reg_def(dst.to_writable_reg());
2040
- collector.reg_use(src1.to_reg());
2041
- src2.get_operands(collector);
2042
- }
2043
- Inst::XmmRmRImmVex {
2044
- src1, src2, dst, ..
2045
- } => {
2046
- collector.reg_def(dst.to_writable_reg());
2047
- collector.reg_use(src1.to_reg());
2048
- src2.get_operands(collector);
2049
- }
2050
- Inst::XmmVexPinsr {
2051
- src1, src2, dst, ..
2052
- } => {
2053
- collector.reg_def(dst.to_writable_reg());
2054
- collector.reg_use(src1.to_reg());
2055
- src2.get_operands(collector);
2056
- }
2057
- Inst::XmmRmRVex3 {
2058
- src1,
2059
- src2,
2060
- src3,
2061
- dst,
2062
- ..
2063
- } => {
2064
- collector.reg_use(src1.to_reg());
2065
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2066
- collector.reg_use(src2.to_reg());
2067
- src3.get_operands(collector);
2068
- }
2069
- Inst::XmmRmRBlendVex {
2070
- src1,
2071
- src2,
2072
- mask,
2073
- dst,
2074
- ..
2075
- } => {
2076
- collector.reg_def(dst.to_writable_reg());
2077
- collector.reg_use(src1.to_reg());
2078
- src2.get_operands(collector);
2079
- collector.reg_use(mask.to_reg());
2080
- }
2081
- Inst::XmmRmREvex {
2082
- op,
2083
- src1,
2084
- src2,
2085
- dst,
2086
- ..
2087
- } => {
2088
- assert_ne!(*op, Avx512Opcode::Vpermi2b);
2089
- collector.reg_def(dst.to_writable_reg());
2090
- collector.reg_use(src2.to_reg());
2091
- src1.get_operands(collector);
2092
- }
2093
- Inst::XmmRmREvex3 {
2094
- op,
2095
- src1,
2096
- src2,
2097
- src3,
2098
- dst,
2099
- ..
2100
- } => {
2101
- assert_eq!(*op, Avx512Opcode::Vpermi2b);
2102
- collector.reg_reuse_def(dst.to_writable_reg(), 2); // Reuse `src3`.
2103
- collector.reg_use(src2.to_reg());
2104
- collector.reg_use(src3.to_reg());
2105
- src1.get_operands(collector);
2106
- }
2107
- Inst::XmmRmRImm {
2108
- src1, src2, dst, ..
2109
- } => {
2110
- collector.reg_use(*src1);
2111
- collector.reg_reuse_def(*dst, 0);
2112
- src2.get_operands(collector);
2113
- }
2114
- Inst::XmmUninitializedValue { dst } => collector.reg_def(dst.to_writable_reg()),
2115
- Inst::XmmMinMaxSeq { lhs, rhs, dst, .. } => {
2116
- collector.reg_use(rhs.to_reg());
2117
- collector.reg_use(lhs.to_reg());
2118
- collector.reg_reuse_def(dst.to_writable_reg(), 0); // Reuse RHS.
2119
- }
2120
- Inst::XmmRmiReg {
2121
- src1, src2, dst, ..
2122
- } => {
2123
- collector.reg_use(src1.to_reg());
2124
- collector.reg_reuse_def(dst.to_writable_reg(), 0); // Reuse RHS.
2125
- src2.get_operands(collector);
2126
- }
2127
- Inst::XmmMovRM { src, dst, .. }
2128
- | Inst::XmmMovRMVex { src, dst, .. }
2129
- | Inst::XmmMovRMImm { src, dst, .. }
2130
- | Inst::XmmMovRMImmVex { src, dst, .. } => {
2131
- collector.reg_use(src.to_reg());
2132
- dst.get_operands(collector);
2133
- }
2134
- Inst::XmmCmpRmR { src, dst, .. } => {
2135
- collector.reg_use(dst.to_reg());
2136
- src.get_operands(collector);
2137
- }
2138
- Inst::Imm { dst, .. } => {
2139
- collector.reg_def(dst.to_writable_reg());
2140
- }
2141
- Inst::MovRR { src, dst, .. } => {
2142
- collector.reg_use(src.to_reg());
2143
- collector.reg_def(dst.to_writable_reg());
2144
- }
2145
- Inst::MovFromPReg { dst, src } => {
2146
- debug_assert!(dst.to_reg().to_reg().is_virtual());
2147
- collector.reg_fixed_nonallocatable(*src);
2148
- collector.reg_def(dst.to_writable_reg());
2149
- }
2150
- Inst::MovToPReg { dst, src } => {
2151
- debug_assert!(src.to_reg().is_virtual());
2152
- collector.reg_use(src.to_reg());
2153
- collector.reg_fixed_nonallocatable(*dst);
2154
- }
2155
- Inst::XmmToGpr { src, dst, .. }
2156
- | Inst::XmmToGprVex { src, dst, .. }
2157
- | Inst::XmmToGprImm { src, dst, .. }
2158
- | Inst::XmmToGprImmVex { src, dst, .. } => {
2159
- collector.reg_use(src.to_reg());
2160
- collector.reg_def(dst.to_writable_reg());
2161
- }
2162
- Inst::GprToXmm { src, dst, .. } | Inst::GprToXmmVex { src, dst, .. } => {
2163
- collector.reg_def(dst.to_writable_reg());
2164
- src.get_operands(collector);
2165
- }
2166
- Inst::CvtUint64ToFloatSeq {
2167
- src,
2168
- dst,
2169
- tmp_gpr1,
2170
- tmp_gpr2,
2171
- ..
2172
- } => {
2173
- collector.reg_use(src.to_reg());
2174
- collector.reg_early_def(dst.to_writable_reg());
2175
- collector.reg_early_def(tmp_gpr1.to_writable_reg());
2176
- collector.reg_early_def(tmp_gpr2.to_writable_reg());
2177
- }
2178
- Inst::CvtFloatToSintSeq {
2179
- src,
2180
- dst,
2181
- tmp_xmm,
2182
- tmp_gpr,
2183
- ..
2184
- } => {
2185
- collector.reg_use(src.to_reg());
2186
- collector.reg_early_def(dst.to_writable_reg());
2187
- collector.reg_early_def(tmp_gpr.to_writable_reg());
2188
- collector.reg_early_def(tmp_xmm.to_writable_reg());
2189
- }
2190
- Inst::CvtFloatToUintSeq {
2191
- src,
2192
- dst,
2193
- tmp_gpr,
2194
- tmp_xmm,
2195
- tmp_xmm2,
2196
- ..
2197
- } => {
2198
- collector.reg_use(src.to_reg());
2199
- collector.reg_early_def(dst.to_writable_reg());
2200
- collector.reg_early_def(tmp_gpr.to_writable_reg());
2201
- collector.reg_early_def(tmp_xmm.to_writable_reg());
2202
- collector.reg_early_def(tmp_xmm2.to_writable_reg());
2203
- }
2204
-
2205
- Inst::MovImmM { dst, .. } => {
2206
- dst.get_operands(collector);
2207
- }
2208
-
2209
- Inst::MovzxRmR { src, dst, .. } => {
2210
- collector.reg_def(dst.to_writable_reg());
2211
- src.get_operands(collector);
2212
- }
2213
- Inst::Mov64MR { src, dst, .. } => {
2214
- collector.reg_def(dst.to_writable_reg());
2215
- src.get_operands(collector);
2216
- }
2217
- Inst::LoadEffectiveAddress { addr: src, dst } => {
2218
- collector.reg_def(dst.to_writable_reg());
2219
- src.get_operands(collector);
2220
- }
2221
- Inst::MovsxRmR { src, dst, .. } => {
2222
- collector.reg_def(dst.to_writable_reg());
2223
- src.get_operands(collector);
2224
- }
2225
- Inst::MovRM { src, dst, .. } => {
2226
- collector.reg_use(src.to_reg());
2227
- dst.get_operands(collector);
2228
- }
2229
- Inst::ShiftR {
2230
- num_bits, src, dst, ..
2231
- } => {
2232
- collector.reg_use(src.to_reg());
2233
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2234
- if let Imm8Reg::Reg { reg } = num_bits.clone().to_imm8_reg() {
2235
- collector.reg_fixed_use(reg, regs::rcx());
2236
- }
2237
- }
2238
- Inst::CmpRmiR { src, dst, .. } => {
2239
- // N.B.: use, not def (cmp doesn't write its result).
2240
- collector.reg_use(dst.to_reg());
2241
- src.get_operands(collector);
2242
- }
2243
- Inst::Setcc { dst, .. } => {
2244
- collector.reg_def(dst.to_writable_reg());
2245
- }
2246
- Inst::Bswap { src, dst, .. } => {
2247
- collector.reg_use(src.to_reg());
2248
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2249
- }
2250
- Inst::Cmove {
2251
- consequent,
2252
- alternative,
2253
- dst,
2254
- ..
2255
- } => {
2256
- collector.reg_use(alternative.to_reg());
2257
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2258
- consequent.get_operands(collector);
2259
- }
2260
- Inst::XmmCmove {
2261
- consequent,
2262
- alternative,
2263
- dst,
2264
- ..
2265
- } => {
2266
- collector.reg_use(alternative.to_reg());
2267
- collector.reg_reuse_def(dst.to_writable_reg(), 0);
2268
- consequent.get_operands(collector);
2269
- }
2270
- Inst::Push64 { src } => {
2271
- src.get_operands(collector);
2272
- }
2273
- Inst::Pop64 { dst } => {
2274
- collector.reg_def(dst.to_writable_reg());
2275
- }
2276
- Inst::StackProbeLoop { tmp, .. } => {
2277
- collector.reg_early_def(*tmp);
2278
- }
2279
-
2280
- Inst::CallKnown { dest, ref info, .. } => {
2281
- // Probestack is special and is only inserted after
2282
- // regalloc, so we do not need to represent its ABI to the
2283
- // register allocator. Assert that we don't alter that
2284
- // arrangement.
2285
- debug_assert_ne!(*dest, ExternalName::LibCall(LibCall::Probestack));
2286
- for u in &info.uses {
2287
- collector.reg_fixed_use(u.vreg, u.preg);
2288
- }
2289
- for d in &info.defs {
2290
- collector.reg_fixed_def(d.vreg, d.preg);
2291
- }
2292
- collector.reg_clobbers(info.clobbers);
2293
- }
2294
-
2295
- Inst::CallUnknown { ref info, dest, .. } => {
2296
- dest.get_operands(collector);
2297
- for u in &info.uses {
2298
- collector.reg_fixed_use(u.vreg, u.preg);
2299
- }
2300
- for d in &info.defs {
2301
- collector.reg_fixed_def(d.vreg, d.preg);
2302
- }
2303
- collector.reg_clobbers(info.clobbers);
2304
- }
2305
-
2306
- Inst::JmpTableSeq {
2307
- ref idx,
2308
- ref tmp1,
2309
- ref tmp2,
2310
- ..
2311
- } => {
2312
- collector.reg_use(*idx);
2313
- collector.reg_early_def(*tmp1);
2314
- // In the sequence emitted for this pseudoinstruction in emit.rs,
2315
- // tmp2 is only written after idx is read, so it doesn't need to be
2316
- // an early def.
2317
- collector.reg_def(*tmp2);
2318
- }
2319
-
2320
- Inst::JmpUnknown { target } => {
2321
- target.get_operands(collector);
2322
- }
2323
-
2324
- Inst::LoadExtName { dst, .. } => {
2325
- collector.reg_def(*dst);
2326
- }
2327
-
2328
- Inst::LockCmpxchg {
2329
- replacement,
2330
- expected,
2331
- mem,
2332
- dst_old,
2333
- ..
2334
- } => {
2335
- collector.reg_use(*replacement);
2336
- collector.reg_fixed_use(*expected, regs::rax());
2337
- collector.reg_fixed_def(*dst_old, regs::rax());
2338
- mem.get_operands(collector);
2339
- }
2340
-
2341
- Inst::AtomicRmwSeq {
2342
- operand,
2343
- temp,
2344
- dst_old,
2345
- mem,
2346
- ..
2347
- } => {
2348
- collector.reg_late_use(*operand);
2349
- collector.reg_early_def(*temp);
2350
- // This `fixed_def` is needed because `CMPXCHG` always uses this
2351
- // register implicitly.
2352
- collector.reg_fixed_def(*dst_old, regs::rax());
2353
- mem.get_operands_late(collector)
2354
- }
2355
-
2356
- Inst::Args { args } => {
2357
- for arg in args {
2358
- collector.reg_fixed_def(arg.vreg, arg.preg);
2359
- }
2360
- }
2361
-
2362
- Inst::Ret { rets } => {
2363
- // The return value(s) are live-out; we represent this
2364
- // with register uses on the return instruction.
2365
- for ret in rets.iter() {
2366
- collector.reg_fixed_use(ret.vreg, ret.preg);
2367
- }
2368
- }
2369
-
2370
- Inst::JmpKnown { .. }
2371
- | Inst::JmpIf { .. }
2372
- | Inst::JmpCond { .. }
2373
- | Inst::Nop { .. }
2374
- | Inst::TrapIf { .. }
2375
- | Inst::TrapIfAnd { .. }
2376
- | Inst::TrapIfOr { .. }
2377
- | Inst::VirtualSPOffsetAdj { .. }
2378
- | Inst::Hlt
2379
- | Inst::Ud2 { .. }
2380
- | Inst::Fence { .. } => {
2381
- // No registers are used.
2382
- }
2383
-
2384
- Inst::ElfTlsGetAddr { dst, .. } | Inst::MachOTlsGetAddr { dst, .. } => {
2385
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
2386
- // All caller-saves are clobbered.
2387
- //
2388
- // We use the SysV calling convention here because the
2389
- // pseudoinstruction (and relocation that it emits) is specific to
2390
- // ELF systems; other x86-64 targets with other conventions (i.e.,
2391
- // Windows) use different TLS strategies.
2392
- let mut clobbers = X64ABIMachineSpec::get_regs_clobbered_by_call(CallConv::SystemV);
2393
- clobbers.remove(regs::gpr_preg(regs::ENC_RAX));
2394
- collector.reg_clobbers(clobbers);
2395
- }
2396
-
2397
- Inst::CoffTlsGetAddr { dst, tmp, .. } => {
2398
- // We also use the gs register. But that register is not allocatable by the
2399
- // register allocator, so we don't need to mark it as used here.
2400
-
2401
- // We use %rax to set the address
2402
- collector.reg_fixed_def(dst.to_writable_reg(), regs::rax());
2403
-
2404
- // We use %rcx as a temporary variable to load the _tls_index
2405
- collector.reg_fixed_def(tmp.to_writable_reg(), regs::rcx());
2406
- }
2407
-
2408
- Inst::Unwind { .. } => {}
2409
-
2410
- Inst::DummyUse { reg } => {
2411
- collector.reg_use(*reg);
2412
- }
2413
- }
2414
- }
2415
-
2416
- //=============================================================================
2417
- // Instructions: misc functions and external interface
2418
-
2419
- impl MachInst for Inst {
2420
- type ABIMachineSpec = X64ABIMachineSpec;
2421
-
2422
- fn get_operands<F: Fn(VReg) -> VReg>(&self, collector: &mut OperandCollector<'_, F>) {
2423
- x64_get_operands(&self, collector)
2424
- }
2425
-
2426
- fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
2427
- match self {
2428
- // Note (carefully!) that a 32-bit mov *isn't* a no-op since it zeroes
2429
- // out the upper 32 bits of the destination. For example, we could
2430
- // conceivably use `movl %reg, %reg` to zero out the top 32 bits of
2431
- // %reg.
2432
- Self::MovRR { size, src, dst, .. } if *size == OperandSize::Size64 => {
2433
- Some((dst.to_writable_reg(), src.to_reg()))
2434
- }
2435
- // Note as well that MOVS[S|D] when used in the `XmmUnaryRmR` context are pure moves of
2436
- // scalar floating-point values (and annotate `dst` as `def`s to the register allocator)
2437
- // whereas the same operation in a packed context, e.g. `XMM_RM_R`, is used to merge a
2438
- // value into the lowest lane of a vector (not a move).
2439
- Self::XmmUnaryRmR { op, src, dst, .. }
2440
- if *op == SseOpcode::Movss
2441
- || *op == SseOpcode::Movsd
2442
- || *op == SseOpcode::Movaps
2443
- || *op == SseOpcode::Movapd
2444
- || *op == SseOpcode::Movups
2445
- || *op == SseOpcode::Movupd
2446
- || *op == SseOpcode::Movdqa
2447
- || *op == SseOpcode::Movdqu =>
2448
- {
2449
- if let RegMem::Reg { reg } = src.clone().to_reg_mem() {
2450
- Some((dst.to_writable_reg(), reg))
2451
- } else {
2452
- None
2453
- }
2454
- }
2455
- _ => None,
2456
- }
2457
- }
2458
-
2459
- fn is_included_in_clobbers(&self) -> bool {
2460
- match self {
2461
- &Inst::Args { .. } => false,
2462
- _ => true,
2463
- }
2464
- }
2465
-
2466
- fn is_trap(&self) -> bool {
2467
- match self {
2468
- Self::Ud2 { .. } => true,
2469
- _ => false,
2470
- }
2471
- }
2472
-
2473
- fn is_args(&self) -> bool {
2474
- match self {
2475
- Self::Args { .. } => true,
2476
- _ => false,
2477
- }
2478
- }
2479
-
2480
- fn is_term(&self) -> MachTerminator {
2481
- match self {
2482
- // Interesting cases.
2483
- &Self::Ret { .. } => MachTerminator::Ret,
2484
- &Self::JmpKnown { .. } => MachTerminator::Uncond,
2485
- &Self::JmpCond { .. } => MachTerminator::Cond,
2486
- &Self::JmpTableSeq { .. } => MachTerminator::Indirect,
2487
- // All other cases are boring.
2488
- _ => MachTerminator::None,
2489
- }
2490
- }
2491
-
2492
- fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, ty: Type) -> Inst {
2493
- trace!(
2494
- "Inst::gen_move {:?} -> {:?} (type: {:?})",
2495
- src_reg,
2496
- dst_reg.to_reg(),
2497
- ty
2498
- );
2499
- let rc_dst = dst_reg.to_reg().class();
2500
- let rc_src = src_reg.class();
2501
- // If this isn't true, we have gone way off the rails.
2502
- debug_assert!(rc_dst == rc_src);
2503
- match rc_dst {
2504
- RegClass::Int => Inst::mov_r_r(OperandSize::Size64, src_reg, dst_reg),
2505
- RegClass::Float => {
2506
- // The Intel optimization manual, in "3.5.1.13 Zero-Latency MOV Instructions",
2507
- // doesn't include MOVSS/MOVSD as instructions with zero-latency. Use movaps for
2508
- // those, which may write more lanes that we need, but are specified to have
2509
- // zero-latency.
2510
- let opcode = match ty {
2511
- types::F32 | types::F64 | types::F32X4 => SseOpcode::Movaps,
2512
- types::F64X2 => SseOpcode::Movapd,
2513
- _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqa,
2514
- _ => unimplemented!("unable to move type: {}", ty),
2515
- };
2516
- Inst::xmm_unary_rm_r(opcode, RegMem::reg(src_reg), dst_reg)
2517
- }
2518
- RegClass::Vector => unreachable!(),
2519
- }
2520
- }
2521
-
2522
- fn gen_nop(preferred_size: usize) -> Inst {
2523
- Inst::nop(std::cmp::min(preferred_size, 15) as u8)
2524
- }
2525
-
2526
- fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
2527
- match ty {
2528
- types::I8 => Ok((&[RegClass::Int], &[types::I8])),
2529
- types::I16 => Ok((&[RegClass::Int], &[types::I16])),
2530
- types::I32 => Ok((&[RegClass::Int], &[types::I32])),
2531
- types::I64 => Ok((&[RegClass::Int], &[types::I64])),
2532
- types::R32 => panic!("32-bit reftype pointer should never be seen on x86-64"),
2533
- types::R64 => Ok((&[RegClass::Int], &[types::R64])),
2534
- types::F32 => Ok((&[RegClass::Float], &[types::F32])),
2535
- types::F64 => Ok((&[RegClass::Float], &[types::F64])),
2536
- types::I128 => Ok((&[RegClass::Int, RegClass::Int], &[types::I64, types::I64])),
2537
- _ if ty.is_vector() => {
2538
- assert!(ty.bits() <= 128);
2539
- Ok((&[RegClass::Float], &[types::I8X16]))
2540
- }
2541
- _ => Err(CodegenError::Unsupported(format!(
2542
- "Unexpected SSA-value type: {}",
2543
- ty
2544
- ))),
2545
- }
2546
- }
2547
-
2548
- fn canonical_type_for_rc(rc: RegClass) -> Type {
2549
- match rc {
2550
- RegClass::Float => types::I8X16,
2551
- RegClass::Int => types::I64,
2552
- RegClass::Vector => unreachable!(),
2553
- }
2554
- }
2555
-
2556
- fn gen_jump(label: MachLabel) -> Inst {
2557
- Inst::jmp_known(label)
2558
- }
2559
-
2560
- fn gen_dummy_use(reg: Reg) -> Self {
2561
- Inst::DummyUse { reg }
2562
- }
2563
-
2564
- fn worst_case_size() -> CodeOffset {
2565
- 15
2566
- }
2567
-
2568
- fn ref_type_regclass(_: &settings::Flags) -> RegClass {
2569
- RegClass::Int
2570
- }
2571
-
2572
- fn is_safepoint(&self) -> bool {
2573
- match self {
2574
- Inst::CallKnown { .. }
2575
- | Inst::CallUnknown { .. }
2576
- | Inst::TrapIf { .. }
2577
- | Inst::Ud2 { .. } => true,
2578
- _ => false,
2579
- }
2580
- }
2581
-
2582
- fn function_alignment() -> FunctionAlignment {
2583
- FunctionAlignment {
2584
- minimum: 1,
2585
- // Prefer an alignment of 16-bytes to hypothetically get the whole
2586
- // function into a minimum number of lines.
2587
- preferred: 16,
2588
- }
2589
- }
2590
-
2591
- type LabelUse = LabelUse;
2592
-
2593
- const TRAP_OPCODE: &'static [u8] = &[0x0f, 0x0b];
2594
- }
2595
-
2596
- /// State carried between emissions of a sequence of instructions.
2597
- #[derive(Default, Clone, Debug)]
2598
- pub struct EmitState {
2599
- /// Addend to convert nominal-SP offsets to real-SP offsets at the current
2600
- /// program point.
2601
- pub(crate) virtual_sp_offset: i64,
2602
- /// Offset of FP from nominal-SP.
2603
- pub(crate) nominal_sp_to_fp: i64,
2604
- /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
2605
- stack_map: Option<StackMap>,
2606
- /// Current source location.
2607
- cur_srcloc: RelSourceLoc,
2608
- /// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
2609
- /// optimized away at compiletime. See [cranelift_control].
2610
- ctrl_plane: ControlPlane,
2611
- }
2612
-
2613
- /// Constant state used during emissions of a sequence of instructions.
2614
- pub struct EmitInfo {
2615
- pub(super) flags: settings::Flags,
2616
- isa_flags: x64_settings::Flags,
2617
- }
2618
-
2619
- impl EmitInfo {
2620
- /// Create a constant state for emission of instructions.
2621
- pub fn new(flags: settings::Flags, isa_flags: x64_settings::Flags) -> Self {
2622
- Self { flags, isa_flags }
2623
- }
2624
- }
2625
-
2626
- impl MachInstEmit for Inst {
2627
- type State = EmitState;
2628
- type Info = EmitInfo;
2629
-
2630
- fn emit(
2631
- &self,
2632
- allocs: &[Allocation],
2633
- sink: &mut MachBuffer<Inst>,
2634
- info: &Self::Info,
2635
- state: &mut Self::State,
2636
- ) {
2637
- let mut allocs = AllocationConsumer::new(allocs);
2638
- emit::emit(self, &mut allocs, sink, info, state);
2639
- }
2640
-
2641
- fn pretty_print_inst(&self, allocs: &[Allocation], _: &mut Self::State) -> String {
2642
- PrettyPrint::pretty_print(self, 0, &mut AllocationConsumer::new(allocs))
2643
- }
2644
- }
2645
-
2646
- impl MachInstEmitState<Inst> for EmitState {
2647
- fn new(abi: &Callee<X64ABIMachineSpec>, ctrl_plane: ControlPlane) -> Self {
2648
- EmitState {
2649
- virtual_sp_offset: 0,
2650
- nominal_sp_to_fp: abi.frame_size() as i64,
2651
- stack_map: None,
2652
- cur_srcloc: Default::default(),
2653
- ctrl_plane,
2654
- }
2655
- }
2656
-
2657
- fn pre_safepoint(&mut self, stack_map: StackMap) {
2658
- self.stack_map = Some(stack_map);
2659
- }
2660
-
2661
- fn pre_sourceloc(&mut self, srcloc: RelSourceLoc) {
2662
- self.cur_srcloc = srcloc;
2663
- }
2664
-
2665
- fn ctrl_plane_mut(&mut self) -> &mut ControlPlane {
2666
- &mut self.ctrl_plane
2667
- }
2668
-
2669
- fn take_ctrl_plane(self) -> ControlPlane {
2670
- self.ctrl_plane
2671
- }
2672
- }
2673
-
2674
- impl EmitState {
2675
- fn take_stack_map(&mut self) -> Option<StackMap> {
2676
- self.stack_map.take()
2677
- }
2678
-
2679
- fn clear_post_insn(&mut self) {
2680
- self.stack_map = None;
2681
- }
2682
- }
2683
-
2684
- /// A label-use (internal relocation) in generated code.
2685
- #[derive(Clone, Copy, Debug, PartialEq, Eq)]
2686
- pub enum LabelUse {
2687
- /// A 32-bit offset from location of relocation itself, added to the existing value at that
2688
- /// location. Used for control flow instructions which consider an offset from the start of the
2689
- /// next instruction (so the size of the payload -- 4 bytes -- is subtracted from the payload).
2690
- JmpRel32,
2691
-
2692
- /// A 32-bit offset from location of relocation itself, added to the existing value at that
2693
- /// location.
2694
- PCRel32,
2695
- }
2696
-
2697
- impl MachInstLabelUse for LabelUse {
2698
- const ALIGN: CodeOffset = 1;
2699
-
2700
- fn max_pos_range(self) -> CodeOffset {
2701
- match self {
2702
- LabelUse::JmpRel32 | LabelUse::PCRel32 => 0x7fff_ffff,
2703
- }
2704
- }
2705
-
2706
- fn max_neg_range(self) -> CodeOffset {
2707
- match self {
2708
- LabelUse::JmpRel32 | LabelUse::PCRel32 => 0x8000_0000,
2709
- }
2710
- }
2711
-
2712
- fn patch_size(self) -> CodeOffset {
2713
- match self {
2714
- LabelUse::JmpRel32 | LabelUse::PCRel32 => 4,
2715
- }
2716
- }
2717
-
2718
- fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
2719
- let pc_rel = (label_offset as i64) - (use_offset as i64);
2720
- debug_assert!(pc_rel <= self.max_pos_range() as i64);
2721
- debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
2722
- let pc_rel = pc_rel as u32;
2723
- match self {
2724
- LabelUse::JmpRel32 => {
2725
- let addend = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
2726
- let value = pc_rel.wrapping_add(addend).wrapping_sub(4);
2727
- buffer.copy_from_slice(&value.to_le_bytes()[..]);
2728
- }
2729
- LabelUse::PCRel32 => {
2730
- let addend = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
2731
- let value = pc_rel.wrapping_add(addend);
2732
- buffer.copy_from_slice(&value.to_le_bytes()[..]);
2733
- }
2734
- }
2735
- }
2736
-
2737
- fn supports_veneer(self) -> bool {
2738
- match self {
2739
- LabelUse::JmpRel32 | LabelUse::PCRel32 => false,
2740
- }
2741
- }
2742
-
2743
- fn veneer_size(self) -> CodeOffset {
2744
- match self {
2745
- LabelUse::JmpRel32 | LabelUse::PCRel32 => 0,
2746
- }
2747
- }
2748
-
2749
- fn generate_veneer(self, _: &mut [u8], _: CodeOffset) -> (CodeOffset, LabelUse) {
2750
- match self {
2751
- LabelUse::JmpRel32 | LabelUse::PCRel32 => {
2752
- panic!("Veneer not supported for JumpRel32 label-use.");
2753
- }
2754
- }
2755
- }
2756
-
2757
- fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
2758
- match (reloc, addend) {
2759
- (Reloc::X86CallPCRel4, -4) => Some(LabelUse::JmpRel32),
2760
- _ => None,
2761
- }
2762
- }
2763
- }