wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,2914 +0,0 @@
1
- //! Riscv64 ISA: binary code emission.
2
-
3
- use crate::binemit::StackMap;
4
- use crate::ir::RelSourceLoc;
5
- use crate::ir::TrapCode;
6
- use crate::isa::riscv64::inst::*;
7
- use crate::isa::riscv64::inst::{zero_reg, AluOPRRR};
8
- use crate::isa::riscv64::lower::isle::generated_code::VecOpMasking;
9
- use crate::machinst::{AllocationConsumer, Reg, Writable};
10
- use cranelift_control::ControlPlane;
11
- use regalloc2::Allocation;
12
-
13
- pub struct EmitInfo {
14
- shared_flag: settings::Flags,
15
- isa_flags: super::super::riscv_settings::Flags,
16
- }
17
-
18
- impl EmitInfo {
19
- pub(crate) fn new(
20
- shared_flag: settings::Flags,
21
- isa_flags: super::super::riscv_settings::Flags,
22
- ) -> Self {
23
- Self {
24
- shared_flag,
25
- isa_flags,
26
- }
27
- }
28
- }
29
-
30
- /// load constant by put the constant in the code stream.
31
- /// calculate the pc and using load instruction.
32
- /// This is only allow used in the emit stage.
33
- /// Because of those instruction must execute together.
34
- /// see https://github.com/bytecodealliance/wasmtime/pull/5612
35
- #[derive(Clone, Copy)]
36
- pub(crate) enum LoadConstant {
37
- U32(u32),
38
- U64(u64),
39
- }
40
-
41
- impl LoadConstant {
42
- fn to_le_bytes(self) -> Vec<u8> {
43
- match self {
44
- LoadConstant::U32(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
45
- LoadConstant::U64(x) => Vec::from_iter(x.to_le_bytes().into_iter()),
46
- }
47
- }
48
- fn load_op(self) -> LoadOP {
49
- match self {
50
- LoadConstant::U32(_) => LoadOP::Lwu,
51
- LoadConstant::U64(_) => LoadOP::Ld,
52
- }
53
- }
54
- fn load_ty(self) -> Type {
55
- match self {
56
- LoadConstant::U32(_) => R32,
57
- LoadConstant::U64(_) => R64,
58
- }
59
- }
60
-
61
- pub(crate) fn load_constant<F: FnMut(Type) -> Writable<Reg>>(
62
- self,
63
- rd: Writable<Reg>,
64
- alloc_tmp: &mut F,
65
- ) -> SmallInstVec<Inst> {
66
- let mut insts = SmallInstVec::new();
67
- // get current pc.
68
- let pc = alloc_tmp(I64);
69
- insts.push(Inst::Auipc {
70
- rd: pc,
71
- imm: Imm20 { bits: 0 },
72
- });
73
- // load
74
- insts.push(Inst::Load {
75
- rd,
76
- op: self.load_op(),
77
- flags: MemFlags::new(),
78
- from: AMode::RegOffset(pc.to_reg(), 12, self.load_ty()),
79
- });
80
- let data = self.to_le_bytes();
81
- // jump over.
82
- insts.push(Inst::Jal {
83
- dest: BranchTarget::ResolvedOffset(Inst::INSTRUCTION_SIZE + data.len() as i32),
84
- });
85
- insts.push(Inst::RawData { data });
86
- insts
87
- }
88
-
89
- // load and perform an extra add.
90
- pub(crate) fn load_constant_and_add(self, rd: Writable<Reg>, rs: Reg) -> SmallInstVec<Inst> {
91
- let mut insts = self.load_constant(rd, &mut |_| rd);
92
- insts.push(Inst::AluRRR {
93
- alu_op: AluOPRRR::Add,
94
- rd,
95
- rs1: rd.to_reg(),
96
- rs2: rs,
97
- });
98
- insts
99
- }
100
- }
101
-
102
- pub(crate) fn reg_to_gpr_num(m: Reg) -> u32 {
103
- u32::try_from(m.to_real_reg().unwrap().hw_enc() & 31).unwrap()
104
- }
105
-
106
- #[derive(Clone, Debug, PartialEq, Default)]
107
- pub enum EmitVState {
108
- #[default]
109
- Unknown,
110
- Known(VState),
111
- }
112
-
113
- /// State carried between emissions of a sequence of instructions.
114
- #[derive(Default, Clone, Debug)]
115
- pub struct EmitState {
116
- pub(crate) virtual_sp_offset: i64,
117
- pub(crate) nominal_sp_to_fp: i64,
118
- /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
119
- stack_map: Option<StackMap>,
120
- /// Current source-code location corresponding to instruction to be emitted.
121
- cur_srcloc: RelSourceLoc,
122
- /// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
123
- /// optimized away at compiletime. See [cranelift_control].
124
- ctrl_plane: ControlPlane,
125
- /// Vector State
126
- /// Controls the current state of the vector unit at the emission point.
127
- vstate: EmitVState,
128
- }
129
-
130
- impl EmitState {
131
- fn take_stack_map(&mut self) -> Option<StackMap> {
132
- self.stack_map.take()
133
- }
134
-
135
- fn clear_post_insn(&mut self) {
136
- self.stack_map = None;
137
- }
138
-
139
- fn cur_srcloc(&self) -> RelSourceLoc {
140
- self.cur_srcloc
141
- }
142
- }
143
-
144
- impl MachInstEmitState<Inst> for EmitState {
145
- fn new(
146
- abi: &Callee<crate::isa::riscv64::abi::Riscv64MachineDeps>,
147
- ctrl_plane: ControlPlane,
148
- ) -> Self {
149
- EmitState {
150
- virtual_sp_offset: 0,
151
- nominal_sp_to_fp: abi.frame_size() as i64,
152
- stack_map: None,
153
- cur_srcloc: RelSourceLoc::default(),
154
- ctrl_plane,
155
- vstate: EmitVState::Unknown,
156
- }
157
- }
158
-
159
- fn pre_safepoint(&mut self, stack_map: StackMap) {
160
- self.stack_map = Some(stack_map);
161
- }
162
-
163
- fn pre_sourceloc(&mut self, srcloc: RelSourceLoc) {
164
- self.cur_srcloc = srcloc;
165
- }
166
-
167
- fn ctrl_plane_mut(&mut self) -> &mut ControlPlane {
168
- &mut self.ctrl_plane
169
- }
170
-
171
- fn take_ctrl_plane(self) -> ControlPlane {
172
- self.ctrl_plane
173
- }
174
-
175
- fn on_new_block(&mut self) {
176
- // Reset the vector state.
177
- self.vstate = EmitVState::Unknown;
178
- }
179
- }
180
-
181
- impl Inst {
182
- /// construct a "imm - rs".
183
- pub(crate) fn construct_imm_sub_rs(rd: Writable<Reg>, imm: u64, rs: Reg) -> SmallInstVec<Inst> {
184
- let mut insts = Inst::load_constant_u64(rd, imm, &mut |_| rd);
185
- insts.push(Inst::AluRRR {
186
- alu_op: AluOPRRR::Sub,
187
- rd,
188
- rs1: rd.to_reg(),
189
- rs2: rs,
190
- });
191
- insts
192
- }
193
-
194
- /// Load int mask.
195
- /// If ty is int then 0xff in rd.
196
- pub(crate) fn load_int_mask(rd: Writable<Reg>, ty: Type) -> SmallInstVec<Inst> {
197
- let mut insts = SmallInstVec::new();
198
- assert!(ty.is_int() && ty.bits() <= 64);
199
- match ty {
200
- I64 => {
201
- insts.push(Inst::load_imm12(rd, Imm12::from_bits(-1)));
202
- }
203
- I32 | I16 => {
204
- insts.push(Inst::load_imm12(rd, Imm12::from_bits(-1)));
205
- insts.push(Inst::Extend {
206
- rd: rd,
207
- rn: rd.to_reg(),
208
- signed: false,
209
- from_bits: ty.bits() as u8,
210
- to_bits: 64,
211
- });
212
- }
213
- I8 => {
214
- insts.push(Inst::load_imm12(rd, Imm12::from_bits(255)));
215
- }
216
- _ => unreachable!("ty:{:?}", ty),
217
- }
218
- insts
219
- }
220
- /// inverse all bit
221
- pub(crate) fn construct_bit_not(rd: Writable<Reg>, rs: Reg) -> Inst {
222
- Inst::AluRRImm12 {
223
- alu_op: AluOPRRI::Xori,
224
- rd,
225
- rs,
226
- imm12: Imm12::from_bits(-1),
227
- }
228
- }
229
-
230
- // emit a float is not a nan.
231
- pub(crate) fn emit_not_nan(rd: Writable<Reg>, rs: Reg, ty: Type) -> Inst {
232
- Inst::FpuRRR {
233
- alu_op: if ty == F32 {
234
- FpuOPRRR::FeqS
235
- } else {
236
- FpuOPRRR::FeqD
237
- },
238
- frm: None,
239
- rd: rd,
240
- rs1: rs,
241
- rs2: rs,
242
- }
243
- }
244
-
245
- pub(crate) fn emit_fabs(rd: Writable<Reg>, rs: Reg, ty: Type) -> Inst {
246
- Inst::FpuRRR {
247
- alu_op: if ty == F32 {
248
- FpuOPRRR::FsgnjxS
249
- } else {
250
- FpuOPRRR::FsgnjxD
251
- },
252
- frm: None,
253
- rd: rd,
254
- rs1: rs,
255
- rs2: rs,
256
- }
257
- }
258
- /// If a float is zero.
259
- pub(crate) fn emit_if_float_not_zero(
260
- tmp: Writable<Reg>,
261
- rs: Reg,
262
- ty: Type,
263
- taken: BranchTarget,
264
- not_taken: BranchTarget,
265
- ) -> SmallInstVec<Inst> {
266
- let mut insts = SmallInstVec::new();
267
- let class_op = if ty == F32 {
268
- FpuOPRR::FclassS
269
- } else {
270
- FpuOPRR::FclassD
271
- };
272
- insts.push(Inst::FpuRR {
273
- alu_op: class_op,
274
- frm: None,
275
- rd: tmp,
276
- rs: rs,
277
- });
278
- insts.push(Inst::AluRRImm12 {
279
- alu_op: AluOPRRI::Andi,
280
- rd: tmp,
281
- rs: tmp.to_reg(),
282
- imm12: Imm12::from_bits(FClassResult::is_zero_bits() as i16),
283
- });
284
- insts.push(Inst::CondBr {
285
- taken,
286
- not_taken,
287
- kind: IntegerCompare {
288
- kind: IntCC::Equal,
289
- rs1: tmp.to_reg(),
290
- rs2: zero_reg(),
291
- },
292
- });
293
- insts
294
- }
295
- pub(crate) fn emit_fneg(rd: Writable<Reg>, rs: Reg, ty: Type) -> Inst {
296
- Inst::FpuRRR {
297
- alu_op: if ty == F32 {
298
- FpuOPRRR::FsgnjnS
299
- } else {
300
- FpuOPRRR::FsgnjnD
301
- },
302
- frm: None,
303
- rd: rd,
304
- rs1: rs,
305
- rs2: rs,
306
- }
307
- }
308
-
309
- pub(crate) fn lower_br_icmp(
310
- cc: IntCC,
311
- a: ValueRegs<Reg>,
312
- b: ValueRegs<Reg>,
313
- taken: BranchTarget,
314
- not_taken: BranchTarget,
315
- ty: Type,
316
- ) -> SmallInstVec<Inst> {
317
- let mut insts = SmallInstVec::new();
318
- if ty.bits() <= 64 {
319
- let rs1 = a.only_reg().unwrap();
320
- let rs2 = b.only_reg().unwrap();
321
- let inst = Inst::CondBr {
322
- taken,
323
- not_taken,
324
- kind: IntegerCompare { kind: cc, rs1, rs2 },
325
- };
326
- insts.push(inst);
327
- return insts;
328
- }
329
- // compare i128
330
- let low = |cc: IntCC| -> IntegerCompare {
331
- IntegerCompare {
332
- rs1: a.regs()[0],
333
- rs2: b.regs()[0],
334
- kind: cc,
335
- }
336
- };
337
- let high = |cc: IntCC| -> IntegerCompare {
338
- IntegerCompare {
339
- rs1: a.regs()[1],
340
- rs2: b.regs()[1],
341
- kind: cc,
342
- }
343
- };
344
- match cc {
345
- IntCC::Equal => {
346
- // if high part not equal,
347
- // then we can go to not_taken otherwise fallthrough.
348
- insts.push(Inst::CondBr {
349
- taken: not_taken,
350
- not_taken: BranchTarget::zero(),
351
- kind: high(IntCC::NotEqual),
352
- });
353
- // the rest part.
354
- insts.push(Inst::CondBr {
355
- taken,
356
- not_taken,
357
- kind: low(IntCC::Equal),
358
- });
359
- }
360
-
361
- IntCC::NotEqual => {
362
- // if the high part not equal ,
363
- // we know the whole must be not equal,
364
- // we can goto the taken part , otherwise fallthrought.
365
- insts.push(Inst::CondBr {
366
- taken,
367
- not_taken: BranchTarget::zero(), // no branch
368
- kind: high(IntCC::NotEqual),
369
- });
370
-
371
- insts.push(Inst::CondBr {
372
- taken,
373
- not_taken,
374
- kind: low(IntCC::NotEqual),
375
- });
376
- }
377
- IntCC::SignedGreaterThanOrEqual
378
- | IntCC::SignedLessThanOrEqual
379
- | IntCC::UnsignedGreaterThanOrEqual
380
- | IntCC::UnsignedLessThanOrEqual
381
- | IntCC::SignedGreaterThan
382
- | IntCC::SignedLessThan
383
- | IntCC::UnsignedLessThan
384
- | IntCC::UnsignedGreaterThan => {
385
- //
386
- insts.push(Inst::CondBr {
387
- taken,
388
- not_taken: BranchTarget::zero(),
389
- kind: high(cc.without_equal()),
390
- });
391
- //
392
- insts.push(Inst::CondBr {
393
- taken: not_taken,
394
- not_taken: BranchTarget::zero(),
395
- kind: high(IntCC::NotEqual),
396
- });
397
- insts.push(Inst::CondBr {
398
- taken,
399
- not_taken,
400
- kind: low(cc.unsigned()),
401
- });
402
- }
403
- }
404
- insts
405
- }
406
-
407
- /// Returns Some(VState) if this insturction is expecting a specific vector state
408
- /// before emission.
409
- fn expected_vstate(&self) -> Option<&VState> {
410
- match self {
411
- Inst::Nop0
412
- | Inst::Nop4
413
- | Inst::BrTable { .. }
414
- | Inst::Auipc { .. }
415
- | Inst::Lui { .. }
416
- | Inst::LoadConst32 { .. }
417
- | Inst::LoadConst64 { .. }
418
- | Inst::AluRRR { .. }
419
- | Inst::FpuRRR { .. }
420
- | Inst::AluRRImm12 { .. }
421
- | Inst::Load { .. }
422
- | Inst::Store { .. }
423
- | Inst::Args { .. }
424
- | Inst::Ret { .. }
425
- | Inst::Extend { .. }
426
- | Inst::AjustSp { .. }
427
- | Inst::Call { .. }
428
- | Inst::CallInd { .. }
429
- | Inst::TrapIf { .. }
430
- | Inst::Jal { .. }
431
- | Inst::CondBr { .. }
432
- | Inst::LoadExtName { .. }
433
- | Inst::LoadAddr { .. }
434
- | Inst::VirtualSPOffsetAdj { .. }
435
- | Inst::Mov { .. }
436
- | Inst::MovFromPReg { .. }
437
- | Inst::Fence { .. }
438
- | Inst::FenceI
439
- | Inst::ECall
440
- | Inst::EBreak
441
- | Inst::Udf { .. }
442
- | Inst::FpuRR { .. }
443
- | Inst::FpuRRRR { .. }
444
- | Inst::Jalr { .. }
445
- | Inst::Atomic { .. }
446
- | Inst::Select { .. }
447
- | Inst::AtomicCas { .. }
448
- | Inst::IntSelect { .. }
449
- | Inst::Icmp { .. }
450
- | Inst::SelectReg { .. }
451
- | Inst::FcvtToInt { .. }
452
- | Inst::RawData { .. }
453
- | Inst::AtomicStore { .. }
454
- | Inst::AtomicLoad { .. }
455
- | Inst::AtomicRmwLoop { .. }
456
- | Inst::TrapIfC { .. }
457
- | Inst::Unwind { .. }
458
- | Inst::DummyUse { .. }
459
- | Inst::FloatRound { .. }
460
- | Inst::FloatSelect { .. }
461
- | Inst::FloatSelectPseudo { .. }
462
- | Inst::Popcnt { .. }
463
- | Inst::Rev8 { .. }
464
- | Inst::Cltz { .. }
465
- | Inst::Brev8 { .. }
466
- | Inst::StackProbeLoop { .. } => None,
467
- // VecSetState does not expect any vstate, rather it updates it.
468
- Inst::VecSetState { .. } => None,
469
-
470
- Inst::VecAluRRR { vstate, .. } |
471
- Inst::VecAluRRImm5 { vstate, .. } |
472
- // TODO: Unit-stride loads and stores only need the AVL to be correct, not
473
- // the full vtype. A future optimization could be to decouple these two when
474
- // updating vstate. This would allow us to avoid emitting a VecSetState in
475
- // some cases.
476
- Inst::VecLoad { vstate, .. }
477
- | Inst::VecStore { vstate, .. } => Some(vstate),
478
- }
479
- }
480
- }
481
-
482
- impl MachInstEmit for Inst {
483
- type State = EmitState;
484
- type Info = EmitInfo;
485
-
486
- fn emit(
487
- &self,
488
- allocs: &[Allocation],
489
- sink: &mut MachBuffer<Inst>,
490
- emit_info: &Self::Info,
491
- state: &mut EmitState,
492
- ) {
493
- let mut allocs = AllocationConsumer::new(allocs);
494
-
495
- // Check if we need to update the vector state before emitting this instruction
496
- if let Some(expected) = self.expected_vstate() {
497
- if state.vstate != EmitVState::Known(expected.clone()) {
498
- // Update the vector state.
499
- Inst::VecSetState {
500
- rd: writable_zero_reg(),
501
- vstate: expected.clone(),
502
- }
503
- .emit(&[], sink, emit_info, state);
504
- }
505
- }
506
-
507
- // N.B.: we *must* not exceed the "worst-case size" used to compute
508
- // where to insert islands, except when islands are explicitly triggered
509
- // (with an `EmitIsland`). We check this in debug builds. This is `mut`
510
- // to allow disabling the check for `JTSequence`, which is always
511
- // emitted following an `EmitIsland`.
512
- let mut start_off = sink.cur_offset();
513
- match self {
514
- &Inst::Nop0 => {
515
- // do nothing
516
- }
517
- // Addi x0, x0, 0
518
- &Inst::Nop4 => {
519
- let x = Inst::AluRRImm12 {
520
- alu_op: AluOPRRI::Addi,
521
- rd: Writable::from_reg(zero_reg()),
522
- rs: zero_reg(),
523
- imm12: Imm12::zero(),
524
- };
525
- x.emit(&[], sink, emit_info, state)
526
- }
527
- &Inst::RawData { ref data } => {
528
- // Right now we only put a u32 or u64 in this instruction.
529
- // It is not very long, no need to check if need `emit_island`.
530
- // If data is very long , this is a bug because RawData is typecial
531
- // use to load some data and rely on some positon in the code stream.
532
- // and we may exceed `Inst::worst_case_size`.
533
- // for more information see https://github.com/bytecodealliance/wasmtime/pull/5612.
534
- sink.put_data(&data[..]);
535
- }
536
- &Inst::Lui { rd, ref imm } => {
537
- let rd = allocs.next_writable(rd);
538
- let x: u32 = 0b0110111 | reg_to_gpr_num(rd.to_reg()) << 7 | (imm.as_u32() << 12);
539
- sink.put4(x);
540
- }
541
- &Inst::LoadConst32 { rd, imm } => {
542
- let rd = allocs.next_writable(rd);
543
- LoadConstant::U32(imm)
544
- .load_constant(rd, &mut |_| rd)
545
- .into_iter()
546
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
547
- }
548
- &Inst::LoadConst64 { rd, imm } => {
549
- let rd = allocs.next_writable(rd);
550
- LoadConstant::U64(imm)
551
- .load_constant(rd, &mut |_| rd)
552
- .into_iter()
553
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
554
- }
555
- &Inst::FpuRR {
556
- frm,
557
- alu_op,
558
- rd,
559
- rs,
560
- } => {
561
- let rs = allocs.next(rs);
562
- let rd = allocs.next_writable(rd);
563
- let x = alu_op.op_code()
564
- | reg_to_gpr_num(rd.to_reg()) << 7
565
- | alu_op.funct3(frm) << 12
566
- | reg_to_gpr_num(rs) << 15
567
- | alu_op.rs2_funct5() << 20
568
- | alu_op.funct7() << 25;
569
- let srcloc = state.cur_srcloc();
570
- if !srcloc.is_default() && alu_op.is_convert_to_int() {
571
- sink.add_trap(TrapCode::BadConversionToInteger);
572
- }
573
- sink.put4(x);
574
- }
575
- &Inst::FpuRRRR {
576
- alu_op,
577
- rd,
578
- rs1,
579
- rs2,
580
- rs3,
581
- frm,
582
- } => {
583
- let rs1 = allocs.next(rs1);
584
- let rs2 = allocs.next(rs2);
585
- let rs3 = allocs.next(rs3);
586
- let rd = allocs.next_writable(rd);
587
- let x = alu_op.op_code()
588
- | reg_to_gpr_num(rd.to_reg()) << 7
589
- | alu_op.funct3(frm) << 12
590
- | reg_to_gpr_num(rs1) << 15
591
- | reg_to_gpr_num(rs2) << 20
592
- | alu_op.funct2() << 25
593
- | reg_to_gpr_num(rs3) << 27;
594
-
595
- sink.put4(x);
596
- }
597
- &Inst::FpuRRR {
598
- alu_op,
599
- frm,
600
- rd,
601
- rs1,
602
- rs2,
603
- } => {
604
- let rs1 = allocs.next(rs1);
605
- let rs2 = allocs.next(rs2);
606
- let rd = allocs.next_writable(rd);
607
-
608
- let x: u32 = alu_op.op_code()
609
- | reg_to_gpr_num(rd.to_reg()) << 7
610
- | (alu_op.funct3(frm)) << 12
611
- | reg_to_gpr_num(rs1) << 15
612
- | reg_to_gpr_num(rs2) << 20
613
- | alu_op.funct7() << 25;
614
- sink.put4(x);
615
- }
616
- &Inst::Unwind { ref inst } => {
617
- sink.add_unwind(inst.clone());
618
- }
619
- &Inst::DummyUse { reg } => {
620
- allocs.next(reg);
621
- }
622
- &Inst::AluRRR {
623
- alu_op,
624
- rd,
625
- rs1,
626
- rs2,
627
- } => {
628
- let rs1 = allocs.next(rs1);
629
- let rs2 = allocs.next(rs2);
630
- let rd = allocs.next_writable(rd);
631
- let (rs1, rs2) = if alu_op.reverse_rs() {
632
- (rs2, rs1)
633
- } else {
634
- (rs1, rs2)
635
- };
636
-
637
- sink.put4(encode_r_type(
638
- alu_op.op_code(),
639
- rd,
640
- alu_op.funct3(),
641
- rs1,
642
- rs2,
643
- alu_op.funct7(),
644
- ));
645
- }
646
- &Inst::AluRRImm12 {
647
- alu_op,
648
- rd,
649
- rs,
650
- imm12,
651
- } => {
652
- let rs = allocs.next(rs);
653
- let rd = allocs.next_writable(rd);
654
- let x = alu_op.op_code()
655
- | reg_to_gpr_num(rd.to_reg()) << 7
656
- | alu_op.funct3() << 12
657
- | reg_to_gpr_num(rs) << 15
658
- | alu_op.imm12(imm12) << 20;
659
- sink.put4(x);
660
- }
661
- &Inst::Load {
662
- rd,
663
- op,
664
- from,
665
- flags,
666
- } => {
667
- let x;
668
- let base = from.get_base_register();
669
- let base = allocs.next(base);
670
- let rd = allocs.next_writable(rd);
671
- let offset = from.get_offset_with_state(state);
672
- if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
673
- let srcloc = state.cur_srcloc();
674
- if !srcloc.is_default() && !flags.notrap() {
675
- // Register the offset at which the actual load instruction starts.
676
- sink.add_trap(TrapCode::HeapOutOfBounds);
677
- }
678
- x = op.op_code()
679
- | reg_to_gpr_num(rd.to_reg()) << 7
680
- | op.funct3() << 12
681
- | reg_to_gpr_num(base) << 15
682
- | (imm12.as_u32()) << 20;
683
- sink.put4(x);
684
- } else {
685
- let tmp = writable_spilltmp_reg();
686
- let mut insts =
687
- LoadConstant::U64(offset as u64).load_constant_and_add(tmp, base);
688
- let srcloc = state.cur_srcloc();
689
- if !srcloc.is_default() && !flags.notrap() {
690
- // Register the offset at which the actual load instruction starts.
691
- sink.add_trap(TrapCode::HeapOutOfBounds);
692
- }
693
- insts.push(Inst::Load {
694
- op,
695
- from: AMode::RegOffset(tmp.to_reg(), 0, I64),
696
- rd,
697
- flags,
698
- });
699
- insts
700
- .into_iter()
701
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
702
- }
703
- }
704
- &Inst::Store { op, src, flags, to } => {
705
- let base = allocs.next(to.get_base_register());
706
- let src = allocs.next(src);
707
- let offset = to.get_offset_with_state(state);
708
- let x;
709
- if let Some(imm12) = Imm12::maybe_from_u64(offset as u64) {
710
- let srcloc = state.cur_srcloc();
711
- if !srcloc.is_default() && !flags.notrap() {
712
- // Register the offset at which the actual load instruction starts.
713
- sink.add_trap(TrapCode::HeapOutOfBounds);
714
- }
715
- x = op.op_code()
716
- | (imm12.as_u32() & 0x1f) << 7
717
- | op.funct3() << 12
718
- | reg_to_gpr_num(base) << 15
719
- | reg_to_gpr_num(src) << 20
720
- | (imm12.as_u32() >> 5) << 25;
721
- sink.put4(x);
722
- } else {
723
- let tmp = writable_spilltmp_reg();
724
- let mut insts =
725
- LoadConstant::U64(offset as u64).load_constant_and_add(tmp, base);
726
- let srcloc = state.cur_srcloc();
727
- if !srcloc.is_default() && !flags.notrap() {
728
- // Register the offset at which the actual load instruction starts.
729
- sink.add_trap(TrapCode::HeapOutOfBounds);
730
- }
731
- insts.push(Inst::Store {
732
- op,
733
- to: AMode::RegOffset(tmp.to_reg(), 0, I64),
734
- flags,
735
- src,
736
- });
737
- insts
738
- .into_iter()
739
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
740
- }
741
- }
742
- &Inst::Args { .. } => {
743
- // Nothing: this is a pseudoinstruction that serves
744
- // only to constrain registers at a certain point.
745
- }
746
- &Inst::Ret { .. } => {
747
- //jalr x0, x1, 0
748
- let x: u32 = (0b1100111) | (1 << 15);
749
- sink.put4(x);
750
- }
751
-
752
- &Inst::Extend {
753
- rd,
754
- rn,
755
- signed,
756
- from_bits,
757
- to_bits: _to_bits,
758
- } => {
759
- let rn = allocs.next(rn);
760
- let rd = allocs.next_writable(rd);
761
- let mut insts = SmallInstVec::new();
762
- let shift_bits = (64 - from_bits) as i16;
763
- let is_u8 = || from_bits == 8 && signed == false;
764
- if is_u8() {
765
- // special for u8.
766
- insts.push(Inst::AluRRImm12 {
767
- alu_op: AluOPRRI::Andi,
768
- rd,
769
- rs: rn,
770
- imm12: Imm12::from_bits(255),
771
- });
772
- } else {
773
- insts.push(Inst::AluRRImm12 {
774
- alu_op: AluOPRRI::Slli,
775
- rd,
776
- rs: rn,
777
- imm12: Imm12::from_bits(shift_bits),
778
- });
779
- insts.push(Inst::AluRRImm12 {
780
- alu_op: if signed {
781
- AluOPRRI::Srai
782
- } else {
783
- AluOPRRI::Srli
784
- },
785
- rd,
786
- rs: rd.to_reg(),
787
- imm12: Imm12::from_bits(shift_bits),
788
- });
789
- }
790
- insts
791
- .into_iter()
792
- .for_each(|i| i.emit(&[], sink, emit_info, state));
793
- }
794
- &Inst::AjustSp { amount } => {
795
- if let Some(imm) = Imm12::maybe_from_u64(amount as u64) {
796
- Inst::AluRRImm12 {
797
- alu_op: AluOPRRI::Addi,
798
- rd: writable_stack_reg(),
799
- rs: stack_reg(),
800
- imm12: imm,
801
- }
802
- .emit(&[], sink, emit_info, state);
803
- } else {
804
- let tmp = writable_spilltmp_reg();
805
- let mut insts = Inst::load_constant_u64(tmp, amount as u64, &mut |_| tmp);
806
- insts.push(Inst::AluRRR {
807
- alu_op: AluOPRRR::Add,
808
- rd: writable_stack_reg(),
809
- rs1: tmp.to_reg(),
810
- rs2: stack_reg(),
811
- });
812
- insts
813
- .into_iter()
814
- .for_each(|i| i.emit(&[], sink, emit_info, state));
815
- }
816
- }
817
- &Inst::Call { ref info } => {
818
- // call
819
- match info.dest {
820
- ExternalName::User { .. } => {
821
- if info.opcode.is_call() {
822
- sink.add_call_site(info.opcode);
823
- }
824
- sink.add_reloc(Reloc::RiscvCall, &info.dest, 0);
825
- if let Some(s) = state.take_stack_map() {
826
- sink.add_stack_map(StackMapExtent::UpcomingBytes(8), s);
827
- }
828
- Inst::construct_auipc_and_jalr(
829
- Some(writable_link_reg()),
830
- writable_link_reg(),
831
- 0,
832
- )
833
- .into_iter()
834
- .for_each(|i| i.emit(&[], sink, emit_info, state));
835
- }
836
- ExternalName::LibCall(..)
837
- | ExternalName::TestCase { .. }
838
- | ExternalName::KnownSymbol(..) => {
839
- // use indirect call. it is more simple.
840
- // load ext name.
841
- Inst::LoadExtName {
842
- rd: writable_spilltmp_reg2(),
843
- name: Box::new(info.dest.clone()),
844
- offset: 0,
845
- }
846
- .emit(&[], sink, emit_info, state);
847
-
848
- if let Some(s) = state.take_stack_map() {
849
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
850
- }
851
- if info.opcode.is_call() {
852
- sink.add_call_site(info.opcode);
853
- }
854
- // call
855
- Inst::Jalr {
856
- rd: writable_link_reg(),
857
- base: spilltmp_reg2(),
858
- offset: Imm12::zero(),
859
- }
860
- .emit(&[], sink, emit_info, state);
861
- }
862
- }
863
- }
864
- &Inst::CallInd { ref info } => {
865
- let rn = allocs.next(info.rn);
866
- if let Some(s) = state.take_stack_map() {
867
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
868
- }
869
-
870
- if info.opcode.is_call() {
871
- sink.add_call_site(info.opcode);
872
- }
873
- Inst::Jalr {
874
- rd: writable_link_reg(),
875
- base: rn,
876
- offset: Imm12::zero(),
877
- }
878
- .emit(&[], sink, emit_info, state);
879
- }
880
-
881
- &Inst::Jal { dest } => {
882
- let code: u32 = 0b1101111;
883
- match dest {
884
- BranchTarget::Label(lable) => {
885
- sink.use_label_at_offset(start_off, lable, LabelUse::Jal20);
886
- sink.add_uncond_branch(start_off, start_off + 4, lable);
887
- sink.put4(code);
888
- }
889
- BranchTarget::ResolvedOffset(offset) => {
890
- let offset = offset as i64;
891
- if offset != 0 {
892
- if LabelUse::Jal20.offset_in_range(offset) {
893
- let mut code = code.to_le_bytes();
894
- LabelUse::Jal20.patch_raw_offset(&mut code, offset);
895
- sink.put_data(&code[..]);
896
- } else {
897
- Inst::construct_auipc_and_jalr(
898
- None,
899
- writable_spilltmp_reg(),
900
- offset,
901
- )
902
- .into_iter()
903
- .for_each(|i| i.emit(&[], sink, emit_info, state));
904
- }
905
- } else {
906
- // CondBr often generate Jal {dest : 0}, means otherwise no jump.
907
- }
908
- }
909
- }
910
- }
911
- &Inst::CondBr {
912
- taken,
913
- not_taken,
914
- mut kind,
915
- } => {
916
- kind.rs1 = allocs.next(kind.rs1);
917
- kind.rs2 = allocs.next(kind.rs2);
918
- match taken {
919
- BranchTarget::Label(label) => {
920
- let code = kind.emit();
921
- let code_inverse = kind.inverse().emit().to_le_bytes();
922
- sink.use_label_at_offset(start_off, label, LabelUse::B12);
923
- sink.add_cond_branch(start_off, start_off + 4, label, &code_inverse);
924
- sink.put4(code);
925
- }
926
- BranchTarget::ResolvedOffset(offset) => {
927
- assert!(offset != 0);
928
- if LabelUse::B12.offset_in_range(offset as i64) {
929
- let code = kind.emit();
930
- let mut code = code.to_le_bytes();
931
- LabelUse::B12.patch_raw_offset(&mut code, offset as i64);
932
- sink.put_data(&code[..])
933
- } else {
934
- let mut code = kind.emit().to_le_bytes();
935
- // jump over the condbr , 4 bytes.
936
- LabelUse::B12.patch_raw_offset(&mut code[..], 4);
937
- sink.put_data(&code[..]);
938
- Inst::construct_auipc_and_jalr(
939
- None,
940
- writable_spilltmp_reg(),
941
- offset as i64,
942
- )
943
- .into_iter()
944
- .for_each(|i| i.emit(&[], sink, emit_info, state));
945
- }
946
- }
947
- }
948
- Inst::Jal { dest: not_taken }.emit(&[], sink, emit_info, state);
949
- }
950
-
951
- &Inst::Mov { rd, rm, ty } => {
952
- if rd.to_reg() != rm {
953
- let rm = allocs.next(rm);
954
- let rd = allocs.next_writable(rd);
955
- if ty.is_float() {
956
- Inst::FpuRRR {
957
- alu_op: if ty == F32 {
958
- FpuOPRRR::FsgnjS
959
- } else {
960
- FpuOPRRR::FsgnjD
961
- },
962
- frm: None,
963
- rd: rd,
964
- rs1: rm,
965
- rs2: rm,
966
- }
967
- .emit(&[], sink, emit_info, state);
968
- } else {
969
- let x = Inst::AluRRImm12 {
970
- alu_op: AluOPRRI::Ori,
971
- rd: rd,
972
- rs: rm,
973
- imm12: Imm12::zero(),
974
- };
975
- x.emit(&[], sink, emit_info, state);
976
- }
977
- }
978
- }
979
-
980
- &Inst::MovFromPReg { rd, rm } => {
981
- debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
982
- let rd = allocs.next_writable(rd);
983
- let x = Inst::AluRRImm12 {
984
- alu_op: AluOPRRI::Ori,
985
- rd,
986
- rs: Reg::from(rm),
987
- imm12: Imm12::zero(),
988
- };
989
- x.emit(&[], sink, emit_info, state);
990
- }
991
-
992
- &Inst::BrTable {
993
- index,
994
- tmp1,
995
- tmp2,
996
- ref targets,
997
- } => {
998
- let index = allocs.next(index);
999
- let tmp1 = allocs.next_writable(tmp1);
1000
- let tmp2 = allocs.next_writable(tmp2);
1001
- let ext_index = writable_spilltmp_reg();
1002
-
1003
- // The default target is passed in as the 0th element of `targets`
1004
- // separate it here for clarity.
1005
- let default_target = targets[0];
1006
- let targets = &targets[1..];
1007
-
1008
- // We emit a bounds check on the index, if the index is larger than the number of
1009
- // jump table entries, we jump to the default block. Otherwise we compute a jump
1010
- // offset by multiplying the index by 8 (the size of each entry) and then jump to
1011
- // that offset. Each jump table entry is a regular auipc+jalr which we emit sequentially.
1012
- //
1013
- // Build the following sequence:
1014
- //
1015
- // extend_index:
1016
- // zext.w ext_index, index
1017
- // bounds_check:
1018
- // li tmp, n_labels
1019
- // bltu ext_index, tmp, compute_target
1020
- // jump_to_default_block:
1021
- // auipc pc, 0
1022
- // jalr zero, pc, default_block
1023
- // compute_target:
1024
- // auipc pc, 0
1025
- // slli tmp, ext_index, 3
1026
- // add pc, pc, tmp
1027
- // jalr zero, pc, 0x10
1028
- // jump_table:
1029
- // ; This repeats for each entry in the jumptable
1030
- // auipc pc, 0
1031
- // jalr zero, pc, block_target
1032
-
1033
- // Extend the index to 64 bits.
1034
- //
1035
- // This prevents us branching on the top 32 bits of the index, which
1036
- // are undefined.
1037
- Inst::Extend {
1038
- rd: ext_index,
1039
- rn: index,
1040
- signed: false,
1041
- from_bits: 32,
1042
- to_bits: 64,
1043
- }
1044
- .emit(&[], sink, emit_info, state);
1045
-
1046
- // Bounds check.
1047
- //
1048
- // Check if the index passed in is larger than the number of jumptable
1049
- // entries that we have. If it is, we fallthrough to a jump into the
1050
- // default block.
1051
- Inst::load_constant_u32(tmp2, targets.len() as u64, &mut |_| tmp2)
1052
- .iter()
1053
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1054
- Inst::CondBr {
1055
- taken: BranchTarget::offset(Inst::INSTRUCTION_SIZE * 3),
1056
- not_taken: BranchTarget::zero(),
1057
- kind: IntegerCompare {
1058
- kind: IntCC::UnsignedLessThan,
1059
- rs1: ext_index.to_reg(),
1060
- rs2: tmp2.to_reg(),
1061
- },
1062
- }
1063
- .emit(&[], sink, emit_info, state);
1064
- sink.use_label_at_offset(
1065
- sink.cur_offset(),
1066
- default_target.as_label().unwrap(),
1067
- LabelUse::PCRel32,
1068
- );
1069
- Inst::construct_auipc_and_jalr(None, tmp2, 0)
1070
- .iter()
1071
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1072
-
1073
- // Compute the jump table offset.
1074
- // We need to emit a PC relative offset,
1075
-
1076
- // Get the current PC.
1077
- Inst::Auipc {
1078
- rd: tmp1,
1079
- imm: Imm20::from_bits(0),
1080
- }
1081
- .emit(&[], sink, emit_info, state);
1082
-
1083
- // Multiply the index by 8, since that is the size in
1084
- // bytes of each jump table entry
1085
- Inst::AluRRImm12 {
1086
- alu_op: AluOPRRI::Slli,
1087
- rd: tmp2,
1088
- rs: ext_index.to_reg(),
1089
- imm12: Imm12::from_bits(3),
1090
- }
1091
- .emit(&[], sink, emit_info, state);
1092
-
1093
- // Calculate the base of the jump, PC + the offset from above.
1094
- Inst::AluRRR {
1095
- alu_op: AluOPRRR::Add,
1096
- rd: tmp1,
1097
- rs1: tmp1.to_reg(),
1098
- rs2: tmp2.to_reg(),
1099
- }
1100
- .emit(&[], sink, emit_info, state);
1101
-
1102
- // Jump to the middle of the jump table.
1103
- // We add a 16 byte offset here, since we used 4 instructions
1104
- // since the AUIPC that was used to get the PC.
1105
- Inst::Jalr {
1106
- rd: writable_zero_reg(),
1107
- base: tmp1.to_reg(),
1108
- offset: Imm12::from_bits((4 * Inst::INSTRUCTION_SIZE) as i16),
1109
- }
1110
- .emit(&[], sink, emit_info, state);
1111
-
1112
- // Emit the jump table.
1113
- //
1114
- // Each entry is a aupc + jalr to the target block. We also start with a island
1115
- // if necessary.
1116
-
1117
- // Each entry in the jump table is 2 instructions, so 8 bytes. Check if
1118
- // we need to emit a jump table here to support that jump.
1119
- let distance = (targets.len() * 2 * Inst::INSTRUCTION_SIZE as usize) as u32;
1120
- if sink.island_needed(distance) {
1121
- sink.emit_island(distance, &mut state.ctrl_plane);
1122
- }
1123
-
1124
- // Emit the jumps back to back
1125
- for target in targets.iter() {
1126
- sink.use_label_at_offset(
1127
- sink.cur_offset(),
1128
- target.as_label().unwrap(),
1129
- LabelUse::PCRel32,
1130
- );
1131
-
1132
- Inst::construct_auipc_and_jalr(None, tmp2, 0)
1133
- .iter()
1134
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1135
- }
1136
-
1137
- // We've just emitted an island that is safe up to *here*.
1138
- // Mark it as such so that we don't needlessly emit additional islands.
1139
- start_off = sink.cur_offset();
1140
- }
1141
-
1142
- &Inst::VirtualSPOffsetAdj { amount } => {
1143
- log::trace!(
1144
- "virtual sp offset adjusted by {} -> {}",
1145
- amount,
1146
- state.virtual_sp_offset + amount
1147
- );
1148
- state.virtual_sp_offset += amount;
1149
- }
1150
- &Inst::Atomic {
1151
- op,
1152
- rd,
1153
- addr,
1154
- src,
1155
- amo,
1156
- } => {
1157
- let addr = allocs.next(addr);
1158
- let src = allocs.next(src);
1159
- let rd = allocs.next_writable(rd);
1160
- let srcloc = state.cur_srcloc();
1161
- if !srcloc.is_default() {
1162
- sink.add_trap(TrapCode::HeapOutOfBounds);
1163
- }
1164
- let x = op.op_code()
1165
- | reg_to_gpr_num(rd.to_reg()) << 7
1166
- | op.funct3() << 12
1167
- | reg_to_gpr_num(addr) << 15
1168
- | reg_to_gpr_num(src) << 20
1169
- | op.funct7(amo) << 25;
1170
-
1171
- sink.put4(x);
1172
- }
1173
- &Inst::Fence { pred, succ } => {
1174
- let x = 0b0001111
1175
- | 0b00000 << 7
1176
- | 0b000 << 12
1177
- | 0b00000 << 15
1178
- | (succ as u32) << 20
1179
- | (pred as u32) << 24;
1180
-
1181
- sink.put4(x);
1182
- }
1183
- &Inst::FenceI => sink.put4(0x0000100f),
1184
- &Inst::Auipc { rd, imm } => {
1185
- let rd = allocs.next_writable(rd);
1186
- let x = enc_auipc(rd, imm);
1187
- sink.put4(x);
1188
- }
1189
-
1190
- &Inst::LoadAddr { rd, mem } => {
1191
- let base = mem.get_base_register();
1192
- let base = allocs.next(base);
1193
- let rd = allocs.next_writable(rd);
1194
- let offset = mem.get_offset_with_state(state);
1195
- if let Some(offset) = Imm12::maybe_from_u64(offset as u64) {
1196
- Inst::AluRRImm12 {
1197
- alu_op: AluOPRRI::Addi,
1198
- rd,
1199
- rs: base,
1200
- imm12: offset,
1201
- }
1202
- .emit(&[], sink, emit_info, state);
1203
- } else {
1204
- let insts = LoadConstant::U64(offset as u64).load_constant_and_add(rd, base);
1205
- insts
1206
- .into_iter()
1207
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1208
- }
1209
- }
1210
-
1211
- &Inst::Select {
1212
- ref dst,
1213
- condition,
1214
- ref x,
1215
- ref y,
1216
- ty: _ty,
1217
- } => {
1218
- let condition = allocs.next(condition);
1219
- let x = alloc_value_regs(x, &mut allocs);
1220
- let y = alloc_value_regs(y, &mut allocs);
1221
- let dst: Vec<_> = dst
1222
- .clone()
1223
- .into_iter()
1224
- .map(|r| allocs.next_writable(r))
1225
- .collect();
1226
-
1227
- let mut insts = SmallInstVec::new();
1228
- let label_false = sink.get_label();
1229
- insts.push(Inst::CondBr {
1230
- taken: BranchTarget::Label(label_false),
1231
- not_taken: BranchTarget::zero(),
1232
- kind: IntegerCompare {
1233
- kind: IntCC::Equal,
1234
- rs1: condition,
1235
- rs2: zero_reg(),
1236
- },
1237
- });
1238
- // here is the true
1239
- // select the first value
1240
- insts.extend(gen_moves(&dst[..], x.regs()));
1241
- let label_jump_over = sink.get_label();
1242
- insts.push(Inst::Jal {
1243
- dest: BranchTarget::Label(label_jump_over),
1244
- });
1245
- // here is false
1246
- insts
1247
- .drain(..)
1248
- .for_each(|i: Inst| i.emit(&[], sink, emit_info, state));
1249
- sink.bind_label(label_false, &mut state.ctrl_plane);
1250
- // select second value1
1251
- insts.extend(gen_moves(&dst[..], y.regs()));
1252
- insts
1253
- .into_iter()
1254
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1255
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
1256
- }
1257
- &Inst::Jalr { rd, base, offset } => {
1258
- let rd = allocs.next_writable(rd);
1259
- let x = enc_jalr(rd, base, offset);
1260
- sink.put4(x);
1261
- }
1262
- &Inst::ECall => {
1263
- sink.put4(0x00000073);
1264
- }
1265
- &Inst::EBreak => {
1266
- sink.put4(0x00100073);
1267
- }
1268
- &Inst::Icmp {
1269
- cc,
1270
- rd,
1271
- ref a,
1272
- ref b,
1273
- ty,
1274
- } => {
1275
- let a = alloc_value_regs(a, &mut allocs);
1276
- let b = alloc_value_regs(b, &mut allocs);
1277
- let rd = allocs.next_writable(rd);
1278
- let label_true = sink.get_label();
1279
- let label_false = sink.get_label();
1280
- Inst::lower_br_icmp(
1281
- cc,
1282
- a,
1283
- b,
1284
- BranchTarget::Label(label_true),
1285
- BranchTarget::Label(label_false),
1286
- ty,
1287
- )
1288
- .into_iter()
1289
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1290
-
1291
- sink.bind_label(label_true, &mut state.ctrl_plane);
1292
- Inst::load_imm12(rd, Imm12::TRUE).emit(&[], sink, emit_info, state);
1293
- Inst::Jal {
1294
- dest: BranchTarget::offset(Inst::INSTRUCTION_SIZE * 2),
1295
- }
1296
- .emit(&[], sink, emit_info, state);
1297
- sink.bind_label(label_false, &mut state.ctrl_plane);
1298
- Inst::load_imm12(rd, Imm12::FALSE).emit(&[], sink, emit_info, state);
1299
- }
1300
- &Inst::AtomicCas {
1301
- offset,
1302
- t0,
1303
- dst,
1304
- e,
1305
- addr,
1306
- v,
1307
- ty,
1308
- } => {
1309
- let offset = allocs.next(offset);
1310
- let e = allocs.next(e);
1311
- let addr = allocs.next(addr);
1312
- let v = allocs.next(v);
1313
- let t0 = allocs.next_writable(t0);
1314
- let dst = allocs.next_writable(dst);
1315
-
1316
- // # addr holds address of memory location
1317
- // # e holds expected value
1318
- // # v holds desired value
1319
- // # dst holds return value
1320
- // cas:
1321
- // lr.w dst, (addr) # Load original value.
1322
- // bne dst, e, fail # Doesn’t match, so fail.
1323
- // sc.w t0, v, (addr) # Try to update.
1324
- // bnez t0 , cas # if store not ok,retry.
1325
- // fail:
1326
- let fail_label = sink.get_label();
1327
- let cas_lebel = sink.get_label();
1328
- sink.bind_label(cas_lebel, &mut state.ctrl_plane);
1329
- Inst::Atomic {
1330
- op: AtomicOP::load_op(ty),
1331
- rd: dst,
1332
- addr,
1333
- src: zero_reg(),
1334
- amo: AMO::SeqCst,
1335
- }
1336
- .emit(&[], sink, emit_info, state);
1337
- if ty.bits() < 32 {
1338
- AtomicOP::extract(dst, offset, dst.to_reg(), ty)
1339
- .iter()
1340
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1341
- } else if ty.bits() == 32 {
1342
- Inst::Extend {
1343
- rd: dst,
1344
- rn: dst.to_reg(),
1345
- signed: false,
1346
- from_bits: 32,
1347
- to_bits: 64,
1348
- }
1349
- .emit(&[], sink, emit_info, state);
1350
- }
1351
- Inst::CondBr {
1352
- taken: BranchTarget::Label(fail_label),
1353
- not_taken: BranchTarget::zero(),
1354
- kind: IntegerCompare {
1355
- kind: IntCC::NotEqual,
1356
- rs1: e,
1357
- rs2: dst.to_reg(),
1358
- },
1359
- }
1360
- .emit(&[], sink, emit_info, state);
1361
- let store_value = if ty.bits() < 32 {
1362
- // reload value to t0.
1363
- Inst::Atomic {
1364
- op: AtomicOP::load_op(ty),
1365
- rd: t0,
1366
- addr,
1367
- src: zero_reg(),
1368
- amo: AMO::SeqCst,
1369
- }
1370
- .emit(&[], sink, emit_info, state);
1371
- // set reset part.
1372
- AtomicOP::merge(t0, writable_spilltmp_reg(), offset, v, ty)
1373
- .iter()
1374
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1375
- t0.to_reg()
1376
- } else {
1377
- v
1378
- };
1379
- Inst::Atomic {
1380
- op: AtomicOP::store_op(ty),
1381
- rd: t0,
1382
- addr,
1383
- src: store_value,
1384
- amo: AMO::SeqCst,
1385
- }
1386
- .emit(&[], sink, emit_info, state);
1387
- // check is our value stored.
1388
- Inst::CondBr {
1389
- taken: BranchTarget::Label(cas_lebel),
1390
- not_taken: BranchTarget::zero(),
1391
- kind: IntegerCompare {
1392
- kind: IntCC::NotEqual,
1393
- rs1: t0.to_reg(),
1394
- rs2: zero_reg(),
1395
- },
1396
- }
1397
- .emit(&[], sink, emit_info, state);
1398
- sink.bind_label(fail_label, &mut state.ctrl_plane);
1399
- }
1400
- &Inst::AtomicRmwLoop {
1401
- offset,
1402
- op,
1403
- dst,
1404
- ty,
1405
- p,
1406
- x,
1407
- t0,
1408
- } => {
1409
- let offset = allocs.next(offset);
1410
- let p = allocs.next(p);
1411
- let x = allocs.next(x);
1412
- let t0 = allocs.next_writable(t0);
1413
- let dst = allocs.next_writable(dst);
1414
- let retry = sink.get_label();
1415
- sink.bind_label(retry, &mut state.ctrl_plane);
1416
- // load old value.
1417
- Inst::Atomic {
1418
- op: AtomicOP::load_op(ty),
1419
- rd: dst,
1420
- addr: p,
1421
- src: zero_reg(),
1422
- amo: AMO::SeqCst,
1423
- }
1424
- .emit(&[], sink, emit_info, state);
1425
- //
1426
-
1427
- let store_value: Reg = match op {
1428
- crate::ir::AtomicRmwOp::Add
1429
- | crate::ir::AtomicRmwOp::Sub
1430
- | crate::ir::AtomicRmwOp::And
1431
- | crate::ir::AtomicRmwOp::Or
1432
- | crate::ir::AtomicRmwOp::Xor => {
1433
- AtomicOP::extract(dst, offset, dst.to_reg(), ty)
1434
- .iter()
1435
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1436
- Inst::AluRRR {
1437
- alu_op: match op {
1438
- crate::ir::AtomicRmwOp::Add => AluOPRRR::Add,
1439
- crate::ir::AtomicRmwOp::Sub => AluOPRRR::Sub,
1440
- crate::ir::AtomicRmwOp::And => AluOPRRR::And,
1441
- crate::ir::AtomicRmwOp::Or => AluOPRRR::Or,
1442
- crate::ir::AtomicRmwOp::Xor => AluOPRRR::Xor,
1443
- _ => unreachable!(),
1444
- },
1445
- rd: t0,
1446
- rs1: dst.to_reg(),
1447
- rs2: x,
1448
- }
1449
- .emit(&[], sink, emit_info, state);
1450
- Inst::Atomic {
1451
- op: AtomicOP::load_op(ty),
1452
- rd: writable_spilltmp_reg2(),
1453
- addr: p,
1454
- src: zero_reg(),
1455
- amo: AMO::SeqCst,
1456
- }
1457
- .emit(&[], sink, emit_info, state);
1458
- AtomicOP::merge(
1459
- writable_spilltmp_reg2(),
1460
- writable_spilltmp_reg(),
1461
- offset,
1462
- t0.to_reg(),
1463
- ty,
1464
- )
1465
- .iter()
1466
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1467
- spilltmp_reg2()
1468
- }
1469
- crate::ir::AtomicRmwOp::Nand => {
1470
- if ty.bits() < 32 {
1471
- AtomicOP::extract(dst, offset, dst.to_reg(), ty)
1472
- .iter()
1473
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1474
- }
1475
- Inst::AluRRR {
1476
- alu_op: AluOPRRR::And,
1477
- rd: t0,
1478
- rs1: x,
1479
- rs2: dst.to_reg(),
1480
- }
1481
- .emit(&[], sink, emit_info, state);
1482
- Inst::construct_bit_not(t0, t0.to_reg()).emit(&[], sink, emit_info, state);
1483
- if ty.bits() < 32 {
1484
- Inst::Atomic {
1485
- op: AtomicOP::load_op(ty),
1486
- rd: writable_spilltmp_reg2(),
1487
- addr: p,
1488
- src: zero_reg(),
1489
- amo: AMO::SeqCst,
1490
- }
1491
- .emit(&[], sink, emit_info, state);
1492
- AtomicOP::merge(
1493
- writable_spilltmp_reg2(),
1494
- writable_spilltmp_reg(),
1495
- offset,
1496
- t0.to_reg(),
1497
- ty,
1498
- )
1499
- .iter()
1500
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1501
- spilltmp_reg2()
1502
- } else {
1503
- t0.to_reg()
1504
- }
1505
- }
1506
-
1507
- crate::ir::AtomicRmwOp::Umin
1508
- | crate::ir::AtomicRmwOp::Umax
1509
- | crate::ir::AtomicRmwOp::Smin
1510
- | crate::ir::AtomicRmwOp::Smax => {
1511
- let label_select_dst = sink.get_label();
1512
- let label_select_done = sink.get_label();
1513
- if op == crate::ir::AtomicRmwOp::Umin || op == crate::ir::AtomicRmwOp::Umax
1514
- {
1515
- AtomicOP::extract(dst, offset, dst.to_reg(), ty)
1516
- } else {
1517
- AtomicOP::extract_sext(dst, offset, dst.to_reg(), ty)
1518
- }
1519
- .iter()
1520
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1521
- Inst::lower_br_icmp(
1522
- match op {
1523
- crate::ir::AtomicRmwOp::Umin => IntCC::UnsignedLessThan,
1524
- crate::ir::AtomicRmwOp::Umax => IntCC::UnsignedGreaterThan,
1525
- crate::ir::AtomicRmwOp::Smin => IntCC::SignedLessThan,
1526
- crate::ir::AtomicRmwOp::Smax => IntCC::SignedGreaterThan,
1527
- _ => unreachable!(),
1528
- },
1529
- ValueRegs::one(dst.to_reg()),
1530
- ValueRegs::one(x),
1531
- BranchTarget::Label(label_select_dst),
1532
- BranchTarget::zero(),
1533
- ty,
1534
- )
1535
- .iter()
1536
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1537
- // here we select x.
1538
- Inst::gen_move(t0, x, I64).emit(&[], sink, emit_info, state);
1539
- Inst::Jal {
1540
- dest: BranchTarget::Label(label_select_done),
1541
- }
1542
- .emit(&[], sink, emit_info, state);
1543
- sink.bind_label(label_select_dst, &mut state.ctrl_plane);
1544
- Inst::gen_move(t0, dst.to_reg(), I64).emit(&[], sink, emit_info, state);
1545
- sink.bind_label(label_select_done, &mut state.ctrl_plane);
1546
- Inst::Atomic {
1547
- op: AtomicOP::load_op(ty),
1548
- rd: writable_spilltmp_reg2(),
1549
- addr: p,
1550
- src: zero_reg(),
1551
- amo: AMO::SeqCst,
1552
- }
1553
- .emit(&[], sink, emit_info, state);
1554
- AtomicOP::merge(
1555
- writable_spilltmp_reg2(),
1556
- writable_spilltmp_reg(),
1557
- offset,
1558
- t0.to_reg(),
1559
- ty,
1560
- )
1561
- .iter()
1562
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1563
- spilltmp_reg2()
1564
- }
1565
- crate::ir::AtomicRmwOp::Xchg => {
1566
- AtomicOP::extract(dst, offset, dst.to_reg(), ty)
1567
- .iter()
1568
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1569
- Inst::Atomic {
1570
- op: AtomicOP::load_op(ty),
1571
- rd: writable_spilltmp_reg2(),
1572
- addr: p,
1573
- src: zero_reg(),
1574
- amo: AMO::SeqCst,
1575
- }
1576
- .emit(&[], sink, emit_info, state);
1577
- AtomicOP::merge(
1578
- writable_spilltmp_reg2(),
1579
- writable_spilltmp_reg(),
1580
- offset,
1581
- x,
1582
- ty,
1583
- )
1584
- .iter()
1585
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1586
- spilltmp_reg2()
1587
- }
1588
- };
1589
-
1590
- Inst::Atomic {
1591
- op: AtomicOP::store_op(ty),
1592
- rd: t0,
1593
- addr: p,
1594
- src: store_value,
1595
- amo: AMO::SeqCst,
1596
- }
1597
- .emit(&[], sink, emit_info, state);
1598
-
1599
- // if store is not ok,retry.
1600
- Inst::CondBr {
1601
- taken: BranchTarget::Label(retry),
1602
- not_taken: BranchTarget::zero(),
1603
- kind: IntegerCompare {
1604
- kind: IntCC::NotEqual,
1605
- rs1: t0.to_reg(),
1606
- rs2: zero_reg(),
1607
- },
1608
- }
1609
- .emit(&[], sink, emit_info, state);
1610
- }
1611
-
1612
- &Inst::IntSelect {
1613
- op,
1614
- ref dst,
1615
- ref x,
1616
- ref y,
1617
- ty,
1618
- } => {
1619
- let x = alloc_value_regs(x, &mut allocs);
1620
- let y = alloc_value_regs(y, &mut allocs);
1621
- let dst: Vec<_> = dst.iter().map(|r| allocs.next_writable(*r)).collect();
1622
- let label_true = sink.get_label();
1623
- let label_false = sink.get_label();
1624
- let label_done = sink.get_label();
1625
- Inst::lower_br_icmp(
1626
- op.to_int_cc(),
1627
- x,
1628
- y,
1629
- BranchTarget::Label(label_true),
1630
- BranchTarget::Label(label_false),
1631
- ty,
1632
- )
1633
- .into_iter()
1634
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1635
-
1636
- let gen_move = |dst: &Vec<Writable<Reg>>,
1637
- val: &ValueRegs<Reg>,
1638
- sink: &mut MachBuffer<Inst>,
1639
- state: &mut EmitState| {
1640
- let mut insts = SmallInstVec::new();
1641
- insts.push(Inst::Mov {
1642
- rd: dst[0],
1643
- rm: val.regs()[0],
1644
- ty: I64,
1645
- });
1646
- if ty.bits() == 128 {
1647
- insts.push(Inst::Mov {
1648
- rd: dst[1],
1649
- rm: val.regs()[1],
1650
- ty,
1651
- });
1652
- }
1653
- insts
1654
- .into_iter()
1655
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1656
- };
1657
- //here is true , use x.
1658
- sink.bind_label(label_true, &mut state.ctrl_plane);
1659
- gen_move(&dst, &x, sink, state);
1660
- Inst::gen_jump(label_done).emit(&[], sink, emit_info, state);
1661
- // here is false use y
1662
- sink.bind_label(label_false, &mut state.ctrl_plane);
1663
- gen_move(&dst, &y, sink, state);
1664
- sink.bind_label(label_done, &mut state.ctrl_plane);
1665
- }
1666
-
1667
- &Inst::SelectReg {
1668
- condition,
1669
- rd,
1670
- rs1,
1671
- rs2,
1672
- } => {
1673
- let mut condition = condition.clone();
1674
- condition.rs1 = allocs.next(condition.rs1);
1675
- condition.rs2 = allocs.next(condition.rs2);
1676
- let rs1 = allocs.next(rs1);
1677
- let rs2 = allocs.next(rs2);
1678
- let rd = allocs.next_writable(rd);
1679
- let label_true = sink.get_label();
1680
- let label_jump_over = sink.get_label();
1681
- sink.use_label_at_offset(sink.cur_offset(), label_true, LabelUse::B12);
1682
- let x = condition.emit();
1683
- sink.put4(x);
1684
- // here is false , use rs2
1685
- Inst::gen_move(rd, rs2, I64).emit(&[], sink, emit_info, state);
1686
- // and jump over
1687
- Inst::Jal {
1688
- dest: BranchTarget::Label(label_jump_over),
1689
- }
1690
- .emit(&[], sink, emit_info, state);
1691
- // here condition is true , use rs1
1692
- sink.bind_label(label_true, &mut state.ctrl_plane);
1693
- Inst::gen_move(rd, rs1, I64).emit(&[], sink, emit_info, state);
1694
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
1695
- }
1696
- &Inst::FcvtToInt {
1697
- is_sat,
1698
- rd,
1699
- rs,
1700
- is_signed,
1701
- in_type,
1702
- out_type,
1703
- tmp,
1704
- } => {
1705
- let rs = allocs.next(rs);
1706
- let tmp = allocs.next_writable(tmp);
1707
- let rd = allocs.next_writable(rd);
1708
- let label_nan = sink.get_label();
1709
- let label_jump_over = sink.get_label();
1710
- // get if nan.
1711
- Inst::emit_not_nan(rd, rs, in_type).emit(&[], sink, emit_info, state);
1712
- // jump to nan.
1713
- Inst::CondBr {
1714
- taken: BranchTarget::Label(label_nan),
1715
- not_taken: BranchTarget::zero(),
1716
- kind: IntegerCompare {
1717
- kind: IntCC::Equal,
1718
- rs2: zero_reg(),
1719
- rs1: rd.to_reg(),
1720
- },
1721
- }
1722
- .emit(&[], sink, emit_info, state);
1723
-
1724
- if !is_sat {
1725
- let f32_bounds = f32_cvt_to_int_bounds(is_signed, out_type.bits() as u8);
1726
- let f64_bounds = f64_cvt_to_int_bounds(is_signed, out_type.bits() as u8);
1727
- if in_type == F32 {
1728
- Inst::load_fp_constant32(tmp, f32_bits(f32_bounds.0), |_| {
1729
- writable_spilltmp_reg()
1730
- })
1731
- } else {
1732
- Inst::load_fp_constant64(tmp, f64_bits(f64_bounds.0), |_| {
1733
- writable_spilltmp_reg()
1734
- })
1735
- }
1736
- .iter()
1737
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1738
-
1739
- let le_op = if in_type == F32 {
1740
- FpuOPRRR::FleS
1741
- } else {
1742
- FpuOPRRR::FleD
1743
- };
1744
-
1745
- // rd := rs <= tmp
1746
- Inst::FpuRRR {
1747
- alu_op: le_op,
1748
- frm: None,
1749
- rd,
1750
- rs1: rs,
1751
- rs2: tmp.to_reg(),
1752
- }
1753
- .emit(&[], sink, emit_info, state);
1754
- Inst::TrapIf {
1755
- test: rd.to_reg(),
1756
- trap_code: TrapCode::IntegerOverflow,
1757
- }
1758
- .emit(&[], sink, emit_info, state);
1759
-
1760
- if in_type == F32 {
1761
- Inst::load_fp_constant32(tmp, f32_bits(f32_bounds.1), |_| {
1762
- writable_spilltmp_reg()
1763
- })
1764
- } else {
1765
- Inst::load_fp_constant64(tmp, f64_bits(f64_bounds.1), |_| {
1766
- writable_spilltmp_reg()
1767
- })
1768
- }
1769
- .iter()
1770
- .for_each(|i| i.emit(&[], sink, emit_info, state));
1771
-
1772
- // rd := rs >= tmp
1773
- Inst::FpuRRR {
1774
- alu_op: le_op,
1775
- frm: None,
1776
- rd,
1777
- rs1: tmp.to_reg(),
1778
- rs2: rs,
1779
- }
1780
- .emit(&[], sink, emit_info, state);
1781
-
1782
- Inst::TrapIf {
1783
- test: rd.to_reg(),
1784
- trap_code: TrapCode::IntegerOverflow,
1785
- }
1786
- .emit(&[], sink, emit_info, state);
1787
- }
1788
- // convert to int normally.
1789
- Inst::FpuRR {
1790
- frm: Some(FRM::RTZ),
1791
- alu_op: FpuOPRR::float_convert_2_int_op(in_type, is_signed, out_type),
1792
- rd,
1793
- rs,
1794
- }
1795
- .emit(&[], sink, emit_info, state);
1796
- if out_type.bits() < 32 && is_signed {
1797
- // load value part mask.
1798
- Inst::load_constant_u32(
1799
- writable_spilltmp_reg(),
1800
- if 16 == out_type.bits() {
1801
- (u16::MAX >> 1) as u64
1802
- } else {
1803
- // I8
1804
- (u8::MAX >> 1) as u64
1805
- },
1806
- &mut |_| writable_spilltmp_reg2(),
1807
- )
1808
- .into_iter()
1809
- .for_each(|x| x.emit(&[], sink, emit_info, state));
1810
- // keep value part.
1811
- Inst::AluRRR {
1812
- alu_op: AluOPRRR::And,
1813
- rd: writable_spilltmp_reg(),
1814
- rs1: rd.to_reg(),
1815
- rs2: spilltmp_reg(),
1816
- }
1817
- .emit(&[], sink, emit_info, state);
1818
- // extact sign bit.
1819
- Inst::AluRRImm12 {
1820
- alu_op: AluOPRRI::Srli,
1821
- rd: rd,
1822
- rs: rd.to_reg(),
1823
- imm12: Imm12::from_bits(31),
1824
- }
1825
- .emit(&[], sink, emit_info, state);
1826
- Inst::AluRRImm12 {
1827
- alu_op: AluOPRRI::Slli,
1828
- rd: rd,
1829
- rs: rd.to_reg(),
1830
- imm12: Imm12::from_bits(if 16 == out_type.bits() {
1831
- 15
1832
- } else {
1833
- // I8
1834
- 7
1835
- }),
1836
- }
1837
- .emit(&[], sink, emit_info, state);
1838
- // make result,sign bit and value part.
1839
- Inst::AluRRR {
1840
- alu_op: AluOPRRR::Or,
1841
- rd: rd,
1842
- rs1: rd.to_reg(),
1843
- rs2: spilltmp_reg(),
1844
- }
1845
- .emit(&[], sink, emit_info, state);
1846
- }
1847
-
1848
- // I already have the result,jump over.
1849
- Inst::Jal {
1850
- dest: BranchTarget::Label(label_jump_over),
1851
- }
1852
- .emit(&[], sink, emit_info, state);
1853
- // here is nan , move 0 into rd register
1854
- sink.bind_label(label_nan, &mut state.ctrl_plane);
1855
- if is_sat {
1856
- Inst::load_imm12(rd, Imm12::from_bits(0)).emit(&[], sink, emit_info, state);
1857
- } else {
1858
- // here is ud2.
1859
- Inst::Udf {
1860
- trap_code: TrapCode::BadConversionToInteger,
1861
- }
1862
- .emit(&[], sink, emit_info, state);
1863
- }
1864
- // bind jump_over
1865
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
1866
- }
1867
-
1868
- &Inst::LoadExtName {
1869
- rd,
1870
- ref name,
1871
- offset,
1872
- } => {
1873
- let rd = allocs.next_writable(rd);
1874
- // get the current pc.
1875
- Inst::Auipc {
1876
- rd: rd,
1877
- imm: Imm20::from_bits(0),
1878
- }
1879
- .emit(&[], sink, emit_info, state);
1880
- // load the value.
1881
- Inst::Load {
1882
- rd: rd,
1883
- op: LoadOP::Ld,
1884
- flags: MemFlags::trusted(),
1885
- from: AMode::RegOffset(
1886
- rd.to_reg(),
1887
- 12, // auipc load and jal.
1888
- I64,
1889
- ),
1890
- }
1891
- .emit(&[], sink, emit_info, state);
1892
- // jump over.
1893
- Inst::Jal {
1894
- // jal and abs8 size for 12.
1895
- dest: BranchTarget::offset(12),
1896
- }
1897
- .emit(&[], sink, emit_info, state);
1898
-
1899
- sink.add_reloc(Reloc::Abs8, name.as_ref(), offset);
1900
- sink.put8(0);
1901
- }
1902
- &Inst::TrapIfC {
1903
- rs1,
1904
- rs2,
1905
- cc,
1906
- trap_code,
1907
- } => {
1908
- let rs1 = allocs.next(rs1);
1909
- let rs2 = allocs.next(rs2);
1910
- let label_trap = sink.get_label();
1911
- let label_jump_over = sink.get_label();
1912
- Inst::CondBr {
1913
- taken: BranchTarget::Label(label_trap),
1914
- not_taken: BranchTarget::Label(label_jump_over),
1915
- kind: IntegerCompare { kind: cc, rs1, rs2 },
1916
- }
1917
- .emit(&[], sink, emit_info, state);
1918
- // trap
1919
- sink.bind_label(label_trap, &mut state.ctrl_plane);
1920
- Inst::Udf {
1921
- trap_code: trap_code,
1922
- }
1923
- .emit(&[], sink, emit_info, state);
1924
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
1925
- }
1926
- &Inst::TrapIf { test, trap_code } => {
1927
- let test = allocs.next(test);
1928
- let label_trap = sink.get_label();
1929
- let label_jump_over = sink.get_label();
1930
- Inst::CondBr {
1931
- taken: BranchTarget::Label(label_trap),
1932
- not_taken: BranchTarget::Label(label_jump_over),
1933
- kind: IntegerCompare {
1934
- kind: IntCC::NotEqual,
1935
- rs1: test,
1936
- rs2: zero_reg(),
1937
- },
1938
- }
1939
- .emit(&[], sink, emit_info, state);
1940
- // trap
1941
- sink.bind_label(label_trap, &mut state.ctrl_plane);
1942
- Inst::Udf {
1943
- trap_code: trap_code,
1944
- }
1945
- .emit(&[], sink, emit_info, state);
1946
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
1947
- }
1948
- &Inst::Udf { trap_code } => {
1949
- sink.add_trap(trap_code);
1950
- if let Some(s) = state.take_stack_map() {
1951
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
1952
- }
1953
- sink.put_data(Inst::TRAP_OPCODE);
1954
- }
1955
- &Inst::AtomicLoad { rd, ty, p } => {
1956
- let p = allocs.next(p);
1957
- let rd = allocs.next_writable(rd);
1958
- // emit the fence.
1959
- Inst::Fence {
1960
- pred: Inst::FENCE_REQ_R | Inst::FENCE_REQ_W,
1961
- succ: Inst::FENCE_REQ_R | Inst::FENCE_REQ_W,
1962
- }
1963
- .emit(&[], sink, emit_info, state);
1964
- // load.
1965
- Inst::Load {
1966
- rd: rd,
1967
- op: LoadOP::from_type(ty),
1968
- flags: MemFlags::new(),
1969
- from: AMode::RegOffset(p, 0, ty),
1970
- }
1971
- .emit(&[], sink, emit_info, state);
1972
- Inst::Fence {
1973
- pred: Inst::FENCE_REQ_R,
1974
- succ: Inst::FENCE_REQ_R | Inst::FENCE_REQ_W,
1975
- }
1976
- .emit(&[], sink, emit_info, state);
1977
- }
1978
- &Inst::AtomicStore { src, ty, p } => {
1979
- let src = allocs.next(src);
1980
- let p = allocs.next(p);
1981
- Inst::Fence {
1982
- pred: Inst::FENCE_REQ_R | Inst::FENCE_REQ_W,
1983
- succ: Inst::FENCE_REQ_W,
1984
- }
1985
- .emit(&[], sink, emit_info, state);
1986
- Inst::Store {
1987
- to: AMode::RegOffset(p, 0, ty),
1988
- op: StoreOP::from_type(ty),
1989
- flags: MemFlags::new(),
1990
- src,
1991
- }
1992
- .emit(&[], sink, emit_info, state);
1993
- }
1994
- &Inst::FloatRound {
1995
- op,
1996
- rd,
1997
- int_tmp,
1998
- f_tmp,
1999
- rs,
2000
- ty,
2001
- } => {
2002
- // this code is port from glibc ceil floor ... implementation.
2003
- let rs = allocs.next(rs);
2004
- let int_tmp = allocs.next_writable(int_tmp);
2005
- let f_tmp = allocs.next_writable(f_tmp);
2006
- let rd = allocs.next_writable(rd);
2007
- let label_nan = sink.get_label();
2008
- let label_x = sink.get_label();
2009
- let label_jump_over = sink.get_label();
2010
- // check if is nan.
2011
- Inst::emit_not_nan(int_tmp, rs, ty).emit(&[], sink, emit_info, state);
2012
- Inst::CondBr {
2013
- taken: BranchTarget::Label(label_nan),
2014
- not_taken: BranchTarget::zero(),
2015
- kind: IntegerCompare {
2016
- kind: IntCC::Equal,
2017
- rs1: int_tmp.to_reg(),
2018
- rs2: zero_reg(),
2019
- },
2020
- }
2021
- .emit(&[], sink, emit_info, state);
2022
- fn max_value_need_round(ty: Type) -> u64 {
2023
- match ty {
2024
- F32 => {
2025
- let x: u64 = 1 << f32::MANTISSA_DIGITS;
2026
- let x = x as f32;
2027
- let x = u32::from_le_bytes(x.to_le_bytes());
2028
- x as u64
2029
- }
2030
- F64 => {
2031
- let x: u64 = 1 << f64::MANTISSA_DIGITS;
2032
- let x = x as f64;
2033
- u64::from_le_bytes(x.to_le_bytes())
2034
- }
2035
- _ => unreachable!(),
2036
- }
2037
- }
2038
- // load max value need to round.
2039
- if ty == F32 {
2040
- Inst::load_fp_constant32(f_tmp, max_value_need_round(ty) as u32, &mut |_| {
2041
- writable_spilltmp_reg()
2042
- })
2043
- } else {
2044
- Inst::load_fp_constant64(f_tmp, max_value_need_round(ty), &mut |_| {
2045
- writable_spilltmp_reg()
2046
- })
2047
- }
2048
- .into_iter()
2049
- .for_each(|i| i.emit(&[], sink, emit_info, state));
2050
-
2051
- // get abs value.
2052
- Inst::emit_fabs(rd, rs, ty).emit(&[], sink, emit_info, state);
2053
-
2054
- // branch if f_tmp < rd
2055
- Inst::FpuRRR {
2056
- frm: None,
2057
- alu_op: if ty == F32 {
2058
- FpuOPRRR::FltS
2059
- } else {
2060
- FpuOPRRR::FltD
2061
- },
2062
- rd: int_tmp,
2063
- rs1: f_tmp.to_reg(),
2064
- rs2: rd.to_reg(),
2065
- }
2066
- .emit(&[], sink, emit_info, state);
2067
-
2068
- Inst::CondBr {
2069
- taken: BranchTarget::Label(label_x),
2070
- not_taken: BranchTarget::zero(),
2071
- kind: IntegerCompare {
2072
- kind: IntCC::NotEqual,
2073
- rs1: int_tmp.to_reg(),
2074
- rs2: zero_reg(),
2075
- },
2076
- }
2077
- .emit(&[], sink, emit_info, state);
2078
-
2079
- //convert to int.
2080
- Inst::FpuRR {
2081
- alu_op: FpuOPRR::float_convert_2_int_op(ty, true, I64),
2082
- frm: Some(op.to_frm()),
2083
- rd: int_tmp,
2084
- rs: rs,
2085
- }
2086
- .emit(&[], sink, emit_info, state);
2087
- //convert back.
2088
- Inst::FpuRR {
2089
- alu_op: FpuOPRR::int_convert_2_float_op(I64, true, ty),
2090
- frm: Some(op.to_frm()),
2091
- rd,
2092
- rs: int_tmp.to_reg(),
2093
- }
2094
- .emit(&[], sink, emit_info, state);
2095
- // copy sign.
2096
- Inst::FpuRRR {
2097
- alu_op: if ty == F32 {
2098
- FpuOPRRR::FsgnjS
2099
- } else {
2100
- FpuOPRRR::FsgnjD
2101
- },
2102
- frm: None,
2103
- rd,
2104
- rs1: rd.to_reg(),
2105
- rs2: rs,
2106
- }
2107
- .emit(&[], sink, emit_info, state);
2108
- // jump over.
2109
- Inst::Jal {
2110
- dest: BranchTarget::Label(label_jump_over),
2111
- }
2112
- .emit(&[], sink, emit_info, state);
2113
- // here is nan.
2114
- sink.bind_label(label_nan, &mut state.ctrl_plane);
2115
- Inst::FpuRRR {
2116
- alu_op: if ty == F32 {
2117
- FpuOPRRR::FaddS
2118
- } else {
2119
- FpuOPRRR::FaddD
2120
- },
2121
- frm: None,
2122
- rd: rd,
2123
- rs1: rs,
2124
- rs2: rs,
2125
- }
2126
- .emit(&[], sink, emit_info, state);
2127
- Inst::Jal {
2128
- dest: BranchTarget::Label(label_jump_over),
2129
- }
2130
- .emit(&[], sink, emit_info, state);
2131
- // here select origin x.
2132
- sink.bind_label(label_x, &mut state.ctrl_plane);
2133
- Inst::gen_move(rd, rs, ty).emit(&[], sink, emit_info, state);
2134
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
2135
- }
2136
- &Inst::FloatSelectPseudo {
2137
- op,
2138
- rd,
2139
- tmp,
2140
- rs1,
2141
- rs2,
2142
- ty,
2143
- } => {
2144
- let rs1 = allocs.next(rs1);
2145
- let rs2 = allocs.next(rs2);
2146
- let tmp = allocs.next_writable(tmp);
2147
- let rd = allocs.next_writable(rd);
2148
- let label_rs2 = sink.get_label();
2149
- let label_jump_over = sink.get_label();
2150
- let lt_op = if ty == F32 {
2151
- FpuOPRRR::FltS
2152
- } else {
2153
- FpuOPRRR::FltD
2154
- };
2155
- Inst::FpuRRR {
2156
- alu_op: lt_op,
2157
- frm: None,
2158
- rd: tmp,
2159
- rs1: if op == FloatSelectOP::Max { rs1 } else { rs2 },
2160
- rs2: if op == FloatSelectOP::Max { rs2 } else { rs1 },
2161
- }
2162
- .emit(&[], sink, emit_info, state);
2163
- Inst::CondBr {
2164
- taken: BranchTarget::Label(label_rs2),
2165
- not_taken: BranchTarget::zero(),
2166
- kind: IntegerCompare {
2167
- kind: IntCC::NotEqual,
2168
- rs1: tmp.to_reg(),
2169
- rs2: zero_reg(),
2170
- },
2171
- }
2172
- .emit(&[], sink, emit_info, state);
2173
- // here select rs1 as result.
2174
- Inst::gen_move(rd, rs1, ty).emit(&[], sink, emit_info, state);
2175
- Inst::Jal {
2176
- dest: BranchTarget::Label(label_jump_over),
2177
- }
2178
- .emit(&[], sink, emit_info, state);
2179
- sink.bind_label(label_rs2, &mut state.ctrl_plane);
2180
- Inst::gen_move(rd, rs2, ty).emit(&[], sink, emit_info, state);
2181
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
2182
- }
2183
-
2184
- &Inst::FloatSelect {
2185
- op,
2186
- rd,
2187
- tmp,
2188
- rs1,
2189
- rs2,
2190
- ty,
2191
- } => {
2192
- let rs1 = allocs.next(rs1);
2193
- let rs2 = allocs.next(rs2);
2194
- let tmp = allocs.next_writable(tmp);
2195
- let rd = allocs.next_writable(rd);
2196
- let label_nan = sink.get_label();
2197
- let label_jump_over = sink.get_label();
2198
- // check if rs1 is nan.
2199
- Inst::emit_not_nan(tmp, rs1, ty).emit(&[], sink, emit_info, state);
2200
- Inst::CondBr {
2201
- taken: BranchTarget::Label(label_nan),
2202
- not_taken: BranchTarget::zero(),
2203
- kind: IntegerCompare {
2204
- kind: IntCC::Equal,
2205
- rs1: tmp.to_reg(),
2206
- rs2: zero_reg(),
2207
- },
2208
- }
2209
- .emit(&[], sink, emit_info, state);
2210
- // check if rs2 is nan.
2211
- Inst::emit_not_nan(tmp, rs2, ty).emit(&[], sink, emit_info, state);
2212
- Inst::CondBr {
2213
- taken: BranchTarget::Label(label_nan),
2214
- not_taken: BranchTarget::zero(),
2215
- kind: IntegerCompare {
2216
- kind: IntCC::Equal,
2217
- rs1: tmp.to_reg(),
2218
- rs2: zero_reg(),
2219
- },
2220
- }
2221
- .emit(&[], sink, emit_info, state);
2222
- // here rs1 and rs2 is not nan.
2223
- Inst::FpuRRR {
2224
- alu_op: op.to_fpuoprrr(ty),
2225
- frm: None,
2226
- rd: rd,
2227
- rs1: rs1,
2228
- rs2: rs2,
2229
- }
2230
- .emit(&[], sink, emit_info, state);
2231
- // special handle for +0 or -0.
2232
- {
2233
- // check is rs1 and rs2 all equal to zero.
2234
- let label_done = sink.get_label();
2235
- {
2236
- // if rs1 == 0
2237
- let mut insts = Inst::emit_if_float_not_zero(
2238
- tmp,
2239
- rs1,
2240
- ty,
2241
- BranchTarget::Label(label_done),
2242
- BranchTarget::zero(),
2243
- );
2244
- insts.extend(Inst::emit_if_float_not_zero(
2245
- tmp,
2246
- rs2,
2247
- ty,
2248
- BranchTarget::Label(label_done),
2249
- BranchTarget::zero(),
2250
- ));
2251
- insts
2252
- .iter()
2253
- .for_each(|i| i.emit(&[], sink, emit_info, state));
2254
- }
2255
- Inst::FpuRR {
2256
- alu_op: FpuOPRR::move_f_to_x_op(ty),
2257
- frm: None,
2258
- rd: tmp,
2259
- rs: rs1,
2260
- }
2261
- .emit(&[], sink, emit_info, state);
2262
- Inst::FpuRR {
2263
- alu_op: FpuOPRR::move_f_to_x_op(ty),
2264
- frm: None,
2265
- rd: writable_spilltmp_reg(),
2266
- rs: rs2,
2267
- }
2268
- .emit(&[], sink, emit_info, state);
2269
- Inst::AluRRR {
2270
- alu_op: if op == FloatSelectOP::Max {
2271
- AluOPRRR::And
2272
- } else {
2273
- AluOPRRR::Or
2274
- },
2275
- rd: tmp,
2276
- rs1: tmp.to_reg(),
2277
- rs2: spilltmp_reg(),
2278
- }
2279
- .emit(&[], sink, emit_info, state);
2280
- // move back to rd.
2281
- Inst::FpuRR {
2282
- alu_op: FpuOPRR::move_x_to_f_op(ty),
2283
- frm: None,
2284
- rd,
2285
- rs: tmp.to_reg(),
2286
- }
2287
- .emit(&[], sink, emit_info, state);
2288
- //
2289
- sink.bind_label(label_done, &mut state.ctrl_plane);
2290
- }
2291
- // we have the reuslt,jump over.
2292
- Inst::Jal {
2293
- dest: BranchTarget::Label(label_jump_over),
2294
- }
2295
- .emit(&[], sink, emit_info, state);
2296
- // here is nan.
2297
- sink.bind_label(label_nan, &mut state.ctrl_plane);
2298
- op.snan_bits(tmp, ty)
2299
- .into_iter()
2300
- .for_each(|i| i.emit(&[], sink, emit_info, state));
2301
- // move to rd.
2302
- Inst::FpuRR {
2303
- alu_op: FpuOPRR::move_x_to_f_op(ty),
2304
- frm: None,
2305
- rd,
2306
- rs: tmp.to_reg(),
2307
- }
2308
- .emit(&[], sink, emit_info, state);
2309
- sink.bind_label(label_jump_over, &mut state.ctrl_plane);
2310
- }
2311
- &Inst::Popcnt {
2312
- sum,
2313
- tmp,
2314
- step,
2315
- rs,
2316
- ty,
2317
- } => {
2318
- let rs = allocs.next(rs);
2319
- let tmp = allocs.next_writable(tmp);
2320
- let step = allocs.next_writable(step);
2321
- let sum = allocs.next_writable(sum);
2322
- // load 0 to sum , init.
2323
- Inst::gen_move(sum, zero_reg(), I64).emit(&[], sink, emit_info, state);
2324
- // load
2325
- Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
2326
- &[],
2327
- sink,
2328
- emit_info,
2329
- state,
2330
- );
2331
- //
2332
- Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
2333
- Inst::AluRRImm12 {
2334
- alu_op: AluOPRRI::Slli,
2335
- rd: tmp,
2336
- rs: tmp.to_reg(),
2337
- imm12: Imm12::from_bits((ty.bits() - 1) as i16),
2338
- }
2339
- .emit(&[], sink, emit_info, state);
2340
- let label_done = sink.get_label();
2341
- let label_loop = sink.get_label();
2342
- sink.bind_label(label_loop, &mut state.ctrl_plane);
2343
- Inst::CondBr {
2344
- taken: BranchTarget::Label(label_done),
2345
- not_taken: BranchTarget::zero(),
2346
- kind: IntegerCompare {
2347
- kind: IntCC::SignedLessThanOrEqual,
2348
- rs1: step.to_reg(),
2349
- rs2: zero_reg(),
2350
- },
2351
- }
2352
- .emit(&[], sink, emit_info, state);
2353
- // test and add sum.
2354
- {
2355
- Inst::AluRRR {
2356
- alu_op: AluOPRRR::And,
2357
- rd: writable_spilltmp_reg2(),
2358
- rs1: tmp.to_reg(),
2359
- rs2: rs,
2360
- }
2361
- .emit(&[], sink, emit_info, state);
2362
- let label_over = sink.get_label();
2363
- Inst::CondBr {
2364
- taken: BranchTarget::Label(label_over),
2365
- not_taken: BranchTarget::zero(),
2366
- kind: IntegerCompare {
2367
- kind: IntCC::Equal,
2368
- rs1: zero_reg(),
2369
- rs2: spilltmp_reg2(),
2370
- },
2371
- }
2372
- .emit(&[], sink, emit_info, state);
2373
- Inst::AluRRImm12 {
2374
- alu_op: AluOPRRI::Addi,
2375
- rd: sum,
2376
- rs: sum.to_reg(),
2377
- imm12: Imm12::from_bits(1),
2378
- }
2379
- .emit(&[], sink, emit_info, state);
2380
- sink.bind_label(label_over, &mut state.ctrl_plane);
2381
- }
2382
- // set step and tmp.
2383
- {
2384
- Inst::AluRRImm12 {
2385
- alu_op: AluOPRRI::Addi,
2386
- rd: step,
2387
- rs: step.to_reg(),
2388
- imm12: Imm12::from_bits(-1),
2389
- }
2390
- .emit(&[], sink, emit_info, state);
2391
- Inst::AluRRImm12 {
2392
- alu_op: AluOPRRI::Srli,
2393
- rd: tmp,
2394
- rs: tmp.to_reg(),
2395
- imm12: Imm12::from_bits(1),
2396
- }
2397
- .emit(&[], sink, emit_info, state);
2398
- Inst::Jal {
2399
- dest: BranchTarget::Label(label_loop),
2400
- }
2401
- .emit(&[], sink, emit_info, state);
2402
- }
2403
- sink.bind_label(label_done, &mut state.ctrl_plane);
2404
- }
2405
- &Inst::Rev8 { rs, rd, tmp, step } => {
2406
- let rs = allocs.next(rs);
2407
- let tmp = allocs.next_writable(tmp);
2408
- let step = allocs.next_writable(step);
2409
- let rd = allocs.next_writable(rd);
2410
- // init.
2411
- Inst::gen_move(rd, zero_reg(), I64).emit(&[], sink, emit_info, state);
2412
- Inst::gen_move(tmp, rs, I64).emit(&[], sink, emit_info, state);
2413
- // load 56 to step.
2414
- Inst::load_imm12(step, Imm12::from_bits(56)).emit(&[], sink, emit_info, state);
2415
- let label_done = sink.get_label();
2416
- let label_loop = sink.get_label();
2417
- sink.bind_label(label_loop, &mut state.ctrl_plane);
2418
- Inst::CondBr {
2419
- taken: BranchTarget::Label(label_done),
2420
- not_taken: BranchTarget::zero(),
2421
- kind: IntegerCompare {
2422
- kind: IntCC::SignedLessThan,
2423
- rs1: step.to_reg(),
2424
- rs2: zero_reg(),
2425
- },
2426
- }
2427
- .emit(&[], sink, emit_info, state);
2428
- Inst::AluRRImm12 {
2429
- alu_op: AluOPRRI::Andi,
2430
- rd: writable_spilltmp_reg(),
2431
- rs: tmp.to_reg(),
2432
- imm12: Imm12::from_bits(255),
2433
- }
2434
- .emit(&[], sink, emit_info, state);
2435
- Inst::AluRRR {
2436
- alu_op: AluOPRRR::Sll,
2437
- rd: writable_spilltmp_reg(),
2438
- rs1: spilltmp_reg(),
2439
- rs2: step.to_reg(),
2440
- }
2441
- .emit(&[], sink, emit_info, state);
2442
-
2443
- Inst::AluRRR {
2444
- alu_op: AluOPRRR::Or,
2445
- rd: rd,
2446
- rs1: rd.to_reg(),
2447
- rs2: spilltmp_reg(),
2448
- }
2449
- .emit(&[], sink, emit_info, state);
2450
- {
2451
- // reset step
2452
- Inst::AluRRImm12 {
2453
- alu_op: AluOPRRI::Addi,
2454
- rd: step,
2455
- rs: step.to_reg(),
2456
- imm12: Imm12::from_bits(-8),
2457
- }
2458
- .emit(&[], sink, emit_info, state);
2459
- //reset tmp.
2460
- Inst::AluRRImm12 {
2461
- alu_op: AluOPRRI::Srli,
2462
- rd: tmp,
2463
- rs: tmp.to_reg(),
2464
- imm12: Imm12::from_bits(8),
2465
- }
2466
- .emit(&[], sink, emit_info, state);
2467
- // loop.
2468
- Inst::Jal {
2469
- dest: BranchTarget::Label(label_loop),
2470
- }
2471
- }
2472
- .emit(&[], sink, emit_info, state);
2473
- sink.bind_label(label_done, &mut state.ctrl_plane);
2474
- }
2475
- &Inst::Cltz {
2476
- sum,
2477
- tmp,
2478
- step,
2479
- rs,
2480
- leading,
2481
- ty,
2482
- } => {
2483
- let rs = allocs.next(rs);
2484
- let tmp = allocs.next_writable(tmp);
2485
- let step = allocs.next_writable(step);
2486
- let sum = allocs.next_writable(sum);
2487
- // load 0 to sum , init.
2488
- Inst::gen_move(sum, zero_reg(), I64).emit(&[], sink, emit_info, state);
2489
- // load
2490
- Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
2491
- &[],
2492
- sink,
2493
- emit_info,
2494
- state,
2495
- );
2496
- //
2497
- Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
2498
- if leading {
2499
- Inst::AluRRImm12 {
2500
- alu_op: AluOPRRI::Slli,
2501
- rd: tmp,
2502
- rs: tmp.to_reg(),
2503
- imm12: Imm12::from_bits((ty.bits() - 1) as i16),
2504
- }
2505
- .emit(&[], sink, emit_info, state);
2506
- }
2507
- let label_done = sink.get_label();
2508
- let label_loop = sink.get_label();
2509
- sink.bind_label(label_loop, &mut state.ctrl_plane);
2510
- Inst::CondBr {
2511
- taken: BranchTarget::Label(label_done),
2512
- not_taken: BranchTarget::zero(),
2513
- kind: IntegerCompare {
2514
- kind: IntCC::SignedLessThanOrEqual,
2515
- rs1: step.to_reg(),
2516
- rs2: zero_reg(),
2517
- },
2518
- }
2519
- .emit(&[], sink, emit_info, state);
2520
- // test and add sum.
2521
- {
2522
- Inst::AluRRR {
2523
- alu_op: AluOPRRR::And,
2524
- rd: writable_spilltmp_reg2(),
2525
- rs1: tmp.to_reg(),
2526
- rs2: rs,
2527
- }
2528
- .emit(&[], sink, emit_info, state);
2529
- Inst::CondBr {
2530
- taken: BranchTarget::Label(label_done),
2531
- not_taken: BranchTarget::zero(),
2532
- kind: IntegerCompare {
2533
- kind: IntCC::NotEqual,
2534
- rs1: zero_reg(),
2535
- rs2: spilltmp_reg2(),
2536
- },
2537
- }
2538
- .emit(&[], sink, emit_info, state);
2539
- Inst::AluRRImm12 {
2540
- alu_op: AluOPRRI::Addi,
2541
- rd: sum,
2542
- rs: sum.to_reg(),
2543
- imm12: Imm12::from_bits(1),
2544
- }
2545
- .emit(&[], sink, emit_info, state);
2546
- }
2547
- // set step and tmp.
2548
- {
2549
- Inst::AluRRImm12 {
2550
- alu_op: AluOPRRI::Addi,
2551
- rd: step,
2552
- rs: step.to_reg(),
2553
- imm12: Imm12::from_bits(-1),
2554
- }
2555
- .emit(&[], sink, emit_info, state);
2556
- Inst::AluRRImm12 {
2557
- alu_op: if leading {
2558
- AluOPRRI::Srli
2559
- } else {
2560
- AluOPRRI::Slli
2561
- },
2562
- rd: tmp,
2563
- rs: tmp.to_reg(),
2564
- imm12: Imm12::from_bits(1),
2565
- }
2566
- .emit(&[], sink, emit_info, state);
2567
- Inst::Jal {
2568
- dest: BranchTarget::Label(label_loop),
2569
- }
2570
- .emit(&[], sink, emit_info, state);
2571
- }
2572
- sink.bind_label(label_done, &mut state.ctrl_plane);
2573
- }
2574
- &Inst::Brev8 {
2575
- rs,
2576
- ty,
2577
- step,
2578
- tmp,
2579
- tmp2,
2580
- rd,
2581
- } => {
2582
- let rs = allocs.next(rs);
2583
- let step = allocs.next_writable(step);
2584
- let tmp = allocs.next_writable(tmp);
2585
- let tmp2 = allocs.next_writable(tmp2);
2586
- let rd = allocs.next_writable(rd);
2587
- Inst::gen_move(rd, zero_reg(), I64).emit(&[], sink, emit_info, state);
2588
- Inst::load_imm12(step, Imm12::from_bits(ty.bits() as i16)).emit(
2589
- &[],
2590
- sink,
2591
- emit_info,
2592
- state,
2593
- );
2594
- //
2595
- Inst::load_imm12(tmp, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
2596
- Inst::AluRRImm12 {
2597
- alu_op: AluOPRRI::Slli,
2598
- rd: tmp,
2599
- rs: tmp.to_reg(),
2600
- imm12: Imm12::from_bits((ty.bits() - 1) as i16),
2601
- }
2602
- .emit(&[], sink, emit_info, state);
2603
- Inst::load_imm12(tmp2, Imm12::from_bits(1)).emit(&[], sink, emit_info, state);
2604
- Inst::AluRRImm12 {
2605
- alu_op: AluOPRRI::Slli,
2606
- rd: tmp2,
2607
- rs: tmp2.to_reg(),
2608
- imm12: Imm12::from_bits((ty.bits() - 8) as i16),
2609
- }
2610
- .emit(&[], sink, emit_info, state);
2611
-
2612
- let label_done = sink.get_label();
2613
- let label_loop = sink.get_label();
2614
- sink.bind_label(label_loop, &mut state.ctrl_plane);
2615
- Inst::CondBr {
2616
- taken: BranchTarget::Label(label_done),
2617
- not_taken: BranchTarget::zero(),
2618
- kind: IntegerCompare {
2619
- kind: IntCC::SignedLessThanOrEqual,
2620
- rs1: step.to_reg(),
2621
- rs2: zero_reg(),
2622
- },
2623
- }
2624
- .emit(&[], sink, emit_info, state);
2625
- // test and set bit.
2626
- {
2627
- Inst::AluRRR {
2628
- alu_op: AluOPRRR::And,
2629
- rd: writable_spilltmp_reg2(),
2630
- rs1: tmp.to_reg(),
2631
- rs2: rs,
2632
- }
2633
- .emit(&[], sink, emit_info, state);
2634
- let label_over = sink.get_label();
2635
- Inst::CondBr {
2636
- taken: BranchTarget::Label(label_over),
2637
- not_taken: BranchTarget::zero(),
2638
- kind: IntegerCompare {
2639
- kind: IntCC::Equal,
2640
- rs1: zero_reg(),
2641
- rs2: spilltmp_reg2(),
2642
- },
2643
- }
2644
- .emit(&[], sink, emit_info, state);
2645
- Inst::AluRRR {
2646
- alu_op: AluOPRRR::Or,
2647
- rd: rd,
2648
- rs1: rd.to_reg(),
2649
- rs2: tmp2.to_reg(),
2650
- }
2651
- .emit(&[], sink, emit_info, state);
2652
- sink.bind_label(label_over, &mut state.ctrl_plane);
2653
- }
2654
- // set step and tmp.
2655
- {
2656
- Inst::AluRRImm12 {
2657
- alu_op: AluOPRRI::Addi,
2658
- rd: step,
2659
- rs: step.to_reg(),
2660
- imm12: Imm12::from_bits(-1),
2661
- }
2662
- .emit(&[], sink, emit_info, state);
2663
- Inst::AluRRImm12 {
2664
- alu_op: AluOPRRI::Srli,
2665
- rd: tmp,
2666
- rs: tmp.to_reg(),
2667
- imm12: Imm12::from_bits(1),
2668
- }
2669
- .emit(&[], sink, emit_info, state);
2670
- {
2671
- // reset tmp2
2672
- // if (step %=8 == 0) then tmp2 = tmp2 >> 15
2673
- // if (step %=8 != 0) then tmp2 = tmp2 << 1
2674
- let label_over = sink.get_label();
2675
- let label_sll_1 = sink.get_label();
2676
- Inst::load_imm12(writable_spilltmp_reg2(), Imm12::from_bits(8)).emit(
2677
- &[],
2678
- sink,
2679
- emit_info,
2680
- state,
2681
- );
2682
- Inst::AluRRR {
2683
- alu_op: AluOPRRR::Rem,
2684
- rd: writable_spilltmp_reg2(),
2685
- rs1: step.to_reg(),
2686
- rs2: spilltmp_reg2(),
2687
- }
2688
- .emit(&[], sink, emit_info, state);
2689
- Inst::CondBr {
2690
- taken: BranchTarget::Label(label_sll_1),
2691
- not_taken: BranchTarget::zero(),
2692
- kind: IntegerCompare {
2693
- kind: IntCC::NotEqual,
2694
- rs1: spilltmp_reg2(),
2695
- rs2: zero_reg(),
2696
- },
2697
- }
2698
- .emit(&[], sink, emit_info, state);
2699
- Inst::AluRRImm12 {
2700
- alu_op: AluOPRRI::Srli,
2701
- rd: tmp2,
2702
- rs: tmp2.to_reg(),
2703
- imm12: Imm12::from_bits(15),
2704
- }
2705
- .emit(&[], sink, emit_info, state);
2706
- Inst::Jal {
2707
- dest: BranchTarget::Label(label_over),
2708
- }
2709
- .emit(&[], sink, emit_info, state);
2710
- sink.bind_label(label_sll_1, &mut state.ctrl_plane);
2711
- Inst::AluRRImm12 {
2712
- alu_op: AluOPRRI::Slli,
2713
- rd: tmp2,
2714
- rs: tmp2.to_reg(),
2715
- imm12: Imm12::from_bits(1),
2716
- }
2717
- .emit(&[], sink, emit_info, state);
2718
- sink.bind_label(label_over, &mut state.ctrl_plane);
2719
- }
2720
- Inst::Jal {
2721
- dest: BranchTarget::Label(label_loop),
2722
- }
2723
- .emit(&[], sink, emit_info, state);
2724
- }
2725
- sink.bind_label(label_done, &mut state.ctrl_plane);
2726
- }
2727
- &Inst::StackProbeLoop {
2728
- guard_size,
2729
- probe_count,
2730
- tmp: guard_size_tmp,
2731
- } => {
2732
- let step = writable_spilltmp_reg();
2733
- Inst::load_constant_u64(
2734
- step,
2735
- (guard_size as u64) * (probe_count as u64),
2736
- &mut |_| step,
2737
- )
2738
- .iter()
2739
- .for_each(|i| i.emit(&[], sink, emit_info, state));
2740
- Inst::load_constant_u64(guard_size_tmp, guard_size as u64, &mut |_| guard_size_tmp)
2741
- .iter()
2742
- .for_each(|i| i.emit(&[], sink, emit_info, state));
2743
-
2744
- let loop_start = sink.get_label();
2745
- let label_done = sink.get_label();
2746
- sink.bind_label(loop_start, &mut state.ctrl_plane);
2747
- Inst::CondBr {
2748
- taken: BranchTarget::Label(label_done),
2749
- not_taken: BranchTarget::zero(),
2750
- kind: IntegerCompare {
2751
- kind: IntCC::UnsignedLessThanOrEqual,
2752
- rs1: step.to_reg(),
2753
- rs2: guard_size_tmp.to_reg(),
2754
- },
2755
- }
2756
- .emit(&[], sink, emit_info, state);
2757
- // compute address.
2758
- Inst::AluRRR {
2759
- alu_op: AluOPRRR::Sub,
2760
- rd: writable_spilltmp_reg2(),
2761
- rs1: stack_reg(),
2762
- rs2: step.to_reg(),
2763
- }
2764
- .emit(&[], sink, emit_info, state);
2765
- Inst::Store {
2766
- to: AMode::RegOffset(spilltmp_reg2(), 0, I8),
2767
- op: StoreOP::Sb,
2768
- flags: MemFlags::new(),
2769
- src: zero_reg(),
2770
- }
2771
- .emit(&[], sink, emit_info, state);
2772
- // reset step.
2773
- Inst::AluRRR {
2774
- alu_op: AluOPRRR::Sub,
2775
- rd: step,
2776
- rs1: step.to_reg(),
2777
- rs2: guard_size_tmp.to_reg(),
2778
- }
2779
- .emit(&[], sink, emit_info, state);
2780
- Inst::Jal {
2781
- dest: BranchTarget::Label(loop_start),
2782
- }
2783
- .emit(&[], sink, emit_info, state);
2784
- sink.bind_label(label_done, &mut state.ctrl_plane);
2785
- }
2786
- &Inst::VecAluRRR {
2787
- op, vd, vs1, vs2, ..
2788
- } => {
2789
- let vs1 = allocs.next(vs1);
2790
- let vs2 = allocs.next(vs2);
2791
- let vd = allocs.next_writable(vd);
2792
-
2793
- sink.put4(encode_valu(op, vd, vs1, vs2, VecOpMasking::Disabled));
2794
- }
2795
- &Inst::VecAluRRImm5 {
2796
- op, vd, imm, vs2, ..
2797
- } => {
2798
- let vs2 = allocs.next(vs2);
2799
- let vd = allocs.next_writable(vd);
2800
-
2801
- sink.put4(encode_valu_imm(op, vd, imm, vs2, VecOpMasking::Disabled));
2802
- }
2803
- &Inst::VecSetState { rd, ref vstate } => {
2804
- let rd = allocs.next_writable(rd);
2805
-
2806
- sink.put4(encode_vcfg_imm(
2807
- 0x57,
2808
- rd.to_reg(),
2809
- vstate.avl.unwrap_static(),
2810
- &vstate.vtype,
2811
- ));
2812
-
2813
- // Update the current vector emit state.
2814
- state.vstate = EmitVState::Known(vstate.clone());
2815
- }
2816
-
2817
- &Inst::VecLoad {
2818
- eew,
2819
- to,
2820
- ref from,
2821
- flags,
2822
- ..
2823
- } => {
2824
- let offset = from.get_offset_with_state(state);
2825
- let from_reg = allocs.next(from.get_base_register());
2826
- let to = allocs.next_writable(to);
2827
-
2828
- // Vector Loads don't support immediate offsets, so we need to load it into a register.
2829
- let addr = writable_spilltmp_reg();
2830
- LoadConstant::U64(offset as u64)
2831
- .load_constant_and_add(addr, from_reg)
2832
- .into_iter()
2833
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
2834
-
2835
- let srcloc = state.cur_srcloc();
2836
- if !srcloc.is_default() && !flags.notrap() {
2837
- // Register the offset at which the actual load instruction starts.
2838
- sink.add_trap(TrapCode::HeapOutOfBounds);
2839
- }
2840
-
2841
- sink.put4(encode_vmem_load(
2842
- 0x07,
2843
- to.to_reg(),
2844
- eew,
2845
- addr.to_reg(),
2846
- from.lumop(),
2847
- // We don't implement masking yet.
2848
- VecOpMasking::Disabled,
2849
- from.mop(),
2850
- from.nf(),
2851
- ));
2852
- }
2853
-
2854
- &Inst::VecStore {
2855
- eew,
2856
- ref to,
2857
- from,
2858
- flags,
2859
- ..
2860
- } => {
2861
- let offset = to.get_offset_with_state(state);
2862
- let to_reg = allocs.next(to.get_base_register());
2863
- let from = allocs.next(from);
2864
-
2865
- // Vector Stores don't support immediate offsets, so we need to load it into a register.
2866
- let addr = writable_spilltmp_reg();
2867
- LoadConstant::U64(offset as u64)
2868
- .load_constant_and_add(addr, to_reg)
2869
- .into_iter()
2870
- .for_each(|inst| inst.emit(&[], sink, emit_info, state));
2871
-
2872
- let srcloc = state.cur_srcloc();
2873
- if !srcloc.is_default() && !flags.notrap() {
2874
- // Register the offset at which the actual load instruction starts.
2875
- sink.add_trap(TrapCode::HeapOutOfBounds);
2876
- }
2877
-
2878
- sink.put4(encode_vmem_store(
2879
- 0x27,
2880
- from,
2881
- eew,
2882
- addr.to_reg(),
2883
- to.sumop(),
2884
- // We don't implement masking yet.
2885
- VecOpMasking::Disabled,
2886
- to.mop(),
2887
- to.nf(),
2888
- ));
2889
- }
2890
- };
2891
- let end_off = sink.cur_offset();
2892
- assert!(
2893
- (end_off - start_off) <= Inst::worst_case_size(),
2894
- "Inst:{:?} length:{} worst_case_size:{}",
2895
- self,
2896
- end_off - start_off,
2897
- Inst::worst_case_size()
2898
- );
2899
- }
2900
-
2901
- fn pretty_print_inst(&self, allocs: &[Allocation], state: &mut Self::State) -> String {
2902
- let mut allocs = AllocationConsumer::new(allocs);
2903
- self.print_with_state(state, &mut allocs)
2904
- }
2905
- }
2906
-
2907
- // helper function.
2908
- fn alloc_value_regs(orgin: &ValueRegs<Reg>, alloc: &mut AllocationConsumer) -> ValueRegs<Reg> {
2909
- match orgin.regs().len() {
2910
- 1 => ValueRegs::one(alloc.next(orgin.regs()[0])),
2911
- 2 => ValueRegs::two(alloc.next(orgin.regs()[0]), alloc.next(orgin.regs()[1])),
2912
- _ => unreachable!(),
2913
- }
2914
- }