wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,3938 +0,0 @@
1
- use crate::binemit::{Addend, Reloc};
2
- use crate::ir::immediates::{Ieee32, Ieee64};
3
- use crate::ir::TrapCode;
4
- use crate::ir::{KnownSymbol, LibCall};
5
- use crate::isa::x64::encoding::evex::{EvexInstruction, EvexVectorLength};
6
- use crate::isa::x64::encoding::rex::{
7
- emit_simm, emit_std_enc_enc, emit_std_enc_mem, emit_std_reg_mem, emit_std_reg_reg, int_reg_enc,
8
- low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, OpcodeMap,
9
- RexFlags,
10
- };
11
- use crate::isa::x64::encoding::vex::{RegisterOrAmode, VexInstruction, VexVectorLength};
12
- use crate::isa::x64::inst::args::*;
13
- use crate::isa::x64::inst::*;
14
- use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel, Reg, Writable};
15
- use core::convert::TryInto;
16
-
17
- /// A small helper to generate a signed conversion instruction.
18
- fn emit_signed_cvt(
19
- sink: &mut MachBuffer<Inst>,
20
- info: &EmitInfo,
21
- state: &mut EmitState,
22
- // Required to be RealRegs.
23
- src: Reg,
24
- dst: Writable<Reg>,
25
- to_f64: bool,
26
- ) {
27
- // Handle an unsigned int, which is the "easy" case: a signed conversion will do the
28
- // right thing.
29
- let op = if to_f64 {
30
- SseOpcode::Cvtsi2sd
31
- } else {
32
- SseOpcode::Cvtsi2ss
33
- };
34
- let inst = Inst::gpr_to_xmm(op, RegMem::reg(src), OperandSize::Size64, dst);
35
- inst.emit(&[], sink, info, state);
36
- }
37
-
38
- /// Emits a one way conditional jump if CC is set (true).
39
- fn one_way_jmp(sink: &mut MachBuffer<Inst>, cc: CC, label: MachLabel) {
40
- let cond_start = sink.cur_offset();
41
- let cond_disp_off = cond_start + 2;
42
- sink.use_label_at_offset(cond_disp_off, label, LabelUse::JmpRel32);
43
- sink.put1(0x0F);
44
- sink.put1(0x80 + cc.get_enc());
45
- sink.put4(0x0);
46
- }
47
-
48
- /// Emits a relocation, attaching the current source location as well.
49
- fn emit_reloc(sink: &mut MachBuffer<Inst>, kind: Reloc, name: &ExternalName, addend: Addend) {
50
- sink.add_reloc(kind, name, addend);
51
- }
52
-
53
- /// The top-level emit function.
54
- ///
55
- /// Important! Do not add improved (shortened) encoding cases to existing
56
- /// instructions without also adding tests for those improved encodings. That
57
- /// is a dangerous game that leads to hard-to-track-down errors in the emitted
58
- /// code.
59
- ///
60
- /// For all instructions, make sure to have test coverage for all of the
61
- /// following situations. Do this by creating the cross product resulting from
62
- /// applying the following rules to each operand:
63
- ///
64
- /// (1) for any insn that mentions a register: one test using a register from
65
- /// the group [rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi] and a second one
66
- /// using a register from the group [r8, r9, r10, r11, r12, r13, r14, r15].
67
- /// This helps detect incorrect REX prefix construction.
68
- ///
69
- /// (2) for any insn that mentions a byte register: one test for each of the
70
- /// four encoding groups [al, cl, dl, bl], [spl, bpl, sil, dil],
71
- /// [r8b .. r11b] and [r12b .. r15b]. This checks that
72
- /// apparently-redundant REX prefixes are retained when required.
73
- ///
74
- /// (3) for any insn that contains an immediate field, check the following
75
- /// cases: field is zero, field is in simm8 range (-128 .. 127), field is
76
- /// in simm32 range (-0x8000_0000 .. 0x7FFF_FFFF). This is because some
77
- /// instructions that require a 32-bit immediate have a short-form encoding
78
- /// when the imm is in simm8 range.
79
- ///
80
- /// Rules (1), (2) and (3) don't apply for registers within address expressions
81
- /// (`Addr`s). Those are already pretty well tested, and the registers in them
82
- /// don't have any effect on the containing instruction (apart from possibly
83
- /// require REX prefix bits).
84
- ///
85
- /// When choosing registers for a test, avoid using registers with the same
86
- /// offset within a given group. For example, don't use rax and r8, since they
87
- /// both have the lowest 3 bits as 000, and so the test won't detect errors
88
- /// where those 3-bit register sub-fields are confused by the emitter. Instead
89
- /// use (eg) rax (lo3 = 000) and r9 (lo3 = 001). Similarly, don't use (eg) cl
90
- /// and bpl since they have the same offset in their group; use instead (eg) cl
91
- /// and sil.
92
- ///
93
- /// For all instructions, also add a test that uses only low-half registers
94
- /// (rax .. rdi, xmm0 .. xmm7) etc, so as to check that any redundant REX
95
- /// prefixes are correctly omitted. This low-half restriction must apply to
96
- /// _all_ registers in the insn, even those in address expressions.
97
- ///
98
- /// Following these rules creates large numbers of test cases, but it's the
99
- /// only way to make the emitter reliable.
100
- ///
101
- /// Known possible improvements:
102
- ///
103
- /// * there's a shorter encoding for shl/shr/sar by a 1-bit immediate. (Do we
104
- /// care?)
105
- pub(crate) fn emit(
106
- inst: &Inst,
107
- allocs: &mut AllocationConsumer<'_>,
108
- sink: &mut MachBuffer<Inst>,
109
- info: &EmitInfo,
110
- state: &mut EmitState,
111
- ) {
112
- let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
113
- match iset_requirement {
114
- // Cranelift assumes SSE2 at least.
115
- InstructionSet::SSE | InstructionSet::SSE2 => true,
116
- InstructionSet::SSSE3 => info.isa_flags.use_ssse3(),
117
- InstructionSet::SSE41 => info.isa_flags.use_sse41(),
118
- InstructionSet::SSE42 => info.isa_flags.use_sse42(),
119
- InstructionSet::Popcnt => info.isa_flags.use_popcnt(),
120
- InstructionSet::Lzcnt => info.isa_flags.use_lzcnt(),
121
- InstructionSet::BMI1 => info.isa_flags.use_bmi1(),
122
- InstructionSet::BMI2 => info.isa_flags.has_bmi2(),
123
- InstructionSet::FMA => info.isa_flags.has_fma(),
124
- InstructionSet::AVX => info.isa_flags.has_avx(),
125
- InstructionSet::AVX2 => info.isa_flags.has_avx2(),
126
- InstructionSet::AVX512BITALG => info.isa_flags.has_avx512bitalg(),
127
- InstructionSet::AVX512DQ => info.isa_flags.has_avx512dq(),
128
- InstructionSet::AVX512F => info.isa_flags.has_avx512f(),
129
- InstructionSet::AVX512VBMI => info.isa_flags.has_avx512vbmi(),
130
- InstructionSet::AVX512VL => info.isa_flags.has_avx512vl(),
131
- }
132
- };
133
-
134
- // Certain instructions may be present in more than one ISA feature set; we must at least match
135
- // one of them in the target CPU.
136
- let isa_requirements = inst.available_in_any_isa();
137
- if !isa_requirements.is_empty() && !isa_requirements.iter().all(matches_isa_flags) {
138
- panic!(
139
- "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
140
- inst, isa_requirements
141
- )
142
- }
143
-
144
- match inst {
145
- Inst::AluRmiR {
146
- size,
147
- op,
148
- src1,
149
- src2,
150
- dst: reg_g,
151
- } => {
152
- let src1 = allocs.next(src1.to_reg());
153
- let reg_g = allocs.next(reg_g.to_reg().to_reg());
154
- debug_assert_eq!(src1, reg_g);
155
- let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
156
-
157
- let prefix = if *size == OperandSize::Size16 {
158
- LegacyPrefixes::_66
159
- } else {
160
- LegacyPrefixes::None
161
- };
162
-
163
- let mut rex = RexFlags::from(*size);
164
- if *op == AluRmiROpcode::Mul {
165
- // We kinda freeloaded Mul into RMI_R_Op, but it doesn't fit the usual pattern, so
166
- // we have to special-case it.
167
- if *size == OperandSize::Size8 {
168
- match src2 {
169
- RegMemImm::Reg { reg: reg_e } => {
170
- debug_assert!(reg_e.is_real());
171
- rex.always_emit_if_8bit_needed(reg_e);
172
- let enc_e = int_reg_enc(reg_e);
173
- emit_std_enc_enc(sink, LegacyPrefixes::None, 0xF6, 1, 5, enc_e, rex);
174
- }
175
-
176
- RegMemImm::Mem { addr } => {
177
- let amode = addr.finalize(state, sink);
178
- emit_std_enc_mem(
179
- sink,
180
- LegacyPrefixes::None,
181
- 0xF6,
182
- 1,
183
- 5,
184
- &amode,
185
- rex,
186
- 0,
187
- );
188
- }
189
-
190
- RegMemImm::Imm { .. } => {
191
- panic!("Cannot emit 8bit imul with 8bit immediate");
192
- }
193
- }
194
- } else {
195
- match src2 {
196
- RegMemImm::Reg { reg: reg_e } => {
197
- emit_std_reg_reg(sink, prefix, 0x0FAF, 2, reg_g, reg_e, rex);
198
- }
199
-
200
- RegMemImm::Mem { addr } => {
201
- let amode = addr.finalize(state, sink);
202
- emit_std_reg_mem(sink, prefix, 0x0FAF, 2, reg_g, &amode, rex, 0);
203
- }
204
-
205
- RegMemImm::Imm { simm32 } => {
206
- let imm_size = if low8_will_sign_extend_to_32(simm32) {
207
- 1
208
- } else {
209
- if *size == OperandSize::Size16 {
210
- 2
211
- } else {
212
- 4
213
- }
214
- };
215
- let opcode = if imm_size == 1 { 0x6B } else { 0x69 };
216
- // Yes, really, reg_g twice.
217
- emit_std_reg_reg(sink, prefix, opcode, 1, reg_g, reg_g, rex);
218
- emit_simm(sink, imm_size, simm32);
219
- }
220
- }
221
- }
222
- } else {
223
- let (opcode_r, opcode_m, subopcode_i) = match op {
224
- AluRmiROpcode::Add => (0x01, 0x03, 0),
225
- AluRmiROpcode::Adc => (0x11, 0x03, 0),
226
- AluRmiROpcode::Sub => (0x29, 0x2B, 5),
227
- AluRmiROpcode::Sbb => (0x19, 0x2B, 5),
228
- AluRmiROpcode::And => (0x21, 0x23, 4),
229
- AluRmiROpcode::Or => (0x09, 0x0B, 1),
230
- AluRmiROpcode::Xor => (0x31, 0x33, 6),
231
- AluRmiROpcode::Mul => panic!("unreachable"),
232
- };
233
-
234
- let (opcode_r, opcode_m) = if *size == OperandSize::Size8 {
235
- (opcode_r - 1, opcode_m - 1)
236
- } else {
237
- (opcode_r, opcode_m)
238
- };
239
-
240
- if *size == OperandSize::Size8 {
241
- debug_assert!(reg_g.is_real());
242
- rex.always_emit_if_8bit_needed(reg_g);
243
- }
244
-
245
- match src2 {
246
- RegMemImm::Reg { reg: reg_e } => {
247
- if *size == OperandSize::Size8 {
248
- debug_assert!(reg_e.is_real());
249
- rex.always_emit_if_8bit_needed(reg_e);
250
- }
251
-
252
- // GCC/llvm use the swapped operand encoding (viz., the R/RM vs RM/R
253
- // duality). Do this too, so as to be able to compare generated machine
254
- // code easily.
255
- emit_std_reg_reg(sink, prefix, opcode_r, 1, reg_e, reg_g, rex);
256
- }
257
-
258
- RegMemImm::Mem { addr } => {
259
- let amode = addr.finalize(state, sink);
260
- // Here we revert to the "normal" G-E ordering.
261
- emit_std_reg_mem(sink, prefix, opcode_m, 1, reg_g, &amode, rex, 0);
262
- }
263
-
264
- RegMemImm::Imm { simm32 } => {
265
- let imm_size = if *size == OperandSize::Size8 {
266
- 1
267
- } else {
268
- if low8_will_sign_extend_to_32(simm32) {
269
- 1
270
- } else {
271
- if *size == OperandSize::Size16 {
272
- 2
273
- } else {
274
- 4
275
- }
276
- }
277
- };
278
-
279
- let opcode = if *size == OperandSize::Size8 {
280
- 0x80
281
- } else if low8_will_sign_extend_to_32(simm32) {
282
- 0x83
283
- } else {
284
- 0x81
285
- };
286
-
287
- // And also here we use the "normal" G-E ordering.
288
- let enc_g = int_reg_enc(reg_g);
289
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode_i, enc_g, rex);
290
- emit_simm(sink, imm_size, simm32);
291
- }
292
- }
293
- }
294
- }
295
-
296
- Inst::AluConstOp { op, size, dst } => {
297
- let dst = allocs.next(dst.to_reg().to_reg());
298
- emit(
299
- &Inst::AluRmiR {
300
- size: *size,
301
- op: *op,
302
- dst: Writable::from_reg(Gpr::new(dst).unwrap()),
303
- src1: Gpr::new(dst).unwrap(),
304
- src2: Gpr::new(dst).unwrap().into(),
305
- },
306
- allocs,
307
- sink,
308
- info,
309
- state,
310
- );
311
- }
312
-
313
- Inst::AluRM {
314
- size,
315
- src1_dst,
316
- src2,
317
- op,
318
- } => {
319
- let src2 = allocs.next(src2.to_reg());
320
- let src1_dst = src1_dst.finalize(state, sink).with_allocs(allocs);
321
-
322
- let opcode = match op {
323
- AluRmiROpcode::Add => 0x01,
324
- AluRmiROpcode::Sub => 0x29,
325
- AluRmiROpcode::And => 0x21,
326
- AluRmiROpcode::Or => 0x09,
327
- AluRmiROpcode::Xor => 0x31,
328
- _ => panic!("Unsupported read-modify-write ALU opcode"),
329
- };
330
-
331
- let prefix = if *size == OperandSize::Size16 {
332
- LegacyPrefixes::_66
333
- } else {
334
- LegacyPrefixes::None
335
- };
336
- let opcode = if *size == OperandSize::Size8 {
337
- opcode - 1
338
- } else {
339
- opcode
340
- };
341
-
342
- let mut rex = RexFlags::from(*size);
343
- if *size == OperandSize::Size8 {
344
- debug_assert!(src2.is_real());
345
- rex.always_emit_if_8bit_needed(src2);
346
- }
347
-
348
- let enc_g = int_reg_enc(src2);
349
- emit_std_enc_mem(sink, prefix, opcode, 1, enc_g, &src1_dst, rex, 0);
350
- }
351
-
352
- Inst::AluRmRVex {
353
- size,
354
- op,
355
- dst,
356
- src1,
357
- src2,
358
- } => {
359
- use AluRmROpcode::*;
360
- let dst = allocs.next(dst.to_reg().to_reg());
361
- let src1 = allocs.next(src1.to_reg());
362
- let src2 = allocs.next(src2.to_reg());
363
-
364
- let w = match size {
365
- OperandSize::Size32 => false,
366
- OperandSize::Size64 => true,
367
-
368
- // the other cases would be rejected by isle constructors
369
- _ => unreachable!(),
370
- };
371
-
372
- let opcode = match op {
373
- Andn => 0xf2,
374
- };
375
-
376
- VexInstruction::new()
377
- .map(OpcodeMap::_0F38)
378
- .w(w)
379
- .reg(dst.to_real_reg().unwrap().hw_enc())
380
- .vvvv(src1.to_real_reg().unwrap().hw_enc())
381
- .rm(src2.to_real_reg().unwrap().hw_enc())
382
- .opcode(opcode)
383
- .encode(sink);
384
- }
385
-
386
- Inst::UnaryRmR { size, op, src, dst } => {
387
- let dst = allocs.next(dst.to_reg().to_reg());
388
- let rex_flags = RexFlags::from(*size);
389
- use UnaryRmROpcode::*;
390
- let prefix = match size {
391
- OperandSize::Size16 => match op {
392
- Bsr | Bsf => LegacyPrefixes::_66,
393
- Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_66F3,
394
- },
395
- OperandSize::Size32 | OperandSize::Size64 => match op {
396
- Bsr | Bsf => LegacyPrefixes::None,
397
- Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_F3,
398
- },
399
- _ => unreachable!(),
400
- };
401
-
402
- let (opcode, num_opcodes) = match op {
403
- Bsr => (0x0fbd, 2),
404
- Bsf => (0x0fbc, 2),
405
- Lzcnt => (0x0fbd, 2),
406
- Tzcnt => (0x0fbc, 2),
407
- Popcnt => (0x0fb8, 2),
408
- };
409
-
410
- match src.clone().into() {
411
- RegMem::Reg { reg: src } => {
412
- let src = allocs.next(src);
413
- emit_std_reg_reg(sink, prefix, opcode, num_opcodes, dst, src, rex_flags);
414
- }
415
- RegMem::Mem { addr: src } => {
416
- let amode = src.finalize(state, sink).with_allocs(allocs);
417
- emit_std_reg_mem(sink, prefix, opcode, num_opcodes, dst, &amode, rex_flags, 0);
418
- }
419
- }
420
- }
421
-
422
- Inst::Not { size, src, dst } => {
423
- let src = allocs.next(src.to_reg());
424
- let dst = allocs.next(dst.to_reg().to_reg());
425
- debug_assert_eq!(src, dst);
426
- let rex_flags = RexFlags::from((*size, dst));
427
- let (opcode, prefix) = match size {
428
- OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
429
- OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
430
- OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
431
- OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
432
- };
433
-
434
- let subopcode = 2;
435
- let enc_src = int_reg_enc(dst);
436
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
437
- }
438
-
439
- Inst::Neg { size, src, dst } => {
440
- let src = allocs.next(src.to_reg());
441
- let dst = allocs.next(dst.to_reg().to_reg());
442
- debug_assert_eq!(src, dst);
443
- let rex_flags = RexFlags::from((*size, dst));
444
- let (opcode, prefix) = match size {
445
- OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
446
- OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
447
- OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
448
- OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
449
- };
450
-
451
- let subopcode = 3;
452
- let enc_src = int_reg_enc(dst);
453
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
454
- }
455
-
456
- Inst::Div {
457
- sign,
458
- trap,
459
- divisor,
460
- ..
461
- }
462
- | Inst::Div8 {
463
- sign,
464
- trap,
465
- divisor,
466
- ..
467
- } => {
468
- let divisor = divisor.clone().to_reg_mem().with_allocs(allocs);
469
- let size = match inst {
470
- Inst::Div {
471
- size,
472
- dividend_lo,
473
- dividend_hi,
474
- dst_quotient,
475
- dst_remainder,
476
- ..
477
- } => {
478
- let dividend_lo = allocs.next(dividend_lo.to_reg());
479
- let dividend_hi = allocs.next(dividend_hi.to_reg());
480
- let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
481
- let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
482
- debug_assert_eq!(dividend_lo, regs::rax());
483
- debug_assert_eq!(dividend_hi, regs::rdx());
484
- debug_assert_eq!(dst_quotient, regs::rax());
485
- debug_assert_eq!(dst_remainder, regs::rdx());
486
- *size
487
- }
488
- Inst::Div8 { dividend, dst, .. } => {
489
- let dividend = allocs.next(dividend.to_reg());
490
- let dst = allocs.next(dst.to_reg().to_reg());
491
- debug_assert_eq!(dividend, regs::rax());
492
- debug_assert_eq!(dst, regs::rax());
493
- OperandSize::Size8
494
- }
495
- _ => unreachable!(),
496
- };
497
-
498
- let (opcode, prefix) = match size {
499
- OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
500
- OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
501
- OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
502
- OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
503
- };
504
-
505
- sink.add_trap(*trap);
506
-
507
- let subopcode = match sign {
508
- DivSignedness::Signed => 7,
509
- DivSignedness::Unsigned => 6,
510
- };
511
- match divisor {
512
- RegMem::Reg { reg } => {
513
- let src = int_reg_enc(reg);
514
- emit_std_enc_enc(
515
- sink,
516
- prefix,
517
- opcode,
518
- 1,
519
- subopcode,
520
- src,
521
- RexFlags::from((size, reg)),
522
- )
523
- }
524
- RegMem::Mem { addr: src } => {
525
- let amode = src.finalize(state, sink);
526
- emit_std_enc_mem(
527
- sink,
528
- prefix,
529
- opcode,
530
- 1,
531
- subopcode,
532
- &amode,
533
- RexFlags::from(size),
534
- 0,
535
- );
536
- }
537
- }
538
- }
539
-
540
- Inst::MulHi {
541
- size,
542
- signed,
543
- src1,
544
- src2,
545
- dst_lo,
546
- dst_hi,
547
- } => {
548
- let src1 = allocs.next(src1.to_reg());
549
- let dst_lo = allocs.next(dst_lo.to_reg().to_reg());
550
- let dst_hi = allocs.next(dst_hi.to_reg().to_reg());
551
- debug_assert_eq!(src1, regs::rax());
552
- debug_assert_eq!(dst_lo, regs::rax());
553
- debug_assert_eq!(dst_hi, regs::rdx());
554
-
555
- let rex_flags = RexFlags::from(*size);
556
- let prefix = match size {
557
- OperandSize::Size16 => LegacyPrefixes::_66,
558
- OperandSize::Size32 => LegacyPrefixes::None,
559
- OperandSize::Size64 => LegacyPrefixes::None,
560
- _ => unreachable!(),
561
- };
562
-
563
- let subopcode = if *signed { 5 } else { 4 };
564
- match src2.clone().to_reg_mem() {
565
- RegMem::Reg { reg } => {
566
- let reg = allocs.next(reg);
567
- let src = int_reg_enc(reg);
568
- emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags)
569
- }
570
- RegMem::Mem { addr: src } => {
571
- let amode = src.finalize(state, sink).with_allocs(allocs);
572
- emit_std_enc_mem(sink, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0);
573
- }
574
- }
575
- }
576
-
577
- Inst::UMulLo {
578
- size,
579
- src1,
580
- src2,
581
- dst,
582
- } => {
583
- let src1 = allocs.next(src1.to_reg());
584
- let dst = allocs.next(dst.to_reg().to_reg());
585
- debug_assert_eq!(src1, regs::rax());
586
- debug_assert_eq!(dst, regs::rax());
587
-
588
- let mut rex = RexFlags::from(*size);
589
- let prefix = match size {
590
- OperandSize::Size16 => LegacyPrefixes::_66,
591
- _ => LegacyPrefixes::None,
592
- };
593
-
594
- let opcode = if *size == OperandSize::Size8 {
595
- 0xF6
596
- } else {
597
- 0xF7
598
- };
599
-
600
- match src2.clone().to_reg_mem() {
601
- RegMem::Reg { reg } => {
602
- let reg = allocs.next(reg);
603
- if *size == OperandSize::Size8 {
604
- rex.always_emit_if_8bit_needed(reg);
605
- }
606
- let reg_e = int_reg_enc(reg);
607
- emit_std_enc_enc(sink, prefix, opcode, 1, 4, reg_e, rex);
608
- }
609
- RegMem::Mem { addr: src } => {
610
- let amode = src.finalize(state, sink).with_allocs(allocs);
611
- emit_std_enc_mem(sink, prefix, opcode, 1, 4, &amode, rex, 0);
612
- }
613
- }
614
- }
615
-
616
- Inst::SignExtendData { size, src, dst } => {
617
- let src = allocs.next(src.to_reg());
618
- let dst = allocs.next(dst.to_reg().to_reg());
619
- debug_assert_eq!(src, regs::rax());
620
- if *size == OperandSize::Size8 {
621
- debug_assert_eq!(dst, regs::rax());
622
- } else {
623
- debug_assert_eq!(dst, regs::rdx());
624
- }
625
- match size {
626
- OperandSize::Size8 => {
627
- sink.put1(0x66);
628
- sink.put1(0x98);
629
- }
630
- OperandSize::Size16 => {
631
- sink.put1(0x66);
632
- sink.put1(0x99);
633
- }
634
- OperandSize::Size32 => sink.put1(0x99),
635
- OperandSize::Size64 => {
636
- sink.put1(0x48);
637
- sink.put1(0x99);
638
- }
639
- }
640
- }
641
-
642
- Inst::CheckedSRemSeq { divisor, .. } | Inst::CheckedSRemSeq8 { divisor, .. } => {
643
- let divisor = allocs.next(divisor.to_reg());
644
-
645
- // Validate that the register constraints of the dividend and the
646
- // destination are all as expected.
647
- let (dst, size) = match inst {
648
- Inst::CheckedSRemSeq {
649
- dividend_lo,
650
- dividend_hi,
651
- dst_quotient,
652
- dst_remainder,
653
- size,
654
- ..
655
- } => {
656
- let dividend_lo = allocs.next(dividend_lo.to_reg());
657
- let dividend_hi = allocs.next(dividend_hi.to_reg());
658
- let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
659
- let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
660
- debug_assert_eq!(dividend_lo, regs::rax());
661
- debug_assert_eq!(dividend_hi, regs::rdx());
662
- debug_assert_eq!(dst_quotient, regs::rax());
663
- debug_assert_eq!(dst_remainder, regs::rdx());
664
- (regs::rdx(), *size)
665
- }
666
- Inst::CheckedSRemSeq8 { dividend, dst, .. } => {
667
- let dividend = allocs.next(dividend.to_reg());
668
- let dst = allocs.next(dst.to_reg().to_reg());
669
- debug_assert_eq!(dividend, regs::rax());
670
- debug_assert_eq!(dst, regs::rax());
671
- (regs::rax(), OperandSize::Size8)
672
- }
673
- _ => unreachable!(),
674
- };
675
-
676
- // Generates the following code sequence:
677
- //
678
- // cmp -1 %divisor
679
- // jnz $do_op
680
- //
681
- // ;; for srem, result is 0
682
- // mov #0, %dst
683
- // j $done
684
- //
685
- // $do_op:
686
- // idiv %divisor
687
- //
688
- // $done:
689
-
690
- let do_op = sink.get_label();
691
- let done_label = sink.get_label();
692
-
693
- // Check if the divisor is -1, and if it isn't then immediately
694
- // go to the `idiv`.
695
- let inst = Inst::cmp_rmi_r(size, RegMemImm::imm(0xffffffff), divisor);
696
- inst.emit(&[], sink, info, state);
697
- one_way_jmp(sink, CC::NZ, do_op);
698
-
699
- // ... otherwise the divisor is -1 and the result is always 0. This
700
- // is written to the destination register which will be %rax for
701
- // 8-bit srem and %rdx otherwise.
702
- //
703
- // Note that for 16-to-64-bit srem operations this leaves the
704
- // second destination, %rax, unchanged. This isn't semantically
705
- // correct if a lowering actually tries to use the `dst_quotient`
706
- // output but for srem only the `dst_remainder` output is used for
707
- // now.
708
- let inst = Inst::imm(OperandSize::Size64, 0, Writable::from_reg(dst));
709
- inst.emit(&[], sink, info, state);
710
- let inst = Inst::jmp_known(done_label);
711
- inst.emit(&[], sink, info, state);
712
-
713
- // Here the `idiv` is executed, which is different depending on the
714
- // size
715
- sink.bind_label(do_op, &mut state.ctrl_plane);
716
- let inst = match size {
717
- OperandSize::Size8 => Inst::div8(
718
- DivSignedness::Signed,
719
- TrapCode::IntegerDivisionByZero,
720
- RegMem::reg(divisor),
721
- Gpr::new(regs::rax()).unwrap(),
722
- Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
723
- ),
724
- _ => Inst::div(
725
- size,
726
- DivSignedness::Signed,
727
- TrapCode::IntegerDivisionByZero,
728
- RegMem::reg(divisor),
729
- Gpr::new(regs::rax()).unwrap(),
730
- Gpr::new(regs::rdx()).unwrap(),
731
- Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
732
- Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
733
- ),
734
- };
735
- inst.emit(&[], sink, info, state);
736
-
737
- sink.bind_label(done_label, &mut state.ctrl_plane);
738
- }
739
-
740
- Inst::Imm {
741
- dst_size,
742
- simm64,
743
- dst,
744
- } => {
745
- let dst = allocs.next(dst.to_reg().to_reg());
746
- let enc_dst = int_reg_enc(dst);
747
- if *dst_size == OperandSize::Size64 {
748
- if low32_will_sign_extend_to_64(*simm64) {
749
- // Sign-extended move imm32.
750
- emit_std_enc_enc(
751
- sink,
752
- LegacyPrefixes::None,
753
- 0xC7,
754
- 1,
755
- /* subopcode */ 0,
756
- enc_dst,
757
- RexFlags::set_w(),
758
- );
759
- sink.put4(*simm64 as u32);
760
- } else {
761
- sink.put1(0x48 | ((enc_dst >> 3) & 1));
762
- sink.put1(0xB8 | (enc_dst & 7));
763
- sink.put8(*simm64);
764
- }
765
- } else {
766
- if ((enc_dst >> 3) & 1) == 1 {
767
- sink.put1(0x41);
768
- }
769
- sink.put1(0xB8 | (enc_dst & 7));
770
- sink.put4(*simm64 as u32);
771
- }
772
- }
773
-
774
- Inst::MovImmM { size, simm64, dst } => {
775
- let dst = &dst.finalize(state, sink).with_allocs(allocs);
776
- let default_rex = RexFlags::clear_w();
777
- let default_opcode = 0xC7;
778
- let bytes = size.to_bytes();
779
- let prefix = LegacyPrefixes::None;
780
-
781
- let (opcode, rex, size, prefix) = match *size {
782
- // In the 8-bit case, we don't need to enforce REX flags via
783
- // `always_emit_if_8bit_needed()` since the destination
784
- // operand is a memory operand, not a possibly 8-bit register.
785
- OperandSize::Size8 => (0xC6, default_rex, bytes, prefix),
786
- OperandSize::Size16 => (0xC7, default_rex, bytes, LegacyPrefixes::_66),
787
- OperandSize::Size64 => {
788
- if !low32_will_sign_extend_to_64(*simm64) {
789
- panic!("Immediate-to-memory moves require immediate operand to sign-extend to 64 bits.");
790
- }
791
-
792
- (default_opcode, RexFlags::from(*size), bytes, prefix)
793
- }
794
-
795
- _ => (default_opcode, default_rex, bytes, prefix),
796
- };
797
-
798
- // 8-bit C6 /0 ib
799
- // 16-bit 0x66 C7 /0 iw
800
- // 32-bit C7 /0 id
801
- // 64-bit REX.W C7 /0 id
802
- emit_std_enc_mem(sink, prefix, opcode, 1, /*subopcode*/ 0, dst, rex, 0);
803
- emit_simm(sink, size, *simm64 as u32);
804
- }
805
-
806
- Inst::MovRR { size, src, dst } => {
807
- let src = allocs.next(src.to_reg());
808
- let dst = allocs.next(dst.to_reg().to_reg());
809
- emit_std_reg_reg(
810
- sink,
811
- LegacyPrefixes::None,
812
- 0x89,
813
- 1,
814
- src,
815
- dst,
816
- RexFlags::from(*size),
817
- );
818
- }
819
-
820
- Inst::MovFromPReg { src, dst } => {
821
- allocs.next_fixed_nonallocatable(*src);
822
- let src: Reg = (*src).into();
823
- debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&src));
824
- let src = Gpr::new(src).unwrap();
825
- let size = OperandSize::Size64;
826
- let dst = allocs.next(dst.to_reg().to_reg());
827
- let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
828
- Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
829
- }
830
-
831
- Inst::MovToPReg { src, dst } => {
832
- let src = allocs.next(src.to_reg());
833
- let src = Gpr::new(src).unwrap();
834
- allocs.next_fixed_nonallocatable(*dst);
835
- let dst: Reg = (*dst).into();
836
- debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&dst));
837
- let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
838
- let size = OperandSize::Size64;
839
- Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
840
- }
841
-
842
- Inst::MovzxRmR { ext_mode, src, dst } => {
843
- let dst = allocs.next(dst.to_reg().to_reg());
844
- let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
845
- ExtMode::BL => {
846
- // MOVZBL is (REX.W==0) 0F B6 /r
847
- (0x0FB6, 2, RexFlags::clear_w())
848
- }
849
- ExtMode::BQ => {
850
- // MOVZBQ is (REX.W==1) 0F B6 /r
851
- // I'm not sure why the Intel manual offers different
852
- // encodings for MOVZBQ than for MOVZBL. AIUI they should
853
- // achieve the same, since MOVZBL is just going to zero out
854
- // the upper half of the destination anyway.
855
- (0x0FB6, 2, RexFlags::set_w())
856
- }
857
- ExtMode::WL => {
858
- // MOVZWL is (REX.W==0) 0F B7 /r
859
- (0x0FB7, 2, RexFlags::clear_w())
860
- }
861
- ExtMode::WQ => {
862
- // MOVZWQ is (REX.W==1) 0F B7 /r
863
- (0x0FB7, 2, RexFlags::set_w())
864
- }
865
- ExtMode::LQ => {
866
- // This is just a standard 32 bit load, and we rely on the
867
- // default zero-extension rule to perform the extension.
868
- // Note that in reg/reg mode, gcc seems to use the swapped form R/RM, which we
869
- // don't do here, since it's the same encoding size.
870
- // MOV r/m32, r32 is (REX.W==0) 8B /r
871
- (0x8B, 1, RexFlags::clear_w())
872
- }
873
- };
874
-
875
- match src.clone().to_reg_mem() {
876
- RegMem::Reg { reg: src } => {
877
- let src = allocs.next(src);
878
- match ext_mode {
879
- ExtMode::BL | ExtMode::BQ => {
880
- // A redundant REX prefix must be emitted for certain register inputs.
881
- rex_flags.always_emit_if_8bit_needed(src);
882
- }
883
- _ => {}
884
- }
885
- emit_std_reg_reg(
886
- sink,
887
- LegacyPrefixes::None,
888
- opcodes,
889
- num_opcodes,
890
- dst,
891
- src,
892
- rex_flags,
893
- )
894
- }
895
-
896
- RegMem::Mem { addr: src } => {
897
- let src = &src.finalize(state, sink).with_allocs(allocs);
898
-
899
- emit_std_reg_mem(
900
- sink,
901
- LegacyPrefixes::None,
902
- opcodes,
903
- num_opcodes,
904
- dst,
905
- src,
906
- rex_flags,
907
- 0,
908
- )
909
- }
910
- }
911
- }
912
-
913
- Inst::Mov64MR { src, dst } => {
914
- let dst = allocs.next(dst.to_reg().to_reg());
915
- let src = &src.finalize(state, sink).with_allocs(allocs);
916
-
917
- emit_std_reg_mem(
918
- sink,
919
- LegacyPrefixes::None,
920
- 0x8B,
921
- 1,
922
- dst,
923
- src,
924
- RexFlags::set_w(),
925
- 0,
926
- )
927
- }
928
-
929
- Inst::LoadEffectiveAddress { addr, dst } => {
930
- let dst = allocs.next(dst.to_reg().to_reg());
931
- let amode = addr.finalize(state, sink).with_allocs(allocs);
932
-
933
- emit_std_reg_mem(
934
- sink,
935
- LegacyPrefixes::None,
936
- 0x8D,
937
- 1,
938
- dst,
939
- &amode,
940
- RexFlags::set_w(),
941
- 0,
942
- );
943
- }
944
-
945
- Inst::MovsxRmR { ext_mode, src, dst } => {
946
- let dst = allocs.next(dst.to_reg().to_reg());
947
- let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
948
- ExtMode::BL => {
949
- // MOVSBL is (REX.W==0) 0F BE /r
950
- (0x0FBE, 2, RexFlags::clear_w())
951
- }
952
- ExtMode::BQ => {
953
- // MOVSBQ is (REX.W==1) 0F BE /r
954
- (0x0FBE, 2, RexFlags::set_w())
955
- }
956
- ExtMode::WL => {
957
- // MOVSWL is (REX.W==0) 0F BF /r
958
- (0x0FBF, 2, RexFlags::clear_w())
959
- }
960
- ExtMode::WQ => {
961
- // MOVSWQ is (REX.W==1) 0F BF /r
962
- (0x0FBF, 2, RexFlags::set_w())
963
- }
964
- ExtMode::LQ => {
965
- // MOVSLQ is (REX.W==1) 63 /r
966
- (0x63, 1, RexFlags::set_w())
967
- }
968
- };
969
-
970
- match src.clone().to_reg_mem() {
971
- RegMem::Reg { reg: src } => {
972
- let src = allocs.next(src);
973
- match ext_mode {
974
- ExtMode::BL | ExtMode::BQ => {
975
- // A redundant REX prefix must be emitted for certain register inputs.
976
- rex_flags.always_emit_if_8bit_needed(src);
977
- }
978
- _ => {}
979
- }
980
- emit_std_reg_reg(
981
- sink,
982
- LegacyPrefixes::None,
983
- opcodes,
984
- num_opcodes,
985
- dst,
986
- src,
987
- rex_flags,
988
- )
989
- }
990
-
991
- RegMem::Mem { addr: src } => {
992
- let src = &src.finalize(state, sink).with_allocs(allocs);
993
-
994
- emit_std_reg_mem(
995
- sink,
996
- LegacyPrefixes::None,
997
- opcodes,
998
- num_opcodes,
999
- dst,
1000
- src,
1001
- rex_flags,
1002
- 0,
1003
- )
1004
- }
1005
- }
1006
- }
1007
-
1008
- Inst::MovRM { size, src, dst } => {
1009
- let src = allocs.next(src.to_reg());
1010
- let dst = &dst.finalize(state, sink).with_allocs(allocs);
1011
-
1012
- let prefix = match size {
1013
- OperandSize::Size16 => LegacyPrefixes::_66,
1014
- _ => LegacyPrefixes::None,
1015
- };
1016
-
1017
- let opcode = match size {
1018
- OperandSize::Size8 => 0x88,
1019
- _ => 0x89,
1020
- };
1021
-
1022
- // This is one of the few places where the presence of a
1023
- // redundant REX prefix changes the meaning of the
1024
- // instruction.
1025
- let rex = RexFlags::from((*size, src));
1026
-
1027
- // 8-bit: MOV r8, r/m8 is (REX.W==0) 88 /r
1028
- // 16-bit: MOV r16, r/m16 is 66 (REX.W==0) 89 /r
1029
- // 32-bit: MOV r32, r/m32 is (REX.W==0) 89 /r
1030
- // 64-bit: MOV r64, r/m64 is (REX.W==1) 89 /r
1031
- emit_std_reg_mem(sink, prefix, opcode, 1, src, dst, rex, 0);
1032
- }
1033
-
1034
- Inst::ShiftR {
1035
- size,
1036
- kind,
1037
- src,
1038
- num_bits,
1039
- dst,
1040
- } => {
1041
- let src = allocs.next(src.to_reg());
1042
- let dst = allocs.next(dst.to_reg().to_reg());
1043
- debug_assert_eq!(src, dst);
1044
- let subopcode = match kind {
1045
- ShiftKind::RotateLeft => 0,
1046
- ShiftKind::RotateRight => 1,
1047
- ShiftKind::ShiftLeft => 4,
1048
- ShiftKind::ShiftRightLogical => 5,
1049
- ShiftKind::ShiftRightArithmetic => 7,
1050
- };
1051
- let enc_dst = int_reg_enc(dst);
1052
- let rex_flags = RexFlags::from((*size, dst));
1053
- match num_bits.clone().to_imm8_reg() {
1054
- Imm8Reg::Reg { reg } => {
1055
- let reg = allocs.next(reg);
1056
- debug_assert_eq!(reg, regs::rcx());
1057
- let (opcode, prefix) = match size {
1058
- OperandSize::Size8 => (0xD2, LegacyPrefixes::None),
1059
- OperandSize::Size16 => (0xD3, LegacyPrefixes::_66),
1060
- OperandSize::Size32 => (0xD3, LegacyPrefixes::None),
1061
- OperandSize::Size64 => (0xD3, LegacyPrefixes::None),
1062
- };
1063
-
1064
- // SHL/SHR/SAR %cl, reg8 is (REX.W==0) D2 /subopcode
1065
- // SHL/SHR/SAR %cl, reg16 is 66 (REX.W==0) D3 /subopcode
1066
- // SHL/SHR/SAR %cl, reg32 is (REX.W==0) D3 /subopcode
1067
- // SHL/SHR/SAR %cl, reg64 is (REX.W==1) D3 /subopcode
1068
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1069
- }
1070
-
1071
- Imm8Reg::Imm8 { imm: num_bits } => {
1072
- let (opcode, prefix) = match size {
1073
- OperandSize::Size8 => (0xC0, LegacyPrefixes::None),
1074
- OperandSize::Size16 => (0xC1, LegacyPrefixes::_66),
1075
- OperandSize::Size32 => (0xC1, LegacyPrefixes::None),
1076
- OperandSize::Size64 => (0xC1, LegacyPrefixes::None),
1077
- };
1078
-
1079
- // SHL/SHR/SAR $ib, reg8 is (REX.W==0) C0 /subopcode
1080
- // SHL/SHR/SAR $ib, reg16 is 66 (REX.W==0) C1 /subopcode
1081
- // SHL/SHR/SAR $ib, reg32 is (REX.W==0) C1 /subopcode ib
1082
- // SHL/SHR/SAR $ib, reg64 is (REX.W==1) C1 /subopcode ib
1083
- // When the shift amount is 1, there's an even shorter encoding, but we don't
1084
- // bother with that nicety here.
1085
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1086
- sink.put1(num_bits);
1087
- }
1088
- }
1089
- }
1090
-
1091
- Inst::XmmRmiReg {
1092
- opcode,
1093
- src1,
1094
- src2,
1095
- dst,
1096
- } => {
1097
- let src1 = allocs.next(src1.to_reg());
1098
- let dst = allocs.next(dst.to_reg().to_reg());
1099
- debug_assert_eq!(src1, dst);
1100
- let rex = RexFlags::clear_w();
1101
- let prefix = LegacyPrefixes::_66;
1102
- let src2 = src2.clone().to_reg_mem_imm();
1103
- if let RegMemImm::Imm { simm32 } = src2 {
1104
- let (opcode_bytes, reg_digit) = match opcode {
1105
- SseOpcode::Psllw => (0x0F71, 6),
1106
- SseOpcode::Pslld => (0x0F72, 6),
1107
- SseOpcode::Psllq => (0x0F73, 6),
1108
- SseOpcode::Psraw => (0x0F71, 4),
1109
- SseOpcode::Psrad => (0x0F72, 4),
1110
- SseOpcode::Psrlw => (0x0F71, 2),
1111
- SseOpcode::Psrld => (0x0F72, 2),
1112
- SseOpcode::Psrlq => (0x0F73, 2),
1113
- _ => panic!("invalid opcode: {}", opcode),
1114
- };
1115
- let dst_enc = reg_enc(dst);
1116
- emit_std_enc_enc(sink, prefix, opcode_bytes, 2, reg_digit, dst_enc, rex);
1117
- let imm = (simm32)
1118
- .try_into()
1119
- .expect("the immediate must be convertible to a u8");
1120
- sink.put1(imm);
1121
- } else {
1122
- let opcode_bytes = match opcode {
1123
- SseOpcode::Psllw => 0x0FF1,
1124
- SseOpcode::Pslld => 0x0FF2,
1125
- SseOpcode::Psllq => 0x0FF3,
1126
- SseOpcode::Psraw => 0x0FE1,
1127
- SseOpcode::Psrad => 0x0FE2,
1128
- SseOpcode::Psrlw => 0x0FD1,
1129
- SseOpcode::Psrld => 0x0FD2,
1130
- SseOpcode::Psrlq => 0x0FD3,
1131
- _ => panic!("invalid opcode: {}", opcode),
1132
- };
1133
-
1134
- match src2 {
1135
- RegMemImm::Reg { reg } => {
1136
- let reg = allocs.next(reg);
1137
- emit_std_reg_reg(sink, prefix, opcode_bytes, 2, dst, reg, rex);
1138
- }
1139
- RegMemImm::Mem { addr } => {
1140
- let addr = &addr.finalize(state, sink).with_allocs(allocs);
1141
- emit_std_reg_mem(sink, prefix, opcode_bytes, 2, dst, addr, rex, 0);
1142
- }
1143
- RegMemImm::Imm { .. } => unreachable!(),
1144
- }
1145
- };
1146
- }
1147
-
1148
- Inst::CmpRmiR {
1149
- size,
1150
- src: src_e,
1151
- dst: reg_g,
1152
- opcode,
1153
- } => {
1154
- let reg_g = allocs.next(reg_g.to_reg());
1155
-
1156
- let is_cmp = match opcode {
1157
- CmpOpcode::Cmp => true,
1158
- CmpOpcode::Test => false,
1159
- };
1160
-
1161
- let mut prefix = LegacyPrefixes::None;
1162
- if *size == OperandSize::Size16 {
1163
- prefix = LegacyPrefixes::_66;
1164
- }
1165
- // A redundant REX prefix can change the meaning of this instruction.
1166
- let mut rex = RexFlags::from((*size, reg_g));
1167
-
1168
- match src_e.clone().to_reg_mem_imm() {
1169
- RegMemImm::Reg { reg: reg_e } => {
1170
- let reg_e = allocs.next(reg_e);
1171
- if *size == OperandSize::Size8 {
1172
- // Check whether the E register forces the use of a redundant REX.
1173
- rex.always_emit_if_8bit_needed(reg_e);
1174
- }
1175
-
1176
- // Use the swapped operands encoding for CMP, to stay consistent with the output of
1177
- // gcc/llvm.
1178
- let opcode = match (*size, is_cmp) {
1179
- (OperandSize::Size8, true) => 0x38,
1180
- (_, true) => 0x39,
1181
- (OperandSize::Size8, false) => 0x84,
1182
- (_, false) => 0x85,
1183
- };
1184
- emit_std_reg_reg(sink, prefix, opcode, 1, reg_e, reg_g, rex);
1185
- }
1186
-
1187
- RegMemImm::Mem { addr } => {
1188
- let addr = &addr.finalize(state, sink).with_allocs(allocs);
1189
- // Whereas here we revert to the "normal" G-E ordering for CMP.
1190
- let opcode = match (*size, is_cmp) {
1191
- (OperandSize::Size8, true) => 0x3A,
1192
- (_, true) => 0x3B,
1193
- (OperandSize::Size8, false) => 0x84,
1194
- (_, false) => 0x85,
1195
- };
1196
- emit_std_reg_mem(sink, prefix, opcode, 1, reg_g, addr, rex, 0);
1197
- }
1198
-
1199
- RegMemImm::Imm { simm32 } => {
1200
- // FIXME JRS 2020Feb11: there are shorter encodings for
1201
- // cmp $imm, rax/eax/ax/al.
1202
- let use_imm8 = is_cmp && low8_will_sign_extend_to_32(simm32);
1203
-
1204
- // And also here we use the "normal" G-E ordering.
1205
- let opcode = if is_cmp {
1206
- if *size == OperandSize::Size8 {
1207
- 0x80
1208
- } else if use_imm8 {
1209
- 0x83
1210
- } else {
1211
- 0x81
1212
- }
1213
- } else {
1214
- if *size == OperandSize::Size8 {
1215
- 0xF6
1216
- } else {
1217
- 0xF7
1218
- }
1219
- };
1220
- let subopcode = if is_cmp { 7 } else { 0 };
1221
-
1222
- let enc_g = int_reg_enc(reg_g);
1223
- emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_g, rex);
1224
- emit_simm(sink, if use_imm8 { 1 } else { size.to_bytes() }, simm32);
1225
- }
1226
- }
1227
- }
1228
-
1229
- Inst::Setcc { cc, dst } => {
1230
- let dst = allocs.next(dst.to_reg().to_reg());
1231
- let opcode = 0x0f90 + cc.get_enc() as u32;
1232
- let mut rex_flags = RexFlags::clear_w();
1233
- rex_flags.always_emit();
1234
- emit_std_enc_enc(
1235
- sink,
1236
- LegacyPrefixes::None,
1237
- opcode,
1238
- 2,
1239
- 0,
1240
- reg_enc(dst),
1241
- rex_flags,
1242
- );
1243
- }
1244
-
1245
- Inst::Bswap { size, src, dst } => {
1246
- let src = allocs.next(src.to_reg());
1247
- let dst = allocs.next(dst.to_reg().to_reg());
1248
- debug_assert_eq!(src, dst);
1249
- let enc_reg = int_reg_enc(dst);
1250
-
1251
- // BSWAP reg32 is (REX.W==0) 0F C8
1252
- // BSWAP reg64 is (REX.W==1) 0F C8
1253
- let rex_flags = RexFlags::from(*size);
1254
- rex_flags.emit_one_op(sink, enc_reg);
1255
-
1256
- sink.put1(0x0F);
1257
- sink.put1(0xC8 | (enc_reg & 7));
1258
- }
1259
-
1260
- Inst::Cmove {
1261
- size,
1262
- cc,
1263
- consequent,
1264
- alternative,
1265
- dst,
1266
- } => {
1267
- let alternative = allocs.next(alternative.to_reg());
1268
- let dst = allocs.next(dst.to_reg().to_reg());
1269
- debug_assert_eq!(alternative, dst);
1270
- let rex_flags = RexFlags::from(*size);
1271
- let prefix = match size {
1272
- OperandSize::Size16 => LegacyPrefixes::_66,
1273
- OperandSize::Size32 => LegacyPrefixes::None,
1274
- OperandSize::Size64 => LegacyPrefixes::None,
1275
- _ => unreachable!("invalid size spec for cmove"),
1276
- };
1277
- let opcode = 0x0F40 + cc.get_enc() as u32;
1278
- match consequent.clone().to_reg_mem() {
1279
- RegMem::Reg { reg } => {
1280
- let reg = allocs.next(reg);
1281
- emit_std_reg_reg(sink, prefix, opcode, 2, dst, reg, rex_flags);
1282
- }
1283
- RegMem::Mem { addr } => {
1284
- let addr = &addr.finalize(state, sink).with_allocs(allocs);
1285
- emit_std_reg_mem(sink, prefix, opcode, 2, dst, addr, rex_flags, 0);
1286
- }
1287
- }
1288
- }
1289
-
1290
- Inst::XmmCmove {
1291
- ty,
1292
- cc,
1293
- consequent,
1294
- alternative,
1295
- dst,
1296
- } => {
1297
- let alternative = allocs.next(alternative.to_reg());
1298
- let dst = allocs.next(dst.to_reg().to_reg());
1299
- debug_assert_eq!(alternative, dst);
1300
- let consequent = consequent.clone().to_reg_mem().with_allocs(allocs);
1301
-
1302
- // Lowering of the Select IR opcode when the input is an fcmp relies on the fact that
1303
- // this doesn't clobber flags. Make sure to not do so here.
1304
- let next = sink.get_label();
1305
-
1306
- // Jump if cc is *not* set.
1307
- one_way_jmp(sink, cc.invert(), next);
1308
-
1309
- let op = match *ty {
1310
- types::F64 => SseOpcode::Movsd,
1311
- types::F32 => SseOpcode::Movsd,
1312
- types::F32X4 => SseOpcode::Movaps,
1313
- types::F64X2 => SseOpcode::Movapd,
1314
- ty => {
1315
- debug_assert!(ty.is_vector() && ty.bytes() == 16);
1316
- SseOpcode::Movdqa
1317
- }
1318
- };
1319
- let inst = Inst::xmm_unary_rm_r(op, consequent, Writable::from_reg(dst));
1320
- inst.emit(&[], sink, info, state);
1321
-
1322
- sink.bind_label(next, &mut state.ctrl_plane);
1323
- }
1324
-
1325
- Inst::Push64 { src } => {
1326
- let src = src.clone().to_reg_mem_imm().with_allocs(allocs);
1327
-
1328
- match src {
1329
- RegMemImm::Reg { reg } => {
1330
- let enc_reg = int_reg_enc(reg);
1331
- let rex = 0x40 | ((enc_reg >> 3) & 1);
1332
- if rex != 0x40 {
1333
- sink.put1(rex);
1334
- }
1335
- sink.put1(0x50 | (enc_reg & 7));
1336
- }
1337
-
1338
- RegMemImm::Mem { addr } => {
1339
- let addr = &addr.finalize(state, sink);
1340
- emit_std_enc_mem(
1341
- sink,
1342
- LegacyPrefixes::None,
1343
- 0xFF,
1344
- 1,
1345
- 6, /*subopcode*/
1346
- addr,
1347
- RexFlags::clear_w(),
1348
- 0,
1349
- );
1350
- }
1351
-
1352
- RegMemImm::Imm { simm32 } => {
1353
- if low8_will_sign_extend_to_64(simm32) {
1354
- sink.put1(0x6A);
1355
- sink.put1(simm32 as u8);
1356
- } else {
1357
- sink.put1(0x68);
1358
- sink.put4(simm32);
1359
- }
1360
- }
1361
- }
1362
- }
1363
-
1364
- Inst::Pop64 { dst } => {
1365
- let dst = allocs.next(dst.to_reg().to_reg());
1366
- let enc_dst = int_reg_enc(dst);
1367
- if enc_dst >= 8 {
1368
- // 0x41 == REX.{W=0, B=1}. It seems that REX.W is irrelevant here.
1369
- sink.put1(0x41);
1370
- }
1371
- sink.put1(0x58 + (enc_dst & 7));
1372
- }
1373
-
1374
- Inst::StackProbeLoop {
1375
- tmp,
1376
- frame_size,
1377
- guard_size,
1378
- } => {
1379
- assert!(info.flags.enable_probestack());
1380
- assert!(guard_size.is_power_of_two());
1381
-
1382
- let tmp = allocs.next_writable(*tmp);
1383
-
1384
- // Number of probes that we need to perform
1385
- let probe_count = align_to(*frame_size, *guard_size) / guard_size;
1386
-
1387
- // The inline stack probe loop has 3 phases:
1388
- //
1389
- // We generate the "guard area" register which is essentially the frame_size aligned to
1390
- // guard_size. We copy the stack pointer and subtract the guard area from it. This
1391
- // gets us a register that we can use to compare when looping.
1392
- //
1393
- // After that we emit the loop. Essentially we just adjust the stack pointer one guard_size'd
1394
- // distance at a time and then touch the stack by writing anything to it. We use the previously
1395
- // created "guard area" register to know when to stop looping.
1396
- //
1397
- // When we have touched all the pages that we need, we have to restore the stack pointer
1398
- // to where it was before.
1399
- //
1400
- // Generate the following code:
1401
- // mov tmp_reg, rsp
1402
- // sub tmp_reg, guard_size * probe_count
1403
- // .loop_start:
1404
- // sub rsp, guard_size
1405
- // mov [rsp], rsp
1406
- // cmp rsp, tmp_reg
1407
- // jne .loop_start
1408
- // add rsp, guard_size * probe_count
1409
-
1410
- // Create the guard bound register
1411
- // mov tmp_reg, rsp
1412
- let inst = Inst::gen_move(tmp, regs::rsp(), types::I64);
1413
- inst.emit(&[], sink, info, state);
1414
-
1415
- // sub tmp_reg, GUARD_SIZE * probe_count
1416
- let inst = Inst::alu_rmi_r(
1417
- OperandSize::Size64,
1418
- AluRmiROpcode::Sub,
1419
- RegMemImm::imm(guard_size * probe_count),
1420
- tmp,
1421
- );
1422
- inst.emit(&[], sink, info, state);
1423
-
1424
- // Emit the main loop!
1425
- let loop_start = sink.get_label();
1426
- sink.bind_label(loop_start, &mut state.ctrl_plane);
1427
-
1428
- // sub rsp, GUARD_SIZE
1429
- let inst = Inst::alu_rmi_r(
1430
- OperandSize::Size64,
1431
- AluRmiROpcode::Sub,
1432
- RegMemImm::imm(*guard_size),
1433
- Writable::from_reg(regs::rsp()),
1434
- );
1435
- inst.emit(&[], sink, info, state);
1436
-
1437
- // TODO: `mov [rsp], 0` would be better, but we don't have that instruction
1438
- // Probe the stack! We don't use Inst::gen_store_stack here because we need a predictable
1439
- // instruction size.
1440
- // mov [rsp], rsp
1441
- let inst = Inst::mov_r_m(
1442
- OperandSize::Size32, // Use Size32 since it saves us one byte
1443
- regs::rsp(),
1444
- SyntheticAmode::Real(Amode::imm_reg(0, regs::rsp())),
1445
- );
1446
- inst.emit(&[], sink, info, state);
1447
-
1448
- // Compare and jump if we are not done yet
1449
- // cmp rsp, tmp_reg
1450
- let inst = Inst::cmp_rmi_r(
1451
- OperandSize::Size64,
1452
- RegMemImm::reg(regs::rsp()),
1453
- tmp.to_reg(),
1454
- );
1455
- inst.emit(&[], sink, info, state);
1456
-
1457
- // jne .loop_start
1458
- // TODO: Encoding the JmpIf as a short jump saves us 4 bytes here.
1459
- one_way_jmp(sink, CC::NZ, loop_start);
1460
-
1461
- // The regular prologue code is going to emit a `sub` after this, so we need to
1462
- // reset the stack pointer
1463
- //
1464
- // TODO: It would be better if we could avoid the `add` + `sub` that is generated here
1465
- // and in the stack adj portion of the prologue
1466
- //
1467
- // add rsp, GUARD_SIZE * probe_count
1468
- let inst = Inst::alu_rmi_r(
1469
- OperandSize::Size64,
1470
- AluRmiROpcode::Add,
1471
- RegMemImm::imm(guard_size * probe_count),
1472
- Writable::from_reg(regs::rsp()),
1473
- );
1474
- inst.emit(&[], sink, info, state);
1475
- }
1476
-
1477
- Inst::CallKnown {
1478
- dest,
1479
- info: call_info,
1480
- ..
1481
- } => {
1482
- if let Some(s) = state.take_stack_map() {
1483
- sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s);
1484
- }
1485
- sink.put1(0xE8);
1486
- // The addend adjusts for the difference between the end of the instruction and the
1487
- // beginning of the immediate field.
1488
- emit_reloc(sink, Reloc::X86CallPCRel4, &dest, -4);
1489
- sink.put4(0);
1490
- if call_info.opcode.is_call() {
1491
- sink.add_call_site(call_info.opcode);
1492
- }
1493
- }
1494
-
1495
- Inst::CallUnknown {
1496
- dest,
1497
- info: call_info,
1498
- ..
1499
- } => {
1500
- let dest = dest.with_allocs(allocs);
1501
-
1502
- let start_offset = sink.cur_offset();
1503
- match dest {
1504
- RegMem::Reg { reg } => {
1505
- let reg_enc = int_reg_enc(reg);
1506
- emit_std_enc_enc(
1507
- sink,
1508
- LegacyPrefixes::None,
1509
- 0xFF,
1510
- 1,
1511
- 2, /*subopcode*/
1512
- reg_enc,
1513
- RexFlags::clear_w(),
1514
- );
1515
- }
1516
-
1517
- RegMem::Mem { addr } => {
1518
- let addr = &addr.finalize(state, sink);
1519
- emit_std_enc_mem(
1520
- sink,
1521
- LegacyPrefixes::None,
1522
- 0xFF,
1523
- 1,
1524
- 2, /*subopcode*/
1525
- addr,
1526
- RexFlags::clear_w(),
1527
- 0,
1528
- );
1529
- }
1530
- }
1531
- if let Some(s) = state.take_stack_map() {
1532
- sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s);
1533
- }
1534
- if call_info.opcode.is_call() {
1535
- sink.add_call_site(call_info.opcode);
1536
- }
1537
- }
1538
-
1539
- Inst::Args { .. } => {}
1540
-
1541
- Inst::Ret { .. } => sink.put1(0xC3),
1542
-
1543
- Inst::JmpKnown { dst } => {
1544
- let br_start = sink.cur_offset();
1545
- let br_disp_off = br_start + 1;
1546
- let br_end = br_start + 5;
1547
-
1548
- sink.use_label_at_offset(br_disp_off, *dst, LabelUse::JmpRel32);
1549
- sink.add_uncond_branch(br_start, br_end, *dst);
1550
-
1551
- sink.put1(0xE9);
1552
- // Placeholder for the label value.
1553
- sink.put4(0x0);
1554
- }
1555
-
1556
- Inst::JmpIf { cc, taken } => {
1557
- let cond_start = sink.cur_offset();
1558
- let cond_disp_off = cond_start + 2;
1559
-
1560
- sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1561
- // Since this is not a terminator, don't enroll in the branch inversion mechanism.
1562
-
1563
- sink.put1(0x0F);
1564
- sink.put1(0x80 + cc.get_enc());
1565
- // Placeholder for the label value.
1566
- sink.put4(0x0);
1567
- }
1568
-
1569
- Inst::JmpCond {
1570
- cc,
1571
- taken,
1572
- not_taken,
1573
- } => {
1574
- // If taken.
1575
- let cond_start = sink.cur_offset();
1576
- let cond_disp_off = cond_start + 2;
1577
- let cond_end = cond_start + 6;
1578
-
1579
- sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1580
- let inverted: [u8; 6] = [0x0F, 0x80 + (cc.invert().get_enc()), 0x00, 0x00, 0x00, 0x00];
1581
- sink.add_cond_branch(cond_start, cond_end, *taken, &inverted[..]);
1582
-
1583
- sink.put1(0x0F);
1584
- sink.put1(0x80 + cc.get_enc());
1585
- // Placeholder for the label value.
1586
- sink.put4(0x0);
1587
-
1588
- // If not taken.
1589
- let uncond_start = sink.cur_offset();
1590
- let uncond_disp_off = uncond_start + 1;
1591
- let uncond_end = uncond_start + 5;
1592
-
1593
- sink.use_label_at_offset(uncond_disp_off, *not_taken, LabelUse::JmpRel32);
1594
- sink.add_uncond_branch(uncond_start, uncond_end, *not_taken);
1595
-
1596
- sink.put1(0xE9);
1597
- // Placeholder for the label value.
1598
- sink.put4(0x0);
1599
- }
1600
-
1601
- Inst::JmpUnknown { target } => {
1602
- let target = target.with_allocs(allocs);
1603
-
1604
- match target {
1605
- RegMem::Reg { reg } => {
1606
- let reg_enc = int_reg_enc(reg);
1607
- emit_std_enc_enc(
1608
- sink,
1609
- LegacyPrefixes::None,
1610
- 0xFF,
1611
- 1,
1612
- 4, /*subopcode*/
1613
- reg_enc,
1614
- RexFlags::clear_w(),
1615
- );
1616
- }
1617
-
1618
- RegMem::Mem { addr } => {
1619
- let addr = &addr.finalize(state, sink);
1620
- emit_std_enc_mem(
1621
- sink,
1622
- LegacyPrefixes::None,
1623
- 0xFF,
1624
- 1,
1625
- 4, /*subopcode*/
1626
- addr,
1627
- RexFlags::clear_w(),
1628
- 0,
1629
- );
1630
- }
1631
- }
1632
- }
1633
-
1634
- Inst::JmpTableSeq {
1635
- idx,
1636
- tmp1,
1637
- tmp2,
1638
- ref targets,
1639
- default_target,
1640
- ..
1641
- } => {
1642
- let idx = allocs.next(*idx);
1643
- let tmp1 = Writable::from_reg(allocs.next(tmp1.to_reg()));
1644
- let tmp2 = Writable::from_reg(allocs.next(tmp2.to_reg()));
1645
-
1646
- // This sequence is *one* instruction in the vcode, and is expanded only here at
1647
- // emission time, because we cannot allow the regalloc to insert spills/reloads in
1648
- // the middle; we depend on hardcoded PC-rel addressing below.
1649
- //
1650
- // We don't have to worry about emitting islands, because the only label-use type has a
1651
- // maximum range of 2 GB. If we later consider using shorter-range label references,
1652
- // this will need to be revisited.
1653
-
1654
- // We generate the following sequence. Note that the only read of %idx is before the
1655
- // write to %tmp2, so regalloc may use the same register for both; fix x64/inst/mod.rs
1656
- // if you change this.
1657
- // lea start_of_jump_table_offset(%rip), %tmp1
1658
- // movslq [%tmp1, %idx, 4], %tmp2 ;; shift of 2, viz. multiply index by 4
1659
- // addq %tmp2, %tmp1
1660
- // j *%tmp1
1661
- // $start_of_jump_table:
1662
- // -- jump table entries
1663
-
1664
- // Load base address of jump table.
1665
- let start_of_jumptable = sink.get_label();
1666
- let inst = Inst::lea(Amode::rip_relative(start_of_jumptable), tmp1);
1667
- inst.emit(&[], sink, info, state);
1668
-
1669
- // Load value out of the jump table. It's a relative offset to the target block, so it
1670
- // might be negative; use a sign-extension.
1671
- let inst = Inst::movsx_rm_r(
1672
- ExtMode::LQ,
1673
- RegMem::mem(Amode::imm_reg_reg_shift(
1674
- 0,
1675
- Gpr::new(tmp1.to_reg()).unwrap(),
1676
- Gpr::new(idx).unwrap(),
1677
- 2,
1678
- )),
1679
- tmp2,
1680
- );
1681
- inst.emit(&[], sink, info, state);
1682
-
1683
- // Add base of jump table to jump-table-sourced block offset.
1684
- let inst = Inst::alu_rmi_r(
1685
- OperandSize::Size64,
1686
- AluRmiROpcode::Add,
1687
- RegMemImm::reg(tmp2.to_reg()),
1688
- tmp1,
1689
- );
1690
- inst.emit(&[], sink, info, state);
1691
-
1692
- // Branch to computed address.
1693
- let inst = Inst::jmp_unknown(RegMem::reg(tmp1.to_reg()));
1694
- inst.emit(&[], sink, info, state);
1695
-
1696
- // Emit jump table (table of 32-bit offsets).
1697
- sink.bind_label(start_of_jumptable, &mut state.ctrl_plane);
1698
- let jt_off = sink.cur_offset();
1699
- for &target in targets.iter().chain(std::iter::once(default_target)) {
1700
- let word_off = sink.cur_offset();
1701
- // off_into_table is an addend here embedded in the label to be later patched at
1702
- // the end of codegen. The offset is initially relative to this jump table entry;
1703
- // with the extra addend, it'll be relative to the jump table's start, after
1704
- // patching.
1705
- let off_into_table = word_off - jt_off;
1706
- sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
1707
- sink.put4(off_into_table);
1708
- }
1709
- }
1710
-
1711
- Inst::TrapIf { cc, trap_code } => {
1712
- let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1713
- one_way_jmp(sink, *cc, trap_label);
1714
- }
1715
-
1716
- Inst::TrapIfAnd {
1717
- cc1,
1718
- cc2,
1719
- trap_code,
1720
- } => {
1721
- let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1722
- let else_label = sink.get_label();
1723
-
1724
- // Jump to the end if the first condition isn't true, and then if
1725
- // the second condition is true go to the trap.
1726
- one_way_jmp(sink, cc1.invert(), else_label);
1727
- one_way_jmp(sink, *cc2, trap_label);
1728
-
1729
- sink.bind_label(else_label, &mut state.ctrl_plane);
1730
- }
1731
-
1732
- Inst::TrapIfOr {
1733
- cc1,
1734
- cc2,
1735
- trap_code,
1736
- } => {
1737
- let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1738
-
1739
- // Emit two jumps to the same trap if either condition code is true.
1740
- one_way_jmp(sink, *cc1, trap_label);
1741
- one_way_jmp(sink, *cc2, trap_label);
1742
- }
1743
-
1744
- Inst::XmmUnaryRmR { op, src, dst } => {
1745
- emit(
1746
- &Inst::XmmUnaryRmRUnaligned {
1747
- op: *op,
1748
- src: XmmMem::new(src.clone().into()).unwrap(),
1749
- dst: *dst,
1750
- },
1751
- allocs,
1752
- sink,
1753
- info,
1754
- state,
1755
- );
1756
- }
1757
-
1758
- Inst::XmmUnaryRmRUnaligned {
1759
- op,
1760
- src: src_e,
1761
- dst: reg_g,
1762
- } => {
1763
- let reg_g = allocs.next(reg_g.to_reg().to_reg());
1764
- let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
1765
-
1766
- let rex = RexFlags::clear_w();
1767
-
1768
- let (prefix, opcode, num_opcodes) = match op {
1769
- SseOpcode::Cvtdq2pd => (LegacyPrefixes::_F3, 0x0FE6, 2),
1770
- SseOpcode::Cvtpd2ps => (LegacyPrefixes::_66, 0x0F5A, 2),
1771
- SseOpcode::Cvtps2pd => (LegacyPrefixes::None, 0x0F5A, 2),
1772
- SseOpcode::Cvtdq2ps => (LegacyPrefixes::None, 0x0F5B, 2),
1773
- SseOpcode::Cvtss2sd => (LegacyPrefixes::_F3, 0x0F5A, 2),
1774
- SseOpcode::Cvtsd2ss => (LegacyPrefixes::_F2, 0x0F5A, 2),
1775
- SseOpcode::Cvttpd2dq => (LegacyPrefixes::_66, 0x0FE6, 2),
1776
- SseOpcode::Cvttps2dq => (LegacyPrefixes::_F3, 0x0F5B, 2),
1777
- SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F28, 2),
1778
- SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F28, 2),
1779
- SseOpcode::Movdqa => (LegacyPrefixes::_66, 0x0F6F, 2),
1780
- SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F6F, 2),
1781
- SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
1782
- SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
1783
- SseOpcode::Movups => (LegacyPrefixes::None, 0x0F10, 2),
1784
- SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F10, 2),
1785
- SseOpcode::Pabsb => (LegacyPrefixes::_66, 0x0F381C, 3),
1786
- SseOpcode::Pabsw => (LegacyPrefixes::_66, 0x0F381D, 3),
1787
- SseOpcode::Pabsd => (LegacyPrefixes::_66, 0x0F381E, 3),
1788
- SseOpcode::Pmovsxbd => (LegacyPrefixes::_66, 0x0F3821, 3),
1789
- SseOpcode::Pmovsxbw => (LegacyPrefixes::_66, 0x0F3820, 3),
1790
- SseOpcode::Pmovsxbq => (LegacyPrefixes::_66, 0x0F3822, 3),
1791
- SseOpcode::Pmovsxwd => (LegacyPrefixes::_66, 0x0F3823, 3),
1792
- SseOpcode::Pmovsxwq => (LegacyPrefixes::_66, 0x0F3824, 3),
1793
- SseOpcode::Pmovsxdq => (LegacyPrefixes::_66, 0x0F3825, 3),
1794
- SseOpcode::Pmovzxbd => (LegacyPrefixes::_66, 0x0F3831, 3),
1795
- SseOpcode::Pmovzxbw => (LegacyPrefixes::_66, 0x0F3830, 3),
1796
- SseOpcode::Pmovzxbq => (LegacyPrefixes::_66, 0x0F3832, 3),
1797
- SseOpcode::Pmovzxwd => (LegacyPrefixes::_66, 0x0F3833, 3),
1798
- SseOpcode::Pmovzxwq => (LegacyPrefixes::_66, 0x0F3834, 3),
1799
- SseOpcode::Pmovzxdq => (LegacyPrefixes::_66, 0x0F3835, 3),
1800
- SseOpcode::Sqrtps => (LegacyPrefixes::None, 0x0F51, 2),
1801
- SseOpcode::Sqrtpd => (LegacyPrefixes::_66, 0x0F51, 2),
1802
- SseOpcode::Sqrtss => (LegacyPrefixes::_F3, 0x0F51, 2),
1803
- SseOpcode::Sqrtsd => (LegacyPrefixes::_F2, 0x0F51, 2),
1804
- SseOpcode::Movddup => (LegacyPrefixes::_F2, 0x0F12, 2),
1805
- _ => unimplemented!("Opcode {:?} not implemented", op),
1806
- };
1807
-
1808
- match src_e {
1809
- RegMem::Reg { reg: reg_e } => {
1810
- emit_std_reg_reg(sink, prefix, opcode, num_opcodes, reg_g, reg_e, rex);
1811
- }
1812
- RegMem::Mem { addr } => {
1813
- let addr = &addr.finalize(state, sink);
1814
- emit_std_reg_mem(sink, prefix, opcode, num_opcodes, reg_g, addr, rex, 0);
1815
- }
1816
- };
1817
- }
1818
-
1819
- Inst::XmmUnaryRmRImm { op, src, dst, imm } => {
1820
- let dst = allocs.next(dst.to_reg().to_reg());
1821
- let src = src.clone().to_reg_mem().with_allocs(allocs);
1822
- let rex = RexFlags::clear_w();
1823
-
1824
- let (prefix, opcode, len) = match op {
1825
- SseOpcode::Roundps => (LegacyPrefixes::_66, 0x0F3A08, 3),
1826
- SseOpcode::Roundss => (LegacyPrefixes::_66, 0x0F3A0A, 3),
1827
- SseOpcode::Roundpd => (LegacyPrefixes::_66, 0x0F3A09, 3),
1828
- SseOpcode::Roundsd => (LegacyPrefixes::_66, 0x0F3A0B, 3),
1829
- SseOpcode::Pshufd => (LegacyPrefixes::_66, 0x0F70, 2),
1830
- SseOpcode::Pshuflw => (LegacyPrefixes::_F2, 0x0F70, 2),
1831
- SseOpcode::Pshufhw => (LegacyPrefixes::_F3, 0x0F70, 2),
1832
- _ => unimplemented!("Opcode {:?} not implemented", op),
1833
- };
1834
- match src {
1835
- RegMem::Reg { reg } => {
1836
- emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
1837
- }
1838
- RegMem::Mem { addr } => {
1839
- let addr = &addr.finalize(state, sink);
1840
- // N.B.: bytes_at_end == 1, because of the `imm` byte below.
1841
- emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
1842
- }
1843
- }
1844
- sink.put1(*imm);
1845
- }
1846
-
1847
- Inst::XmmUnaryRmREvex { op, src, dst } => {
1848
- let dst = allocs.next(dst.to_reg().to_reg());
1849
- let src = src.clone().to_reg_mem().with_allocs(allocs);
1850
-
1851
- let (prefix, map, w, opcode) = match op {
1852
- Avx512Opcode::Vcvtudq2ps => (LegacyPrefixes::_F2, OpcodeMap::_0F, false, 0x7a),
1853
- Avx512Opcode::Vpabsq => (LegacyPrefixes::_66, OpcodeMap::_0F38, true, 0x1f),
1854
- Avx512Opcode::Vpopcntb => (LegacyPrefixes::_66, OpcodeMap::_0F38, false, 0x54),
1855
- _ => unimplemented!("Opcode {:?} not implemented", op),
1856
- };
1857
- match src {
1858
- RegMem::Reg { reg: src } => EvexInstruction::new()
1859
- .length(EvexVectorLength::V128)
1860
- .prefix(prefix)
1861
- .map(map)
1862
- .w(w)
1863
- .opcode(opcode)
1864
- .reg(dst.to_real_reg().unwrap().hw_enc())
1865
- .rm(src.to_real_reg().unwrap().hw_enc())
1866
- .encode(sink),
1867
- _ => todo!(),
1868
- };
1869
- }
1870
-
1871
- Inst::XmmRmR {
1872
- op,
1873
- src1,
1874
- src2,
1875
- dst,
1876
- } => emit(
1877
- &Inst::XmmRmRUnaligned {
1878
- op: *op,
1879
- dst: *dst,
1880
- src1: *src1,
1881
- src2: XmmMem::new(src2.clone().to_reg_mem()).unwrap(),
1882
- },
1883
- allocs,
1884
- sink,
1885
- info,
1886
- state,
1887
- ),
1888
-
1889
- Inst::XmmRmRUnaligned {
1890
- op,
1891
- src1,
1892
- src2: src_e,
1893
- dst: reg_g,
1894
- } => {
1895
- let src1 = allocs.next(src1.to_reg());
1896
- let reg_g = allocs.next(reg_g.to_reg().to_reg());
1897
- let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
1898
- debug_assert_eq!(src1, reg_g);
1899
-
1900
- let rex = RexFlags::clear_w();
1901
- let (prefix, opcode, length) = match op {
1902
- SseOpcode::Addps => (LegacyPrefixes::None, 0x0F58, 2),
1903
- SseOpcode::Addpd => (LegacyPrefixes::_66, 0x0F58, 2),
1904
- SseOpcode::Addss => (LegacyPrefixes::_F3, 0x0F58, 2),
1905
- SseOpcode::Addsd => (LegacyPrefixes::_F2, 0x0F58, 2),
1906
- SseOpcode::Andps => (LegacyPrefixes::None, 0x0F54, 2),
1907
- SseOpcode::Andpd => (LegacyPrefixes::_66, 0x0F54, 2),
1908
- SseOpcode::Andnps => (LegacyPrefixes::None, 0x0F55, 2),
1909
- SseOpcode::Andnpd => (LegacyPrefixes::_66, 0x0F55, 2),
1910
- SseOpcode::Divps => (LegacyPrefixes::None, 0x0F5E, 2),
1911
- SseOpcode::Divpd => (LegacyPrefixes::_66, 0x0F5E, 2),
1912
- SseOpcode::Divss => (LegacyPrefixes::_F3, 0x0F5E, 2),
1913
- SseOpcode::Divsd => (LegacyPrefixes::_F2, 0x0F5E, 2),
1914
- SseOpcode::Maxps => (LegacyPrefixes::None, 0x0F5F, 2),
1915
- SseOpcode::Maxpd => (LegacyPrefixes::_66, 0x0F5F, 2),
1916
- SseOpcode::Maxss => (LegacyPrefixes::_F3, 0x0F5F, 2),
1917
- SseOpcode::Maxsd => (LegacyPrefixes::_F2, 0x0F5F, 2),
1918
- SseOpcode::Minps => (LegacyPrefixes::None, 0x0F5D, 2),
1919
- SseOpcode::Minpd => (LegacyPrefixes::_66, 0x0F5D, 2),
1920
- SseOpcode::Minss => (LegacyPrefixes::_F3, 0x0F5D, 2),
1921
- SseOpcode::Minsd => (LegacyPrefixes::_F2, 0x0F5D, 2),
1922
- SseOpcode::Movlhps => (LegacyPrefixes::None, 0x0F16, 2),
1923
- SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
1924
- SseOpcode::Mulps => (LegacyPrefixes::None, 0x0F59, 2),
1925
- SseOpcode::Mulpd => (LegacyPrefixes::_66, 0x0F59, 2),
1926
- SseOpcode::Mulss => (LegacyPrefixes::_F3, 0x0F59, 2),
1927
- SseOpcode::Mulsd => (LegacyPrefixes::_F2, 0x0F59, 2),
1928
- SseOpcode::Orpd => (LegacyPrefixes::_66, 0x0F56, 2),
1929
- SseOpcode::Orps => (LegacyPrefixes::None, 0x0F56, 2),
1930
- SseOpcode::Packssdw => (LegacyPrefixes::_66, 0x0F6B, 2),
1931
- SseOpcode::Packsswb => (LegacyPrefixes::_66, 0x0F63, 2),
1932
- SseOpcode::Packusdw => (LegacyPrefixes::_66, 0x0F382B, 3),
1933
- SseOpcode::Packuswb => (LegacyPrefixes::_66, 0x0F67, 2),
1934
- SseOpcode::Paddb => (LegacyPrefixes::_66, 0x0FFC, 2),
1935
- SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
1936
- SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
1937
- SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
1938
- SseOpcode::Paddsb => (LegacyPrefixes::_66, 0x0FEC, 2),
1939
- SseOpcode::Paddsw => (LegacyPrefixes::_66, 0x0FED, 2),
1940
- SseOpcode::Paddusb => (LegacyPrefixes::_66, 0x0FDC, 2),
1941
- SseOpcode::Paddusw => (LegacyPrefixes::_66, 0x0FDD, 2),
1942
- SseOpcode::Pmaddubsw => (LegacyPrefixes::_66, 0x0F3804, 3),
1943
- SseOpcode::Pand => (LegacyPrefixes::_66, 0x0FDB, 2),
1944
- SseOpcode::Pandn => (LegacyPrefixes::_66, 0x0FDF, 2),
1945
- SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
1946
- SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
1947
- SseOpcode::Pcmpeqb => (LegacyPrefixes::_66, 0x0F74, 2),
1948
- SseOpcode::Pcmpeqw => (LegacyPrefixes::_66, 0x0F75, 2),
1949
- SseOpcode::Pcmpeqd => (LegacyPrefixes::_66, 0x0F76, 2),
1950
- SseOpcode::Pcmpeqq => (LegacyPrefixes::_66, 0x0F3829, 3),
1951
- SseOpcode::Pcmpgtb => (LegacyPrefixes::_66, 0x0F64, 2),
1952
- SseOpcode::Pcmpgtw => (LegacyPrefixes::_66, 0x0F65, 2),
1953
- SseOpcode::Pcmpgtd => (LegacyPrefixes::_66, 0x0F66, 2),
1954
- SseOpcode::Pcmpgtq => (LegacyPrefixes::_66, 0x0F3837, 3),
1955
- SseOpcode::Pmaddwd => (LegacyPrefixes::_66, 0x0FF5, 2),
1956
- SseOpcode::Pmaxsb => (LegacyPrefixes::_66, 0x0F383C, 3),
1957
- SseOpcode::Pmaxsw => (LegacyPrefixes::_66, 0x0FEE, 2),
1958
- SseOpcode::Pmaxsd => (LegacyPrefixes::_66, 0x0F383D, 3),
1959
- SseOpcode::Pmaxub => (LegacyPrefixes::_66, 0x0FDE, 2),
1960
- SseOpcode::Pmaxuw => (LegacyPrefixes::_66, 0x0F383E, 3),
1961
- SseOpcode::Pmaxud => (LegacyPrefixes::_66, 0x0F383F, 3),
1962
- SseOpcode::Pminsb => (LegacyPrefixes::_66, 0x0F3838, 3),
1963
- SseOpcode::Pminsw => (LegacyPrefixes::_66, 0x0FEA, 2),
1964
- SseOpcode::Pminsd => (LegacyPrefixes::_66, 0x0F3839, 3),
1965
- SseOpcode::Pminub => (LegacyPrefixes::_66, 0x0FDA, 2),
1966
- SseOpcode::Pminuw => (LegacyPrefixes::_66, 0x0F383A, 3),
1967
- SseOpcode::Pminud => (LegacyPrefixes::_66, 0x0F383B, 3),
1968
- SseOpcode::Pmuldq => (LegacyPrefixes::_66, 0x0F3828, 3),
1969
- SseOpcode::Pmulhw => (LegacyPrefixes::_66, 0x0FE5, 2),
1970
- SseOpcode::Pmulhrsw => (LegacyPrefixes::_66, 0x0F380B, 3),
1971
- SseOpcode::Pmulhuw => (LegacyPrefixes::_66, 0x0FE4, 2),
1972
- SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
1973
- SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
1974
- SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
1975
- SseOpcode::Por => (LegacyPrefixes::_66, 0x0FEB, 2),
1976
- SseOpcode::Pshufb => (LegacyPrefixes::_66, 0x0F3800, 3),
1977
- SseOpcode::Psubb => (LegacyPrefixes::_66, 0x0FF8, 2),
1978
- SseOpcode::Psubd => (LegacyPrefixes::_66, 0x0FFA, 2),
1979
- SseOpcode::Psubq => (LegacyPrefixes::_66, 0x0FFB, 2),
1980
- SseOpcode::Psubw => (LegacyPrefixes::_66, 0x0FF9, 2),
1981
- SseOpcode::Psubsb => (LegacyPrefixes::_66, 0x0FE8, 2),
1982
- SseOpcode::Psubsw => (LegacyPrefixes::_66, 0x0FE9, 2),
1983
- SseOpcode::Psubusb => (LegacyPrefixes::_66, 0x0FD8, 2),
1984
- SseOpcode::Psubusw => (LegacyPrefixes::_66, 0x0FD9, 2),
1985
- SseOpcode::Punpckhbw => (LegacyPrefixes::_66, 0x0F68, 2),
1986
- SseOpcode::Punpckhwd => (LegacyPrefixes::_66, 0x0F69, 2),
1987
- SseOpcode::Punpcklbw => (LegacyPrefixes::_66, 0x0F60, 2),
1988
- SseOpcode::Punpcklwd => (LegacyPrefixes::_66, 0x0F61, 2),
1989
- SseOpcode::Punpckldq => (LegacyPrefixes::_66, 0x0F62, 2),
1990
- SseOpcode::Punpcklqdq => (LegacyPrefixes::_66, 0x0F6C, 2),
1991
- SseOpcode::Punpckhdq => (LegacyPrefixes::_66, 0x0F6A, 2),
1992
- SseOpcode::Punpckhqdq => (LegacyPrefixes::_66, 0x0F6D, 2),
1993
- SseOpcode::Pxor => (LegacyPrefixes::_66, 0x0FEF, 2),
1994
- SseOpcode::Subps => (LegacyPrefixes::None, 0x0F5C, 2),
1995
- SseOpcode::Subpd => (LegacyPrefixes::_66, 0x0F5C, 2),
1996
- SseOpcode::Subss => (LegacyPrefixes::_F3, 0x0F5C, 2),
1997
- SseOpcode::Subsd => (LegacyPrefixes::_F2, 0x0F5C, 2),
1998
- SseOpcode::Unpcklps => (LegacyPrefixes::None, 0x0F14, 2),
1999
- SseOpcode::Unpckhps => (LegacyPrefixes::None, 0x0F15, 2),
2000
- SseOpcode::Xorps => (LegacyPrefixes::None, 0x0F57, 2),
2001
- SseOpcode::Xorpd => (LegacyPrefixes::_66, 0x0F57, 2),
2002
- SseOpcode::Phaddw => (LegacyPrefixes::_66, 0x0F3801, 3),
2003
- SseOpcode::Phaddd => (LegacyPrefixes::_66, 0x0F3802, 3),
2004
- _ => unimplemented!("Opcode {:?} not implemented", op),
2005
- };
2006
-
2007
- match src_e {
2008
- RegMem::Reg { reg: reg_e } => {
2009
- emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2010
- }
2011
- RegMem::Mem { addr } => {
2012
- let addr = &addr.finalize(state, sink);
2013
- emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2014
- }
2015
- }
2016
- }
2017
-
2018
- Inst::XmmRmRBlend {
2019
- op,
2020
- src1,
2021
- src2,
2022
- dst,
2023
- mask,
2024
- } => {
2025
- let src1 = allocs.next(src1.to_reg());
2026
- let mask = allocs.next(mask.to_reg());
2027
- debug_assert_eq!(mask, regs::xmm0());
2028
- let reg_g = allocs.next(dst.to_reg().to_reg());
2029
- debug_assert_eq!(src1, reg_g);
2030
- let src_e = src2.clone().to_reg_mem().with_allocs(allocs);
2031
-
2032
- let rex = RexFlags::clear_w();
2033
- let (prefix, opcode, length) = match op {
2034
- SseOpcode::Blendvps => (LegacyPrefixes::_66, 0x0F3814, 3),
2035
- SseOpcode::Blendvpd => (LegacyPrefixes::_66, 0x0F3815, 3),
2036
- SseOpcode::Pblendvb => (LegacyPrefixes::_66, 0x0F3810, 3),
2037
- _ => unimplemented!("Opcode {:?} not implemented", op),
2038
- };
2039
-
2040
- match src_e {
2041
- RegMem::Reg { reg: reg_e } => {
2042
- emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2043
- }
2044
- RegMem::Mem { addr } => {
2045
- let addr = &addr.finalize(state, sink);
2046
- emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2047
- }
2048
- }
2049
- }
2050
-
2051
- Inst::XmmRmiRVex {
2052
- op,
2053
- src1,
2054
- src2,
2055
- dst,
2056
- } => {
2057
- use LegacyPrefixes as LP;
2058
- use OpcodeMap as OM;
2059
-
2060
- let dst = allocs.next(dst.to_reg().to_reg());
2061
- let src1 = allocs.next(src1.to_reg());
2062
- let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
2063
-
2064
- let src2 = match src2 {
2065
- // For opcodes where one of the operands is an immediate the
2066
- // encoding is a bit different, notably the usage of
2067
- // `opcode_ext`, so handle that specially here.
2068
- RegMemImm::Imm { simm32 } => {
2069
- let (opcode, opcode_ext, prefix) = match op {
2070
- AvxOpcode::Vpsrlw => (0x71, 2, LegacyPrefixes::_66),
2071
- AvxOpcode::Vpsrld => (0x72, 2, LegacyPrefixes::_66),
2072
- AvxOpcode::Vpsrlq => (0x73, 2, LegacyPrefixes::_66),
2073
- AvxOpcode::Vpsllw => (0x71, 6, LegacyPrefixes::_66),
2074
- AvxOpcode::Vpslld => (0x72, 6, LegacyPrefixes::_66),
2075
- AvxOpcode::Vpsllq => (0x73, 6, LegacyPrefixes::_66),
2076
- AvxOpcode::Vpsraw => (0x71, 4, LegacyPrefixes::_66),
2077
- AvxOpcode::Vpsrad => (0x72, 4, LegacyPrefixes::_66),
2078
- _ => panic!("unexpected rmi_r_vex opcode with immediate {op:?}"),
2079
- };
2080
- VexInstruction::new()
2081
- .length(VexVectorLength::V128)
2082
- .prefix(prefix)
2083
- .map(OpcodeMap::_0F)
2084
- .opcode(opcode)
2085
- .opcode_ext(opcode_ext)
2086
- .vvvv(dst.to_real_reg().unwrap().hw_enc())
2087
- .prefix(LegacyPrefixes::_66)
2088
- .rm(src1.to_real_reg().unwrap().hw_enc())
2089
- .imm(simm32.try_into().unwrap())
2090
- .encode(sink);
2091
- return;
2092
- }
2093
- RegMemImm::Reg { reg } => {
2094
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2095
- }
2096
- RegMemImm::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2097
- };
2098
- let (prefix, map, opcode) = match op {
2099
- AvxOpcode::Vminps => (LP::None, OM::_0F, 0x5D),
2100
- AvxOpcode::Vminpd => (LP::_66, OM::_0F, 0x5D),
2101
- AvxOpcode::Vmaxps => (LP::None, OM::_0F, 0x5F),
2102
- AvxOpcode::Vmaxpd => (LP::_66, OM::_0F, 0x5F),
2103
- AvxOpcode::Vandnps => (LP::None, OM::_0F, 0x55),
2104
- AvxOpcode::Vandnpd => (LP::_66, OM::_0F, 0x55),
2105
- AvxOpcode::Vpandn => (LP::_66, OM::_0F, 0xDF),
2106
- AvxOpcode::Vpsrlw => (LP::_66, OM::_0F, 0xD1),
2107
- AvxOpcode::Vpsrld => (LP::_66, OM::_0F, 0xD2),
2108
- AvxOpcode::Vpsrlq => (LP::_66, OM::_0F, 0xD3),
2109
- AvxOpcode::Vpaddb => (LP::_66, OM::_0F, 0xFC),
2110
- AvxOpcode::Vpaddw => (LP::_66, OM::_0F, 0xFD),
2111
- AvxOpcode::Vpaddd => (LP::_66, OM::_0F, 0xFE),
2112
- AvxOpcode::Vpaddq => (LP::_66, OM::_0F, 0xD4),
2113
- AvxOpcode::Vpaddsb => (LP::_66, OM::_0F, 0xEC),
2114
- AvxOpcode::Vpaddsw => (LP::_66, OM::_0F, 0xED),
2115
- AvxOpcode::Vpaddusb => (LP::_66, OM::_0F, 0xDC),
2116
- AvxOpcode::Vpaddusw => (LP::_66, OM::_0F, 0xDD),
2117
- AvxOpcode::Vpsubb => (LP::_66, OM::_0F, 0xF8),
2118
- AvxOpcode::Vpsubw => (LP::_66, OM::_0F, 0xF9),
2119
- AvxOpcode::Vpsubd => (LP::_66, OM::_0F, 0xFA),
2120
- AvxOpcode::Vpsubq => (LP::_66, OM::_0F, 0xFB),
2121
- AvxOpcode::Vpsubsb => (LP::_66, OM::_0F, 0xE8),
2122
- AvxOpcode::Vpsubsw => (LP::_66, OM::_0F, 0xE9),
2123
- AvxOpcode::Vpsubusb => (LP::_66, OM::_0F, 0xD8),
2124
- AvxOpcode::Vpsubusw => (LP::_66, OM::_0F, 0xD9),
2125
- AvxOpcode::Vpavgb => (LP::_66, OM::_0F, 0xE0),
2126
- AvxOpcode::Vpavgw => (LP::_66, OM::_0F, 0xE3),
2127
- AvxOpcode::Vpand => (LP::_66, OM::_0F, 0xDB),
2128
- AvxOpcode::Vandps => (LP::None, OM::_0F, 0x54),
2129
- AvxOpcode::Vandpd => (LP::_66, OM::_0F, 0x54),
2130
- AvxOpcode::Vpor => (LP::_66, OM::_0F, 0xEB),
2131
- AvxOpcode::Vorps => (LP::None, OM::_0F, 0x56),
2132
- AvxOpcode::Vorpd => (LP::_66, OM::_0F, 0x56),
2133
- AvxOpcode::Vpxor => (LP::_66, OM::_0F, 0xEF),
2134
- AvxOpcode::Vxorps => (LP::None, OM::_0F, 0x57),
2135
- AvxOpcode::Vxorpd => (LP::_66, OM::_0F, 0x57),
2136
- AvxOpcode::Vpmullw => (LP::_66, OM::_0F, 0xD5),
2137
- AvxOpcode::Vpmulld => (LP::_66, OM::_0F38, 0x40),
2138
- AvxOpcode::Vpmulhw => (LP::_66, OM::_0F, 0xE5),
2139
- AvxOpcode::Vpmulhrsw => (LP::_66, OM::_0F38, 0x0B),
2140
- AvxOpcode::Vpmulhuw => (LP::_66, OM::_0F, 0xE4),
2141
- AvxOpcode::Vpmuldq => (LP::_66, OM::_0F38, 0x28),
2142
- AvxOpcode::Vpmuludq => (LP::_66, OM::_0F, 0xF4),
2143
- AvxOpcode::Vpunpckhwd => (LP::_66, OM::_0F, 0x69),
2144
- AvxOpcode::Vpunpcklwd => (LP::_66, OM::_0F, 0x61),
2145
- AvxOpcode::Vunpcklps => (LP::None, OM::_0F, 0x14),
2146
- AvxOpcode::Vunpckhps => (LP::None, OM::_0F, 0x15),
2147
- AvxOpcode::Vaddps => (LP::None, OM::_0F, 0x58),
2148
- AvxOpcode::Vaddpd => (LP::_66, OM::_0F, 0x58),
2149
- AvxOpcode::Vsubps => (LP::None, OM::_0F, 0x5C),
2150
- AvxOpcode::Vsubpd => (LP::_66, OM::_0F, 0x5C),
2151
- AvxOpcode::Vmulps => (LP::None, OM::_0F, 0x59),
2152
- AvxOpcode::Vmulpd => (LP::_66, OM::_0F, 0x59),
2153
- AvxOpcode::Vdivps => (LP::None, OM::_0F, 0x5E),
2154
- AvxOpcode::Vdivpd => (LP::_66, OM::_0F, 0x5E),
2155
- AvxOpcode::Vpcmpeqb => (LP::_66, OM::_0F, 0x74),
2156
- AvxOpcode::Vpcmpeqw => (LP::_66, OM::_0F, 0x75),
2157
- AvxOpcode::Vpcmpeqd => (LP::_66, OM::_0F, 0x76),
2158
- AvxOpcode::Vpcmpeqq => (LP::_66, OM::_0F38, 0x29),
2159
- AvxOpcode::Vpcmpgtb => (LP::_66, OM::_0F, 0x64),
2160
- AvxOpcode::Vpcmpgtw => (LP::_66, OM::_0F, 0x65),
2161
- AvxOpcode::Vpcmpgtd => (LP::_66, OM::_0F, 0x66),
2162
- AvxOpcode::Vpcmpgtq => (LP::_66, OM::_0F38, 0x37),
2163
- AvxOpcode::Vmovlhps => (LP::None, OM::_0F, 0x16),
2164
- AvxOpcode::Vpminsb => (LP::_66, OM::_0F38, 0x38),
2165
- AvxOpcode::Vpminsw => (LP::_66, OM::_0F, 0xEA),
2166
- AvxOpcode::Vpminsd => (LP::_66, OM::_0F38, 0x39),
2167
- AvxOpcode::Vpmaxsb => (LP::_66, OM::_0F38, 0x3C),
2168
- AvxOpcode::Vpmaxsw => (LP::_66, OM::_0F, 0xEE),
2169
- AvxOpcode::Vpmaxsd => (LP::_66, OM::_0F38, 0x3D),
2170
- AvxOpcode::Vpminub => (LP::_66, OM::_0F, 0xDA),
2171
- AvxOpcode::Vpminuw => (LP::_66, OM::_0F38, 0x3A),
2172
- AvxOpcode::Vpminud => (LP::_66, OM::_0F38, 0x3B),
2173
- AvxOpcode::Vpmaxub => (LP::_66, OM::_0F, 0xDE),
2174
- AvxOpcode::Vpmaxuw => (LP::_66, OM::_0F38, 0x3E),
2175
- AvxOpcode::Vpmaxud => (LP::_66, OM::_0F38, 0x3F),
2176
- AvxOpcode::Vpunpcklbw => (LP::_66, OM::_0F, 0x60),
2177
- AvxOpcode::Vpunpckhbw => (LP::_66, OM::_0F, 0x68),
2178
- AvxOpcode::Vpacksswb => (LP::_66, OM::_0F, 0x63),
2179
- AvxOpcode::Vpackssdw => (LP::_66, OM::_0F, 0x6B),
2180
- AvxOpcode::Vpackuswb => (LP::_66, OM::_0F, 0x67),
2181
- AvxOpcode::Vpackusdw => (LP::_66, OM::_0F38, 0x2B),
2182
- AvxOpcode::Vpmaddwd => (LP::_66, OM::_0F, 0xF5),
2183
- AvxOpcode::Vpmaddubsw => (LP::_66, OM::_0F38, 0x04),
2184
- AvxOpcode::Vpshufb => (LP::_66, OM::_0F38, 0x00),
2185
- AvxOpcode::Vpsllw => (LP::_66, OM::_0F, 0xF1),
2186
- AvxOpcode::Vpslld => (LP::_66, OM::_0F, 0xF2),
2187
- AvxOpcode::Vpsllq => (LP::_66, OM::_0F, 0xF3),
2188
- AvxOpcode::Vpsraw => (LP::_66, OM::_0F, 0xE1),
2189
- AvxOpcode::Vpsrad => (LP::_66, OM::_0F, 0xE2),
2190
- AvxOpcode::Vaddss => (LP::_F3, OM::_0F, 0x58),
2191
- AvxOpcode::Vaddsd => (LP::_F2, OM::_0F, 0x58),
2192
- AvxOpcode::Vmulss => (LP::_F3, OM::_0F, 0x59),
2193
- AvxOpcode::Vmulsd => (LP::_F2, OM::_0F, 0x59),
2194
- AvxOpcode::Vsubss => (LP::_F3, OM::_0F, 0x5C),
2195
- AvxOpcode::Vsubsd => (LP::_F2, OM::_0F, 0x5C),
2196
- AvxOpcode::Vdivss => (LP::_F3, OM::_0F, 0x5E),
2197
- AvxOpcode::Vdivsd => (LP::_F2, OM::_0F, 0x5E),
2198
- AvxOpcode::Vminss => (LP::_F3, OM::_0F, 0x5D),
2199
- AvxOpcode::Vminsd => (LP::_F2, OM::_0F, 0x5D),
2200
- AvxOpcode::Vmaxss => (LP::_F3, OM::_0F, 0x5F),
2201
- AvxOpcode::Vmaxsd => (LP::_F2, OM::_0F, 0x5F),
2202
- AvxOpcode::Vphaddw => (LP::_66, OM::_0F38, 0x01),
2203
- AvxOpcode::Vphaddd => (LP::_66, OM::_0F38, 0x02),
2204
- AvxOpcode::Vpunpckldq => (LP::_66, OM::_0F, 0x62),
2205
- AvxOpcode::Vpunpckhdq => (LP::_66, OM::_0F, 0x6A),
2206
- AvxOpcode::Vpunpcklqdq => (LP::_66, OM::_0F, 0x6C),
2207
- AvxOpcode::Vpunpckhqdq => (LP::_66, OM::_0F, 0x6D),
2208
- AvxOpcode::Vmovsd => (LP::_F2, OM::_0F, 0x10),
2209
- _ => panic!("unexpected rmir vex opcode {op:?}"),
2210
- };
2211
- VexInstruction::new()
2212
- .length(VexVectorLength::V128)
2213
- .prefix(prefix)
2214
- .map(map)
2215
- .opcode(opcode)
2216
- .reg(dst.to_real_reg().unwrap().hw_enc())
2217
- .vvvv(src1.to_real_reg().unwrap().hw_enc())
2218
- .rm(src2)
2219
- .encode(sink);
2220
- }
2221
-
2222
- Inst::XmmRmRImmVex {
2223
- op,
2224
- src1,
2225
- src2,
2226
- dst,
2227
- imm,
2228
- } => {
2229
- let dst = allocs.next(dst.to_reg().to_reg());
2230
- let src1 = allocs.next(src1.to_reg());
2231
- let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2232
- RegMem::Reg { reg } => {
2233
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2234
- }
2235
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2236
- };
2237
-
2238
- let (w, prefix, map, opcode) = match op {
2239
- AvxOpcode::Vcmpps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC2),
2240
- AvxOpcode::Vcmppd => (false, LegacyPrefixes::_66, OpcodeMap::_0F, 0xC2),
2241
- AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
2242
- AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
2243
- AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
2244
- AvxOpcode::Vpblendw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0E),
2245
- _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2246
- };
2247
-
2248
- VexInstruction::new()
2249
- .length(VexVectorLength::V128)
2250
- .prefix(prefix)
2251
- .map(map)
2252
- .w(w)
2253
- .opcode(opcode)
2254
- .reg(dst.to_real_reg().unwrap().hw_enc())
2255
- .vvvv(src1.to_real_reg().unwrap().hw_enc())
2256
- .rm(src2)
2257
- .imm(*imm)
2258
- .encode(sink);
2259
- }
2260
-
2261
- Inst::XmmVexPinsr {
2262
- op,
2263
- src1,
2264
- src2,
2265
- dst,
2266
- imm,
2267
- } => {
2268
- let dst = allocs.next(dst.to_reg().to_reg());
2269
- let src1 = allocs.next(src1.to_reg());
2270
- let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2271
- RegMem::Reg { reg } => {
2272
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2273
- }
2274
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2275
- };
2276
-
2277
- let (w, map, opcode) = match op {
2278
- AvxOpcode::Vpinsrb => (false, OpcodeMap::_0F3A, 0x20),
2279
- AvxOpcode::Vpinsrw => (false, OpcodeMap::_0F, 0xC4),
2280
- AvxOpcode::Vpinsrd => (false, OpcodeMap::_0F3A, 0x22),
2281
- AvxOpcode::Vpinsrq => (true, OpcodeMap::_0F3A, 0x22),
2282
- _ => panic!("unexpected vex_pinsr opcode {op:?}"),
2283
- };
2284
-
2285
- VexInstruction::new()
2286
- .length(VexVectorLength::V128)
2287
- .prefix(LegacyPrefixes::_66)
2288
- .map(map)
2289
- .w(w)
2290
- .opcode(opcode)
2291
- .reg(dst.to_real_reg().unwrap().hw_enc())
2292
- .vvvv(src1.to_real_reg().unwrap().hw_enc())
2293
- .rm(src2)
2294
- .imm(*imm)
2295
- .encode(sink);
2296
- }
2297
-
2298
- Inst::XmmRmRVex3 {
2299
- op,
2300
- src1,
2301
- src2,
2302
- src3,
2303
- dst,
2304
- } => {
2305
- let src1 = allocs.next(src1.to_reg());
2306
- let dst = allocs.next(dst.to_reg().to_reg());
2307
- debug_assert_eq!(src1, dst);
2308
- let src2 = allocs.next(src2.to_reg());
2309
- let src3 = match src3.clone().to_reg_mem().with_allocs(allocs) {
2310
- RegMem::Reg { reg } => {
2311
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2312
- }
2313
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2314
- };
2315
-
2316
- let (w, map, opcode) = match op {
2317
- AvxOpcode::Vfmadd132ss => (false, OpcodeMap::_0F38, 0x99),
2318
- AvxOpcode::Vfmadd213ss => (false, OpcodeMap::_0F38, 0xA9),
2319
- AvxOpcode::Vfnmadd132ss => (false, OpcodeMap::_0F38, 0x9D),
2320
- AvxOpcode::Vfnmadd213ss => (false, OpcodeMap::_0F38, 0xAD),
2321
- AvxOpcode::Vfmadd132sd => (true, OpcodeMap::_0F38, 0x99),
2322
- AvxOpcode::Vfmadd213sd => (true, OpcodeMap::_0F38, 0xA9),
2323
- AvxOpcode::Vfnmadd132sd => (true, OpcodeMap::_0F38, 0x9D),
2324
- AvxOpcode::Vfnmadd213sd => (true, OpcodeMap::_0F38, 0xAD),
2325
- AvxOpcode::Vfmadd132ps => (false, OpcodeMap::_0F38, 0x98),
2326
- AvxOpcode::Vfmadd213ps => (false, OpcodeMap::_0F38, 0xA8),
2327
- AvxOpcode::Vfnmadd132ps => (false, OpcodeMap::_0F38, 0x9C),
2328
- AvxOpcode::Vfnmadd213ps => (false, OpcodeMap::_0F38, 0xAC),
2329
- AvxOpcode::Vfmadd132pd => (true, OpcodeMap::_0F38, 0x98),
2330
- AvxOpcode::Vfmadd213pd => (true, OpcodeMap::_0F38, 0xA8),
2331
- AvxOpcode::Vfnmadd132pd => (true, OpcodeMap::_0F38, 0x9C),
2332
- AvxOpcode::Vfnmadd213pd => (true, OpcodeMap::_0F38, 0xAC),
2333
- AvxOpcode::Vblendvps => (false, OpcodeMap::_0F3A, 0x4A),
2334
- AvxOpcode::Vblendvpd => (false, OpcodeMap::_0F3A, 0x4B),
2335
- AvxOpcode::Vpblendvb => (false, OpcodeMap::_0F3A, 0x4C),
2336
- _ => unreachable!(),
2337
- };
2338
-
2339
- VexInstruction::new()
2340
- .length(VexVectorLength::V128)
2341
- .prefix(LegacyPrefixes::_66)
2342
- .map(map)
2343
- .w(w)
2344
- .opcode(opcode)
2345
- .reg(dst.to_real_reg().unwrap().hw_enc())
2346
- .rm(src3)
2347
- .vvvv(src2.to_real_reg().unwrap().hw_enc())
2348
- .encode(sink);
2349
- }
2350
-
2351
- Inst::XmmRmRBlendVex {
2352
- op,
2353
- src1,
2354
- src2,
2355
- mask,
2356
- dst,
2357
- } => {
2358
- let dst = allocs.next(dst.to_reg().to_reg());
2359
- let src1 = allocs.next(src1.to_reg());
2360
- let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2361
- RegMem::Reg { reg } => {
2362
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2363
- }
2364
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2365
- };
2366
- let mask = allocs.next(mask.to_reg());
2367
-
2368
- let opcode = match op {
2369
- AvxOpcode::Vblendvps => 0x4A,
2370
- AvxOpcode::Vblendvpd => 0x4B,
2371
- AvxOpcode::Vpblendvb => 0x4C,
2372
- _ => unreachable!(),
2373
- };
2374
-
2375
- VexInstruction::new()
2376
- .length(VexVectorLength::V128)
2377
- .prefix(LegacyPrefixes::_66)
2378
- .map(OpcodeMap::_0F3A)
2379
- .opcode(opcode)
2380
- .reg(dst.to_real_reg().unwrap().hw_enc())
2381
- .vvvv(src1.to_real_reg().unwrap().hw_enc())
2382
- .rm(src2)
2383
- .imm(mask.to_real_reg().unwrap().hw_enc() << 4)
2384
- .encode(sink);
2385
- }
2386
-
2387
- Inst::XmmUnaryRmRVex { op, src, dst } => {
2388
- let dst = allocs.next(dst.to_reg().to_reg());
2389
- let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2390
- RegMem::Reg { reg } => {
2391
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2392
- }
2393
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2394
- };
2395
-
2396
- let (prefix, map, opcode) = match op {
2397
- AvxOpcode::Vpmovsxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x20),
2398
- AvxOpcode::Vpmovzxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x30),
2399
- AvxOpcode::Vpmovsxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x23),
2400
- AvxOpcode::Vpmovzxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x33),
2401
- AvxOpcode::Vpmovsxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x25),
2402
- AvxOpcode::Vpmovzxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x35),
2403
- AvxOpcode::Vpabsb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1C),
2404
- AvxOpcode::Vpabsw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1D),
2405
- AvxOpcode::Vpabsd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1E),
2406
- AvxOpcode::Vsqrtps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x51),
2407
- AvxOpcode::Vsqrtpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x51),
2408
- AvxOpcode::Vcvtdq2pd => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0xE6),
2409
- AvxOpcode::Vcvtdq2ps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5B),
2410
- AvxOpcode::Vcvtpd2ps => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x5A),
2411
- AvxOpcode::Vcvtps2pd => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5A),
2412
- AvxOpcode::Vcvttpd2dq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xE6),
2413
- AvxOpcode::Vcvttps2dq => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x5B),
2414
- AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x6F),
2415
- AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x10),
2416
- AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x10),
2417
-
2418
- // Note that for `vmov{s,d}` the `inst.isle` rules should
2419
- // statically ensure that only `Amode` operands are used here.
2420
- // Otherwise the other encodings of `vmovss` are more like
2421
- // 2-operand instructions which this unary encoding does not
2422
- // have.
2423
- AvxOpcode::Vmovss => match &src {
2424
- RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x10),
2425
- _ => unreachable!(),
2426
- },
2427
- AvxOpcode::Vmovsd => match &src {
2428
- RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x10),
2429
- _ => unreachable!(),
2430
- },
2431
-
2432
- AvxOpcode::Vpbroadcastb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x78),
2433
- AvxOpcode::Vpbroadcastw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x79),
2434
- AvxOpcode::Vpbroadcastd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x58),
2435
- AvxOpcode::Vbroadcastss => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x18),
2436
- AvxOpcode::Vmovddup => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x12),
2437
-
2438
- AvxOpcode::Vcvtss2sd => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x5A),
2439
- AvxOpcode::Vcvtsd2ss => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x5A),
2440
- AvxOpcode::Vsqrtss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x51),
2441
- AvxOpcode::Vsqrtsd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x51),
2442
-
2443
- _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2444
- };
2445
-
2446
- let vex = VexInstruction::new()
2447
- .length(VexVectorLength::V128)
2448
- .prefix(prefix)
2449
- .map(map)
2450
- .opcode(opcode)
2451
- .reg(dst.to_real_reg().unwrap().hw_enc())
2452
- .rm(src);
2453
-
2454
- // These opcodes take a second operand through `vvvv` which copies
2455
- // the upper bits into the destination register. That's not
2456
- // reflected in the CLIF instruction, however, since the SSE version
2457
- // doesn't have this functionality. Instead just copy whatever
2458
- // happens to already be in the destination, which at least is what
2459
- // LLVM seems to do.
2460
- let vex = match op {
2461
- AvxOpcode::Vcvtss2sd
2462
- | AvxOpcode::Vcvtsd2ss
2463
- | AvxOpcode::Vsqrtss
2464
- | AvxOpcode::Vsqrtsd => vex.vvvv(dst.to_real_reg().unwrap().hw_enc()),
2465
- _ => vex,
2466
- };
2467
- vex.encode(sink);
2468
- }
2469
-
2470
- Inst::XmmUnaryRmRImmVex { op, src, dst, imm } => {
2471
- let dst = allocs.next(dst.to_reg().to_reg());
2472
- let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2473
- RegMem::Reg { reg } => {
2474
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2475
- }
2476
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2477
- };
2478
-
2479
- let (prefix, map, opcode) = match op {
2480
- AvxOpcode::Vroundps => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x08),
2481
- AvxOpcode::Vroundpd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x09),
2482
- AvxOpcode::Vpshuflw => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x70),
2483
- AvxOpcode::Vpshufhw => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x70),
2484
- AvxOpcode::Vpshufd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x70),
2485
- AvxOpcode::Vroundss => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0A),
2486
- AvxOpcode::Vroundsd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0B),
2487
- _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2488
- };
2489
-
2490
- let vex = VexInstruction::new()
2491
- .length(VexVectorLength::V128)
2492
- .prefix(prefix)
2493
- .map(map)
2494
- .opcode(opcode)
2495
- .reg(dst.to_real_reg().unwrap().hw_enc())
2496
- .rm(src)
2497
- .imm(*imm);
2498
-
2499
- // See comments in similar block above in `XmmUnaryRmRVex` for what
2500
- // this is doing.
2501
- let vex = match op {
2502
- AvxOpcode::Vroundss | AvxOpcode::Vroundsd => {
2503
- vex.vvvv(dst.to_real_reg().unwrap().hw_enc())
2504
- }
2505
- _ => vex,
2506
- };
2507
- vex.encode(sink);
2508
- }
2509
-
2510
- Inst::XmmMovRMVex { op, src, dst } => {
2511
- let src = allocs.next(src.to_reg());
2512
- let dst = dst.with_allocs(allocs).finalize(state, sink);
2513
-
2514
- let (prefix, map, opcode) = match op {
2515
- AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x7F),
2516
- AvxOpcode::Vmovss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x11),
2517
- AvxOpcode::Vmovsd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x11),
2518
- AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x11),
2519
- AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x11),
2520
- _ => unimplemented!("Opcode {:?} not implemented", op),
2521
- };
2522
- VexInstruction::new()
2523
- .length(VexVectorLength::V128)
2524
- .prefix(prefix)
2525
- .map(map)
2526
- .opcode(opcode)
2527
- .rm(dst)
2528
- .reg(src.to_real_reg().unwrap().hw_enc())
2529
- .encode(sink);
2530
- }
2531
-
2532
- Inst::XmmMovRMImmVex { op, src, dst, imm } => {
2533
- let src = allocs.next(src.to_reg());
2534
- let dst = dst.with_allocs(allocs).finalize(state, sink);
2535
-
2536
- let (w, prefix, map, opcode) = match op {
2537
- AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2538
- AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2539
- AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2540
- AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2541
- _ => unimplemented!("Opcode {:?} not implemented", op),
2542
- };
2543
- VexInstruction::new()
2544
- .length(VexVectorLength::V128)
2545
- .w(w)
2546
- .prefix(prefix)
2547
- .map(map)
2548
- .opcode(opcode)
2549
- .rm(dst)
2550
- .reg(src.to_real_reg().unwrap().hw_enc())
2551
- .imm(*imm)
2552
- .encode(sink);
2553
- }
2554
-
2555
- Inst::XmmToGprImmVex { op, src, dst, imm } => {
2556
- let src = allocs.next(src.to_reg());
2557
- let dst = allocs.next(dst.to_reg().to_reg());
2558
-
2559
- let (w, prefix, map, opcode) = match op {
2560
- AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2561
- AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2562
- AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2563
- AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2564
- _ => unimplemented!("Opcode {:?} not implemented", op),
2565
- };
2566
- VexInstruction::new()
2567
- .length(VexVectorLength::V128)
2568
- .w(w)
2569
- .prefix(prefix)
2570
- .map(map)
2571
- .opcode(opcode)
2572
- .rm(dst.to_real_reg().unwrap().hw_enc())
2573
- .reg(src.to_real_reg().unwrap().hw_enc())
2574
- .imm(*imm)
2575
- .encode(sink);
2576
- }
2577
-
2578
- Inst::XmmToGprVex {
2579
- op,
2580
- src,
2581
- dst,
2582
- dst_size,
2583
- } => {
2584
- let src = allocs.next(src.to_reg());
2585
- let dst = allocs.next(dst.to_reg().to_reg());
2586
-
2587
- let (prefix, map, opcode) = match op {
2588
- // vmovd/vmovq are differentiated by `w`
2589
- AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x7E),
2590
- AvxOpcode::Vmovmskps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x50),
2591
- AvxOpcode::Vmovmskpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x50),
2592
- AvxOpcode::Vpmovmskb => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xD7),
2593
- _ => unimplemented!("Opcode {:?} not implemented", op),
2594
- };
2595
- let w = match dst_size {
2596
- OperandSize::Size64 => true,
2597
- _ => false,
2598
- };
2599
- let mut vex = VexInstruction::new()
2600
- .length(VexVectorLength::V128)
2601
- .w(w)
2602
- .prefix(prefix)
2603
- .map(map)
2604
- .opcode(opcode);
2605
- vex = match op {
2606
- // The `vmovq/vmovd` reverse the order of the destination/source
2607
- // relative to other opcodes using this shape of instruction.
2608
- AvxOpcode::Vmovd | AvxOpcode::Vmovq => vex
2609
- .rm(dst.to_real_reg().unwrap().hw_enc())
2610
- .reg(src.to_real_reg().unwrap().hw_enc()),
2611
- _ => vex
2612
- .rm(src.to_real_reg().unwrap().hw_enc())
2613
- .reg(dst.to_real_reg().unwrap().hw_enc()),
2614
- };
2615
- vex.encode(sink);
2616
- }
2617
-
2618
- Inst::GprToXmmVex {
2619
- op,
2620
- src,
2621
- dst,
2622
- src_size,
2623
- } => {
2624
- let dst = allocs.next(dst.to_reg().to_reg());
2625
- let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2626
- RegMem::Reg { reg } => {
2627
- RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2628
- }
2629
- RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2630
- };
2631
-
2632
- let (prefix, map, opcode) = match op {
2633
- // vmovd/vmovq are differentiated by `w`
2634
- AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x6E),
2635
- AvxOpcode::Vcvtsi2ss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x2A),
2636
- AvxOpcode::Vcvtsi2sd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x2A),
2637
- _ => unimplemented!("Opcode {:?} not implemented", op),
2638
- };
2639
- let w = match src_size {
2640
- OperandSize::Size64 => true,
2641
- _ => false,
2642
- };
2643
- let mut insn = VexInstruction::new()
2644
- .length(VexVectorLength::V128)
2645
- .w(w)
2646
- .prefix(prefix)
2647
- .map(map)
2648
- .opcode(opcode)
2649
- .rm(src)
2650
- .reg(dst.to_real_reg().unwrap().hw_enc());
2651
- // These opcodes technically take a second operand which is the
2652
- // upper bits to preserve during the float conversion. We don't
2653
- // actually use this in this backend right now so reuse the
2654
- // destination register. This at least matches what LLVM does.
2655
- if let AvxOpcode::Vcvtsi2ss | AvxOpcode::Vcvtsi2sd = op {
2656
- insn = insn.vvvv(dst.to_real_reg().unwrap().hw_enc());
2657
- }
2658
- insn.encode(sink);
2659
- }
2660
-
2661
- Inst::XmmRmREvex {
2662
- op,
2663
- src1,
2664
- src2,
2665
- dst,
2666
- }
2667
- | Inst::XmmRmREvex3 {
2668
- op,
2669
- src1,
2670
- src2,
2671
- dst,
2672
- // `dst` reuses `src3`.
2673
- ..
2674
- } => {
2675
- let dst = allocs.next(dst.to_reg().to_reg());
2676
- let src2 = allocs.next(src2.to_reg());
2677
- if let Inst::XmmRmREvex3 { src3, .. } = inst {
2678
- let src3 = allocs.next(src3.to_reg());
2679
- debug_assert_eq!(src3, dst);
2680
- }
2681
- let src1 = src1.clone().to_reg_mem().with_allocs(allocs);
2682
-
2683
- let (w, opcode) = match op {
2684
- Avx512Opcode::Vpermi2b => (false, 0x75),
2685
- Avx512Opcode::Vpmullq => (true, 0x40),
2686
- _ => unimplemented!("Opcode {:?} not implemented", op),
2687
- };
2688
- match src1 {
2689
- RegMem::Reg { reg: src } => EvexInstruction::new()
2690
- .length(EvexVectorLength::V128)
2691
- .prefix(LegacyPrefixes::_66)
2692
- .map(OpcodeMap::_0F38)
2693
- .w(w)
2694
- .opcode(opcode)
2695
- .reg(dst.to_real_reg().unwrap().hw_enc())
2696
- .rm(src.to_real_reg().unwrap().hw_enc())
2697
- .vvvvv(src2.to_real_reg().unwrap().hw_enc())
2698
- .encode(sink),
2699
- _ => todo!(),
2700
- };
2701
- }
2702
-
2703
- Inst::XmmMinMaxSeq {
2704
- size,
2705
- is_min,
2706
- lhs,
2707
- rhs,
2708
- dst,
2709
- } => {
2710
- let rhs = allocs.next(rhs.to_reg());
2711
- let lhs = allocs.next(lhs.to_reg());
2712
- let dst = allocs.next(dst.to_reg().to_reg());
2713
- debug_assert_eq!(rhs, dst);
2714
-
2715
- // Generates the following sequence:
2716
- // cmpss/cmpsd %lhs, %rhs_dst
2717
- // jnz do_min_max
2718
- // jp propagate_nan
2719
- //
2720
- // ;; ordered and equal: propagate the sign bit (for -0 vs 0):
2721
- // {and,or}{ss,sd} %lhs, %rhs_dst
2722
- // j done
2723
- //
2724
- // ;; to get the desired NaN behavior (signalling NaN transformed into a quiet NaN, the
2725
- // ;; NaN value is returned), we add both inputs.
2726
- // propagate_nan:
2727
- // add{ss,sd} %lhs, %rhs_dst
2728
- // j done
2729
- //
2730
- // do_min_max:
2731
- // {min,max}{ss,sd} %lhs, %rhs_dst
2732
- //
2733
- // done:
2734
- let done = sink.get_label();
2735
- let propagate_nan = sink.get_label();
2736
- let do_min_max = sink.get_label();
2737
-
2738
- let (add_op, cmp_op, and_op, or_op, min_max_op) = match size {
2739
- OperandSize::Size32 => (
2740
- SseOpcode::Addss,
2741
- SseOpcode::Ucomiss,
2742
- SseOpcode::Andps,
2743
- SseOpcode::Orps,
2744
- if *is_min {
2745
- SseOpcode::Minss
2746
- } else {
2747
- SseOpcode::Maxss
2748
- },
2749
- ),
2750
- OperandSize::Size64 => (
2751
- SseOpcode::Addsd,
2752
- SseOpcode::Ucomisd,
2753
- SseOpcode::Andpd,
2754
- SseOpcode::Orpd,
2755
- if *is_min {
2756
- SseOpcode::Minsd
2757
- } else {
2758
- SseOpcode::Maxsd
2759
- },
2760
- ),
2761
- _ => unreachable!(),
2762
- };
2763
-
2764
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(lhs), dst);
2765
- inst.emit(&[], sink, info, state);
2766
-
2767
- one_way_jmp(sink, CC::NZ, do_min_max);
2768
- one_way_jmp(sink, CC::P, propagate_nan);
2769
-
2770
- // Ordered and equal. The operands are bit-identical unless they are zero
2771
- // and negative zero. These instructions merge the sign bits in that
2772
- // case, and are no-ops otherwise.
2773
- let op = if *is_min { or_op } else { and_op };
2774
- let inst = Inst::xmm_rm_r(op, RegMem::reg(lhs), Writable::from_reg(dst));
2775
- inst.emit(&[], sink, info, state);
2776
-
2777
- let inst = Inst::jmp_known(done);
2778
- inst.emit(&[], sink, info, state);
2779
-
2780
- // x86's min/max are not symmetric; if either operand is a NaN, they return the
2781
- // read-only operand: perform an addition between the two operands, which has the
2782
- // desired NaN propagation effects.
2783
- sink.bind_label(propagate_nan, &mut state.ctrl_plane);
2784
- let inst = Inst::xmm_rm_r(add_op, RegMem::reg(lhs), Writable::from_reg(dst));
2785
- inst.emit(&[], sink, info, state);
2786
-
2787
- one_way_jmp(sink, CC::P, done);
2788
-
2789
- sink.bind_label(do_min_max, &mut state.ctrl_plane);
2790
-
2791
- let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(lhs), Writable::from_reg(dst));
2792
- inst.emit(&[], sink, info, state);
2793
-
2794
- sink.bind_label(done, &mut state.ctrl_plane);
2795
- }
2796
-
2797
- Inst::XmmRmRImm {
2798
- op,
2799
- src1,
2800
- src2,
2801
- dst,
2802
- imm,
2803
- size,
2804
- } => {
2805
- let src1 = allocs.next(*src1);
2806
- let dst = allocs.next(dst.to_reg());
2807
- let src2 = src2.with_allocs(allocs);
2808
- debug_assert_eq!(src1, dst);
2809
-
2810
- let (prefix, opcode, len) = match op {
2811
- SseOpcode::Cmpps => (LegacyPrefixes::None, 0x0FC2, 2),
2812
- SseOpcode::Cmppd => (LegacyPrefixes::_66, 0x0FC2, 2),
2813
- SseOpcode::Cmpss => (LegacyPrefixes::_F3, 0x0FC2, 2),
2814
- SseOpcode::Cmpsd => (LegacyPrefixes::_F2, 0x0FC2, 2),
2815
- SseOpcode::Insertps => (LegacyPrefixes::_66, 0x0F3A21, 3),
2816
- SseOpcode::Palignr => (LegacyPrefixes::_66, 0x0F3A0F, 3),
2817
- SseOpcode::Pinsrb => (LegacyPrefixes::_66, 0x0F3A20, 3),
2818
- SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
2819
- SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
2820
- SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
2821
- SseOpcode::Pblendw => (LegacyPrefixes::_66, 0x0F3A0E, 3),
2822
- _ => unimplemented!("Opcode {:?} not implemented", op),
2823
- };
2824
- let rex = RexFlags::from(*size);
2825
- let regs_swapped = match *op {
2826
- // These opcodes (and not the SSE2 version of PEXTRW) flip the operand
2827
- // encoding: `dst` in ModRM's r/m, `src` in ModRM's reg field.
2828
- SseOpcode::Pextrb | SseOpcode::Pextrd => true,
2829
- // The rest of the opcodes have the customary encoding: `dst` in ModRM's reg,
2830
- // `src` in ModRM's r/m field.
2831
- _ => false,
2832
- };
2833
- match src2 {
2834
- RegMem::Reg { reg } => {
2835
- if regs_swapped {
2836
- emit_std_reg_reg(sink, prefix, opcode, len, reg, dst, rex);
2837
- } else {
2838
- emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
2839
- }
2840
- }
2841
- RegMem::Mem { addr } => {
2842
- let addr = &addr.finalize(state, sink);
2843
- assert!(
2844
- !regs_swapped,
2845
- "No existing way to encode a mem argument in the ModRM r/m field."
2846
- );
2847
- // N.B.: bytes_at_end == 1, because of the `imm` byte below.
2848
- emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
2849
- }
2850
- }
2851
- sink.put1(*imm);
2852
- }
2853
-
2854
- Inst::XmmUninitializedValue { .. } => {
2855
- // This instruction format only exists to declare a register as a `def`; no code is
2856
- // emitted.
2857
- }
2858
-
2859
- Inst::XmmMovRM { op, src, dst } => {
2860
- let src = allocs.next(src.to_reg());
2861
- let dst = dst.with_allocs(allocs);
2862
-
2863
- let (prefix, opcode) = match op {
2864
- SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F29),
2865
- SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F29),
2866
- SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F7F),
2867
- SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F11),
2868
- SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F11),
2869
- SseOpcode::Movups => (LegacyPrefixes::None, 0x0F11),
2870
- SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F11),
2871
- _ => unimplemented!("Opcode {:?} not implemented", op),
2872
- };
2873
- let dst = &dst.finalize(state, sink);
2874
- emit_std_reg_mem(sink, prefix, opcode, 2, src, dst, RexFlags::clear_w(), 0);
2875
- }
2876
-
2877
- Inst::XmmMovRMImm { op, src, dst, imm } => {
2878
- let src = allocs.next(src.to_reg());
2879
- let dst = dst.with_allocs(allocs);
2880
-
2881
- let (w, prefix, opcode) = match op {
2882
- SseOpcode::Pextrb => (false, LegacyPrefixes::_66, 0x0F3A14),
2883
- SseOpcode::Pextrw => (false, LegacyPrefixes::_66, 0x0F3A15),
2884
- SseOpcode::Pextrd => (false, LegacyPrefixes::_66, 0x0F3A16),
2885
- SseOpcode::Pextrq => (true, LegacyPrefixes::_66, 0x0F3A16),
2886
- _ => unimplemented!("Opcode {:?} not implemented", op),
2887
- };
2888
- let rex = if w {
2889
- RexFlags::set_w()
2890
- } else {
2891
- RexFlags::clear_w()
2892
- };
2893
- let dst = &dst.finalize(state, sink);
2894
- emit_std_reg_mem(sink, prefix, opcode, 3, src, dst, rex, 1);
2895
- sink.put1(*imm);
2896
- }
2897
-
2898
- Inst::XmmToGpr {
2899
- op,
2900
- src,
2901
- dst,
2902
- dst_size,
2903
- } => {
2904
- let src = allocs.next(src.to_reg());
2905
- let dst = allocs.next(dst.to_reg().to_reg());
2906
-
2907
- let (prefix, opcode, dst_first) = match op {
2908
- SseOpcode::Cvttss2si => (LegacyPrefixes::_F3, 0x0F2C, true),
2909
- SseOpcode::Cvttsd2si => (LegacyPrefixes::_F2, 0x0F2C, true),
2910
- // Movd and movq use the same opcode; the presence of the REX prefix (set below)
2911
- // actually determines which is used.
2912
- SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F7E, false),
2913
- SseOpcode::Movmskps => (LegacyPrefixes::None, 0x0F50, true),
2914
- SseOpcode::Movmskpd => (LegacyPrefixes::_66, 0x0F50, true),
2915
- SseOpcode::Pmovmskb => (LegacyPrefixes::_66, 0x0FD7, true),
2916
- _ => panic!("unexpected opcode {:?}", op),
2917
- };
2918
- let rex = RexFlags::from(*dst_size);
2919
- let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
2920
-
2921
- emit_std_reg_reg(sink, prefix, opcode, 2, src, dst, rex);
2922
- }
2923
-
2924
- Inst::XmmToGprImm { op, src, dst, imm } => {
2925
- use OperandSize as OS;
2926
-
2927
- let src = allocs.next(src.to_reg());
2928
- let dst = allocs.next(dst.to_reg().to_reg());
2929
-
2930
- let (prefix, opcode, opcode_bytes, dst_size, dst_first) = match op {
2931
- SseOpcode::Pextrb => (LegacyPrefixes::_66, 0x0F3A14, 3, OS::Size32, false),
2932
- SseOpcode::Pextrw => (LegacyPrefixes::_66, 0x0FC5, 2, OS::Size32, true),
2933
- SseOpcode::Pextrd => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size32, false),
2934
- SseOpcode::Pextrq => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size64, false),
2935
- _ => panic!("unexpected opcode {:?}", op),
2936
- };
2937
- let rex = RexFlags::from(dst_size);
2938
- let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
2939
-
2940
- emit_std_reg_reg(sink, prefix, opcode, opcode_bytes, src, dst, rex);
2941
- sink.put1(*imm);
2942
- }
2943
-
2944
- Inst::GprToXmm {
2945
- op,
2946
- src: src_e,
2947
- dst: reg_g,
2948
- src_size,
2949
- } => {
2950
- let reg_g = allocs.next(reg_g.to_reg().to_reg());
2951
- let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
2952
-
2953
- let (prefix, opcode) = match op {
2954
- // Movd and movq use the same opcode; the presence of the REX prefix (set below)
2955
- // actually determines which is used.
2956
- SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F6E),
2957
- SseOpcode::Cvtsi2ss => (LegacyPrefixes::_F3, 0x0F2A),
2958
- SseOpcode::Cvtsi2sd => (LegacyPrefixes::_F2, 0x0F2A),
2959
- _ => panic!("unexpected opcode {:?}", op),
2960
- };
2961
- let rex = RexFlags::from(*src_size);
2962
- match src_e {
2963
- RegMem::Reg { reg: reg_e } => {
2964
- emit_std_reg_reg(sink, prefix, opcode, 2, reg_g, reg_e, rex);
2965
- }
2966
- RegMem::Mem { addr } => {
2967
- let addr = &addr.finalize(state, sink);
2968
- emit_std_reg_mem(sink, prefix, opcode, 2, reg_g, addr, rex, 0);
2969
- }
2970
- }
2971
- }
2972
-
2973
- Inst::XmmCmpRmR { op, src, dst } => {
2974
- let dst = allocs.next(dst.to_reg());
2975
- let src = src.clone().to_reg_mem().with_allocs(allocs);
2976
-
2977
- let rex = RexFlags::clear_w();
2978
- let (prefix, opcode, len) = match op {
2979
- SseOpcode::Ptest => (LegacyPrefixes::_66, 0x0F3817, 3),
2980
- SseOpcode::Ucomisd => (LegacyPrefixes::_66, 0x0F2E, 2),
2981
- SseOpcode::Ucomiss => (LegacyPrefixes::None, 0x0F2E, 2),
2982
- _ => unimplemented!("Emit xmm cmp rm r"),
2983
- };
2984
-
2985
- match src {
2986
- RegMem::Reg { reg } => {
2987
- emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
2988
- }
2989
- RegMem::Mem { addr } => {
2990
- let addr = &addr.finalize(state, sink);
2991
- emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 0);
2992
- }
2993
- }
2994
- }
2995
-
2996
- Inst::CvtUint64ToFloatSeq {
2997
- dst_size,
2998
- src,
2999
- dst,
3000
- tmp_gpr1,
3001
- tmp_gpr2,
3002
- } => {
3003
- let src = allocs.next(src.to_reg());
3004
- let dst = allocs.next(dst.to_reg().to_reg());
3005
- let tmp_gpr1 = allocs.next(tmp_gpr1.to_reg().to_reg());
3006
- let tmp_gpr2 = allocs.next(tmp_gpr2.to_reg().to_reg());
3007
-
3008
- // Note: this sequence is specific to 64-bit mode; a 32-bit mode would require a
3009
- // different sequence.
3010
- //
3011
- // Emit the following sequence:
3012
- //
3013
- // cmp 0, %src
3014
- // jl handle_negative
3015
- //
3016
- // ;; handle positive, which can't overflow
3017
- // cvtsi2sd/cvtsi2ss %src, %dst
3018
- // j done
3019
- //
3020
- // ;; handle negative: see below for an explanation of what it's doing.
3021
- // handle_negative:
3022
- // mov %src, %tmp_gpr1
3023
- // shr $1, %tmp_gpr1
3024
- // mov %src, %tmp_gpr2
3025
- // and $1, %tmp_gpr2
3026
- // or %tmp_gpr1, %tmp_gpr2
3027
- // cvtsi2sd/cvtsi2ss %tmp_gpr2, %dst
3028
- // addsd/addss %dst, %dst
3029
- //
3030
- // done:
3031
-
3032
- assert_ne!(src, tmp_gpr1);
3033
- assert_ne!(src, tmp_gpr2);
3034
- assert_ne!(tmp_gpr1, tmp_gpr2);
3035
-
3036
- let handle_negative = sink.get_label();
3037
- let done = sink.get_label();
3038
-
3039
- // If x seen as a signed int64 is not negative, a signed-conversion will do the right
3040
- // thing.
3041
- // TODO use tst src, src here.
3042
- let inst = Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(0), src);
3043
- inst.emit(&[], sink, info, state);
3044
-
3045
- one_way_jmp(sink, CC::L, handle_negative);
3046
-
3047
- // Handle a positive int64, which is the "easy" case: a signed conversion will do the
3048
- // right thing.
3049
- emit_signed_cvt(
3050
- sink,
3051
- info,
3052
- state,
3053
- src,
3054
- Writable::from_reg(dst),
3055
- *dst_size == OperandSize::Size64,
3056
- );
3057
-
3058
- let inst = Inst::jmp_known(done);
3059
- inst.emit(&[], sink, info, state);
3060
-
3061
- sink.bind_label(handle_negative, &mut state.ctrl_plane);
3062
-
3063
- // Divide x by two to get it in range for the signed conversion, keep the LSB, and
3064
- // scale it back up on the FP side.
3065
- let inst = Inst::gen_move(Writable::from_reg(tmp_gpr1), src, types::I64);
3066
- inst.emit(&[], sink, info, state);
3067
-
3068
- // tmp_gpr1 := src >> 1
3069
- let inst = Inst::shift_r(
3070
- OperandSize::Size64,
3071
- ShiftKind::ShiftRightLogical,
3072
- Imm8Gpr::new(Imm8Reg::Imm8 { imm: 1 }).unwrap(),
3073
- tmp_gpr1,
3074
- Writable::from_reg(tmp_gpr1),
3075
- );
3076
- inst.emit(&[], sink, info, state);
3077
-
3078
- let inst = Inst::gen_move(Writable::from_reg(tmp_gpr2), src, types::I64);
3079
- inst.emit(&[], sink, info, state);
3080
-
3081
- let inst = Inst::alu_rmi_r(
3082
- OperandSize::Size64,
3083
- AluRmiROpcode::And,
3084
- RegMemImm::imm(1),
3085
- Writable::from_reg(tmp_gpr2),
3086
- );
3087
- inst.emit(&[], sink, info, state);
3088
-
3089
- let inst = Inst::alu_rmi_r(
3090
- OperandSize::Size64,
3091
- AluRmiROpcode::Or,
3092
- RegMemImm::reg(tmp_gpr1),
3093
- Writable::from_reg(tmp_gpr2),
3094
- );
3095
- inst.emit(&[], sink, info, state);
3096
-
3097
- emit_signed_cvt(
3098
- sink,
3099
- info,
3100
- state,
3101
- tmp_gpr2,
3102
- Writable::from_reg(dst),
3103
- *dst_size == OperandSize::Size64,
3104
- );
3105
-
3106
- let add_op = if *dst_size == OperandSize::Size64 {
3107
- SseOpcode::Addsd
3108
- } else {
3109
- SseOpcode::Addss
3110
- };
3111
- let inst = Inst::xmm_rm_r(add_op, RegMem::reg(dst), Writable::from_reg(dst));
3112
- inst.emit(&[], sink, info, state);
3113
-
3114
- sink.bind_label(done, &mut state.ctrl_plane);
3115
- }
3116
-
3117
- Inst::CvtFloatToSintSeq {
3118
- src_size,
3119
- dst_size,
3120
- is_saturating,
3121
- src,
3122
- dst,
3123
- tmp_gpr,
3124
- tmp_xmm,
3125
- } => {
3126
- let src = allocs.next(src.to_reg());
3127
- let dst = allocs.next(dst.to_reg().to_reg());
3128
- let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3129
- let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3130
-
3131
- // Emits the following common sequence:
3132
- //
3133
- // cvttss2si/cvttsd2si %src, %dst
3134
- // cmp %dst, 1
3135
- // jno done
3136
- //
3137
- // Then, for saturating conversions:
3138
- //
3139
- // ;; check for NaN
3140
- // cmpss/cmpsd %src, %src
3141
- // jnp not_nan
3142
- // xor %dst, %dst
3143
- //
3144
- // ;; positive inputs get saturated to INT_MAX; negative ones to INT_MIN, which is
3145
- // ;; already in %dst.
3146
- // xorpd %tmp_xmm, %tmp_xmm
3147
- // cmpss/cmpsd %src, %tmp_xmm
3148
- // jnb done
3149
- // mov/movaps $INT_MAX, %dst
3150
- //
3151
- // done:
3152
- //
3153
- // Then, for non-saturating conversions:
3154
- //
3155
- // ;; check for NaN
3156
- // cmpss/cmpsd %src, %src
3157
- // jnp not_nan
3158
- // ud2 trap BadConversionToInteger
3159
- //
3160
- // ;; check if INT_MIN was the correct result, against a magic constant:
3161
- // not_nan:
3162
- // movaps/mov $magic, %tmp_gpr
3163
- // movq/movd %tmp_gpr, %tmp_xmm
3164
- // cmpss/cmpsd %tmp_xmm, %src
3165
- // jnb/jnbe $check_positive
3166
- // ud2 trap IntegerOverflow
3167
- //
3168
- // ;; if positive, it was a real overflow
3169
- // check_positive:
3170
- // xorpd %tmp_xmm, %tmp_xmm
3171
- // cmpss/cmpsd %src, %tmp_xmm
3172
- // jnb done
3173
- // ud2 trap IntegerOverflow
3174
- //
3175
- // done:
3176
-
3177
- let (cast_op, cmp_op, trunc_op) = match src_size {
3178
- OperandSize::Size64 => (SseOpcode::Movq, SseOpcode::Ucomisd, SseOpcode::Cvttsd2si),
3179
- OperandSize::Size32 => (SseOpcode::Movd, SseOpcode::Ucomiss, SseOpcode::Cvttss2si),
3180
- _ => unreachable!(),
3181
- };
3182
-
3183
- let done = sink.get_label();
3184
-
3185
- // The truncation.
3186
- let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3187
- inst.emit(&[], sink, info, state);
3188
-
3189
- // Compare against 1, in case of overflow the dst operand was INT_MIN.
3190
- let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(1), dst);
3191
- inst.emit(&[], sink, info, state);
3192
-
3193
- one_way_jmp(sink, CC::NO, done); // no overflow => done
3194
-
3195
- // Check for NaN.
3196
-
3197
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), src);
3198
- inst.emit(&[], sink, info, state);
3199
-
3200
- if *is_saturating {
3201
- let not_nan = sink.get_label();
3202
- one_way_jmp(sink, CC::NP, not_nan); // go to not_nan if not a NaN
3203
-
3204
- // For NaN, emit 0.
3205
- let inst = Inst::alu_rmi_r(
3206
- *dst_size,
3207
- AluRmiROpcode::Xor,
3208
- RegMemImm::reg(dst),
3209
- Writable::from_reg(dst),
3210
- );
3211
- inst.emit(&[], sink, info, state);
3212
-
3213
- let inst = Inst::jmp_known(done);
3214
- inst.emit(&[], sink, info, state);
3215
-
3216
- sink.bind_label(not_nan, &mut state.ctrl_plane);
3217
-
3218
- // If the input was positive, saturate to INT_MAX.
3219
-
3220
- // Zero out tmp_xmm.
3221
- let inst = Inst::xmm_rm_r(
3222
- SseOpcode::Xorpd,
3223
- RegMem::reg(tmp_xmm),
3224
- Writable::from_reg(tmp_xmm),
3225
- );
3226
- inst.emit(&[], sink, info, state);
3227
-
3228
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3229
- inst.emit(&[], sink, info, state);
3230
-
3231
- // Jump if >= to done.
3232
- one_way_jmp(sink, CC::NB, done);
3233
-
3234
- // Otherwise, put INT_MAX.
3235
- if *dst_size == OperandSize::Size64 {
3236
- let inst = Inst::imm(
3237
- OperandSize::Size64,
3238
- 0x7fffffffffffffff,
3239
- Writable::from_reg(dst),
3240
- );
3241
- inst.emit(&[], sink, info, state);
3242
- } else {
3243
- let inst = Inst::imm(OperandSize::Size32, 0x7fffffff, Writable::from_reg(dst));
3244
- inst.emit(&[], sink, info, state);
3245
- }
3246
- } else {
3247
- let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3248
- inst.emit(&[], sink, info, state);
3249
-
3250
- // Check if INT_MIN was the correct result: determine the smallest floating point
3251
- // number that would convert to INT_MIN, put it in a temporary register, and compare
3252
- // against the src register.
3253
- // If the src register is less (or in some cases, less-or-equal) than the threshold,
3254
- // trap!
3255
-
3256
- let mut no_overflow_cc = CC::NB; // >=
3257
- let output_bits = dst_size.to_bits();
3258
- match *src_size {
3259
- OperandSize::Size32 => {
3260
- let cst = Ieee32::pow2(output_bits - 1).neg().bits();
3261
- let inst =
3262
- Inst::imm(OperandSize::Size32, cst as u64, Writable::from_reg(tmp_gpr));
3263
- inst.emit(&[], sink, info, state);
3264
- }
3265
- OperandSize::Size64 => {
3266
- // An f64 can represent `i32::min_value() - 1` exactly with precision to spare,
3267
- // so there are values less than -2^(N-1) that convert correctly to INT_MIN.
3268
- let cst = if output_bits < 64 {
3269
- no_overflow_cc = CC::NBE; // >
3270
- Ieee64::fcvt_to_sint_negative_overflow(output_bits)
3271
- } else {
3272
- Ieee64::pow2(output_bits - 1).neg()
3273
- };
3274
- let inst =
3275
- Inst::imm(OperandSize::Size64, cst.bits(), Writable::from_reg(tmp_gpr));
3276
- inst.emit(&[], sink, info, state);
3277
- }
3278
- _ => unreachable!(),
3279
- }
3280
-
3281
- let inst = Inst::gpr_to_xmm(
3282
- cast_op,
3283
- RegMem::reg(tmp_gpr),
3284
- *src_size,
3285
- Writable::from_reg(tmp_xmm),
3286
- );
3287
- inst.emit(&[], sink, info, state);
3288
-
3289
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3290
- inst.emit(&[], sink, info, state);
3291
-
3292
- // no trap if src >= or > threshold
3293
- let inst = Inst::trap_if(no_overflow_cc.invert(), TrapCode::IntegerOverflow);
3294
- inst.emit(&[], sink, info, state);
3295
-
3296
- // If positive, it was a real overflow.
3297
-
3298
- // Zero out the tmp_xmm register.
3299
- let inst = Inst::xmm_rm_r(
3300
- SseOpcode::Xorpd,
3301
- RegMem::reg(tmp_xmm),
3302
- Writable::from_reg(tmp_xmm),
3303
- );
3304
- inst.emit(&[], sink, info, state);
3305
-
3306
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3307
- inst.emit(&[], sink, info, state);
3308
-
3309
- // no trap if 0 >= src
3310
- let inst = Inst::trap_if(CC::B, TrapCode::IntegerOverflow);
3311
- inst.emit(&[], sink, info, state);
3312
- }
3313
-
3314
- sink.bind_label(done, &mut state.ctrl_plane);
3315
- }
3316
-
3317
- Inst::CvtFloatToUintSeq {
3318
- src_size,
3319
- dst_size,
3320
- is_saturating,
3321
- src,
3322
- dst,
3323
- tmp_gpr,
3324
- tmp_xmm,
3325
- tmp_xmm2,
3326
- } => {
3327
- let src = allocs.next(src.to_reg());
3328
- let dst = allocs.next(dst.to_reg().to_reg());
3329
- let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3330
- let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3331
- let tmp_xmm2 = allocs.next(tmp_xmm2.to_reg().to_reg());
3332
-
3333
- // The only difference in behavior between saturating and non-saturating is how we
3334
- // handle errors. Emits the following sequence:
3335
- //
3336
- // movaps/mov 2**(int_width - 1), %tmp_gpr
3337
- // movq/movd %tmp_gpr, %tmp_xmm
3338
- // cmpss/cmpsd %tmp_xmm, %src
3339
- // jnb is_large
3340
- //
3341
- // ;; check for NaN inputs
3342
- // jnp not_nan
3343
- // -- non-saturating: ud2 trap BadConversionToInteger
3344
- // -- saturating: xor %dst, %dst; j done
3345
- //
3346
- // not_nan:
3347
- // cvttss2si/cvttsd2si %src, %dst
3348
- // cmp 0, %dst
3349
- // jnl done
3350
- // -- non-saturating: ud2 trap IntegerOverflow
3351
- // -- saturating: xor %dst, %dst; j done
3352
- //
3353
- // is_large:
3354
- // mov %src, %tmp_xmm2
3355
- // subss/subsd %tmp_xmm, %tmp_xmm2
3356
- // cvttss2si/cvttss2sd %tmp_x, %dst
3357
- // cmp 0, %dst
3358
- // jnl next_is_large
3359
- // -- non-saturating: ud2 trap IntegerOverflow
3360
- // -- saturating: movaps $UINT_MAX, %dst; j done
3361
- //
3362
- // next_is_large:
3363
- // add 2**(int_width -1), %dst ;; 2 instructions for 64-bits integers
3364
- //
3365
- // done:
3366
-
3367
- assert_ne!(tmp_xmm, src, "tmp_xmm clobbers src!");
3368
-
3369
- let (sub_op, cast_op, cmp_op, trunc_op) = match src_size {
3370
- OperandSize::Size32 => (
3371
- SseOpcode::Subss,
3372
- SseOpcode::Movd,
3373
- SseOpcode::Ucomiss,
3374
- SseOpcode::Cvttss2si,
3375
- ),
3376
- OperandSize::Size64 => (
3377
- SseOpcode::Subsd,
3378
- SseOpcode::Movq,
3379
- SseOpcode::Ucomisd,
3380
- SseOpcode::Cvttsd2si,
3381
- ),
3382
- _ => unreachable!(),
3383
- };
3384
-
3385
- let done = sink.get_label();
3386
-
3387
- let cst = match src_size {
3388
- OperandSize::Size32 => Ieee32::pow2(dst_size.to_bits() - 1).bits() as u64,
3389
- OperandSize::Size64 => Ieee64::pow2(dst_size.to_bits() - 1).bits(),
3390
- _ => unreachable!(),
3391
- };
3392
-
3393
- let inst = Inst::imm(*src_size, cst, Writable::from_reg(tmp_gpr));
3394
- inst.emit(&[], sink, info, state);
3395
-
3396
- let inst = Inst::gpr_to_xmm(
3397
- cast_op,
3398
- RegMem::reg(tmp_gpr),
3399
- *src_size,
3400
- Writable::from_reg(tmp_xmm),
3401
- );
3402
- inst.emit(&[], sink, info, state);
3403
-
3404
- let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3405
- inst.emit(&[], sink, info, state);
3406
-
3407
- let handle_large = sink.get_label();
3408
- one_way_jmp(sink, CC::NB, handle_large); // jump to handle_large if src >= large_threshold
3409
-
3410
- if *is_saturating {
3411
- // If not NaN jump over this 0-return, otherwise return 0
3412
- let not_nan = sink.get_label();
3413
- one_way_jmp(sink, CC::NP, not_nan);
3414
- let inst = Inst::alu_rmi_r(
3415
- *dst_size,
3416
- AluRmiROpcode::Xor,
3417
- RegMemImm::reg(dst),
3418
- Writable::from_reg(dst),
3419
- );
3420
- inst.emit(&[], sink, info, state);
3421
-
3422
- let inst = Inst::jmp_known(done);
3423
- inst.emit(&[], sink, info, state);
3424
- sink.bind_label(not_nan, &mut state.ctrl_plane);
3425
- } else {
3426
- // Trap.
3427
- let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3428
- inst.emit(&[], sink, info, state);
3429
- }
3430
-
3431
- // Actual truncation for small inputs: if the result is not positive, then we had an
3432
- // overflow.
3433
-
3434
- let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3435
- inst.emit(&[], sink, info, state);
3436
-
3437
- let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3438
- inst.emit(&[], sink, info, state);
3439
-
3440
- one_way_jmp(sink, CC::NL, done); // if dst >= 0, jump to done
3441
-
3442
- if *is_saturating {
3443
- // The input was "small" (< 2**(width -1)), so the only way to get an integer
3444
- // overflow is because the input was too small: saturate to the min value, i.e. 0.
3445
- let inst = Inst::alu_rmi_r(
3446
- *dst_size,
3447
- AluRmiROpcode::Xor,
3448
- RegMemImm::reg(dst),
3449
- Writable::from_reg(dst),
3450
- );
3451
- inst.emit(&[], sink, info, state);
3452
-
3453
- let inst = Inst::jmp_known(done);
3454
- inst.emit(&[], sink, info, state);
3455
- } else {
3456
- // Trap.
3457
- let inst = Inst::trap(TrapCode::IntegerOverflow);
3458
- inst.emit(&[], sink, info, state);
3459
- }
3460
-
3461
- // Now handle large inputs.
3462
-
3463
- sink.bind_label(handle_large, &mut state.ctrl_plane);
3464
-
3465
- let inst = Inst::gen_move(Writable::from_reg(tmp_xmm2), src, types::F64);
3466
- inst.emit(&[], sink, info, state);
3467
-
3468
- let inst = Inst::xmm_rm_r(sub_op, RegMem::reg(tmp_xmm), Writable::from_reg(tmp_xmm2));
3469
- inst.emit(&[], sink, info, state);
3470
-
3471
- let inst = Inst::xmm_to_gpr(trunc_op, tmp_xmm2, Writable::from_reg(dst), *dst_size);
3472
- inst.emit(&[], sink, info, state);
3473
-
3474
- let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3475
- inst.emit(&[], sink, info, state);
3476
-
3477
- if *is_saturating {
3478
- let next_is_large = sink.get_label();
3479
- one_way_jmp(sink, CC::NL, next_is_large); // if dst >= 0, jump to next_is_large
3480
-
3481
- // The input was "large" (>= 2**(width -1)), so the only way to get an integer
3482
- // overflow is because the input was too large: saturate to the max value.
3483
- let inst = Inst::imm(
3484
- OperandSize::Size64,
3485
- if *dst_size == OperandSize::Size64 {
3486
- u64::max_value()
3487
- } else {
3488
- u32::max_value() as u64
3489
- },
3490
- Writable::from_reg(dst),
3491
- );
3492
- inst.emit(&[], sink, info, state);
3493
-
3494
- let inst = Inst::jmp_known(done);
3495
- inst.emit(&[], sink, info, state);
3496
- sink.bind_label(next_is_large, &mut state.ctrl_plane);
3497
- } else {
3498
- let inst = Inst::trap_if(CC::L, TrapCode::IntegerOverflow);
3499
- inst.emit(&[], sink, info, state);
3500
- }
3501
-
3502
- if *dst_size == OperandSize::Size64 {
3503
- let inst = Inst::imm(OperandSize::Size64, 1 << 63, Writable::from_reg(tmp_gpr));
3504
- inst.emit(&[], sink, info, state);
3505
-
3506
- let inst = Inst::alu_rmi_r(
3507
- OperandSize::Size64,
3508
- AluRmiROpcode::Add,
3509
- RegMemImm::reg(tmp_gpr),
3510
- Writable::from_reg(dst),
3511
- );
3512
- inst.emit(&[], sink, info, state);
3513
- } else {
3514
- let inst = Inst::alu_rmi_r(
3515
- OperandSize::Size32,
3516
- AluRmiROpcode::Add,
3517
- RegMemImm::imm(1 << 31),
3518
- Writable::from_reg(dst),
3519
- );
3520
- inst.emit(&[], sink, info, state);
3521
- }
3522
-
3523
- sink.bind_label(done, &mut state.ctrl_plane);
3524
- }
3525
-
3526
- Inst::LoadExtName { dst, name, offset } => {
3527
- let dst = allocs.next(dst.to_reg());
3528
-
3529
- if info.flags.is_pic() {
3530
- // Generates: movq symbol@GOTPCREL(%rip), %dst
3531
- let enc_dst = int_reg_enc(dst);
3532
- sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
3533
- sink.put1(0x8B);
3534
- sink.put1(0x05 | ((enc_dst & 7) << 3));
3535
- emit_reloc(sink, Reloc::X86GOTPCRel4, name, -4);
3536
- sink.put4(0);
3537
- // Offset in the relocation above applies to the address of the *GOT entry*, not
3538
- // the loaded address; so we emit a separate add or sub instruction if needed.
3539
- if *offset < 0 {
3540
- assert!(*offset >= -i32::MAX as i64);
3541
- sink.put1(0x48 | ((enc_dst >> 3) & 1));
3542
- sink.put1(0x81);
3543
- sink.put1(0xe8 | (enc_dst & 7));
3544
- sink.put4((-*offset) as u32);
3545
- } else if *offset > 0 {
3546
- assert!(*offset <= i32::MAX as i64);
3547
- sink.put1(0x48 | ((enc_dst >> 3) & 1));
3548
- sink.put1(0x81);
3549
- sink.put1(0xc0 | (enc_dst & 7));
3550
- sink.put4(*offset as u32);
3551
- }
3552
- } else {
3553
- // The full address can be encoded in the register, with a relocation.
3554
- // Generates: movabsq $name, %dst
3555
- let enc_dst = int_reg_enc(dst);
3556
- sink.put1(0x48 | ((enc_dst >> 3) & 1));
3557
- sink.put1(0xB8 | (enc_dst & 7));
3558
- emit_reloc(sink, Reloc::Abs8, name, *offset);
3559
- sink.put8(0);
3560
- }
3561
- }
3562
-
3563
- Inst::LockCmpxchg {
3564
- ty,
3565
- replacement,
3566
- expected,
3567
- mem,
3568
- dst_old,
3569
- } => {
3570
- let replacement = allocs.next(*replacement);
3571
- let expected = allocs.next(*expected);
3572
- let dst_old = allocs.next(dst_old.to_reg());
3573
- let mem = mem.with_allocs(allocs);
3574
-
3575
- debug_assert_eq!(expected, regs::rax());
3576
- debug_assert_eq!(dst_old, regs::rax());
3577
-
3578
- // lock cmpxchg{b,w,l,q} %replacement, (mem)
3579
- // Note that 0xF0 is the Lock prefix.
3580
- let (prefix, opcodes) = match *ty {
3581
- types::I8 => (LegacyPrefixes::_F0, 0x0FB0),
3582
- types::I16 => (LegacyPrefixes::_66F0, 0x0FB1),
3583
- types::I32 => (LegacyPrefixes::_F0, 0x0FB1),
3584
- types::I64 => (LegacyPrefixes::_F0, 0x0FB1),
3585
- _ => unreachable!(),
3586
- };
3587
- let rex = RexFlags::from((OperandSize::from_ty(*ty), replacement));
3588
- let amode = mem.finalize(state, sink);
3589
- emit_std_reg_mem(sink, prefix, opcodes, 2, replacement, &amode, rex, 0);
3590
- }
3591
-
3592
- Inst::AtomicRmwSeq {
3593
- ty,
3594
- op,
3595
- mem,
3596
- operand,
3597
- temp,
3598
- dst_old,
3599
- } => {
3600
- let operand = allocs.next(*operand);
3601
- let temp = allocs.next_writable(*temp);
3602
- let dst_old = allocs.next_writable(*dst_old);
3603
- debug_assert_eq!(dst_old.to_reg(), regs::rax());
3604
- let mem = mem.finalize(state, sink).with_allocs(allocs);
3605
-
3606
- // Emit this:
3607
- // mov{zbq,zwq,zlq,q} (%r_address), %rax // rax = old value
3608
- // again:
3609
- // movq %rax, %r_temp // rax = old value, r_temp = old value
3610
- // `op`q %r_operand, %r_temp // rax = old value, r_temp = new value
3611
- // lock cmpxchg{b,w,l,q} %r_temp, (%r_address) // try to store new value
3612
- // jnz again // If this is taken, rax will have a "revised" old value
3613
- //
3614
- // Operand conventions: IN: %r_address, %r_operand OUT: %rax (old
3615
- // value), %r_temp (trashed), %rflags (trashed)
3616
- //
3617
- // In the case where the operation is 'xchg', the "`op`q"
3618
- // instruction is instead: movq %r_operand,
3619
- // %r_temp so that we simply write in the destination, the "2nd
3620
- // arg for `op`".
3621
- //
3622
- // TODO: this sequence can be significantly improved (e.g., to `lock
3623
- // <op>`) when it is known that `dst_old` is not used later, see
3624
- // https://github.com/bytecodealliance/wasmtime/issues/2153.
3625
- let again_label = sink.get_label();
3626
-
3627
- // mov{zbq,zwq,zlq,q} (%r_address), %rax
3628
- // No need to call `add_trap` here, since the `i1` emit will do that.
3629
- let i1 = Inst::load(*ty, mem.clone(), dst_old, ExtKind::ZeroExtend);
3630
- i1.emit(&[], sink, info, state);
3631
-
3632
- // again:
3633
- sink.bind_label(again_label, &mut state.ctrl_plane);
3634
-
3635
- // movq %rax, %r_temp
3636
- let i2 = Inst::mov_r_r(OperandSize::Size64, dst_old.to_reg(), temp);
3637
- i2.emit(&[], sink, info, state);
3638
-
3639
- let operand_rmi = RegMemImm::reg(operand);
3640
- use inst_common::MachAtomicRmwOp as RmwOp;
3641
- match op {
3642
- RmwOp::Xchg => {
3643
- // movq %r_operand, %r_temp
3644
- let i3 = Inst::mov_r_r(OperandSize::Size64, operand, temp);
3645
- i3.emit(&[], sink, info, state);
3646
- }
3647
- RmwOp::Nand => {
3648
- // andq %r_operand, %r_temp
3649
- let i3 =
3650
- Inst::alu_rmi_r(OperandSize::Size64, AluRmiROpcode::And, operand_rmi, temp);
3651
- i3.emit(&[], sink, info, state);
3652
-
3653
- // notq %r_temp
3654
- let i4 = Inst::not(OperandSize::Size64, temp);
3655
- i4.emit(&[], sink, info, state);
3656
- }
3657
- RmwOp::Umin | RmwOp::Umax | RmwOp::Smin | RmwOp::Smax => {
3658
- // cmp %r_temp, %r_operand
3659
- let i3 = Inst::cmp_rmi_r(
3660
- OperandSize::from_ty(*ty),
3661
- RegMemImm::reg(temp.to_reg()),
3662
- operand,
3663
- );
3664
- i3.emit(&[], sink, info, state);
3665
-
3666
- // cmovcc %r_operand, %r_temp
3667
- let cc = match op {
3668
- RmwOp::Umin => CC::BE,
3669
- RmwOp::Umax => CC::NB,
3670
- RmwOp::Smin => CC::LE,
3671
- RmwOp::Smax => CC::NL,
3672
- _ => unreachable!(),
3673
- };
3674
- let i4 = Inst::cmove(OperandSize::Size64, cc, RegMem::reg(operand), temp);
3675
- i4.emit(&[], sink, info, state);
3676
- }
3677
- _ => {
3678
- // opq %r_operand, %r_temp
3679
- let alu_op = match op {
3680
- RmwOp::Add => AluRmiROpcode::Add,
3681
- RmwOp::Sub => AluRmiROpcode::Sub,
3682
- RmwOp::And => AluRmiROpcode::And,
3683
- RmwOp::Or => AluRmiROpcode::Or,
3684
- RmwOp::Xor => AluRmiROpcode::Xor,
3685
- RmwOp::Xchg
3686
- | RmwOp::Nand
3687
- | RmwOp::Umin
3688
- | RmwOp::Umax
3689
- | RmwOp::Smin
3690
- | RmwOp::Smax => unreachable!(),
3691
- };
3692
- let i3 = Inst::alu_rmi_r(OperandSize::Size64, alu_op, operand_rmi, temp);
3693
- i3.emit(&[], sink, info, state);
3694
- }
3695
- }
3696
-
3697
- // lock cmpxchg{b,w,l,q} %r_temp, (%r_address)
3698
- // No need to call `add_trap` here, since the `i4` emit will do that.
3699
- let i4 = Inst::LockCmpxchg {
3700
- ty: *ty,
3701
- replacement: temp.to_reg(),
3702
- expected: dst_old.to_reg(),
3703
- mem: mem.into(),
3704
- dst_old,
3705
- };
3706
- i4.emit(&[], sink, info, state);
3707
-
3708
- // jnz again
3709
- one_way_jmp(sink, CC::NZ, again_label);
3710
- }
3711
-
3712
- Inst::Fence { kind } => {
3713
- sink.put1(0x0F);
3714
- sink.put1(0xAE);
3715
- match kind {
3716
- FenceKind::MFence => sink.put1(0xF0), // mfence = 0F AE F0
3717
- FenceKind::LFence => sink.put1(0xE8), // lfence = 0F AE E8
3718
- FenceKind::SFence => sink.put1(0xF8), // sfence = 0F AE F8
3719
- }
3720
- }
3721
-
3722
- Inst::Hlt => {
3723
- sink.put1(0xcc);
3724
- }
3725
-
3726
- Inst::Ud2 { trap_code } => {
3727
- sink.add_trap(*trap_code);
3728
- if let Some(s) = state.take_stack_map() {
3729
- sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
3730
- }
3731
- sink.put_data(Inst::TRAP_OPCODE);
3732
- }
3733
-
3734
- Inst::VirtualSPOffsetAdj { offset } => {
3735
- trace!(
3736
- "virtual sp offset adjusted by {} -> {}",
3737
- offset,
3738
- state.virtual_sp_offset + offset
3739
- );
3740
- state.virtual_sp_offset += offset;
3741
- }
3742
-
3743
- Inst::Nop { len } => {
3744
- // These encodings can all be found in Intel's architecture manual, at the NOP
3745
- // instruction description.
3746
- let mut len = *len;
3747
- while len != 0 {
3748
- let emitted = u8::min(len, 9);
3749
- match emitted {
3750
- 0 => {}
3751
- 1 => sink.put1(0x90), // NOP
3752
- 2 => {
3753
- // 66 NOP
3754
- sink.put1(0x66);
3755
- sink.put1(0x90);
3756
- }
3757
- 3 => {
3758
- // NOP [EAX]
3759
- sink.put1(0x0F);
3760
- sink.put1(0x1F);
3761
- sink.put1(0x00);
3762
- }
3763
- 4 => {
3764
- // NOP 0(EAX), with 0 a 1-byte immediate.
3765
- sink.put1(0x0F);
3766
- sink.put1(0x1F);
3767
- sink.put1(0x40);
3768
- sink.put1(0x00);
3769
- }
3770
- 5 => {
3771
- // NOP [EAX, EAX, 1]
3772
- sink.put1(0x0F);
3773
- sink.put1(0x1F);
3774
- sink.put1(0x44);
3775
- sink.put1(0x00);
3776
- sink.put1(0x00);
3777
- }
3778
- 6 => {
3779
- // 66 NOP [EAX, EAX, 1]
3780
- sink.put1(0x66);
3781
- sink.put1(0x0F);
3782
- sink.put1(0x1F);
3783
- sink.put1(0x44);
3784
- sink.put1(0x00);
3785
- sink.put1(0x00);
3786
- }
3787
- 7 => {
3788
- // NOP 0[EAX], but 0 is a 4 bytes immediate.
3789
- sink.put1(0x0F);
3790
- sink.put1(0x1F);
3791
- sink.put1(0x80);
3792
- sink.put1(0x00);
3793
- sink.put1(0x00);
3794
- sink.put1(0x00);
3795
- sink.put1(0x00);
3796
- }
3797
- 8 => {
3798
- // NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
3799
- sink.put1(0x0F);
3800
- sink.put1(0x1F);
3801
- sink.put1(0x84);
3802
- sink.put1(0x00);
3803
- sink.put1(0x00);
3804
- sink.put1(0x00);
3805
- sink.put1(0x00);
3806
- sink.put1(0x00);
3807
- }
3808
- 9 => {
3809
- // 66 NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
3810
- sink.put1(0x66);
3811
- sink.put1(0x0F);
3812
- sink.put1(0x1F);
3813
- sink.put1(0x84);
3814
- sink.put1(0x00);
3815
- sink.put1(0x00);
3816
- sink.put1(0x00);
3817
- sink.put1(0x00);
3818
- sink.put1(0x00);
3819
- }
3820
- _ => unreachable!(),
3821
- }
3822
- len -= emitted;
3823
- }
3824
- }
3825
-
3826
- Inst::ElfTlsGetAddr { ref symbol, dst } => {
3827
- let dst = allocs.next(dst.to_reg().to_reg());
3828
- debug_assert_eq!(dst, regs::rax());
3829
-
3830
- // N.B.: Must be exactly this byte sequence; the linker requires it,
3831
- // because it must know how to rewrite the bytes.
3832
-
3833
- // data16 lea gv@tlsgd(%rip),%rdi
3834
- sink.put1(0x66); // data16
3835
- sink.put1(0b01001000); // REX.W
3836
- sink.put1(0x8d); // LEA
3837
- sink.put1(0x3d); // ModRM byte
3838
- emit_reloc(sink, Reloc::ElfX86_64TlsGd, symbol, -4);
3839
- sink.put4(0); // offset
3840
-
3841
- // data16 data16 callq __tls_get_addr-4
3842
- sink.put1(0x66); // data16
3843
- sink.put1(0x66); // data16
3844
- sink.put1(0b01001000); // REX.W
3845
- sink.put1(0xe8); // CALL
3846
- emit_reloc(
3847
- sink,
3848
- Reloc::X86CallPLTRel4,
3849
- &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
3850
- -4,
3851
- );
3852
- sink.put4(0); // offset
3853
- }
3854
-
3855
- Inst::MachOTlsGetAddr { ref symbol, dst } => {
3856
- let dst = allocs.next(dst.to_reg().to_reg());
3857
- debug_assert_eq!(dst, regs::rax());
3858
-
3859
- // movq gv@tlv(%rip), %rdi
3860
- sink.put1(0x48); // REX.w
3861
- sink.put1(0x8b); // MOV
3862
- sink.put1(0x3d); // ModRM byte
3863
- emit_reloc(sink, Reloc::MachOX86_64Tlv, symbol, -4);
3864
- sink.put4(0); // offset
3865
-
3866
- // callq *(%rdi)
3867
- sink.put1(0xff);
3868
- sink.put1(0x17);
3869
- }
3870
-
3871
- Inst::CoffTlsGetAddr {
3872
- ref symbol,
3873
- dst,
3874
- tmp,
3875
- } => {
3876
- let dst = allocs.next(dst.to_reg().to_reg());
3877
- debug_assert_eq!(dst, regs::rax());
3878
-
3879
- // tmp is used below directly as %rcx
3880
- let tmp = allocs.next(tmp.to_reg().to_reg());
3881
- debug_assert_eq!(tmp, regs::rcx());
3882
-
3883
- // See: https://gcc.godbolt.org/z/M8or9x6ss
3884
- // And: https://github.com/bjorn3/rustc_codegen_cranelift/issues/388#issuecomment-532930282
3885
-
3886
- // Emit the following sequence
3887
- // movl (%rip), %eax ; IMAGE_REL_AMD64_REL32 _tls_index
3888
- // movq %gs:88, %rcx
3889
- // movq (%rcx,%rax,8), %rax
3890
- // leaq (%rax), %rax ; Reloc: IMAGE_REL_AMD64_SECREL symbol
3891
-
3892
- // Load TLS index for current thread
3893
- // movl (%rip), %eax
3894
- sink.put1(0x8b); // mov
3895
- sink.put1(0x05);
3896
- emit_reloc(
3897
- sink,
3898
- Reloc::X86PCRel4,
3899
- &ExternalName::KnownSymbol(KnownSymbol::CoffTlsIndex),
3900
- -4,
3901
- );
3902
- sink.put4(0); // offset
3903
-
3904
- // movq %gs:88, %rcx
3905
- // Load the TLS Storage Array pointer
3906
- // The gs segment register refers to the base address of the TEB on x64.
3907
- // 0x58 is the offset in the TEB for the ThreadLocalStoragePointer member on x64:
3908
- sink.put_data(&[
3909
- 0x65, 0x48, // REX.W
3910
- 0x8b, // MOV
3911
- 0x0c, 0x25, 0x58, // 0x58 - ThreadLocalStoragePointer offset
3912
- 0x00, 0x00, 0x00,
3913
- ]);
3914
-
3915
- // movq (%rcx,%rax,8), %rax
3916
- // Load the actual TLS entry for this thread.
3917
- // Computes ThreadLocalStoragePointer + _tls_index*8
3918
- sink.put_data(&[0x48, 0x8b, 0x04, 0xc1]);
3919
-
3920
- // leaq (%rax), %rax
3921
- sink.put1(0x48);
3922
- sink.put1(0x8d);
3923
- sink.put1(0x80);
3924
- emit_reloc(sink, Reloc::X86SecRel, symbol, 0);
3925
- sink.put4(0); // offset
3926
- }
3927
-
3928
- Inst::Unwind { ref inst } => {
3929
- sink.add_unwind(inst.clone());
3930
- }
3931
-
3932
- Inst::DummyUse { .. } => {
3933
- // Nothing.
3934
- }
3935
- }
3936
-
3937
- state.clear_post_insn();
3938
- }