wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,4090 @@
1
+ use crate::binemit::{Addend, Reloc};
2
+ use crate::ir::immediates::{Ieee32, Ieee64};
3
+ use crate::ir::TrapCode;
4
+ use crate::ir::{KnownSymbol, LibCall};
5
+ use crate::isa::x64::encoding::evex::{EvexInstruction, EvexVectorLength, RegisterOrAmode};
6
+ use crate::isa::x64::encoding::rex::{
7
+ emit_simm, emit_std_enc_enc, emit_std_enc_mem, emit_std_reg_mem, emit_std_reg_reg, int_reg_enc,
8
+ low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, OpcodeMap,
9
+ RexFlags,
10
+ };
11
+ use crate::isa::x64::encoding::vex::{VexInstruction, VexVectorLength};
12
+ use crate::isa::x64::inst::args::*;
13
+ use crate::isa::x64::inst::*;
14
+ use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel, Reg, Writable};
15
+ use core::convert::TryInto;
16
+
17
+ /// A small helper to generate a signed conversion instruction.
18
+ fn emit_signed_cvt(
19
+ sink: &mut MachBuffer<Inst>,
20
+ info: &EmitInfo,
21
+ state: &mut EmitState,
22
+ // Required to be RealRegs.
23
+ src: Reg,
24
+ dst: Writable<Reg>,
25
+ to_f64: bool,
26
+ ) {
27
+ // Handle an unsigned int, which is the "easy" case: a signed conversion will do the
28
+ // right thing.
29
+ let op = if to_f64 {
30
+ SseOpcode::Cvtsi2sd
31
+ } else {
32
+ SseOpcode::Cvtsi2ss
33
+ };
34
+ let inst = Inst::gpr_to_xmm(op, RegMem::reg(src), OperandSize::Size64, dst);
35
+ inst.emit(&[], sink, info, state);
36
+ }
37
+
38
+ /// Emits a one way conditional jump if CC is set (true).
39
+ fn one_way_jmp(sink: &mut MachBuffer<Inst>, cc: CC, label: MachLabel) {
40
+ let cond_start = sink.cur_offset();
41
+ let cond_disp_off = cond_start + 2;
42
+ sink.use_label_at_offset(cond_disp_off, label, LabelUse::JmpRel32);
43
+ sink.put1(0x0F);
44
+ sink.put1(0x80 + cc.get_enc());
45
+ sink.put4(0x0);
46
+ }
47
+
48
+ /// Emits a relocation, attaching the current source location as well.
49
+ fn emit_reloc(sink: &mut MachBuffer<Inst>, kind: Reloc, name: &ExternalName, addend: Addend) {
50
+ sink.add_reloc(kind, name, addend);
51
+ }
52
+
53
+ /// The top-level emit function.
54
+ ///
55
+ /// Important! Do not add improved (shortened) encoding cases to existing
56
+ /// instructions without also adding tests for those improved encodings. That
57
+ /// is a dangerous game that leads to hard-to-track-down errors in the emitted
58
+ /// code.
59
+ ///
60
+ /// For all instructions, make sure to have test coverage for all of the
61
+ /// following situations. Do this by creating the cross product resulting from
62
+ /// applying the following rules to each operand:
63
+ ///
64
+ /// (1) for any insn that mentions a register: one test using a register from
65
+ /// the group [rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi] and a second one
66
+ /// using a register from the group [r8, r9, r10, r11, r12, r13, r14, r15].
67
+ /// This helps detect incorrect REX prefix construction.
68
+ ///
69
+ /// (2) for any insn that mentions a byte register: one test for each of the
70
+ /// four encoding groups [al, cl, dl, bl], [spl, bpl, sil, dil],
71
+ /// [r8b .. r11b] and [r12b .. r15b]. This checks that
72
+ /// apparently-redundant REX prefixes are retained when required.
73
+ ///
74
+ /// (3) for any insn that contains an immediate field, check the following
75
+ /// cases: field is zero, field is in simm8 range (-128 .. 127), field is
76
+ /// in simm32 range (-0x8000_0000 .. 0x7FFF_FFFF). This is because some
77
+ /// instructions that require a 32-bit immediate have a short-form encoding
78
+ /// when the imm is in simm8 range.
79
+ ///
80
+ /// Rules (1), (2) and (3) don't apply for registers within address expressions
81
+ /// (`Addr`s). Those are already pretty well tested, and the registers in them
82
+ /// don't have any effect on the containing instruction (apart from possibly
83
+ /// require REX prefix bits).
84
+ ///
85
+ /// When choosing registers for a test, avoid using registers with the same
86
+ /// offset within a given group. For example, don't use rax and r8, since they
87
+ /// both have the lowest 3 bits as 000, and so the test won't detect errors
88
+ /// where those 3-bit register sub-fields are confused by the emitter. Instead
89
+ /// use (eg) rax (lo3 = 000) and r9 (lo3 = 001). Similarly, don't use (eg) cl
90
+ /// and bpl since they have the same offset in their group; use instead (eg) cl
91
+ /// and sil.
92
+ ///
93
+ /// For all instructions, also add a test that uses only low-half registers
94
+ /// (rax .. rdi, xmm0 .. xmm7) etc, so as to check that any redundant REX
95
+ /// prefixes are correctly omitted. This low-half restriction must apply to
96
+ /// _all_ registers in the insn, even those in address expressions.
97
+ ///
98
+ /// Following these rules creates large numbers of test cases, but it's the
99
+ /// only way to make the emitter reliable.
100
+ ///
101
+ /// Known possible improvements:
102
+ ///
103
+ /// * there's a shorter encoding for shl/shr/sar by a 1-bit immediate. (Do we
104
+ /// care?)
105
+ pub(crate) fn emit(
106
+ inst: &Inst,
107
+ allocs: &mut AllocationConsumer<'_>,
108
+ sink: &mut MachBuffer<Inst>,
109
+ info: &EmitInfo,
110
+ state: &mut EmitState,
111
+ ) {
112
+ let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
113
+ match iset_requirement {
114
+ // Cranelift assumes SSE2 at least.
115
+ InstructionSet::SSE | InstructionSet::SSE2 => true,
116
+ InstructionSet::SSSE3 => info.isa_flags.use_ssse3(),
117
+ InstructionSet::SSE41 => info.isa_flags.use_sse41(),
118
+ InstructionSet::SSE42 => info.isa_flags.use_sse42(),
119
+ InstructionSet::Popcnt => info.isa_flags.use_popcnt(),
120
+ InstructionSet::Lzcnt => info.isa_flags.use_lzcnt(),
121
+ InstructionSet::BMI1 => info.isa_flags.use_bmi1(),
122
+ InstructionSet::BMI2 => info.isa_flags.has_bmi2(),
123
+ InstructionSet::FMA => info.isa_flags.has_fma(),
124
+ InstructionSet::AVX => info.isa_flags.has_avx(),
125
+ InstructionSet::AVX2 => info.isa_flags.has_avx2(),
126
+ InstructionSet::AVX512BITALG => info.isa_flags.has_avx512bitalg(),
127
+ InstructionSet::AVX512DQ => info.isa_flags.has_avx512dq(),
128
+ InstructionSet::AVX512F => info.isa_flags.has_avx512f(),
129
+ InstructionSet::AVX512VBMI => info.isa_flags.has_avx512vbmi(),
130
+ InstructionSet::AVX512VL => info.isa_flags.has_avx512vl(),
131
+ }
132
+ };
133
+
134
+ // Certain instructions may be present in more than one ISA feature set; we must at least match
135
+ // one of them in the target CPU.
136
+ let isa_requirements = inst.available_in_any_isa();
137
+ if !isa_requirements.is_empty() && !isa_requirements.iter().all(matches_isa_flags) {
138
+ panic!(
139
+ "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
140
+ inst, isa_requirements
141
+ )
142
+ }
143
+
144
+ match inst {
145
+ Inst::AluRmiR {
146
+ size,
147
+ op,
148
+ src1,
149
+ src2,
150
+ dst: reg_g,
151
+ } => {
152
+ let src1 = allocs.next(src1.to_reg());
153
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
154
+ debug_assert_eq!(src1, reg_g);
155
+ let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
156
+
157
+ let prefix = if *size == OperandSize::Size16 {
158
+ LegacyPrefixes::_66
159
+ } else {
160
+ LegacyPrefixes::None
161
+ };
162
+
163
+ let mut rex = RexFlags::from(*size);
164
+ if *op == AluRmiROpcode::Mul {
165
+ // We kinda freeloaded Mul into RMI_R_Op, but it doesn't fit the usual pattern, so
166
+ // we have to special-case it.
167
+ if *size == OperandSize::Size8 {
168
+ match src2 {
169
+ RegMemImm::Reg { reg: reg_e } => {
170
+ debug_assert!(reg_e.is_real());
171
+ rex.always_emit_if_8bit_needed(reg_e);
172
+ let enc_e = int_reg_enc(reg_e);
173
+ emit_std_enc_enc(sink, LegacyPrefixes::None, 0xF6, 1, 5, enc_e, rex);
174
+ }
175
+
176
+ RegMemImm::Mem { addr } => {
177
+ let amode = addr.finalize(state, sink);
178
+ emit_std_enc_mem(
179
+ sink,
180
+ LegacyPrefixes::None,
181
+ 0xF6,
182
+ 1,
183
+ 5,
184
+ &amode,
185
+ rex,
186
+ 0,
187
+ );
188
+ }
189
+
190
+ RegMemImm::Imm { .. } => {
191
+ panic!("Cannot emit 8bit imul with 8bit immediate");
192
+ }
193
+ }
194
+ } else {
195
+ match src2 {
196
+ RegMemImm::Reg { reg: reg_e } => {
197
+ emit_std_reg_reg(sink, prefix, 0x0FAF, 2, reg_g, reg_e, rex);
198
+ }
199
+
200
+ RegMemImm::Mem { addr } => {
201
+ let amode = addr.finalize(state, sink);
202
+ emit_std_reg_mem(sink, prefix, 0x0FAF, 2, reg_g, &amode, rex, 0);
203
+ }
204
+
205
+ RegMemImm::Imm { simm32 } => {
206
+ let imm_size = if low8_will_sign_extend_to_32(simm32) {
207
+ 1
208
+ } else {
209
+ if *size == OperandSize::Size16 {
210
+ 2
211
+ } else {
212
+ 4
213
+ }
214
+ };
215
+ let opcode = if imm_size == 1 { 0x6B } else { 0x69 };
216
+ // Yes, really, reg_g twice.
217
+ emit_std_reg_reg(sink, prefix, opcode, 1, reg_g, reg_g, rex);
218
+ emit_simm(sink, imm_size, simm32);
219
+ }
220
+ }
221
+ }
222
+ } else {
223
+ let (opcode_r, opcode_m, subopcode_i) = match op {
224
+ AluRmiROpcode::Add => (0x01, 0x03, 0),
225
+ AluRmiROpcode::Adc => (0x11, 0x03, 0),
226
+ AluRmiROpcode::Sub => (0x29, 0x2B, 5),
227
+ AluRmiROpcode::Sbb => (0x19, 0x2B, 5),
228
+ AluRmiROpcode::And => (0x21, 0x23, 4),
229
+ AluRmiROpcode::Or => (0x09, 0x0B, 1),
230
+ AluRmiROpcode::Xor => (0x31, 0x33, 6),
231
+ AluRmiROpcode::Mul => panic!("unreachable"),
232
+ };
233
+
234
+ let (opcode_r, opcode_m) = if *size == OperandSize::Size8 {
235
+ (opcode_r - 1, opcode_m - 1)
236
+ } else {
237
+ (opcode_r, opcode_m)
238
+ };
239
+
240
+ if *size == OperandSize::Size8 {
241
+ debug_assert!(reg_g.is_real());
242
+ rex.always_emit_if_8bit_needed(reg_g);
243
+ }
244
+
245
+ match src2 {
246
+ RegMemImm::Reg { reg: reg_e } => {
247
+ if *size == OperandSize::Size8 {
248
+ debug_assert!(reg_e.is_real());
249
+ rex.always_emit_if_8bit_needed(reg_e);
250
+ }
251
+
252
+ // GCC/llvm use the swapped operand encoding (viz., the R/RM vs RM/R
253
+ // duality). Do this too, so as to be able to compare generated machine
254
+ // code easily.
255
+ emit_std_reg_reg(sink, prefix, opcode_r, 1, reg_e, reg_g, rex);
256
+ }
257
+
258
+ RegMemImm::Mem { addr } => {
259
+ let amode = addr.finalize(state, sink);
260
+ // Here we revert to the "normal" G-E ordering.
261
+ emit_std_reg_mem(sink, prefix, opcode_m, 1, reg_g, &amode, rex, 0);
262
+ }
263
+
264
+ RegMemImm::Imm { simm32 } => {
265
+ let imm_size = if *size == OperandSize::Size8 {
266
+ 1
267
+ } else {
268
+ if low8_will_sign_extend_to_32(simm32) {
269
+ 1
270
+ } else {
271
+ if *size == OperandSize::Size16 {
272
+ 2
273
+ } else {
274
+ 4
275
+ }
276
+ }
277
+ };
278
+
279
+ let opcode = if *size == OperandSize::Size8 {
280
+ 0x80
281
+ } else if low8_will_sign_extend_to_32(simm32) {
282
+ 0x83
283
+ } else {
284
+ 0x81
285
+ };
286
+
287
+ // And also here we use the "normal" G-E ordering.
288
+ let enc_g = int_reg_enc(reg_g);
289
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode_i, enc_g, rex);
290
+ emit_simm(sink, imm_size, simm32);
291
+ }
292
+ }
293
+ }
294
+ }
295
+
296
+ Inst::AluConstOp { op, size, dst } => {
297
+ let dst = allocs.next(dst.to_reg().to_reg());
298
+ emit(
299
+ &Inst::AluRmiR {
300
+ size: *size,
301
+ op: *op,
302
+ dst: Writable::from_reg(Gpr::new(dst).unwrap()),
303
+ src1: Gpr::new(dst).unwrap(),
304
+ src2: Gpr::new(dst).unwrap().into(),
305
+ },
306
+ allocs,
307
+ sink,
308
+ info,
309
+ state,
310
+ );
311
+ }
312
+
313
+ Inst::AluRM {
314
+ size,
315
+ src1_dst,
316
+ src2,
317
+ op,
318
+ } => {
319
+ let src2 = allocs.next(src2.to_reg());
320
+ let src1_dst = src1_dst.finalize(state, sink).with_allocs(allocs);
321
+
322
+ let opcode = match op {
323
+ AluRmiROpcode::Add => 0x01,
324
+ AluRmiROpcode::Sub => 0x29,
325
+ AluRmiROpcode::And => 0x21,
326
+ AluRmiROpcode::Or => 0x09,
327
+ AluRmiROpcode::Xor => 0x31,
328
+ _ => panic!("Unsupported read-modify-write ALU opcode"),
329
+ };
330
+
331
+ let prefix = if *size == OperandSize::Size16 {
332
+ LegacyPrefixes::_66
333
+ } else {
334
+ LegacyPrefixes::None
335
+ };
336
+ let opcode = if *size == OperandSize::Size8 {
337
+ opcode - 1
338
+ } else {
339
+ opcode
340
+ };
341
+
342
+ let mut rex = RexFlags::from(*size);
343
+ if *size == OperandSize::Size8 {
344
+ debug_assert!(src2.is_real());
345
+ rex.always_emit_if_8bit_needed(src2);
346
+ }
347
+
348
+ let enc_g = int_reg_enc(src2);
349
+ emit_std_enc_mem(sink, prefix, opcode, 1, enc_g, &src1_dst, rex, 0);
350
+ }
351
+
352
+ Inst::AluRmRVex {
353
+ size,
354
+ op,
355
+ dst,
356
+ src1,
357
+ src2,
358
+ } => {
359
+ use AluRmROpcode::*;
360
+ let dst = allocs.next(dst.to_reg().to_reg());
361
+ let src1 = allocs.next(src1.to_reg());
362
+ let src2 = allocs.next(src2.to_reg());
363
+
364
+ let w = match size {
365
+ OperandSize::Size32 => false,
366
+ OperandSize::Size64 => true,
367
+
368
+ // the other cases would be rejected by isle constructors
369
+ _ => unreachable!(),
370
+ };
371
+
372
+ let opcode = match op {
373
+ Andn => 0xf2,
374
+ };
375
+
376
+ VexInstruction::new()
377
+ .map(OpcodeMap::_0F38)
378
+ .w(w)
379
+ .reg(dst.to_real_reg().unwrap().hw_enc())
380
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
381
+ .rm(src2.to_real_reg().unwrap().hw_enc())
382
+ .opcode(opcode)
383
+ .encode(sink);
384
+ }
385
+
386
+ Inst::UnaryRmR { size, op, src, dst } => {
387
+ let dst = allocs.next(dst.to_reg().to_reg());
388
+ let rex_flags = RexFlags::from(*size);
389
+ use UnaryRmROpcode::*;
390
+ let prefix = match size {
391
+ OperandSize::Size16 => match op {
392
+ Bsr | Bsf => LegacyPrefixes::_66,
393
+ Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_66F3,
394
+ },
395
+ OperandSize::Size32 | OperandSize::Size64 => match op {
396
+ Bsr | Bsf => LegacyPrefixes::None,
397
+ Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_F3,
398
+ },
399
+ _ => unreachable!(),
400
+ };
401
+
402
+ let (opcode, num_opcodes) = match op {
403
+ Bsr => (0x0fbd, 2),
404
+ Bsf => (0x0fbc, 2),
405
+ Lzcnt => (0x0fbd, 2),
406
+ Tzcnt => (0x0fbc, 2),
407
+ Popcnt => (0x0fb8, 2),
408
+ };
409
+
410
+ match src.clone().into() {
411
+ RegMem::Reg { reg: src } => {
412
+ let src = allocs.next(src);
413
+ emit_std_reg_reg(sink, prefix, opcode, num_opcodes, dst, src, rex_flags);
414
+ }
415
+ RegMem::Mem { addr: src } => {
416
+ let amode = src.finalize(state, sink).with_allocs(allocs);
417
+ emit_std_reg_mem(sink, prefix, opcode, num_opcodes, dst, &amode, rex_flags, 0);
418
+ }
419
+ }
420
+ }
421
+
422
+ Inst::UnaryRmRVex { size, op, src, dst } => {
423
+ let dst = allocs.next(dst.to_reg().to_reg());
424
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
425
+ RegMem::Reg { reg } => {
426
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
427
+ }
428
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
429
+ };
430
+
431
+ let (opcode, opcode_ext) = match op {
432
+ UnaryRmRVexOpcode::Blsr => (0xF3, 1),
433
+ UnaryRmRVexOpcode::Blsmsk => (0xF3, 2),
434
+ UnaryRmRVexOpcode::Blsi => (0xF3, 3),
435
+ };
436
+
437
+ VexInstruction::new()
438
+ .map(OpcodeMap::_0F38)
439
+ .w(*size == OperandSize::Size64)
440
+ .opcode(opcode)
441
+ .reg(opcode_ext)
442
+ .vvvv(dst.to_real_reg().unwrap().hw_enc())
443
+ .rm(src)
444
+ .encode(sink);
445
+ }
446
+
447
+ Inst::Not { size, src, dst } => {
448
+ let src = allocs.next(src.to_reg());
449
+ let dst = allocs.next(dst.to_reg().to_reg());
450
+ debug_assert_eq!(src, dst);
451
+ let rex_flags = RexFlags::from((*size, dst));
452
+ let (opcode, prefix) = match size {
453
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
454
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
455
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
456
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
457
+ };
458
+
459
+ let subopcode = 2;
460
+ let enc_src = int_reg_enc(dst);
461
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
462
+ }
463
+
464
+ Inst::Neg { size, src, dst } => {
465
+ let src = allocs.next(src.to_reg());
466
+ let dst = allocs.next(dst.to_reg().to_reg());
467
+ debug_assert_eq!(src, dst);
468
+ let rex_flags = RexFlags::from((*size, dst));
469
+ let (opcode, prefix) = match size {
470
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
471
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
472
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
473
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
474
+ };
475
+
476
+ let subopcode = 3;
477
+ let enc_src = int_reg_enc(dst);
478
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
479
+ }
480
+
481
+ Inst::Div {
482
+ sign,
483
+ trap,
484
+ divisor,
485
+ ..
486
+ }
487
+ | Inst::Div8 {
488
+ sign,
489
+ trap,
490
+ divisor,
491
+ ..
492
+ } => {
493
+ let divisor = divisor.clone().to_reg_mem().with_allocs(allocs);
494
+ let size = match inst {
495
+ Inst::Div {
496
+ size,
497
+ dividend_lo,
498
+ dividend_hi,
499
+ dst_quotient,
500
+ dst_remainder,
501
+ ..
502
+ } => {
503
+ let dividend_lo = allocs.next(dividend_lo.to_reg());
504
+ let dividend_hi = allocs.next(dividend_hi.to_reg());
505
+ let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
506
+ let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
507
+ debug_assert_eq!(dividend_lo, regs::rax());
508
+ debug_assert_eq!(dividend_hi, regs::rdx());
509
+ debug_assert_eq!(dst_quotient, regs::rax());
510
+ debug_assert_eq!(dst_remainder, regs::rdx());
511
+ *size
512
+ }
513
+ Inst::Div8 { dividend, dst, .. } => {
514
+ let dividend = allocs.next(dividend.to_reg());
515
+ let dst = allocs.next(dst.to_reg().to_reg());
516
+ debug_assert_eq!(dividend, regs::rax());
517
+ debug_assert_eq!(dst, regs::rax());
518
+ OperandSize::Size8
519
+ }
520
+ _ => unreachable!(),
521
+ };
522
+
523
+ let (opcode, prefix) = match size {
524
+ OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
525
+ OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
526
+ OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
527
+ OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
528
+ };
529
+
530
+ sink.add_trap(*trap);
531
+
532
+ let subopcode = match sign {
533
+ DivSignedness::Signed => 7,
534
+ DivSignedness::Unsigned => 6,
535
+ };
536
+ match divisor {
537
+ RegMem::Reg { reg } => {
538
+ let src = int_reg_enc(reg);
539
+ emit_std_enc_enc(
540
+ sink,
541
+ prefix,
542
+ opcode,
543
+ 1,
544
+ subopcode,
545
+ src,
546
+ RexFlags::from((size, reg)),
547
+ )
548
+ }
549
+ RegMem::Mem { addr: src } => {
550
+ let amode = src.finalize(state, sink);
551
+ emit_std_enc_mem(
552
+ sink,
553
+ prefix,
554
+ opcode,
555
+ 1,
556
+ subopcode,
557
+ &amode,
558
+ RexFlags::from(size),
559
+ 0,
560
+ );
561
+ }
562
+ }
563
+ }
564
+
565
+ Inst::MulHi {
566
+ size,
567
+ signed,
568
+ src1,
569
+ src2,
570
+ dst_lo,
571
+ dst_hi,
572
+ } => {
573
+ let src1 = allocs.next(src1.to_reg());
574
+ let dst_lo = allocs.next(dst_lo.to_reg().to_reg());
575
+ let dst_hi = allocs.next(dst_hi.to_reg().to_reg());
576
+ debug_assert_eq!(src1, regs::rax());
577
+ debug_assert_eq!(dst_lo, regs::rax());
578
+ debug_assert_eq!(dst_hi, regs::rdx());
579
+
580
+ let rex_flags = RexFlags::from(*size);
581
+ let prefix = match size {
582
+ OperandSize::Size16 => LegacyPrefixes::_66,
583
+ OperandSize::Size32 => LegacyPrefixes::None,
584
+ OperandSize::Size64 => LegacyPrefixes::None,
585
+ _ => unreachable!(),
586
+ };
587
+
588
+ let subopcode = if *signed { 5 } else { 4 };
589
+ match src2.clone().to_reg_mem() {
590
+ RegMem::Reg { reg } => {
591
+ let reg = allocs.next(reg);
592
+ let src = int_reg_enc(reg);
593
+ emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags)
594
+ }
595
+ RegMem::Mem { addr: src } => {
596
+ let amode = src.finalize(state, sink).with_allocs(allocs);
597
+ emit_std_enc_mem(sink, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0);
598
+ }
599
+ }
600
+ }
601
+
602
+ Inst::UMulLo {
603
+ size,
604
+ src1,
605
+ src2,
606
+ dst,
607
+ } => {
608
+ let src1 = allocs.next(src1.to_reg());
609
+ let dst = allocs.next(dst.to_reg().to_reg());
610
+ debug_assert_eq!(src1, regs::rax());
611
+ debug_assert_eq!(dst, regs::rax());
612
+
613
+ let mut rex = RexFlags::from(*size);
614
+ let prefix = match size {
615
+ OperandSize::Size16 => LegacyPrefixes::_66,
616
+ _ => LegacyPrefixes::None,
617
+ };
618
+
619
+ let opcode = if *size == OperandSize::Size8 {
620
+ 0xF6
621
+ } else {
622
+ 0xF7
623
+ };
624
+
625
+ match src2.clone().to_reg_mem() {
626
+ RegMem::Reg { reg } => {
627
+ let reg = allocs.next(reg);
628
+ if *size == OperandSize::Size8 {
629
+ rex.always_emit_if_8bit_needed(reg);
630
+ }
631
+ let reg_e = int_reg_enc(reg);
632
+ emit_std_enc_enc(sink, prefix, opcode, 1, 4, reg_e, rex);
633
+ }
634
+ RegMem::Mem { addr: src } => {
635
+ let amode = src.finalize(state, sink).with_allocs(allocs);
636
+ emit_std_enc_mem(sink, prefix, opcode, 1, 4, &amode, rex, 0);
637
+ }
638
+ }
639
+ }
640
+
641
+ Inst::SignExtendData { size, src, dst } => {
642
+ let src = allocs.next(src.to_reg());
643
+ let dst = allocs.next(dst.to_reg().to_reg());
644
+ debug_assert_eq!(src, regs::rax());
645
+ if *size == OperandSize::Size8 {
646
+ debug_assert_eq!(dst, regs::rax());
647
+ } else {
648
+ debug_assert_eq!(dst, regs::rdx());
649
+ }
650
+ match size {
651
+ OperandSize::Size8 => {
652
+ sink.put1(0x66);
653
+ sink.put1(0x98);
654
+ }
655
+ OperandSize::Size16 => {
656
+ sink.put1(0x66);
657
+ sink.put1(0x99);
658
+ }
659
+ OperandSize::Size32 => sink.put1(0x99),
660
+ OperandSize::Size64 => {
661
+ sink.put1(0x48);
662
+ sink.put1(0x99);
663
+ }
664
+ }
665
+ }
666
+
667
+ Inst::CheckedSRemSeq { divisor, .. } | Inst::CheckedSRemSeq8 { divisor, .. } => {
668
+ let divisor = allocs.next(divisor.to_reg());
669
+
670
+ // Validate that the register constraints of the dividend and the
671
+ // destination are all as expected.
672
+ let (dst, size) = match inst {
673
+ Inst::CheckedSRemSeq {
674
+ dividend_lo,
675
+ dividend_hi,
676
+ dst_quotient,
677
+ dst_remainder,
678
+ size,
679
+ ..
680
+ } => {
681
+ let dividend_lo = allocs.next(dividend_lo.to_reg());
682
+ let dividend_hi = allocs.next(dividend_hi.to_reg());
683
+ let dst_quotient = allocs.next(dst_quotient.to_reg().to_reg());
684
+ let dst_remainder = allocs.next(dst_remainder.to_reg().to_reg());
685
+ debug_assert_eq!(dividend_lo, regs::rax());
686
+ debug_assert_eq!(dividend_hi, regs::rdx());
687
+ debug_assert_eq!(dst_quotient, regs::rax());
688
+ debug_assert_eq!(dst_remainder, regs::rdx());
689
+ (regs::rdx(), *size)
690
+ }
691
+ Inst::CheckedSRemSeq8 { dividend, dst, .. } => {
692
+ let dividend = allocs.next(dividend.to_reg());
693
+ let dst = allocs.next(dst.to_reg().to_reg());
694
+ debug_assert_eq!(dividend, regs::rax());
695
+ debug_assert_eq!(dst, regs::rax());
696
+ (regs::rax(), OperandSize::Size8)
697
+ }
698
+ _ => unreachable!(),
699
+ };
700
+
701
+ // Generates the following code sequence:
702
+ //
703
+ // cmp -1 %divisor
704
+ // jnz $do_op
705
+ //
706
+ // ;; for srem, result is 0
707
+ // mov #0, %dst
708
+ // j $done
709
+ //
710
+ // $do_op:
711
+ // idiv %divisor
712
+ //
713
+ // $done:
714
+
715
+ let do_op = sink.get_label();
716
+ let done_label = sink.get_label();
717
+
718
+ // Check if the divisor is -1, and if it isn't then immediately
719
+ // go to the `idiv`.
720
+ let inst = Inst::cmp_rmi_r(size, RegMemImm::imm(0xffffffff), divisor);
721
+ inst.emit(&[], sink, info, state);
722
+ one_way_jmp(sink, CC::NZ, do_op);
723
+
724
+ // ... otherwise the divisor is -1 and the result is always 0. This
725
+ // is written to the destination register which will be %rax for
726
+ // 8-bit srem and %rdx otherwise.
727
+ //
728
+ // Note that for 16-to-64-bit srem operations this leaves the
729
+ // second destination, %rax, unchanged. This isn't semantically
730
+ // correct if a lowering actually tries to use the `dst_quotient`
731
+ // output but for srem only the `dst_remainder` output is used for
732
+ // now.
733
+ let inst = Inst::imm(OperandSize::Size64, 0, Writable::from_reg(dst));
734
+ inst.emit(&[], sink, info, state);
735
+ let inst = Inst::jmp_known(done_label);
736
+ inst.emit(&[], sink, info, state);
737
+
738
+ // Here the `idiv` is executed, which is different depending on the
739
+ // size
740
+ sink.bind_label(do_op, &mut state.ctrl_plane);
741
+ let inst = match size {
742
+ OperandSize::Size8 => Inst::div8(
743
+ DivSignedness::Signed,
744
+ TrapCode::IntegerDivisionByZero,
745
+ RegMem::reg(divisor),
746
+ Gpr::new(regs::rax()).unwrap(),
747
+ Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
748
+ ),
749
+ _ => Inst::div(
750
+ size,
751
+ DivSignedness::Signed,
752
+ TrapCode::IntegerDivisionByZero,
753
+ RegMem::reg(divisor),
754
+ Gpr::new(regs::rax()).unwrap(),
755
+ Gpr::new(regs::rdx()).unwrap(),
756
+ Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
757
+ Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
758
+ ),
759
+ };
760
+ inst.emit(&[], sink, info, state);
761
+
762
+ sink.bind_label(done_label, &mut state.ctrl_plane);
763
+ }
764
+
765
+ Inst::Imm {
766
+ dst_size,
767
+ simm64,
768
+ dst,
769
+ } => {
770
+ let dst = allocs.next(dst.to_reg().to_reg());
771
+ let enc_dst = int_reg_enc(dst);
772
+ if *dst_size == OperandSize::Size64 {
773
+ if low32_will_sign_extend_to_64(*simm64) {
774
+ // Sign-extended move imm32.
775
+ emit_std_enc_enc(
776
+ sink,
777
+ LegacyPrefixes::None,
778
+ 0xC7,
779
+ 1,
780
+ /* subopcode */ 0,
781
+ enc_dst,
782
+ RexFlags::set_w(),
783
+ );
784
+ sink.put4(*simm64 as u32);
785
+ } else {
786
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
787
+ sink.put1(0xB8 | (enc_dst & 7));
788
+ sink.put8(*simm64);
789
+ }
790
+ } else {
791
+ if ((enc_dst >> 3) & 1) == 1 {
792
+ sink.put1(0x41);
793
+ }
794
+ sink.put1(0xB8 | (enc_dst & 7));
795
+ sink.put4(*simm64 as u32);
796
+ }
797
+ }
798
+
799
+ Inst::MovImmM { size, simm64, dst } => {
800
+ let dst = &dst.finalize(state, sink).with_allocs(allocs);
801
+ let default_rex = RexFlags::clear_w();
802
+ let default_opcode = 0xC7;
803
+ let bytes = size.to_bytes();
804
+ let prefix = LegacyPrefixes::None;
805
+
806
+ let (opcode, rex, size, prefix) = match *size {
807
+ // In the 8-bit case, we don't need to enforce REX flags via
808
+ // `always_emit_if_8bit_needed()` since the destination
809
+ // operand is a memory operand, not a possibly 8-bit register.
810
+ OperandSize::Size8 => (0xC6, default_rex, bytes, prefix),
811
+ OperandSize::Size16 => (0xC7, default_rex, bytes, LegacyPrefixes::_66),
812
+ OperandSize::Size64 => {
813
+ if !low32_will_sign_extend_to_64(*simm64) {
814
+ panic!("Immediate-to-memory moves require immediate operand to sign-extend to 64 bits.");
815
+ }
816
+
817
+ (default_opcode, RexFlags::from(*size), bytes, prefix)
818
+ }
819
+
820
+ _ => (default_opcode, default_rex, bytes, prefix),
821
+ };
822
+
823
+ // 8-bit C6 /0 ib
824
+ // 16-bit 0x66 C7 /0 iw
825
+ // 32-bit C7 /0 id
826
+ // 64-bit REX.W C7 /0 id
827
+ emit_std_enc_mem(sink, prefix, opcode, 1, /*subopcode*/ 0, dst, rex, 0);
828
+ emit_simm(sink, size, *simm64 as u32);
829
+ }
830
+
831
+ Inst::MovRR { size, src, dst } => {
832
+ let src = allocs.next(src.to_reg());
833
+ let dst = allocs.next(dst.to_reg().to_reg());
834
+ emit_std_reg_reg(
835
+ sink,
836
+ LegacyPrefixes::None,
837
+ 0x89,
838
+ 1,
839
+ src,
840
+ dst,
841
+ RexFlags::from(*size),
842
+ );
843
+ }
844
+
845
+ Inst::MovFromPReg { src, dst } => {
846
+ allocs.next_fixed_nonallocatable(*src);
847
+ let src: Reg = (*src).into();
848
+ debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&src));
849
+ let src = Gpr::new(src).unwrap();
850
+ let size = OperandSize::Size64;
851
+ let dst = allocs.next(dst.to_reg().to_reg());
852
+ let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
853
+ Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
854
+ }
855
+
856
+ Inst::MovToPReg { src, dst } => {
857
+ let src = allocs.next(src.to_reg());
858
+ let src = Gpr::new(src).unwrap();
859
+ allocs.next_fixed_nonallocatable(*dst);
860
+ let dst: Reg = (*dst).into();
861
+ debug_assert!([regs::rsp(), regs::rbp(), regs::pinned_reg()].contains(&dst));
862
+ let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst)).unwrap();
863
+ let size = OperandSize::Size64;
864
+ Inst::MovRR { size, src, dst }.emit(&[], sink, info, state);
865
+ }
866
+
867
+ Inst::MovzxRmR { ext_mode, src, dst } => {
868
+ let dst = allocs.next(dst.to_reg().to_reg());
869
+ let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
870
+ ExtMode::BL => {
871
+ // MOVZBL is (REX.W==0) 0F B6 /r
872
+ (0x0FB6, 2, RexFlags::clear_w())
873
+ }
874
+ ExtMode::BQ => {
875
+ // MOVZBQ is (REX.W==1) 0F B6 /r
876
+ // I'm not sure why the Intel manual offers different
877
+ // encodings for MOVZBQ than for MOVZBL. AIUI they should
878
+ // achieve the same, since MOVZBL is just going to zero out
879
+ // the upper half of the destination anyway.
880
+ (0x0FB6, 2, RexFlags::set_w())
881
+ }
882
+ ExtMode::WL => {
883
+ // MOVZWL is (REX.W==0) 0F B7 /r
884
+ (0x0FB7, 2, RexFlags::clear_w())
885
+ }
886
+ ExtMode::WQ => {
887
+ // MOVZWQ is (REX.W==1) 0F B7 /r
888
+ (0x0FB7, 2, RexFlags::set_w())
889
+ }
890
+ ExtMode::LQ => {
891
+ // This is just a standard 32 bit load, and we rely on the
892
+ // default zero-extension rule to perform the extension.
893
+ // Note that in reg/reg mode, gcc seems to use the swapped form R/RM, which we
894
+ // don't do here, since it's the same encoding size.
895
+ // MOV r/m32, r32 is (REX.W==0) 8B /r
896
+ (0x8B, 1, RexFlags::clear_w())
897
+ }
898
+ };
899
+
900
+ match src.clone().to_reg_mem() {
901
+ RegMem::Reg { reg: src } => {
902
+ let src = allocs.next(src);
903
+ match ext_mode {
904
+ ExtMode::BL | ExtMode::BQ => {
905
+ // A redundant REX prefix must be emitted for certain register inputs.
906
+ rex_flags.always_emit_if_8bit_needed(src);
907
+ }
908
+ _ => {}
909
+ }
910
+ emit_std_reg_reg(
911
+ sink,
912
+ LegacyPrefixes::None,
913
+ opcodes,
914
+ num_opcodes,
915
+ dst,
916
+ src,
917
+ rex_flags,
918
+ )
919
+ }
920
+
921
+ RegMem::Mem { addr: src } => {
922
+ let src = &src.finalize(state, sink).with_allocs(allocs);
923
+
924
+ emit_std_reg_mem(
925
+ sink,
926
+ LegacyPrefixes::None,
927
+ opcodes,
928
+ num_opcodes,
929
+ dst,
930
+ src,
931
+ rex_flags,
932
+ 0,
933
+ )
934
+ }
935
+ }
936
+ }
937
+
938
+ Inst::Mov64MR { src, dst } => {
939
+ let dst = allocs.next(dst.to_reg().to_reg());
940
+ let src = &src.finalize(state, sink).with_allocs(allocs);
941
+
942
+ emit_std_reg_mem(
943
+ sink,
944
+ LegacyPrefixes::None,
945
+ 0x8B,
946
+ 1,
947
+ dst,
948
+ src,
949
+ RexFlags::set_w(),
950
+ 0,
951
+ )
952
+ }
953
+
954
+ Inst::LoadEffectiveAddress { addr, dst, size } => {
955
+ let dst = allocs.next(dst.to_reg().to_reg());
956
+ let amode = addr.finalize(state, sink).with_allocs(allocs);
957
+
958
+ // If this `lea` can actually get encoded as an `add` then do that
959
+ // instead. Currently all candidate `iadd`s become an `lea`
960
+ // pseudo-instruction here but maximizing the sue of `lea` is not
961
+ // necessarily optimal. The `lea` instruction goes through dedicated
962
+ // address units on cores which are finite and disjoint from the
963
+ // general ALU, so if everything uses `lea` then those units can get
964
+ // saturated while leaving the ALU idle.
965
+ //
966
+ // To help make use of more parts of a cpu, this attempts to use
967
+ // `add` when it's semantically equivalent to `lea`, or otherwise
968
+ // when the `dst` register is the same as the `base` or `index`
969
+ // register.
970
+ //
971
+ // FIXME: ideally regalloc is informed of this constraint. Register
972
+ // allocation of `lea` should "attempt" to put the `base` in the
973
+ // same register as `dst` but not at the expense of generating a
974
+ // `mov` instruction. Currently that's not possible but perhaps one
975
+ // day it may be worth it.
976
+ match amode {
977
+ // If `base == dst` then this is `add $imm, %dst`, so encode
978
+ // that instead.
979
+ Amode::ImmReg {
980
+ simm32,
981
+ base,
982
+ flags: _,
983
+ } if base == dst => {
984
+ let inst = Inst::alu_rmi_r(
985
+ *size,
986
+ AluRmiROpcode::Add,
987
+ RegMemImm::imm(simm32),
988
+ Writable::from_reg(dst),
989
+ );
990
+ inst.emit(&[], sink, info, state);
991
+ }
992
+ // If the offset is 0 and the shift is 0 (meaning multiplication
993
+ // by 1) then:
994
+ //
995
+ // * If `base == dst`, then this is `add %index, %base`
996
+ // * If `index == dst`, then this is `add %base, %index`
997
+ //
998
+ // Encode the appropriate instruction here in that case.
999
+ Amode::ImmRegRegShift {
1000
+ simm32: 0,
1001
+ base,
1002
+ index,
1003
+ shift: 0,
1004
+ flags: _,
1005
+ } if base == dst || index == dst => {
1006
+ let (dst, operand) = if base == dst {
1007
+ (base, index)
1008
+ } else {
1009
+ (index, base)
1010
+ };
1011
+ let inst = Inst::alu_rmi_r(
1012
+ *size,
1013
+ AluRmiROpcode::Add,
1014
+ RegMemImm::reg(operand.to_reg()),
1015
+ Writable::from_reg(dst.to_reg()),
1016
+ );
1017
+ inst.emit(&[], sink, info, state);
1018
+ }
1019
+
1020
+ // If `lea`'s 3-operand mode is leveraged by regalloc, or if
1021
+ // it's fancy like imm-plus-shift-plus-base, then `lea` is
1022
+ // actually emitted.
1023
+ _ => {
1024
+ let flags = match size {
1025
+ OperandSize::Size32 => RexFlags::clear_w(),
1026
+ OperandSize::Size64 => RexFlags::set_w(),
1027
+ _ => unreachable!(),
1028
+ };
1029
+ emit_std_reg_mem(sink, LegacyPrefixes::None, 0x8D, 1, dst, &amode, flags, 0);
1030
+ }
1031
+ };
1032
+ }
1033
+
1034
+ Inst::MovsxRmR { ext_mode, src, dst } => {
1035
+ let dst = allocs.next(dst.to_reg().to_reg());
1036
+ let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
1037
+ ExtMode::BL => {
1038
+ // MOVSBL is (REX.W==0) 0F BE /r
1039
+ (0x0FBE, 2, RexFlags::clear_w())
1040
+ }
1041
+ ExtMode::BQ => {
1042
+ // MOVSBQ is (REX.W==1) 0F BE /r
1043
+ (0x0FBE, 2, RexFlags::set_w())
1044
+ }
1045
+ ExtMode::WL => {
1046
+ // MOVSWL is (REX.W==0) 0F BF /r
1047
+ (0x0FBF, 2, RexFlags::clear_w())
1048
+ }
1049
+ ExtMode::WQ => {
1050
+ // MOVSWQ is (REX.W==1) 0F BF /r
1051
+ (0x0FBF, 2, RexFlags::set_w())
1052
+ }
1053
+ ExtMode::LQ => {
1054
+ // MOVSLQ is (REX.W==1) 63 /r
1055
+ (0x63, 1, RexFlags::set_w())
1056
+ }
1057
+ };
1058
+
1059
+ match src.clone().to_reg_mem() {
1060
+ RegMem::Reg { reg: src } => {
1061
+ let src = allocs.next(src);
1062
+ match ext_mode {
1063
+ ExtMode::BL | ExtMode::BQ => {
1064
+ // A redundant REX prefix must be emitted for certain register inputs.
1065
+ rex_flags.always_emit_if_8bit_needed(src);
1066
+ }
1067
+ _ => {}
1068
+ }
1069
+ emit_std_reg_reg(
1070
+ sink,
1071
+ LegacyPrefixes::None,
1072
+ opcodes,
1073
+ num_opcodes,
1074
+ dst,
1075
+ src,
1076
+ rex_flags,
1077
+ )
1078
+ }
1079
+
1080
+ RegMem::Mem { addr: src } => {
1081
+ let src = &src.finalize(state, sink).with_allocs(allocs);
1082
+
1083
+ emit_std_reg_mem(
1084
+ sink,
1085
+ LegacyPrefixes::None,
1086
+ opcodes,
1087
+ num_opcodes,
1088
+ dst,
1089
+ src,
1090
+ rex_flags,
1091
+ 0,
1092
+ )
1093
+ }
1094
+ }
1095
+ }
1096
+
1097
+ Inst::MovRM { size, src, dst } => {
1098
+ let src = allocs.next(src.to_reg());
1099
+ let dst = &dst.finalize(state, sink).with_allocs(allocs);
1100
+
1101
+ let prefix = match size {
1102
+ OperandSize::Size16 => LegacyPrefixes::_66,
1103
+ _ => LegacyPrefixes::None,
1104
+ };
1105
+
1106
+ let opcode = match size {
1107
+ OperandSize::Size8 => 0x88,
1108
+ _ => 0x89,
1109
+ };
1110
+
1111
+ // This is one of the few places where the presence of a
1112
+ // redundant REX prefix changes the meaning of the
1113
+ // instruction.
1114
+ let rex = RexFlags::from((*size, src));
1115
+
1116
+ // 8-bit: MOV r8, r/m8 is (REX.W==0) 88 /r
1117
+ // 16-bit: MOV r16, r/m16 is 66 (REX.W==0) 89 /r
1118
+ // 32-bit: MOV r32, r/m32 is (REX.W==0) 89 /r
1119
+ // 64-bit: MOV r64, r/m64 is (REX.W==1) 89 /r
1120
+ emit_std_reg_mem(sink, prefix, opcode, 1, src, dst, rex, 0);
1121
+ }
1122
+
1123
+ Inst::ShiftR {
1124
+ size,
1125
+ kind,
1126
+ src,
1127
+ num_bits,
1128
+ dst,
1129
+ } => {
1130
+ let src = allocs.next(src.to_reg());
1131
+ let dst = allocs.next(dst.to_reg().to_reg());
1132
+ debug_assert_eq!(src, dst);
1133
+ let subopcode = match kind {
1134
+ ShiftKind::RotateLeft => 0,
1135
+ ShiftKind::RotateRight => 1,
1136
+ ShiftKind::ShiftLeft => 4,
1137
+ ShiftKind::ShiftRightLogical => 5,
1138
+ ShiftKind::ShiftRightArithmetic => 7,
1139
+ };
1140
+ let enc_dst = int_reg_enc(dst);
1141
+ let rex_flags = RexFlags::from((*size, dst));
1142
+ match num_bits.clone().to_imm8_reg() {
1143
+ Imm8Reg::Reg { reg } => {
1144
+ let reg = allocs.next(reg);
1145
+ debug_assert_eq!(reg, regs::rcx());
1146
+ let (opcode, prefix) = match size {
1147
+ OperandSize::Size8 => (0xD2, LegacyPrefixes::None),
1148
+ OperandSize::Size16 => (0xD3, LegacyPrefixes::_66),
1149
+ OperandSize::Size32 => (0xD3, LegacyPrefixes::None),
1150
+ OperandSize::Size64 => (0xD3, LegacyPrefixes::None),
1151
+ };
1152
+
1153
+ // SHL/SHR/SAR %cl, reg8 is (REX.W==0) D2 /subopcode
1154
+ // SHL/SHR/SAR %cl, reg16 is 66 (REX.W==0) D3 /subopcode
1155
+ // SHL/SHR/SAR %cl, reg32 is (REX.W==0) D3 /subopcode
1156
+ // SHL/SHR/SAR %cl, reg64 is (REX.W==1) D3 /subopcode
1157
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1158
+ }
1159
+
1160
+ Imm8Reg::Imm8 { imm: num_bits } => {
1161
+ let (opcode, prefix) = match size {
1162
+ OperandSize::Size8 => (0xC0, LegacyPrefixes::None),
1163
+ OperandSize::Size16 => (0xC1, LegacyPrefixes::_66),
1164
+ OperandSize::Size32 => (0xC1, LegacyPrefixes::None),
1165
+ OperandSize::Size64 => (0xC1, LegacyPrefixes::None),
1166
+ };
1167
+
1168
+ // SHL/SHR/SAR $ib, reg8 is (REX.W==0) C0 /subopcode
1169
+ // SHL/SHR/SAR $ib, reg16 is 66 (REX.W==0) C1 /subopcode
1170
+ // SHL/SHR/SAR $ib, reg32 is (REX.W==0) C1 /subopcode ib
1171
+ // SHL/SHR/SAR $ib, reg64 is (REX.W==1) C1 /subopcode ib
1172
+ // When the shift amount is 1, there's an even shorter encoding, but we don't
1173
+ // bother with that nicety here.
1174
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
1175
+ sink.put1(num_bits);
1176
+ }
1177
+ }
1178
+ }
1179
+
1180
+ Inst::XmmRmiReg {
1181
+ opcode,
1182
+ src1,
1183
+ src2,
1184
+ dst,
1185
+ } => {
1186
+ let src1 = allocs.next(src1.to_reg());
1187
+ let dst = allocs.next(dst.to_reg().to_reg());
1188
+ debug_assert_eq!(src1, dst);
1189
+ let rex = RexFlags::clear_w();
1190
+ let prefix = LegacyPrefixes::_66;
1191
+ let src2 = src2.clone().to_reg_mem_imm();
1192
+ if let RegMemImm::Imm { simm32 } = src2 {
1193
+ let (opcode_bytes, reg_digit) = match opcode {
1194
+ SseOpcode::Psllw => (0x0F71, 6),
1195
+ SseOpcode::Pslld => (0x0F72, 6),
1196
+ SseOpcode::Psllq => (0x0F73, 6),
1197
+ SseOpcode::Psraw => (0x0F71, 4),
1198
+ SseOpcode::Psrad => (0x0F72, 4),
1199
+ SseOpcode::Psrlw => (0x0F71, 2),
1200
+ SseOpcode::Psrld => (0x0F72, 2),
1201
+ SseOpcode::Psrlq => (0x0F73, 2),
1202
+ _ => panic!("invalid opcode: {}", opcode),
1203
+ };
1204
+ let dst_enc = reg_enc(dst);
1205
+ emit_std_enc_enc(sink, prefix, opcode_bytes, 2, reg_digit, dst_enc, rex);
1206
+ let imm = (simm32)
1207
+ .try_into()
1208
+ .expect("the immediate must be convertible to a u8");
1209
+ sink.put1(imm);
1210
+ } else {
1211
+ let opcode_bytes = match opcode {
1212
+ SseOpcode::Psllw => 0x0FF1,
1213
+ SseOpcode::Pslld => 0x0FF2,
1214
+ SseOpcode::Psllq => 0x0FF3,
1215
+ SseOpcode::Psraw => 0x0FE1,
1216
+ SseOpcode::Psrad => 0x0FE2,
1217
+ SseOpcode::Psrlw => 0x0FD1,
1218
+ SseOpcode::Psrld => 0x0FD2,
1219
+ SseOpcode::Psrlq => 0x0FD3,
1220
+ _ => panic!("invalid opcode: {}", opcode),
1221
+ };
1222
+
1223
+ match src2 {
1224
+ RegMemImm::Reg { reg } => {
1225
+ let reg = allocs.next(reg);
1226
+ emit_std_reg_reg(sink, prefix, opcode_bytes, 2, dst, reg, rex);
1227
+ }
1228
+ RegMemImm::Mem { addr } => {
1229
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1230
+ emit_std_reg_mem(sink, prefix, opcode_bytes, 2, dst, addr, rex, 0);
1231
+ }
1232
+ RegMemImm::Imm { .. } => unreachable!(),
1233
+ }
1234
+ };
1235
+ }
1236
+
1237
+ Inst::CmpRmiR {
1238
+ size,
1239
+ src: src_e,
1240
+ dst: reg_g,
1241
+ opcode,
1242
+ } => {
1243
+ let reg_g = allocs.next(reg_g.to_reg());
1244
+
1245
+ let is_cmp = match opcode {
1246
+ CmpOpcode::Cmp => true,
1247
+ CmpOpcode::Test => false,
1248
+ };
1249
+
1250
+ let mut prefix = LegacyPrefixes::None;
1251
+ if *size == OperandSize::Size16 {
1252
+ prefix = LegacyPrefixes::_66;
1253
+ }
1254
+ // A redundant REX prefix can change the meaning of this instruction.
1255
+ let mut rex = RexFlags::from((*size, reg_g));
1256
+
1257
+ match src_e.clone().to_reg_mem_imm() {
1258
+ RegMemImm::Reg { reg: reg_e } => {
1259
+ let reg_e = allocs.next(reg_e);
1260
+ if *size == OperandSize::Size8 {
1261
+ // Check whether the E register forces the use of a redundant REX.
1262
+ rex.always_emit_if_8bit_needed(reg_e);
1263
+ }
1264
+
1265
+ // Use the swapped operands encoding for CMP, to stay consistent with the output of
1266
+ // gcc/llvm.
1267
+ let opcode = match (*size, is_cmp) {
1268
+ (OperandSize::Size8, true) => 0x38,
1269
+ (_, true) => 0x39,
1270
+ (OperandSize::Size8, false) => 0x84,
1271
+ (_, false) => 0x85,
1272
+ };
1273
+ emit_std_reg_reg(sink, prefix, opcode, 1, reg_e, reg_g, rex);
1274
+ }
1275
+
1276
+ RegMemImm::Mem { addr } => {
1277
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1278
+ // Whereas here we revert to the "normal" G-E ordering for CMP.
1279
+ let opcode = match (*size, is_cmp) {
1280
+ (OperandSize::Size8, true) => 0x3A,
1281
+ (_, true) => 0x3B,
1282
+ (OperandSize::Size8, false) => 0x84,
1283
+ (_, false) => 0x85,
1284
+ };
1285
+ emit_std_reg_mem(sink, prefix, opcode, 1, reg_g, addr, rex, 0);
1286
+ }
1287
+
1288
+ RegMemImm::Imm { simm32 } => {
1289
+ // FIXME JRS 2020Feb11: there are shorter encodings for
1290
+ // cmp $imm, rax/eax/ax/al.
1291
+ let use_imm8 = is_cmp && low8_will_sign_extend_to_32(simm32);
1292
+
1293
+ // And also here we use the "normal" G-E ordering.
1294
+ let opcode = if is_cmp {
1295
+ if *size == OperandSize::Size8 {
1296
+ 0x80
1297
+ } else if use_imm8 {
1298
+ 0x83
1299
+ } else {
1300
+ 0x81
1301
+ }
1302
+ } else {
1303
+ if *size == OperandSize::Size8 {
1304
+ 0xF6
1305
+ } else {
1306
+ 0xF7
1307
+ }
1308
+ };
1309
+ let subopcode = if is_cmp { 7 } else { 0 };
1310
+
1311
+ let enc_g = int_reg_enc(reg_g);
1312
+ emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_g, rex);
1313
+ emit_simm(sink, if use_imm8 { 1 } else { size.to_bytes() }, simm32);
1314
+ }
1315
+ }
1316
+ }
1317
+
1318
+ Inst::Setcc { cc, dst } => {
1319
+ let dst = allocs.next(dst.to_reg().to_reg());
1320
+ let opcode = 0x0f90 + cc.get_enc() as u32;
1321
+ let mut rex_flags = RexFlags::clear_w();
1322
+ rex_flags.always_emit();
1323
+ emit_std_enc_enc(
1324
+ sink,
1325
+ LegacyPrefixes::None,
1326
+ opcode,
1327
+ 2,
1328
+ 0,
1329
+ reg_enc(dst),
1330
+ rex_flags,
1331
+ );
1332
+ }
1333
+
1334
+ Inst::Bswap { size, src, dst } => {
1335
+ let src = allocs.next(src.to_reg());
1336
+ let dst = allocs.next(dst.to_reg().to_reg());
1337
+ debug_assert_eq!(src, dst);
1338
+ let enc_reg = int_reg_enc(dst);
1339
+
1340
+ // BSWAP reg32 is (REX.W==0) 0F C8
1341
+ // BSWAP reg64 is (REX.W==1) 0F C8
1342
+ let rex_flags = RexFlags::from(*size);
1343
+ rex_flags.emit_one_op(sink, enc_reg);
1344
+
1345
+ sink.put1(0x0F);
1346
+ sink.put1(0xC8 | (enc_reg & 7));
1347
+ }
1348
+
1349
+ Inst::Cmove {
1350
+ size,
1351
+ cc,
1352
+ consequent,
1353
+ alternative,
1354
+ dst,
1355
+ } => {
1356
+ let alternative = allocs.next(alternative.to_reg());
1357
+ let dst = allocs.next(dst.to_reg().to_reg());
1358
+ debug_assert_eq!(alternative, dst);
1359
+ let rex_flags = RexFlags::from(*size);
1360
+ let prefix = match size {
1361
+ OperandSize::Size16 => LegacyPrefixes::_66,
1362
+ OperandSize::Size32 => LegacyPrefixes::None,
1363
+ OperandSize::Size64 => LegacyPrefixes::None,
1364
+ _ => unreachable!("invalid size spec for cmove"),
1365
+ };
1366
+ let opcode = 0x0F40 + cc.get_enc() as u32;
1367
+ match consequent.clone().to_reg_mem() {
1368
+ RegMem::Reg { reg } => {
1369
+ let reg = allocs.next(reg);
1370
+ emit_std_reg_reg(sink, prefix, opcode, 2, dst, reg, rex_flags);
1371
+ }
1372
+ RegMem::Mem { addr } => {
1373
+ let addr = &addr.finalize(state, sink).with_allocs(allocs);
1374
+ emit_std_reg_mem(sink, prefix, opcode, 2, dst, addr, rex_flags, 0);
1375
+ }
1376
+ }
1377
+ }
1378
+
1379
+ Inst::XmmCmove {
1380
+ ty,
1381
+ cc,
1382
+ consequent,
1383
+ alternative,
1384
+ dst,
1385
+ } => {
1386
+ let alternative = allocs.next(alternative.to_reg());
1387
+ let dst = allocs.next(dst.to_reg().to_reg());
1388
+ debug_assert_eq!(alternative, dst);
1389
+ let consequent = consequent.clone().to_reg_mem().with_allocs(allocs);
1390
+
1391
+ // Lowering of the Select IR opcode when the input is an fcmp relies on the fact that
1392
+ // this doesn't clobber flags. Make sure to not do so here.
1393
+ let next = sink.get_label();
1394
+
1395
+ // Jump if cc is *not* set.
1396
+ one_way_jmp(sink, cc.invert(), next);
1397
+
1398
+ let op = match *ty {
1399
+ types::F64 => SseOpcode::Movsd,
1400
+ types::F32 => SseOpcode::Movsd,
1401
+ types::F32X4 => SseOpcode::Movaps,
1402
+ types::F64X2 => SseOpcode::Movapd,
1403
+ ty => {
1404
+ debug_assert!(ty.is_vector() && ty.bytes() == 16);
1405
+ SseOpcode::Movdqa
1406
+ }
1407
+ };
1408
+ let inst = Inst::xmm_unary_rm_r(op, consequent, Writable::from_reg(dst));
1409
+ inst.emit(&[], sink, info, state);
1410
+
1411
+ sink.bind_label(next, &mut state.ctrl_plane);
1412
+ }
1413
+
1414
+ Inst::Push64 { src } => {
1415
+ let src = src.clone().to_reg_mem_imm().with_allocs(allocs);
1416
+
1417
+ match src {
1418
+ RegMemImm::Reg { reg } => {
1419
+ let enc_reg = int_reg_enc(reg);
1420
+ let rex = 0x40 | ((enc_reg >> 3) & 1);
1421
+ if rex != 0x40 {
1422
+ sink.put1(rex);
1423
+ }
1424
+ sink.put1(0x50 | (enc_reg & 7));
1425
+ }
1426
+
1427
+ RegMemImm::Mem { addr } => {
1428
+ let addr = &addr.finalize(state, sink);
1429
+ emit_std_enc_mem(
1430
+ sink,
1431
+ LegacyPrefixes::None,
1432
+ 0xFF,
1433
+ 1,
1434
+ 6, /*subopcode*/
1435
+ addr,
1436
+ RexFlags::clear_w(),
1437
+ 0,
1438
+ );
1439
+ }
1440
+
1441
+ RegMemImm::Imm { simm32 } => {
1442
+ if low8_will_sign_extend_to_64(simm32) {
1443
+ sink.put1(0x6A);
1444
+ sink.put1(simm32 as u8);
1445
+ } else {
1446
+ sink.put1(0x68);
1447
+ sink.put4(simm32);
1448
+ }
1449
+ }
1450
+ }
1451
+ }
1452
+
1453
+ Inst::Pop64 { dst } => {
1454
+ let dst = allocs.next(dst.to_reg().to_reg());
1455
+ let enc_dst = int_reg_enc(dst);
1456
+ if enc_dst >= 8 {
1457
+ // 0x41 == REX.{W=0, B=1}. It seems that REX.W is irrelevant here.
1458
+ sink.put1(0x41);
1459
+ }
1460
+ sink.put1(0x58 + (enc_dst & 7));
1461
+ }
1462
+
1463
+ Inst::StackProbeLoop {
1464
+ tmp,
1465
+ frame_size,
1466
+ guard_size,
1467
+ } => {
1468
+ assert!(info.flags.enable_probestack());
1469
+ assert!(guard_size.is_power_of_two());
1470
+
1471
+ let tmp = allocs.next_writable(*tmp);
1472
+
1473
+ // Number of probes that we need to perform
1474
+ let probe_count = align_to(*frame_size, *guard_size) / guard_size;
1475
+
1476
+ // The inline stack probe loop has 3 phases:
1477
+ //
1478
+ // We generate the "guard area" register which is essentially the frame_size aligned to
1479
+ // guard_size. We copy the stack pointer and subtract the guard area from it. This
1480
+ // gets us a register that we can use to compare when looping.
1481
+ //
1482
+ // After that we emit the loop. Essentially we just adjust the stack pointer one guard_size'd
1483
+ // distance at a time and then touch the stack by writing anything to it. We use the previously
1484
+ // created "guard area" register to know when to stop looping.
1485
+ //
1486
+ // When we have touched all the pages that we need, we have to restore the stack pointer
1487
+ // to where it was before.
1488
+ //
1489
+ // Generate the following code:
1490
+ // mov tmp_reg, rsp
1491
+ // sub tmp_reg, guard_size * probe_count
1492
+ // .loop_start:
1493
+ // sub rsp, guard_size
1494
+ // mov [rsp], rsp
1495
+ // cmp rsp, tmp_reg
1496
+ // jne .loop_start
1497
+ // add rsp, guard_size * probe_count
1498
+
1499
+ // Create the guard bound register
1500
+ // mov tmp_reg, rsp
1501
+ let inst = Inst::gen_move(tmp, regs::rsp(), types::I64);
1502
+ inst.emit(&[], sink, info, state);
1503
+
1504
+ // sub tmp_reg, GUARD_SIZE * probe_count
1505
+ let inst = Inst::alu_rmi_r(
1506
+ OperandSize::Size64,
1507
+ AluRmiROpcode::Sub,
1508
+ RegMemImm::imm(guard_size * probe_count),
1509
+ tmp,
1510
+ );
1511
+ inst.emit(&[], sink, info, state);
1512
+
1513
+ // Emit the main loop!
1514
+ let loop_start = sink.get_label();
1515
+ sink.bind_label(loop_start, &mut state.ctrl_plane);
1516
+
1517
+ // sub rsp, GUARD_SIZE
1518
+ let inst = Inst::alu_rmi_r(
1519
+ OperandSize::Size64,
1520
+ AluRmiROpcode::Sub,
1521
+ RegMemImm::imm(*guard_size),
1522
+ Writable::from_reg(regs::rsp()),
1523
+ );
1524
+ inst.emit(&[], sink, info, state);
1525
+
1526
+ // TODO: `mov [rsp], 0` would be better, but we don't have that instruction
1527
+ // Probe the stack! We don't use Inst::gen_store_stack here because we need a predictable
1528
+ // instruction size.
1529
+ // mov [rsp], rsp
1530
+ let inst = Inst::mov_r_m(
1531
+ OperandSize::Size32, // Use Size32 since it saves us one byte
1532
+ regs::rsp(),
1533
+ SyntheticAmode::Real(Amode::imm_reg(0, regs::rsp())),
1534
+ );
1535
+ inst.emit(&[], sink, info, state);
1536
+
1537
+ // Compare and jump if we are not done yet
1538
+ // cmp rsp, tmp_reg
1539
+ let inst = Inst::cmp_rmi_r(
1540
+ OperandSize::Size64,
1541
+ RegMemImm::reg(regs::rsp()),
1542
+ tmp.to_reg(),
1543
+ );
1544
+ inst.emit(&[], sink, info, state);
1545
+
1546
+ // jne .loop_start
1547
+ // TODO: Encoding the JmpIf as a short jump saves us 4 bytes here.
1548
+ one_way_jmp(sink, CC::NZ, loop_start);
1549
+
1550
+ // The regular prologue code is going to emit a `sub` after this, so we need to
1551
+ // reset the stack pointer
1552
+ //
1553
+ // TODO: It would be better if we could avoid the `add` + `sub` that is generated here
1554
+ // and in the stack adj portion of the prologue
1555
+ //
1556
+ // add rsp, GUARD_SIZE * probe_count
1557
+ let inst = Inst::alu_rmi_r(
1558
+ OperandSize::Size64,
1559
+ AluRmiROpcode::Add,
1560
+ RegMemImm::imm(guard_size * probe_count),
1561
+ Writable::from_reg(regs::rsp()),
1562
+ );
1563
+ inst.emit(&[], sink, info, state);
1564
+ }
1565
+
1566
+ Inst::CallKnown {
1567
+ dest,
1568
+ info: call_info,
1569
+ ..
1570
+ } => {
1571
+ if let Some(s) = state.take_stack_map() {
1572
+ sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s);
1573
+ }
1574
+ sink.put1(0xE8);
1575
+ // The addend adjusts for the difference between the end of the instruction and the
1576
+ // beginning of the immediate field.
1577
+ emit_reloc(sink, Reloc::X86CallPCRel4, &dest, -4);
1578
+ sink.put4(0);
1579
+ if call_info.opcode.is_call() {
1580
+ sink.add_call_site(call_info.opcode);
1581
+ }
1582
+ }
1583
+
1584
+ Inst::CallUnknown {
1585
+ dest,
1586
+ info: call_info,
1587
+ ..
1588
+ } => {
1589
+ let dest = dest.with_allocs(allocs);
1590
+
1591
+ let start_offset = sink.cur_offset();
1592
+ match dest {
1593
+ RegMem::Reg { reg } => {
1594
+ let reg_enc = int_reg_enc(reg);
1595
+ emit_std_enc_enc(
1596
+ sink,
1597
+ LegacyPrefixes::None,
1598
+ 0xFF,
1599
+ 1,
1600
+ 2, /*subopcode*/
1601
+ reg_enc,
1602
+ RexFlags::clear_w(),
1603
+ );
1604
+ }
1605
+
1606
+ RegMem::Mem { addr } => {
1607
+ let addr = &addr.finalize(state, sink);
1608
+ emit_std_enc_mem(
1609
+ sink,
1610
+ LegacyPrefixes::None,
1611
+ 0xFF,
1612
+ 1,
1613
+ 2, /*subopcode*/
1614
+ addr,
1615
+ RexFlags::clear_w(),
1616
+ 0,
1617
+ );
1618
+ }
1619
+ }
1620
+ if let Some(s) = state.take_stack_map() {
1621
+ sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s);
1622
+ }
1623
+ if call_info.opcode.is_call() {
1624
+ sink.add_call_site(call_info.opcode);
1625
+ }
1626
+ }
1627
+
1628
+ Inst::Args { .. } => {}
1629
+
1630
+ Inst::Ret {
1631
+ stack_bytes_to_pop: 0,
1632
+ ..
1633
+ } => sink.put1(0xC3),
1634
+
1635
+ Inst::Ret {
1636
+ stack_bytes_to_pop, ..
1637
+ } => {
1638
+ sink.put1(0xC2);
1639
+ sink.put2(u16::try_from(*stack_bytes_to_pop).unwrap());
1640
+ }
1641
+
1642
+ Inst::JmpKnown { dst } => {
1643
+ let br_start = sink.cur_offset();
1644
+ let br_disp_off = br_start + 1;
1645
+ let br_end = br_start + 5;
1646
+
1647
+ sink.use_label_at_offset(br_disp_off, *dst, LabelUse::JmpRel32);
1648
+ sink.add_uncond_branch(br_start, br_end, *dst);
1649
+
1650
+ sink.put1(0xE9);
1651
+ // Placeholder for the label value.
1652
+ sink.put4(0x0);
1653
+ }
1654
+
1655
+ Inst::JmpIf { cc, taken } => {
1656
+ let cond_start = sink.cur_offset();
1657
+ let cond_disp_off = cond_start + 2;
1658
+
1659
+ sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1660
+ // Since this is not a terminator, don't enroll in the branch inversion mechanism.
1661
+
1662
+ sink.put1(0x0F);
1663
+ sink.put1(0x80 + cc.get_enc());
1664
+ // Placeholder for the label value.
1665
+ sink.put4(0x0);
1666
+ }
1667
+
1668
+ Inst::JmpCond {
1669
+ cc,
1670
+ taken,
1671
+ not_taken,
1672
+ } => {
1673
+ // If taken.
1674
+ let cond_start = sink.cur_offset();
1675
+ let cond_disp_off = cond_start + 2;
1676
+ let cond_end = cond_start + 6;
1677
+
1678
+ sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
1679
+ let inverted: [u8; 6] = [0x0F, 0x80 + (cc.invert().get_enc()), 0x00, 0x00, 0x00, 0x00];
1680
+ sink.add_cond_branch(cond_start, cond_end, *taken, &inverted[..]);
1681
+
1682
+ sink.put1(0x0F);
1683
+ sink.put1(0x80 + cc.get_enc());
1684
+ // Placeholder for the label value.
1685
+ sink.put4(0x0);
1686
+
1687
+ // If not taken.
1688
+ let uncond_start = sink.cur_offset();
1689
+ let uncond_disp_off = uncond_start + 1;
1690
+ let uncond_end = uncond_start + 5;
1691
+
1692
+ sink.use_label_at_offset(uncond_disp_off, *not_taken, LabelUse::JmpRel32);
1693
+ sink.add_uncond_branch(uncond_start, uncond_end, *not_taken);
1694
+
1695
+ sink.put1(0xE9);
1696
+ // Placeholder for the label value.
1697
+ sink.put4(0x0);
1698
+ }
1699
+
1700
+ Inst::JmpUnknown { target } => {
1701
+ let target = target.with_allocs(allocs);
1702
+
1703
+ match target {
1704
+ RegMem::Reg { reg } => {
1705
+ let reg_enc = int_reg_enc(reg);
1706
+ emit_std_enc_enc(
1707
+ sink,
1708
+ LegacyPrefixes::None,
1709
+ 0xFF,
1710
+ 1,
1711
+ 4, /*subopcode*/
1712
+ reg_enc,
1713
+ RexFlags::clear_w(),
1714
+ );
1715
+ }
1716
+
1717
+ RegMem::Mem { addr } => {
1718
+ let addr = &addr.finalize(state, sink);
1719
+ emit_std_enc_mem(
1720
+ sink,
1721
+ LegacyPrefixes::None,
1722
+ 0xFF,
1723
+ 1,
1724
+ 4, /*subopcode*/
1725
+ addr,
1726
+ RexFlags::clear_w(),
1727
+ 0,
1728
+ );
1729
+ }
1730
+ }
1731
+ }
1732
+
1733
+ Inst::JmpTableSeq {
1734
+ idx,
1735
+ tmp1,
1736
+ tmp2,
1737
+ ref targets,
1738
+ default_target,
1739
+ ..
1740
+ } => {
1741
+ let idx = allocs.next(*idx);
1742
+ let tmp1 = Writable::from_reg(allocs.next(tmp1.to_reg()));
1743
+ let tmp2 = Writable::from_reg(allocs.next(tmp2.to_reg()));
1744
+
1745
+ // This sequence is *one* instruction in the vcode, and is expanded only here at
1746
+ // emission time, because we cannot allow the regalloc to insert spills/reloads in
1747
+ // the middle; we depend on hardcoded PC-rel addressing below.
1748
+ //
1749
+ // We don't have to worry about emitting islands, because the only label-use type has a
1750
+ // maximum range of 2 GB. If we later consider using shorter-range label references,
1751
+ // this will need to be revisited.
1752
+
1753
+ // We generate the following sequence. Note that the only read of %idx is before the
1754
+ // write to %tmp2, so regalloc may use the same register for both; fix x64/inst/mod.rs
1755
+ // if you change this.
1756
+ // lea start_of_jump_table_offset(%rip), %tmp1
1757
+ // movslq [%tmp1, %idx, 4], %tmp2 ;; shift of 2, viz. multiply index by 4
1758
+ // addq %tmp2, %tmp1
1759
+ // j *%tmp1
1760
+ // $start_of_jump_table:
1761
+ // -- jump table entries
1762
+
1763
+ // Load base address of jump table.
1764
+ let start_of_jumptable = sink.get_label();
1765
+ let inst = Inst::lea(Amode::rip_relative(start_of_jumptable), tmp1);
1766
+ inst.emit(&[], sink, info, state);
1767
+
1768
+ // Load value out of the jump table. It's a relative offset to the target block, so it
1769
+ // might be negative; use a sign-extension.
1770
+ let inst = Inst::movsx_rm_r(
1771
+ ExtMode::LQ,
1772
+ RegMem::mem(Amode::imm_reg_reg_shift(
1773
+ 0,
1774
+ Gpr::new(tmp1.to_reg()).unwrap(),
1775
+ Gpr::new(idx).unwrap(),
1776
+ 2,
1777
+ )),
1778
+ tmp2,
1779
+ );
1780
+ inst.emit(&[], sink, info, state);
1781
+
1782
+ // Add base of jump table to jump-table-sourced block offset.
1783
+ let inst = Inst::alu_rmi_r(
1784
+ OperandSize::Size64,
1785
+ AluRmiROpcode::Add,
1786
+ RegMemImm::reg(tmp2.to_reg()),
1787
+ tmp1,
1788
+ );
1789
+ inst.emit(&[], sink, info, state);
1790
+
1791
+ // Branch to computed address.
1792
+ let inst = Inst::jmp_unknown(RegMem::reg(tmp1.to_reg()));
1793
+ inst.emit(&[], sink, info, state);
1794
+
1795
+ // Emit jump table (table of 32-bit offsets).
1796
+ sink.bind_label(start_of_jumptable, &mut state.ctrl_plane);
1797
+ let jt_off = sink.cur_offset();
1798
+ for &target in targets.iter().chain(std::iter::once(default_target)) {
1799
+ let word_off = sink.cur_offset();
1800
+ // off_into_table is an addend here embedded in the label to be later patched at
1801
+ // the end of codegen. The offset is initially relative to this jump table entry;
1802
+ // with the extra addend, it'll be relative to the jump table's start, after
1803
+ // patching.
1804
+ let off_into_table = word_off - jt_off;
1805
+ sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
1806
+ sink.put4(off_into_table);
1807
+ }
1808
+ }
1809
+
1810
+ Inst::TrapIf { cc, trap_code } => {
1811
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1812
+ one_way_jmp(sink, *cc, trap_label);
1813
+ }
1814
+
1815
+ Inst::TrapIfAnd {
1816
+ cc1,
1817
+ cc2,
1818
+ trap_code,
1819
+ } => {
1820
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1821
+ let else_label = sink.get_label();
1822
+
1823
+ // Jump to the end if the first condition isn't true, and then if
1824
+ // the second condition is true go to the trap.
1825
+ one_way_jmp(sink, cc1.invert(), else_label);
1826
+ one_way_jmp(sink, *cc2, trap_label);
1827
+
1828
+ sink.bind_label(else_label, &mut state.ctrl_plane);
1829
+ }
1830
+
1831
+ Inst::TrapIfOr {
1832
+ cc1,
1833
+ cc2,
1834
+ trap_code,
1835
+ } => {
1836
+ let trap_label = sink.defer_trap(*trap_code, state.take_stack_map());
1837
+
1838
+ // Emit two jumps to the same trap if either condition code is true.
1839
+ one_way_jmp(sink, *cc1, trap_label);
1840
+ one_way_jmp(sink, *cc2, trap_label);
1841
+ }
1842
+
1843
+ Inst::XmmUnaryRmR { op, src, dst } => {
1844
+ emit(
1845
+ &Inst::XmmUnaryRmRUnaligned {
1846
+ op: *op,
1847
+ src: XmmMem::new(src.clone().into()).unwrap(),
1848
+ dst: *dst,
1849
+ },
1850
+ allocs,
1851
+ sink,
1852
+ info,
1853
+ state,
1854
+ );
1855
+ }
1856
+
1857
+ Inst::XmmUnaryRmRUnaligned {
1858
+ op,
1859
+ src: src_e,
1860
+ dst: reg_g,
1861
+ } => {
1862
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
1863
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
1864
+
1865
+ let rex = RexFlags::clear_w();
1866
+
1867
+ let (prefix, opcode, num_opcodes) = match op {
1868
+ SseOpcode::Cvtdq2pd => (LegacyPrefixes::_F3, 0x0FE6, 2),
1869
+ SseOpcode::Cvtpd2ps => (LegacyPrefixes::_66, 0x0F5A, 2),
1870
+ SseOpcode::Cvtps2pd => (LegacyPrefixes::None, 0x0F5A, 2),
1871
+ SseOpcode::Cvtdq2ps => (LegacyPrefixes::None, 0x0F5B, 2),
1872
+ SseOpcode::Cvtss2sd => (LegacyPrefixes::_F3, 0x0F5A, 2),
1873
+ SseOpcode::Cvtsd2ss => (LegacyPrefixes::_F2, 0x0F5A, 2),
1874
+ SseOpcode::Cvttpd2dq => (LegacyPrefixes::_66, 0x0FE6, 2),
1875
+ SseOpcode::Cvttps2dq => (LegacyPrefixes::_F3, 0x0F5B, 2),
1876
+ SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F28, 2),
1877
+ SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F28, 2),
1878
+ SseOpcode::Movdqa => (LegacyPrefixes::_66, 0x0F6F, 2),
1879
+ SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F6F, 2),
1880
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
1881
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
1882
+ SseOpcode::Movups => (LegacyPrefixes::None, 0x0F10, 2),
1883
+ SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F10, 2),
1884
+ SseOpcode::Pabsb => (LegacyPrefixes::_66, 0x0F381C, 3),
1885
+ SseOpcode::Pabsw => (LegacyPrefixes::_66, 0x0F381D, 3),
1886
+ SseOpcode::Pabsd => (LegacyPrefixes::_66, 0x0F381E, 3),
1887
+ SseOpcode::Pmovsxbd => (LegacyPrefixes::_66, 0x0F3821, 3),
1888
+ SseOpcode::Pmovsxbw => (LegacyPrefixes::_66, 0x0F3820, 3),
1889
+ SseOpcode::Pmovsxbq => (LegacyPrefixes::_66, 0x0F3822, 3),
1890
+ SseOpcode::Pmovsxwd => (LegacyPrefixes::_66, 0x0F3823, 3),
1891
+ SseOpcode::Pmovsxwq => (LegacyPrefixes::_66, 0x0F3824, 3),
1892
+ SseOpcode::Pmovsxdq => (LegacyPrefixes::_66, 0x0F3825, 3),
1893
+ SseOpcode::Pmovzxbd => (LegacyPrefixes::_66, 0x0F3831, 3),
1894
+ SseOpcode::Pmovzxbw => (LegacyPrefixes::_66, 0x0F3830, 3),
1895
+ SseOpcode::Pmovzxbq => (LegacyPrefixes::_66, 0x0F3832, 3),
1896
+ SseOpcode::Pmovzxwd => (LegacyPrefixes::_66, 0x0F3833, 3),
1897
+ SseOpcode::Pmovzxwq => (LegacyPrefixes::_66, 0x0F3834, 3),
1898
+ SseOpcode::Pmovzxdq => (LegacyPrefixes::_66, 0x0F3835, 3),
1899
+ SseOpcode::Sqrtps => (LegacyPrefixes::None, 0x0F51, 2),
1900
+ SseOpcode::Sqrtpd => (LegacyPrefixes::_66, 0x0F51, 2),
1901
+ SseOpcode::Sqrtss => (LegacyPrefixes::_F3, 0x0F51, 2),
1902
+ SseOpcode::Sqrtsd => (LegacyPrefixes::_F2, 0x0F51, 2),
1903
+ SseOpcode::Movddup => (LegacyPrefixes::_F2, 0x0F12, 2),
1904
+ _ => unimplemented!("Opcode {:?} not implemented", op),
1905
+ };
1906
+
1907
+ match src_e {
1908
+ RegMem::Reg { reg: reg_e } => {
1909
+ emit_std_reg_reg(sink, prefix, opcode, num_opcodes, reg_g, reg_e, rex);
1910
+ }
1911
+ RegMem::Mem { addr } => {
1912
+ let addr = &addr.finalize(state, sink);
1913
+ emit_std_reg_mem(sink, prefix, opcode, num_opcodes, reg_g, addr, rex, 0);
1914
+ }
1915
+ };
1916
+ }
1917
+
1918
+ Inst::XmmUnaryRmRImm { op, src, dst, imm } => {
1919
+ let dst = allocs.next(dst.to_reg().to_reg());
1920
+ let src = src.clone().to_reg_mem().with_allocs(allocs);
1921
+ let rex = RexFlags::clear_w();
1922
+
1923
+ let (prefix, opcode, len) = match op {
1924
+ SseOpcode::Roundps => (LegacyPrefixes::_66, 0x0F3A08, 3),
1925
+ SseOpcode::Roundss => (LegacyPrefixes::_66, 0x0F3A0A, 3),
1926
+ SseOpcode::Roundpd => (LegacyPrefixes::_66, 0x0F3A09, 3),
1927
+ SseOpcode::Roundsd => (LegacyPrefixes::_66, 0x0F3A0B, 3),
1928
+ SseOpcode::Pshufd => (LegacyPrefixes::_66, 0x0F70, 2),
1929
+ SseOpcode::Pshuflw => (LegacyPrefixes::_F2, 0x0F70, 2),
1930
+ SseOpcode::Pshufhw => (LegacyPrefixes::_F3, 0x0F70, 2),
1931
+ _ => unimplemented!("Opcode {:?} not implemented", op),
1932
+ };
1933
+ match src {
1934
+ RegMem::Reg { reg } => {
1935
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
1936
+ }
1937
+ RegMem::Mem { addr } => {
1938
+ let addr = &addr.finalize(state, sink);
1939
+ // N.B.: bytes_at_end == 1, because of the `imm` byte below.
1940
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
1941
+ }
1942
+ }
1943
+ sink.put1(*imm);
1944
+ }
1945
+
1946
+ Inst::XmmUnaryRmREvex { op, src, dst } => {
1947
+ let dst = allocs.next(dst.to_reg().to_reg());
1948
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
1949
+ RegMem::Reg { reg } => {
1950
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
1951
+ }
1952
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
1953
+ };
1954
+
1955
+ let (prefix, map, w, opcode) = match op {
1956
+ Avx512Opcode::Vcvtudq2ps => (LegacyPrefixes::_F2, OpcodeMap::_0F, false, 0x7a),
1957
+ Avx512Opcode::Vpabsq => (LegacyPrefixes::_66, OpcodeMap::_0F38, true, 0x1f),
1958
+ Avx512Opcode::Vpopcntb => (LegacyPrefixes::_66, OpcodeMap::_0F38, false, 0x54),
1959
+ _ => unimplemented!("Opcode {:?} not implemented", op),
1960
+ };
1961
+ EvexInstruction::new()
1962
+ .length(EvexVectorLength::V128)
1963
+ .prefix(prefix)
1964
+ .map(map)
1965
+ .w(w)
1966
+ .opcode(opcode)
1967
+ .tuple_type(op.tuple_type())
1968
+ .reg(dst.to_real_reg().unwrap().hw_enc())
1969
+ .rm(src)
1970
+ .encode(sink);
1971
+ }
1972
+
1973
+ Inst::XmmUnaryRmRImmEvex { op, src, dst, imm } => {
1974
+ let dst = allocs.next(dst.to_reg().to_reg());
1975
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
1976
+ RegMem::Reg { reg } => {
1977
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
1978
+ }
1979
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
1980
+ };
1981
+
1982
+ let (opcode, opcode_ext, w) = match op {
1983
+ Avx512Opcode::VpsraqImm => (0x72, 4, true),
1984
+ _ => unimplemented!("Opcode {:?} not implemented", op),
1985
+ };
1986
+ EvexInstruction::new()
1987
+ .length(EvexVectorLength::V128)
1988
+ .prefix(LegacyPrefixes::_66)
1989
+ .map(OpcodeMap::_0F)
1990
+ .w(w)
1991
+ .opcode(opcode)
1992
+ .reg(opcode_ext)
1993
+ .vvvvv(dst.to_real_reg().unwrap().hw_enc())
1994
+ .tuple_type(op.tuple_type())
1995
+ .rm(src)
1996
+ .imm(*imm)
1997
+ .encode(sink);
1998
+ }
1999
+
2000
+ Inst::XmmRmR {
2001
+ op,
2002
+ src1,
2003
+ src2,
2004
+ dst,
2005
+ } => emit(
2006
+ &Inst::XmmRmRUnaligned {
2007
+ op: *op,
2008
+ dst: *dst,
2009
+ src1: *src1,
2010
+ src2: XmmMem::new(src2.clone().to_reg_mem()).unwrap(),
2011
+ },
2012
+ allocs,
2013
+ sink,
2014
+ info,
2015
+ state,
2016
+ ),
2017
+
2018
+ Inst::XmmRmRUnaligned {
2019
+ op,
2020
+ src1,
2021
+ src2: src_e,
2022
+ dst: reg_g,
2023
+ } => {
2024
+ let src1 = allocs.next(src1.to_reg());
2025
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
2026
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
2027
+ debug_assert_eq!(src1, reg_g);
2028
+
2029
+ let rex = RexFlags::clear_w();
2030
+ let (prefix, opcode, length) = match op {
2031
+ SseOpcode::Addps => (LegacyPrefixes::None, 0x0F58, 2),
2032
+ SseOpcode::Addpd => (LegacyPrefixes::_66, 0x0F58, 2),
2033
+ SseOpcode::Addss => (LegacyPrefixes::_F3, 0x0F58, 2),
2034
+ SseOpcode::Addsd => (LegacyPrefixes::_F2, 0x0F58, 2),
2035
+ SseOpcode::Andps => (LegacyPrefixes::None, 0x0F54, 2),
2036
+ SseOpcode::Andpd => (LegacyPrefixes::_66, 0x0F54, 2),
2037
+ SseOpcode::Andnps => (LegacyPrefixes::None, 0x0F55, 2),
2038
+ SseOpcode::Andnpd => (LegacyPrefixes::_66, 0x0F55, 2),
2039
+ SseOpcode::Divps => (LegacyPrefixes::None, 0x0F5E, 2),
2040
+ SseOpcode::Divpd => (LegacyPrefixes::_66, 0x0F5E, 2),
2041
+ SseOpcode::Divss => (LegacyPrefixes::_F3, 0x0F5E, 2),
2042
+ SseOpcode::Divsd => (LegacyPrefixes::_F2, 0x0F5E, 2),
2043
+ SseOpcode::Maxps => (LegacyPrefixes::None, 0x0F5F, 2),
2044
+ SseOpcode::Maxpd => (LegacyPrefixes::_66, 0x0F5F, 2),
2045
+ SseOpcode::Maxss => (LegacyPrefixes::_F3, 0x0F5F, 2),
2046
+ SseOpcode::Maxsd => (LegacyPrefixes::_F2, 0x0F5F, 2),
2047
+ SseOpcode::Minps => (LegacyPrefixes::None, 0x0F5D, 2),
2048
+ SseOpcode::Minpd => (LegacyPrefixes::_66, 0x0F5D, 2),
2049
+ SseOpcode::Minss => (LegacyPrefixes::_F3, 0x0F5D, 2),
2050
+ SseOpcode::Minsd => (LegacyPrefixes::_F2, 0x0F5D, 2),
2051
+ SseOpcode::Movlhps => (LegacyPrefixes::None, 0x0F16, 2),
2052
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
2053
+ SseOpcode::Mulps => (LegacyPrefixes::None, 0x0F59, 2),
2054
+ SseOpcode::Mulpd => (LegacyPrefixes::_66, 0x0F59, 2),
2055
+ SseOpcode::Mulss => (LegacyPrefixes::_F3, 0x0F59, 2),
2056
+ SseOpcode::Mulsd => (LegacyPrefixes::_F2, 0x0F59, 2),
2057
+ SseOpcode::Orpd => (LegacyPrefixes::_66, 0x0F56, 2),
2058
+ SseOpcode::Orps => (LegacyPrefixes::None, 0x0F56, 2),
2059
+ SseOpcode::Packssdw => (LegacyPrefixes::_66, 0x0F6B, 2),
2060
+ SseOpcode::Packsswb => (LegacyPrefixes::_66, 0x0F63, 2),
2061
+ SseOpcode::Packusdw => (LegacyPrefixes::_66, 0x0F382B, 3),
2062
+ SseOpcode::Packuswb => (LegacyPrefixes::_66, 0x0F67, 2),
2063
+ SseOpcode::Paddb => (LegacyPrefixes::_66, 0x0FFC, 2),
2064
+ SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
2065
+ SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
2066
+ SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
2067
+ SseOpcode::Paddsb => (LegacyPrefixes::_66, 0x0FEC, 2),
2068
+ SseOpcode::Paddsw => (LegacyPrefixes::_66, 0x0FED, 2),
2069
+ SseOpcode::Paddusb => (LegacyPrefixes::_66, 0x0FDC, 2),
2070
+ SseOpcode::Paddusw => (LegacyPrefixes::_66, 0x0FDD, 2),
2071
+ SseOpcode::Pmaddubsw => (LegacyPrefixes::_66, 0x0F3804, 3),
2072
+ SseOpcode::Pand => (LegacyPrefixes::_66, 0x0FDB, 2),
2073
+ SseOpcode::Pandn => (LegacyPrefixes::_66, 0x0FDF, 2),
2074
+ SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
2075
+ SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
2076
+ SseOpcode::Pcmpeqb => (LegacyPrefixes::_66, 0x0F74, 2),
2077
+ SseOpcode::Pcmpeqw => (LegacyPrefixes::_66, 0x0F75, 2),
2078
+ SseOpcode::Pcmpeqd => (LegacyPrefixes::_66, 0x0F76, 2),
2079
+ SseOpcode::Pcmpeqq => (LegacyPrefixes::_66, 0x0F3829, 3),
2080
+ SseOpcode::Pcmpgtb => (LegacyPrefixes::_66, 0x0F64, 2),
2081
+ SseOpcode::Pcmpgtw => (LegacyPrefixes::_66, 0x0F65, 2),
2082
+ SseOpcode::Pcmpgtd => (LegacyPrefixes::_66, 0x0F66, 2),
2083
+ SseOpcode::Pcmpgtq => (LegacyPrefixes::_66, 0x0F3837, 3),
2084
+ SseOpcode::Pmaddwd => (LegacyPrefixes::_66, 0x0FF5, 2),
2085
+ SseOpcode::Pmaxsb => (LegacyPrefixes::_66, 0x0F383C, 3),
2086
+ SseOpcode::Pmaxsw => (LegacyPrefixes::_66, 0x0FEE, 2),
2087
+ SseOpcode::Pmaxsd => (LegacyPrefixes::_66, 0x0F383D, 3),
2088
+ SseOpcode::Pmaxub => (LegacyPrefixes::_66, 0x0FDE, 2),
2089
+ SseOpcode::Pmaxuw => (LegacyPrefixes::_66, 0x0F383E, 3),
2090
+ SseOpcode::Pmaxud => (LegacyPrefixes::_66, 0x0F383F, 3),
2091
+ SseOpcode::Pminsb => (LegacyPrefixes::_66, 0x0F3838, 3),
2092
+ SseOpcode::Pminsw => (LegacyPrefixes::_66, 0x0FEA, 2),
2093
+ SseOpcode::Pminsd => (LegacyPrefixes::_66, 0x0F3839, 3),
2094
+ SseOpcode::Pminub => (LegacyPrefixes::_66, 0x0FDA, 2),
2095
+ SseOpcode::Pminuw => (LegacyPrefixes::_66, 0x0F383A, 3),
2096
+ SseOpcode::Pminud => (LegacyPrefixes::_66, 0x0F383B, 3),
2097
+ SseOpcode::Pmuldq => (LegacyPrefixes::_66, 0x0F3828, 3),
2098
+ SseOpcode::Pmulhw => (LegacyPrefixes::_66, 0x0FE5, 2),
2099
+ SseOpcode::Pmulhrsw => (LegacyPrefixes::_66, 0x0F380B, 3),
2100
+ SseOpcode::Pmulhuw => (LegacyPrefixes::_66, 0x0FE4, 2),
2101
+ SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
2102
+ SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
2103
+ SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
2104
+ SseOpcode::Por => (LegacyPrefixes::_66, 0x0FEB, 2),
2105
+ SseOpcode::Pshufb => (LegacyPrefixes::_66, 0x0F3800, 3),
2106
+ SseOpcode::Psubb => (LegacyPrefixes::_66, 0x0FF8, 2),
2107
+ SseOpcode::Psubd => (LegacyPrefixes::_66, 0x0FFA, 2),
2108
+ SseOpcode::Psubq => (LegacyPrefixes::_66, 0x0FFB, 2),
2109
+ SseOpcode::Psubw => (LegacyPrefixes::_66, 0x0FF9, 2),
2110
+ SseOpcode::Psubsb => (LegacyPrefixes::_66, 0x0FE8, 2),
2111
+ SseOpcode::Psubsw => (LegacyPrefixes::_66, 0x0FE9, 2),
2112
+ SseOpcode::Psubusb => (LegacyPrefixes::_66, 0x0FD8, 2),
2113
+ SseOpcode::Psubusw => (LegacyPrefixes::_66, 0x0FD9, 2),
2114
+ SseOpcode::Punpckhbw => (LegacyPrefixes::_66, 0x0F68, 2),
2115
+ SseOpcode::Punpckhwd => (LegacyPrefixes::_66, 0x0F69, 2),
2116
+ SseOpcode::Punpcklbw => (LegacyPrefixes::_66, 0x0F60, 2),
2117
+ SseOpcode::Punpcklwd => (LegacyPrefixes::_66, 0x0F61, 2),
2118
+ SseOpcode::Punpckldq => (LegacyPrefixes::_66, 0x0F62, 2),
2119
+ SseOpcode::Punpcklqdq => (LegacyPrefixes::_66, 0x0F6C, 2),
2120
+ SseOpcode::Punpckhdq => (LegacyPrefixes::_66, 0x0F6A, 2),
2121
+ SseOpcode::Punpckhqdq => (LegacyPrefixes::_66, 0x0F6D, 2),
2122
+ SseOpcode::Pxor => (LegacyPrefixes::_66, 0x0FEF, 2),
2123
+ SseOpcode::Subps => (LegacyPrefixes::None, 0x0F5C, 2),
2124
+ SseOpcode::Subpd => (LegacyPrefixes::_66, 0x0F5C, 2),
2125
+ SseOpcode::Subss => (LegacyPrefixes::_F3, 0x0F5C, 2),
2126
+ SseOpcode::Subsd => (LegacyPrefixes::_F2, 0x0F5C, 2),
2127
+ SseOpcode::Unpcklps => (LegacyPrefixes::None, 0x0F14, 2),
2128
+ SseOpcode::Unpckhps => (LegacyPrefixes::None, 0x0F15, 2),
2129
+ SseOpcode::Xorps => (LegacyPrefixes::None, 0x0F57, 2),
2130
+ SseOpcode::Xorpd => (LegacyPrefixes::_66, 0x0F57, 2),
2131
+ SseOpcode::Phaddw => (LegacyPrefixes::_66, 0x0F3801, 3),
2132
+ SseOpcode::Phaddd => (LegacyPrefixes::_66, 0x0F3802, 3),
2133
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
2134
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2135
+ };
2136
+
2137
+ match src_e {
2138
+ RegMem::Reg { reg: reg_e } => {
2139
+ emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2140
+ }
2141
+ RegMem::Mem { addr } => {
2142
+ let addr = &addr.finalize(state, sink);
2143
+ emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2144
+ }
2145
+ }
2146
+ }
2147
+
2148
+ Inst::XmmRmRBlend {
2149
+ op,
2150
+ src1,
2151
+ src2,
2152
+ dst,
2153
+ mask,
2154
+ } => {
2155
+ let src1 = allocs.next(src1.to_reg());
2156
+ let mask = allocs.next(mask.to_reg());
2157
+ debug_assert_eq!(mask, regs::xmm0());
2158
+ let reg_g = allocs.next(dst.to_reg().to_reg());
2159
+ debug_assert_eq!(src1, reg_g);
2160
+ let src_e = src2.clone().to_reg_mem().with_allocs(allocs);
2161
+
2162
+ let rex = RexFlags::clear_w();
2163
+ let (prefix, opcode, length) = match op {
2164
+ SseOpcode::Blendvps => (LegacyPrefixes::_66, 0x0F3814, 3),
2165
+ SseOpcode::Blendvpd => (LegacyPrefixes::_66, 0x0F3815, 3),
2166
+ SseOpcode::Pblendvb => (LegacyPrefixes::_66, 0x0F3810, 3),
2167
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2168
+ };
2169
+
2170
+ match src_e {
2171
+ RegMem::Reg { reg: reg_e } => {
2172
+ emit_std_reg_reg(sink, prefix, opcode, length, reg_g, reg_e, rex);
2173
+ }
2174
+ RegMem::Mem { addr } => {
2175
+ let addr = &addr.finalize(state, sink);
2176
+ emit_std_reg_mem(sink, prefix, opcode, length, reg_g, addr, rex, 0);
2177
+ }
2178
+ }
2179
+ }
2180
+
2181
+ Inst::XmmRmiRVex {
2182
+ op,
2183
+ src1,
2184
+ src2,
2185
+ dst,
2186
+ } => {
2187
+ use LegacyPrefixes as LP;
2188
+ use OpcodeMap as OM;
2189
+
2190
+ let dst = allocs.next(dst.to_reg().to_reg());
2191
+ let src1 = allocs.next(src1.to_reg());
2192
+ let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
2193
+
2194
+ let src2 = match src2 {
2195
+ // For opcodes where one of the operands is an immediate the
2196
+ // encoding is a bit different, notably the usage of
2197
+ // `opcode_ext`, so handle that specially here.
2198
+ RegMemImm::Imm { simm32 } => {
2199
+ let (opcode, opcode_ext, prefix) = match op {
2200
+ AvxOpcode::Vpsrlw => (0x71, 2, LegacyPrefixes::_66),
2201
+ AvxOpcode::Vpsrld => (0x72, 2, LegacyPrefixes::_66),
2202
+ AvxOpcode::Vpsrlq => (0x73, 2, LegacyPrefixes::_66),
2203
+ AvxOpcode::Vpsllw => (0x71, 6, LegacyPrefixes::_66),
2204
+ AvxOpcode::Vpslld => (0x72, 6, LegacyPrefixes::_66),
2205
+ AvxOpcode::Vpsllq => (0x73, 6, LegacyPrefixes::_66),
2206
+ AvxOpcode::Vpsraw => (0x71, 4, LegacyPrefixes::_66),
2207
+ AvxOpcode::Vpsrad => (0x72, 4, LegacyPrefixes::_66),
2208
+ _ => panic!("unexpected rmi_r_vex opcode with immediate {op:?}"),
2209
+ };
2210
+ VexInstruction::new()
2211
+ .length(VexVectorLength::V128)
2212
+ .prefix(prefix)
2213
+ .map(OpcodeMap::_0F)
2214
+ .opcode(opcode)
2215
+ .opcode_ext(opcode_ext)
2216
+ .vvvv(dst.to_real_reg().unwrap().hw_enc())
2217
+ .prefix(LegacyPrefixes::_66)
2218
+ .rm(src1.to_real_reg().unwrap().hw_enc())
2219
+ .imm(simm32.try_into().unwrap())
2220
+ .encode(sink);
2221
+ return;
2222
+ }
2223
+ RegMemImm::Reg { reg } => {
2224
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2225
+ }
2226
+ RegMemImm::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2227
+ };
2228
+ let (prefix, map, opcode) = match op {
2229
+ AvxOpcode::Vminps => (LP::None, OM::_0F, 0x5D),
2230
+ AvxOpcode::Vminpd => (LP::_66, OM::_0F, 0x5D),
2231
+ AvxOpcode::Vmaxps => (LP::None, OM::_0F, 0x5F),
2232
+ AvxOpcode::Vmaxpd => (LP::_66, OM::_0F, 0x5F),
2233
+ AvxOpcode::Vandnps => (LP::None, OM::_0F, 0x55),
2234
+ AvxOpcode::Vandnpd => (LP::_66, OM::_0F, 0x55),
2235
+ AvxOpcode::Vpandn => (LP::_66, OM::_0F, 0xDF),
2236
+ AvxOpcode::Vpsrlw => (LP::_66, OM::_0F, 0xD1),
2237
+ AvxOpcode::Vpsrld => (LP::_66, OM::_0F, 0xD2),
2238
+ AvxOpcode::Vpsrlq => (LP::_66, OM::_0F, 0xD3),
2239
+ AvxOpcode::Vpaddb => (LP::_66, OM::_0F, 0xFC),
2240
+ AvxOpcode::Vpaddw => (LP::_66, OM::_0F, 0xFD),
2241
+ AvxOpcode::Vpaddd => (LP::_66, OM::_0F, 0xFE),
2242
+ AvxOpcode::Vpaddq => (LP::_66, OM::_0F, 0xD4),
2243
+ AvxOpcode::Vpaddsb => (LP::_66, OM::_0F, 0xEC),
2244
+ AvxOpcode::Vpaddsw => (LP::_66, OM::_0F, 0xED),
2245
+ AvxOpcode::Vpaddusb => (LP::_66, OM::_0F, 0xDC),
2246
+ AvxOpcode::Vpaddusw => (LP::_66, OM::_0F, 0xDD),
2247
+ AvxOpcode::Vpsubb => (LP::_66, OM::_0F, 0xF8),
2248
+ AvxOpcode::Vpsubw => (LP::_66, OM::_0F, 0xF9),
2249
+ AvxOpcode::Vpsubd => (LP::_66, OM::_0F, 0xFA),
2250
+ AvxOpcode::Vpsubq => (LP::_66, OM::_0F, 0xFB),
2251
+ AvxOpcode::Vpsubsb => (LP::_66, OM::_0F, 0xE8),
2252
+ AvxOpcode::Vpsubsw => (LP::_66, OM::_0F, 0xE9),
2253
+ AvxOpcode::Vpsubusb => (LP::_66, OM::_0F, 0xD8),
2254
+ AvxOpcode::Vpsubusw => (LP::_66, OM::_0F, 0xD9),
2255
+ AvxOpcode::Vpavgb => (LP::_66, OM::_0F, 0xE0),
2256
+ AvxOpcode::Vpavgw => (LP::_66, OM::_0F, 0xE3),
2257
+ AvxOpcode::Vpand => (LP::_66, OM::_0F, 0xDB),
2258
+ AvxOpcode::Vandps => (LP::None, OM::_0F, 0x54),
2259
+ AvxOpcode::Vandpd => (LP::_66, OM::_0F, 0x54),
2260
+ AvxOpcode::Vpor => (LP::_66, OM::_0F, 0xEB),
2261
+ AvxOpcode::Vorps => (LP::None, OM::_0F, 0x56),
2262
+ AvxOpcode::Vorpd => (LP::_66, OM::_0F, 0x56),
2263
+ AvxOpcode::Vpxor => (LP::_66, OM::_0F, 0xEF),
2264
+ AvxOpcode::Vxorps => (LP::None, OM::_0F, 0x57),
2265
+ AvxOpcode::Vxorpd => (LP::_66, OM::_0F, 0x57),
2266
+ AvxOpcode::Vpmullw => (LP::_66, OM::_0F, 0xD5),
2267
+ AvxOpcode::Vpmulld => (LP::_66, OM::_0F38, 0x40),
2268
+ AvxOpcode::Vpmulhw => (LP::_66, OM::_0F, 0xE5),
2269
+ AvxOpcode::Vpmulhrsw => (LP::_66, OM::_0F38, 0x0B),
2270
+ AvxOpcode::Vpmulhuw => (LP::_66, OM::_0F, 0xE4),
2271
+ AvxOpcode::Vpmuldq => (LP::_66, OM::_0F38, 0x28),
2272
+ AvxOpcode::Vpmuludq => (LP::_66, OM::_0F, 0xF4),
2273
+ AvxOpcode::Vpunpckhwd => (LP::_66, OM::_0F, 0x69),
2274
+ AvxOpcode::Vpunpcklwd => (LP::_66, OM::_0F, 0x61),
2275
+ AvxOpcode::Vunpcklps => (LP::None, OM::_0F, 0x14),
2276
+ AvxOpcode::Vunpckhps => (LP::None, OM::_0F, 0x15),
2277
+ AvxOpcode::Vaddps => (LP::None, OM::_0F, 0x58),
2278
+ AvxOpcode::Vaddpd => (LP::_66, OM::_0F, 0x58),
2279
+ AvxOpcode::Vsubps => (LP::None, OM::_0F, 0x5C),
2280
+ AvxOpcode::Vsubpd => (LP::_66, OM::_0F, 0x5C),
2281
+ AvxOpcode::Vmulps => (LP::None, OM::_0F, 0x59),
2282
+ AvxOpcode::Vmulpd => (LP::_66, OM::_0F, 0x59),
2283
+ AvxOpcode::Vdivps => (LP::None, OM::_0F, 0x5E),
2284
+ AvxOpcode::Vdivpd => (LP::_66, OM::_0F, 0x5E),
2285
+ AvxOpcode::Vpcmpeqb => (LP::_66, OM::_0F, 0x74),
2286
+ AvxOpcode::Vpcmpeqw => (LP::_66, OM::_0F, 0x75),
2287
+ AvxOpcode::Vpcmpeqd => (LP::_66, OM::_0F, 0x76),
2288
+ AvxOpcode::Vpcmpeqq => (LP::_66, OM::_0F38, 0x29),
2289
+ AvxOpcode::Vpcmpgtb => (LP::_66, OM::_0F, 0x64),
2290
+ AvxOpcode::Vpcmpgtw => (LP::_66, OM::_0F, 0x65),
2291
+ AvxOpcode::Vpcmpgtd => (LP::_66, OM::_0F, 0x66),
2292
+ AvxOpcode::Vpcmpgtq => (LP::_66, OM::_0F38, 0x37),
2293
+ AvxOpcode::Vmovlhps => (LP::None, OM::_0F, 0x16),
2294
+ AvxOpcode::Vpminsb => (LP::_66, OM::_0F38, 0x38),
2295
+ AvxOpcode::Vpminsw => (LP::_66, OM::_0F, 0xEA),
2296
+ AvxOpcode::Vpminsd => (LP::_66, OM::_0F38, 0x39),
2297
+ AvxOpcode::Vpmaxsb => (LP::_66, OM::_0F38, 0x3C),
2298
+ AvxOpcode::Vpmaxsw => (LP::_66, OM::_0F, 0xEE),
2299
+ AvxOpcode::Vpmaxsd => (LP::_66, OM::_0F38, 0x3D),
2300
+ AvxOpcode::Vpminub => (LP::_66, OM::_0F, 0xDA),
2301
+ AvxOpcode::Vpminuw => (LP::_66, OM::_0F38, 0x3A),
2302
+ AvxOpcode::Vpminud => (LP::_66, OM::_0F38, 0x3B),
2303
+ AvxOpcode::Vpmaxub => (LP::_66, OM::_0F, 0xDE),
2304
+ AvxOpcode::Vpmaxuw => (LP::_66, OM::_0F38, 0x3E),
2305
+ AvxOpcode::Vpmaxud => (LP::_66, OM::_0F38, 0x3F),
2306
+ AvxOpcode::Vpunpcklbw => (LP::_66, OM::_0F, 0x60),
2307
+ AvxOpcode::Vpunpckhbw => (LP::_66, OM::_0F, 0x68),
2308
+ AvxOpcode::Vpacksswb => (LP::_66, OM::_0F, 0x63),
2309
+ AvxOpcode::Vpackssdw => (LP::_66, OM::_0F, 0x6B),
2310
+ AvxOpcode::Vpackuswb => (LP::_66, OM::_0F, 0x67),
2311
+ AvxOpcode::Vpackusdw => (LP::_66, OM::_0F38, 0x2B),
2312
+ AvxOpcode::Vpmaddwd => (LP::_66, OM::_0F, 0xF5),
2313
+ AvxOpcode::Vpmaddubsw => (LP::_66, OM::_0F38, 0x04),
2314
+ AvxOpcode::Vpshufb => (LP::_66, OM::_0F38, 0x00),
2315
+ AvxOpcode::Vpsllw => (LP::_66, OM::_0F, 0xF1),
2316
+ AvxOpcode::Vpslld => (LP::_66, OM::_0F, 0xF2),
2317
+ AvxOpcode::Vpsllq => (LP::_66, OM::_0F, 0xF3),
2318
+ AvxOpcode::Vpsraw => (LP::_66, OM::_0F, 0xE1),
2319
+ AvxOpcode::Vpsrad => (LP::_66, OM::_0F, 0xE2),
2320
+ AvxOpcode::Vaddss => (LP::_F3, OM::_0F, 0x58),
2321
+ AvxOpcode::Vaddsd => (LP::_F2, OM::_0F, 0x58),
2322
+ AvxOpcode::Vmulss => (LP::_F3, OM::_0F, 0x59),
2323
+ AvxOpcode::Vmulsd => (LP::_F2, OM::_0F, 0x59),
2324
+ AvxOpcode::Vsubss => (LP::_F3, OM::_0F, 0x5C),
2325
+ AvxOpcode::Vsubsd => (LP::_F2, OM::_0F, 0x5C),
2326
+ AvxOpcode::Vdivss => (LP::_F3, OM::_0F, 0x5E),
2327
+ AvxOpcode::Vdivsd => (LP::_F2, OM::_0F, 0x5E),
2328
+ AvxOpcode::Vminss => (LP::_F3, OM::_0F, 0x5D),
2329
+ AvxOpcode::Vminsd => (LP::_F2, OM::_0F, 0x5D),
2330
+ AvxOpcode::Vmaxss => (LP::_F3, OM::_0F, 0x5F),
2331
+ AvxOpcode::Vmaxsd => (LP::_F2, OM::_0F, 0x5F),
2332
+ AvxOpcode::Vphaddw => (LP::_66, OM::_0F38, 0x01),
2333
+ AvxOpcode::Vphaddd => (LP::_66, OM::_0F38, 0x02),
2334
+ AvxOpcode::Vpunpckldq => (LP::_66, OM::_0F, 0x62),
2335
+ AvxOpcode::Vpunpckhdq => (LP::_66, OM::_0F, 0x6A),
2336
+ AvxOpcode::Vpunpcklqdq => (LP::_66, OM::_0F, 0x6C),
2337
+ AvxOpcode::Vpunpckhqdq => (LP::_66, OM::_0F, 0x6D),
2338
+ AvxOpcode::Vmovsd => (LP::_F2, OM::_0F, 0x10),
2339
+ AvxOpcode::Vmovss => (LP::_F3, OM::_0F, 0x10),
2340
+ _ => panic!("unexpected rmir vex opcode {op:?}"),
2341
+ };
2342
+ VexInstruction::new()
2343
+ .length(VexVectorLength::V128)
2344
+ .prefix(prefix)
2345
+ .map(map)
2346
+ .opcode(opcode)
2347
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2348
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2349
+ .rm(src2)
2350
+ .encode(sink);
2351
+ }
2352
+
2353
+ Inst::XmmRmRImmVex {
2354
+ op,
2355
+ src1,
2356
+ src2,
2357
+ dst,
2358
+ imm,
2359
+ } => {
2360
+ let dst = allocs.next(dst.to_reg().to_reg());
2361
+ let src1 = allocs.next(src1.to_reg());
2362
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2363
+ RegMem::Reg { reg } => {
2364
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2365
+ }
2366
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2367
+ };
2368
+
2369
+ let (w, prefix, map, opcode) = match op {
2370
+ AvxOpcode::Vcmpps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC2),
2371
+ AvxOpcode::Vcmppd => (false, LegacyPrefixes::_66, OpcodeMap::_0F, 0xC2),
2372
+ AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
2373
+ AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
2374
+ AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
2375
+ AvxOpcode::Vpblendw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0E),
2376
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2377
+ };
2378
+
2379
+ VexInstruction::new()
2380
+ .length(VexVectorLength::V128)
2381
+ .prefix(prefix)
2382
+ .map(map)
2383
+ .w(w)
2384
+ .opcode(opcode)
2385
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2386
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2387
+ .rm(src2)
2388
+ .imm(*imm)
2389
+ .encode(sink);
2390
+ }
2391
+
2392
+ Inst::XmmVexPinsr {
2393
+ op,
2394
+ src1,
2395
+ src2,
2396
+ dst,
2397
+ imm,
2398
+ } => {
2399
+ let dst = allocs.next(dst.to_reg().to_reg());
2400
+ let src1 = allocs.next(src1.to_reg());
2401
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2402
+ RegMem::Reg { reg } => {
2403
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2404
+ }
2405
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2406
+ };
2407
+
2408
+ let (w, map, opcode) = match op {
2409
+ AvxOpcode::Vpinsrb => (false, OpcodeMap::_0F3A, 0x20),
2410
+ AvxOpcode::Vpinsrw => (false, OpcodeMap::_0F, 0xC4),
2411
+ AvxOpcode::Vpinsrd => (false, OpcodeMap::_0F3A, 0x22),
2412
+ AvxOpcode::Vpinsrq => (true, OpcodeMap::_0F3A, 0x22),
2413
+ _ => panic!("unexpected vex_pinsr opcode {op:?}"),
2414
+ };
2415
+
2416
+ VexInstruction::new()
2417
+ .length(VexVectorLength::V128)
2418
+ .prefix(LegacyPrefixes::_66)
2419
+ .map(map)
2420
+ .w(w)
2421
+ .opcode(opcode)
2422
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2423
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2424
+ .rm(src2)
2425
+ .imm(*imm)
2426
+ .encode(sink);
2427
+ }
2428
+
2429
+ Inst::XmmRmRVex3 {
2430
+ op,
2431
+ src1,
2432
+ src2,
2433
+ src3,
2434
+ dst,
2435
+ } => {
2436
+ let src1 = allocs.next(src1.to_reg());
2437
+ let dst = allocs.next(dst.to_reg().to_reg());
2438
+ debug_assert_eq!(src1, dst);
2439
+ let src2 = allocs.next(src2.to_reg());
2440
+ let src3 = match src3.clone().to_reg_mem().with_allocs(allocs) {
2441
+ RegMem::Reg { reg } => {
2442
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2443
+ }
2444
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2445
+ };
2446
+
2447
+ let (w, map, opcode) = match op {
2448
+ AvxOpcode::Vfmadd132ss => (false, OpcodeMap::_0F38, 0x99),
2449
+ AvxOpcode::Vfmadd213ss => (false, OpcodeMap::_0F38, 0xA9),
2450
+ AvxOpcode::Vfnmadd132ss => (false, OpcodeMap::_0F38, 0x9D),
2451
+ AvxOpcode::Vfnmadd213ss => (false, OpcodeMap::_0F38, 0xAD),
2452
+ AvxOpcode::Vfmadd132sd => (true, OpcodeMap::_0F38, 0x99),
2453
+ AvxOpcode::Vfmadd213sd => (true, OpcodeMap::_0F38, 0xA9),
2454
+ AvxOpcode::Vfnmadd132sd => (true, OpcodeMap::_0F38, 0x9D),
2455
+ AvxOpcode::Vfnmadd213sd => (true, OpcodeMap::_0F38, 0xAD),
2456
+ AvxOpcode::Vfmadd132ps => (false, OpcodeMap::_0F38, 0x98),
2457
+ AvxOpcode::Vfmadd213ps => (false, OpcodeMap::_0F38, 0xA8),
2458
+ AvxOpcode::Vfnmadd132ps => (false, OpcodeMap::_0F38, 0x9C),
2459
+ AvxOpcode::Vfnmadd213ps => (false, OpcodeMap::_0F38, 0xAC),
2460
+ AvxOpcode::Vfmadd132pd => (true, OpcodeMap::_0F38, 0x98),
2461
+ AvxOpcode::Vfmadd213pd => (true, OpcodeMap::_0F38, 0xA8),
2462
+ AvxOpcode::Vfnmadd132pd => (true, OpcodeMap::_0F38, 0x9C),
2463
+ AvxOpcode::Vfnmadd213pd => (true, OpcodeMap::_0F38, 0xAC),
2464
+ AvxOpcode::Vblendvps => (false, OpcodeMap::_0F3A, 0x4A),
2465
+ AvxOpcode::Vblendvpd => (false, OpcodeMap::_0F3A, 0x4B),
2466
+ AvxOpcode::Vpblendvb => (false, OpcodeMap::_0F3A, 0x4C),
2467
+ _ => unreachable!(),
2468
+ };
2469
+
2470
+ VexInstruction::new()
2471
+ .length(VexVectorLength::V128)
2472
+ .prefix(LegacyPrefixes::_66)
2473
+ .map(map)
2474
+ .w(w)
2475
+ .opcode(opcode)
2476
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2477
+ .rm(src3)
2478
+ .vvvv(src2.to_real_reg().unwrap().hw_enc())
2479
+ .encode(sink);
2480
+ }
2481
+
2482
+ Inst::XmmRmRBlendVex {
2483
+ op,
2484
+ src1,
2485
+ src2,
2486
+ mask,
2487
+ dst,
2488
+ } => {
2489
+ let dst = allocs.next(dst.to_reg().to_reg());
2490
+ let src1 = allocs.next(src1.to_reg());
2491
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2492
+ RegMem::Reg { reg } => {
2493
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2494
+ }
2495
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2496
+ };
2497
+ let mask = allocs.next(mask.to_reg());
2498
+
2499
+ let opcode = match op {
2500
+ AvxOpcode::Vblendvps => 0x4A,
2501
+ AvxOpcode::Vblendvpd => 0x4B,
2502
+ AvxOpcode::Vpblendvb => 0x4C,
2503
+ _ => unreachable!(),
2504
+ };
2505
+
2506
+ VexInstruction::new()
2507
+ .length(VexVectorLength::V128)
2508
+ .prefix(LegacyPrefixes::_66)
2509
+ .map(OpcodeMap::_0F3A)
2510
+ .opcode(opcode)
2511
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2512
+ .vvvv(src1.to_real_reg().unwrap().hw_enc())
2513
+ .rm(src2)
2514
+ .imm(mask.to_real_reg().unwrap().hw_enc() << 4)
2515
+ .encode(sink);
2516
+ }
2517
+
2518
+ Inst::XmmUnaryRmRVex { op, src, dst } => {
2519
+ let dst = allocs.next(dst.to_reg().to_reg());
2520
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2521
+ RegMem::Reg { reg } => {
2522
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2523
+ }
2524
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2525
+ };
2526
+
2527
+ let (prefix, map, opcode) = match op {
2528
+ AvxOpcode::Vpmovsxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x20),
2529
+ AvxOpcode::Vpmovzxbw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x30),
2530
+ AvxOpcode::Vpmovsxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x23),
2531
+ AvxOpcode::Vpmovzxwd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x33),
2532
+ AvxOpcode::Vpmovsxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x25),
2533
+ AvxOpcode::Vpmovzxdq => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x35),
2534
+ AvxOpcode::Vpabsb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1C),
2535
+ AvxOpcode::Vpabsw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1D),
2536
+ AvxOpcode::Vpabsd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x1E),
2537
+ AvxOpcode::Vsqrtps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x51),
2538
+ AvxOpcode::Vsqrtpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x51),
2539
+ AvxOpcode::Vcvtdq2pd => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0xE6),
2540
+ AvxOpcode::Vcvtdq2ps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5B),
2541
+ AvxOpcode::Vcvtpd2ps => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x5A),
2542
+ AvxOpcode::Vcvtps2pd => (LegacyPrefixes::None, OpcodeMap::_0F, 0x5A),
2543
+ AvxOpcode::Vcvttpd2dq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xE6),
2544
+ AvxOpcode::Vcvttps2dq => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x5B),
2545
+ AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x6F),
2546
+ AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x10),
2547
+ AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x10),
2548
+
2549
+ // Note that for `vmov{s,d}` the `inst.isle` rules should
2550
+ // statically ensure that only `Amode` operands are used here.
2551
+ // Otherwise the other encodings of `vmovss` are more like
2552
+ // 2-operand instructions which this unary encoding does not
2553
+ // have.
2554
+ AvxOpcode::Vmovss => match &src {
2555
+ RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x10),
2556
+ _ => unreachable!(),
2557
+ },
2558
+ AvxOpcode::Vmovsd => match &src {
2559
+ RegisterOrAmode::Amode(_) => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x10),
2560
+ _ => unreachable!(),
2561
+ },
2562
+
2563
+ AvxOpcode::Vpbroadcastb => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x78),
2564
+ AvxOpcode::Vpbroadcastw => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x79),
2565
+ AvxOpcode::Vpbroadcastd => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x58),
2566
+ AvxOpcode::Vbroadcastss => (LegacyPrefixes::_66, OpcodeMap::_0F38, 0x18),
2567
+ AvxOpcode::Vmovddup => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x12),
2568
+
2569
+ AvxOpcode::Vcvtss2sd => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x5A),
2570
+ AvxOpcode::Vcvtsd2ss => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x5A),
2571
+ AvxOpcode::Vsqrtss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x51),
2572
+ AvxOpcode::Vsqrtsd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x51),
2573
+
2574
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2575
+ };
2576
+
2577
+ let vex = VexInstruction::new()
2578
+ .length(VexVectorLength::V128)
2579
+ .prefix(prefix)
2580
+ .map(map)
2581
+ .opcode(opcode)
2582
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2583
+ .rm(src);
2584
+
2585
+ // These opcodes take a second operand through `vvvv` which copies
2586
+ // the upper bits into the destination register. That's not
2587
+ // reflected in the CLIF instruction, however, since the SSE version
2588
+ // doesn't have this functionality. Instead just copy whatever
2589
+ // happens to already be in the destination, which at least is what
2590
+ // LLVM seems to do.
2591
+ let vex = match op {
2592
+ AvxOpcode::Vcvtss2sd
2593
+ | AvxOpcode::Vcvtsd2ss
2594
+ | AvxOpcode::Vsqrtss
2595
+ | AvxOpcode::Vsqrtsd => vex.vvvv(dst.to_real_reg().unwrap().hw_enc()),
2596
+ _ => vex,
2597
+ };
2598
+ vex.encode(sink);
2599
+ }
2600
+
2601
+ Inst::XmmUnaryRmRImmVex { op, src, dst, imm } => {
2602
+ let dst = allocs.next(dst.to_reg().to_reg());
2603
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2604
+ RegMem::Reg { reg } => {
2605
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2606
+ }
2607
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2608
+ };
2609
+
2610
+ let (prefix, map, opcode) = match op {
2611
+ AvxOpcode::Vroundps => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x08),
2612
+ AvxOpcode::Vroundpd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x09),
2613
+ AvxOpcode::Vpshuflw => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x70),
2614
+ AvxOpcode::Vpshufhw => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x70),
2615
+ AvxOpcode::Vpshufd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x70),
2616
+ AvxOpcode::Vroundss => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0A),
2617
+ AvxOpcode::Vroundsd => (LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0B),
2618
+ _ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
2619
+ };
2620
+
2621
+ let vex = VexInstruction::new()
2622
+ .length(VexVectorLength::V128)
2623
+ .prefix(prefix)
2624
+ .map(map)
2625
+ .opcode(opcode)
2626
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2627
+ .rm(src)
2628
+ .imm(*imm);
2629
+
2630
+ // See comments in similar block above in `XmmUnaryRmRVex` for what
2631
+ // this is doing.
2632
+ let vex = match op {
2633
+ AvxOpcode::Vroundss | AvxOpcode::Vroundsd => {
2634
+ vex.vvvv(dst.to_real_reg().unwrap().hw_enc())
2635
+ }
2636
+ _ => vex,
2637
+ };
2638
+ vex.encode(sink);
2639
+ }
2640
+
2641
+ Inst::XmmMovRMVex { op, src, dst } => {
2642
+ let src = allocs.next(src.to_reg());
2643
+ let dst = dst.with_allocs(allocs).finalize(state, sink);
2644
+
2645
+ let (prefix, map, opcode) = match op {
2646
+ AvxOpcode::Vmovdqu => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x7F),
2647
+ AvxOpcode::Vmovss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x11),
2648
+ AvxOpcode::Vmovsd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x11),
2649
+ AvxOpcode::Vmovups => (LegacyPrefixes::None, OpcodeMap::_0F, 0x11),
2650
+ AvxOpcode::Vmovupd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x11),
2651
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2652
+ };
2653
+ VexInstruction::new()
2654
+ .length(VexVectorLength::V128)
2655
+ .prefix(prefix)
2656
+ .map(map)
2657
+ .opcode(opcode)
2658
+ .rm(dst)
2659
+ .reg(src.to_real_reg().unwrap().hw_enc())
2660
+ .encode(sink);
2661
+ }
2662
+
2663
+ Inst::XmmMovRMImmVex { op, src, dst, imm } => {
2664
+ let src = allocs.next(src.to_reg());
2665
+ let dst = dst.with_allocs(allocs).finalize(state, sink);
2666
+
2667
+ let (w, prefix, map, opcode) = match op {
2668
+ AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2669
+ AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2670
+ AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2671
+ AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2672
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2673
+ };
2674
+ VexInstruction::new()
2675
+ .length(VexVectorLength::V128)
2676
+ .w(w)
2677
+ .prefix(prefix)
2678
+ .map(map)
2679
+ .opcode(opcode)
2680
+ .rm(dst)
2681
+ .reg(src.to_real_reg().unwrap().hw_enc())
2682
+ .imm(*imm)
2683
+ .encode(sink);
2684
+ }
2685
+
2686
+ Inst::XmmToGprImmVex { op, src, dst, imm } => {
2687
+ let src = allocs.next(src.to_reg());
2688
+ let dst = allocs.next(dst.to_reg().to_reg());
2689
+
2690
+ let (w, prefix, map, opcode) = match op {
2691
+ AvxOpcode::Vpextrb => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x14),
2692
+ AvxOpcode::Vpextrw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x15),
2693
+ AvxOpcode::Vpextrd => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2694
+ AvxOpcode::Vpextrq => (true, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x16),
2695
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2696
+ };
2697
+ VexInstruction::new()
2698
+ .length(VexVectorLength::V128)
2699
+ .w(w)
2700
+ .prefix(prefix)
2701
+ .map(map)
2702
+ .opcode(opcode)
2703
+ .rm(dst.to_real_reg().unwrap().hw_enc())
2704
+ .reg(src.to_real_reg().unwrap().hw_enc())
2705
+ .imm(*imm)
2706
+ .encode(sink);
2707
+ }
2708
+
2709
+ Inst::XmmToGprVex {
2710
+ op,
2711
+ src,
2712
+ dst,
2713
+ dst_size,
2714
+ } => {
2715
+ let src = allocs.next(src.to_reg());
2716
+ let dst = allocs.next(dst.to_reg().to_reg());
2717
+
2718
+ let (prefix, map, opcode) = match op {
2719
+ // vmovd/vmovq are differentiated by `w`
2720
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x7E),
2721
+ AvxOpcode::Vmovmskps => (LegacyPrefixes::None, OpcodeMap::_0F, 0x50),
2722
+ AvxOpcode::Vmovmskpd => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x50),
2723
+ AvxOpcode::Vpmovmskb => (LegacyPrefixes::_66, OpcodeMap::_0F, 0xD7),
2724
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2725
+ };
2726
+ let w = match dst_size {
2727
+ OperandSize::Size64 => true,
2728
+ _ => false,
2729
+ };
2730
+ let mut vex = VexInstruction::new()
2731
+ .length(VexVectorLength::V128)
2732
+ .w(w)
2733
+ .prefix(prefix)
2734
+ .map(map)
2735
+ .opcode(opcode);
2736
+ vex = match op {
2737
+ // The `vmovq/vmovd` reverse the order of the destination/source
2738
+ // relative to other opcodes using this shape of instruction.
2739
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => vex
2740
+ .rm(dst.to_real_reg().unwrap().hw_enc())
2741
+ .reg(src.to_real_reg().unwrap().hw_enc()),
2742
+ _ => vex
2743
+ .rm(src.to_real_reg().unwrap().hw_enc())
2744
+ .reg(dst.to_real_reg().unwrap().hw_enc()),
2745
+ };
2746
+ vex.encode(sink);
2747
+ }
2748
+
2749
+ Inst::GprToXmmVex {
2750
+ op,
2751
+ src,
2752
+ dst,
2753
+ src_size,
2754
+ } => {
2755
+ let dst = allocs.next(dst.to_reg().to_reg());
2756
+ let src = match src.clone().to_reg_mem().with_allocs(allocs) {
2757
+ RegMem::Reg { reg } => {
2758
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2759
+ }
2760
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2761
+ };
2762
+
2763
+ let (prefix, map, opcode) = match op {
2764
+ // vmovd/vmovq are differentiated by `w`
2765
+ AvxOpcode::Vmovd | AvxOpcode::Vmovq => (LegacyPrefixes::_66, OpcodeMap::_0F, 0x6E),
2766
+ AvxOpcode::Vcvtsi2ss => (LegacyPrefixes::_F3, OpcodeMap::_0F, 0x2A),
2767
+ AvxOpcode::Vcvtsi2sd => (LegacyPrefixes::_F2, OpcodeMap::_0F, 0x2A),
2768
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2769
+ };
2770
+ let w = match src_size {
2771
+ OperandSize::Size64 => true,
2772
+ _ => false,
2773
+ };
2774
+ let mut insn = VexInstruction::new()
2775
+ .length(VexVectorLength::V128)
2776
+ .w(w)
2777
+ .prefix(prefix)
2778
+ .map(map)
2779
+ .opcode(opcode)
2780
+ .rm(src)
2781
+ .reg(dst.to_real_reg().unwrap().hw_enc());
2782
+ // These opcodes technically take a second operand which is the
2783
+ // upper bits to preserve during the float conversion. We don't
2784
+ // actually use this in this backend right now so reuse the
2785
+ // destination register. This at least matches what LLVM does.
2786
+ if let AvxOpcode::Vcvtsi2ss | AvxOpcode::Vcvtsi2sd = op {
2787
+ insn = insn.vvvv(dst.to_real_reg().unwrap().hw_enc());
2788
+ }
2789
+ insn.encode(sink);
2790
+ }
2791
+
2792
+ Inst::XmmRmREvex {
2793
+ op,
2794
+ src1,
2795
+ src2,
2796
+ dst,
2797
+ }
2798
+ | Inst::XmmRmREvex3 {
2799
+ op,
2800
+ src1: _, // `dst` reuses `src1`.
2801
+ src2: src1,
2802
+ src3: src2,
2803
+ dst,
2804
+ } => {
2805
+ let reused_src = match inst {
2806
+ Inst::XmmRmREvex3 { src1, .. } => Some(allocs.next(src1.to_reg())),
2807
+ _ => None,
2808
+ };
2809
+ let src1 = allocs.next(src1.to_reg());
2810
+ let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
2811
+ RegMem::Reg { reg } => {
2812
+ RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
2813
+ }
2814
+ RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
2815
+ };
2816
+ let dst = allocs.next(dst.to_reg().to_reg());
2817
+ if let Some(src1) = reused_src {
2818
+ debug_assert_eq!(src1, dst);
2819
+ }
2820
+
2821
+ let (w, opcode, map) = match op {
2822
+ Avx512Opcode::Vpermi2b => (false, 0x75, OpcodeMap::_0F38),
2823
+ Avx512Opcode::Vpmullq => (true, 0x40, OpcodeMap::_0F38),
2824
+ Avx512Opcode::Vpsraq => (true, 0xE2, OpcodeMap::_0F),
2825
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2826
+ };
2827
+ EvexInstruction::new()
2828
+ .length(EvexVectorLength::V128)
2829
+ .prefix(LegacyPrefixes::_66)
2830
+ .map(map)
2831
+ .w(w)
2832
+ .opcode(opcode)
2833
+ .tuple_type(op.tuple_type())
2834
+ .reg(dst.to_real_reg().unwrap().hw_enc())
2835
+ .vvvvv(src1.to_real_reg().unwrap().hw_enc())
2836
+ .rm(src2)
2837
+ .encode(sink);
2838
+ }
2839
+
2840
+ Inst::XmmMinMaxSeq {
2841
+ size,
2842
+ is_min,
2843
+ lhs,
2844
+ rhs,
2845
+ dst,
2846
+ } => {
2847
+ let rhs = allocs.next(rhs.to_reg());
2848
+ let lhs = allocs.next(lhs.to_reg());
2849
+ let dst = allocs.next(dst.to_reg().to_reg());
2850
+ debug_assert_eq!(rhs, dst);
2851
+
2852
+ // Generates the following sequence:
2853
+ // cmpss/cmpsd %lhs, %rhs_dst
2854
+ // jnz do_min_max
2855
+ // jp propagate_nan
2856
+ //
2857
+ // ;; ordered and equal: propagate the sign bit (for -0 vs 0):
2858
+ // {and,or}{ss,sd} %lhs, %rhs_dst
2859
+ // j done
2860
+ //
2861
+ // ;; to get the desired NaN behavior (signalling NaN transformed into a quiet NaN, the
2862
+ // ;; NaN value is returned), we add both inputs.
2863
+ // propagate_nan:
2864
+ // add{ss,sd} %lhs, %rhs_dst
2865
+ // j done
2866
+ //
2867
+ // do_min_max:
2868
+ // {min,max}{ss,sd} %lhs, %rhs_dst
2869
+ //
2870
+ // done:
2871
+ let done = sink.get_label();
2872
+ let propagate_nan = sink.get_label();
2873
+ let do_min_max = sink.get_label();
2874
+
2875
+ let (add_op, cmp_op, and_op, or_op, min_max_op) = match size {
2876
+ OperandSize::Size32 => (
2877
+ SseOpcode::Addss,
2878
+ SseOpcode::Ucomiss,
2879
+ SseOpcode::Andps,
2880
+ SseOpcode::Orps,
2881
+ if *is_min {
2882
+ SseOpcode::Minss
2883
+ } else {
2884
+ SseOpcode::Maxss
2885
+ },
2886
+ ),
2887
+ OperandSize::Size64 => (
2888
+ SseOpcode::Addsd,
2889
+ SseOpcode::Ucomisd,
2890
+ SseOpcode::Andpd,
2891
+ SseOpcode::Orpd,
2892
+ if *is_min {
2893
+ SseOpcode::Minsd
2894
+ } else {
2895
+ SseOpcode::Maxsd
2896
+ },
2897
+ ),
2898
+ _ => unreachable!(),
2899
+ };
2900
+
2901
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(lhs), dst);
2902
+ inst.emit(&[], sink, info, state);
2903
+
2904
+ one_way_jmp(sink, CC::NZ, do_min_max);
2905
+ one_way_jmp(sink, CC::P, propagate_nan);
2906
+
2907
+ // Ordered and equal. The operands are bit-identical unless they are zero
2908
+ // and negative zero. These instructions merge the sign bits in that
2909
+ // case, and are no-ops otherwise.
2910
+ let op = if *is_min { or_op } else { and_op };
2911
+ let inst = Inst::xmm_rm_r(op, RegMem::reg(lhs), Writable::from_reg(dst));
2912
+ inst.emit(&[], sink, info, state);
2913
+
2914
+ let inst = Inst::jmp_known(done);
2915
+ inst.emit(&[], sink, info, state);
2916
+
2917
+ // x86's min/max are not symmetric; if either operand is a NaN, they return the
2918
+ // read-only operand: perform an addition between the two operands, which has the
2919
+ // desired NaN propagation effects.
2920
+ sink.bind_label(propagate_nan, &mut state.ctrl_plane);
2921
+ let inst = Inst::xmm_rm_r(add_op, RegMem::reg(lhs), Writable::from_reg(dst));
2922
+ inst.emit(&[], sink, info, state);
2923
+
2924
+ one_way_jmp(sink, CC::P, done);
2925
+
2926
+ sink.bind_label(do_min_max, &mut state.ctrl_plane);
2927
+
2928
+ let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(lhs), Writable::from_reg(dst));
2929
+ inst.emit(&[], sink, info, state);
2930
+
2931
+ sink.bind_label(done, &mut state.ctrl_plane);
2932
+ }
2933
+
2934
+ Inst::XmmRmRImm {
2935
+ op,
2936
+ src1,
2937
+ src2,
2938
+ dst,
2939
+ imm,
2940
+ size,
2941
+ } => {
2942
+ let src1 = allocs.next(*src1);
2943
+ let dst = allocs.next(dst.to_reg());
2944
+ let src2 = src2.with_allocs(allocs);
2945
+ debug_assert_eq!(src1, dst);
2946
+
2947
+ let (prefix, opcode, len) = match op {
2948
+ SseOpcode::Cmpps => (LegacyPrefixes::None, 0x0FC2, 2),
2949
+ SseOpcode::Cmppd => (LegacyPrefixes::_66, 0x0FC2, 2),
2950
+ SseOpcode::Cmpss => (LegacyPrefixes::_F3, 0x0FC2, 2),
2951
+ SseOpcode::Cmpsd => (LegacyPrefixes::_F2, 0x0FC2, 2),
2952
+ SseOpcode::Insertps => (LegacyPrefixes::_66, 0x0F3A21, 3),
2953
+ SseOpcode::Palignr => (LegacyPrefixes::_66, 0x0F3A0F, 3),
2954
+ SseOpcode::Pinsrb => (LegacyPrefixes::_66, 0x0F3A20, 3),
2955
+ SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
2956
+ SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
2957
+ SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
2958
+ SseOpcode::Pblendw => (LegacyPrefixes::_66, 0x0F3A0E, 3),
2959
+ _ => unimplemented!("Opcode {:?} not implemented", op),
2960
+ };
2961
+ let rex = RexFlags::from(*size);
2962
+ let regs_swapped = match *op {
2963
+ // These opcodes (and not the SSE2 version of PEXTRW) flip the operand
2964
+ // encoding: `dst` in ModRM's r/m, `src` in ModRM's reg field.
2965
+ SseOpcode::Pextrb | SseOpcode::Pextrd => true,
2966
+ // The rest of the opcodes have the customary encoding: `dst` in ModRM's reg,
2967
+ // `src` in ModRM's r/m field.
2968
+ _ => false,
2969
+ };
2970
+ match src2 {
2971
+ RegMem::Reg { reg } => {
2972
+ if regs_swapped {
2973
+ emit_std_reg_reg(sink, prefix, opcode, len, reg, dst, rex);
2974
+ } else {
2975
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
2976
+ }
2977
+ }
2978
+ RegMem::Mem { addr } => {
2979
+ let addr = &addr.finalize(state, sink);
2980
+ assert!(
2981
+ !regs_swapped,
2982
+ "No existing way to encode a mem argument in the ModRM r/m field."
2983
+ );
2984
+ // N.B.: bytes_at_end == 1, because of the `imm` byte below.
2985
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 1);
2986
+ }
2987
+ }
2988
+ sink.put1(*imm);
2989
+ }
2990
+
2991
+ Inst::XmmUninitializedValue { .. } => {
2992
+ // This instruction format only exists to declare a register as a `def`; no code is
2993
+ // emitted.
2994
+ }
2995
+
2996
+ Inst::XmmMovRM { op, src, dst } => {
2997
+ let src = allocs.next(src.to_reg());
2998
+ let dst = dst.with_allocs(allocs);
2999
+
3000
+ let (prefix, opcode) = match op {
3001
+ SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F29),
3002
+ SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F29),
3003
+ SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F7F),
3004
+ SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F11),
3005
+ SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F11),
3006
+ SseOpcode::Movups => (LegacyPrefixes::None, 0x0F11),
3007
+ SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F11),
3008
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3009
+ };
3010
+ let dst = &dst.finalize(state, sink);
3011
+ emit_std_reg_mem(sink, prefix, opcode, 2, src, dst, RexFlags::clear_w(), 0);
3012
+ }
3013
+
3014
+ Inst::XmmMovRMImm { op, src, dst, imm } => {
3015
+ let src = allocs.next(src.to_reg());
3016
+ let dst = dst.with_allocs(allocs);
3017
+
3018
+ let (w, prefix, opcode) = match op {
3019
+ SseOpcode::Pextrb => (false, LegacyPrefixes::_66, 0x0F3A14),
3020
+ SseOpcode::Pextrw => (false, LegacyPrefixes::_66, 0x0F3A15),
3021
+ SseOpcode::Pextrd => (false, LegacyPrefixes::_66, 0x0F3A16),
3022
+ SseOpcode::Pextrq => (true, LegacyPrefixes::_66, 0x0F3A16),
3023
+ _ => unimplemented!("Opcode {:?} not implemented", op),
3024
+ };
3025
+ let rex = if w {
3026
+ RexFlags::set_w()
3027
+ } else {
3028
+ RexFlags::clear_w()
3029
+ };
3030
+ let dst = &dst.finalize(state, sink);
3031
+ emit_std_reg_mem(sink, prefix, opcode, 3, src, dst, rex, 1);
3032
+ sink.put1(*imm);
3033
+ }
3034
+
3035
+ Inst::XmmToGpr {
3036
+ op,
3037
+ src,
3038
+ dst,
3039
+ dst_size,
3040
+ } => {
3041
+ let src = allocs.next(src.to_reg());
3042
+ let dst = allocs.next(dst.to_reg().to_reg());
3043
+
3044
+ let (prefix, opcode, dst_first) = match op {
3045
+ SseOpcode::Cvttss2si => (LegacyPrefixes::_F3, 0x0F2C, true),
3046
+ SseOpcode::Cvttsd2si => (LegacyPrefixes::_F2, 0x0F2C, true),
3047
+ // Movd and movq use the same opcode; the presence of the REX prefix (set below)
3048
+ // actually determines which is used.
3049
+ SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F7E, false),
3050
+ SseOpcode::Movmskps => (LegacyPrefixes::None, 0x0F50, true),
3051
+ SseOpcode::Movmskpd => (LegacyPrefixes::_66, 0x0F50, true),
3052
+ SseOpcode::Pmovmskb => (LegacyPrefixes::_66, 0x0FD7, true),
3053
+ _ => panic!("unexpected opcode {:?}", op),
3054
+ };
3055
+ let rex = RexFlags::from(*dst_size);
3056
+ let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
3057
+
3058
+ emit_std_reg_reg(sink, prefix, opcode, 2, src, dst, rex);
3059
+ }
3060
+
3061
+ Inst::XmmToGprImm { op, src, dst, imm } => {
3062
+ use OperandSize as OS;
3063
+
3064
+ let src = allocs.next(src.to_reg());
3065
+ let dst = allocs.next(dst.to_reg().to_reg());
3066
+
3067
+ let (prefix, opcode, opcode_bytes, dst_size, dst_first) = match op {
3068
+ SseOpcode::Pextrb => (LegacyPrefixes::_66, 0x0F3A14, 3, OS::Size32, false),
3069
+ SseOpcode::Pextrw => (LegacyPrefixes::_66, 0x0FC5, 2, OS::Size32, true),
3070
+ SseOpcode::Pextrd => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size32, false),
3071
+ SseOpcode::Pextrq => (LegacyPrefixes::_66, 0x0F3A16, 3, OS::Size64, false),
3072
+ _ => panic!("unexpected opcode {:?}", op),
3073
+ };
3074
+ let rex = RexFlags::from(dst_size);
3075
+ let (src, dst) = if dst_first { (dst, src) } else { (src, dst) };
3076
+
3077
+ emit_std_reg_reg(sink, prefix, opcode, opcode_bytes, src, dst, rex);
3078
+ sink.put1(*imm);
3079
+ }
3080
+
3081
+ Inst::GprToXmm {
3082
+ op,
3083
+ src: src_e,
3084
+ dst: reg_g,
3085
+ src_size,
3086
+ } => {
3087
+ let reg_g = allocs.next(reg_g.to_reg().to_reg());
3088
+ let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
3089
+
3090
+ let (prefix, opcode) = match op {
3091
+ // Movd and movq use the same opcode; the presence of the REX prefix (set below)
3092
+ // actually determines which is used.
3093
+ SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F6E),
3094
+ SseOpcode::Cvtsi2ss => (LegacyPrefixes::_F3, 0x0F2A),
3095
+ SseOpcode::Cvtsi2sd => (LegacyPrefixes::_F2, 0x0F2A),
3096
+ _ => panic!("unexpected opcode {:?}", op),
3097
+ };
3098
+ let rex = RexFlags::from(*src_size);
3099
+ match src_e {
3100
+ RegMem::Reg { reg: reg_e } => {
3101
+ emit_std_reg_reg(sink, prefix, opcode, 2, reg_g, reg_e, rex);
3102
+ }
3103
+ RegMem::Mem { addr } => {
3104
+ let addr = &addr.finalize(state, sink);
3105
+ emit_std_reg_mem(sink, prefix, opcode, 2, reg_g, addr, rex, 0);
3106
+ }
3107
+ }
3108
+ }
3109
+
3110
+ Inst::XmmCmpRmR { op, src, dst } => {
3111
+ let dst = allocs.next(dst.to_reg());
3112
+ let src = src.clone().to_reg_mem().with_allocs(allocs);
3113
+
3114
+ let rex = RexFlags::clear_w();
3115
+ let (prefix, opcode, len) = match op {
3116
+ SseOpcode::Ptest => (LegacyPrefixes::_66, 0x0F3817, 3),
3117
+ SseOpcode::Ucomisd => (LegacyPrefixes::_66, 0x0F2E, 2),
3118
+ SseOpcode::Ucomiss => (LegacyPrefixes::None, 0x0F2E, 2),
3119
+ _ => unimplemented!("Emit xmm cmp rm r"),
3120
+ };
3121
+
3122
+ match src {
3123
+ RegMem::Reg { reg } => {
3124
+ emit_std_reg_reg(sink, prefix, opcode, len, dst, reg, rex);
3125
+ }
3126
+ RegMem::Mem { addr } => {
3127
+ let addr = &addr.finalize(state, sink);
3128
+ emit_std_reg_mem(sink, prefix, opcode, len, dst, addr, rex, 0);
3129
+ }
3130
+ }
3131
+ }
3132
+
3133
+ Inst::CvtUint64ToFloatSeq {
3134
+ dst_size,
3135
+ src,
3136
+ dst,
3137
+ tmp_gpr1,
3138
+ tmp_gpr2,
3139
+ } => {
3140
+ let src = allocs.next(src.to_reg());
3141
+ let dst = allocs.next(dst.to_reg().to_reg());
3142
+ let tmp_gpr1 = allocs.next(tmp_gpr1.to_reg().to_reg());
3143
+ let tmp_gpr2 = allocs.next(tmp_gpr2.to_reg().to_reg());
3144
+
3145
+ // Note: this sequence is specific to 64-bit mode; a 32-bit mode would require a
3146
+ // different sequence.
3147
+ //
3148
+ // Emit the following sequence:
3149
+ //
3150
+ // cmp 0, %src
3151
+ // jl handle_negative
3152
+ //
3153
+ // ;; handle positive, which can't overflow
3154
+ // cvtsi2sd/cvtsi2ss %src, %dst
3155
+ // j done
3156
+ //
3157
+ // ;; handle negative: see below for an explanation of what it's doing.
3158
+ // handle_negative:
3159
+ // mov %src, %tmp_gpr1
3160
+ // shr $1, %tmp_gpr1
3161
+ // mov %src, %tmp_gpr2
3162
+ // and $1, %tmp_gpr2
3163
+ // or %tmp_gpr1, %tmp_gpr2
3164
+ // cvtsi2sd/cvtsi2ss %tmp_gpr2, %dst
3165
+ // addsd/addss %dst, %dst
3166
+ //
3167
+ // done:
3168
+
3169
+ assert_ne!(src, tmp_gpr1);
3170
+ assert_ne!(src, tmp_gpr2);
3171
+ assert_ne!(tmp_gpr1, tmp_gpr2);
3172
+
3173
+ let handle_negative = sink.get_label();
3174
+ let done = sink.get_label();
3175
+
3176
+ // If x seen as a signed int64 is not negative, a signed-conversion will do the right
3177
+ // thing.
3178
+ // TODO use tst src, src here.
3179
+ let inst = Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(0), src);
3180
+ inst.emit(&[], sink, info, state);
3181
+
3182
+ one_way_jmp(sink, CC::L, handle_negative);
3183
+
3184
+ // Handle a positive int64, which is the "easy" case: a signed conversion will do the
3185
+ // right thing.
3186
+ emit_signed_cvt(
3187
+ sink,
3188
+ info,
3189
+ state,
3190
+ src,
3191
+ Writable::from_reg(dst),
3192
+ *dst_size == OperandSize::Size64,
3193
+ );
3194
+
3195
+ let inst = Inst::jmp_known(done);
3196
+ inst.emit(&[], sink, info, state);
3197
+
3198
+ sink.bind_label(handle_negative, &mut state.ctrl_plane);
3199
+
3200
+ // Divide x by two to get it in range for the signed conversion, keep the LSB, and
3201
+ // scale it back up on the FP side.
3202
+ let inst = Inst::gen_move(Writable::from_reg(tmp_gpr1), src, types::I64);
3203
+ inst.emit(&[], sink, info, state);
3204
+
3205
+ // tmp_gpr1 := src >> 1
3206
+ let inst = Inst::shift_r(
3207
+ OperandSize::Size64,
3208
+ ShiftKind::ShiftRightLogical,
3209
+ Imm8Gpr::new(Imm8Reg::Imm8 { imm: 1 }).unwrap(),
3210
+ tmp_gpr1,
3211
+ Writable::from_reg(tmp_gpr1),
3212
+ );
3213
+ inst.emit(&[], sink, info, state);
3214
+
3215
+ let inst = Inst::gen_move(Writable::from_reg(tmp_gpr2), src, types::I64);
3216
+ inst.emit(&[], sink, info, state);
3217
+
3218
+ let inst = Inst::alu_rmi_r(
3219
+ OperandSize::Size64,
3220
+ AluRmiROpcode::And,
3221
+ RegMemImm::imm(1),
3222
+ Writable::from_reg(tmp_gpr2),
3223
+ );
3224
+ inst.emit(&[], sink, info, state);
3225
+
3226
+ let inst = Inst::alu_rmi_r(
3227
+ OperandSize::Size64,
3228
+ AluRmiROpcode::Or,
3229
+ RegMemImm::reg(tmp_gpr1),
3230
+ Writable::from_reg(tmp_gpr2),
3231
+ );
3232
+ inst.emit(&[], sink, info, state);
3233
+
3234
+ emit_signed_cvt(
3235
+ sink,
3236
+ info,
3237
+ state,
3238
+ tmp_gpr2,
3239
+ Writable::from_reg(dst),
3240
+ *dst_size == OperandSize::Size64,
3241
+ );
3242
+
3243
+ let add_op = if *dst_size == OperandSize::Size64 {
3244
+ SseOpcode::Addsd
3245
+ } else {
3246
+ SseOpcode::Addss
3247
+ };
3248
+ let inst = Inst::xmm_rm_r(add_op, RegMem::reg(dst), Writable::from_reg(dst));
3249
+ inst.emit(&[], sink, info, state);
3250
+
3251
+ sink.bind_label(done, &mut state.ctrl_plane);
3252
+ }
3253
+
3254
+ Inst::CvtFloatToSintSeq {
3255
+ src_size,
3256
+ dst_size,
3257
+ is_saturating,
3258
+ src,
3259
+ dst,
3260
+ tmp_gpr,
3261
+ tmp_xmm,
3262
+ } => {
3263
+ let src = allocs.next(src.to_reg());
3264
+ let dst = allocs.next(dst.to_reg().to_reg());
3265
+ let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3266
+ let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3267
+
3268
+ // Emits the following common sequence:
3269
+ //
3270
+ // cvttss2si/cvttsd2si %src, %dst
3271
+ // cmp %dst, 1
3272
+ // jno done
3273
+ //
3274
+ // Then, for saturating conversions:
3275
+ //
3276
+ // ;; check for NaN
3277
+ // cmpss/cmpsd %src, %src
3278
+ // jnp not_nan
3279
+ // xor %dst, %dst
3280
+ //
3281
+ // ;; positive inputs get saturated to INT_MAX; negative ones to INT_MIN, which is
3282
+ // ;; already in %dst.
3283
+ // xorpd %tmp_xmm, %tmp_xmm
3284
+ // cmpss/cmpsd %src, %tmp_xmm
3285
+ // jnb done
3286
+ // mov/movaps $INT_MAX, %dst
3287
+ //
3288
+ // done:
3289
+ //
3290
+ // Then, for non-saturating conversions:
3291
+ //
3292
+ // ;; check for NaN
3293
+ // cmpss/cmpsd %src, %src
3294
+ // jnp not_nan
3295
+ // ud2 trap BadConversionToInteger
3296
+ //
3297
+ // ;; check if INT_MIN was the correct result, against a magic constant:
3298
+ // not_nan:
3299
+ // movaps/mov $magic, %tmp_gpr
3300
+ // movq/movd %tmp_gpr, %tmp_xmm
3301
+ // cmpss/cmpsd %tmp_xmm, %src
3302
+ // jnb/jnbe $check_positive
3303
+ // ud2 trap IntegerOverflow
3304
+ //
3305
+ // ;; if positive, it was a real overflow
3306
+ // check_positive:
3307
+ // xorpd %tmp_xmm, %tmp_xmm
3308
+ // cmpss/cmpsd %src, %tmp_xmm
3309
+ // jnb done
3310
+ // ud2 trap IntegerOverflow
3311
+ //
3312
+ // done:
3313
+
3314
+ let (cast_op, cmp_op, trunc_op) = match src_size {
3315
+ OperandSize::Size64 => (SseOpcode::Movq, SseOpcode::Ucomisd, SseOpcode::Cvttsd2si),
3316
+ OperandSize::Size32 => (SseOpcode::Movd, SseOpcode::Ucomiss, SseOpcode::Cvttss2si),
3317
+ _ => unreachable!(),
3318
+ };
3319
+
3320
+ let done = sink.get_label();
3321
+
3322
+ // The truncation.
3323
+ let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3324
+ inst.emit(&[], sink, info, state);
3325
+
3326
+ // Compare against 1, in case of overflow the dst operand was INT_MIN.
3327
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(1), dst);
3328
+ inst.emit(&[], sink, info, state);
3329
+
3330
+ one_way_jmp(sink, CC::NO, done); // no overflow => done
3331
+
3332
+ // Check for NaN.
3333
+
3334
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), src);
3335
+ inst.emit(&[], sink, info, state);
3336
+
3337
+ if *is_saturating {
3338
+ let not_nan = sink.get_label();
3339
+ one_way_jmp(sink, CC::NP, not_nan); // go to not_nan if not a NaN
3340
+
3341
+ // For NaN, emit 0.
3342
+ let inst = Inst::alu_rmi_r(
3343
+ *dst_size,
3344
+ AluRmiROpcode::Xor,
3345
+ RegMemImm::reg(dst),
3346
+ Writable::from_reg(dst),
3347
+ );
3348
+ inst.emit(&[], sink, info, state);
3349
+
3350
+ let inst = Inst::jmp_known(done);
3351
+ inst.emit(&[], sink, info, state);
3352
+
3353
+ sink.bind_label(not_nan, &mut state.ctrl_plane);
3354
+
3355
+ // If the input was positive, saturate to INT_MAX.
3356
+
3357
+ // Zero out tmp_xmm.
3358
+ let inst = Inst::xmm_rm_r(
3359
+ SseOpcode::Xorpd,
3360
+ RegMem::reg(tmp_xmm),
3361
+ Writable::from_reg(tmp_xmm),
3362
+ );
3363
+ inst.emit(&[], sink, info, state);
3364
+
3365
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3366
+ inst.emit(&[], sink, info, state);
3367
+
3368
+ // Jump if >= to done.
3369
+ one_way_jmp(sink, CC::NB, done);
3370
+
3371
+ // Otherwise, put INT_MAX.
3372
+ if *dst_size == OperandSize::Size64 {
3373
+ let inst = Inst::imm(
3374
+ OperandSize::Size64,
3375
+ 0x7fffffffffffffff,
3376
+ Writable::from_reg(dst),
3377
+ );
3378
+ inst.emit(&[], sink, info, state);
3379
+ } else {
3380
+ let inst = Inst::imm(OperandSize::Size32, 0x7fffffff, Writable::from_reg(dst));
3381
+ inst.emit(&[], sink, info, state);
3382
+ }
3383
+ } else {
3384
+ let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3385
+ inst.emit(&[], sink, info, state);
3386
+
3387
+ // Check if INT_MIN was the correct result: determine the smallest floating point
3388
+ // number that would convert to INT_MIN, put it in a temporary register, and compare
3389
+ // against the src register.
3390
+ // If the src register is less (or in some cases, less-or-equal) than the threshold,
3391
+ // trap!
3392
+
3393
+ let mut no_overflow_cc = CC::NB; // >=
3394
+ let output_bits = dst_size.to_bits();
3395
+ match *src_size {
3396
+ OperandSize::Size32 => {
3397
+ let cst = Ieee32::pow2(output_bits - 1).neg().bits();
3398
+ let inst =
3399
+ Inst::imm(OperandSize::Size32, cst as u64, Writable::from_reg(tmp_gpr));
3400
+ inst.emit(&[], sink, info, state);
3401
+ }
3402
+ OperandSize::Size64 => {
3403
+ // An f64 can represent `i32::min_value() - 1` exactly with precision to spare,
3404
+ // so there are values less than -2^(N-1) that convert correctly to INT_MIN.
3405
+ let cst = if output_bits < 64 {
3406
+ no_overflow_cc = CC::NBE; // >
3407
+ Ieee64::fcvt_to_sint_negative_overflow(output_bits)
3408
+ } else {
3409
+ Ieee64::pow2(output_bits - 1).neg()
3410
+ };
3411
+ let inst =
3412
+ Inst::imm(OperandSize::Size64, cst.bits(), Writable::from_reg(tmp_gpr));
3413
+ inst.emit(&[], sink, info, state);
3414
+ }
3415
+ _ => unreachable!(),
3416
+ }
3417
+
3418
+ let inst = Inst::gpr_to_xmm(
3419
+ cast_op,
3420
+ RegMem::reg(tmp_gpr),
3421
+ *src_size,
3422
+ Writable::from_reg(tmp_xmm),
3423
+ );
3424
+ inst.emit(&[], sink, info, state);
3425
+
3426
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3427
+ inst.emit(&[], sink, info, state);
3428
+
3429
+ // no trap if src >= or > threshold
3430
+ let inst = Inst::trap_if(no_overflow_cc.invert(), TrapCode::IntegerOverflow);
3431
+ inst.emit(&[], sink, info, state);
3432
+
3433
+ // If positive, it was a real overflow.
3434
+
3435
+ // Zero out the tmp_xmm register.
3436
+ let inst = Inst::xmm_rm_r(
3437
+ SseOpcode::Xorpd,
3438
+ RegMem::reg(tmp_xmm),
3439
+ Writable::from_reg(tmp_xmm),
3440
+ );
3441
+ inst.emit(&[], sink, info, state);
3442
+
3443
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src), tmp_xmm);
3444
+ inst.emit(&[], sink, info, state);
3445
+
3446
+ // no trap if 0 >= src
3447
+ let inst = Inst::trap_if(CC::B, TrapCode::IntegerOverflow);
3448
+ inst.emit(&[], sink, info, state);
3449
+ }
3450
+
3451
+ sink.bind_label(done, &mut state.ctrl_plane);
3452
+ }
3453
+
3454
+ Inst::CvtFloatToUintSeq {
3455
+ src_size,
3456
+ dst_size,
3457
+ is_saturating,
3458
+ src,
3459
+ dst,
3460
+ tmp_gpr,
3461
+ tmp_xmm,
3462
+ tmp_xmm2,
3463
+ } => {
3464
+ let src = allocs.next(src.to_reg());
3465
+ let dst = allocs.next(dst.to_reg().to_reg());
3466
+ let tmp_gpr = allocs.next(tmp_gpr.to_reg().to_reg());
3467
+ let tmp_xmm = allocs.next(tmp_xmm.to_reg().to_reg());
3468
+ let tmp_xmm2 = allocs.next(tmp_xmm2.to_reg().to_reg());
3469
+
3470
+ // The only difference in behavior between saturating and non-saturating is how we
3471
+ // handle errors. Emits the following sequence:
3472
+ //
3473
+ // movaps/mov 2**(int_width - 1), %tmp_gpr
3474
+ // movq/movd %tmp_gpr, %tmp_xmm
3475
+ // cmpss/cmpsd %tmp_xmm, %src
3476
+ // jnb is_large
3477
+ //
3478
+ // ;; check for NaN inputs
3479
+ // jnp not_nan
3480
+ // -- non-saturating: ud2 trap BadConversionToInteger
3481
+ // -- saturating: xor %dst, %dst; j done
3482
+ //
3483
+ // not_nan:
3484
+ // cvttss2si/cvttsd2si %src, %dst
3485
+ // cmp 0, %dst
3486
+ // jnl done
3487
+ // -- non-saturating: ud2 trap IntegerOverflow
3488
+ // -- saturating: xor %dst, %dst; j done
3489
+ //
3490
+ // is_large:
3491
+ // mov %src, %tmp_xmm2
3492
+ // subss/subsd %tmp_xmm, %tmp_xmm2
3493
+ // cvttss2si/cvttss2sd %tmp_x, %dst
3494
+ // cmp 0, %dst
3495
+ // jnl next_is_large
3496
+ // -- non-saturating: ud2 trap IntegerOverflow
3497
+ // -- saturating: movaps $UINT_MAX, %dst; j done
3498
+ //
3499
+ // next_is_large:
3500
+ // add 2**(int_width -1), %dst ;; 2 instructions for 64-bits integers
3501
+ //
3502
+ // done:
3503
+
3504
+ assert_ne!(tmp_xmm, src, "tmp_xmm clobbers src!");
3505
+
3506
+ let (sub_op, cast_op, cmp_op, trunc_op) = match src_size {
3507
+ OperandSize::Size32 => (
3508
+ SseOpcode::Subss,
3509
+ SseOpcode::Movd,
3510
+ SseOpcode::Ucomiss,
3511
+ SseOpcode::Cvttss2si,
3512
+ ),
3513
+ OperandSize::Size64 => (
3514
+ SseOpcode::Subsd,
3515
+ SseOpcode::Movq,
3516
+ SseOpcode::Ucomisd,
3517
+ SseOpcode::Cvttsd2si,
3518
+ ),
3519
+ _ => unreachable!(),
3520
+ };
3521
+
3522
+ let done = sink.get_label();
3523
+
3524
+ let cst = match src_size {
3525
+ OperandSize::Size32 => Ieee32::pow2(dst_size.to_bits() - 1).bits() as u64,
3526
+ OperandSize::Size64 => Ieee64::pow2(dst_size.to_bits() - 1).bits(),
3527
+ _ => unreachable!(),
3528
+ };
3529
+
3530
+ let inst = Inst::imm(*src_size, cst, Writable::from_reg(tmp_gpr));
3531
+ inst.emit(&[], sink, info, state);
3532
+
3533
+ let inst = Inst::gpr_to_xmm(
3534
+ cast_op,
3535
+ RegMem::reg(tmp_gpr),
3536
+ *src_size,
3537
+ Writable::from_reg(tmp_xmm),
3538
+ );
3539
+ inst.emit(&[], sink, info, state);
3540
+
3541
+ let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(tmp_xmm), src);
3542
+ inst.emit(&[], sink, info, state);
3543
+
3544
+ let handle_large = sink.get_label();
3545
+ one_way_jmp(sink, CC::NB, handle_large); // jump to handle_large if src >= large_threshold
3546
+
3547
+ if *is_saturating {
3548
+ // If not NaN jump over this 0-return, otherwise return 0
3549
+ let not_nan = sink.get_label();
3550
+ one_way_jmp(sink, CC::NP, not_nan);
3551
+ let inst = Inst::alu_rmi_r(
3552
+ *dst_size,
3553
+ AluRmiROpcode::Xor,
3554
+ RegMemImm::reg(dst),
3555
+ Writable::from_reg(dst),
3556
+ );
3557
+ inst.emit(&[], sink, info, state);
3558
+
3559
+ let inst = Inst::jmp_known(done);
3560
+ inst.emit(&[], sink, info, state);
3561
+ sink.bind_label(not_nan, &mut state.ctrl_plane);
3562
+ } else {
3563
+ // Trap.
3564
+ let inst = Inst::trap_if(CC::P, TrapCode::BadConversionToInteger);
3565
+ inst.emit(&[], sink, info, state);
3566
+ }
3567
+
3568
+ // Actual truncation for small inputs: if the result is not positive, then we had an
3569
+ // overflow.
3570
+
3571
+ let inst = Inst::xmm_to_gpr(trunc_op, src, Writable::from_reg(dst), *dst_size);
3572
+ inst.emit(&[], sink, info, state);
3573
+
3574
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3575
+ inst.emit(&[], sink, info, state);
3576
+
3577
+ one_way_jmp(sink, CC::NL, done); // if dst >= 0, jump to done
3578
+
3579
+ if *is_saturating {
3580
+ // The input was "small" (< 2**(width -1)), so the only way to get an integer
3581
+ // overflow is because the input was too small: saturate to the min value, i.e. 0.
3582
+ let inst = Inst::alu_rmi_r(
3583
+ *dst_size,
3584
+ AluRmiROpcode::Xor,
3585
+ RegMemImm::reg(dst),
3586
+ Writable::from_reg(dst),
3587
+ );
3588
+ inst.emit(&[], sink, info, state);
3589
+
3590
+ let inst = Inst::jmp_known(done);
3591
+ inst.emit(&[], sink, info, state);
3592
+ } else {
3593
+ // Trap.
3594
+ let inst = Inst::trap(TrapCode::IntegerOverflow);
3595
+ inst.emit(&[], sink, info, state);
3596
+ }
3597
+
3598
+ // Now handle large inputs.
3599
+
3600
+ sink.bind_label(handle_large, &mut state.ctrl_plane);
3601
+
3602
+ let inst = Inst::gen_move(Writable::from_reg(tmp_xmm2), src, types::F64);
3603
+ inst.emit(&[], sink, info, state);
3604
+
3605
+ let inst = Inst::xmm_rm_r(sub_op, RegMem::reg(tmp_xmm), Writable::from_reg(tmp_xmm2));
3606
+ inst.emit(&[], sink, info, state);
3607
+
3608
+ let inst = Inst::xmm_to_gpr(trunc_op, tmp_xmm2, Writable::from_reg(dst), *dst_size);
3609
+ inst.emit(&[], sink, info, state);
3610
+
3611
+ let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst);
3612
+ inst.emit(&[], sink, info, state);
3613
+
3614
+ if *is_saturating {
3615
+ let next_is_large = sink.get_label();
3616
+ one_way_jmp(sink, CC::NL, next_is_large); // if dst >= 0, jump to next_is_large
3617
+
3618
+ // The input was "large" (>= 2**(width -1)), so the only way to get an integer
3619
+ // overflow is because the input was too large: saturate to the max value.
3620
+ let inst = Inst::imm(
3621
+ OperandSize::Size64,
3622
+ if *dst_size == OperandSize::Size64 {
3623
+ u64::max_value()
3624
+ } else {
3625
+ u32::max_value() as u64
3626
+ },
3627
+ Writable::from_reg(dst),
3628
+ );
3629
+ inst.emit(&[], sink, info, state);
3630
+
3631
+ let inst = Inst::jmp_known(done);
3632
+ inst.emit(&[], sink, info, state);
3633
+ sink.bind_label(next_is_large, &mut state.ctrl_plane);
3634
+ } else {
3635
+ let inst = Inst::trap_if(CC::L, TrapCode::IntegerOverflow);
3636
+ inst.emit(&[], sink, info, state);
3637
+ }
3638
+
3639
+ if *dst_size == OperandSize::Size64 {
3640
+ let inst = Inst::imm(OperandSize::Size64, 1 << 63, Writable::from_reg(tmp_gpr));
3641
+ inst.emit(&[], sink, info, state);
3642
+
3643
+ let inst = Inst::alu_rmi_r(
3644
+ OperandSize::Size64,
3645
+ AluRmiROpcode::Add,
3646
+ RegMemImm::reg(tmp_gpr),
3647
+ Writable::from_reg(dst),
3648
+ );
3649
+ inst.emit(&[], sink, info, state);
3650
+ } else {
3651
+ let inst = Inst::alu_rmi_r(
3652
+ OperandSize::Size32,
3653
+ AluRmiROpcode::Add,
3654
+ RegMemImm::imm(1 << 31),
3655
+ Writable::from_reg(dst),
3656
+ );
3657
+ inst.emit(&[], sink, info, state);
3658
+ }
3659
+
3660
+ sink.bind_label(done, &mut state.ctrl_plane);
3661
+ }
3662
+
3663
+ Inst::LoadExtName {
3664
+ dst,
3665
+ name,
3666
+ offset,
3667
+ distance,
3668
+ } => {
3669
+ let dst = allocs.next(dst.to_reg());
3670
+
3671
+ if info.flags.is_pic() {
3672
+ // Generates: movq symbol@GOTPCREL(%rip), %dst
3673
+ let enc_dst = int_reg_enc(dst);
3674
+ sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
3675
+ sink.put1(0x8B);
3676
+ sink.put1(0x05 | ((enc_dst & 7) << 3));
3677
+ emit_reloc(sink, Reloc::X86GOTPCRel4, name, -4);
3678
+ sink.put4(0);
3679
+ // Offset in the relocation above applies to the address of the *GOT entry*, not
3680
+ // the loaded address; so we emit a separate add or sub instruction if needed.
3681
+ if *offset < 0 {
3682
+ assert!(*offset >= -i32::MAX as i64);
3683
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3684
+ sink.put1(0x81);
3685
+ sink.put1(0xe8 | (enc_dst & 7));
3686
+ sink.put4((-*offset) as u32);
3687
+ } else if *offset > 0 {
3688
+ assert!(*offset <= i32::MAX as i64);
3689
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3690
+ sink.put1(0x81);
3691
+ sink.put1(0xc0 | (enc_dst & 7));
3692
+ sink.put4(*offset as u32);
3693
+ }
3694
+ } else if distance == &RelocDistance::Near {
3695
+ // If we know the distance to the name is within 2GB (e.g., a module-local function),
3696
+ // we can generate a RIP-relative address, with a relocation.
3697
+ // Generates: lea $name(%rip), $dst
3698
+ let enc_dst = int_reg_enc(dst);
3699
+ sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
3700
+ sink.put1(0x8D);
3701
+ sink.put1(0x05 | ((enc_dst & 7) << 3));
3702
+ emit_reloc(sink, Reloc::X86CallPCRel4, name, -4);
3703
+ sink.put4(0);
3704
+ } else {
3705
+ // The full address can be encoded in the register, with a relocation.
3706
+ // Generates: movabsq $name, %dst
3707
+ let enc_dst = int_reg_enc(dst);
3708
+ sink.put1(0x48 | ((enc_dst >> 3) & 1));
3709
+ sink.put1(0xB8 | (enc_dst & 7));
3710
+ emit_reloc(sink, Reloc::Abs8, name, *offset);
3711
+ sink.put8(0);
3712
+ }
3713
+ }
3714
+
3715
+ Inst::LockCmpxchg {
3716
+ ty,
3717
+ replacement,
3718
+ expected,
3719
+ mem,
3720
+ dst_old,
3721
+ } => {
3722
+ let replacement = allocs.next(*replacement);
3723
+ let expected = allocs.next(*expected);
3724
+ let dst_old = allocs.next(dst_old.to_reg());
3725
+ let mem = mem.with_allocs(allocs);
3726
+
3727
+ debug_assert_eq!(expected, regs::rax());
3728
+ debug_assert_eq!(dst_old, regs::rax());
3729
+
3730
+ // lock cmpxchg{b,w,l,q} %replacement, (mem)
3731
+ // Note that 0xF0 is the Lock prefix.
3732
+ let (prefix, opcodes) = match *ty {
3733
+ types::I8 => (LegacyPrefixes::_F0, 0x0FB0),
3734
+ types::I16 => (LegacyPrefixes::_66F0, 0x0FB1),
3735
+ types::I32 => (LegacyPrefixes::_F0, 0x0FB1),
3736
+ types::I64 => (LegacyPrefixes::_F0, 0x0FB1),
3737
+ _ => unreachable!(),
3738
+ };
3739
+ let rex = RexFlags::from((OperandSize::from_ty(*ty), replacement));
3740
+ let amode = mem.finalize(state, sink);
3741
+ emit_std_reg_mem(sink, prefix, opcodes, 2, replacement, &amode, rex, 0);
3742
+ }
3743
+
3744
+ Inst::AtomicRmwSeq {
3745
+ ty,
3746
+ op,
3747
+ mem,
3748
+ operand,
3749
+ temp,
3750
+ dst_old,
3751
+ } => {
3752
+ let operand = allocs.next(*operand);
3753
+ let temp = allocs.next_writable(*temp);
3754
+ let dst_old = allocs.next_writable(*dst_old);
3755
+ debug_assert_eq!(dst_old.to_reg(), regs::rax());
3756
+ let mem = mem.finalize(state, sink).with_allocs(allocs);
3757
+
3758
+ // Emit this:
3759
+ // mov{zbq,zwq,zlq,q} (%r_address), %rax // rax = old value
3760
+ // again:
3761
+ // movq %rax, %r_temp // rax = old value, r_temp = old value
3762
+ // `op`q %r_operand, %r_temp // rax = old value, r_temp = new value
3763
+ // lock cmpxchg{b,w,l,q} %r_temp, (%r_address) // try to store new value
3764
+ // jnz again // If this is taken, rax will have a "revised" old value
3765
+ //
3766
+ // Operand conventions: IN: %r_address, %r_operand OUT: %rax (old
3767
+ // value), %r_temp (trashed), %rflags (trashed)
3768
+ //
3769
+ // In the case where the operation is 'xchg', the "`op`q"
3770
+ // instruction is instead: movq %r_operand,
3771
+ // %r_temp so that we simply write in the destination, the "2nd
3772
+ // arg for `op`".
3773
+ //
3774
+ // TODO: this sequence can be significantly improved (e.g., to `lock
3775
+ // <op>`) when it is known that `dst_old` is not used later, see
3776
+ // https://github.com/bytecodealliance/wasmtime/issues/2153.
3777
+ let again_label = sink.get_label();
3778
+
3779
+ // mov{zbq,zwq,zlq,q} (%r_address), %rax
3780
+ // No need to call `add_trap` here, since the `i1` emit will do that.
3781
+ let i1 = Inst::load(*ty, mem.clone(), dst_old, ExtKind::ZeroExtend);
3782
+ i1.emit(&[], sink, info, state);
3783
+
3784
+ // again:
3785
+ sink.bind_label(again_label, &mut state.ctrl_plane);
3786
+
3787
+ // movq %rax, %r_temp
3788
+ let i2 = Inst::mov_r_r(OperandSize::Size64, dst_old.to_reg(), temp);
3789
+ i2.emit(&[], sink, info, state);
3790
+
3791
+ let operand_rmi = RegMemImm::reg(operand);
3792
+ use inst_common::MachAtomicRmwOp as RmwOp;
3793
+ match op {
3794
+ RmwOp::Xchg => {
3795
+ // movq %r_operand, %r_temp
3796
+ let i3 = Inst::mov_r_r(OperandSize::Size64, operand, temp);
3797
+ i3.emit(&[], sink, info, state);
3798
+ }
3799
+ RmwOp::Nand => {
3800
+ // andq %r_operand, %r_temp
3801
+ let i3 =
3802
+ Inst::alu_rmi_r(OperandSize::Size64, AluRmiROpcode::And, operand_rmi, temp);
3803
+ i3.emit(&[], sink, info, state);
3804
+
3805
+ // notq %r_temp
3806
+ let i4 = Inst::not(OperandSize::Size64, temp);
3807
+ i4.emit(&[], sink, info, state);
3808
+ }
3809
+ RmwOp::Umin | RmwOp::Umax | RmwOp::Smin | RmwOp::Smax => {
3810
+ // cmp %r_temp, %r_operand
3811
+ let i3 = Inst::cmp_rmi_r(
3812
+ OperandSize::from_ty(*ty),
3813
+ RegMemImm::reg(temp.to_reg()),
3814
+ operand,
3815
+ );
3816
+ i3.emit(&[], sink, info, state);
3817
+
3818
+ // cmovcc %r_operand, %r_temp
3819
+ let cc = match op {
3820
+ RmwOp::Umin => CC::BE,
3821
+ RmwOp::Umax => CC::NB,
3822
+ RmwOp::Smin => CC::LE,
3823
+ RmwOp::Smax => CC::NL,
3824
+ _ => unreachable!(),
3825
+ };
3826
+ let i4 = Inst::cmove(OperandSize::Size64, cc, RegMem::reg(operand), temp);
3827
+ i4.emit(&[], sink, info, state);
3828
+ }
3829
+ _ => {
3830
+ // opq %r_operand, %r_temp
3831
+ let alu_op = match op {
3832
+ RmwOp::Add => AluRmiROpcode::Add,
3833
+ RmwOp::Sub => AluRmiROpcode::Sub,
3834
+ RmwOp::And => AluRmiROpcode::And,
3835
+ RmwOp::Or => AluRmiROpcode::Or,
3836
+ RmwOp::Xor => AluRmiROpcode::Xor,
3837
+ RmwOp::Xchg
3838
+ | RmwOp::Nand
3839
+ | RmwOp::Umin
3840
+ | RmwOp::Umax
3841
+ | RmwOp::Smin
3842
+ | RmwOp::Smax => unreachable!(),
3843
+ };
3844
+ let i3 = Inst::alu_rmi_r(OperandSize::Size64, alu_op, operand_rmi, temp);
3845
+ i3.emit(&[], sink, info, state);
3846
+ }
3847
+ }
3848
+
3849
+ // lock cmpxchg{b,w,l,q} %r_temp, (%r_address)
3850
+ // No need to call `add_trap` here, since the `i4` emit will do that.
3851
+ let i4 = Inst::LockCmpxchg {
3852
+ ty: *ty,
3853
+ replacement: temp.to_reg(),
3854
+ expected: dst_old.to_reg(),
3855
+ mem: mem.into(),
3856
+ dst_old,
3857
+ };
3858
+ i4.emit(&[], sink, info, state);
3859
+
3860
+ // jnz again
3861
+ one_way_jmp(sink, CC::NZ, again_label);
3862
+ }
3863
+
3864
+ Inst::Fence { kind } => {
3865
+ sink.put1(0x0F);
3866
+ sink.put1(0xAE);
3867
+ match kind {
3868
+ FenceKind::MFence => sink.put1(0xF0), // mfence = 0F AE F0
3869
+ FenceKind::LFence => sink.put1(0xE8), // lfence = 0F AE E8
3870
+ FenceKind::SFence => sink.put1(0xF8), // sfence = 0F AE F8
3871
+ }
3872
+ }
3873
+
3874
+ Inst::Hlt => {
3875
+ sink.put1(0xcc);
3876
+ }
3877
+
3878
+ Inst::Ud2 { trap_code } => {
3879
+ sink.add_trap(*trap_code);
3880
+ if let Some(s) = state.take_stack_map() {
3881
+ sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
3882
+ }
3883
+ sink.put_data(Inst::TRAP_OPCODE);
3884
+ }
3885
+
3886
+ Inst::VirtualSPOffsetAdj { offset } => {
3887
+ trace!(
3888
+ "virtual sp offset adjusted by {} -> {}",
3889
+ offset,
3890
+ state.virtual_sp_offset + offset
3891
+ );
3892
+ state.virtual_sp_offset += offset;
3893
+ }
3894
+
3895
+ Inst::Nop { len } => {
3896
+ // These encodings can all be found in Intel's architecture manual, at the NOP
3897
+ // instruction description.
3898
+ let mut len = *len;
3899
+ while len != 0 {
3900
+ let emitted = u8::min(len, 9);
3901
+ match emitted {
3902
+ 0 => {}
3903
+ 1 => sink.put1(0x90), // NOP
3904
+ 2 => {
3905
+ // 66 NOP
3906
+ sink.put1(0x66);
3907
+ sink.put1(0x90);
3908
+ }
3909
+ 3 => {
3910
+ // NOP [EAX]
3911
+ sink.put1(0x0F);
3912
+ sink.put1(0x1F);
3913
+ sink.put1(0x00);
3914
+ }
3915
+ 4 => {
3916
+ // NOP 0(EAX), with 0 a 1-byte immediate.
3917
+ sink.put1(0x0F);
3918
+ sink.put1(0x1F);
3919
+ sink.put1(0x40);
3920
+ sink.put1(0x00);
3921
+ }
3922
+ 5 => {
3923
+ // NOP [EAX, EAX, 1]
3924
+ sink.put1(0x0F);
3925
+ sink.put1(0x1F);
3926
+ sink.put1(0x44);
3927
+ sink.put1(0x00);
3928
+ sink.put1(0x00);
3929
+ }
3930
+ 6 => {
3931
+ // 66 NOP [EAX, EAX, 1]
3932
+ sink.put1(0x66);
3933
+ sink.put1(0x0F);
3934
+ sink.put1(0x1F);
3935
+ sink.put1(0x44);
3936
+ sink.put1(0x00);
3937
+ sink.put1(0x00);
3938
+ }
3939
+ 7 => {
3940
+ // NOP 0[EAX], but 0 is a 4 bytes immediate.
3941
+ sink.put1(0x0F);
3942
+ sink.put1(0x1F);
3943
+ sink.put1(0x80);
3944
+ sink.put1(0x00);
3945
+ sink.put1(0x00);
3946
+ sink.put1(0x00);
3947
+ sink.put1(0x00);
3948
+ }
3949
+ 8 => {
3950
+ // NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
3951
+ sink.put1(0x0F);
3952
+ sink.put1(0x1F);
3953
+ sink.put1(0x84);
3954
+ sink.put1(0x00);
3955
+ sink.put1(0x00);
3956
+ sink.put1(0x00);
3957
+ sink.put1(0x00);
3958
+ sink.put1(0x00);
3959
+ }
3960
+ 9 => {
3961
+ // 66 NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
3962
+ sink.put1(0x66);
3963
+ sink.put1(0x0F);
3964
+ sink.put1(0x1F);
3965
+ sink.put1(0x84);
3966
+ sink.put1(0x00);
3967
+ sink.put1(0x00);
3968
+ sink.put1(0x00);
3969
+ sink.put1(0x00);
3970
+ sink.put1(0x00);
3971
+ }
3972
+ _ => unreachable!(),
3973
+ }
3974
+ len -= emitted;
3975
+ }
3976
+ }
3977
+
3978
+ Inst::ElfTlsGetAddr { ref symbol, dst } => {
3979
+ let dst = allocs.next(dst.to_reg().to_reg());
3980
+ debug_assert_eq!(dst, regs::rax());
3981
+
3982
+ // N.B.: Must be exactly this byte sequence; the linker requires it,
3983
+ // because it must know how to rewrite the bytes.
3984
+
3985
+ // data16 lea gv@tlsgd(%rip),%rdi
3986
+ sink.put1(0x66); // data16
3987
+ sink.put1(0b01001000); // REX.W
3988
+ sink.put1(0x8d); // LEA
3989
+ sink.put1(0x3d); // ModRM byte
3990
+ emit_reloc(sink, Reloc::ElfX86_64TlsGd, symbol, -4);
3991
+ sink.put4(0); // offset
3992
+
3993
+ // data16 data16 callq __tls_get_addr-4
3994
+ sink.put1(0x66); // data16
3995
+ sink.put1(0x66); // data16
3996
+ sink.put1(0b01001000); // REX.W
3997
+ sink.put1(0xe8); // CALL
3998
+ emit_reloc(
3999
+ sink,
4000
+ Reloc::X86CallPLTRel4,
4001
+ &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
4002
+ -4,
4003
+ );
4004
+ sink.put4(0); // offset
4005
+ }
4006
+
4007
+ Inst::MachOTlsGetAddr { ref symbol, dst } => {
4008
+ let dst = allocs.next(dst.to_reg().to_reg());
4009
+ debug_assert_eq!(dst, regs::rax());
4010
+
4011
+ // movq gv@tlv(%rip), %rdi
4012
+ sink.put1(0x48); // REX.w
4013
+ sink.put1(0x8b); // MOV
4014
+ sink.put1(0x3d); // ModRM byte
4015
+ emit_reloc(sink, Reloc::MachOX86_64Tlv, symbol, -4);
4016
+ sink.put4(0); // offset
4017
+
4018
+ // callq *(%rdi)
4019
+ sink.put1(0xff);
4020
+ sink.put1(0x17);
4021
+ }
4022
+
4023
+ Inst::CoffTlsGetAddr {
4024
+ ref symbol,
4025
+ dst,
4026
+ tmp,
4027
+ } => {
4028
+ let dst = allocs.next(dst.to_reg().to_reg());
4029
+ debug_assert_eq!(dst, regs::rax());
4030
+
4031
+ // tmp is used below directly as %rcx
4032
+ let tmp = allocs.next(tmp.to_reg().to_reg());
4033
+ debug_assert_eq!(tmp, regs::rcx());
4034
+
4035
+ // See: https://gcc.godbolt.org/z/M8or9x6ss
4036
+ // And: https://github.com/bjorn3/rustc_codegen_cranelift/issues/388#issuecomment-532930282
4037
+
4038
+ // Emit the following sequence
4039
+ // movl (%rip), %eax ; IMAGE_REL_AMD64_REL32 _tls_index
4040
+ // movq %gs:88, %rcx
4041
+ // movq (%rcx,%rax,8), %rax
4042
+ // leaq (%rax), %rax ; Reloc: IMAGE_REL_AMD64_SECREL symbol
4043
+
4044
+ // Load TLS index for current thread
4045
+ // movl (%rip), %eax
4046
+ sink.put1(0x8b); // mov
4047
+ sink.put1(0x05);
4048
+ emit_reloc(
4049
+ sink,
4050
+ Reloc::X86PCRel4,
4051
+ &ExternalName::KnownSymbol(KnownSymbol::CoffTlsIndex),
4052
+ -4,
4053
+ );
4054
+ sink.put4(0); // offset
4055
+
4056
+ // movq %gs:88, %rcx
4057
+ // Load the TLS Storage Array pointer
4058
+ // The gs segment register refers to the base address of the TEB on x64.
4059
+ // 0x58 is the offset in the TEB for the ThreadLocalStoragePointer member on x64:
4060
+ sink.put_data(&[
4061
+ 0x65, 0x48, // REX.W
4062
+ 0x8b, // MOV
4063
+ 0x0c, 0x25, 0x58, // 0x58 - ThreadLocalStoragePointer offset
4064
+ 0x00, 0x00, 0x00,
4065
+ ]);
4066
+
4067
+ // movq (%rcx,%rax,8), %rax
4068
+ // Load the actual TLS entry for this thread.
4069
+ // Computes ThreadLocalStoragePointer + _tls_index*8
4070
+ sink.put_data(&[0x48, 0x8b, 0x04, 0xc1]);
4071
+
4072
+ // leaq (%rax), %rax
4073
+ sink.put1(0x48);
4074
+ sink.put1(0x8d);
4075
+ sink.put1(0x80);
4076
+ emit_reloc(sink, Reloc::X86SecRel, symbol, 0);
4077
+ sink.put4(0); // offset
4078
+ }
4079
+
4080
+ Inst::Unwind { ref inst } => {
4081
+ sink.add_unwind(inst.clone());
4082
+ }
4083
+
4084
+ Inst::DummyUse { .. } => {
4085
+ // Nothing.
4086
+ }
4087
+ }
4088
+
4089
+ state.clear_post_insn();
4090
+ }