wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,3991 @@
1
+ ;; s390x instruction selection and CLIF-to-MachInst lowering.
2
+
3
+ ;; The main lowering constructor term: takes a clif `Inst` and returns the
4
+ ;; register(s) within which the lowered instruction's result values live.
5
+ (decl partial lower (Inst) InstOutput)
6
+
7
+ ;; A variant of the main lowering constructor term, used for branches.
8
+ ;; The only difference is that it gets an extra argument holding a vector
9
+ ;; of branch targets to be used.
10
+ (decl partial lower_branch (Inst VecMachLabel) Unit)
11
+
12
+
13
+ ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
+
15
+ (rule (lower (has_type ty (iconst (u64_from_imm64 n))))
16
+ (imm ty n))
17
+
18
+
19
+ ;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
20
+
21
+ (rule (lower (f32const (u32_from_ieee32 x)))
22
+ (imm $F32 x))
23
+
24
+
25
+ ;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
26
+
27
+ (rule (lower (f64const (u64_from_ieee64 x)))
28
+ (imm $F64 x))
29
+
30
+
31
+ ;;;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
32
+
33
+ (rule (lower (has_type ty (vconst (u128_from_constant x))))
34
+ (vec_imm ty (be_vec_const ty x)))
35
+
36
+
37
+ ;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38
+
39
+ (rule (lower (has_type ty (null)))
40
+ (imm ty 0))
41
+
42
+
43
+ ;;;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
44
+
45
+ (rule (lower (nop))
46
+ (invalid_reg))
47
+
48
+
49
+ ;;;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
50
+
51
+ (rule (lower (has_type (vr128_ty ty) (iconcat x y)))
52
+ (mov_to_vec128 ty y x))
53
+
54
+
55
+ ;;;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
56
+
57
+ (rule (lower (isplit x @ (value_type $I128)))
58
+ (let ((x_reg Reg x)
59
+ (x_hi Reg (vec_extract_lane $I64X2 x_reg 0 (zero_reg)))
60
+ (x_lo Reg (vec_extract_lane $I64X2 x_reg 1 (zero_reg))))
61
+ (output_pair x_lo x_hi)))
62
+
63
+
64
+ ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
65
+
66
+ ;; Add two registers.
67
+ (rule 0 (lower (has_type (fits_in_64 ty) (iadd x y)))
68
+ (add_reg ty x y))
69
+
70
+ ;; Add a register and a sign-extended register.
71
+ (rule 8 (lower (has_type (fits_in_64 ty) (iadd x (sext32_value y))))
72
+ (add_reg_sext32 ty x y))
73
+ (rule 15 (lower (has_type (fits_in_64 ty) (iadd (sext32_value x) y)))
74
+ (add_reg_sext32 ty y x))
75
+
76
+ ;; Add a register and an immediate.
77
+ (rule 7 (lower (has_type (fits_in_64 ty) (iadd x (i16_from_value y))))
78
+ (add_simm16 ty x y))
79
+ (rule 14 (lower (has_type (fits_in_64 ty) (iadd (i16_from_value x) y)))
80
+ (add_simm16 ty y x))
81
+ (rule 6 (lower (has_type (fits_in_64 ty) (iadd x (i32_from_value y))))
82
+ (add_simm32 ty x y))
83
+ (rule 13 (lower (has_type (fits_in_64 ty) (iadd (i32_from_value x) y)))
84
+ (add_simm32 ty y x))
85
+
86
+ ;; Add a register and memory (32/64-bit types).
87
+ (rule 5 (lower (has_type (fits_in_64 ty) (iadd x (sinkable_load_32_64 y))))
88
+ (add_mem ty x (sink_load y)))
89
+ (rule 12 (lower (has_type (fits_in_64 ty) (iadd (sinkable_load_32_64 x) y)))
90
+ (add_mem ty y (sink_load x)))
91
+
92
+ ;; Add a register and memory (16-bit types).
93
+ (rule 4 (lower (has_type (fits_in_64 ty) (iadd x (sinkable_load_16 y))))
94
+ (add_mem_sext16 ty x (sink_load y)))
95
+ (rule 11 (lower (has_type (fits_in_64 ty) (iadd (sinkable_load_16 x) y)))
96
+ (add_mem_sext16 ty y (sink_load x)))
97
+
98
+ ;; Add a register and sign-extended memory.
99
+ (rule 3 (lower (has_type (fits_in_64 ty) (iadd x (sinkable_sload16 y))))
100
+ (add_mem_sext16 ty x (sink_sload16 y)))
101
+ (rule 10 (lower (has_type (fits_in_64 ty) (iadd (sinkable_sload16 x) y)))
102
+ (add_mem_sext16 ty y (sink_sload16 x)))
103
+ (rule 2 (lower (has_type (fits_in_64 ty) (iadd x (sinkable_sload32 y))))
104
+ (add_mem_sext32 ty x (sink_sload32 y)))
105
+ (rule 9 (lower (has_type (fits_in_64 ty) (iadd (sinkable_sload32 x) y)))
106
+ (add_mem_sext32 ty y (sink_sload32 x)))
107
+
108
+ ;; Add two vector registers.
109
+ (rule 1 (lower (has_type (vr128_ty ty) (iadd x y)))
110
+ (vec_add ty x y))
111
+
112
+
113
+ ;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
114
+
115
+ ;; Add (saturate unsigned) two vector registers.
116
+ (rule (lower (has_type (ty_vec128 ty) (uadd_sat x y)))
117
+ (let ((sum Reg (vec_add ty x y)))
118
+ (vec_or ty sum (vec_cmphl ty x sum))))
119
+
120
+
121
+ ;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
122
+
123
+ ;; Add (saturate signed) two vector registers. $I64X2 not supported.
124
+ (rule (lower (has_type (ty_vec128 ty) (sadd_sat x y)))
125
+ (vec_pack_ssat (vec_widen_type ty)
126
+ (vec_add (vec_widen_type ty) (vec_unpacks_high ty x)
127
+ (vec_unpacks_high ty y))
128
+ (vec_add (vec_widen_type ty) (vec_unpacks_low ty x)
129
+ (vec_unpacks_low ty y))))
130
+
131
+
132
+ ;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
133
+
134
+ ;; Lane-wise integer pairwise addition for 8-/16/32-bit vector registers.
135
+ (rule (lower (has_type ty @ (multi_lane bits _) (iadd_pairwise x y)))
136
+ (let ((size Reg (vec_imm_splat $I8X16 (u32_as_u64 bits))))
137
+ (vec_pack_lane_order (vec_widen_type ty)
138
+ (vec_add ty x (vec_lshr_by_byte x size))
139
+ (vec_add ty y (vec_lshr_by_byte y size)))))
140
+
141
+ ;; special case for the `i32x4.dot_i16x8_s` wasm instruction
142
+ (rule 1 (lower
143
+ (has_type dst_ty (iadd_pairwise
144
+ (imul (swiden_low x @ (value_type src_ty)) (swiden_low y))
145
+ (imul (swiden_high x) (swiden_high y)))))
146
+ (vec_add dst_ty (vec_smul_even src_ty x y)
147
+ (vec_smul_odd src_ty x y)))
148
+
149
+
150
+ ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
151
+
152
+ ;; Sub two registers.
153
+ (rule 0 (lower (has_type (fits_in_64 ty) (isub x y)))
154
+ (sub_reg ty x y))
155
+
156
+ ;; Sub a register and a sign-extended register.
157
+ (rule 8 (lower (has_type (fits_in_64 ty) (isub x (sext32_value y))))
158
+ (sub_reg_sext32 ty x y))
159
+
160
+ ;; Sub a register and an immediate (using add of the negated value).
161
+ (rule 7 (lower (has_type (fits_in_64 ty) (isub x (i16_from_negated_value y))))
162
+ (add_simm16 ty x y))
163
+ (rule 6 (lower (has_type (fits_in_64 ty) (isub x (i32_from_negated_value y))))
164
+ (add_simm32 ty x y))
165
+
166
+ ;; Sub a register and memory (32/64-bit types).
167
+ (rule 5 (lower (has_type (fits_in_64 ty) (isub x (sinkable_load_32_64 y))))
168
+ (sub_mem ty x (sink_load y)))
169
+
170
+ ;; Sub a register and memory (16-bit types).
171
+ (rule 4 (lower (has_type (fits_in_64 ty) (isub x (sinkable_load_16 y))))
172
+ (sub_mem_sext16 ty x (sink_load y)))
173
+
174
+ ;; Sub a register and sign-extended memory.
175
+ (rule 3 (lower (has_type (fits_in_64 ty) (isub x (sinkable_sload16 y))))
176
+ (sub_mem_sext16 ty x (sink_sload16 y)))
177
+ (rule 2 (lower (has_type (fits_in_64 ty) (isub x (sinkable_sload32 y))))
178
+ (sub_mem_sext32 ty x (sink_sload32 y)))
179
+
180
+ ;; Sub two vector registers.
181
+ (rule 1 (lower (has_type (vr128_ty ty) (isub x y)))
182
+ (vec_sub ty x y))
183
+
184
+
185
+ ;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
186
+
187
+ ;; Add (saturate unsigned) two vector registers.
188
+ (rule (lower (has_type (ty_vec128 ty) (usub_sat x y)))
189
+ (vec_and ty (vec_sub ty x y) (vec_cmphl ty x y)))
190
+
191
+
192
+ ;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
193
+
194
+ ;; Add (saturate signed) two vector registers. $I64X2 not supported.
195
+ (rule (lower (has_type (ty_vec128 ty) (ssub_sat x y)))
196
+ (vec_pack_ssat (vec_widen_type ty)
197
+ (vec_sub (vec_widen_type ty) (vec_unpacks_high ty x)
198
+ (vec_unpacks_high ty y))
199
+ (vec_sub (vec_widen_type ty) (vec_unpacks_low ty x)
200
+ (vec_unpacks_low ty y))))
201
+
202
+
203
+ ;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
204
+
205
+ ;; Absolute value of a register.
206
+ ;; For types smaller than 32-bit, the input value must be sign-extended.
207
+ (rule 2 (lower (has_type (fits_in_64 ty) (iabs x)))
208
+ (abs_reg (ty_ext32 ty) (put_in_reg_sext32 x)))
209
+
210
+ ;; Absolute value of a sign-extended register.
211
+ (rule 3 (lower (has_type (fits_in_64 ty) (iabs (sext32_value x))))
212
+ (abs_reg_sext32 ty x))
213
+
214
+ ;; Absolute value of a vector register.
215
+ (rule 1 (lower (has_type (ty_vec128 ty) (iabs x)))
216
+ (vec_abs ty x))
217
+
218
+ ;; Absolute value of a 128-bit integer.
219
+ (rule 0 (lower (has_type $I128 (iabs x)))
220
+ (let ((zero Reg (vec_imm $I128 0))
221
+ (pos Reg x)
222
+ (neg Reg (vec_sub $I128 zero pos))
223
+ (rep Reg (vec_replicate_lane $I64X2 pos 0))
224
+ (mask Reg (vec_cmph $I64X2 zero rep)))
225
+ (vec_select $I128 neg pos mask)))
226
+
227
+
228
+ ;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
229
+
230
+ ;; Negate a register.
231
+ (rule 2 (lower (has_type (fits_in_64 ty) (ineg x)))
232
+ (neg_reg ty x))
233
+
234
+ ;; Negate a sign-extended register.
235
+ (rule 3 (lower (has_type (fits_in_64 ty) (ineg (sext32_value x))))
236
+ (neg_reg_sext32 ty x))
237
+
238
+ ;; Negate a vector register.
239
+ (rule 1 (lower (has_type (ty_vec128 ty) (ineg x)))
240
+ (vec_neg ty x))
241
+
242
+ ;; Negate a 128-bit integer.
243
+ (rule 0 (lower (has_type $I128 (ineg x)))
244
+ (vec_sub $I128 (vec_imm $I128 0) x))
245
+
246
+
247
+ ;;;; Rules for `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
248
+
249
+ ;; Unsigned maximum of two scalar integers - expand to icmp + select.
250
+ (rule 2 (lower (has_type (fits_in_64 ty) (umax x y)))
251
+ (let ((x_ext Reg (put_in_reg_zext32 x))
252
+ (y_ext Reg (put_in_reg_zext32 y))
253
+ (cond ProducesBool (bool (icmpu_reg (ty_ext32 ty) x_ext y_ext)
254
+ (intcc_as_cond (IntCC.UnsignedLessThan)))))
255
+ (select_bool_reg ty cond y_ext x_ext)))
256
+
257
+ ;; Unsigned maximum of two 128-bit integers - expand to icmp + select.
258
+ (rule 1 (lower (has_type $I128 (umax x y)))
259
+ (let ((x_reg Reg (put_in_reg x))
260
+ (y_reg Reg (put_in_reg y))
261
+ (cond ProducesBool (vec_int128_ucmphi y_reg x_reg)))
262
+ (select_bool_reg $I128 cond y_reg x_reg)))
263
+
264
+ ;; Unsigned maximum of two vector registers.
265
+ (rule 0 (lower (has_type (ty_vec128 ty) (umax x y)))
266
+ (vec_umax ty x y))
267
+
268
+
269
+ ;;;; Rules for `umin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
270
+
271
+ ;; Unsigned minimum of two scalar integers - expand to icmp + select.
272
+ (rule 2 (lower (has_type (fits_in_64 ty) (umin x y)))
273
+ (let ((x_ext Reg (put_in_reg_zext32 x))
274
+ (y_ext Reg (put_in_reg_zext32 y))
275
+ (cond ProducesBool (bool (icmpu_reg (ty_ext32 ty) x_ext y_ext)
276
+ (intcc_as_cond (IntCC.UnsignedGreaterThan)))))
277
+ (select_bool_reg ty cond y_ext x_ext)))
278
+
279
+ ;; Unsigned maximum of two 128-bit integers - expand to icmp + select.
280
+ (rule 1 (lower (has_type $I128 (umin x y)))
281
+ (let ((x_reg Reg (put_in_reg x))
282
+ (y_reg Reg (put_in_reg y))
283
+ (cond ProducesBool (vec_int128_ucmphi x_reg y_reg)))
284
+ (select_bool_reg $I128 cond y_reg x_reg)))
285
+
286
+ ;; Unsigned minimum of two vector registers.
287
+ (rule 0 (lower (has_type (ty_vec128 ty) (umin x y)))
288
+ (vec_umin ty x y))
289
+
290
+
291
+ ;;;; Rules for `smax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
292
+
293
+ ;; Signed maximum of two scalar integers - expand to icmp + select.
294
+ (rule 2 (lower (has_type (fits_in_64 ty) (smax x y)))
295
+ (let ((x_ext Reg (put_in_reg_sext32 x))
296
+ (y_ext Reg (put_in_reg_sext32 y))
297
+ (cond ProducesBool (bool (icmps_reg (ty_ext32 ty) x_ext y_ext)
298
+ (intcc_as_cond (IntCC.SignedLessThan)))))
299
+ (select_bool_reg ty cond y_ext x_ext)))
300
+
301
+ ;; Signed maximum of two 128-bit integers - expand to icmp + select.
302
+ (rule 1 (lower (has_type $I128 (smax x y)))
303
+ (let ((x_reg Reg (put_in_reg x))
304
+ (y_reg Reg (put_in_reg y))
305
+ (cond ProducesBool (vec_int128_scmphi y_reg x_reg)))
306
+ (select_bool_reg $I128 cond y_reg x_reg)))
307
+
308
+ ;; Signed maximum of two vector registers.
309
+ (rule (lower (has_type (ty_vec128 ty) (smax x y)))
310
+ (vec_smax ty x y))
311
+
312
+
313
+ ;;;; Rules for `smin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
314
+
315
+ ;; Signed minimum of two scalar integers - expand to icmp + select.
316
+ (rule 2 (lower (has_type (fits_in_64 ty) (smin x y)))
317
+ (let ((x_ext Reg (put_in_reg_sext32 x))
318
+ (y_ext Reg (put_in_reg_sext32 y))
319
+ (cond ProducesBool (bool (icmps_reg (ty_ext32 ty) x_ext y_ext)
320
+ (intcc_as_cond (IntCC.SignedGreaterThan)))))
321
+ (select_bool_reg ty cond y_ext x_ext)))
322
+
323
+ ;; Signed maximum of two 128-bit integers - expand to icmp + select.
324
+ (rule 1 (lower (has_type $I128 (smin x y)))
325
+ (let ((x_reg Reg (put_in_reg x))
326
+ (y_reg Reg (put_in_reg y))
327
+ (cond ProducesBool (vec_int128_scmphi x_reg y_reg)))
328
+ (select_bool_reg $I128 cond y_reg x_reg)))
329
+
330
+ ;; Signed minimum of two vector registers.
331
+ (rule (lower (has_type (ty_vec128 ty) (smin x y)))
332
+ (vec_smin ty x y))
333
+
334
+
335
+ ;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
336
+
337
+ ;; Unsigned average of two vector registers.
338
+ (rule (lower (has_type (ty_vec128 ty) (avg_round x y)))
339
+ (vec_uavg ty x y))
340
+
341
+
342
+ ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
343
+
344
+ ;; Multiply two registers.
345
+ (rule 0 (lower (has_type (fits_in_64 ty) (imul x y)))
346
+ (mul_reg ty x y))
347
+
348
+ ;; Multiply a register and a sign-extended register.
349
+ (rule 8 (lower (has_type (fits_in_64 ty) (imul x (sext32_value y))))
350
+ (mul_reg_sext32 ty x y))
351
+ (rule 15 (lower (has_type (fits_in_64 ty) (imul (sext32_value x) y)))
352
+ (mul_reg_sext32 ty y x))
353
+
354
+ ;; Multiply a register and an immediate.
355
+ (rule 7 (lower (has_type (fits_in_64 ty) (imul x (i16_from_value y))))
356
+ (mul_simm16 ty x y))
357
+ (rule 14 (lower (has_type (fits_in_64 ty) (imul (i16_from_value x) y)))
358
+ (mul_simm16 ty y x))
359
+ (rule 6 (lower (has_type (fits_in_64 ty) (imul x (i32_from_value y))))
360
+ (mul_simm32 ty x y))
361
+ (rule 13 (lower (has_type (fits_in_64 ty) (imul (i32_from_value x) y)))
362
+ (mul_simm32 ty y x))
363
+
364
+ ;; Multiply a register and memory (32/64-bit types).
365
+ (rule 5 (lower (has_type (fits_in_64 ty) (imul x (sinkable_load_32_64 y))))
366
+ (mul_mem ty x (sink_load y)))
367
+ (rule 12 (lower (has_type (fits_in_64 ty) (imul (sinkable_load_32_64 x) y)))
368
+ (mul_mem ty y (sink_load x)))
369
+
370
+ ;; Multiply a register and memory (16-bit types).
371
+ (rule 4 (lower (has_type (fits_in_64 ty) (imul x (sinkable_load_16 y))))
372
+ (mul_mem_sext16 ty x (sink_load y)))
373
+ (rule 11 (lower (has_type (fits_in_64 ty) (imul (sinkable_load_16 x) y)))
374
+ (mul_mem_sext16 ty y (sink_load x)))
375
+
376
+ ;; Multiply a register and sign-extended memory.
377
+ (rule 3 (lower (has_type (fits_in_64 ty) (imul x (sinkable_sload16 y))))
378
+ (mul_mem_sext16 ty x (sink_sload16 y)))
379
+ (rule 10 (lower (has_type (fits_in_64 ty) (imul (sinkable_sload16 x) y)))
380
+ (mul_mem_sext16 ty y (sink_sload16 x)))
381
+ (rule 2 (lower (has_type (fits_in_64 ty) (imul x (sinkable_sload32 y))))
382
+ (mul_mem_sext32 ty x (sink_sload32 y)))
383
+ (rule 9 (lower (has_type (fits_in_64 ty) (imul (sinkable_sload32 x) y)))
384
+ (mul_mem_sext32 ty y (sink_sload32 x)))
385
+
386
+ ;; Multiply two vector registers, using a helper.
387
+ (decl vec_mul_impl (Type Reg Reg) Reg)
388
+ (rule 1 (lower (has_type (vr128_ty ty) (imul x y)))
389
+ (vec_mul_impl ty x y))
390
+
391
+ ;; Multiply two vector registers - byte, halfword, and word.
392
+ (rule (vec_mul_impl $I8X16 x y) (vec_mul $I8X16 x y))
393
+ (rule (vec_mul_impl $I16X8 x y) (vec_mul $I16X8 x y))
394
+ (rule (vec_mul_impl $I32X4 x y) (vec_mul $I32X4 x y))
395
+
396
+ ;; Multiply two vector registers - doubleword. Has to be scalarized.
397
+ (rule (vec_mul_impl $I64X2 x y)
398
+ (mov_to_vec128 $I64X2
399
+ (mul_reg $I64 (vec_extract_lane $I64X2 x 0 (zero_reg))
400
+ (vec_extract_lane $I64X2 y 0 (zero_reg)))
401
+ (mul_reg $I64 (vec_extract_lane $I64X2 x 1 (zero_reg))
402
+ (vec_extract_lane $I64X2 y 1 (zero_reg)))))
403
+
404
+ ;; Multiply two vector registers - quadword.
405
+ (rule (vec_mul_impl $I128 x y)
406
+ (let ((x_hi Reg (vec_extract_lane $I64X2 x 0 (zero_reg)))
407
+ (x_lo Reg (vec_extract_lane $I64X2 x 1 (zero_reg)))
408
+ (y_hi Reg (vec_extract_lane $I64X2 y 0 (zero_reg)))
409
+ (y_lo Reg (vec_extract_lane $I64X2 y 1 (zero_reg)))
410
+ (lo_pair RegPair (umul_wide x_lo y_lo))
411
+ (res_lo Reg (regpair_lo lo_pair))
412
+ (res_hi_1 Reg (regpair_hi lo_pair))
413
+ (res_hi_2 Reg (mul_reg $I64 x_lo y_hi))
414
+ (res_hi_3 Reg (mul_reg $I64 x_hi y_lo))
415
+ (res_hi Reg (add_reg $I64 res_hi_3 (add_reg $I64 res_hi_2 res_hi_1))))
416
+ (mov_to_vec128 $I64X2 res_hi res_lo)))
417
+
418
+
419
+ ;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
420
+
421
+ ;; Multiply high part unsigned, 8-bit or 16-bit types. (Uses 32-bit multiply.)
422
+ (rule -1 (lower (has_type (ty_8_or_16 ty) (umulhi x y)))
423
+ (let ((ext_reg_x Reg (put_in_reg_zext32 x))
424
+ (ext_reg_y Reg (put_in_reg_zext32 y))
425
+ (ext_mul Reg (mul_reg $I32 ext_reg_x ext_reg_y)))
426
+ (lshr_imm $I32 ext_mul (ty_bits ty))))
427
+
428
+ ;; Multiply high part unsigned, 32-bit types. (Uses 64-bit multiply.)
429
+ (rule (lower (has_type $I32 (umulhi x y)))
430
+ (let ((ext_reg_x Reg (put_in_reg_zext64 x))
431
+ (ext_reg_y Reg (put_in_reg_zext64 y))
432
+ (ext_mul Reg (mul_reg $I64 ext_reg_x ext_reg_y)))
433
+ (lshr_imm $I64 ext_mul 32)))
434
+
435
+ ;; Multiply high part unsigned, 64-bit types. (Uses umul_wide.)
436
+ (rule (lower (has_type $I64 (umulhi x y)))
437
+ (let ((pair RegPair (umul_wide x y)))
438
+ (regpair_hi pair)))
439
+
440
+ ;; Multiply high part unsigned, vector types with 8-, 16-, or 32-bit elements.
441
+ (rule (lower (has_type $I8X16 (umulhi x y))) (vec_umulhi $I8X16 x y))
442
+ (rule (lower (has_type $I16X8 (umulhi x y))) (vec_umulhi $I16X8 x y))
443
+ (rule (lower (has_type $I32X4 (umulhi x y))) (vec_umulhi $I32X4 x y))
444
+
445
+ ;; Multiply high part unsigned, vector types with 64-bit elements.
446
+ ;; Has to be scalarized.
447
+ (rule (lower (has_type $I64X2 (umulhi x y)))
448
+ (let ((pair_0 RegPair (umul_wide (vec_extract_lane $I64X2 x 0 (zero_reg))
449
+ (vec_extract_lane $I64X2 y 0 (zero_reg))))
450
+ (res_0 Reg (regpair_hi pair_0))
451
+ (pair_1 RegPair (umul_wide (vec_extract_lane $I64X2 x 1 (zero_reg))
452
+ (vec_extract_lane $I64X2 y 1 (zero_reg))))
453
+ (res_1 Reg (regpair_hi pair_1)))
454
+ (mov_to_vec128 $I64X2 res_0 res_1)))
455
+
456
+
457
+ ;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
458
+
459
+ ;; Multiply high part signed, 8-bit or 16-bit types. (Uses 32-bit multiply.)
460
+ (rule -1 (lower (has_type (ty_8_or_16 ty) (smulhi x y)))
461
+ (let ((ext_reg_x Reg (put_in_reg_sext32 x))
462
+ (ext_reg_y Reg (put_in_reg_sext32 y))
463
+ (ext_mul Reg (mul_reg $I32 ext_reg_x ext_reg_y)))
464
+ (ashr_imm $I32 ext_mul (ty_bits ty))))
465
+
466
+ ;; Multiply high part signed, 32-bit types. (Uses 64-bit multiply.)
467
+ (rule (lower (has_type $I32 (smulhi x y)))
468
+ (let ((ext_reg_x Reg (put_in_reg_sext64 x))
469
+ (ext_reg_y Reg (put_in_reg_sext64 y))
470
+ (ext_mul Reg (mul_reg $I64 ext_reg_x ext_reg_y)))
471
+ (ashr_imm $I64 ext_mul 32)))
472
+
473
+ ;; Multiply high part signed, 64-bit types. (Uses smul_wide.)
474
+ (rule (lower (has_type $I64 (smulhi x y)))
475
+ (let ((pair RegPair (smul_wide x y)))
476
+ (regpair_hi pair)))
477
+
478
+ ;; Multiply high part signed, vector types with 8-, 16-, or 32-bit elements.
479
+ (rule (lower (has_type $I8X16 (smulhi x y))) (vec_smulhi $I8X16 x y))
480
+ (rule (lower (has_type $I16X8 (smulhi x y))) (vec_smulhi $I16X8 x y))
481
+ (rule (lower (has_type $I32X4 (smulhi x y))) (vec_smulhi $I32X4 x y))
482
+
483
+ ;; Multiply high part unsigned, vector types with 64-bit elements.
484
+ ;; Has to be scalarized.
485
+ (rule (lower (has_type $I64X2 (smulhi x y)))
486
+ (let ((pair_0 RegPair (smul_wide (vec_extract_lane $I64X2 x 0 (zero_reg))
487
+ (vec_extract_lane $I64X2 y 0 (zero_reg))))
488
+ (res_0 Reg (copy_reg $I64 (regpair_hi pair_0)))
489
+ (pair_1 RegPair (smul_wide (vec_extract_lane $I64X2 x 1 (zero_reg))
490
+ (vec_extract_lane $I64X2 y 1 (zero_reg))))
491
+ (res_1 Reg (regpair_hi pair_1)))
492
+ (mov_to_vec128 $I64X2 res_0 res_1)))
493
+
494
+
495
+ ;;;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
496
+
497
+ ;; Fixed-point multiplication of two vector registers.
498
+ (rule (lower (has_type (ty_vec128 ty) (sqmul_round_sat x y)))
499
+ (vec_pack_ssat (vec_widen_type ty)
500
+ (sqmul_impl (vec_widen_type ty)
501
+ (vec_unpacks_high ty x)
502
+ (vec_unpacks_high ty y))
503
+ (sqmul_impl (vec_widen_type ty)
504
+ (vec_unpacks_low ty x)
505
+ (vec_unpacks_low ty y))))
506
+
507
+ ;; Helper to perform the rounded multiply in the wider type.
508
+ (decl sqmul_impl (Type Reg Reg) Reg)
509
+ (rule (sqmul_impl $I32X4 x y)
510
+ (vec_ashr_imm $I32X4 (vec_add $I32X4 (vec_mul_impl $I32X4 x y)
511
+ (vec_imm_bit_mask $I32X4 17 17))
512
+ 15))
513
+ (rule (sqmul_impl $I64X2 x y)
514
+ (vec_ashr_imm $I64X2 (vec_add $I64X2 (vec_mul_impl $I64X2 x y)
515
+ (vec_imm_bit_mask $I64X2 33 33))
516
+ 31))
517
+
518
+
519
+ ;;;; Rules for `udiv` and `urem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
520
+
521
+ ;; Divide two registers. The architecture provides combined udiv / urem
522
+ ;; instructions with the following combination of data types:
523
+ ;;
524
+ ;; - 64-bit dividend (split across a 2x32-bit register pair),
525
+ ;; 32-bit divisor (in a single input register)
526
+ ;; 32-bit quotient & remainder (in a 2x32-bit register pair)
527
+ ;;
528
+ ;; - 128-bit dividend (split across a 2x64-bit register pair),
529
+ ;; 64-bit divisor (in a single input register)
530
+ ;; 64-bit quotient & remainder (in a 2x64-bit register pair)
531
+ ;;
532
+ ;; We use the first variant for 32-bit and smaller input types,
533
+ ;; and the second variant for 64-bit input types.
534
+
535
+ ;; Implement `udiv`.
536
+ (rule (lower (has_type (fits_in_64 ty) (udiv x y)))
537
+ (let (;; Look at the divisor to determine whether we need to generate
538
+ ;; an explicit division-by zero check.
539
+ ;; Load up the dividend, by loading the input (possibly zero-
540
+ ;; extended) input into the low half of the register pair,
541
+ ;; and setting the high half to zero.
542
+ (ext_x RegPair (regpair (imm (ty_ext32 ty) 0)
543
+ (put_in_reg_zext32 x)))
544
+ ;; Load up the divisor, zero-extended if necessary.
545
+ (ext_y Reg (put_in_reg_zext32 y))
546
+ (ext_ty Type (ty_ext32 ty))
547
+ ;; Emit the actual divide instruction.
548
+ (pair RegPair (udivmod ext_ty ext_x ext_y)))
549
+ ;; The quotient can be found in the low half of the result.
550
+ (regpair_lo pair)))
551
+
552
+ ;; Implement `urem`. Same as `udiv`, but finds the remainder in
553
+ ;; the high half of the result register pair instead.
554
+ (rule (lower (has_type (fits_in_64 ty) (urem x y)))
555
+ (let ((ext_x RegPair (regpair (imm (ty_ext32 ty) 0)
556
+ (put_in_reg_zext32 x)))
557
+ (ext_y Reg (put_in_reg_zext32 y))
558
+ (ext_ty Type (ty_ext32 ty))
559
+ (pair RegPair (udivmod ext_ty ext_x ext_y)))
560
+ (regpair_hi pair)))
561
+
562
+
563
+ ;;;; Rules for `sdiv` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
564
+
565
+ ;; Divide two registers. The architecture provides combined sdiv / srem
566
+ ;; instructions with the following combination of data types:
567
+ ;;
568
+ ;; - 64-bit dividend (in the low half of a 2x64-bit register pair),
569
+ ;; 32-bit divisor (in a single input register)
570
+ ;; 64-bit quotient & remainder (in a 2x64-bit register pair)
571
+ ;;
572
+ ;; - 64-bit dividend (in the low half of a 2x64-bit register pair),
573
+ ;; 64-bit divisor (in a single input register)
574
+ ;; 64-bit quotient & remainder (in a 2x64-bit register pair)
575
+ ;;
576
+ ;; We use the first variant for 32-bit and smaller input types,
577
+ ;; and the second variant for 64-bit input types.
578
+
579
+ ;; Implement `sdiv`.
580
+ (rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
581
+ (let (;; Look at the divisor to determine whether we need to generate
582
+ ;; explicit division-by-zero and/or integer-overflow checks.
583
+ (OFcheck bool (div_overflow_check_needed y))
584
+ ;; Load up the dividend (sign-extended to 64-bit)
585
+ (ext_x Reg (put_in_reg_sext64 x))
586
+ ;; Load up the divisor (sign-extended if necessary).
587
+ (ext_y Reg (put_in_reg_sext32 y))
588
+ (ext_ty Type (ty_ext32 ty))
589
+ ;; Perform integer-overflow check if necessary.
590
+ (_ Reg (maybe_trap_if_sdiv_overflow OFcheck ext_ty ty ext_x ext_y))
591
+ ;; Emit the actual divide instruction.
592
+ (pair RegPair (sdivmod ext_ty ext_x ext_y)))
593
+ ;; The quotient can be found in the low half of the result.
594
+ (regpair_lo pair)))
595
+
596
+ ;; Implement `srem`. Same as `sdiv`, but finds the remainder in
597
+ ;; the high half of the result register pair instead. Also, handle
598
+ ;; the integer overflow case differently, see below.
599
+ (rule (lower (has_type (fits_in_64 ty) (srem x y)))
600
+ (let ((OFcheck bool (div_overflow_check_needed y))
601
+ (ext_x Reg (put_in_reg_sext64 x))
602
+ (ext_y Reg (put_in_reg_sext32 y))
603
+ (ext_ty Type (ty_ext32 ty))
604
+ (checked_x Reg (maybe_avoid_srem_overflow OFcheck ext_ty ext_x ext_y))
605
+ (pair RegPair (sdivmod ext_ty checked_x ext_y)))
606
+ (regpair_hi pair)))
607
+
608
+ ;; Determine whether we need to perform an integer-overflow check.
609
+ ;;
610
+ ;; We never rely on the divide instruction itself to trap; while that trap
611
+ ;; would indeed happen, we have no way of signalling two different trap
612
+ ;; conditions from the same instruction. By explicity checking for the
613
+ ;; integer-overflow case ahead of time, any hardware trap in the divide
614
+ ;; instruction is guaranteed to indicate divison-by-zero.
615
+ ;;
616
+ ;; In addition, for types smaller than 64 bits we would have to perform
617
+ ;; the check explicitly anyway, since the instruction provides a 64-bit
618
+ ;; quotient and only traps if *that* overflows.
619
+ ;;
620
+ ;; However, the only case where integer overflow can occur is if the
621
+ ;; minimum (signed) integer value is divided by -1, so if the divisor
622
+ ;; is any immediate different from -1, the check can be omitted.
623
+ (decl div_overflow_check_needed (Value) bool)
624
+ (rule 1 (div_overflow_check_needed (i64_from_value x))
625
+ (if (i64_not_neg1 x))
626
+ $false)
627
+ (rule (div_overflow_check_needed _) $true)
628
+
629
+ ;; Perform the integer-overflow check if necessary. This implements:
630
+ ;;
631
+ ;; if divisor == INT_MIN && dividend == -1 { trap }
632
+ ;;
633
+ ;; but to avoid introducing control flow, it is actually done as:
634
+ ;;
635
+ ;; if ((divisor ^ INT_MAX) & dividend) == -1 { trap }
636
+ ;;
637
+ ;; instead, using a single conditional trap instruction.
638
+ (decl maybe_trap_if_sdiv_overflow (bool Type Type Reg Reg) Reg)
639
+ (rule (maybe_trap_if_sdiv_overflow $false ext_ty _ _ _) (invalid_reg))
640
+ (rule (maybe_trap_if_sdiv_overflow $true ext_ty ty x y)
641
+ (let ((int_max Reg (imm ext_ty (int_max ty)))
642
+ (reg Reg (and_reg ext_ty (xor_reg ext_ty int_max x) y)))
643
+ (icmps_simm16_and_trap ext_ty reg -1
644
+ (intcc_as_cond (IntCC.Equal))
645
+ (trap_code_integer_overflow))))
646
+ (decl int_max (Type) u64)
647
+ (rule (int_max $I8) 0x7f)
648
+ (rule (int_max $I16) 0x7fff)
649
+ (rule (int_max $I32) 0x7fffffff)
650
+ (rule (int_max $I64) 0x7fffffffffffffff)
651
+
652
+ ;; When performing `srem`, we do not want to trap in the
653
+ ;; integer-overflow scenario, because it is only the quotient
654
+ ;; that overflows, not the remainder.
655
+ ;;
656
+ ;; For types smaller than 64 bits, we can simply let the
657
+ ;; instruction execute, since (as above) it will never trap.
658
+ ;;
659
+ ;; For 64-bit inputs, we check whether the divisor is -1, and
660
+ ;; if so simply replace the dividend by zero, which will give
661
+ ;; the correct result, since any value modulo -1 is zero.
662
+ ;;
663
+ ;; (We could in fact avoid executing the divide instruction
664
+ ;; at all in this case, but that would require introducing
665
+ ;; control flow.)
666
+ (decl maybe_avoid_srem_overflow (bool Type Reg Reg) Reg)
667
+ (rule (maybe_avoid_srem_overflow $false _ x _) x)
668
+ (rule (maybe_avoid_srem_overflow $true $I32 x _) x)
669
+ (rule (maybe_avoid_srem_overflow $true $I64 x y)
670
+ (with_flags_reg (icmps_simm16 $I64 y -1)
671
+ (cmov_imm $I64 (intcc_as_cond (IntCC.Equal)) 0 x)))
672
+
673
+
674
+ ;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
675
+
676
+ ;; Shift left, shift amount in register.
677
+ (rule 0 (lower (has_type (fits_in_64 ty) (ishl x y)))
678
+ (let ((masked_amt Reg (mask_amt_reg ty (amt_reg y))))
679
+ (lshl_reg ty x masked_amt)))
680
+
681
+ ;; Shift left, immediate shift amount.
682
+ (rule 1 (lower (has_type (fits_in_64 ty) (ishl x (i64_from_value y))))
683
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
684
+ (lshl_imm ty x masked_amt)))
685
+
686
+ ;; Vector shift left, shift amount in register.
687
+ (rule 2 (lower (has_type (ty_vec128 ty) (ishl x y)))
688
+ (vec_lshl_reg ty x (amt_reg y)))
689
+
690
+ ;; Vector shift left, immediate shift amount.
691
+ (rule 3 (lower (has_type (ty_vec128 ty) (ishl x (i64_from_value y))))
692
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
693
+ (vec_lshl_imm ty x masked_amt)))
694
+
695
+ ;; 128-bit vector shift left.
696
+ (rule 4 (lower (has_type $I128 (ishl x y)))
697
+ (let ((amt Reg (amt_vr y)))
698
+ (vec_lshl_by_bit (vec_lshl_by_byte x amt) amt)))
699
+
700
+
701
+ ;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
702
+
703
+ ;; Shift right logical, shift amount in register.
704
+ ;; For types smaller than 32-bit, the input value must be zero-extended.
705
+ (rule 0 (lower (has_type (fits_in_64 ty) (ushr x y)))
706
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
707
+ (masked_amt Reg (mask_amt_reg ty (amt_reg y))))
708
+ (lshr_reg (ty_ext32 ty) ext_reg masked_amt)))
709
+
710
+ ;; Shift right logical, immediate shift amount.
711
+ ;; For types smaller than 32-bit, the input value must be zero-extended.
712
+ (rule 1 (lower (has_type (fits_in_64 ty) (ushr x (i64_from_value y))))
713
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
714
+ (masked_amt u8 (mask_amt_imm ty y)))
715
+ (lshr_imm (ty_ext32 ty) ext_reg masked_amt)))
716
+
717
+ ;; Vector shift right logical, shift amount in register.
718
+ (rule 2 (lower (has_type (ty_vec128 ty) (ushr x y)))
719
+ (vec_lshr_reg ty x (amt_reg y)))
720
+
721
+ ;; Vector shift right logical, immediate shift amount.
722
+ (rule 3 (lower (has_type (ty_vec128 ty) (ushr x (i64_from_value y))))
723
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
724
+ (vec_lshr_imm ty x masked_amt)))
725
+
726
+ ;; 128-bit vector shift right logical.
727
+ (rule 4 (lower (has_type $I128 (ushr x y)))
728
+ (let ((amt Reg (amt_vr y)))
729
+ (vec_lshr_by_bit (vec_lshr_by_byte x amt) amt)))
730
+
731
+
732
+ ;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
733
+
734
+ ;; Shift right arithmetic, shift amount in register.
735
+ ;; For types smaller than 32-bit, the input value must be sign-extended.
736
+ (rule 0 (lower (has_type (fits_in_64 ty) (sshr x y)))
737
+ (let ((ext_reg Reg (put_in_reg_sext32 x))
738
+ (masked_amt Reg (mask_amt_reg ty (amt_reg y))))
739
+ (ashr_reg (ty_ext32 ty) ext_reg masked_amt)))
740
+
741
+ ;; Shift right arithmetic, immediate shift amount.
742
+ ;; For types smaller than 32-bit, the input value must be sign-extended.
743
+ (rule 1 (lower (has_type (fits_in_64 ty) (sshr x (i64_from_value y))))
744
+ (let ((ext_reg Reg (put_in_reg_sext32 x))
745
+ (masked_amt u8 (mask_amt_imm ty y)))
746
+ (ashr_imm (ty_ext32 ty) ext_reg masked_amt)))
747
+
748
+ ;; Vector shift right arithmetic, shift amount in register.
749
+ (rule 2 (lower (has_type (ty_vec128 ty) (sshr x y)))
750
+ (vec_ashr_reg ty x (amt_reg y)))
751
+
752
+ ;; Vector shift right arithmetic, immediate shift amount.
753
+ (rule 3 (lower (has_type (ty_vec128 ty) (sshr x (i64_from_value y))))
754
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
755
+ (vec_ashr_imm ty x masked_amt)))
756
+
757
+ ;; 128-bit vector shift right arithmetic.
758
+ (rule 4 (lower (has_type $I128 (sshr x y)))
759
+ (let ((amt Reg (amt_vr y)))
760
+ (vec_ashr_by_bit (vec_ashr_by_byte x amt) amt)))
761
+
762
+
763
+ ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
764
+
765
+ ;; Rotate left, shift amount in register. 32-bit or 64-bit types.
766
+ (rule 0 (lower (has_type (ty_32_or_64 ty) (rotl x y)))
767
+ (rot_reg ty x (amt_reg y)))
768
+
769
+ ;; Rotate left arithmetic, immediate shift amount. 32-bit or 64-bit types.
770
+ (rule 1 (lower (has_type (ty_32_or_64 ty) (rotl x (i64_from_value y))))
771
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
772
+ (rot_imm ty x masked_amt)))
773
+
774
+ ;; Rotate left, shift amount in register. 8-bit or 16-bit types.
775
+ ;; Implemented via a pair of 32-bit shifts on the zero-extended input.
776
+ (rule 2 (lower (has_type (ty_8_or_16 ty) (rotl x y)))
777
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
778
+ (ext_ty Type (ty_ext32 ty))
779
+ (pos_amt Reg (amt_reg y))
780
+ (neg_amt Reg (neg_reg $I32 pos_amt))
781
+ (masked_pos_amt Reg (mask_amt_reg ty pos_amt))
782
+ (masked_neg_amt Reg (mask_amt_reg ty neg_amt)))
783
+ (or_reg ty (lshl_reg ext_ty ext_reg masked_pos_amt)
784
+ (lshr_reg ext_ty ext_reg masked_neg_amt))))
785
+
786
+ ;; Rotate left, immediate shift amount. 8-bit or 16-bit types.
787
+ ;; Implemented via a pair of 32-bit shifts on the zero-extended input.
788
+ (rule 3 (lower (has_type (ty_8_or_16 ty) (rotl x (and (i64_from_value pos_amt)
789
+ (i64_from_negated_value neg_amt)))))
790
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
791
+ (ext_ty Type (ty_ext32 ty))
792
+ (masked_pos_amt u8 (mask_amt_imm ty pos_amt))
793
+ (masked_neg_amt u8 (mask_amt_imm ty neg_amt)))
794
+ (or_reg ty (lshl_imm ext_ty ext_reg masked_pos_amt)
795
+ (lshr_imm ext_ty ext_reg masked_neg_amt))))
796
+
797
+ ;; Vector rotate left, shift amount in register.
798
+ (rule 4 (lower (has_type (ty_vec128 ty) (rotl x y)))
799
+ (vec_rot_reg ty x (amt_reg y)))
800
+
801
+ ;; Vector rotate left, immediate shift amount.
802
+ (rule 5 (lower (has_type (ty_vec128 ty) (rotl x (i64_from_value y))))
803
+ (let ((masked_amt u8 (mask_amt_imm ty y)))
804
+ (vec_rot_imm ty x masked_amt)))
805
+
806
+ ;; 128-bit full vector rotate left.
807
+ ;; Implemented via a pair of 128-bit full vector shifts.
808
+ (rule 6 (lower (has_type $I128 (rotl x y)))
809
+ (let ((x_reg Reg x)
810
+ (pos_amt Reg (amt_vr y))
811
+ (neg_amt Reg (vec_neg $I8X16 pos_amt)))
812
+ (vec_or $I128
813
+ (vec_lshl_by_bit (vec_lshl_by_byte x_reg pos_amt) pos_amt)
814
+ (vec_lshr_by_bit (vec_lshr_by_byte x_reg neg_amt) neg_amt))))
815
+
816
+
817
+ ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
818
+
819
+ ;; Rotate right, shift amount in register. 32-bit or 64-bit types.
820
+ ;; Implemented as rotate left with negated rotate amount.
821
+ (rule 0 (lower (has_type (ty_32_or_64 ty) (rotr x y)))
822
+ (let ((negated_amt Reg (neg_reg $I32 (amt_reg y))))
823
+ (rot_reg ty x negated_amt)))
824
+
825
+ ;; Rotate right arithmetic, immediate shift amount. 32-bit or 64-bit types.
826
+ ;; Implemented as rotate left with negated rotate amount.
827
+ (rule 1 (lower (has_type (ty_32_or_64 ty) (rotr x (i64_from_negated_value y))))
828
+ (let ((negated_amt u8 (mask_amt_imm ty y)))
829
+ (rot_imm ty x negated_amt)))
830
+
831
+ ;; Rotate right, shift amount in register. 8-bit or 16-bit types.
832
+ ;; Implemented as rotate left with negated rotate amount.
833
+ (rule 2 (lower (has_type (ty_8_or_16 ty) (rotr x y)))
834
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
835
+ (ext_ty Type (ty_ext32 ty))
836
+ (pos_amt Reg (amt_reg y))
837
+ (neg_amt Reg (neg_reg $I32 pos_amt))
838
+ (masked_pos_amt Reg (mask_amt_reg ty pos_amt))
839
+ (masked_neg_amt Reg (mask_amt_reg ty neg_amt)))
840
+ (or_reg ty (lshl_reg ext_ty ext_reg masked_neg_amt)
841
+ (lshr_reg ext_ty ext_reg masked_pos_amt))))
842
+
843
+ ;; Rotate right, immediate shift amount. 8-bit or 16-bit types.
844
+ ;; Implemented as rotate left with negated rotate amount.
845
+ (rule 3 (lower (has_type (ty_8_or_16 ty) (rotr x (and (i64_from_value pos_amt)
846
+ (i64_from_negated_value neg_amt)))))
847
+ (let ((ext_reg Reg (put_in_reg_zext32 x))
848
+ (ext_ty Type (ty_ext32 ty))
849
+ (masked_pos_amt u8 (mask_amt_imm ty pos_amt))
850
+ (masked_neg_amt u8 (mask_amt_imm ty neg_amt)))
851
+ (or_reg ty (lshl_imm ext_ty ext_reg masked_neg_amt)
852
+ (lshr_imm ext_ty ext_reg masked_pos_amt))))
853
+
854
+ ;; Vector rotate right, shift amount in register.
855
+ ;; Implemented as rotate left with negated rotate amount.
856
+ (rule 4 (lower (has_type (ty_vec128 ty) (rotr x y)))
857
+ (let ((negated_amt Reg (neg_reg $I32 (amt_reg y))))
858
+ (vec_rot_reg ty x negated_amt)))
859
+
860
+ ;; Vector rotate right, immediate shift amount.
861
+ ;; Implemented as rotate left with negated rotate amount.
862
+ (rule 5 (lower (has_type (ty_vec128 ty) (rotr x (i64_from_negated_value y))))
863
+ (let ((negated_amt u8 (mask_amt_imm ty y)))
864
+ (vec_rot_imm ty x negated_amt)))
865
+
866
+ ;; 128-bit full vector rotate right.
867
+ ;; Implemented via a pair of 128-bit full vector shifts.
868
+ (rule 6 (lower (has_type $I128 (rotr x y)))
869
+ (let ((x_reg Reg x)
870
+ (pos_amt Reg (amt_vr y))
871
+ (neg_amt Reg (vec_neg $I8X16 pos_amt)))
872
+ (vec_or $I128
873
+ (vec_lshl_by_bit (vec_lshl_by_byte x_reg neg_amt) neg_amt)
874
+ (vec_lshr_by_bit (vec_lshr_by_byte x_reg pos_amt) pos_amt))))
875
+
876
+
877
+ ;;;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
878
+
879
+ ;; Up to 64-bit source type: Always a no-op.
880
+ (rule 1 (lower (ireduce x @ (value_type (fits_in_64 _ty))))
881
+ x)
882
+
883
+ ;; 128-bit source type: Extract the low half.
884
+ (rule (lower (ireduce x @ (value_type (vr128_ty _ty))))
885
+ (vec_extract_lane $I64X2 x 1 (zero_reg)))
886
+
887
+
888
+ ;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
889
+
890
+ ;; 16- or 32-bit target types.
891
+ (rule 1 (lower (has_type (gpr32_ty _ty) (uextend x)))
892
+ (put_in_reg_zext32 x))
893
+
894
+ ;; 64-bit target types.
895
+ (rule 2 (lower (has_type (gpr64_ty _ty) (uextend x)))
896
+ (put_in_reg_zext64 x))
897
+
898
+ ;; 128-bit target types.
899
+ (rule (lower (has_type $I128 (uextend x @ (value_type $I8))))
900
+ (vec_insert_lane $I8X16 (vec_imm $I128 0) x 15 (zero_reg)))
901
+ (rule (lower (has_type $I128 (uextend x @ (value_type $I16))))
902
+ (vec_insert_lane $I16X8 (vec_imm $I128 0) x 7 (zero_reg)))
903
+ (rule (lower (has_type $I128 (uextend x @ (value_type $I32))))
904
+ (vec_insert_lane $I32X4 (vec_imm $I128 0) x 3 (zero_reg)))
905
+ (rule (lower (has_type $I128 (uextend x @ (value_type $I64))))
906
+ (vec_insert_lane $I64X2 (vec_imm $I128 0) x 1 (zero_reg)))
907
+
908
+
909
+ ;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
910
+
911
+ ;; 16- or 32-bit target types.
912
+ (rule 1 (lower (has_type (gpr32_ty _ty) (sextend x)))
913
+ (put_in_reg_sext32 x))
914
+
915
+ ;; 64-bit target types.
916
+ (rule 2 (lower (has_type (gpr64_ty _ty) (sextend x)))
917
+ (put_in_reg_sext64 x))
918
+
919
+ ;; 128-bit target types.
920
+ (rule (lower (has_type $I128 (sextend x)))
921
+ (let ((x_ext Reg (put_in_reg_sext64 x)))
922
+ (mov_to_vec128 $I128 (ashr_imm $I64 x_ext 63) x_ext)))
923
+
924
+
925
+ ;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
926
+
927
+ (rule (lower (snarrow x @ (value_type (ty_vec128 ty)) y))
928
+ (vec_pack_ssat_lane_order ty x y))
929
+
930
+
931
+ ;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
932
+
933
+ (rule (lower (uunarrow x @ (value_type (ty_vec128 ty)) y))
934
+ (vec_pack_usat_lane_order ty x y))
935
+
936
+
937
+ ;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
938
+
939
+ (rule (lower (unarrow x @ (value_type (ty_vec128 ty)) y))
940
+ (let ((zero Reg (vec_imm ty 0)))
941
+ (vec_pack_usat_lane_order ty (vec_smax ty x zero) (vec_smax ty y zero))))
942
+
943
+
944
+ ;;;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
945
+
946
+ (rule (lower (swiden_low x @ (value_type (ty_vec128 ty))))
947
+ (vec_unpacks_low_lane_order ty x))
948
+
949
+
950
+ ;;;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
951
+
952
+ (rule (lower (swiden_high x @ (value_type (ty_vec128 ty))))
953
+ (vec_unpacks_high_lane_order ty x))
954
+
955
+
956
+ ;;;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
957
+
958
+ (rule (lower (uwiden_low x @ (value_type (ty_vec128 ty))))
959
+ (vec_unpacku_low_lane_order ty x))
960
+
961
+
962
+ ;;;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
963
+
964
+ (rule (lower (uwiden_high x @ (value_type (ty_vec128 ty))))
965
+ (vec_unpacku_high_lane_order ty x))
966
+
967
+
968
+ ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
969
+
970
+ ;; z15 version using a single instruction (NOR).
971
+ (rule 2 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bnot x)))
972
+ (let ((rx Reg x))
973
+ (not_or_reg ty rx rx)))
974
+
975
+ ;; z14 version using XOR with -1.
976
+ (rule 1 (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bnot x)))
977
+ (not_reg ty x))
978
+
979
+ ;; Vector version using vector NOR.
980
+ (rule (lower (has_type (vr128_ty ty) (bnot x)))
981
+ (vec_not ty x))
982
+
983
+ ;; With z15 (bnot (bxor ...)) can be a single instruction, similar to the
984
+ ;; (bxor _ (bnot _)) lowering.
985
+ (rule 3 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bnot (bxor x y))))
986
+ (not_xor_reg ty x y))
987
+
988
+ ;; Combine a not/xor operation of vector types into one.
989
+ (rule 4 (lower (has_type (vr128_ty ty) (bnot (bxor x y))))
990
+ (vec_not_xor ty x y))
991
+
992
+
993
+ ;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
994
+
995
+ ;; And two registers.
996
+ (rule -1 (lower (has_type (fits_in_64 ty) (band x y)))
997
+ (and_reg ty x y))
998
+
999
+ ;; And a register and an immediate.
1000
+ (rule 5 (lower (has_type (fits_in_64 ty) (band x (uimm16shifted_from_inverted_value y))))
1001
+ (and_uimm16shifted ty x y))
1002
+ (rule 6 (lower (has_type (fits_in_64 ty) (band (uimm16shifted_from_inverted_value x) y)))
1003
+ (and_uimm16shifted ty y x))
1004
+ (rule 3 (lower (has_type (fits_in_64 ty) (band x (uimm32shifted_from_inverted_value y))))
1005
+ (and_uimm32shifted ty x y))
1006
+ (rule 4 (lower (has_type (fits_in_64 ty) (band (uimm32shifted_from_inverted_value x) y)))
1007
+ (and_uimm32shifted ty y x))
1008
+
1009
+ ;; And a register and memory (32/64-bit types).
1010
+ (rule 1 (lower (has_type (fits_in_64 ty) (band x (sinkable_load_32_64 y))))
1011
+ (and_mem ty x (sink_load y)))
1012
+ (rule 2 (lower (has_type (fits_in_64 ty) (band (sinkable_load_32_64 x) y)))
1013
+ (and_mem ty y (sink_load x)))
1014
+
1015
+ ;; And two vector registers.
1016
+ (rule 0 (lower (has_type (vr128_ty ty) (band x y)))
1017
+ (vec_and ty x y))
1018
+
1019
+ ;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
1020
+ ;; by Cranelift's `band_not` instruction that is legalized into the simpler
1021
+ ;; forms early on.
1022
+
1023
+ ;; z15 version using a single instruction.
1024
+ (rule 7 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (band x (bnot y))))
1025
+ (and_not_reg ty x y))
1026
+ (rule 8 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (band (bnot y) x)))
1027
+ (and_not_reg ty x y))
1028
+
1029
+ ;; And-not two vector registers.
1030
+ (rule 9 (lower (has_type (vr128_ty ty) (band x (bnot y))))
1031
+ (vec_and_not ty x y))
1032
+ (rule 10 (lower (has_type (vr128_ty ty) (band (bnot y) x)))
1033
+ (vec_and_not ty x y))
1034
+
1035
+ ;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1036
+
1037
+ ;; Or two registers.
1038
+ (rule -1 (lower (has_type (fits_in_64 ty) (bor x y)))
1039
+ (or_reg ty x y))
1040
+
1041
+ ;; Or a register and an immediate.
1042
+ (rule 5 (lower (has_type (fits_in_64 ty) (bor x (uimm16shifted_from_value y))))
1043
+ (or_uimm16shifted ty x y))
1044
+ (rule 6 (lower (has_type (fits_in_64 ty) (bor (uimm16shifted_from_value x) y)))
1045
+ (or_uimm16shifted ty y x))
1046
+ (rule 3 (lower (has_type (fits_in_64 ty) (bor x (uimm32shifted_from_value y))))
1047
+ (or_uimm32shifted ty x y))
1048
+ (rule 4 (lower (has_type (fits_in_64 ty) (bor (uimm32shifted_from_value x) y)))
1049
+ (or_uimm32shifted ty y x))
1050
+
1051
+ ;; Or a register and memory (32/64-bit types).
1052
+ (rule 1 (lower (has_type (fits_in_64 ty) (bor x (sinkable_load_32_64 y))))
1053
+ (or_mem ty x (sink_load y)))
1054
+ (rule 2 (lower (has_type (fits_in_64 ty) (bor (sinkable_load_32_64 x) y)))
1055
+ (or_mem ty y (sink_load x)))
1056
+
1057
+ ;; Or two vector registers.
1058
+ (rule 0 (lower (has_type (vr128_ty ty) (bor x y)))
1059
+ (vec_or ty x y))
1060
+
1061
+ ;; Specialized lowerings for `(bor x (bnot y))` which is additionally produced
1062
+ ;; by Cranelift's `bor_not` instruction that is legalized into the simpler
1063
+ ;; forms early on.
1064
+
1065
+ ;; z15 version using a single instruction.
1066
+ (rule 7 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bor x (bnot y))))
1067
+ (or_not_reg ty x y))
1068
+ (rule 8 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bor (bnot y) x)))
1069
+ (or_not_reg ty x y))
1070
+
1071
+ ;; Or-not two vector registers.
1072
+ (rule 9 (lower (has_type (vr128_ty ty) (bor x (bnot y))))
1073
+ (vec_or_not ty x y))
1074
+ (rule 10 (lower (has_type (vr128_ty ty) (bor (bnot y) x)))
1075
+ (vec_or_not ty x y))
1076
+
1077
+
1078
+ ;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1079
+
1080
+ ;; Xor two registers.
1081
+ (rule -1 (lower (has_type (fits_in_64 ty) (bxor x y)))
1082
+ (xor_reg ty x y))
1083
+
1084
+ ;; Xor a register and an immediate.
1085
+ (rule 3 (lower (has_type (fits_in_64 ty) (bxor x (uimm32shifted_from_value y))))
1086
+ (xor_uimm32shifted ty x y))
1087
+ (rule 4 (lower (has_type (fits_in_64 ty) (bxor (uimm32shifted_from_value x) y)))
1088
+ (xor_uimm32shifted ty y x))
1089
+
1090
+ ;; Xor a register and memory (32/64-bit types).
1091
+ (rule 1 (lower (has_type (fits_in_64 ty) (bxor x (sinkable_load_32_64 y))))
1092
+ (xor_mem ty x (sink_load y)))
1093
+ (rule 2 (lower (has_type (fits_in_64 ty) (bxor (sinkable_load_32_64 x) y)))
1094
+ (xor_mem ty y (sink_load x)))
1095
+
1096
+ ;; Xor two vector registers.
1097
+ (rule 0 (lower (has_type (vr128_ty ty) (bxor x y)))
1098
+ (vec_xor ty x y))
1099
+
1100
+ ;; Specialized lowerings for `(bxor x (bnot y))` which is additionally produced
1101
+ ;; by Cranelift's `bxor_not` instruction that is legalized into the simpler
1102
+ ;; forms early on.
1103
+
1104
+ ;; z15 version using a single instruction.
1105
+ (rule 5 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bxor x (bnot y))))
1106
+ (not_xor_reg ty x y))
1107
+ (rule 6 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bxor (bnot y) x)))
1108
+ (not_xor_reg ty x y))
1109
+
1110
+ ;; Xor-not two vector registers.
1111
+ (rule 7 (lower (has_type (vr128_ty ty) (bxor x (bnot y))))
1112
+ (vec_not_xor ty x y))
1113
+ (rule 8 (lower (has_type (vr128_ty ty) (bxor (bnot y) x)))
1114
+ (vec_not_xor ty x y))
1115
+
1116
+
1117
+ ;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1118
+
1119
+ ;; z15 version using a NAND instruction.
1120
+ (rule 2 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bitselect x y z)))
1121
+ (let ((rx Reg x)
1122
+ (if_true Reg (and_reg ty y rx))
1123
+ (if_false Reg (and_not_reg ty z rx)))
1124
+ (or_reg ty if_false if_true)))
1125
+
1126
+ ;; z14 version using XOR with -1.
1127
+ (rule 1 (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bitselect x y z)))
1128
+ (let ((rx Reg x)
1129
+ (if_true Reg (and_reg ty y rx))
1130
+ (if_false Reg (and_reg ty z (not_reg ty rx))))
1131
+ (or_reg ty if_false if_true)))
1132
+
1133
+ ;; Bitselect vector registers.
1134
+ (rule (lower (has_type (vr128_ty ty) (bitselect x y z)))
1135
+ (vec_select ty y z x))
1136
+
1137
+
1138
+ ;;;; Rules for `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1139
+
1140
+ (rule (lower (has_type ty (bmask x)))
1141
+ (lower_bool_to_mask ty (value_nonzero x)))
1142
+
1143
+
1144
+ ;;;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1145
+
1146
+ (rule (lower (has_type ty (bitrev x)))
1147
+ (bitrev_bytes ty
1148
+ (bitrev_bits 4 0xf0f0_f0f0_f0f0_f0f0 ty
1149
+ (bitrev_bits 2 0xcccc_cccc_cccc_cccc ty
1150
+ (bitrev_bits 1 0xaaaa_aaaa_aaaa_aaaa ty x)))))
1151
+
1152
+ (decl bitrev_bits (u8 u64 Type Reg) Reg)
1153
+ (rule 1 (bitrev_bits size bitmask (fits_in_64 ty) x)
1154
+ (let ((mask Reg (imm ty bitmask))
1155
+ (xh Reg (lshl_imm (ty_ext32 ty) x size))
1156
+ (xl Reg (lshr_imm (ty_ext32 ty) x size))
1157
+ (xh_masked Reg (and_reg ty xh mask))
1158
+ (xl_masked Reg (and_reg ty xl (not_reg ty mask))))
1159
+ (or_reg ty xh_masked xl_masked)))
1160
+
1161
+ (rule (bitrev_bits size bitmask (vr128_ty ty) x)
1162
+ (let ((mask Reg (vec_imm_splat $I64X2 bitmask))
1163
+ (size_reg Reg (vec_imm_splat $I8X16 (u8_as_u64 size)))
1164
+ (xh Reg (vec_lshl_by_bit x size_reg))
1165
+ (xl Reg (vec_lshr_by_bit x size_reg)))
1166
+ (vec_select ty xh xl mask)))
1167
+
1168
+ (decl bitrev_bytes (Type Reg) Reg)
1169
+ (rule (bitrev_bytes $I8 x) x)
1170
+ (rule (bitrev_bytes $I16 x) (lshr_imm $I32 (bswap_reg $I32 x) 16))
1171
+ (rule (bitrev_bytes $I32 x) (bswap_reg $I32 x))
1172
+ (rule (bitrev_bytes $I64 x) (bswap_reg $I64 x))
1173
+ (rule (bitrev_bytes $I128 x)
1174
+ (vec_permute $I128 x x
1175
+ (vec_imm $I8X16 (imm8x16 15 14 13 12 11 10 9 8
1176
+ 7 6 5 4 3 2 1 0))))
1177
+
1178
+
1179
+ ;;;; Rules for `bswap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1180
+
1181
+ (rule (lower (has_type ty (bswap x)))
1182
+ (bitrev_bytes ty x))
1183
+
1184
+ ;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1185
+
1186
+ ;; The FLOGR hardware instruction always operates on the full 64-bit register.
1187
+ ;; We can zero-extend smaller types, but then we have to compensate for the
1188
+ ;; additional leading zero bits the instruction will actually see.
1189
+ (decl clz_offset (Type Reg) Reg)
1190
+ (rule (clz_offset $I8 x) (add_simm16 $I8 x -56))
1191
+ (rule (clz_offset $I16 x) (add_simm16 $I16 x -48))
1192
+ (rule (clz_offset $I32 x) (add_simm16 $I32 x -32))
1193
+ (rule (clz_offset $I64 x) x)
1194
+
1195
+ ;; Count leading zeros, via FLOGR on an input zero-extended to 64 bits,
1196
+ ;; with the result compensated for the extra bits.
1197
+ (rule 1 (lower (has_type (fits_in_64 ty) (clz x)))
1198
+ (let ((ext_reg Reg (put_in_reg_zext64 x))
1199
+ ;; Ask for a value of 64 in the all-zero 64-bit input case.
1200
+ ;; After compensation this will match the expected semantics.
1201
+ (clz Reg (clz_reg 64 ext_reg)))
1202
+ (clz_offset ty clz)))
1203
+
1204
+ ;; Count leading zeros, 128-bit full vector.
1205
+ (rule (lower (has_type $I128 (clz x)))
1206
+ (let ((clz_vec Reg (vec_clz $I64X2 x))
1207
+ (zero Reg (vec_imm $I64X2 0))
1208
+ (clz_hi Reg (vec_permute_dw_imm $I64X2 zero 0 clz_vec 0))
1209
+ (clz_lo Reg (vec_permute_dw_imm $I64X2 zero 0 clz_vec 1))
1210
+ (clz_sum Reg (vec_add $I64X2 clz_hi clz_lo))
1211
+ (mask Reg (vec_cmpeq $I64X2 clz_hi (vec_imm_splat $I64X2 64))))
1212
+ (vec_select $I128 clz_sum clz_hi mask)))
1213
+
1214
+
1215
+ ;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1216
+
1217
+ ;; The result of cls is not supposed to count the sign bit itself, just
1218
+ ;; additional copies of it. Therefore, when computing cls in terms of clz,
1219
+ ;; we need to subtract one. Fold this into the offset computation.
1220
+ (decl cls_offset (Type Reg) Reg)
1221
+ (rule (cls_offset $I8 x) (add_simm16 $I8 x -57))
1222
+ (rule (cls_offset $I16 x) (add_simm16 $I16 x -49))
1223
+ (rule (cls_offset $I32 x) (add_simm16 $I32 x -33))
1224
+ (rule (cls_offset $I64 x) (add_simm16 $I64 x -1))
1225
+
1226
+ ;; Count leading sign-bit copies. We don't have any instruction for that,
1227
+ ;; so we instead count the leading zeros after inverting the input if negative,
1228
+ ;; i.e. computing
1229
+ ;; cls(x) == clz(x ^ (x >> 63)) - 1
1230
+ ;; where x is the sign-extended input.
1231
+ (rule 1 (lower (has_type (fits_in_64 ty) (cls x)))
1232
+ (let ((ext_reg Reg (put_in_reg_sext64 x))
1233
+ (signbit_copies Reg (ashr_imm $I64 ext_reg 63))
1234
+ (inv_reg Reg (xor_reg $I64 ext_reg signbit_copies))
1235
+ (clz Reg (clz_reg 64 inv_reg)))
1236
+ (cls_offset ty clz)))
1237
+
1238
+ ;; Count leading sign-bit copies, 128-bit full vector.
1239
+ (rule (lower (has_type $I128 (cls x)))
1240
+ (let ((x_reg Reg x)
1241
+ (ones Reg (vec_imm_splat $I8X16 255))
1242
+ (signbit_copies Reg (vec_ashr_by_bit (vec_ashr_by_byte x_reg ones) ones))
1243
+ (inv_reg Reg (vec_xor $I128 x_reg signbit_copies))
1244
+ (clz_vec Reg (vec_clz $I64X2 inv_reg))
1245
+ (zero Reg (vec_imm $I64X2 0))
1246
+ (clz_hi Reg (vec_permute_dw_imm $I64X2 zero 0 clz_vec 0))
1247
+ (clz_lo Reg (vec_permute_dw_imm $I64X2 zero 0 clz_vec 1))
1248
+ (clz_sum Reg (vec_add $I64X2 clz_hi clz_lo))
1249
+ (mask Reg (vec_cmpeq $I64X2 clz_hi (vec_imm_splat $I64X2 64))))
1250
+ (vec_add $I128 (vec_select $I128 clz_sum clz_hi mask) ones)))
1251
+
1252
+
1253
+ ;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1254
+
1255
+ ;; To count trailing zeros, we find the last bit set in the input via (x & -x),
1256
+ ;; count the leading zeros of that value, and subtract from 63:
1257
+ ;;
1258
+ ;; ctz(x) == 63 - clz(x & -x)
1259
+ ;;
1260
+ ;; This works for all cases except a zero input, where the above formula would
1261
+ ;; return -1, but we are expected to return the type size. The compensation
1262
+ ;; for this case is handled differently for 64-bit types vs. smaller types.
1263
+
1264
+ ;; For smaller types, we simply ensure that the extended 64-bit input is
1265
+ ;; never zero by setting a "guard bit" in the position corresponding to
1266
+ ;; the input type size. This way the 64-bit algorithm above will handle
1267
+ ;; that case correctly automatically.
1268
+ (rule 2 (lower (has_type (gpr32_ty ty) (ctz x)))
1269
+ (let ((rx Reg (or_uimm16shifted $I64 x (ctz_guardbit ty)))
1270
+ (lastbit Reg (and_reg $I64 rx (neg_reg $I64 rx)))
1271
+ (clz Reg (clz_reg 64 lastbit)))
1272
+ (sub_reg ty (imm ty 63) clz)))
1273
+
1274
+ (decl ctz_guardbit (Type) UImm16Shifted)
1275
+ (rule (ctz_guardbit $I8) (uimm16shifted 256 0))
1276
+ (rule (ctz_guardbit $I16) (uimm16shifted 1 16))
1277
+ (rule (ctz_guardbit $I32) (uimm16shifted 1 32))
1278
+
1279
+ ;; For 64-bit types, the FLOGR instruction will indicate the zero input case
1280
+ ;; via its condition code. We check for that and replace the instruction
1281
+ ;; result with the value -1 via a conditional move, which will then lead to
1282
+ ;; the correct result after the final subtraction from 63.
1283
+ (rule 1 (lower (has_type (gpr64_ty _ty) (ctz x)))
1284
+ (let ((rx Reg x)
1285
+ (lastbit Reg (and_reg $I64 rx (neg_reg $I64 rx)))
1286
+ (clz Reg (clz_reg -1 lastbit)))
1287
+ (sub_reg $I64 (imm $I64 63) clz)))
1288
+
1289
+ ;; Count trailing zeros, 128-bit full vector.
1290
+ (rule 0 (lower (has_type $I128 (ctz x)))
1291
+ (let ((ctz_vec Reg (vec_ctz $I64X2 x))
1292
+ (zero Reg (vec_imm $I64X2 0))
1293
+ (ctz_hi Reg (vec_permute_dw_imm $I64X2 zero 0 ctz_vec 0))
1294
+ (ctz_lo Reg (vec_permute_dw_imm $I64X2 zero 0 ctz_vec 1))
1295
+ (ctz_sum Reg (vec_add $I64X2 ctz_hi ctz_lo))
1296
+ (mask Reg (vec_cmpeq $I64X2 ctz_lo (vec_imm_splat $I64X2 64))))
1297
+ (vec_select $I128 ctz_sum ctz_lo mask)))
1298
+
1299
+
1300
+ ;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1301
+
1302
+ ;; Population count for 8-bit types is supported by the POPCNT instruction.
1303
+ (rule (lower (has_type $I8 (popcnt x)))
1304
+ (popcnt_byte x))
1305
+
1306
+ ;; On z15, the POPCNT instruction has a variant to compute a full 64-bit
1307
+ ;; population count, which we also use for 16- and 32-bit types.
1308
+ (rule -1 (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (popcnt x)))
1309
+ (popcnt_reg (put_in_reg_zext64 x)))
1310
+
1311
+ ;; On z14, we use the regular POPCNT, which computes the population count
1312
+ ;; of each input byte separately, so we need to accumulate those partial
1313
+ ;; results via a series of log2(type size in bytes) - 1 additions. We
1314
+ ;; accumulate in the high byte, so that a final right shift will zero out
1315
+ ;; any unrelated bits to give a clean result. (This does not work with
1316
+ ;; $I16, where we instead accumulate in the low byte and clear high bits
1317
+ ;; via an explicit and operation.)
1318
+
1319
+ (rule (lower (has_type (and (mie2_disabled) $I16) (popcnt x)))
1320
+ (let ((cnt2 Reg (popcnt_byte x))
1321
+ (cnt1 Reg (add_reg $I32 cnt2 (lshr_imm $I32 cnt2 8))))
1322
+ (and_uimm16shifted $I32 cnt1 (uimm16shifted 255 0))))
1323
+
1324
+ (rule (lower (has_type (and (mie2_disabled) $I32) (popcnt x)))
1325
+ (let ((cnt4 Reg (popcnt_byte x))
1326
+ (cnt2 Reg (add_reg $I32 cnt4 (lshl_imm $I32 cnt4 16)))
1327
+ (cnt1 Reg (add_reg $I32 cnt2 (lshl_imm $I32 cnt2 8))))
1328
+ (lshr_imm $I32 cnt1 24)))
1329
+
1330
+ (rule (lower (has_type (and (mie2_disabled) $I64) (popcnt x)))
1331
+ (let ((cnt8 Reg (popcnt_byte x))
1332
+ (cnt4 Reg (add_reg $I64 cnt8 (lshl_imm $I64 cnt8 32)))
1333
+ (cnt2 Reg (add_reg $I64 cnt4 (lshl_imm $I64 cnt4 16)))
1334
+ (cnt1 Reg (add_reg $I64 cnt2 (lshl_imm $I64 cnt2 8))))
1335
+ (lshr_imm $I64 cnt1 56)))
1336
+
1337
+ ;; Population count for vector types.
1338
+ (rule 1 (lower (has_type (ty_vec128 ty) (popcnt x)))
1339
+ (vec_popcnt ty x))
1340
+
1341
+ ;; Population count, 128-bit full vector.
1342
+ (rule (lower (has_type $I128 (popcnt x)))
1343
+ (let ((popcnt_vec Reg (vec_popcnt $I64X2 x))
1344
+ (zero Reg (vec_imm $I64X2 0))
1345
+ (popcnt_hi Reg (vec_permute_dw_imm $I64X2 zero 0 popcnt_vec 0))
1346
+ (popcnt_lo Reg (vec_permute_dw_imm $I64X2 zero 0 popcnt_vec 1)))
1347
+ (vec_add $I64X2 popcnt_hi popcnt_lo)))
1348
+
1349
+
1350
+ ;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1351
+
1352
+ ;; Add two registers.
1353
+ (rule (lower (has_type ty (fadd x y)))
1354
+ (fadd_reg ty x y))
1355
+
1356
+
1357
+ ;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1358
+
1359
+ ;; Subtract two registers.
1360
+ (rule (lower (has_type ty (fsub x y)))
1361
+ (fsub_reg ty x y))
1362
+
1363
+
1364
+ ;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1365
+
1366
+ ;; Multiply two registers.
1367
+ (rule (lower (has_type ty (fmul x y)))
1368
+ (fmul_reg ty x y))
1369
+
1370
+
1371
+ ;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1372
+
1373
+ ;; Divide two registers.
1374
+ (rule (lower (has_type ty (fdiv x y)))
1375
+ (fdiv_reg ty x y))
1376
+
1377
+
1378
+ ;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1379
+
1380
+ ;; Minimum of two registers.
1381
+ (rule (lower (has_type ty (fmin x y)))
1382
+ (fmin_reg ty x y))
1383
+
1384
+
1385
+ ;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1386
+
1387
+ ;; Maximum of two registers.
1388
+ (rule (lower (has_type ty (fmax x y)))
1389
+ (fmax_reg ty x y))
1390
+
1391
+
1392
+ ;;;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1393
+
1394
+ ;; Minimum of two registers.
1395
+ (rule (lower (has_type ty (fmin_pseudo x y)))
1396
+ (fmin_pseudo_reg ty x y))
1397
+
1398
+
1399
+ ;;;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1400
+
1401
+ ;; Maximum of two registers.
1402
+ (rule (lower (has_type ty (fmax_pseudo x y)))
1403
+ (fmax_pseudo_reg ty x y))
1404
+
1405
+
1406
+ ;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1407
+
1408
+ ;; Copysign of two registers.
1409
+ (rule (lower (has_type $F32 (fcopysign x y)))
1410
+ (vec_select $F32 x y (imm $F32 2147483647)))
1411
+ (rule (lower (has_type $F64 (fcopysign x y)))
1412
+ (vec_select $F64 x y (imm $F64 9223372036854775807)))
1413
+ (rule (lower (has_type $F32X4 (fcopysign x y)))
1414
+ (vec_select $F32X4 x y (vec_imm_bit_mask $F32X4 1 31)))
1415
+ (rule (lower (has_type $F64X2 (fcopysign x y)))
1416
+ (vec_select $F64X2 x y (vec_imm_bit_mask $F64X2 1 63)))
1417
+
1418
+
1419
+ ;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1420
+
1421
+ ;; Multiply-and-add of three registers.
1422
+ (rule (lower (has_type ty (fma x y z)))
1423
+ (fma_reg ty x y z))
1424
+
1425
+
1426
+ ;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1427
+
1428
+ ;; Square root of a register.
1429
+ (rule (lower (has_type ty (sqrt x)))
1430
+ (sqrt_reg ty x))
1431
+
1432
+
1433
+ ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1434
+
1435
+ ;; Negated value of a register.
1436
+ (rule (lower (has_type ty (fneg x)))
1437
+ (fneg_reg ty x))
1438
+
1439
+
1440
+ ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1441
+
1442
+ ;; Absolute value of a register.
1443
+ (rule (lower (has_type ty (fabs x)))
1444
+ (fabs_reg ty x))
1445
+
1446
+
1447
+ ;;;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1448
+
1449
+ ;; Round value in a register towards positive infinity.
1450
+ (rule (lower (has_type ty (ceil x)))
1451
+ (ceil_reg ty x))
1452
+
1453
+
1454
+ ;;;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1455
+
1456
+ ;; Round value in a register towards negative infinity.
1457
+ (rule (lower (has_type ty (floor x)))
1458
+ (floor_reg ty x))
1459
+
1460
+
1461
+ ;;;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1462
+
1463
+ ;; Round value in a register towards zero.
1464
+ (rule (lower (has_type ty (trunc x)))
1465
+ (trunc_reg ty x))
1466
+
1467
+
1468
+ ;;;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1469
+
1470
+ ;; Round value in a register towards nearest.
1471
+ (rule (lower (has_type ty (nearest x)))
1472
+ (nearest_reg ty x))
1473
+
1474
+
1475
+ ;;;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1476
+
1477
+ ;; Promote a register.
1478
+ (rule (lower (has_type (fits_in_64 dst_ty) (fpromote x @ (value_type src_ty))))
1479
+ (fpromote_reg dst_ty src_ty x))
1480
+
1481
+
1482
+ ;;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1483
+
1484
+ ;; Promote a register.
1485
+ (rule (lower (has_type $F64X2 (fvpromote_low x @ (value_type $F32X4))))
1486
+ (fpromote_reg $F64X2 $F32X4 (vec_merge_low_lane_order $I32X4 x x)))
1487
+
1488
+
1489
+ ;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1490
+
1491
+ ;; Demote a register.
1492
+ (rule (lower (has_type (fits_in_64 dst_ty) (fdemote x @ (value_type src_ty))))
1493
+ (fdemote_reg dst_ty src_ty (FpuRoundMode.Current) x))
1494
+
1495
+
1496
+ ;;;; Rules for `fvdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1497
+
1498
+ ;; Demote a register.
1499
+ (rule (lower (has_type $F32X4 (fvdemote x @ (value_type $F64X2))))
1500
+ (let ((dst Reg (fdemote_reg $F32X4 $F64X2 (FpuRoundMode.Current) x)))
1501
+ (vec_pack_lane_order $I64X2 (vec_lshr_imm $I64X2 dst 32)
1502
+ (vec_imm $I64X2 0))))
1503
+
1504
+
1505
+ ;;;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1506
+
1507
+ ;; Convert a 32-bit or smaller unsigned integer to $F32 (z15 instruction).
1508
+ (rule 1 (lower (has_type $F32
1509
+ (fcvt_from_uint x @ (value_type (and (vxrs_ext2_enabled) (fits_in_32 ty))))))
1510
+ (fcvt_from_uint_reg $F32 (FpuRoundMode.ToNearestTiesToEven)
1511
+ (put_in_reg_zext32 x)))
1512
+
1513
+ ;; Convert a 64-bit or smaller unsigned integer to $F32, via an intermediate $F64.
1514
+ (rule (lower (has_type $F32 (fcvt_from_uint x @ (value_type (fits_in_64 ty)))))
1515
+ (fdemote_reg $F32 $F64 (FpuRoundMode.ToNearestTiesToEven)
1516
+ (fcvt_from_uint_reg $F64 (FpuRoundMode.ShorterPrecision)
1517
+ (put_in_reg_zext64 x))))
1518
+
1519
+ ;; Convert a 64-bit or smaller unsigned integer to $F64.
1520
+ (rule (lower (has_type $F64 (fcvt_from_uint x @ (value_type (fits_in_64 ty)))))
1521
+ (fcvt_from_uint_reg $F64 (FpuRoundMode.ToNearestTiesToEven)
1522
+ (put_in_reg_zext64 x)))
1523
+
1524
+ ;; Convert $I32X4 to $F32X4 (z15 instruction).
1525
+ (rule 1 (lower (has_type (and (vxrs_ext2_enabled) $F32X4)
1526
+ (fcvt_from_uint x @ (value_type $I32X4))))
1527
+ (fcvt_from_uint_reg $F32X4 (FpuRoundMode.ToNearestTiesToEven) x))
1528
+
1529
+ ;; Convert $I32X4 to $F32X4 (via two $F64X2 on z14).
1530
+ (rule (lower (has_type (and (vxrs_ext2_disabled) $F32X4)
1531
+ (fcvt_from_uint x @ (value_type $I32X4))))
1532
+ (vec_permute $F32X4
1533
+ (fdemote_reg $F32X4 $F64X2 (FpuRoundMode.ToNearestTiesToEven)
1534
+ (fcvt_from_uint_reg $F64X2 (FpuRoundMode.ShorterPrecision)
1535
+ (vec_unpacku_high $I32X4 x)))
1536
+ (fdemote_reg $F32X4 $F64X2 (FpuRoundMode.ToNearestTiesToEven)
1537
+ (fcvt_from_uint_reg $F64X2 (FpuRoundMode.ShorterPrecision)
1538
+ (vec_unpacku_low $I32X4 x)))
1539
+ (vec_imm $I8X16 (imm8x16 0 1 2 3 8 9 10 11 16 17 18 19 24 25 26 27))))
1540
+
1541
+ ;; Convert $I64X2 to $F64X2.
1542
+ (rule (lower (has_type $F64X2 (fcvt_from_uint x @ (value_type $I64X2))))
1543
+ (fcvt_from_uint_reg $F64X2 (FpuRoundMode.ToNearestTiesToEven) x))
1544
+
1545
+
1546
+ ;;;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1547
+
1548
+ ;; Convert a 32-bit or smaller signed integer to $F32 (z15 instruction).
1549
+ (rule 1 (lower (has_type $F32
1550
+ (fcvt_from_sint x @ (value_type (and (vxrs_ext2_enabled) (fits_in_32 ty))))))
1551
+ (fcvt_from_sint_reg $F32 (FpuRoundMode.ToNearestTiesToEven)
1552
+ (put_in_reg_sext32 x)))
1553
+
1554
+ ;; Convert a 64-bit or smaller signed integer to $F32, via an intermediate $F64.
1555
+ (rule (lower (has_type $F32 (fcvt_from_sint x @ (value_type (fits_in_64 ty)))))
1556
+ (fdemote_reg $F32 $F64 (FpuRoundMode.ToNearestTiesToEven)
1557
+ (fcvt_from_sint_reg $F64 (FpuRoundMode.ShorterPrecision)
1558
+ (put_in_reg_sext64 x))))
1559
+
1560
+ ;; Convert a 64-bit or smaller signed integer to $F64.
1561
+ (rule (lower (has_type $F64 (fcvt_from_sint x @ (value_type (fits_in_64 ty)))))
1562
+ (fcvt_from_sint_reg $F64 (FpuRoundMode.ToNearestTiesToEven)
1563
+ (put_in_reg_sext64 x)))
1564
+
1565
+ ;; Convert $I32X4 to $F32X4 (z15 instruction).
1566
+ (rule 1 (lower (has_type (and (vxrs_ext2_enabled) $F32X4)
1567
+ (fcvt_from_sint x @ (value_type $I32X4))))
1568
+ (fcvt_from_sint_reg $F32X4 (FpuRoundMode.ToNearestTiesToEven) x))
1569
+
1570
+ ;; Convert $I32X4 to $F32X4 (via two $F64X2 on z14).
1571
+ (rule (lower (has_type (and (vxrs_ext2_disabled) $F32X4)
1572
+ (fcvt_from_sint x @ (value_type $I32X4))))
1573
+ (vec_permute $F32X4
1574
+ (fdemote_reg $F32X4 $F64X2 (FpuRoundMode.ToNearestTiesToEven)
1575
+ (fcvt_from_sint_reg $F64X2 (FpuRoundMode.ShorterPrecision)
1576
+ (vec_unpacks_high $I32X4 x)))
1577
+ (fdemote_reg $F32X4 $F64X2 (FpuRoundMode.ToNearestTiesToEven)
1578
+ (fcvt_from_sint_reg $F64X2 (FpuRoundMode.ShorterPrecision)
1579
+ (vec_unpacks_low $I32X4 x)))
1580
+ (vec_imm $I8X16 (imm8x16 0 1 2 3 8 9 10 11 16 17 18 19 24 25 26 27))))
1581
+
1582
+ ;; Convert $I64X2 to $F64X2.
1583
+ (rule (lower (has_type $F64X2 (fcvt_from_sint x @ (value_type $I64X2))))
1584
+ (fcvt_from_sint_reg $F64X2 (FpuRoundMode.ToNearestTiesToEven) x))
1585
+
1586
+
1587
+ ;;;; Rules for `fcvt_low_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1588
+
1589
+ ;; Convert the low half of a $I32X4 to a $F64X2.
1590
+ (rule (lower (has_type $F64X2 (fcvt_low_from_sint x @ (value_type $I32X4))))
1591
+ (fcvt_from_sint_reg $F64X2 (FpuRoundMode.ToNearestTiesToEven)
1592
+ (vec_unpacks_low_lane_order $I32X4 x)))
1593
+
1594
+
1595
+ ;;;; Rules for `fcvt_to_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1596
+
1597
+ ;; Convert a scalar floating-point value in a register to an unsigned integer.
1598
+ ;; Traps if the input cannot be represented in the output type.
1599
+ (rule (lower (has_type (fits_in_64 dst_ty)
1600
+ (fcvt_to_uint x @ (value_type src_ty))))
1601
+ (let ((src Reg (put_in_reg x))
1602
+ ;; First, check whether the input is a NaN, and trap if so.
1603
+ (_ Reg (trap_if (fcmp_reg src_ty src src)
1604
+ (floatcc_as_cond (FloatCC.Unordered))
1605
+ (trap_code_bad_conversion_to_integer)))
1606
+ ;; Now check whether the input is out of range for the target type.
1607
+ (_ Reg (trap_if (fcmp_reg src_ty src (fcvt_to_uint_ub src_ty dst_ty))
1608
+ (floatcc_as_cond (FloatCC.GreaterThanOrEqual))
1609
+ (trap_code_integer_overflow)))
1610
+ (_ Reg (trap_if (fcmp_reg src_ty src (fcvt_to_uint_lb src_ty))
1611
+ (floatcc_as_cond (FloatCC.LessThanOrEqual))
1612
+ (trap_code_integer_overflow)))
1613
+ ;; Perform the conversion using the larger type size.
1614
+ (flt_ty Type (fcvt_flt_ty dst_ty src_ty))
1615
+ (src_ext Reg (fpromote_reg flt_ty src_ty src)))
1616
+ (fcvt_to_uint_reg flt_ty (FpuRoundMode.ToZero) src_ext)))
1617
+
1618
+
1619
+ ;;;; Rules for `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1620
+
1621
+ ;; Convert a scalar floating-point value in a register to a signed integer.
1622
+ ;; Traps if the input cannot be represented in the output type.
1623
+ (rule (lower (has_type (fits_in_64 dst_ty)
1624
+ (fcvt_to_sint x @ (value_type src_ty))))
1625
+ (let ((src Reg (put_in_reg x))
1626
+ ;; First, check whether the input is a NaN, and trap if so.
1627
+ (_ Reg (trap_if (fcmp_reg src_ty src src)
1628
+ (floatcc_as_cond (FloatCC.Unordered))
1629
+ (trap_code_bad_conversion_to_integer)))
1630
+ ;; Now check whether the input is out of range for the target type.
1631
+ (_ Reg (trap_if (fcmp_reg src_ty src (fcvt_to_sint_ub src_ty dst_ty))
1632
+ (floatcc_as_cond (FloatCC.GreaterThanOrEqual))
1633
+ (trap_code_integer_overflow)))
1634
+ (_ Reg (trap_if (fcmp_reg src_ty src (fcvt_to_sint_lb src_ty dst_ty))
1635
+ (floatcc_as_cond (FloatCC.LessThanOrEqual))
1636
+ (trap_code_integer_overflow)))
1637
+ ;; Perform the conversion using the larger type size.
1638
+ (flt_ty Type (fcvt_flt_ty dst_ty src_ty))
1639
+ (src_ext Reg (fpromote_reg flt_ty src_ty src)))
1640
+ ;; Perform the conversion.
1641
+ (fcvt_to_sint_reg flt_ty (FpuRoundMode.ToZero) src_ext)))
1642
+
1643
+
1644
+ ;;;; Rules for `fcvt_to_uint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1645
+
1646
+ ;; Convert a scalar floating-point value in a register to an unsigned integer.
1647
+ (rule -1 (lower (has_type (fits_in_64 dst_ty)
1648
+ (fcvt_to_uint_sat x @ (value_type src_ty))))
1649
+ (let ((src Reg (put_in_reg x))
1650
+ ;; Perform the conversion using the larger type size.
1651
+ (flt_ty Type (fcvt_flt_ty dst_ty src_ty))
1652
+ (int_ty Type (fcvt_int_ty dst_ty src_ty))
1653
+ (src_ext Reg (fpromote_reg flt_ty src_ty src))
1654
+ (dst Reg (fcvt_to_uint_reg flt_ty (FpuRoundMode.ToZero) src_ext)))
1655
+ ;; Clamp the output to the destination type bounds.
1656
+ (uint_sat_reg dst_ty int_ty dst)))
1657
+
1658
+ ;; Convert $F32X4 to $I32X4 (z15 instruction).
1659
+ (rule 1 (lower (has_type (and (vxrs_ext2_enabled) $I32X4)
1660
+ (fcvt_to_uint_sat x @ (value_type $F32X4))))
1661
+ (fcvt_to_uint_reg $F32X4 (FpuRoundMode.ToZero) x))
1662
+
1663
+ ;; Convert $F32X4 to $I32X4 (via two $F64X2 on z14).
1664
+ (rule (lower (has_type (and (vxrs_ext2_disabled) $I32X4)
1665
+ (fcvt_to_uint_sat x @ (value_type $F32X4))))
1666
+ (vec_pack_usat $I64X2
1667
+ (fcvt_to_uint_reg $F64X2 (FpuRoundMode.ToZero)
1668
+ (fpromote_reg $F64X2 $F32X4 (vec_merge_high $I32X4 x x)))
1669
+ (fcvt_to_uint_reg $F64X2 (FpuRoundMode.ToZero)
1670
+ (fpromote_reg $F64X2 $F32X4 (vec_merge_low $I32X4 x x)))))
1671
+
1672
+ ;; Convert $F64X2 to $I64X2.
1673
+ (rule (lower (has_type $I64X2 (fcvt_to_uint_sat x @ (value_type $F64X2))))
1674
+ (fcvt_to_uint_reg $F64X2 (FpuRoundMode.ToZero) x))
1675
+
1676
+
1677
+ ;;;; Rules for `fcvt_to_sint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1678
+
1679
+ ;; Convert a scalar floating-point value in a register to a signed integer.
1680
+ (rule -1 (lower (has_type (fits_in_64 dst_ty)
1681
+ (fcvt_to_sint_sat x @ (value_type src_ty))))
1682
+ (let ((src Reg (put_in_reg x))
1683
+ ;; Perform the conversion using the larger type size.
1684
+ (flt_ty Type (fcvt_flt_ty dst_ty src_ty))
1685
+ (int_ty Type (fcvt_int_ty dst_ty src_ty))
1686
+ (src_ext Reg (fpromote_reg flt_ty src_ty src))
1687
+ (dst Reg (fcvt_to_sint_reg flt_ty (FpuRoundMode.ToZero) src_ext))
1688
+ ;; In most special cases, the Z instruction already yields the
1689
+ ;; result expected by Cranelift semantics. The only exception
1690
+ ;; it the case where the input was a NaN. We explicitly check
1691
+ ;; for that and force the output to 0 in that case.
1692
+ (sat Reg (with_flags_reg (fcmp_reg src_ty src src)
1693
+ (cmov_imm int_ty
1694
+ (floatcc_as_cond (FloatCC.Unordered)) 0 dst))))
1695
+ ;; Clamp the output to the destination type bounds.
1696
+ (sint_sat_reg dst_ty int_ty sat)))
1697
+
1698
+ ;; Convert $F32X4 to $I32X4 (z15 instruction).
1699
+ (rule 1 (lower (has_type (and (vxrs_ext2_enabled) $I32X4)
1700
+ (fcvt_to_sint_sat src @ (value_type $F32X4))))
1701
+ ;; See above for why we need to handle NaNs specially.
1702
+ (vec_select $I32X4
1703
+ (fcvt_to_sint_reg $F32X4 (FpuRoundMode.ToZero) src)
1704
+ (vec_imm $I32X4 0) (vec_fcmpeq $F32X4 src src)))
1705
+
1706
+ ;; Convert $F32X4 to $I32X4 (via two $F64X2 on z14).
1707
+ (rule (lower (has_type (and (vxrs_ext2_disabled) $I32X4)
1708
+ (fcvt_to_sint_sat src @ (value_type $F32X4))))
1709
+ ;; See above for why we need to handle NaNs specially.
1710
+ (vec_select $I32X4
1711
+ (vec_pack_ssat $I64X2
1712
+ (fcvt_to_sint_reg $F64X2 (FpuRoundMode.ToZero)
1713
+ (fpromote_reg $F64X2 $F32X4 (vec_merge_high $I32X4 src src)))
1714
+ (fcvt_to_sint_reg $F64X2 (FpuRoundMode.ToZero)
1715
+ (fpromote_reg $F64X2 $F32X4 (vec_merge_low $I32X4 src src))))
1716
+ (vec_imm $I32X4 0) (vec_fcmpeq $F32X4 src src)))
1717
+
1718
+ ;; Convert $F64X2 to $I64X2.
1719
+ (rule (lower (has_type $I64X2 (fcvt_to_sint_sat src @ (value_type $F64X2))))
1720
+ ;; See above for why we need to handle NaNs specially.
1721
+ (vec_select $I64X2
1722
+ (fcvt_to_sint_reg $F64X2 (FpuRoundMode.ToZero) src)
1723
+ (vec_imm $I64X2 0) (vec_fcmpeq $F64X2 src src)))
1724
+
1725
+
1726
+ ;;;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1727
+
1728
+ ;; Reinterpret a 64-bit integer value as floating-point.
1729
+ (rule (lower (has_type $F64 (bitcast _ x @ (value_type $I64))))
1730
+ (vec_insert_lane_undef $F64X2 x 0 (zero_reg)))
1731
+
1732
+ ;; Reinterpret a 64-bit floating-point value as integer.
1733
+ (rule (lower (has_type $I64 (bitcast _ x @ (value_type $F64))))
1734
+ (vec_extract_lane $F64X2 x 0 (zero_reg)))
1735
+
1736
+ ;; Reinterpret a 32-bit integer value as floating-point.
1737
+ (rule (lower (has_type $F32 (bitcast _ x @ (value_type $I32))))
1738
+ (vec_insert_lane_undef $F32X4 x 0 (zero_reg)))
1739
+
1740
+ ;; Reinterpret a 32-bit floating-point value as integer.
1741
+ (rule (lower (has_type $I32 (bitcast _ x @ (value_type $F32))))
1742
+ (vec_extract_lane $F32X4 x 0 (zero_reg)))
1743
+
1744
+ ;; Bitcast between types residing in GPRs is a no-op.
1745
+ (rule 1 (lower (has_type (gpr32_ty _)
1746
+ (bitcast _ x @ (value_type (gpr32_ty _))))) x)
1747
+ (rule 2 (lower (has_type (gpr64_ty _)
1748
+ (bitcast _ x @ (value_type (gpr64_ty _))))) x)
1749
+
1750
+ ;; Bitcast between types residing in FPRs is a no-op.
1751
+ (rule 3 (lower (has_type (ty_scalar_float _)
1752
+ (bitcast _ x @ (value_type (ty_scalar_float _))))) x)
1753
+
1754
+ ;; Bitcast between types residing in VRs is a no-op if lane count is unchanged.
1755
+ (rule 5 (lower (has_type (multi_lane bits count)
1756
+ (bitcast _ x @ (value_type (multi_lane bits count))))) x)
1757
+
1758
+ ;; Bitcast between types residing in VRs with different lane counts is a
1759
+ ;; no-op if the operation's MemFlags indicate a byte order compatible with
1760
+ ;; the current lane order. Otherwise, lane elements need to be swapped,
1761
+ ;; first in the input type, and then again in the output type. This could
1762
+ ;; be optimized further, but we don't bother at the moment since due to our
1763
+ ;; choice of lane order depending on the current function ABI, this case will
1764
+ ;; currently never arise in practice.
1765
+ (rule 4 (lower (has_type (vr128_ty out_ty)
1766
+ (bitcast flags x @ (value_type (vr128_ty in_ty)))))
1767
+ (abi_vec_elt_rev (lane_order_from_memflags flags) out_ty
1768
+ (abi_vec_elt_rev (lane_order_from_memflags flags) in_ty x)))
1769
+
1770
+
1771
+ ;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1772
+
1773
+ ;; Insert vector lane from general-purpose register.
1774
+ (rule 1 (lower (insertlane x @ (value_type ty)
1775
+ y @ (value_type in_ty)
1776
+ (u8_from_uimm8 idx)))
1777
+ (if (ty_int_ref_scalar_64 in_ty))
1778
+ (vec_insert_lane ty x y (be_lane_idx ty idx) (zero_reg)))
1779
+
1780
+ ;; Insert vector lane from floating-point register.
1781
+ (rule 0 (lower (insertlane x @ (value_type ty)
1782
+ y @ (value_type (ty_scalar_float _))
1783
+ (u8_from_uimm8 idx)))
1784
+ (vec_move_lane_and_insert ty x (be_lane_idx ty idx) y 0))
1785
+
1786
+ ;; Insert vector lane from another vector lane.
1787
+ (rule 2 (lower (insertlane x @ (value_type ty)
1788
+ (extractlane y (u8_from_uimm8 src_idx))
1789
+ (u8_from_uimm8 dst_idx)))
1790
+ (vec_move_lane_and_insert ty x (be_lane_idx ty dst_idx)
1791
+ y (be_lane_idx ty src_idx)))
1792
+
1793
+ ;; Insert vector lane from signed 16-bit immediate.
1794
+ (rule 3 (lower (insertlane x @ (value_type ty) (i16_from_value y)
1795
+ (u8_from_uimm8 idx)))
1796
+ (vec_insert_lane_imm ty x y (be_lane_idx ty idx)))
1797
+
1798
+ ;; Insert vector lane from big-endian memory.
1799
+ (rule 4 (lower (insertlane x @ (value_type ty) (sinkable_load y)
1800
+ (u8_from_uimm8 idx)))
1801
+ (vec_load_lane ty x (sink_load y) (be_lane_idx ty idx)))
1802
+
1803
+ ;; Insert vector lane from little-endian memory.
1804
+ (rule 5 (lower (insertlane x @ (value_type ty) (sinkable_load_little y)
1805
+ (u8_from_uimm8 idx)))
1806
+ (vec_load_lane_little ty x (sink_load y) (be_lane_idx ty idx)))
1807
+
1808
+
1809
+ ;; Helper to extract one lane from a vector and insert it into another.
1810
+ (decl vec_move_lane_and_insert (Type Reg u8 Reg u8) Reg)
1811
+
1812
+ ;; For 64-bit elements we always use VPDI.
1813
+ (rule (vec_move_lane_and_insert ty @ (multi_lane 64 _) dst 0 src src_idx)
1814
+ (vec_permute_dw_imm ty src src_idx dst 1))
1815
+ (rule (vec_move_lane_and_insert ty @ (multi_lane 64 _) dst 1 src src_idx)
1816
+ (vec_permute_dw_imm ty dst 0 src src_idx))
1817
+
1818
+ ;; If source and destination index are the same, use vec_select.
1819
+ (rule -1 (vec_move_lane_and_insert ty dst idx src idx)
1820
+ (vec_select ty src
1821
+ dst (vec_imm_byte_mask ty (lane_byte_mask ty idx))))
1822
+
1823
+ ;; Otherwise replicate source first and then use vec_select.
1824
+ (rule -2 (vec_move_lane_and_insert ty dst dst_idx src src_idx)
1825
+ (vec_select ty (vec_replicate_lane ty src src_idx)
1826
+ dst (vec_imm_byte_mask ty (lane_byte_mask ty dst_idx))))
1827
+
1828
+
1829
+ ;; Helper to implement a generic little-endian variant of vec_load_lane.
1830
+ (decl vec_load_lane_little (Type Reg MemArg u8) Reg)
1831
+
1832
+ ;; 8-byte little-endian loads can be performed via a normal load.
1833
+ (rule (vec_load_lane_little ty @ (multi_lane 8 _) dst addr lane_imm)
1834
+ (vec_load_lane ty dst addr lane_imm))
1835
+
1836
+ ;; On z15, we have instructions to perform little-endian loads.
1837
+ (rule 1 (vec_load_lane_little (and (vxrs_ext2_enabled)
1838
+ ty @ (multi_lane 16 _)) dst addr lane_imm)
1839
+ (vec_load_lane_rev ty dst addr lane_imm))
1840
+ (rule 1 (vec_load_lane_little (and (vxrs_ext2_enabled)
1841
+ ty @ (multi_lane 32 _)) dst addr lane_imm)
1842
+ (vec_load_lane_rev ty dst addr lane_imm))
1843
+ (rule 1 (vec_load_lane_little (and (vxrs_ext2_enabled)
1844
+ ty @ (multi_lane 64 _)) dst addr lane_imm)
1845
+ (vec_load_lane_rev ty dst addr lane_imm))
1846
+
1847
+ ;; On z14, use a little-endian load to GPR followed by vec_insert_lane.
1848
+ (rule (vec_load_lane_little (and (vxrs_ext2_disabled)
1849
+ ty @ (multi_lane 16 _)) dst addr lane_imm)
1850
+ (vec_insert_lane ty dst (loadrev16 addr) lane_imm (zero_reg)))
1851
+ (rule (vec_load_lane_little (and (vxrs_ext2_disabled)
1852
+ ty @ (multi_lane 32 _)) dst addr lane_imm)
1853
+ (vec_insert_lane ty dst (loadrev32 addr) lane_imm (zero_reg)))
1854
+ (rule (vec_load_lane_little (and (vxrs_ext2_disabled)
1855
+ ty @ (multi_lane 64 _)) dst addr lane_imm)
1856
+ (vec_insert_lane ty dst (loadrev64 addr) lane_imm (zero_reg)))
1857
+
1858
+ ;; Helper to implement a generic little-endian variant of vec_load_lane_undef.
1859
+ (decl vec_load_lane_little_undef (Type MemArg u8) Reg)
1860
+
1861
+ ;; 8-byte little-endian loads can be performed via a normal load.
1862
+ (rule (vec_load_lane_little_undef ty @ (multi_lane 8 _) addr lane_imm)
1863
+ (vec_load_lane_undef ty addr lane_imm))
1864
+
1865
+ ;; On z15, we have instructions to perform little-endian loads.
1866
+ (rule 1 (vec_load_lane_little_undef (and (vxrs_ext2_enabled)
1867
+ ty @ (multi_lane 16 _)) addr lane_imm)
1868
+ (vec_load_lane_rev_undef ty addr lane_imm))
1869
+ (rule 1 (vec_load_lane_little_undef (and (vxrs_ext2_enabled)
1870
+ ty @ (multi_lane 32 _)) addr lane_imm)
1871
+ (vec_load_lane_rev_undef ty addr lane_imm))
1872
+ (rule 1 (vec_load_lane_little_undef (and (vxrs_ext2_enabled)
1873
+ ty @ (multi_lane 64 _)) addr lane_imm)
1874
+ (vec_load_lane_rev_undef ty addr lane_imm))
1875
+
1876
+ ;; On z14, use a little-endian load to GPR followed by vec_insert_lane_undef.
1877
+ (rule (vec_load_lane_little_undef (and (vxrs_ext2_disabled)
1878
+ ty @ (multi_lane 16 _)) addr lane_imm)
1879
+ (vec_insert_lane_undef ty (loadrev16 addr) lane_imm (zero_reg)))
1880
+ (rule (vec_load_lane_little_undef (and (vxrs_ext2_disabled)
1881
+ ty @ (multi_lane 32 _)) addr lane_imm)
1882
+ (vec_insert_lane_undef ty (loadrev32 addr) lane_imm (zero_reg)))
1883
+ (rule (vec_load_lane_little_undef (and (vxrs_ext2_disabled)
1884
+ ty @ (multi_lane 64 _)) addr lane_imm)
1885
+ (vec_insert_lane_undef ty (loadrev64 addr) lane_imm (zero_reg)))
1886
+
1887
+
1888
+ ;;;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1889
+
1890
+ ;; Extract vector lane to general-purpose register.
1891
+ (rule 1 (lower (has_type out_ty
1892
+ (extractlane x @ (value_type ty) (u8_from_uimm8 idx))))
1893
+ (if (ty_int_ref_scalar_64 out_ty))
1894
+ (vec_extract_lane ty x (be_lane_idx ty idx) (zero_reg)))
1895
+
1896
+ ;; Extract vector lane to floating-point register.
1897
+ (rule 0 (lower (has_type (ty_scalar_float _)
1898
+ (extractlane x @ (value_type ty) (u8_from_uimm8 idx))))
1899
+ (vec_replicate_lane ty x (be_lane_idx ty idx)))
1900
+
1901
+ ;; Extract vector lane and store to big-endian memory.
1902
+ (rule 6 (lower (store flags @ (bigendian)
1903
+ (extractlane x @ (value_type ty) (u8_from_uimm8 idx))
1904
+ addr offset))
1905
+ (side_effect (vec_store_lane ty x
1906
+ (lower_address flags addr offset) (be_lane_idx ty idx))))
1907
+
1908
+ ;; Extract vector lane and store to little-endian memory.
1909
+ (rule 5 (lower (store flags @ (littleendian)
1910
+ (extractlane x @ (value_type ty) (u8_from_uimm8 idx))
1911
+ addr offset))
1912
+ (side_effect (vec_store_lane_little ty x
1913
+ (lower_address flags addr offset) (be_lane_idx ty idx))))
1914
+
1915
+
1916
+ ;; Helper to implement a generic little-endian variant of vec_store_lane.
1917
+ (decl vec_store_lane_little (Type Reg MemArg u8) SideEffectNoResult)
1918
+
1919
+ ;; 8-byte little-endian stores can be performed via a normal store.
1920
+ (rule (vec_store_lane_little ty @ (multi_lane 8 _) src addr lane_imm)
1921
+ (vec_store_lane ty src addr lane_imm))
1922
+
1923
+ ;; On z15, we have instructions to perform little-endian stores.
1924
+ (rule 1 (vec_store_lane_little (and (vxrs_ext2_enabled)
1925
+ ty @ (multi_lane 16 _)) src addr lane_imm)
1926
+ (vec_store_lane_rev ty src addr lane_imm))
1927
+ (rule 1 (vec_store_lane_little (and (vxrs_ext2_enabled)
1928
+ ty @ (multi_lane 32 _)) src addr lane_imm)
1929
+ (vec_store_lane_rev ty src addr lane_imm))
1930
+ (rule 1 (vec_store_lane_little (and (vxrs_ext2_enabled)
1931
+ ty @ (multi_lane 64 _)) src addr lane_imm)
1932
+ (vec_store_lane_rev ty src addr lane_imm))
1933
+
1934
+ ;; On z14, use vec_extract_lane followed by a little-endian store from GPR.
1935
+ (rule (vec_store_lane_little (and (vxrs_ext2_disabled)
1936
+ ty @ (multi_lane 16 _)) src addr lane_imm)
1937
+ (storerev16 (vec_extract_lane ty src lane_imm (zero_reg)) addr))
1938
+ (rule (vec_store_lane_little (and (vxrs_ext2_disabled)
1939
+ ty @ (multi_lane 32 _)) src addr lane_imm)
1940
+ (storerev32 (vec_extract_lane ty src lane_imm (zero_reg)) addr))
1941
+ (rule (vec_store_lane_little (and (vxrs_ext2_disabled)
1942
+ ty @ (multi_lane 64 _)) src addr lane_imm)
1943
+ (storerev64 (vec_extract_lane ty src lane_imm (zero_reg)) addr))
1944
+
1945
+
1946
+ ;;;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1947
+
1948
+ ;; Load replicated value from general-purpose register.
1949
+ (rule 1 (lower (has_type ty (splat x @ (value_type in_ty))))
1950
+ (if (ty_int_ref_scalar_64 in_ty))
1951
+ (vec_replicate_lane ty (vec_insert_lane_undef ty x 0 (zero_reg)) 0))
1952
+
1953
+ ;; Load replicated value from floating-point register.
1954
+ (rule 0 (lower (has_type ty (splat
1955
+ x @ (value_type (ty_scalar_float _)))))
1956
+ (vec_replicate_lane ty x 0))
1957
+
1958
+ ;; Load replicated value from vector lane.
1959
+ (rule 2 (lower (has_type ty (splat (extractlane x (u8_from_uimm8 idx)))))
1960
+ (vec_replicate_lane ty x (be_lane_idx ty idx)))
1961
+
1962
+ ;; Load replicated 16-bit immediate value.
1963
+ (rule 3 (lower (has_type ty (splat (i16_from_value x))))
1964
+ (vec_imm_replicate ty x))
1965
+
1966
+ ;; Load replicated value from big-endian memory.
1967
+ (rule 4 (lower (has_type ty (splat (sinkable_load x))))
1968
+ (vec_load_replicate ty (sink_load x)))
1969
+
1970
+ ;; Load replicated value from little-endian memory.
1971
+ (rule 5 (lower (has_type ty (splat (sinkable_load_little x))))
1972
+ (vec_load_replicate_little ty (sink_load x)))
1973
+
1974
+
1975
+ ;; Helper to implement a generic little-endian variant of vec_load_replicate
1976
+ (decl vec_load_replicate_little (Type MemArg) Reg)
1977
+
1978
+ ;; 8-byte little-endian loads can be performed via a normal load.
1979
+ (rule (vec_load_replicate_little ty @ (multi_lane 8 _) addr)
1980
+ (vec_load_replicate ty addr))
1981
+
1982
+ ;; On z15, we have instructions to perform little-endian loads.
1983
+ (rule 1 (vec_load_replicate_little (and (vxrs_ext2_enabled)
1984
+ ty @ (multi_lane 16 _)) addr)
1985
+ (vec_load_replicate_rev ty addr))
1986
+ (rule 1 (vec_load_replicate_little (and (vxrs_ext2_enabled)
1987
+ ty @ (multi_lane 32 _)) addr)
1988
+ (vec_load_replicate_rev ty addr))
1989
+ (rule 1 (vec_load_replicate_little (and (vxrs_ext2_enabled)
1990
+ ty @ (multi_lane 64 _)) addr)
1991
+ (vec_load_replicate_rev ty addr))
1992
+
1993
+ ;; On z14, use a little-endian load (via GPR) and replicate.
1994
+ (rule (vec_load_replicate_little (and (vxrs_ext2_disabled)
1995
+ ty @ (multi_lane 16 _)) addr)
1996
+ (vec_replicate_lane ty (vec_load_lane_little_undef ty addr 0) 0))
1997
+ (rule (vec_load_replicate_little (and (vxrs_ext2_disabled)
1998
+ ty @ (multi_lane 32 _)) addr)
1999
+ (vec_replicate_lane ty (vec_load_lane_little_undef ty addr 0) 0))
2000
+ (rule (vec_load_replicate_little (and (vxrs_ext2_disabled)
2001
+ ty @ (multi_lane 64 _)) addr)
2002
+ (vec_replicate_lane ty (vec_load_lane_little_undef ty addr 0) 0))
2003
+
2004
+
2005
+ ;;;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2006
+
2007
+ ;; Load scalar value from general-purpose register.
2008
+ (rule 1 (lower (has_type ty (scalar_to_vector
2009
+ x @ (value_type in_ty))))
2010
+ (if (ty_int_ref_scalar_64 in_ty))
2011
+ (vec_insert_lane ty (vec_imm ty 0) x (be_lane_idx ty 0) (zero_reg)))
2012
+
2013
+ ;; Load scalar value from floating-point register.
2014
+ (rule 0 (lower (has_type ty (scalar_to_vector
2015
+ x @ (value_type (ty_scalar_float _)))))
2016
+ (vec_move_lane_and_zero ty (be_lane_idx ty 0) x 0))
2017
+
2018
+ ;; Load scalar value from vector lane.
2019
+ (rule 2 (lower (has_type ty (scalar_to_vector
2020
+ (extractlane x (u8_from_uimm8 idx)))))
2021
+ (vec_move_lane_and_zero ty (be_lane_idx ty 0) x (be_lane_idx ty idx)))
2022
+
2023
+ ;; Load scalar 16-bit immediate value.
2024
+ (rule 3 (lower (has_type ty (scalar_to_vector (i16_from_value x))))
2025
+ (vec_insert_lane_imm ty (vec_imm ty 0) x (be_lane_idx ty 0)))
2026
+
2027
+ ;; Load scalar value from big-endian memory.
2028
+ (rule 4 (lower (has_type ty (scalar_to_vector (sinkable_load x))))
2029
+ (vec_load_lane ty (vec_imm ty 0) (sink_load x) (be_lane_idx ty 0)))
2030
+
2031
+ ;; Load scalar value lane from little-endian memory.
2032
+ (rule 5 (lower (has_type ty (scalar_to_vector (sinkable_load_little x))))
2033
+ (vec_load_lane_little ty (vec_imm ty 0) (sink_load x) (be_lane_idx ty 0)))
2034
+
2035
+
2036
+ ;; Helper to extract one lane from a vector and insert it into a zero vector.
2037
+ (decl vec_move_lane_and_zero (Type u8 Reg u8) Reg)
2038
+
2039
+ ;; For 64-bit elements we always use VPDI.
2040
+ (rule (vec_move_lane_and_zero ty @ (multi_lane 64 _) 0 src src_idx)
2041
+ (vec_permute_dw_imm ty src src_idx (vec_imm ty 0) 0))
2042
+ (rule (vec_move_lane_and_zero ty @ (multi_lane 64 _) 1 src src_idx)
2043
+ (vec_permute_dw_imm ty (vec_imm ty 0) 0 src src_idx))
2044
+
2045
+ ;; If source and destination index are the same, simply mask to this lane.
2046
+ (rule -1 (vec_move_lane_and_zero ty idx src idx)
2047
+ (vec_and ty src
2048
+ (vec_imm_byte_mask ty (lane_byte_mask ty idx))))
2049
+
2050
+ ;; Otherwise replicate source first and then mask to the lane.
2051
+ (rule -2 (vec_move_lane_and_zero ty dst_idx src src_idx)
2052
+ (vec_and ty (vec_replicate_lane ty src src_idx)
2053
+ (vec_imm_byte_mask ty (lane_byte_mask ty dst_idx))))
2054
+
2055
+
2056
+ ;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2057
+
2058
+ ;; General case: use vec_permute and then mask off zero lanes.
2059
+ (rule -2 (lower (shuffle x y (shuffle_mask permute_mask and_mask)))
2060
+ (vec_and $I8X16 (vec_imm_byte_mask $I8X16 and_mask)
2061
+ (vec_permute $I8X16 x y (vec_imm $I8X16 permute_mask))))
2062
+
2063
+ ;; If the pattern has no zero lanes, just a vec_permute suffices.
2064
+ (rule -1 (lower (shuffle x y (shuffle_mask permute_mask 65535)))
2065
+ (vec_permute $I8X16 x y (vec_imm $I8X16 permute_mask)))
2066
+
2067
+ ;; Special patterns that can be implemented via MERGE HIGH.
2068
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23) 65535)))
2069
+ (vec_merge_high $I64X2 x y))
2070
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 16 17 18 19 4 5 6 7 20 21 22 23) 65535)))
2071
+ (vec_merge_high $I32X4 x y))
2072
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 16 17 2 3 18 19 4 5 20 21 6 7 22 23) 65535)))
2073
+ (vec_merge_high $I16X8 x y))
2074
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23) 65535)))
2075
+ (vec_merge_high $I8X16 x y))
2076
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7) 65535)))
2077
+ (vec_merge_high $I64X2 y x))
2078
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 0 1 2 3 20 21 22 23 4 5 6 7) 65535)))
2079
+ (vec_merge_high $I32X4 y x))
2080
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 0 1 18 19 2 3 20 21 4 5 22 23 6 7) 65535)))
2081
+ (vec_merge_high $I16X8 y x))
2082
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 0 17 1 18 2 19 3 20 4 21 5 22 6 23 7) 65535)))
2083
+ (vec_merge_high $I8X16 y x))
2084
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7) 65535)))
2085
+ (vec_merge_high $I64X2 x x))
2086
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 0 1 2 3 4 5 6 7 4 5 6 7) 65535)))
2087
+ (vec_merge_high $I32X4 x x))
2088
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 0 1 2 3 2 3 4 5 4 5 6 7 6 7) 65535)))
2089
+ (vec_merge_high $I16X8 x x))
2090
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7) 65535)))
2091
+ (vec_merge_high $I8X16 x x))
2092
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 20 21 22 23 16 17 18 19 20 21 22 23) 65535)))
2093
+ (vec_merge_high $I64X2 y y))
2094
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 16 17 18 19 20 21 22 23 20 21 22 23) 65535)))
2095
+ (vec_merge_high $I32X4 y y))
2096
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 16 17 18 19 18 19 20 21 20 21 22 23 22 23) 65535)))
2097
+ (vec_merge_high $I16X8 y y))
2098
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23) 65535)))
2099
+ (vec_merge_high $I8X16 y y))
2100
+
2101
+ ;; Special patterns that can be implemented via MERGE LOW.
2102
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31) 65535)))
2103
+ (vec_merge_low $I64X2 x y))
2104
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 24 25 26 27 12 13 14 15 28 29 30 31) 65535)))
2105
+ (vec_merge_low $I32X4 x y))
2106
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 24 25 10 11 26 27 12 13 28 29 14 15 30 31) 65535)))
2107
+ (vec_merge_low $I16X8 x y))
2108
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 24 9 25 10 26 11 27 12 28 13 29 14 30 15 31) 65535)))
2109
+ (vec_merge_low $I8X16 x y))
2110
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 28 29 30 31 8 9 10 11 12 13 14 15) 65535)))
2111
+ (vec_merge_low $I64X2 y x))
2112
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 8 9 10 11 28 29 30 31 12 13 14 15) 65535)))
2113
+ (vec_merge_low $I32X4 y x))
2114
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 8 9 26 27 10 11 28 29 12 13 30 31 14 15) 65535)))
2115
+ (vec_merge_low $I16X8 y x))
2116
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 8 25 9 26 10 27 11 28 12 29 13 30 14 31 15) 65535)))
2117
+ (vec_merge_low $I8X16 y x))
2118
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15) 65535)))
2119
+ (vec_merge_low $I64X2 x x))
2120
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 8 9 10 11 12 13 14 15 12 13 14 15) 65535)))
2121
+ (vec_merge_low $I32X4 x x))
2122
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 8 9 10 11 10 11 12 13 12 13 14 15 14 15) 65535)))
2123
+ (vec_merge_low $I16X8 x x))
2124
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15) 65535)))
2125
+ (vec_merge_low $I8X16 x x))
2126
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 28 29 30 31 24 25 26 27 28 29 30 31) 65535)))
2127
+ (vec_merge_low $I64X2 y y))
2128
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 24 25 26 27 28 29 30 31 28 29 30 31) 65535)))
2129
+ (vec_merge_low $I32X4 y y))
2130
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 24 25 26 27 26 27 28 29 28 29 30 31 30 31) 65535)))
2131
+ (vec_merge_low $I16X8 y y))
2132
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31) 65535)))
2133
+ (vec_merge_low $I8X16 y y))
2134
+
2135
+ ;; Special patterns that can be implemented via PACK.
2136
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 4 5 6 7 12 13 14 15 20 21 22 23 28 29 30 31) 65535)))
2137
+ (vec_pack $I64X2 x y))
2138
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 2 3 6 7 10 11 14 15 18 19 22 23 26 27 30 31) 65535)))
2139
+ (vec_pack $I32X4 x y))
2140
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31) 65535)))
2141
+ (vec_pack $I16X8 x y))
2142
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 20 21 22 23 28 29 30 31 4 5 6 7 12 13 14 15) 65535)))
2143
+ (vec_pack $I64X2 y x))
2144
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 18 19 22 23 26 27 30 31 2 3 6 7 10 11 14 15) 65535)))
2145
+ (vec_pack $I32X4 y x))
2146
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 17 19 21 23 25 27 29 31 1 3 5 7 9 11 13 15) 65535)))
2147
+ (vec_pack $I16X8 y x))
2148
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 4 5 6 7 12 13 14 15 4 5 6 7 12 13 14 15) 65535)))
2149
+ (vec_pack $I64X2 x x))
2150
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 2 3 6 7 10 11 14 15 2 3 6 7 10 11 14 15) 65535)))
2151
+ (vec_pack $I32X4 x x))
2152
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15) 65535)))
2153
+ (vec_pack $I16X8 x x))
2154
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 20 21 22 23 28 29 30 31 20 21 22 23 28 29 30 31) 65535)))
2155
+ (vec_pack $I64X2 y y))
2156
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 18 19 22 23 26 27 30 31 18 19 22 23 26 27 30 31) 65535)))
2157
+ (vec_pack $I32X4 y y))
2158
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 17 19 21 23 25 27 29 31 17 19 21 23 25 27 29 31) 65535)))
2159
+ (vec_pack $I16X8 y y))
2160
+
2161
+ ;; Special patterns that can be implemented via UNPACK HIGH.
2162
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ _ _ 0 1 2 3 _ _ _ _ 4 5 6 7) 3855)))
2163
+ (vec_unpacku_high $I32X4 x))
2164
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ 0 1 _ _ 2 3 _ _ 4 5 _ _ 6 7) 13107)))
2165
+ (vec_unpacku_high $I16X8 x))
2166
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ 0 _ 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7) 21845)))
2167
+ (vec_unpacku_high $I8X16 x))
2168
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ _ _ 16 17 18 19 _ _ _ _ 20 21 22 23) 3855)))
2169
+ (vec_unpacku_high $I32X4 y))
2170
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ 16 17 _ _ 18 19 _ _ 20 21 _ _ 22 23) 13107)))
2171
+ (vec_unpacku_high $I16X8 y))
2172
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ 16 _ 17 _ 18 _ 19 _ 20 _ 21 _ 22 _ 23) 21845)))
2173
+ (vec_unpacku_high $I8X16 y))
2174
+
2175
+ ;; Special patterns that can be implemented via UNPACK LOW.
2176
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ _ _ 8 9 10 11 _ _ _ _ 12 13 14 15) 3855)))
2177
+ (vec_unpacku_low $I32X4 x))
2178
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ 8 9 _ _ 10 11 _ _ 12 13 _ _ 14 15) 13107)))
2179
+ (vec_unpacku_low $I16X8 x))
2180
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ 8 _ 9 _ 10 _ 11 _ 12 _ 13 _ 14 _ 15) 21845)))
2181
+ (vec_unpacku_low $I8X16 x))
2182
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ _ _ 24 25 26 27 _ _ _ _ 28 29 30 31) 3855)))
2183
+ (vec_unpacku_low $I32X4 y))
2184
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ _ 24 25 _ _ 26 27 _ _ 28 29 _ _ 30 31) 13107)))
2185
+ (vec_unpacku_low $I16X8 y))
2186
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 _ 24 _ 25 _ 26 _ 27 _ 28 _ 29 _ 30 _ 31) 21845)))
2187
+ (vec_unpacku_low $I8X16 y))
2188
+
2189
+ ;; Special patterns that can be implemented via PERMUTE DOUBLEWORD IMMEDIATE.
2190
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 4 5 6 7 24 25 26 27 28 29 30 31) 65535)))
2191
+ (vec_permute_dw_imm $I8X16 x 0 y 1))
2192
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23) 65535)))
2193
+ (vec_permute_dw_imm $I8X16 x 1 y 0))
2194
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15) 65535)))
2195
+ (vec_permute_dw_imm $I8X16 y 0 x 1))
2196
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7) 65535)))
2197
+ (vec_permute_dw_imm $I8X16 y 1 x 0))
2198
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15) 65535)))
2199
+ (vec_permute_dw_imm $I8X16 x 0 x 1))
2200
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7) 65535)))
2201
+ (vec_permute_dw_imm $I8X16 x 1 x 0))
2202
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31) 65535)))
2203
+ (vec_permute_dw_imm $I8X16 y 0 y 1))
2204
+ (rule (lower (shuffle x y (shuffle_mask (imm8x16 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23) 65535)))
2205
+ (vec_permute_dw_imm $I8X16 y 1 y 0))
2206
+
2207
+
2208
+ ;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2209
+
2210
+ ;; When using big-endian lane order, the lane mask is mostly correct, but we
2211
+ ;; need to handle mask elements outside the range 0..15 by zeroing the lane.
2212
+ ;;
2213
+ ;; To do so efficiently, we compute:
2214
+ ;; permute-lane-element := umin (16, swizzle-lane-element)
2215
+ ;; and pass a zero vector as second operand to the permute instruction.
2216
+
2217
+ (rule 1 (lower (has_type (ty_vec128 ty) (swizzle x y)))
2218
+ (if-let (LaneOrder.BigEndian) (lane_order))
2219
+ (vec_permute ty x (vec_imm ty 0)
2220
+ (vec_umin $I8X16 (vec_imm_splat $I8X16 16) y)))
2221
+
2222
+ ;; When using little-endian lane order, in addition to zeroing (as above),
2223
+ ;; we need to convert from little-endian to big-endian lane numbering.
2224
+ ;;
2225
+ ;; To do so efficiently, we compute:
2226
+ ;; permute-lane-element := umax (239, ~ swizzle-lane-element)
2227
+ ;; which has the following effect:
2228
+ ;; elements 0 .. 15 --> 255 .. 240 (i.e. 31 .. 16 mod 32)
2229
+ ;; everything else --> 239 (i.e. 15 mod 32)
2230
+ ;;
2231
+ ;; Then, we can use a single permute instruction with
2232
+ ;; a zero vector as first operand (covering lane 15)
2233
+ ;; the input vector as second operand (covering lanes 16 .. 31)
2234
+ ;; to implement the required swizzle semantics.
2235
+
2236
+ (rule (lower (has_type (ty_vec128 ty) (swizzle x y)))
2237
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2238
+ (vec_permute ty (vec_imm ty 0) x
2239
+ (vec_umax $I8X16 (vec_imm_splat $I8X16 239)
2240
+ (vec_not $I8X16 y))))
2241
+
2242
+
2243
+ ;;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2244
+
2245
+ ;; Load the address of a stack slot.
2246
+ (rule (lower (has_type ty (stack_addr stack_slot offset)))
2247
+ (stack_addr_impl ty stack_slot offset))
2248
+
2249
+
2250
+ ;;;; Rules for `func_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2251
+
2252
+ ;; Load the address of a function, target reachable via PC-relative instruction.
2253
+ (rule 1 (lower (func_addr (func_ref_data _ name (reloc_distance_near))))
2254
+ (load_addr (memarg_symbol name 0 (memflags_trusted))))
2255
+
2256
+ ;; Load the address of a function, general case.
2257
+ (rule (lower (func_addr (func_ref_data _ name _)))
2258
+ (load_symbol_reloc (SymbolReloc.Absolute name 0)))
2259
+
2260
+
2261
+ ;;;; Rules for `symbol_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2262
+
2263
+ ;; Load the address of a symbol, target reachable via PC-relative instruction.
2264
+ (rule 1 (lower (symbol_value (symbol_value_data name (reloc_distance_near)
2265
+ off)))
2266
+ (if-let offset (memarg_symbol_offset off))
2267
+ (load_addr (memarg_symbol name offset (memflags_trusted))))
2268
+
2269
+ ;; Load the address of a symbol, general case.
2270
+ (rule (lower (symbol_value (symbol_value_data name _ offset)))
2271
+ (load_symbol_reloc (SymbolReloc.Absolute name offset)))
2272
+
2273
+
2274
+ ;;;; Rules for `tls_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2275
+
2276
+ ;; Load the address of a TLS symbol (ELF general-dynamic model).
2277
+ (rule (lower (tls_value (symbol_value_data name _ 0)))
2278
+ (if (tls_model_is_elf_gd))
2279
+ (let ((symbol SymbolReloc (SymbolReloc.TlsGd name))
2280
+ (got Reg (load_addr (memarg_got)))
2281
+ (got_offset Reg (load_symbol_reloc symbol))
2282
+ (tls_offset Reg (lib_call_tls_get_offset got got_offset symbol)))
2283
+ (add_reg $I64 tls_offset (thread_pointer))))
2284
+
2285
+ ;; Helper to perform a call to the __tls_get_offset library routine.
2286
+ (decl lib_call_tls_get_offset (Reg Reg SymbolReloc) Reg)
2287
+ (rule (lib_call_tls_get_offset got got_offset symbol)
2288
+ (let ((tls_offset WritableReg (temp_writable_reg $I64))
2289
+ (libcall LibCallInfo (lib_call_info_tls_get_offset tls_offset got got_offset symbol))
2290
+ (_ Unit (lib_accumulate_outgoing_args_size libcall))
2291
+ (_ InstOutput (side_effect (lib_call libcall))))
2292
+ tls_offset))
2293
+
2294
+ ;; Helper to extract the current thread pointer from %a0/%a1.
2295
+ (decl thread_pointer () Reg)
2296
+ (rule (thread_pointer)
2297
+ (insert_ar (lshl_imm $I64 (load_ar 0) 32) 1))
2298
+
2299
+
2300
+ ;;;; Rules for `load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2301
+
2302
+ ;; Load 8-bit integers.
2303
+ (rule (lower (has_type $I8 (load flags addr offset)))
2304
+ (zext32_mem $I8 (lower_address flags addr offset)))
2305
+
2306
+ ;; Load 16-bit big-endian integers.
2307
+ (rule (lower (has_type $I16 (load flags @ (bigendian) addr offset)))
2308
+ (zext32_mem $I16 (lower_address flags addr offset)))
2309
+
2310
+ ;; Load 16-bit little-endian integers.
2311
+ (rule -1 (lower (has_type $I16 (load flags @ (littleendian) addr offset)))
2312
+ (loadrev16 (lower_address flags addr offset)))
2313
+
2314
+ ;; Load 32-bit big-endian integers.
2315
+ (rule (lower (has_type $I32 (load flags @ (bigendian) addr offset)))
2316
+ (load32 (lower_address flags addr offset)))
2317
+
2318
+ ;; Load 32-bit little-endian integers.
2319
+ (rule -1 (lower (has_type $I32 (load flags @ (littleendian) addr offset)))
2320
+ (loadrev32 (lower_address flags addr offset)))
2321
+
2322
+ ;; Load 64-bit big-endian integers.
2323
+ (rule (lower (has_type $I64 (load flags @ (bigendian) addr offset)))
2324
+ (load64 (lower_address flags addr offset)))
2325
+
2326
+ ;; Load 64-bit little-endian integers.
2327
+ (rule -1 (lower (has_type $I64 (load flags @ (littleendian) addr offset)))
2328
+ (loadrev64 (lower_address flags addr offset)))
2329
+
2330
+ ;; Load 64-bit big-endian references.
2331
+ (rule (lower (has_type $R64 (load flags @ (bigendian) addr offset)))
2332
+ (load64 (lower_address flags addr offset)))
2333
+
2334
+ ;; Load 64-bit little-endian references.
2335
+ (rule -1 (lower (has_type $R64 (load flags @ (littleendian) addr offset)))
2336
+ (loadrev64 (lower_address flags addr offset)))
2337
+
2338
+ ;; Load 32-bit big-endian floating-point values (as vector lane).
2339
+ (rule (lower (has_type $F32 (load flags @ (bigendian) addr offset)))
2340
+ (vec_load_lane_undef $F32X4 (lower_address flags addr offset) 0))
2341
+
2342
+ ;; Load 32-bit little-endian floating-point values (as vector lane).
2343
+ (rule -1 (lower (has_type $F32 (load flags @ (littleendian) addr offset)))
2344
+ (vec_load_lane_little_undef $F32X4 (lower_address flags addr offset) 0))
2345
+
2346
+ ;; Load 64-bit big-endian floating-point values (as vector lane).
2347
+ (rule (lower (has_type $F64 (load flags @ (bigendian) addr offset)))
2348
+ (vec_load_lane_undef $F64X2 (lower_address flags addr offset) 0))
2349
+
2350
+ ;; Load 64-bit little-endian floating-point values (as vector lane).
2351
+ (rule -1 (lower (has_type $F64 (load flags @ (littleendian) addr offset)))
2352
+ (vec_load_lane_little_undef $F64X2 (lower_address flags addr offset) 0))
2353
+
2354
+ ;; Load 128-bit big-endian vector values, BE lane order - direct load.
2355
+ (rule 4 (lower (has_type (vr128_ty ty) (load flags @ (bigendian) addr offset)))
2356
+ (if-let (LaneOrder.BigEndian) (lane_order))
2357
+ (vec_load ty (lower_address flags addr offset)))
2358
+
2359
+ ;; Load 128-bit little-endian vector values, BE lane order - byte-reversed load.
2360
+ (rule 3 (lower (has_type (vr128_ty ty) (load flags @ (littleendian) addr offset)))
2361
+ (if-let (LaneOrder.BigEndian) (lane_order))
2362
+ (vec_load_byte_rev ty flags addr offset))
2363
+
2364
+ ;; Load 128-bit big-endian vector values, LE lane order - element-reversed load.
2365
+ (rule 2 (lower (has_type (vr128_ty ty) (load flags @ (bigendian) addr offset)))
2366
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2367
+ (vec_load_elt_rev ty flags addr offset))
2368
+
2369
+ ;; Load 128-bit little-endian vector values, LE lane order - fully-reversed load.
2370
+ (rule 1 (lower (has_type (vr128_ty ty) (load flags @ (littleendian) addr offset)))
2371
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2372
+ (vec_load_full_rev ty flags addr offset))
2373
+
2374
+
2375
+ ;; Helper to perform a 128-bit full-vector byte-reversed load.
2376
+ (decl vec_load_full_rev (Type MemFlags Value Offset32) Reg)
2377
+
2378
+ ;; Full-vector byte-reversed load via single instruction on z15.
2379
+ (rule 1 (vec_load_full_rev (and (vxrs_ext2_enabled) (vr128_ty ty)) flags addr offset)
2380
+ (vec_loadrev ty (lower_address flags addr offset)))
2381
+
2382
+ ;; Full-vector byte-reversed load via GPRs on z14.
2383
+ (rule (vec_load_full_rev (and (vxrs_ext2_disabled) (vr128_ty ty)) flags addr offset)
2384
+ (let ((lo_addr MemArg (lower_address_bias flags addr offset 0))
2385
+ (hi_addr MemArg (lower_address_bias flags addr offset 8))
2386
+ (lo_val Reg (loadrev64 lo_addr))
2387
+ (hi_val Reg (loadrev64 hi_addr)))
2388
+ (mov_to_vec128 ty hi_val lo_val)))
2389
+
2390
+
2391
+ ;; Helper to perform an element-wise byte-reversed load.
2392
+ (decl vec_load_byte_rev (Type MemFlags Value Offset32) Reg)
2393
+
2394
+ ;; Element-wise byte-reversed 1x128-bit load is a full byte-reversed load.
2395
+ (rule -1 (vec_load_byte_rev $I128 flags addr offset)
2396
+ (vec_load_full_rev $I128 flags addr offset))
2397
+
2398
+ ;; Element-wise byte-reversed 16x8-bit load is a direct load.
2399
+ (rule (vec_load_byte_rev ty @ (multi_lane 8 16) flags addr offset)
2400
+ (vec_load ty (lower_address flags addr offset)))
2401
+
2402
+ ;; Element-wise byte-reversed load via single instruction on z15.
2403
+ (rule 1 (vec_load_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 64 2))
2404
+ flags addr offset)
2405
+ (vec_load_byte64rev ty (lower_address flags addr offset)))
2406
+ (rule 1 (vec_load_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 32 4))
2407
+ flags addr offset)
2408
+ (vec_load_byte32rev ty (lower_address flags addr offset)))
2409
+ (rule 1 (vec_load_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 16 8))
2410
+ flags addr offset)
2411
+ (vec_load_byte16rev ty (lower_address flags addr offset)))
2412
+
2413
+ ;; Element-wise byte-reversed load as element-swapped byte-reversed load on z14.
2414
+ (rule (vec_load_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 64 2))
2415
+ flags addr offset)
2416
+ (vec_elt_rev ty (vec_load_full_rev ty flags addr offset)))
2417
+ (rule (vec_load_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 32 4))
2418
+ flags addr offset)
2419
+ (vec_elt_rev ty (vec_load_full_rev ty flags addr offset)))
2420
+ (rule (vec_load_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 16 8))
2421
+ flags addr offset)
2422
+ (vec_elt_rev ty (vec_load_full_rev ty flags addr offset)))
2423
+
2424
+
2425
+ ;; Helper to perform an element-reversed load.
2426
+ (decl vec_load_elt_rev (Type MemFlags Value Offset32) Reg)
2427
+
2428
+ ;; Element-reversed 1x128-bit load is a direct load.
2429
+ ;; For 1x128-bit types, this is a direct load.
2430
+ (rule -1 (vec_load_elt_rev $I128 flags addr offset)
2431
+ (vec_load $I128 (lower_address flags addr offset)))
2432
+
2433
+ ;; Element-reversed 16x8-bit load is a full byte-reversed load.
2434
+ (rule (vec_load_elt_rev ty @ (multi_lane 8 16) flags addr offset)
2435
+ (vec_load_full_rev ty flags addr offset))
2436
+
2437
+ ;; Element-reversed load via single instruction on z15.
2438
+ (rule 1 (vec_load_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 64 2))
2439
+ flags addr offset)
2440
+ (vec_load_elt64rev ty (lower_address flags addr offset)))
2441
+ (rule 1 (vec_load_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 32 4))
2442
+ flags addr offset)
2443
+ (vec_load_elt32rev ty (lower_address flags addr offset)))
2444
+ (rule 1 (vec_load_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 16 8))
2445
+ flags addr offset)
2446
+ (vec_load_elt16rev ty (lower_address flags addr offset)))
2447
+
2448
+ ;; Element-reversed load as element-swapped direct load on z14.
2449
+ (rule (vec_load_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 64 2))
2450
+ flags addr offset)
2451
+ (vec_elt_rev ty (vec_load ty (lower_address flags addr offset))))
2452
+ (rule (vec_load_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 32 4))
2453
+ flags addr offset)
2454
+ (vec_elt_rev ty (vec_load ty (lower_address flags addr offset))))
2455
+ (rule (vec_load_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 16 8))
2456
+ flags addr offset)
2457
+ (vec_elt_rev ty (vec_load ty (lower_address flags addr offset))))
2458
+
2459
+
2460
+ ;;;; Rules for `uload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2461
+
2462
+ ;; 16- or 32-bit target types.
2463
+ (rule (lower (has_type (gpr32_ty _ty) (uload8 flags addr offset)))
2464
+ (zext32_mem $I8 (lower_address flags addr offset)))
2465
+
2466
+ ;; 64-bit target types.
2467
+ (rule 1 (lower (has_type (gpr64_ty _ty) (uload8 flags addr offset)))
2468
+ (zext64_mem $I8 (lower_address flags addr offset)))
2469
+
2470
+
2471
+ ;;;; Rules for `sload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2472
+
2473
+ ;; 16- or 32-bit target types.
2474
+ (rule (lower (has_type (gpr32_ty _ty) (sload8 flags addr offset)))
2475
+ (sext32_mem $I8 (lower_address flags addr offset)))
2476
+
2477
+ ;; 64-bit target types.
2478
+ (rule 1 (lower (has_type (gpr64_ty _ty) (sload8 flags addr offset)))
2479
+ (sext64_mem $I8 (lower_address flags addr offset)))
2480
+
2481
+
2482
+ ;;;; Rules for `uload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2483
+
2484
+ ;; 32-bit target type, big-endian source value.
2485
+ (rule 3 (lower (has_type (gpr32_ty _ty)
2486
+ (uload16 flags @ (bigendian) addr offset)))
2487
+ (zext32_mem $I16 (lower_address flags addr offset)))
2488
+
2489
+ ;; 32-bit target type, little-endian source value (via explicit extension).
2490
+ (rule 1 (lower (has_type (gpr32_ty _ty)
2491
+ (uload16 flags @ (littleendian) addr offset)))
2492
+ (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
2493
+ (zext32_reg $I16 reg16)))
2494
+
2495
+ ;; 64-bit target type, big-endian source value.
2496
+ (rule 4 (lower (has_type (gpr64_ty _ty)
2497
+ (uload16 flags @ (bigendian) addr offset)))
2498
+ (zext64_mem $I16 (lower_address flags addr offset)))
2499
+
2500
+ ;; 64-bit target type, little-endian source value (via explicit extension).
2501
+ (rule 2 (lower (has_type (gpr64_ty _ty)
2502
+ (uload16 flags @ (littleendian) addr offset)))
2503
+ (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
2504
+ (zext64_reg $I16 reg16)))
2505
+
2506
+
2507
+ ;;;; Rules for `sload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2508
+
2509
+ ;; 32-bit target type, big-endian source value.
2510
+ (rule 2 (lower (has_type (gpr32_ty _ty)
2511
+ (sload16 flags @ (bigendian) addr offset)))
2512
+ (sext32_mem $I16 (lower_address flags addr offset)))
2513
+
2514
+ ;; 32-bit target type, little-endian source value (via explicit extension).
2515
+ (rule 0 (lower (has_type (gpr32_ty _ty)
2516
+ (sload16 flags @ (littleendian) addr offset)))
2517
+ (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
2518
+ (sext32_reg $I16 reg16)))
2519
+
2520
+ ;; 64-bit target type, big-endian source value.
2521
+ (rule 3 (lower (has_type (gpr64_ty _ty)
2522
+ (sload16 flags @ (bigendian) addr offset)))
2523
+ (sext64_mem $I16 (lower_address flags addr offset)))
2524
+
2525
+ ;; 64-bit target type, little-endian source value (via explicit extension).
2526
+ (rule 1 (lower (has_type (gpr64_ty _ty)
2527
+ (sload16 flags @ (littleendian) addr offset)))
2528
+ (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
2529
+ (sext64_reg $I16 reg16)))
2530
+
2531
+
2532
+ ;;;; Rules for `uload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2533
+
2534
+ ;; 64-bit target type, big-endian source value.
2535
+ (rule 1 (lower (has_type (gpr64_ty _ty)
2536
+ (uload32 flags @ (bigendian) addr offset)))
2537
+ (zext64_mem $I32 (lower_address flags addr offset)))
2538
+
2539
+ ;; 64-bit target type, little-endian source value (via explicit extension).
2540
+ (rule (lower (has_type (gpr64_ty _ty)
2541
+ (uload32 flags @ (littleendian) addr offset)))
2542
+ (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
2543
+ (zext64_reg $I32 reg32)))
2544
+
2545
+
2546
+ ;;;; Rules for `sload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2547
+
2548
+ ;; 64-bit target type, big-endian source value.
2549
+ (rule 1 (lower (has_type (gpr64_ty _ty)
2550
+ (sload32 flags @ (bigendian) addr offset)))
2551
+ (sext64_mem $I32 (lower_address flags addr offset)))
2552
+
2553
+ ;; 64-bit target type, little-endian source value (via explicit extension).
2554
+ (rule (lower (has_type (gpr64_ty _ty)
2555
+ (sload32 flags @ (littleendian) addr offset)))
2556
+ (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
2557
+ (sext64_reg $I32 reg32)))
2558
+
2559
+
2560
+ ;;;; Rules for `uloadNxM` and `sloadNxM` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2561
+
2562
+ ;; Unsigned 8->16 bit extension.
2563
+ (rule (lower (has_type $I16X8 (uload8x8 flags addr offset)))
2564
+ (vec_unpacku_high $I8X16 (load_v64 $I8X16 flags addr offset)))
2565
+
2566
+ ;; Signed 8->16 bit extension.
2567
+ (rule (lower (has_type $I16X8 (sload8x8 flags addr offset)))
2568
+ (vec_unpacks_high $I8X16 (load_v64 $I8X16 flags addr offset)))
2569
+
2570
+ ;; Unsigned 16->32 bit extension.
2571
+ (rule (lower (has_type $I32X4 (uload16x4 flags addr offset)))
2572
+ (vec_unpacku_high $I16X8 (load_v64 $I16X8 flags addr offset)))
2573
+
2574
+ ;; Signed 16->32 bit extension.
2575
+ (rule (lower (has_type $I32X4 (sload16x4 flags addr offset)))
2576
+ (vec_unpacks_high $I16X8 (load_v64 $I16X8 flags addr offset)))
2577
+
2578
+ ;; Unsigned 32->64 bit extension.
2579
+ (rule (lower (has_type $I64X2 (uload32x2 flags addr offset)))
2580
+ (vec_unpacku_high $I32X4 (load_v64 $I32X4 flags addr offset)))
2581
+
2582
+ ;; Signed 32->64 bit extension.
2583
+ (rule (lower (has_type $I64X2 (sload32x2 flags addr offset)))
2584
+ (vec_unpacks_high $I32X4 (load_v64 $I32X4 flags addr offset)))
2585
+
2586
+
2587
+ ;; Helper to load a 64-bit half-size vector from memory.
2588
+ (decl load_v64 (Type MemFlags Value Offset32) Reg)
2589
+
2590
+ ;; Any big-endian source value, BE lane order.
2591
+ (rule -1 (load_v64 _ flags @ (bigendian) addr offset)
2592
+ (if-let (LaneOrder.BigEndian) (lane_order))
2593
+ (vec_load_lane_undef $I64X2 (lower_address flags addr offset) 0))
2594
+
2595
+ ;; Any little-endian source value, LE lane order.
2596
+ (rule -2 (load_v64 _ flags @ (littleendian) addr offset)
2597
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2598
+ (vec_load_lane_little_undef $I64X2 (lower_address flags addr offset) 0))
2599
+
2600
+ ;; Big-endian or little-endian 8x8-bit source value, BE lane order.
2601
+ (rule (load_v64 (multi_lane 8 16) flags addr offset)
2602
+ (if-let (LaneOrder.BigEndian) (lane_order))
2603
+ (vec_load_lane_undef $I64X2 (lower_address flags addr offset) 0))
2604
+
2605
+ ;; Big-endian or little-endian 8x8-bit source value, LE lane order.
2606
+ (rule 1 (load_v64 (multi_lane 8 16) flags addr offset)
2607
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2608
+ (vec_load_lane_little_undef $I64X2 (lower_address flags addr offset) 0))
2609
+
2610
+ ;; Little-endian 4x16-bit source value, BE lane order.
2611
+ (rule (load_v64 (multi_lane 16 8) flags @ (littleendian) addr offset)
2612
+ (if-let (LaneOrder.BigEndian) (lane_order))
2613
+ (vec_rot_imm $I16X8
2614
+ (vec_load_lane_undef $I64X2 (lower_address flags addr offset) 0) 8))
2615
+
2616
+ ;; Big-endian 4x16-bit source value, LE lane order.
2617
+ (rule 1 (load_v64 (multi_lane 16 8) flags @ (bigendian) addr offset)
2618
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2619
+ (vec_rot_imm $I16X8
2620
+ (vec_load_lane_little_undef $I64X2 (lower_address flags addr offset) 0) 8))
2621
+
2622
+ ;; Little-endian 2x32-bit source value, BE lane order.
2623
+ (rule (load_v64 (multi_lane 32 4) flags @ (littleendian) addr offset)
2624
+ (if-let (LaneOrder.BigEndian) (lane_order))
2625
+ (vec_rot_imm $I64X2
2626
+ (vec_load_lane_little_undef $I64X2 (lower_address flags addr offset) 0) 32))
2627
+
2628
+ ;; Big-endian 2x32-bit source value, LE lane order.
2629
+ (rule 1 (load_v64 (multi_lane 32 4) flags @ (bigendian) addr offset)
2630
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2631
+ (vec_rot_imm $I64X2
2632
+ (vec_load_lane_undef $I64X2 (lower_address flags addr offset) 0) 32))
2633
+
2634
+
2635
+ ;;;; Rules for `store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2636
+
2637
+ ;; The actual store logic for integer types is identical for the `store`,
2638
+ ;; `istoreNN`, and `atomic_store` instructions, so we share common helpers.
2639
+
2640
+ ;; Store 8-bit integer type, main lowering entry point.
2641
+ (rule (lower (store flags val @ (value_type $I8) addr offset))
2642
+ (side_effect (istore8_impl flags val addr offset)))
2643
+
2644
+ ;; Store 16-bit integer type, main lowering entry point.
2645
+ (rule (lower (store flags val @ (value_type $I16) addr offset))
2646
+ (side_effect (istore16_impl flags val addr offset)))
2647
+
2648
+ ;; Store 32-bit integer type, main lowering entry point.
2649
+ (rule (lower (store flags val @ (value_type $I32) addr offset))
2650
+ (side_effect (istore32_impl flags val addr offset)))
2651
+
2652
+ ;; Store 64-bit integer type, main lowering entry point.
2653
+ (rule (lower (store flags val @ (value_type $I64) addr offset))
2654
+ (side_effect (istore64_impl flags val addr offset)))
2655
+
2656
+ ;; Store 64-bit reference type, main lowering entry point.
2657
+ (rule (lower (store flags val @ (value_type $R64) addr offset))
2658
+ (side_effect (istore64_impl flags val addr offset)))
2659
+
2660
+ ;; Store 32-bit big-endian floating-point type (as vector lane).
2661
+ (rule -1 (lower (store flags @ (bigendian)
2662
+ val @ (value_type $F32) addr offset))
2663
+ (side_effect (vec_store_lane $F32X4 val
2664
+ (lower_address flags addr offset) 0)))
2665
+
2666
+ ;; Store 32-bit little-endian floating-point type (as vector lane).
2667
+ (rule (lower (store flags @ (littleendian)
2668
+ val @ (value_type $F32) addr offset))
2669
+ (side_effect (vec_store_lane_little $F32X4 val
2670
+ (lower_address flags addr offset) 0)))
2671
+
2672
+ ;; Store 64-bit big-endian floating-point type (as vector lane).
2673
+ (rule -1 (lower (store flags @ (bigendian)
2674
+ val @ (value_type $F64) addr offset))
2675
+ (side_effect (vec_store_lane $F64X2 val
2676
+ (lower_address flags addr offset) 0)))
2677
+
2678
+ ;; Store 64-bit little-endian floating-point type (as vector lane).
2679
+ (rule (lower (store flags @ (littleendian)
2680
+ val @ (value_type $F64) addr offset))
2681
+ (side_effect (vec_store_lane_little $F64X2 val
2682
+ (lower_address flags addr offset) 0)))
2683
+
2684
+ ;; Store 128-bit big-endian vector type, BE lane order - direct store.
2685
+ (rule 4 (lower (store flags @ (bigendian)
2686
+ val @ (value_type (vr128_ty ty)) addr offset))
2687
+ (if-let (LaneOrder.BigEndian) (lane_order))
2688
+ (side_effect (vec_store val (lower_address flags addr offset))))
2689
+
2690
+ ;; Store 128-bit little-endian vector type, BE lane order - byte-reversed store.
2691
+ (rule 3 (lower (store flags @ (littleendian)
2692
+ val @ (value_type (vr128_ty ty)) addr offset))
2693
+ (if-let (LaneOrder.BigEndian) (lane_order))
2694
+ (side_effect (vec_store_byte_rev ty val flags addr offset)))
2695
+
2696
+ ;; Store 128-bit big-endian vector type, LE lane order - element-reversed store.
2697
+ (rule 2 (lower (store flags @ (bigendian)
2698
+ val @ (value_type (vr128_ty ty)) addr offset))
2699
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2700
+ (side_effect (vec_store_elt_rev ty val flags addr offset)))
2701
+
2702
+ ;; Store 128-bit little-endian vector type, LE lane order - fully-reversed store.
2703
+ (rule 1 (lower (store flags @ (littleendian)
2704
+ val @ (value_type (vr128_ty ty)) addr offset))
2705
+ (if-let (LaneOrder.LittleEndian) (lane_order))
2706
+ (side_effect (vec_store_full_rev ty val flags addr offset)))
2707
+
2708
+
2709
+ ;; Helper to perform a 128-bit full-vector byte-reversed store.
2710
+ (decl vec_store_full_rev (Type Reg MemFlags Value Offset32) SideEffectNoResult)
2711
+
2712
+ ;; Full-vector byte-reversed store via single instruction on z15.
2713
+ (rule 1 (vec_store_full_rev (vxrs_ext2_enabled) val flags addr offset)
2714
+ (vec_storerev val (lower_address flags addr offset)))
2715
+
2716
+ ;; Full-vector byte-reversed store via GPRs on z14.
2717
+ (rule (vec_store_full_rev (vxrs_ext2_disabled) val flags addr offset)
2718
+ (let ((lo_addr MemArg (lower_address_bias flags addr offset 0))
2719
+ (hi_addr MemArg (lower_address_bias flags addr offset 8))
2720
+ (lo_val Reg (vec_extract_lane $I64X2 val 1 (zero_reg)))
2721
+ (hi_val Reg (vec_extract_lane $I64X2 val 0 (zero_reg))))
2722
+ (side_effect_concat (storerev64 lo_val lo_addr)
2723
+ (storerev64 hi_val hi_addr))))
2724
+
2725
+
2726
+ ;; Helper to perform an element-wise byte-reversed store.
2727
+ (decl vec_store_byte_rev (Type Reg MemFlags Value Offset32) SideEffectNoResult)
2728
+
2729
+ ;; Element-wise byte-reversed 1x128-bit store is a full byte-reversed store.
2730
+ (rule -1 (vec_store_byte_rev $I128 val flags addr offset)
2731
+ (vec_store_full_rev $I128 val flags addr offset))
2732
+
2733
+ ;; Element-wise byte-reversed 16x8-bit store is a direct store.
2734
+ (rule (vec_store_byte_rev (multi_lane 8 16) val flags addr offset)
2735
+ (vec_store val (lower_address flags addr offset)))
2736
+
2737
+ ;; Element-wise byte-reversed store via single instruction on z15.
2738
+ (rule 1 (vec_store_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 64 2))
2739
+ val flags addr offset)
2740
+ (vec_store_byte64rev val (lower_address flags addr offset)))
2741
+ (rule 1 (vec_store_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 32 4))
2742
+ val flags addr offset)
2743
+ (vec_store_byte32rev val (lower_address flags addr offset)))
2744
+ (rule 1 (vec_store_byte_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 16 8))
2745
+ val flags addr offset)
2746
+ (vec_store_byte16rev val (lower_address flags addr offset)))
2747
+
2748
+ ;; Element-wise byte-reversed load as element-swapped byte-reversed store on z14.
2749
+ (rule (vec_store_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 64 2))
2750
+ val flags addr offset)
2751
+ (vec_store_full_rev ty (vec_elt_rev ty val) flags addr offset))
2752
+ (rule (vec_store_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 32 4))
2753
+ val flags addr offset)
2754
+ (vec_store_full_rev ty (vec_elt_rev ty val) flags addr offset))
2755
+ (rule (vec_store_byte_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 16 8))
2756
+ val flags addr offset)
2757
+ (vec_store_full_rev ty (vec_elt_rev ty val) flags addr offset))
2758
+
2759
+
2760
+ ;; Helper to perform an element-reversed store.
2761
+ (decl vec_store_elt_rev (Type Reg MemFlags Value Offset32) SideEffectNoResult)
2762
+
2763
+ ;; Element-reversed 1x128-bit store is a direct store.
2764
+ (rule -1 (vec_store_elt_rev $I128 val flags addr offset)
2765
+ (vec_store val (lower_address flags addr offset)))
2766
+
2767
+ ;; Element-reversed 16x8-bit store is a full byte-reversed store.
2768
+ (rule (vec_store_elt_rev ty @ (multi_lane 8 16) val flags addr offset)
2769
+ (vec_store_full_rev ty val flags addr offset))
2770
+
2771
+ ;; Element-reversed store via single instruction on z15.
2772
+ (rule 1 (vec_store_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 64 2))
2773
+ val flags addr offset)
2774
+ (vec_store_elt64rev val (lower_address flags addr offset)))
2775
+ (rule 1 (vec_store_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 32 4))
2776
+ val flags addr offset)
2777
+ (vec_store_elt32rev val (lower_address flags addr offset)))
2778
+ (rule 1 (vec_store_elt_rev (and (vxrs_ext2_enabled) ty @ (multi_lane 16 8))
2779
+ val flags addr offset)
2780
+ (vec_store_elt16rev val (lower_address flags addr offset)))
2781
+
2782
+ ;; Element-reversed store as element-swapped direct store on z14.
2783
+ (rule (vec_store_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 64 2))
2784
+ val flags addr offset)
2785
+ (vec_store (vec_elt_rev ty val) (lower_address flags addr offset)))
2786
+ (rule (vec_store_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 32 4))
2787
+ val flags addr offset)
2788
+ (vec_store (vec_elt_rev ty val) (lower_address flags addr offset)))
2789
+ (rule (vec_store_elt_rev (and (vxrs_ext2_disabled) ty @ (multi_lane 16 8))
2790
+ val flags addr offset)
2791
+ (vec_store (vec_elt_rev ty val) (lower_address flags addr offset)))
2792
+
2793
+
2794
+ ;;;; Rules for 8-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2795
+
2796
+ ;; Main `istore8` lowering entry point, dispatching to the helper.
2797
+ (rule (lower (istore8 flags val addr offset))
2798
+ (side_effect (istore8_impl flags val addr offset)))
2799
+
2800
+ ;; Helper to store 8-bit integer types.
2801
+ (decl istore8_impl (MemFlags Value Value Offset32) SideEffectNoResult)
2802
+
2803
+ ;; Store 8-bit integer types, register input.
2804
+ (rule (istore8_impl flags val addr offset)
2805
+ (store8 (put_in_reg val) (lower_address flags addr offset)))
2806
+
2807
+ ;; Store 8-bit integer types, immediate input.
2808
+ (rule 1 (istore8_impl flags (u8_from_value imm) addr offset)
2809
+ (store8_imm imm (lower_address flags addr offset)))
2810
+
2811
+
2812
+ ;;;; Rules for 16-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2813
+
2814
+ ;; Main `istore16` lowering entry point, dispatching to the helper.
2815
+ (rule (lower (istore16 flags val addr offset))
2816
+ (side_effect (istore16_impl flags val addr offset)))
2817
+
2818
+ ;; Helper to store 16-bit integer types.
2819
+ (decl istore16_impl (MemFlags Value Value Offset32) SideEffectNoResult)
2820
+
2821
+ ;; Store 16-bit big-endian integer types, register input.
2822
+ (rule 2 (istore16_impl flags @ (bigendian) val addr offset)
2823
+ (store16 (put_in_reg val) (lower_address flags addr offset)))
2824
+
2825
+ ;; Store 16-bit little-endian integer types, register input.
2826
+ (rule 0 (istore16_impl flags @ (littleendian) val addr offset)
2827
+ (storerev16 (put_in_reg val) (lower_address flags addr offset)))
2828
+
2829
+ ;; Store 16-bit big-endian integer types, immediate input.
2830
+ (rule 3 (istore16_impl flags @ (bigendian) (i16_from_value imm) addr offset)
2831
+ (store16_imm imm (lower_address flags addr offset)))
2832
+
2833
+ ;; Store 16-bit little-endian integer types, immediate input.
2834
+ (rule 1 (istore16_impl flags @ (littleendian) (i16_from_swapped_value imm) addr offset)
2835
+ (store16_imm imm (lower_address flags addr offset)))
2836
+
2837
+
2838
+ ;;;; Rules for 32-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2839
+
2840
+ ;; Main `istore32` lowering entry point, dispatching to the helper.
2841
+ (rule (lower (istore32 flags val addr offset))
2842
+ (side_effect (istore32_impl flags val addr offset)))
2843
+
2844
+ ;; Helper to store 32-bit integer types.
2845
+ (decl istore32_impl (MemFlags Value Value Offset32) SideEffectNoResult)
2846
+
2847
+ ;; Store 32-bit big-endian integer types, register input.
2848
+ (rule 1 (istore32_impl flags @ (bigendian) val addr offset)
2849
+ (store32 (put_in_reg val) (lower_address flags addr offset)))
2850
+
2851
+ ;; Store 32-bit big-endian integer types, immediate input.
2852
+ (rule 2 (istore32_impl flags @ (bigendian) (i16_from_value imm) addr offset)
2853
+ (store32_simm16 imm (lower_address flags addr offset)))
2854
+
2855
+ ;; Store 32-bit little-endian integer types.
2856
+ (rule 0 (istore32_impl flags @ (littleendian) val addr offset)
2857
+ (storerev32 (put_in_reg val) (lower_address flags addr offset)))
2858
+
2859
+
2860
+ ;;;; Rules for 64-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2861
+
2862
+ ;; Helper to store 64-bit integer types.
2863
+ (decl istore64_impl (MemFlags Value Value Offset32) SideEffectNoResult)
2864
+
2865
+ ;; Store 64-bit big-endian integer types, register input.
2866
+ (rule 1 (istore64_impl flags @ (bigendian) val addr offset)
2867
+ (store64 (put_in_reg val) (lower_address flags addr offset)))
2868
+
2869
+ ;; Store 64-bit big-endian integer types, immediate input.
2870
+ (rule 2 (istore64_impl flags @ (bigendian) (i16_from_value imm) addr offset)
2871
+ (store64_simm16 imm (lower_address flags addr offset)))
2872
+
2873
+ ;; Store 64-bit little-endian integer types.
2874
+ (rule 0 (istore64_impl flags @ (littleendian) val addr offset)
2875
+ (storerev64 (put_in_reg val) (lower_address flags addr offset)))
2876
+
2877
+
2878
+ ;;;; Rules for `atomic_rmw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2879
+
2880
+ ;; Atomic operations that do not require a compare-and-swap loop.
2881
+
2882
+ ;; Atomic AND for 32/64-bit big-endian types, using a single instruction.
2883
+ (rule 1 (lower (has_type (ty_32_or_64 ty)
2884
+ (atomic_rmw flags @ (bigendian) (AtomicRmwOp.And) addr src)))
2885
+ (atomic_rmw_and ty (put_in_reg src)
2886
+ (lower_address flags addr (zero_offset))))
2887
+
2888
+ ;; Atomic AND for 32/64-bit big-endian types, using byte-swapped input/output.
2889
+ (rule (lower (has_type (ty_32_or_64 ty)
2890
+ (atomic_rmw flags @ (littleendian) (AtomicRmwOp.And) addr src)))
2891
+ (bswap_reg ty (atomic_rmw_and ty (bswap_reg ty (put_in_reg src))
2892
+ (lower_address flags addr (zero_offset)))))
2893
+
2894
+ ;; Atomic OR for 32/64-bit big-endian types, using a single instruction.
2895
+ (rule 1 (lower (has_type (ty_32_or_64 ty)
2896
+ (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Or) addr src)))
2897
+ (atomic_rmw_or ty (put_in_reg src)
2898
+ (lower_address flags addr (zero_offset))))
2899
+
2900
+ ;; Atomic OR for 32/64-bit little-endian types, using byte-swapped input/output.
2901
+ (rule (lower (has_type (ty_32_or_64 ty)
2902
+ (atomic_rmw flags @ (littleendian) (AtomicRmwOp.Or) addr src)))
2903
+ (bswap_reg ty (atomic_rmw_or ty (bswap_reg ty (put_in_reg src))
2904
+ (lower_address flags addr (zero_offset)))))
2905
+
2906
+ ;; Atomic XOR for 32/64-bit big-endian types, using a single instruction.
2907
+ (rule 1 (lower (has_type (ty_32_or_64 ty)
2908
+ (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Xor) addr src)))
2909
+ (atomic_rmw_xor ty (put_in_reg src)
2910
+ (lower_address flags addr (zero_offset))))
2911
+
2912
+ ;; Atomic XOR for 32/64-bit little-endian types, using byte-swapped input/output.
2913
+ (rule (lower (has_type (ty_32_or_64 ty)
2914
+ (atomic_rmw flags @ (littleendian) (AtomicRmwOp.Xor) addr src)))
2915
+ (bswap_reg ty (atomic_rmw_xor ty (bswap_reg ty (put_in_reg src))
2916
+ (lower_address flags addr (zero_offset)))))
2917
+
2918
+ ;; Atomic ADD for 32/64-bit big-endian types, using a single instruction.
2919
+ (rule (lower (has_type (ty_32_or_64 ty)
2920
+ (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Add) addr src)))
2921
+ (atomic_rmw_add ty (put_in_reg src)
2922
+ (lower_address flags addr (zero_offset))))
2923
+
2924
+ ;; Atomic SUB for 32/64-bit big-endian types, using atomic ADD with negated input.
2925
+ (rule (lower (has_type (ty_32_or_64 ty)
2926
+ (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Sub) addr src)))
2927
+ (atomic_rmw_add ty (neg_reg ty (put_in_reg src))
2928
+ (lower_address flags addr (zero_offset))))
2929
+
2930
+
2931
+ ;; Atomic operations that require a compare-and-swap loop.
2932
+
2933
+ ;; Operations for 32/64-bit types can use a fullword compare-and-swap loop.
2934
+ (rule -1 (lower (has_type (ty_32_or_64 ty) (atomic_rmw flags op addr src)))
2935
+ (let ((src_reg Reg (put_in_reg src))
2936
+ (addr_reg Reg (put_in_reg addr))
2937
+ ;; Create body of compare-and-swap loop.
2938
+ (ib VecMInstBuilder (inst_builder_new))
2939
+ (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
2940
+ (val1 Reg (atomic_rmw_body ib ty flags op
2941
+ (casloop_tmp_reg) val0 src_reg)))
2942
+ ;; Emit compare-and-swap loop and extract final result.
2943
+ (casloop ib ty flags addr_reg val1)))
2944
+
2945
+ ;; Operations for 8/16-bit types must operate on the surrounding aligned word.
2946
+ (rule -2 (lower (has_type (ty_8_or_16 ty) (atomic_rmw flags op addr src)))
2947
+ (let ((src_reg Reg (put_in_reg src))
2948
+ (addr_reg Reg (put_in_reg addr))
2949
+ ;; Prepare access to surrounding aligned word.
2950
+ (bitshift Reg (casloop_bitshift addr_reg))
2951
+ (aligned_addr Reg (casloop_aligned_addr addr_reg))
2952
+ ;; Create body of compare-and-swap loop.
2953
+ (ib VecMInstBuilder (inst_builder_new))
2954
+ (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
2955
+ (val1 Reg (casloop_rotate_in ib ty flags bitshift val0))
2956
+ (val2 Reg (atomic_rmw_body ib ty flags op
2957
+ (casloop_tmp_reg) val1 src_reg))
2958
+ (val3 Reg (casloop_rotate_out ib ty flags bitshift val2)))
2959
+ ;; Emit compare-and-swap loop and extract final result.
2960
+ (casloop_subword ib ty flags aligned_addr bitshift val3)))
2961
+
2962
+ ;; Loop bodies for atomic read-modify-write operations.
2963
+ (decl atomic_rmw_body (VecMInstBuilder Type MemFlags AtomicRmwOp
2964
+ WritableReg Reg Reg) Reg)
2965
+
2966
+ ;; Loop bodies for 32-/64-bit atomic XCHG operations.
2967
+ ;; Simply use the source (possibly byte-swapped) as new target value.
2968
+ (rule 2 (atomic_rmw_body ib (ty_32_or_64 ty) (bigendian)
2969
+ (AtomicRmwOp.Xchg) tmp val src)
2970
+ src)
2971
+ (rule 1 (atomic_rmw_body ib (ty_32_or_64 ty) (littleendian)
2972
+ (AtomicRmwOp.Xchg) tmp val src)
2973
+ (bswap_reg ty src))
2974
+
2975
+ ;; Loop bodies for 32-/64-bit atomic NAND operations.
2976
+ ;; On z15 this can use the NN(G)RK instruction. On z14, perform an And
2977
+ ;; operation and invert the result. In the little-endian case, we can
2978
+ ;; simply byte-swap the source operand.
2979
+ (rule 4 (atomic_rmw_body ib (and (mie2_enabled) (ty_32_or_64 ty)) (bigendian)
2980
+ (AtomicRmwOp.Nand) tmp val src)
2981
+ (push_alu_reg ib (aluop_not_and ty) tmp val src))
2982
+ (rule 3 (atomic_rmw_body ib (and (mie2_enabled) (ty_32_or_64 ty)) (littleendian)
2983
+ (AtomicRmwOp.Nand) tmp val src)
2984
+ (push_alu_reg ib (aluop_not_and ty) tmp val (bswap_reg ty src)))
2985
+ (rule 2 (atomic_rmw_body ib (and (mie2_disabled) (ty_32_or_64 ty)) (bigendian)
2986
+ (AtomicRmwOp.Nand) tmp val src)
2987
+ (push_not_reg ib ty tmp
2988
+ (push_alu_reg ib (aluop_and ty) tmp val src)))
2989
+ (rule 1 (atomic_rmw_body ib (and (mie2_disabled) (ty_32_or_64 ty)) (littleendian)
2990
+ (AtomicRmwOp.Nand) tmp val src)
2991
+ (push_not_reg ib ty tmp
2992
+ (push_alu_reg ib (aluop_and ty) tmp val (bswap_reg ty src))))
2993
+
2994
+ ;; Loop bodies for 8-/16-bit atomic bit operations.
2995
+ ;; These use the "rotate-then-<op>-selected bits" family of instructions.
2996
+ ;; For the Nand operation, we again perform And and invert the result.
2997
+ (rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Xchg) tmp val src)
2998
+ (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Insert) tmp val src))
2999
+ (rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.And) tmp val src)
3000
+ (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.And) tmp val src))
3001
+ (rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Or) tmp val src)
3002
+ (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Or) tmp val src))
3003
+ (rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Xor) tmp val src)
3004
+ (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Xor) tmp val src))
3005
+ (rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Nand) tmp val src)
3006
+ (atomic_rmw_body_invert ib ty flags tmp
3007
+ (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.And) tmp val src)))
3008
+
3009
+ ;; RxSBG subword operation.
3010
+ (decl atomic_rmw_body_rxsbg (VecMInstBuilder Type MemFlags RxSBGOp
3011
+ WritableReg Reg Reg) Reg)
3012
+ ;; 8-bit case: use the low byte of "src" and the high byte of "val".
3013
+ (rule (atomic_rmw_body_rxsbg ib $I8 _ op tmp val src)
3014
+ (push_rxsbg ib op tmp val src 32 40 24))
3015
+ ;; 16-bit big-endian case: use the low two bytes of "src" and the
3016
+ ;; high two bytes of "val".
3017
+ (rule 1 (atomic_rmw_body_rxsbg ib $I16 (bigendian) op tmp val src)
3018
+ (push_rxsbg ib op tmp val src 32 48 16))
3019
+ ;; 16-bit little-endian case: use the low two bytes of "src", byte-swapped
3020
+ ;; so they end up in the high two bytes, and the low two bytes of "val".
3021
+ (rule (atomic_rmw_body_rxsbg ib $I16 (littleendian) op tmp val src)
3022
+ (push_rxsbg ib op tmp val (bswap_reg $I32 src) 48 64 -16))
3023
+
3024
+ ;; Invert a subword.
3025
+ (decl atomic_rmw_body_invert (VecMInstBuilder Type MemFlags WritableReg Reg) Reg)
3026
+ ;; 8-bit case: invert the high byte.
3027
+ (rule (atomic_rmw_body_invert ib $I8 _ tmp val)
3028
+ (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xff000000 0)))
3029
+ ;; 16-bit big-endian case: invert the two high bytes.
3030
+ (rule 1 (atomic_rmw_body_invert ib $I16 (bigendian) tmp val)
3031
+ (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xffff0000 0)))
3032
+ ;; 16-bit little-endian case: invert the two low bytes.
3033
+ (rule (atomic_rmw_body_invert ib $I16 (littleendian) tmp val)
3034
+ (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xffff 0)))
3035
+
3036
+ ;; Loop bodies for atomic ADD/SUB operations.
3037
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Add) tmp val src)
3038
+ (atomic_rmw_body_addsub ib ty flags (aluop_add (ty_ext32 ty)) tmp val src))
3039
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Sub) tmp val src)
3040
+ (atomic_rmw_body_addsub ib ty flags (aluop_sub (ty_ext32 ty)) tmp val src))
3041
+
3042
+ ;; Addition or subtraction operation.
3043
+ (decl atomic_rmw_body_addsub (VecMInstBuilder Type MemFlags ALUOp
3044
+ WritableReg Reg Reg) Reg)
3045
+ ;; 32/64-bit big-endian case: just a regular add/sub operation.
3046
+ (rule 2 (atomic_rmw_body_addsub ib (ty_32_or_64 ty) (bigendian) op tmp val src)
3047
+ (push_alu_reg ib op tmp val src))
3048
+ ;; 32/64-bit little-endian case: byte-swap the value loaded from memory before
3049
+ ;; and after performing the operation in native endianness.
3050
+ (rule 1 (atomic_rmw_body_addsub ib (ty_32_or_64 ty) (littleendian) op tmp val src)
3051
+ (let ((val_swapped Reg (push_bswap_reg ib ty tmp val))
3052
+ (res_swapped Reg (push_alu_reg ib op tmp val_swapped src)))
3053
+ (push_bswap_reg ib ty tmp res_swapped)))
3054
+ ;; 8-bit case: perform a 32-bit addition of the source value shifted by 24 bits
3055
+ ;; to the memory value, which contains the target in its high byte.
3056
+ (rule (atomic_rmw_body_addsub ib $I8 _ op tmp val src)
3057
+ (let ((src_shifted Reg (lshl_imm $I32 src 24)))
3058
+ (push_alu_reg ib op tmp val src_shifted)))
3059
+ ;; 16-bit big-endian case: similar, just shift the source by 16 bits.
3060
+ (rule 3 (atomic_rmw_body_addsub ib $I16 (bigendian) op tmp val src)
3061
+ (let ((src_shifted Reg (lshl_imm $I32 src 16)))
3062
+ (push_alu_reg ib op tmp val src_shifted)))
3063
+ ;; 16-bit little-endian case: the same, but in addition we need to byte-swap
3064
+ ;; the memory value before and after the operation. Since the value was placed
3065
+ ;; in the low two bytes by our standard rotation, we can use a 32-bit byte-swap
3066
+ ;; and the native-endian value will end up in the high bytes where we need it
3067
+ ;; to perform the operation.
3068
+ (rule (atomic_rmw_body_addsub ib $I16 (littleendian) op tmp val src)
3069
+ (let ((src_shifted Reg (lshl_imm $I32 src 16))
3070
+ (val_swapped Reg (push_bswap_reg ib $I32 tmp val))
3071
+ (res_swapped Reg (push_alu_reg ib op tmp val_swapped src_shifted)))
3072
+ (push_bswap_reg ib $I32 tmp res_swapped)))
3073
+
3074
+ ;; Loop bodies for atomic MIN/MAX operations.
3075
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Smin) tmp val src)
3076
+ (atomic_rmw_body_minmax ib ty flags (cmpop_cmps (ty_ext32 ty))
3077
+ (intcc_as_cond (IntCC.SignedLessThan)) tmp val src))
3078
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Smax) tmp val src)
3079
+ (atomic_rmw_body_minmax ib ty flags (cmpop_cmps (ty_ext32 ty))
3080
+ (intcc_as_cond (IntCC.SignedGreaterThan)) tmp val src))
3081
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Umin) tmp val src)
3082
+ (atomic_rmw_body_minmax ib ty flags (cmpop_cmpu (ty_ext32 ty))
3083
+ (intcc_as_cond (IntCC.UnsignedLessThan)) tmp val src))
3084
+ (rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Umax) tmp val src)
3085
+ (atomic_rmw_body_minmax ib ty flags (cmpop_cmpu (ty_ext32 ty))
3086
+ (intcc_as_cond (IntCC.UnsignedGreaterThan)) tmp val src))
3087
+
3088
+ ;; Minimum or maximum operation.
3089
+ (decl atomic_rmw_body_minmax (VecMInstBuilder Type MemFlags CmpOp Cond
3090
+ WritableReg Reg Reg) Reg)
3091
+ ;; 32/64-bit big-endian case: just a comparison followed by a conditional
3092
+ ;; break out of the loop if the memory value does not need to change.
3093
+ ;; If it does need to change, the new value is simply the source operand.
3094
+ (rule 2 (atomic_rmw_body_minmax ib (ty_32_or_64 ty) (bigendian)
3095
+ op cond tmp val src)
3096
+ (let ((_ Reg (push_break_if ib (cmp_rr op src val) (invert_cond cond))))
3097
+ src))
3098
+ ;; 32/64-bit little-endian case: similar, but we need to byte-swap the
3099
+ ;; memory value before the comparison. If we need to store the new value,
3100
+ ;; it also needs to be byte-swapped.
3101
+ (rule 1 (atomic_rmw_body_minmax ib (ty_32_or_64 ty) (littleendian)
3102
+ op cond tmp val src)
3103
+ (let ((val_swapped Reg (push_bswap_reg ib ty tmp val))
3104
+ (_ Reg (push_break_if ib (cmp_rr op src val_swapped)
3105
+ (invert_cond cond))))
3106
+ (push_bswap_reg ib ty tmp src)))
3107
+ ;; 8-bit case: compare the memory value (which contains the target in the
3108
+ ;; high byte) with the source operand shifted by 24 bits. Note that in
3109
+ ;; the case where the high bytes are equal, the comparison may succeed
3110
+ ;; or fail depending on the unrelated low bits of the memory value, and
3111
+ ;; so we either may or may not perform the update. But it would be an
3112
+ ;; update with the same value in any case, so this does not matter.
3113
+ (rule (atomic_rmw_body_minmax ib $I8 _ op cond tmp val src)
3114
+ (let ((src_shifted Reg (lshl_imm $I32 src 24))
3115
+ (_ Reg (push_break_if ib (cmp_rr op src_shifted val)
3116
+ (invert_cond cond))))
3117
+ (push_rxsbg ib (RxSBGOp.Insert) tmp val src_shifted 32 40 0)))
3118
+ ;; 16-bit big-endian case: similar, just shift the source by 16 bits.
3119
+ (rule 3 (atomic_rmw_body_minmax ib $I16 (bigendian) op cond tmp val src)
3120
+ (let ((src_shifted Reg (lshl_imm $I32 src 16))
3121
+ (_ Reg (push_break_if ib (cmp_rr op src_shifted val)
3122
+ (invert_cond cond))))
3123
+ (push_rxsbg ib (RxSBGOp.Insert) tmp val src_shifted 32 48 0)))
3124
+ ;; 16-bit little-endian case: similar, but in addition byte-swap the
3125
+ ;; memory value before and after the operation, like for _addsub_.
3126
+ (rule (atomic_rmw_body_minmax ib $I16 (littleendian) op cond tmp val src)
3127
+ (let ((src_shifted Reg (lshl_imm $I32 src 16))
3128
+ (val_swapped Reg (push_bswap_reg ib $I32 tmp val))
3129
+ (_ Reg (push_break_if ib (cmp_rr op src_shifted val_swapped)
3130
+ (invert_cond cond)))
3131
+ (res_swapped Reg (push_rxsbg ib (RxSBGOp.Insert)
3132
+ tmp val_swapped src_shifted 32 48 0)))
3133
+ (push_bswap_reg ib $I32 tmp res_swapped)))
3134
+
3135
+
3136
+ ;;;; Rules for `atomic_cas` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3137
+
3138
+ ;; 32/64-bit big-endian atomic compare-and-swap instruction.
3139
+ (rule 2 (lower (has_type (ty_32_or_64 ty)
3140
+ (atomic_cas flags @ (bigendian) addr src1 src2)))
3141
+ (atomic_cas_impl ty (put_in_reg src1) (put_in_reg src2)
3142
+ (lower_address flags addr (zero_offset))))
3143
+
3144
+ ;; 32/64-bit little-endian atomic compare-and-swap instruction.
3145
+ ;; Implemented by byte-swapping old/new inputs and the output.
3146
+ (rule 1 (lower (has_type (ty_32_or_64 ty)
3147
+ (atomic_cas flags @ (littleendian) addr src1 src2)))
3148
+ (bswap_reg ty (atomic_cas_impl ty (bswap_reg ty (put_in_reg src1))
3149
+ (bswap_reg ty (put_in_reg src2))
3150
+ (lower_address flags addr (zero_offset)))))
3151
+
3152
+ ;; 8/16-bit atomic compare-and-swap implemented via loop.
3153
+ (rule (lower (has_type (ty_8_or_16 ty) (atomic_cas flags addr src1 src2)))
3154
+ (let ((src1_reg Reg (put_in_reg src1))
3155
+ (src2_reg Reg (put_in_reg src2))
3156
+ (addr_reg Reg (put_in_reg addr))
3157
+ ;; Prepare access to the surrounding aligned word.
3158
+ (bitshift Reg (casloop_bitshift addr_reg))
3159
+ (aligned_addr Reg (casloop_aligned_addr addr_reg))
3160
+ ;; Create body of compare-and-swap loop.
3161
+ (ib VecMInstBuilder (inst_builder_new))
3162
+ (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
3163
+ (val1 Reg (casloop_rotate_in ib ty flags bitshift val0))
3164
+ (val2 Reg (atomic_cas_body ib ty flags
3165
+ (casloop_tmp_reg) val1 src1_reg src2_reg))
3166
+ (val3 Reg (casloop_rotate_out ib ty flags bitshift val2)))
3167
+ ;; Emit compare-and-swap loop and extract final result.
3168
+ (casloop_subword ib ty flags aligned_addr bitshift val3)))
3169
+
3170
+ ;; Emit loop body instructions to perform a subword compare-and-swap.
3171
+ (decl atomic_cas_body (VecMInstBuilder Type MemFlags
3172
+ WritableReg Reg Reg Reg) Reg)
3173
+
3174
+ ;; 8-bit case: "val" contains the value loaded from memory in the high byte.
3175
+ ;; Compare with the comparison value in the low byte of "src1". If unequal,
3176
+ ;; break out of the loop, otherwise replace the target byte in "val" with
3177
+ ;; the low byte of "src2".
3178
+ (rule (atomic_cas_body ib $I8 _ tmp val src1 src2)
3179
+ (let ((_ Reg (push_break_if ib (rxsbg_test (RxSBGOp.Xor) val src1 32 40 24)
3180
+ (intcc_as_cond (IntCC.NotEqual)))))
3181
+ (push_rxsbg ib (RxSBGOp.Insert) tmp val src2 32 40 24)))
3182
+
3183
+ ;; 16-bit big-endian case: Same as above, except with values in the high
3184
+ ;; two bytes of "val" and low two bytes of "src1" and "src2".
3185
+ (rule 1 (atomic_cas_body ib $I16 (bigendian) tmp val src1 src2)
3186
+ (let ((_ Reg (push_break_if ib (rxsbg_test (RxSBGOp.Xor) val src1 32 48 16)
3187
+ (intcc_as_cond (IntCC.NotEqual)))))
3188
+ (push_rxsbg ib (RxSBGOp.Insert) tmp val src2 32 48 16)))
3189
+
3190
+ ;; 16-bit little-endian case: "val" here contains a little-endian value in the
3191
+ ;; *low* two bytes. "src1" and "src2" contain native (i.e. big-endian) values
3192
+ ;; in their low two bytes. Perform the operation in little-endian mode by
3193
+ ;; byte-swapping "src1" and "src" ahead of the loop. Note that this is a
3194
+ ;; 32-bit operation so the little-endian 16-bit values end up in the *high*
3195
+ ;; two bytes of the swapped values.
3196
+ (rule (atomic_cas_body ib $I16 (littleendian) tmp val src1 src2)
3197
+ (let ((src1_swapped Reg (bswap_reg $I32 src1))
3198
+ (src2_swapped Reg (bswap_reg $I32 src2))
3199
+ (_ Reg (push_break_if ib
3200
+ (rxsbg_test (RxSBGOp.Xor) val src1_swapped 48 64 -16)
3201
+ (intcc_as_cond (IntCC.NotEqual)))))
3202
+ (push_rxsbg ib (RxSBGOp.Insert) tmp val src2_swapped 48 64 -16)))
3203
+
3204
+
3205
+ ;;;; Rules for `atomic_load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3206
+
3207
+ ;; Atomic loads can be implemented via regular loads on this platform.
3208
+
3209
+ ;; 8-bit atomic load.
3210
+ (rule (lower (has_type $I8 (atomic_load flags addr)))
3211
+ (zext32_mem $I8 (lower_address flags addr (zero_offset))))
3212
+
3213
+ ;; 16-bit big-endian atomic load.
3214
+ (rule 1 (lower (has_type $I16 (atomic_load flags @ (bigendian) addr)))
3215
+ (zext32_mem $I16 (lower_address flags addr (zero_offset))))
3216
+
3217
+ ;; 16-bit little-endian atomic load.
3218
+ (rule (lower (has_type $I16 (atomic_load flags @ (littleendian) addr)))
3219
+ (loadrev16 (lower_address flags addr (zero_offset))))
3220
+
3221
+ ;; 32-bit big-endian atomic load.
3222
+ (rule 1 (lower (has_type $I32 (atomic_load flags @ (bigendian) addr)))
3223
+ (load32 (lower_address flags addr (zero_offset))))
3224
+
3225
+ ;; 32-bit little-endian atomic load.
3226
+ (rule (lower (has_type $I32 (atomic_load flags @ (littleendian) addr)))
3227
+ (loadrev32 (lower_address flags addr (zero_offset))))
3228
+
3229
+ ;; 64-bit big-endian atomic load.
3230
+ (rule 1 (lower (has_type $I64 (atomic_load flags @ (bigendian) addr)))
3231
+ (load64 (lower_address flags addr (zero_offset))))
3232
+
3233
+ ;; 64-bit little-endian atomic load.
3234
+ (rule (lower (has_type $I64 (atomic_load flags @ (littleendian) addr)))
3235
+ (loadrev64 (lower_address flags addr (zero_offset))))
3236
+
3237
+
3238
+ ;;;; Rules for `atomic_store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3239
+
3240
+ ;; Atomic stores can be implemented via regular stores followed by a fence.
3241
+ (decl atomic_store_impl (SideEffectNoResult) InstOutput)
3242
+ (rule (atomic_store_impl store)
3243
+ (let ((_ InstOutput (side_effect store)))
3244
+ (side_effect (fence_impl))))
3245
+
3246
+ ;; 8-bit atomic store.
3247
+ (rule (lower (atomic_store flags val @ (value_type $I8) addr))
3248
+ (atomic_store_impl (istore8_impl flags val addr (zero_offset))))
3249
+
3250
+ ;; 16-bit atomic store.
3251
+ (rule (lower (atomic_store flags val @ (value_type $I16) addr))
3252
+ (atomic_store_impl (istore16_impl flags val addr (zero_offset))))
3253
+
3254
+ ;; 32-bit atomic store.
3255
+ (rule (lower (atomic_store flags val @ (value_type $I32) addr))
3256
+ (atomic_store_impl (istore32_impl flags val addr (zero_offset))))
3257
+
3258
+ ;; 64-bit atomic store.
3259
+ (rule (lower (atomic_store flags val @ (value_type $I64) addr))
3260
+ (atomic_store_impl (istore64_impl flags val addr (zero_offset))))
3261
+
3262
+
3263
+ ;;;; Rules for `fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3264
+
3265
+ ;; Fence to ensure sequential consistency.
3266
+ (rule (lower (fence))
3267
+ (side_effect (fence_impl)))
3268
+
3269
+
3270
+ ;;;; Rules for `icmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3271
+
3272
+ ;; We want to optimize the typical use of `icmp` (generating an integer 0/1
3273
+ ;; result) followed by some user, like a `select` or a conditional branch.
3274
+ ;; Instead of first generating the integer result and later testing it again,
3275
+ ;; we want to sink the comparison to be performed at the site of use.
3276
+ ;;
3277
+ ;; To enable this, we provide generic helpers that return a `ProducesBool`
3278
+ ;; encapsulating the comparison in question, which can be used by all the
3279
+ ;; above scenarios.
3280
+ ;;
3281
+ ;; N.B. There are specific considerations when sinking a memory load into a
3282
+ ;; comparison. When emitting an `icmp` directly, this can of course be done
3283
+ ;; as usual. However, when we use the `ProducesBool` elsewhere, we need to
3284
+ ;; consider *three* instructions: the load, the `icmp`, and the final user
3285
+ ;; (e.g. a conditional branch). The only way to safely sink the load would
3286
+ ;; be to sink it direct into the final user, which is only possible if there
3287
+ ;; is no *other* user of the `icmp` result. This is not currently being
3288
+ ;; verified by the `SinkableInst` logic, so to be safe we do not perform this
3289
+ ;; optimization at all.
3290
+ ;;
3291
+ ;; The generic `icmp_val` helper therefore has a flag indicating whether
3292
+ ;; it is being invoked in a context where it is safe to sink memory loads
3293
+ ;; (e.g. when directly emitting an `icmp`), or whether it is not (e.g. when
3294
+ ;; sinking the `icmp` result into a conditional branch or select).
3295
+
3296
+ ;; Main `icmp` entry point. Generate a `ProducesBool` capturing the
3297
+ ;; integer comparison and immediately lower it to a 0/1 integer result.
3298
+ ;; In this case, it is safe to sink memory loads.
3299
+ (rule -1 (lower (has_type (fits_in_64 ty) (icmp int_cc x y)))
3300
+ (lower_bool ty (icmp_val $true int_cc x y)))
3301
+
3302
+
3303
+ ;; Return a `ProducesBool` to implement any integer comparison.
3304
+ ;; The first argument is a flag to indicate whether it is safe to sink
3305
+ ;; memory loads as discussed above.
3306
+ (decl icmp_val (bool IntCC Value Value) ProducesBool)
3307
+
3308
+ ;; Dispatch for signed comparisons.
3309
+ (rule -1 (icmp_val allow_mem int_cc @ (signed) x @ (value_type (fits_in_64 _)) y)
3310
+ (bool (icmps_val allow_mem x y) (intcc_as_cond int_cc)))
3311
+ ;; Dispatch for unsigned comparisons.
3312
+ (rule -2 (icmp_val allow_mem int_cc @ (unsigned) x @ (value_type (fits_in_64 _)) y)
3313
+ (bool (icmpu_val allow_mem x y) (intcc_as_cond int_cc)))
3314
+
3315
+
3316
+ ;; Return a `ProducesBool` to implement signed integer comparisons.
3317
+ (decl icmps_val (bool Value Value) ProducesFlags)
3318
+
3319
+ ;; Compare (signed) two registers.
3320
+ (rule 0 (icmps_val _ x @ (value_type (fits_in_64 ty)) y)
3321
+ (icmps_reg (ty_ext32 ty) (put_in_reg_sext32 x) (put_in_reg_sext32 y)))
3322
+
3323
+ ;; Compare (signed) a register and a sign-extended register.
3324
+ (rule 3 (icmps_val _ x @ (value_type (fits_in_64 ty)) (sext32_value y))
3325
+ (icmps_reg_sext32 ty x y))
3326
+
3327
+ ;; Compare (signed) a register and an immediate.
3328
+ (rule 2 (icmps_val _ x @ (value_type (fits_in_64 ty)) (i16_from_value y))
3329
+ (icmps_simm16 (ty_ext32 ty) (put_in_reg_sext32 x) y))
3330
+ (rule 1 (icmps_val _ x @ (value_type (fits_in_64 ty)) (i32_from_value y))
3331
+ (icmps_simm32 (ty_ext32 ty) (put_in_reg_sext32 x) y))
3332
+
3333
+ ;; Compare (signed) a register and memory (32/64-bit types).
3334
+ (rule 4 (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_32_64 y))
3335
+ (icmps_mem ty x (sink_load y)))
3336
+
3337
+ ;; Compare (signed) a register and memory (16-bit types).
3338
+ (rule 5 (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_16 y))
3339
+ (icmps_mem_sext16 (ty_ext32 ty) (put_in_reg_sext32 x) (sink_load y)))
3340
+
3341
+ ;; Compare (signed) a register and sign-extended memory.
3342
+ (rule 4 (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_sload16 y))
3343
+ (icmps_mem_sext16 ty x (sink_sload16 y)))
3344
+ (rule 4 (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_sload32 y))
3345
+ (icmps_mem_sext32 ty x (sink_sload32 y)))
3346
+
3347
+
3348
+ ;; Return a `ProducesBool` to implement unsigned integer comparisons.
3349
+ (decl icmpu_val (bool Value Value) ProducesFlags)
3350
+
3351
+ ;; Compare (unsigned) two registers.
3352
+ (rule (icmpu_val _ x @ (value_type (fits_in_64 ty)) y)
3353
+ (icmpu_reg (ty_ext32 ty) (put_in_reg_zext32 x) (put_in_reg_zext32 y)))
3354
+
3355
+ ;; Compare (unsigned) a register and a sign-extended register.
3356
+ (rule 1 (icmpu_val _ x @ (value_type (fits_in_64 ty)) (zext32_value y))
3357
+ (icmpu_reg_zext32 ty x y))
3358
+
3359
+ ;; Compare (unsigned) a register and an immediate.
3360
+ (rule 2 (icmpu_val _ x @ (value_type (fits_in_64 ty)) (u32_from_value y))
3361
+ (icmpu_uimm32 (ty_ext32 ty) (put_in_reg_zext32 x) y))
3362
+
3363
+ ;; Compare (unsigned) a register and memory (32/64-bit types).
3364
+ (rule 4 (icmpu_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_32_64 y))
3365
+ (icmpu_mem ty x (sink_load y)))
3366
+
3367
+ ;; Compare (unsigned) a register and memory (16-bit types).
3368
+ ;; Note that the ISA only provides instructions with a PC-relative memory
3369
+ ;; address here, so we need to check whether the sinkable load matches this.
3370
+ (rule 3 (icmpu_val $true x @ (value_type (fits_in_64 ty))
3371
+ (sinkable_load_16 ld))
3372
+ (if-let y (load_sym ld))
3373
+ (icmpu_mem_zext16 (ty_ext32 ty) (put_in_reg_zext32 x) (sink_load y)))
3374
+
3375
+ ;; Compare (unsigned) a register and zero-extended memory.
3376
+ ;; Note that the ISA only provides instructions with a PC-relative memory
3377
+ ;; address here, so we need to check whether the sinkable load matches this.
3378
+ (rule 3 (icmpu_val $true x @ (value_type (fits_in_64 ty))
3379
+ (sinkable_uload16 ld))
3380
+ (if-let y (uload16_sym ld))
3381
+ (icmpu_mem_zext16 ty x (sink_uload16 y)))
3382
+ (rule 3 (icmpu_val $true x @ (value_type (fits_in_64 ty)) (sinkable_uload32 y))
3383
+ (icmpu_mem_zext32 ty x (sink_uload32 y)))
3384
+
3385
+
3386
+ ;; Compare 128-bit integers for equality.
3387
+ ;; Implemented via element-wise comparison using the all-element true CC flag.
3388
+ (rule (icmp_val _ (IntCC.Equal) x @ (value_type (vr128_ty _)) y)
3389
+ (bool (vec_cmpeqs $I64X2 x y)
3390
+ (floatcc_as_cond (FloatCC.Equal))))
3391
+ (rule (icmp_val _ (IntCC.NotEqual) x @ (value_type (vr128_ty _)) y)
3392
+ (bool (vec_cmpeqs $I64X2 x y)
3393
+ (floatcc_as_cond (FloatCC.NotEqual))))
3394
+
3395
+ ;; Compare (signed) 128-bit integers for relational inequality.
3396
+ ;; Implemented via synthetic instruction using VECG and VCHLGS.
3397
+ (rule (icmp_val _ (IntCC.SignedGreaterThan) x @ (value_type (vr128_ty ty)) y)
3398
+ (vec_int128_scmphi x y))
3399
+ (rule (icmp_val _ (IntCC.SignedLessThan) x @ (value_type (vr128_ty ty)) y)
3400
+ (vec_int128_scmphi y x))
3401
+ (rule (icmp_val _ (IntCC.SignedGreaterThanOrEqual) x @ (value_type (vr128_ty ty)) y)
3402
+ (invert_bool (vec_int128_scmphi y x)))
3403
+ (rule (icmp_val _ (IntCC.SignedLessThanOrEqual) x @ (value_type (vr128_ty ty)) y)
3404
+ (invert_bool (vec_int128_scmphi x y)))
3405
+
3406
+ ;; Compare (unsigned) 128-bit integers for relational inequality.
3407
+ ;; Implemented via synthetic instruction using VECLG and VCHLGS.
3408
+ (rule (icmp_val _ (IntCC.UnsignedGreaterThan) x @ (value_type (vr128_ty ty)) y)
3409
+ (vec_int128_ucmphi x y))
3410
+ (rule (icmp_val _ (IntCC.UnsignedLessThan) x @ (value_type (vr128_ty ty)) y)
3411
+ (vec_int128_ucmphi y x))
3412
+ (rule (icmp_val _ (IntCC.UnsignedGreaterThanOrEqual) x @ (value_type (vr128_ty ty)) y)
3413
+ (invert_bool (vec_int128_ucmphi y x)))
3414
+ (rule (icmp_val _ (IntCC.UnsignedLessThanOrEqual) x @ (value_type (vr128_ty ty)) y)
3415
+ (invert_bool (vec_int128_ucmphi x y)))
3416
+
3417
+
3418
+ ;; Vector `icmp` produces a boolean vector.
3419
+ ;; We need to handle the various IntCC flags separately here.
3420
+
3421
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.Equal) x y)))
3422
+ (vec_cmpeq ty x y))
3423
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.NotEqual) x y)))
3424
+ (vec_not ty (vec_cmpeq ty x y)))
3425
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.SignedGreaterThan) x y)))
3426
+ (vec_cmph ty x y))
3427
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.SignedLessThanOrEqual) x y)))
3428
+ (vec_not ty (vec_cmph ty x y)))
3429
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.SignedLessThan) x y)))
3430
+ (vec_cmph ty y x))
3431
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.SignedGreaterThanOrEqual) x y)))
3432
+ (vec_not ty (vec_cmph ty y x)))
3433
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.UnsignedGreaterThan) x y)))
3434
+ (vec_cmphl ty x y))
3435
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.UnsignedLessThanOrEqual) x y)))
3436
+ (vec_not ty (vec_cmphl ty x y)))
3437
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.UnsignedLessThan) x y)))
3438
+ (vec_cmphl ty y x))
3439
+ (rule (lower (has_type (ty_vec128 ty) (icmp (IntCC.UnsignedGreaterThanOrEqual) x y)))
3440
+ (vec_not ty (vec_cmphl ty y x)))
3441
+
3442
+
3443
+ ;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3444
+
3445
+ ;; Main `fcmp` entry point. Generate a `ProducesBool` capturing the
3446
+ ;; integer comparison and immediately lower it to a 0/1 integer result.
3447
+ (rule -1 (lower (has_type (fits_in_64 ty) (fcmp float_cc x y)))
3448
+ (lower_bool ty (fcmp_val float_cc x y)))
3449
+
3450
+ ;; Return a `ProducesBool` to implement any floating-point comparison.
3451
+ (decl fcmp_val (FloatCC Value Value) ProducesBool)
3452
+ (rule (fcmp_val float_cc x @ (value_type ty) y)
3453
+ (bool (fcmp_reg ty x y)
3454
+ (floatcc_as_cond float_cc)))
3455
+
3456
+ ;; Vector `fcmp` produces a boolean vector.
3457
+ ;; We need to handle the various FloatCC flags separately here.
3458
+
3459
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.Equal) x y)))
3460
+ (vec_fcmpeq ty x y))
3461
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.NotEqual) x y)))
3462
+ (vec_not ty (vec_fcmpeq ty x y)))
3463
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.GreaterThan) x y)))
3464
+ (vec_fcmph ty x y))
3465
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.UnorderedOrLessThanOrEqual) x y)))
3466
+ (vec_not ty (vec_fcmph ty x y)))
3467
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.GreaterThanOrEqual) x y)))
3468
+ (vec_fcmphe ty x y))
3469
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.UnorderedOrLessThan) x y)))
3470
+ (vec_not ty (vec_fcmphe ty x y)))
3471
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.LessThan) x y)))
3472
+ (vec_fcmph ty y x))
3473
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) x y)))
3474
+ (vec_not ty (vec_fcmph ty y x)))
3475
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.LessThanOrEqual) x y)))
3476
+ (vec_fcmphe ty y x))
3477
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.UnorderedOrGreaterThan) x y)))
3478
+ (vec_not ty (vec_fcmphe ty y x)))
3479
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.Ordered) x y)))
3480
+ (vec_or ty (vec_fcmphe ty x y) (vec_fcmphe ty y x)))
3481
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.Unordered) x y)))
3482
+ (vec_not_or ty (vec_fcmphe ty x y) (vec_fcmphe ty y x)))
3483
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.OrderedNotEqual) x y)))
3484
+ (vec_or ty (vec_fcmph ty x y) (vec_fcmph ty y x)))
3485
+ (rule (lower (has_type (ty_vec128 ty) (fcmp (FloatCC.UnorderedOrEqual) x y)))
3486
+ (vec_not_or ty (vec_fcmph ty x y) (vec_fcmph ty y x)))
3487
+
3488
+
3489
+ ;;;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3490
+
3491
+ ;; Main `vall_true` entry point. Generate a `ProducesBool` capturing the
3492
+ ;; comparison and immediately lower it to a 0/1 integer result.
3493
+ (rule (lower (has_type (fits_in_64 ty) (vall_true x)))
3494
+ (lower_bool ty (vall_true_val x)))
3495
+
3496
+ ;; Return a `ProducesBool` to implement `vall_true`.
3497
+ (decl vall_true_val (Value) ProducesBool)
3498
+ (rule -1 (vall_true_val x @ (value_type ty))
3499
+ (bool (vec_cmpeqs ty x (vec_imm ty 0))
3500
+ (floatcc_as_cond (FloatCC.Unordered))))
3501
+
3502
+ ;; Short-circuit `vall_true` on the result of a `icmp`.
3503
+ (rule (vall_true_val (has_type ty (icmp (IntCC.Equal) x y)))
3504
+ (bool (vec_cmpeqs ty x y)
3505
+ (floatcc_as_cond (FloatCC.Equal))))
3506
+ (rule (vall_true_val (has_type ty (icmp (IntCC.NotEqual) x y)))
3507
+ (bool (vec_cmpeqs ty x y)
3508
+ (floatcc_as_cond (FloatCC.Unordered))))
3509
+ (rule (vall_true_val (has_type ty (icmp (IntCC.SignedGreaterThan) x y)))
3510
+ (bool (vec_cmphs ty x y)
3511
+ (floatcc_as_cond (FloatCC.Equal))))
3512
+ (rule (vall_true_val (has_type ty (icmp (IntCC.SignedLessThanOrEqual) x y)))
3513
+ (bool (vec_cmphs ty x y)
3514
+ (floatcc_as_cond (FloatCC.Unordered))))
3515
+ (rule (vall_true_val (has_type ty (icmp (IntCC.SignedLessThan) x y)))
3516
+ (bool (vec_cmphs ty y x)
3517
+ (floatcc_as_cond (FloatCC.Equal))))
3518
+ (rule (vall_true_val (has_type ty (icmp (IntCC.SignedGreaterThanOrEqual) x y)))
3519
+ (bool (vec_cmphs ty y x)
3520
+ (floatcc_as_cond (FloatCC.Unordered))))
3521
+ (rule (vall_true_val (has_type ty (icmp (IntCC.UnsignedGreaterThan) x y)))
3522
+ (bool (vec_cmphls ty x y)
3523
+ (floatcc_as_cond (FloatCC.Equal))))
3524
+ (rule (vall_true_val (has_type ty (icmp (IntCC.UnsignedLessThanOrEqual) x y)))
3525
+ (bool (vec_cmphls ty x y)
3526
+ (floatcc_as_cond (FloatCC.Unordered))))
3527
+ (rule (vall_true_val (has_type ty (icmp (IntCC.UnsignedLessThan) x y)))
3528
+ (bool (vec_cmphls ty y x)
3529
+ (floatcc_as_cond (FloatCC.Equal))))
3530
+ (rule (vall_true_val (has_type ty (icmp (IntCC.UnsignedGreaterThanOrEqual) x y)))
3531
+ (bool (vec_cmphls ty y x)
3532
+ (floatcc_as_cond (FloatCC.Unordered))))
3533
+
3534
+ ;; Short-circuit `vall_true` on the result of a `fcmp` where possible.
3535
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.Equal) x y)))
3536
+ (bool (vec_fcmpeqs ty x y)
3537
+ (floatcc_as_cond (FloatCC.Equal))))
3538
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.NotEqual) x y)))
3539
+ (bool (vec_fcmpeqs ty x y)
3540
+ (floatcc_as_cond (FloatCC.Unordered))))
3541
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.GreaterThan) x y)))
3542
+ (bool (vec_fcmphs ty x y)
3543
+ (floatcc_as_cond (FloatCC.Equal))))
3544
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.UnorderedOrLessThanOrEqual) x y)))
3545
+ (bool (vec_fcmphs ty x y)
3546
+ (floatcc_as_cond (FloatCC.Unordered))))
3547
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.GreaterThanOrEqual) x y)))
3548
+ (bool (vec_fcmphes ty x y)
3549
+ (floatcc_as_cond (FloatCC.Equal))))
3550
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.UnorderedOrLessThan) x y)))
3551
+ (bool (vec_fcmphes ty x y)
3552
+ (floatcc_as_cond (FloatCC.Unordered))))
3553
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.LessThan) x y)))
3554
+ (bool (vec_fcmphs ty y x)
3555
+ (floatcc_as_cond (FloatCC.Equal))))
3556
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) x y)))
3557
+ (bool (vec_fcmphs ty y x)
3558
+ (floatcc_as_cond (FloatCC.Unordered))))
3559
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.LessThanOrEqual) x y)))
3560
+ (bool (vec_fcmphes ty y x)
3561
+ (floatcc_as_cond (FloatCC.Equal))))
3562
+ (rule (vall_true_val (has_type ty (fcmp (FloatCC.UnorderedOrGreaterThan) x y)))
3563
+ (bool (vec_fcmphes ty y x)
3564
+ (floatcc_as_cond (FloatCC.Unordered))))
3565
+
3566
+
3567
+ ;;;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3568
+
3569
+ ;; Main `vany_true` entry point. Generate a `ProducesBool` capturing the
3570
+ ;; comparison and immediately lower it to a 0/1 integer result.
3571
+ (rule (lower (has_type (fits_in_64 ty) (vany_true x)))
3572
+ (lower_bool ty (vany_true_val x)))
3573
+
3574
+ ;; Return a `ProducesBool` to implement `vany_true`.
3575
+ (decl vany_true_val (Value) ProducesBool)
3576
+ (rule -1 (vany_true_val x @ (value_type ty))
3577
+ (bool (vec_cmpeqs ty x (vec_imm ty 0))
3578
+ (floatcc_as_cond (FloatCC.NotEqual))))
3579
+
3580
+ ;; Short-circuit `vany_true` on the result of a `icmp`.
3581
+ (rule (vany_true_val (has_type ty (icmp (IntCC.Equal) x y)))
3582
+ (bool (vec_cmpeqs ty x y)
3583
+ (floatcc_as_cond (FloatCC.Ordered))))
3584
+ (rule (vany_true_val (has_type ty (icmp (IntCC.NotEqual) x y)))
3585
+ (bool (vec_cmpeqs ty x y)
3586
+ (floatcc_as_cond (FloatCC.NotEqual))))
3587
+ (rule (vany_true_val (has_type ty (icmp (IntCC.SignedGreaterThan) x y)))
3588
+ (bool (vec_cmphs ty x y)
3589
+ (floatcc_as_cond (FloatCC.Ordered))))
3590
+ (rule (vany_true_val (has_type ty (icmp (IntCC.SignedLessThanOrEqual) x y)))
3591
+ (bool (vec_cmphs ty x y)
3592
+ (floatcc_as_cond (FloatCC.NotEqual))))
3593
+ (rule (vany_true_val (has_type ty (icmp (IntCC.SignedLessThan) x y)))
3594
+ (bool (vec_cmphs ty y x)
3595
+ (floatcc_as_cond (FloatCC.Ordered))))
3596
+ (rule (vany_true_val (has_type ty (icmp (IntCC.SignedGreaterThanOrEqual) x y)))
3597
+ (bool (vec_cmphs ty y x)
3598
+ (floatcc_as_cond (FloatCC.NotEqual))))
3599
+ (rule (vany_true_val (has_type ty (icmp (IntCC.UnsignedGreaterThan) x y)))
3600
+ (bool (vec_cmphls ty x y)
3601
+ (floatcc_as_cond (FloatCC.Ordered))))
3602
+ (rule (vany_true_val (has_type ty (icmp (IntCC.UnsignedLessThanOrEqual) x y)))
3603
+ (bool (vec_cmphls ty x y)
3604
+ (floatcc_as_cond (FloatCC.NotEqual))))
3605
+ (rule (vany_true_val (has_type ty (icmp (IntCC.UnsignedLessThan) x y)))
3606
+ (bool (vec_cmphls ty y x)
3607
+ (floatcc_as_cond (FloatCC.Ordered))))
3608
+ (rule (vany_true_val (has_type ty (icmp (IntCC.UnsignedGreaterThanOrEqual) x y)))
3609
+ (bool (vec_cmphls ty y x)
3610
+ (floatcc_as_cond (FloatCC.NotEqual))))
3611
+
3612
+ ;; Short-circuit `vany_true` on the result of a `fcmp` where possible.
3613
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.Equal) x y)))
3614
+ (bool (vec_fcmpeqs ty x y)
3615
+ (floatcc_as_cond (FloatCC.Ordered))))
3616
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.NotEqual) x y)))
3617
+ (bool (vec_fcmpeqs ty x y)
3618
+ (floatcc_as_cond (FloatCC.NotEqual))))
3619
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.GreaterThan) x y)))
3620
+ (bool (vec_fcmphs ty x y)
3621
+ (floatcc_as_cond (FloatCC.Ordered))))
3622
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.UnorderedOrLessThanOrEqual) x y)))
3623
+ (bool (vec_fcmphs ty x y)
3624
+ (floatcc_as_cond (FloatCC.NotEqual))))
3625
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.GreaterThanOrEqual) x y)))
3626
+ (bool (vec_fcmphes ty x y)
3627
+ (floatcc_as_cond (FloatCC.Ordered))))
3628
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.UnorderedOrLessThan) x y)))
3629
+ (bool (vec_fcmphes ty x y)
3630
+ (floatcc_as_cond (FloatCC.NotEqual))))
3631
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.LessThan) x y)))
3632
+ (bool (vec_fcmphs ty y x)
3633
+ (floatcc_as_cond (FloatCC.Ordered))))
3634
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) x y)))
3635
+ (bool (vec_fcmphs ty y x)
3636
+ (floatcc_as_cond (FloatCC.NotEqual))))
3637
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.LessThanOrEqual) x y)))
3638
+ (bool (vec_fcmphes ty y x)
3639
+ (floatcc_as_cond (FloatCC.Ordered))))
3640
+ (rule (vany_true_val (has_type ty (fcmp (FloatCC.UnorderedOrGreaterThan) x y)))
3641
+ (bool (vec_fcmphes ty y x)
3642
+ (floatcc_as_cond (FloatCC.NotEqual))))
3643
+
3644
+
3645
+ ;;;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3646
+
3647
+ (rule (lower (vhigh_bits x @ (value_type (multi_lane 8 16))))
3648
+ (if-let (LaneOrder.LittleEndian) (lane_order))
3649
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 0 8 16 24 32 40 48 56
3650
+ 64 72 80 88 96 104 112 120))))
3651
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3652
+ (rule 1 (lower (vhigh_bits x @ (value_type (multi_lane 8 16))))
3653
+ (if-let (LaneOrder.BigEndian) (lane_order))
3654
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 120 112 104 96 88 80 72 64
3655
+ 56 48 40 32 24 16 8 0))))
3656
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3657
+
3658
+ (rule (lower (vhigh_bits x @ (value_type (multi_lane 16 8))))
3659
+ (if-let (LaneOrder.LittleEndian) (lane_order))
3660
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3661
+ 0 16 32 48 64 80 96 112))))
3662
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3663
+ (rule 1 (lower (vhigh_bits x @ (value_type (multi_lane 16 8))))
3664
+ (if-let (LaneOrder.BigEndian) (lane_order))
3665
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3666
+ 112 96 80 64 48 32 16 0))))
3667
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3668
+
3669
+ (rule (lower (vhigh_bits x @ (value_type (multi_lane 32 4))))
3670
+ (if-let (LaneOrder.LittleEndian) (lane_order))
3671
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3672
+ 128 128 128 128 0 32 64 96))))
3673
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3674
+ (rule 1 (lower (vhigh_bits x @ (value_type (multi_lane 32 4))))
3675
+ (if-let (LaneOrder.BigEndian) (lane_order))
3676
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3677
+ 128 128 128 128 96 64 32 0))))
3678
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3679
+
3680
+ (rule (lower (vhigh_bits x @ (value_type (multi_lane 64 2))))
3681
+ (if-let (LaneOrder.LittleEndian) (lane_order))
3682
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3683
+ 128 128 128 128 128 128 0 64))))
3684
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3685
+ (rule 1 (lower (vhigh_bits x @ (value_type (multi_lane 64 2))))
3686
+ (if-let (LaneOrder.BigEndian) (lane_order))
3687
+ (let ((mask Reg (vec_imm $I8X16 (imm8x16 128 128 128 128 128 128 128 128
3688
+ 128 128 128 128 128 128 64 0))))
3689
+ (vec_extract_lane $I64X2 (vec_bitpermute x mask) 0 (zero_reg))))
3690
+
3691
+
3692
+ ;;;; Rules for `is_null` and `is_invalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3693
+
3694
+ ;; Null references are represented by the constant value 0.
3695
+ (rule (lower (has_type $I8 (is_null x @ (value_type $R64))))
3696
+ (lower_bool $I8 (bool (icmps_simm16 $I64 x 0)
3697
+ (intcc_as_cond (IntCC.Equal)))))
3698
+
3699
+
3700
+ ;; Invalid references are represented by the constant value -1.
3701
+ (rule (lower (has_type $I8 (is_invalid x @ (value_type $R64))))
3702
+ (lower_bool $I8 (bool (icmps_simm16 $I64 x -1)
3703
+ (intcc_as_cond (IntCC.Equal)))))
3704
+
3705
+
3706
+ ;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3707
+
3708
+ ;; Return a `ProducesBool` to capture the fact that the input value is nonzero.
3709
+ ;; In the common case where that input is the result of an `icmp` or `fcmp`
3710
+ ;; instruction, directly use that compare. Note that it is not safe to sink
3711
+ ;; memory loads here, see the `icmp` comment.
3712
+ (decl value_nonzero (Value) ProducesBool)
3713
+ (rule (value_nonzero (icmp int_cc x y)) (icmp_val $false int_cc x y))
3714
+ (rule (value_nonzero (fcmp float_cc x y)) (fcmp_val float_cc x y))
3715
+ (rule -1 (value_nonzero val @ (value_type (gpr32_ty ty)))
3716
+ (bool (icmps_simm16 $I32 (put_in_reg_sext32 val) 0)
3717
+ (intcc_as_cond (IntCC.NotEqual))))
3718
+ (rule -2 (value_nonzero val @ (value_type (gpr64_ty ty)))
3719
+ (bool (icmps_simm16 $I64 (put_in_reg val) 0)
3720
+ (intcc_as_cond (IntCC.NotEqual))))
3721
+ (rule -3 (value_nonzero val @ (value_type (vr128_ty ty)))
3722
+ (bool (vec_cmpeqs $I64X2 val (vec_imm $I64X2 0))
3723
+ (floatcc_as_cond (FloatCC.NotEqual))))
3724
+
3725
+ ;; Main `select` entry point. Lower the `value_nonzero` result.
3726
+ (rule (lower (has_type ty (select val_cond val_true val_false)))
3727
+ (select_bool_reg ty (value_nonzero val_cond)
3728
+ (put_in_reg val_true) (put_in_reg val_false)))
3729
+
3730
+
3731
+ ;;;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3732
+
3733
+ ;; We need to guarantee a conditional move instruction. But on this platform
3734
+ ;; this is already the best way to implement select in general, so the
3735
+ ;; implementation of `select_spectre_guard` is identical to `select`.
3736
+ (rule (lower (has_type ty (select_spectre_guard
3737
+ val_cond val_true val_false)))
3738
+ (select_bool_reg ty (value_nonzero val_cond)
3739
+ (put_in_reg val_true) (put_in_reg val_false)))
3740
+
3741
+
3742
+ ;;;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3743
+
3744
+ ;; Unconditional branch. The target is found as first (and only) element in
3745
+ ;; the list of the current block's branch targets passed as `targets`.
3746
+ (rule (lower_branch (jump _) targets)
3747
+ (emit_side_effect (jump_impl (vec_element targets 0))))
3748
+
3749
+
3750
+ ;;;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3751
+
3752
+ ;; Jump table. `targets` contains the default target followed by the
3753
+ ;; list of branch targets per index value.
3754
+ (rule (lower_branch (br_table val_idx _) targets)
3755
+ (let ((idx Reg (put_in_reg_zext64 val_idx))
3756
+ ;; Bounds-check the index and branch to default.
3757
+ ;; This is an internal branch that is not a terminator insn.
3758
+ ;; Instead, the default target is listed a potential target
3759
+ ;; in the final JTSequence, which is the block terminator.
3760
+ (cond ProducesBool
3761
+ (bool (icmpu_uimm32 $I64 idx (vec_length_minus1 targets))
3762
+ (intcc_as_cond (IntCC.UnsignedGreaterThanOrEqual))))
3763
+ (_ Unit (emit_side_effect (oneway_cond_br_bool cond
3764
+ (vec_element targets 0)))))
3765
+ ;; Scale the index by the element size, and then emit the
3766
+ ;; compound instruction that does:
3767
+ ;;
3768
+ ;; larl %r1, <jt-base>
3769
+ ;; agf %r1, 0(%r1, %rScaledIndex)
3770
+ ;; br %r1
3771
+ ;; [jt entries]
3772
+ ;;
3773
+ ;; This must be *one* instruction in the vcode because
3774
+ ;; we cannot allow regalloc to insert any spills/fills
3775
+ ;; in the middle of the sequence; otherwise, the LARL's
3776
+ ;; PC-rel offset to the jumptable would be incorrect.
3777
+ ;; (The alternative is to introduce a relocation pass
3778
+ ;; for inlined jumptables, which is much worse, IMHO.)
3779
+ (emit_side_effect (jt_sequence (lshl_imm $I64 idx 2) targets))))
3780
+
3781
+
3782
+ ;;;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3783
+
3784
+ ;; Two-way conditional branch on nonzero. `targets` contains:
3785
+ ;; - element 0: target if the condition is true (i.e. value is nonzero)
3786
+ ;; - element 1: target if the condition is false (i.e. value is zero)
3787
+ (rule (lower_branch (brif val_cond _ _) targets)
3788
+ (emit_side_effect (cond_br_bool (value_nonzero val_cond)
3789
+ (vec_element targets 0)
3790
+ (vec_element targets 1))))
3791
+
3792
+
3793
+ ;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3794
+
3795
+ (rule (lower (trap trap_code))
3796
+ (side_effect (trap_impl trap_code)))
3797
+
3798
+
3799
+ ;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3800
+
3801
+ (rule (lower (resumable_trap trap_code))
3802
+ (side_effect (trap_impl trap_code)))
3803
+
3804
+
3805
+ ;;;; Rules for `trapz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3806
+
3807
+ (rule (lower (trapz val trap_code))
3808
+ (side_effect (trap_if_bool (invert_bool (value_nonzero val)) trap_code)))
3809
+
3810
+
3811
+ ;;;; Rules for `trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3812
+
3813
+ (rule (lower (trapnz val trap_code))
3814
+ (side_effect (trap_if_bool (value_nonzero val) trap_code)))
3815
+
3816
+
3817
+ ;;;; Rules for `resumable_trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3818
+
3819
+ (rule (lower (resumable_trapnz val trap_code))
3820
+ (side_effect (trap_if_bool (value_nonzero val) trap_code)))
3821
+
3822
+
3823
+ ;;;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3824
+
3825
+ (rule (lower (debugtrap))
3826
+ (side_effect (debugtrap_impl)))
3827
+
3828
+ ;;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3829
+
3830
+ ;; UaddOverflowTrap is implemented via a ADD LOGICAL instruction, which sets the
3831
+ ;; the condition code as follows:
3832
+ ;; 0 Result zero; no carry
3833
+ ;; 1 Result not zero; no carry
3834
+ ;; 2 Result zero; carry
3835
+ ;; 3 Result not zero; carry
3836
+ ;; This means "carry" corresponds to condition code 2 or 3, i.e.
3837
+ ;; a condition mask of 2 | 1.
3838
+ ;;
3839
+ ;; As this does not match any of the encodings used with a normal integer
3840
+ ;; comparsion, this cannot be represented by any IntCC value. We need to
3841
+ ;; remap the IntCC::UnsignedGreaterThan value that we have here as result
3842
+ ;; of the unsigned_add_overflow_condition call to the correct mask.
3843
+
3844
+ (rule 0 (lower (has_type (fits_in_64 ty) (uadd_overflow_trap x y tc)))
3845
+ (with_flags
3846
+ (add_logical_reg_with_flags_paired ty x y)
3847
+ (trap_if_impl (mask_as_cond 3) tc)))
3848
+
3849
+ ;; Add a register an a zero-extended register.
3850
+ (rule 4 (lower (has_type (fits_in_64 ty)
3851
+ (uadd_overflow_trap x (zext32_value y) tc)))
3852
+ (with_flags
3853
+ (add_logical_reg_zext32_with_flags_paired ty x y)
3854
+ (trap_if_impl (mask_as_cond 3) tc)))
3855
+ (rule 8 (lower (has_type (fits_in_64 ty)
3856
+ (uadd_overflow_trap (zext32_value x) y tc)))
3857
+ (with_flags
3858
+ (add_logical_reg_zext32_with_flags_paired ty y x)
3859
+ (trap_if_impl (mask_as_cond 3) tc)))
3860
+
3861
+ ;; Add a register and an immediate
3862
+ (rule 3 (lower (has_type (fits_in_64 ty)
3863
+ (uadd_overflow_trap x (u32_from_value y) tc)))
3864
+ (with_flags
3865
+ (add_logical_zimm32_with_flags_paired ty x y)
3866
+ (trap_if_impl (mask_as_cond 3) tc)))
3867
+ (rule 7 (lower (has_type (fits_in_64 ty)
3868
+ (uadd_overflow_trap (u32_from_value x) y tc)))
3869
+ (with_flags
3870
+ (add_logical_zimm32_with_flags_paired ty y x)
3871
+ (trap_if_impl (mask_as_cond 3) tc)))
3872
+
3873
+ ;; Add a register and memory (32/64-bit types).
3874
+ (rule 2 (lower (has_type (fits_in_64 ty)
3875
+ (uadd_overflow_trap x (sinkable_load_32_64 y) tc)))
3876
+ (with_flags
3877
+ (add_logical_mem_with_flags_paired ty x (sink_load y))
3878
+ (trap_if_impl (mask_as_cond 3) tc)))
3879
+ (rule 6 (lower (has_type (fits_in_64 ty)
3880
+ (uadd_overflow_trap (sinkable_load_32_64 x) y tc)))
3881
+ (with_flags
3882
+ (add_logical_mem_with_flags_paired ty y (sink_load x))
3883
+ (trap_if_impl (mask_as_cond 3) tc)))
3884
+
3885
+ ;; Add a register and zero-extended memory.
3886
+ (rule 1 (lower (has_type (fits_in_64 ty)
3887
+ (uadd_overflow_trap x (sinkable_uload32 y) tc)))
3888
+ (with_flags
3889
+ (add_logical_mem_zext32_with_flags_paired ty x (sink_uload32 y))
3890
+ (trap_if_impl (mask_as_cond 3) tc)))
3891
+ (rule 5 (lower (has_type (fits_in_64 ty)
3892
+ (uadd_overflow_trap (sinkable_uload32 x) y tc)))
3893
+ (with_flags
3894
+ (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x))
3895
+ (trap_if_impl (mask_as_cond 3) tc)))
3896
+
3897
+ ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3898
+
3899
+ (rule (lower (return args))
3900
+ (lower_return args))
3901
+
3902
+
3903
+ ;;;; Rules for `call` and `call_indirect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3904
+
3905
+ ;; Direct call to an in-range function.
3906
+ (rule 1 (lower (call (func_ref_data sig_ref name (reloc_distance_near)) args))
3907
+ (let ((abi Sig (abi_sig sig_ref))
3908
+ (_ Unit (abi_accumulate_outgoing_args_size abi))
3909
+ (uses CallArgList (lower_call_args abi (range 0 (abi_num_args abi)) args))
3910
+ (defs CallRetList (defs_init abi))
3911
+ (_ InstOutput (side_effect (abi_call abi name uses defs (Opcode.Call)))))
3912
+ (lower_call_rets abi defs (range (abi_first_ret sig_ref abi)
3913
+ (abi_num_rets abi)) (output_builder_new))))
3914
+
3915
+ ;; Direct call to an out-of-range function (implicitly via pointer).
3916
+ (rule (lower (call (func_ref_data sig_ref name _) args))
3917
+ (let ((abi Sig (abi_sig sig_ref))
3918
+ (_ Unit (abi_accumulate_outgoing_args_size abi))
3919
+ (uses CallArgList (lower_call_args abi (range 0 (abi_num_args abi)) args))
3920
+ (defs CallRetList (defs_init abi))
3921
+ (target Reg (load_symbol_reloc (SymbolReloc.Absolute name 0)))
3922
+ (_ InstOutput (side_effect (abi_call_ind abi target uses defs (Opcode.Call)))))
3923
+ (lower_call_rets abi defs (range (abi_first_ret sig_ref abi)
3924
+ (abi_num_rets abi)) (output_builder_new))))
3925
+
3926
+ ;; Indirect call.
3927
+ (rule (lower (call_indirect sig_ref ptr args))
3928
+ (let ((abi Sig (abi_sig sig_ref))
3929
+ (target Reg (put_in_reg ptr))
3930
+ (_ Unit (abi_accumulate_outgoing_args_size abi))
3931
+ (uses CallArgList (lower_call_args abi (range 0 (abi_num_args abi)) args))
3932
+ (defs CallRetList (defs_init abi))
3933
+ (_ InstOutput (side_effect (abi_call_ind abi target uses defs (Opcode.CallIndirect)))))
3934
+ (lower_call_rets abi defs (range (abi_first_ret sig_ref abi)
3935
+ (abi_num_rets abi)) (output_builder_new))))
3936
+
3937
+ ;; Lower function arguments.
3938
+ (decl lower_call_args (Sig Range ValueSlice) CallArgList)
3939
+ (rule (lower_call_args abi range args)
3940
+ (let ((uses CallArgListBuilder (args_builder_new))
3941
+ (_ InstOutput (lower_call_args_buffer abi range args))
3942
+ (_ InstOutput (lower_call_args_slots abi uses range args))
3943
+ (_ InstOutput (lower_call_ret_arg abi uses)))
3944
+ (args_builder_finish uses)))
3945
+
3946
+ ;; Lower function arguments (part 1): prepare buffer copies.
3947
+ (decl lower_call_args_buffer (Sig Range ValueSlice) InstOutput)
3948
+ (rule (lower_call_args_buffer abi (range_empty) _) (output_none))
3949
+ (rule (lower_call_args_buffer abi (range_unwrap head tail) args)
3950
+ (let ((_ InstOutput (copy_to_buffer 0 (abi_get_arg abi head)
3951
+ (value_slice_get args head))))
3952
+ (lower_call_args_buffer abi tail args)))
3953
+
3954
+ ;; Lower function arguments (part 2): set up registers / stack slots.
3955
+ (decl lower_call_args_slots (Sig CallArgListBuilder Range ValueSlice) InstOutput)
3956
+ (rule (lower_call_args_slots abi _ (range_empty) _) (output_none))
3957
+ (rule (lower_call_args_slots abi uses (range_unwrap head tail) args)
3958
+ (let ((_ InstOutput (copy_to_arg uses (abi_lane_order abi)
3959
+ 0 (abi_get_arg abi head)
3960
+ (value_slice_get args head))))
3961
+ (lower_call_args_slots abi uses tail args)))
3962
+
3963
+ ;; Lower function arguments (part 3): implicit return-area pointer.
3964
+ (decl lower_call_ret_arg (Sig CallArgListBuilder) InstOutput)
3965
+ (rule (lower_call_ret_arg (abi_no_ret_arg) _) (output_none))
3966
+ (rule 1 (lower_call_ret_arg abi @ (abi_ret_arg (abi_arg_only_slot slot)) uses)
3967
+ (let ((mem MemArg (memarg_stack_off (abi_sized_stack_arg_space abi) 0)))
3968
+ (copy_reg_to_arg_slot uses (abi_lane_order abi) 0 slot (load_addr mem))))
3969
+
3970
+ ;; Lower function return values by collecting them from registers / stack slots.
3971
+ (decl lower_call_rets (Sig CallRetList Range InstOutputBuilder) InstOutput)
3972
+ (rule (lower_call_rets abi _ (range_empty) builder) (output_builder_finish builder))
3973
+ (rule (lower_call_rets abi defs (range_unwrap head tail) builder)
3974
+ (let ((ret ValueRegs (copy_from_arg defs (abi_lane_order abi)
3975
+ (abi_sized_stack_arg_space abi)
3976
+ (abi_get_ret abi head)))
3977
+ (_ Unit (output_builder_push builder ret)))
3978
+ (lower_call_rets abi defs tail builder)))
3979
+
3980
+ ;;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;
3981
+
3982
+ (rule (lower (get_stack_pointer))
3983
+ (sp))
3984
+
3985
+ (rule (lower (get_frame_pointer))
3986
+ (load64 (memarg_stack_off 0 0)))
3987
+
3988
+ (rule (lower (get_return_address))
3989
+ ;; The return address is 14 pointer-sized slots above the initial SP. So
3990
+ ;; our offset is `14 * 8 = 112`.
3991
+ (load64 (memarg_initial_sp_offset 112)))