wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,3697 +0,0 @@
1
- //! S390x ISA: binary code emission.
2
-
3
- use crate::binemit::{Reloc, StackMap};
4
- use crate::ir::{MemFlags, RelSourceLoc, TrapCode};
5
- use crate::isa::s390x::abi::S390xMachineDeps;
6
- use crate::isa::s390x::inst::*;
7
- use crate::isa::s390x::settings as s390x_settings;
8
- use crate::machinst::{Reg, RegClass};
9
- use crate::trace;
10
- use core::convert::TryFrom;
11
- use cranelift_control::ControlPlane;
12
- use regalloc2::Allocation;
13
-
14
- /// Debug macro for testing that a regpair is valid: that the high register is even, and the low
15
- /// register is one higher than the high register.
16
- macro_rules! debug_assert_valid_regpair {
17
- ($hi:expr, $lo:expr) => {
18
- if cfg!(debug_assertions) {
19
- match ($hi.to_real_reg(), $lo.to_real_reg()) {
20
- (Some(hi), Some(lo)) => {
21
- assert!(
22
- hi.hw_enc() % 2 == 0,
23
- "High register is not even: {}",
24
- show_reg($hi)
25
- );
26
- assert_eq!(
27
- hi.hw_enc() + 1,
28
- lo.hw_enc(),
29
- "Low register is not valid: {}, {}",
30
- show_reg($hi),
31
- show_reg($lo)
32
- );
33
- }
34
-
35
- _ => {
36
- panic!(
37
- "Expected real registers for {} {}",
38
- show_reg($hi),
39
- show_reg($lo)
40
- );
41
- }
42
- }
43
- }
44
- };
45
- }
46
-
47
- /// Type(s) of memory instructions available for mem_finalize.
48
- pub struct MemInstType {
49
- /// True if 12-bit unsigned displacement is supported.
50
- pub have_d12: bool,
51
- /// True if 20-bit signed displacement is supported.
52
- pub have_d20: bool,
53
- /// True if PC-relative addressing is supported (memory access).
54
- pub have_pcrel: bool,
55
- /// True if PC-relative addressing is supported (load address).
56
- pub have_unaligned_pcrel: bool,
57
- /// True if an index register is supported.
58
- pub have_index: bool,
59
- }
60
-
61
- /// Memory addressing mode finalization: convert "special" modes (e.g.,
62
- /// generic arbitrary stack offset) into real addressing modes, possibly by
63
- /// emitting some helper instructions that come immediately before the use
64
- /// of this amode.
65
- pub fn mem_finalize(
66
- mem: &MemArg,
67
- state: &EmitState,
68
- mi: MemInstType,
69
- ) -> (SmallVec<[Inst; 4]>, MemArg) {
70
- let mut insts = SmallVec::new();
71
-
72
- // Resolve virtual addressing modes.
73
- let mem = match mem {
74
- &MemArg::RegOffset { off, .. }
75
- | &MemArg::InitialSPOffset { off }
76
- | &MemArg::NominalSPOffset { off } => {
77
- let base = match mem {
78
- &MemArg::RegOffset { reg, .. } => reg,
79
- &MemArg::InitialSPOffset { .. } | &MemArg::NominalSPOffset { .. } => stack_reg(),
80
- _ => unreachable!(),
81
- };
82
- let adj = match mem {
83
- &MemArg::InitialSPOffset { .. } => {
84
- state.initial_sp_offset + state.virtual_sp_offset
85
- }
86
- &MemArg::NominalSPOffset { .. } => state.virtual_sp_offset,
87
- _ => 0,
88
- };
89
- let off = off + adj;
90
-
91
- if let Some(disp) = UImm12::maybe_from_u64(off as u64) {
92
- MemArg::BXD12 {
93
- base,
94
- index: zero_reg(),
95
- disp,
96
- flags: mem.get_flags(),
97
- }
98
- } else if let Some(disp) = SImm20::maybe_from_i64(off) {
99
- MemArg::BXD20 {
100
- base,
101
- index: zero_reg(),
102
- disp,
103
- flags: mem.get_flags(),
104
- }
105
- } else {
106
- let tmp = writable_spilltmp_reg();
107
- assert!(base != tmp.to_reg());
108
- if let Ok(imm) = i16::try_from(off) {
109
- insts.push(Inst::Mov64SImm16 { rd: tmp, imm });
110
- } else if let Ok(imm) = i32::try_from(off) {
111
- insts.push(Inst::Mov64SImm32 { rd: tmp, imm });
112
- } else {
113
- // The offset must be smaller than the stack frame size,
114
- // which the ABI code limits to 128 MB.
115
- unreachable!();
116
- }
117
- MemArg::reg_plus_reg(base, tmp.to_reg(), mem.get_flags())
118
- }
119
- }
120
- _ => mem.clone(),
121
- };
122
-
123
- // If this addressing mode cannot be handled by the instruction, use load-address.
124
- let need_load_address = match &mem {
125
- &MemArg::Label { .. } | &MemArg::Symbol { .. } if !mi.have_pcrel => true,
126
- &MemArg::Symbol { flags, .. } if !mi.have_unaligned_pcrel && !flags.aligned() => true,
127
- &MemArg::BXD20 { .. } if !mi.have_d20 => true,
128
- &MemArg::BXD12 { index, .. } | &MemArg::BXD20 { index, .. } if !mi.have_index => {
129
- index != zero_reg()
130
- }
131
- _ => false,
132
- };
133
- let mem = if need_load_address {
134
- let flags = mem.get_flags();
135
- let tmp = writable_spilltmp_reg();
136
- insts.push(Inst::LoadAddr { rd: tmp, mem });
137
- MemArg::reg(tmp.to_reg(), flags)
138
- } else {
139
- mem
140
- };
141
-
142
- // Convert 12-bit displacement to 20-bit if required.
143
- let mem = match &mem {
144
- &MemArg::BXD12 {
145
- base,
146
- index,
147
- disp,
148
- flags,
149
- } if !mi.have_d12 => {
150
- assert!(mi.have_d20);
151
- MemArg::BXD20 {
152
- base,
153
- index,
154
- disp: SImm20::from_uimm12(disp),
155
- flags,
156
- }
157
- }
158
- _ => mem,
159
- };
160
-
161
- (insts, mem)
162
- }
163
-
164
- pub fn mem_emit(
165
- rd: Reg,
166
- mem: &MemArg,
167
- opcode_rx: Option<u16>,
168
- opcode_rxy: Option<u16>,
169
- opcode_ril: Option<u16>,
170
- add_trap: bool,
171
- sink: &mut MachBuffer<Inst>,
172
- emit_info: &EmitInfo,
173
- state: &mut EmitState,
174
- ) {
175
- let (mem_insts, mem) = mem_finalize(
176
- mem,
177
- state,
178
- MemInstType {
179
- have_d12: opcode_rx.is_some(),
180
- have_d20: opcode_rxy.is_some(),
181
- have_pcrel: opcode_ril.is_some(),
182
- have_unaligned_pcrel: opcode_ril.is_some() && !add_trap,
183
- have_index: true,
184
- },
185
- );
186
- for inst in mem_insts.into_iter() {
187
- inst.emit(&[], sink, emit_info, state);
188
- }
189
-
190
- if add_trap && mem.can_trap() {
191
- let srcloc = state.cur_srcloc();
192
- if !srcloc.is_default() {
193
- sink.add_trap(TrapCode::HeapOutOfBounds);
194
- }
195
- }
196
-
197
- match &mem {
198
- &MemArg::BXD12 {
199
- base, index, disp, ..
200
- } => {
201
- put(
202
- sink,
203
- &enc_rx(opcode_rx.unwrap(), rd, base, index, disp.bits()),
204
- );
205
- }
206
- &MemArg::BXD20 {
207
- base, index, disp, ..
208
- } => {
209
- put(
210
- sink,
211
- &enc_rxy(opcode_rxy.unwrap(), rd, base, index, disp.bits()),
212
- );
213
- }
214
- &MemArg::Label { target } => {
215
- sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
216
- put(sink, &enc_ril_b(opcode_ril.unwrap(), rd, 0));
217
- }
218
- &MemArg::Symbol {
219
- ref name, offset, ..
220
- } => {
221
- let reloc = Reloc::S390xPCRel32Dbl;
222
- put_with_reloc(
223
- sink,
224
- &enc_ril_b(opcode_ril.unwrap(), rd, 0),
225
- 2,
226
- reloc,
227
- name,
228
- offset.into(),
229
- );
230
- }
231
- _ => unreachable!(),
232
- }
233
- }
234
-
235
- pub fn mem_rs_emit(
236
- rd: Reg,
237
- rn: Reg,
238
- mem: &MemArg,
239
- opcode_rs: Option<u16>,
240
- opcode_rsy: Option<u16>,
241
- add_trap: bool,
242
- sink: &mut MachBuffer<Inst>,
243
- emit_info: &EmitInfo,
244
- state: &mut EmitState,
245
- ) {
246
- let (mem_insts, mem) = mem_finalize(
247
- mem,
248
- state,
249
- MemInstType {
250
- have_d12: opcode_rs.is_some(),
251
- have_d20: opcode_rsy.is_some(),
252
- have_pcrel: false,
253
- have_unaligned_pcrel: false,
254
- have_index: false,
255
- },
256
- );
257
- for inst in mem_insts.into_iter() {
258
- inst.emit(&[], sink, emit_info, state);
259
- }
260
-
261
- if add_trap && mem.can_trap() {
262
- let srcloc = state.cur_srcloc();
263
- if !srcloc.is_default() {
264
- sink.add_trap(TrapCode::HeapOutOfBounds);
265
- }
266
- }
267
-
268
- match &mem {
269
- &MemArg::BXD12 {
270
- base, index, disp, ..
271
- } => {
272
- assert!(index == zero_reg());
273
- put(sink, &enc_rs(opcode_rs.unwrap(), rd, rn, base, disp.bits()));
274
- }
275
- &MemArg::BXD20 {
276
- base, index, disp, ..
277
- } => {
278
- assert!(index == zero_reg());
279
- put(
280
- sink,
281
- &enc_rsy(opcode_rsy.unwrap(), rd, rn, base, disp.bits()),
282
- );
283
- }
284
- _ => unreachable!(),
285
- }
286
- }
287
-
288
- pub fn mem_imm8_emit(
289
- imm: u8,
290
- mem: &MemArg,
291
- opcode_si: u16,
292
- opcode_siy: u16,
293
- add_trap: bool,
294
- sink: &mut MachBuffer<Inst>,
295
- emit_info: &EmitInfo,
296
- state: &mut EmitState,
297
- ) {
298
- let (mem_insts, mem) = mem_finalize(
299
- mem,
300
- state,
301
- MemInstType {
302
- have_d12: true,
303
- have_d20: true,
304
- have_pcrel: false,
305
- have_unaligned_pcrel: false,
306
- have_index: false,
307
- },
308
- );
309
- for inst in mem_insts.into_iter() {
310
- inst.emit(&[], sink, emit_info, state);
311
- }
312
-
313
- if add_trap && mem.can_trap() {
314
- let srcloc = state.cur_srcloc();
315
- if !srcloc.is_default() {
316
- sink.add_trap(TrapCode::HeapOutOfBounds);
317
- }
318
- }
319
-
320
- match &mem {
321
- &MemArg::BXD12 {
322
- base, index, disp, ..
323
- } => {
324
- assert!(index == zero_reg());
325
- put(sink, &enc_si(opcode_si, base, disp.bits(), imm));
326
- }
327
- &MemArg::BXD20 {
328
- base, index, disp, ..
329
- } => {
330
- assert!(index == zero_reg());
331
- put(sink, &enc_siy(opcode_siy, base, disp.bits(), imm));
332
- }
333
- _ => unreachable!(),
334
- }
335
- }
336
-
337
- pub fn mem_imm16_emit(
338
- imm: i16,
339
- mem: &MemArg,
340
- opcode_sil: u16,
341
- add_trap: bool,
342
- sink: &mut MachBuffer<Inst>,
343
- emit_info: &EmitInfo,
344
- state: &mut EmitState,
345
- ) {
346
- let (mem_insts, mem) = mem_finalize(
347
- mem,
348
- state,
349
- MemInstType {
350
- have_d12: true,
351
- have_d20: false,
352
- have_pcrel: false,
353
- have_unaligned_pcrel: false,
354
- have_index: false,
355
- },
356
- );
357
- for inst in mem_insts.into_iter() {
358
- inst.emit(&[], sink, emit_info, state);
359
- }
360
-
361
- if add_trap && mem.can_trap() {
362
- let srcloc = state.cur_srcloc();
363
- if !srcloc.is_default() {
364
- sink.add_trap(TrapCode::HeapOutOfBounds);
365
- }
366
- }
367
-
368
- match &mem {
369
- &MemArg::BXD12 {
370
- base, index, disp, ..
371
- } => {
372
- assert!(index == zero_reg());
373
- put(sink, &enc_sil(opcode_sil, base, disp.bits(), imm));
374
- }
375
- _ => unreachable!(),
376
- }
377
- }
378
-
379
- pub fn mem_mem_emit(
380
- dst: &MemArgPair,
381
- src: &MemArgPair,
382
- len_minus_one: u8,
383
- opcode_ss: u8,
384
- add_trap: bool,
385
- sink: &mut MachBuffer<Inst>,
386
- state: &mut EmitState,
387
- ) {
388
- if add_trap && (dst.can_trap() || src.can_trap()) {
389
- let srcloc = state.cur_srcloc();
390
- if srcloc != Default::default() {
391
- sink.add_trap(TrapCode::HeapOutOfBounds);
392
- }
393
- }
394
-
395
- put(
396
- sink,
397
- &enc_ss_a(
398
- opcode_ss,
399
- dst.base,
400
- dst.disp.bits(),
401
- src.base,
402
- src.disp.bits(),
403
- len_minus_one,
404
- ),
405
- );
406
- }
407
-
408
- pub fn mem_vrx_emit(
409
- rd: Reg,
410
- mem: &MemArg,
411
- opcode: u16,
412
- m3: u8,
413
- add_trap: bool,
414
- sink: &mut MachBuffer<Inst>,
415
- emit_info: &EmitInfo,
416
- state: &mut EmitState,
417
- ) {
418
- let (mem_insts, mem) = mem_finalize(
419
- mem,
420
- state,
421
- MemInstType {
422
- have_d12: true,
423
- have_d20: false,
424
- have_pcrel: false,
425
- have_unaligned_pcrel: false,
426
- have_index: true,
427
- },
428
- );
429
- for inst in mem_insts.into_iter() {
430
- inst.emit(&[], sink, emit_info, state);
431
- }
432
-
433
- if add_trap && mem.can_trap() {
434
- let srcloc = state.cur_srcloc();
435
- if !srcloc.is_default() {
436
- sink.add_trap(TrapCode::HeapOutOfBounds);
437
- }
438
- }
439
-
440
- match &mem {
441
- &MemArg::BXD12 {
442
- base, index, disp, ..
443
- } => {
444
- put(sink, &enc_vrx(opcode, rd, base, index, disp.bits(), m3));
445
- }
446
- _ => unreachable!(),
447
- }
448
- }
449
-
450
- //=============================================================================
451
- // Instructions and subcomponents: emission
452
-
453
- fn machreg_to_gpr(m: Reg) -> u8 {
454
- assert_eq!(m.class(), RegClass::Int);
455
- u8::try_from(m.to_real_reg().unwrap().hw_enc()).unwrap()
456
- }
457
-
458
- fn machreg_to_vr(m: Reg) -> u8 {
459
- assert_eq!(m.class(), RegClass::Float);
460
- u8::try_from(m.to_real_reg().unwrap().hw_enc()).unwrap()
461
- }
462
-
463
- fn machreg_to_fpr(m: Reg) -> u8 {
464
- assert!(is_fpr(m));
465
- u8::try_from(m.to_real_reg().unwrap().hw_enc()).unwrap()
466
- }
467
-
468
- fn machreg_to_gpr_or_fpr(m: Reg) -> u8 {
469
- let reg = u8::try_from(m.to_real_reg().unwrap().hw_enc()).unwrap();
470
- assert!(reg < 16);
471
- reg
472
- }
473
-
474
- fn rxb(v1: Option<Reg>, v2: Option<Reg>, v3: Option<Reg>, v4: Option<Reg>) -> u8 {
475
- let mut rxb = 0;
476
-
477
- let is_high_vr = |reg| -> bool {
478
- if let Some(reg) = reg {
479
- if !is_fpr(reg) {
480
- return true;
481
- }
482
- }
483
- false
484
- };
485
-
486
- if is_high_vr(v1) {
487
- rxb = rxb | 8;
488
- }
489
- if is_high_vr(v2) {
490
- rxb = rxb | 4;
491
- }
492
- if is_high_vr(v3) {
493
- rxb = rxb | 2;
494
- }
495
- if is_high_vr(v4) {
496
- rxb = rxb | 1;
497
- }
498
-
499
- rxb
500
- }
501
-
502
- /// E-type instructions.
503
- ///
504
- /// 15
505
- /// opcode
506
- /// 0
507
- ///
508
- fn enc_e(opcode: u16) -> [u8; 2] {
509
- let mut enc: [u8; 2] = [0; 2];
510
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
511
- let opcode2 = (opcode & 0xff) as u8;
512
-
513
- enc[0] = opcode1;
514
- enc[1] = opcode2;
515
- enc
516
- }
517
-
518
- /// RIa-type instructions.
519
- ///
520
- /// 31 23 19 15
521
- /// opcode1 r1 opcode2 i2
522
- /// 24 20 16 0
523
- ///
524
- fn enc_ri_a(opcode: u16, r1: Reg, i2: u16) -> [u8; 4] {
525
- let mut enc: [u8; 4] = [0; 4];
526
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
527
- let opcode2 = (opcode & 0xf) as u8;
528
- let r1 = machreg_to_gpr(r1) & 0x0f;
529
-
530
- enc[0] = opcode1;
531
- enc[1] = r1 << 4 | opcode2;
532
- enc[2..].copy_from_slice(&i2.to_be_bytes());
533
- enc
534
- }
535
-
536
- /// RIb-type instructions.
537
- ///
538
- /// 31 23 19 15
539
- /// opcode1 r1 opcode2 ri2
540
- /// 24 20 16 0
541
- ///
542
- fn enc_ri_b(opcode: u16, r1: Reg, ri2: i32) -> [u8; 4] {
543
- let mut enc: [u8; 4] = [0; 4];
544
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
545
- let opcode2 = (opcode & 0xf) as u8;
546
- let r1 = machreg_to_gpr(r1) & 0x0f;
547
- let ri2 = ((ri2 >> 1) & 0xffff) as u16;
548
-
549
- enc[0] = opcode1;
550
- enc[1] = r1 << 4 | opcode2;
551
- enc[2..].copy_from_slice(&ri2.to_be_bytes());
552
- enc
553
- }
554
-
555
- /// RIc-type instructions.
556
- ///
557
- /// 31 23 19 15
558
- /// opcode1 m1 opcode2 ri2
559
- /// 24 20 16 0
560
- ///
561
- fn enc_ri_c(opcode: u16, m1: u8, ri2: i32) -> [u8; 4] {
562
- let mut enc: [u8; 4] = [0; 4];
563
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
564
- let opcode2 = (opcode & 0xf) as u8;
565
- let m1 = m1 & 0x0f;
566
- let ri2 = ((ri2 >> 1) & 0xffff) as u16;
567
-
568
- enc[0] = opcode1;
569
- enc[1] = m1 << 4 | opcode2;
570
- enc[2..].copy_from_slice(&ri2.to_be_bytes());
571
- enc
572
- }
573
-
574
- /// RIEa-type instructions.
575
- ///
576
- /// 47 39 35 31 15 11 7
577
- /// opcode1 r1 -- i2 m3 -- opcode2
578
- /// 40 36 32 16 12 8 0
579
- ///
580
- fn enc_rie_a(opcode: u16, r1: Reg, i2: u16, m3: u8) -> [u8; 6] {
581
- let mut enc: [u8; 6] = [0; 6];
582
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
583
- let opcode2 = (opcode & 0xff) as u8;
584
- let r1 = machreg_to_gpr(r1) & 0x0f;
585
- let m3 = m3 & 0x0f;
586
-
587
- enc[0] = opcode1;
588
- enc[1] = r1 << 4;
589
- enc[2..4].copy_from_slice(&i2.to_be_bytes());
590
- enc[4] = m3 << 4;
591
- enc[5] = opcode2;
592
- enc
593
- }
594
-
595
- /// RIEd-type instructions.
596
- ///
597
- /// 47 39 35 31 15 7
598
- /// opcode1 r1 r3 i2 -- opcode2
599
- /// 40 36 32 16 8 0
600
- ///
601
- fn enc_rie_d(opcode: u16, r1: Reg, r3: Reg, i2: u16) -> [u8; 6] {
602
- let mut enc: [u8; 6] = [0; 6];
603
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
604
- let opcode2 = (opcode & 0xff) as u8;
605
- let r1 = machreg_to_gpr(r1) & 0x0f;
606
- let r3 = machreg_to_gpr(r3) & 0x0f;
607
-
608
- enc[0] = opcode1;
609
- enc[1] = r1 << 4 | r3;
610
- enc[2..4].copy_from_slice(&i2.to_be_bytes());
611
- enc[5] = opcode2;
612
- enc
613
- }
614
-
615
- /// RIEf-type instructions.
616
- ///
617
- /// 47 39 35 31 23 15 7
618
- /// opcode1 r1 r2 i3 i4 i5 opcode2
619
- /// 40 36 32 24 16 8 0
620
- ///
621
- fn enc_rie_f(opcode: u16, r1: Reg, r2: Reg, i3: u8, i4: u8, i5: u8) -> [u8; 6] {
622
- let mut enc: [u8; 6] = [0; 6];
623
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
624
- let opcode2 = (opcode & 0xff) as u8;
625
- let r1 = machreg_to_gpr(r1) & 0x0f;
626
- let r2 = machreg_to_gpr(r2) & 0x0f;
627
-
628
- enc[0] = opcode1;
629
- enc[1] = r1 << 4 | r2;
630
- enc[2] = i3;
631
- enc[3] = i4;
632
- enc[4] = i5;
633
- enc[5] = opcode2;
634
- enc
635
- }
636
-
637
- /// RIEg-type instructions.
638
- ///
639
- /// 47 39 35 31 15 7
640
- /// opcode1 r1 m3 i2 -- opcode2
641
- /// 40 36 32 16 8 0
642
- ///
643
- fn enc_rie_g(opcode: u16, r1: Reg, i2: u16, m3: u8) -> [u8; 6] {
644
- let mut enc: [u8; 6] = [0; 6];
645
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
646
- let opcode2 = (opcode & 0xff) as u8;
647
- let r1 = machreg_to_gpr(r1) & 0x0f;
648
- let m3 = m3 & 0x0f;
649
-
650
- enc[0] = opcode1;
651
- enc[1] = r1 << 4 | m3;
652
- enc[2..4].copy_from_slice(&i2.to_be_bytes());
653
- enc[5] = opcode2;
654
- enc
655
- }
656
-
657
- /// RILa-type instructions.
658
- ///
659
- /// 47 39 35 31
660
- /// opcode1 r1 opcode2 i2
661
- /// 40 36 32 0
662
- ///
663
- fn enc_ril_a(opcode: u16, r1: Reg, i2: u32) -> [u8; 6] {
664
- let mut enc: [u8; 6] = [0; 6];
665
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
666
- let opcode2 = (opcode & 0xf) as u8;
667
- let r1 = machreg_to_gpr(r1) & 0x0f;
668
-
669
- enc[0] = opcode1;
670
- enc[1] = r1 << 4 | opcode2;
671
- enc[2..].copy_from_slice(&i2.to_be_bytes());
672
- enc
673
- }
674
-
675
- /// RILb-type instructions.
676
- ///
677
- /// 47 39 35 31
678
- /// opcode1 r1 opcode2 ri2
679
- /// 40 36 32 0
680
- ///
681
- fn enc_ril_b(opcode: u16, r1: Reg, ri2: u32) -> [u8; 6] {
682
- let mut enc: [u8; 6] = [0; 6];
683
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
684
- let opcode2 = (opcode & 0xf) as u8;
685
- let r1 = machreg_to_gpr(r1) & 0x0f;
686
- let ri2 = ri2 >> 1;
687
-
688
- enc[0] = opcode1;
689
- enc[1] = r1 << 4 | opcode2;
690
- enc[2..].copy_from_slice(&ri2.to_be_bytes());
691
- enc
692
- }
693
-
694
- /// RILc-type instructions.
695
- ///
696
- /// 47 39 35 31
697
- /// opcode1 m1 opcode2 i2
698
- /// 40 36 32 0
699
- ///
700
- fn enc_ril_c(opcode: u16, m1: u8, ri2: u32) -> [u8; 6] {
701
- let mut enc: [u8; 6] = [0; 6];
702
- let opcode1 = ((opcode >> 4) & 0xff) as u8;
703
- let opcode2 = (opcode & 0xf) as u8;
704
- let m1 = m1 & 0x0f;
705
- let ri2 = ri2 >> 1;
706
-
707
- enc[0] = opcode1;
708
- enc[1] = m1 << 4 | opcode2;
709
- enc[2..].copy_from_slice(&ri2.to_be_bytes());
710
- enc
711
- }
712
-
713
- /// RR-type instructions.
714
- ///
715
- /// 15 7 3
716
- /// opcode r1 r2
717
- /// 8 4 0
718
- ///
719
- fn enc_rr(opcode: u16, r1: Reg, r2: Reg) -> [u8; 2] {
720
- let mut enc: [u8; 2] = [0; 2];
721
- let opcode = (opcode & 0xff) as u8;
722
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
723
- let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
724
-
725
- enc[0] = opcode;
726
- enc[1] = r1 << 4 | r2;
727
- enc
728
- }
729
-
730
- /// RRD-type instructions.
731
- ///
732
- /// 31 15 11 7 3
733
- /// opcode r1 -- r3 r2
734
- /// 16 12 8 4 0
735
- ///
736
- fn enc_rrd(opcode: u16, r1: Reg, r2: Reg, r3: Reg) -> [u8; 4] {
737
- let mut enc: [u8; 4] = [0; 4];
738
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
739
- let opcode2 = (opcode & 0xff) as u8;
740
- let r1 = machreg_to_fpr(r1) & 0x0f;
741
- let r2 = machreg_to_fpr(r2) & 0x0f;
742
- let r3 = machreg_to_fpr(r3) & 0x0f;
743
-
744
- enc[0] = opcode1;
745
- enc[1] = opcode2;
746
- enc[2] = r1 << 4;
747
- enc[3] = r3 << 4 | r2;
748
- enc
749
- }
750
-
751
- /// RRE-type instructions.
752
- ///
753
- /// 31 15 7 3
754
- /// opcode -- r1 r2
755
- /// 16 8 4 0
756
- ///
757
- fn enc_rre(opcode: u16, r1: Reg, r2: Reg) -> [u8; 4] {
758
- let mut enc: [u8; 4] = [0; 4];
759
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
760
- let opcode2 = (opcode & 0xff) as u8;
761
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
762
- let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
763
-
764
- enc[0] = opcode1;
765
- enc[1] = opcode2;
766
- enc[3] = r1 << 4 | r2;
767
- enc
768
- }
769
-
770
- /// RRFa/b-type instructions.
771
- ///
772
- /// 31 15 11 7 3
773
- /// opcode r3 m4 r1 r2
774
- /// 16 12 8 4 0
775
- ///
776
- fn enc_rrf_ab(opcode: u16, r1: Reg, r2: Reg, r3: Reg, m4: u8) -> [u8; 4] {
777
- let mut enc: [u8; 4] = [0; 4];
778
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
779
- let opcode2 = (opcode & 0xff) as u8;
780
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
781
- let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
782
- let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
783
- let m4 = m4 & 0x0f;
784
-
785
- enc[0] = opcode1;
786
- enc[1] = opcode2;
787
- enc[2] = r3 << 4 | m4;
788
- enc[3] = r1 << 4 | r2;
789
- enc
790
- }
791
-
792
- /// RRFc/d/e-type instructions.
793
- ///
794
- /// 31 15 11 7 3
795
- /// opcode m3 m4 r1 r2
796
- /// 16 12 8 4 0
797
- ///
798
- fn enc_rrf_cde(opcode: u16, r1: Reg, r2: Reg, m3: u8, m4: u8) -> [u8; 4] {
799
- let mut enc: [u8; 4] = [0; 4];
800
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
801
- let opcode2 = (opcode & 0xff) as u8;
802
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
803
- let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
804
- let m3 = m3 & 0x0f;
805
- let m4 = m4 & 0x0f;
806
-
807
- enc[0] = opcode1;
808
- enc[1] = opcode2;
809
- enc[2] = m3 << 4 | m4;
810
- enc[3] = r1 << 4 | r2;
811
- enc
812
- }
813
-
814
- /// RS-type instructions.
815
- ///
816
- /// 31 23 19 15 11
817
- /// opcode r1 r3 b2 d2
818
- /// 24 20 16 12 0
819
- ///
820
- fn enc_rs(opcode: u16, r1: Reg, r3: Reg, b2: Reg, d2: u32) -> [u8; 4] {
821
- let opcode = (opcode & 0xff) as u8;
822
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
823
- let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
824
- let b2 = machreg_to_gpr(b2) & 0x0f;
825
- let d2_lo = (d2 & 0xff) as u8;
826
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
827
-
828
- let mut enc: [u8; 4] = [0; 4];
829
- enc[0] = opcode;
830
- enc[1] = r1 << 4 | r3;
831
- enc[2] = b2 << 4 | d2_hi;
832
- enc[3] = d2_lo;
833
- enc
834
- }
835
-
836
- /// RSY-type instructions.
837
- ///
838
- /// 47 39 35 31 27 15 7
839
- /// opcode1 r1 r3 b2 dl2 dh2 opcode2
840
- /// 40 36 32 28 16 8 0
841
- ///
842
- fn enc_rsy(opcode: u16, r1: Reg, r3: Reg, b2: Reg, d2: u32) -> [u8; 6] {
843
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
844
- let opcode2 = (opcode & 0xff) as u8;
845
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
846
- let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
847
- let b2 = machreg_to_gpr(b2) & 0x0f;
848
- let dl2_lo = (d2 & 0xff) as u8;
849
- let dl2_hi = ((d2 >> 8) & 0x0f) as u8;
850
- let dh2 = ((d2 >> 12) & 0xff) as u8;
851
-
852
- let mut enc: [u8; 6] = [0; 6];
853
- enc[0] = opcode1;
854
- enc[1] = r1 << 4 | r3;
855
- enc[2] = b2 << 4 | dl2_hi;
856
- enc[3] = dl2_lo;
857
- enc[4] = dh2;
858
- enc[5] = opcode2;
859
- enc
860
- }
861
-
862
- /// RX-type instructions.
863
- ///
864
- /// 31 23 19 15 11
865
- /// opcode r1 x2 b2 d2
866
- /// 24 20 16 12 0
867
- ///
868
- fn enc_rx(opcode: u16, r1: Reg, b2: Reg, x2: Reg, d2: u32) -> [u8; 4] {
869
- let opcode = (opcode & 0xff) as u8;
870
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
871
- let b2 = machreg_to_gpr(b2) & 0x0f;
872
- let x2 = machreg_to_gpr(x2) & 0x0f;
873
- let d2_lo = (d2 & 0xff) as u8;
874
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
875
-
876
- let mut enc: [u8; 4] = [0; 4];
877
- enc[0] = opcode;
878
- enc[1] = r1 << 4 | x2;
879
- enc[2] = b2 << 4 | d2_hi;
880
- enc[3] = d2_lo;
881
- enc
882
- }
883
-
884
- /// RXY-type instructions.
885
- ///
886
- /// 47 39 35 31 27 15 7
887
- /// opcode1 r1 x2 b2 dl2 dh2 opcode2
888
- /// 40 36 32 28 16 8 0
889
- ///
890
- fn enc_rxy(opcode: u16, r1: Reg, b2: Reg, x2: Reg, d2: u32) -> [u8; 6] {
891
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
892
- let opcode2 = (opcode & 0xff) as u8;
893
- let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
894
- let b2 = machreg_to_gpr(b2) & 0x0f;
895
- let x2 = machreg_to_gpr(x2) & 0x0f;
896
- let dl2_lo = (d2 & 0xff) as u8;
897
- let dl2_hi = ((d2 >> 8) & 0x0f) as u8;
898
- let dh2 = ((d2 >> 12) & 0xff) as u8;
899
-
900
- let mut enc: [u8; 6] = [0; 6];
901
- enc[0] = opcode1;
902
- enc[1] = r1 << 4 | x2;
903
- enc[2] = b2 << 4 | dl2_hi;
904
- enc[3] = dl2_lo;
905
- enc[4] = dh2;
906
- enc[5] = opcode2;
907
- enc
908
- }
909
-
910
- /// SI-type instructions.
911
- ///
912
- /// 31 23 15 11
913
- /// opcode i2 b1 d1
914
- /// 24 16 12 0
915
- ///
916
- fn enc_si(opcode: u16, b1: Reg, d1: u32, i2: u8) -> [u8; 4] {
917
- let opcode = (opcode & 0xff) as u8;
918
- let b1 = machreg_to_gpr(b1) & 0x0f;
919
- let d1_lo = (d1 & 0xff) as u8;
920
- let d1_hi = ((d1 >> 8) & 0x0f) as u8;
921
-
922
- let mut enc: [u8; 4] = [0; 4];
923
- enc[0] = opcode;
924
- enc[1] = i2;
925
- enc[2] = b1 << 4 | d1_hi;
926
- enc[3] = d1_lo;
927
- enc
928
- }
929
-
930
- /// SIL-type instructions.
931
- ///
932
- /// 47 31 27 15
933
- /// opcode b1 d1 i2
934
- /// 32 28 16 0
935
- ///
936
- fn enc_sil(opcode: u16, b1: Reg, d1: u32, i2: i16) -> [u8; 6] {
937
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
938
- let opcode2 = (opcode & 0xff) as u8;
939
- let b1 = machreg_to_gpr(b1) & 0x0f;
940
- let d1_lo = (d1 & 0xff) as u8;
941
- let d1_hi = ((d1 >> 8) & 0x0f) as u8;
942
-
943
- let mut enc: [u8; 6] = [0; 6];
944
- enc[0] = opcode1;
945
- enc[1] = opcode2;
946
- enc[2] = b1 << 4 | d1_hi;
947
- enc[3] = d1_lo;
948
- enc[4..].copy_from_slice(&i2.to_be_bytes());
949
- enc
950
- }
951
-
952
- /// SIY-type instructions.
953
- ///
954
- /// 47 39 31 27 15 7
955
- /// opcode1 i2 b1 dl1 dh1 opcode2
956
- /// 40 32 28 16 8 0
957
- ///
958
- fn enc_siy(opcode: u16, b1: Reg, d1: u32, i2: u8) -> [u8; 6] {
959
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
960
- let opcode2 = (opcode & 0xff) as u8;
961
- let b1 = machreg_to_gpr(b1) & 0x0f;
962
- let dl1_lo = (d1 & 0xff) as u8;
963
- let dl1_hi = ((d1 >> 8) & 0x0f) as u8;
964
- let dh1 = ((d1 >> 12) & 0xff) as u8;
965
-
966
- let mut enc: [u8; 6] = [0; 6];
967
- enc[0] = opcode1;
968
- enc[1] = i2;
969
- enc[2] = b1 << 4 | dl1_hi;
970
- enc[3] = dl1_lo;
971
- enc[4] = dh1;
972
- enc[5] = opcode2;
973
- enc
974
- }
975
-
976
- /// SSa-type instructions.
977
- ///
978
- /// 47 39 31 27 15 11
979
- /// opcode l b1 d1 b2 d2
980
- /// 40 32 28 16 12 0
981
- ///
982
- ///
983
- fn enc_ss_a(opcode: u8, b1: Reg, d1: u32, b2: Reg, d2: u32, l: u8) -> [u8; 6] {
984
- let b1 = machreg_to_gpr(b1) & 0x0f;
985
- let d1_lo = (d1 & 0xff) as u8;
986
- let d1_hi = ((d1 >> 8) & 0x0f) as u8;
987
- let b2 = machreg_to_gpr(b2) & 0x0f;
988
- let d2_lo = (d2 & 0xff) as u8;
989
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
990
-
991
- let mut enc: [u8; 6] = [0; 6];
992
- enc[0] = opcode;
993
- enc[1] = l;
994
- enc[2] = b1 << 4 | d1_hi;
995
- enc[3] = d1_lo;
996
- enc[4] = b2 << 4 | d2_hi;
997
- enc[5] = d2_lo;
998
- enc
999
- }
1000
-
1001
- /// VRIa-type instructions.
1002
- ///
1003
- /// 47 39 35 31 15 11 7
1004
- /// opcode1 v1 - i2 m3 rxb opcode2
1005
- /// 40 36 32 16 12 8 0
1006
- ///
1007
- fn enc_vri_a(opcode: u16, v1: Reg, i2: u16, m3: u8) -> [u8; 6] {
1008
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1009
- let opcode2 = (opcode & 0xff) as u8;
1010
- let rxb = rxb(Some(v1), None, None, None);
1011
- let v1 = machreg_to_vr(v1) & 0x0f;
1012
- let m3 = m3 & 0x0f;
1013
-
1014
- let mut enc: [u8; 6] = [0; 6];
1015
- enc[0] = opcode1;
1016
- enc[1] = v1 << 4;
1017
- enc[2..4].copy_from_slice(&i2.to_be_bytes());
1018
- enc[4] = m3 << 4 | rxb;
1019
- enc[5] = opcode2;
1020
- enc
1021
- }
1022
-
1023
- /// VRIb-type instructions.
1024
- ///
1025
- /// 47 39 35 31 23 15 11 7
1026
- /// opcode1 v1 - i2 i3 m4 rxb opcode2
1027
- /// 40 36 32 24 16 12 8 0
1028
- ///
1029
- fn enc_vri_b(opcode: u16, v1: Reg, i2: u8, i3: u8, m4: u8) -> [u8; 6] {
1030
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1031
- let opcode2 = (opcode & 0xff) as u8;
1032
- let rxb = rxb(Some(v1), None, None, None);
1033
- let v1 = machreg_to_vr(v1) & 0x0f;
1034
- let m4 = m4 & 0x0f;
1035
-
1036
- let mut enc: [u8; 6] = [0; 6];
1037
- enc[0] = opcode1;
1038
- enc[1] = v1 << 4;
1039
- enc[2] = i2;
1040
- enc[3] = i3;
1041
- enc[4] = m4 << 4 | rxb;
1042
- enc[5] = opcode2;
1043
- enc
1044
- }
1045
-
1046
- /// VRIc-type instructions.
1047
- ///
1048
- /// 47 39 35 31 15 11 7
1049
- /// opcode1 v1 v3 i2 m4 rxb opcode2
1050
- /// 40 36 32 16 12 8 0
1051
- ///
1052
- fn enc_vri_c(opcode: u16, v1: Reg, i2: u16, v3: Reg, m4: u8) -> [u8; 6] {
1053
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1054
- let opcode2 = (opcode & 0xff) as u8;
1055
- let rxb = rxb(Some(v1), Some(v3), None, None);
1056
- let v1 = machreg_to_vr(v1) & 0x0f;
1057
- let v3 = machreg_to_vr(v3) & 0x0f;
1058
- let m4 = m4 & 0x0f;
1059
-
1060
- let mut enc: [u8; 6] = [0; 6];
1061
- enc[0] = opcode1;
1062
- enc[1] = v1 << 4 | v3;
1063
- enc[2..4].copy_from_slice(&i2.to_be_bytes());
1064
- enc[4] = m4 << 4 | rxb;
1065
- enc[5] = opcode2;
1066
- enc
1067
- }
1068
-
1069
- /// VRRa-type instructions.
1070
- ///
1071
- /// 47 39 35 31 23 19 15 11 7
1072
- /// opcode1 v1 v2 - m5 m3 m2 rxb opcode2
1073
- /// 40 36 32 24 20 16 12 8 0
1074
- ///
1075
- fn enc_vrr_a(opcode: u16, v1: Reg, v2: Reg, m3: u8, m4: u8, m5: u8) -> [u8; 6] {
1076
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1077
- let opcode2 = (opcode & 0xff) as u8;
1078
- let rxb = rxb(Some(v1), Some(v2), None, None);
1079
- let v1 = machreg_to_vr(v1) & 0x0f;
1080
- let v2 = machreg_to_vr(v2) & 0x0f;
1081
- let m3 = m3 & 0x0f;
1082
- let m4 = m4 & 0x0f;
1083
- let m5 = m5 & 0x0f;
1084
-
1085
- let mut enc: [u8; 6] = [0; 6];
1086
- enc[0] = opcode1;
1087
- enc[1] = v1 << 4 | v2;
1088
- enc[2] = 0;
1089
- enc[3] = m5 << 4 | m4;
1090
- enc[4] = m3 << 4 | rxb;
1091
- enc[5] = opcode2;
1092
- enc
1093
- }
1094
-
1095
- /// VRRb-type instructions.
1096
- ///
1097
- /// 47 39 35 31 27 23 19 15 11 7
1098
- /// opcode1 v1 v2 v3 - m5 - m4 rxb opcode2
1099
- /// 40 36 32 28 24 20 16 12 8 0
1100
- ///
1101
- fn enc_vrr_b(opcode: u16, v1: Reg, v2: Reg, v3: Reg, m4: u8, m5: u8) -> [u8; 6] {
1102
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1103
- let opcode2 = (opcode & 0xff) as u8;
1104
- let rxb = rxb(Some(v1), Some(v2), Some(v3), None);
1105
- let v1 = machreg_to_vr(v1) & 0x0f;
1106
- let v2 = machreg_to_vr(v2) & 0x0f;
1107
- let v3 = machreg_to_vr(v3) & 0x0f;
1108
- let m4 = m4 & 0x0f;
1109
- let m5 = m5 & 0x0f;
1110
-
1111
- let mut enc: [u8; 6] = [0; 6];
1112
- enc[0] = opcode1;
1113
- enc[1] = v1 << 4 | v2;
1114
- enc[2] = v3 << 4;
1115
- enc[3] = m5 << 4;
1116
- enc[4] = m4 << 4 | rxb;
1117
- enc[5] = opcode2;
1118
- enc
1119
- }
1120
-
1121
- /// VRRc-type instructions.
1122
- ///
1123
- /// 47 39 35 31 27 23 19 15 11 7
1124
- /// opcode1 v1 v2 v3 - m6 m5 m4 rxb opcode2
1125
- /// 40 36 32 28 24 20 16 12 8 0
1126
- ///
1127
- fn enc_vrr_c(opcode: u16, v1: Reg, v2: Reg, v3: Reg, m4: u8, m5: u8, m6: u8) -> [u8; 6] {
1128
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1129
- let opcode2 = (opcode & 0xff) as u8;
1130
- let rxb = rxb(Some(v1), Some(v2), Some(v3), None);
1131
- let v1 = machreg_to_vr(v1) & 0x0f;
1132
- let v2 = machreg_to_vr(v2) & 0x0f;
1133
- let v3 = machreg_to_vr(v3) & 0x0f;
1134
- let m4 = m4 & 0x0f;
1135
- let m5 = m5 & 0x0f;
1136
- let m6 = m6 & 0x0f;
1137
-
1138
- let mut enc: [u8; 6] = [0; 6];
1139
- enc[0] = opcode1;
1140
- enc[1] = v1 << 4 | v2;
1141
- enc[2] = v3 << 4;
1142
- enc[3] = m6 << 4 | m5;
1143
- enc[4] = m4 << 4 | rxb;
1144
- enc[5] = opcode2;
1145
- enc
1146
- }
1147
-
1148
- /// VRRe-type instructions.
1149
- ///
1150
- /// 47 39 35 31 27 23 19 15 11 7
1151
- /// opcode1 v1 v2 v3 m6 - m5 v4 rxb opcode2
1152
- /// 40 36 32 28 24 20 16 12 8 0
1153
- ///
1154
- fn enc_vrr_e(opcode: u16, v1: Reg, v2: Reg, v3: Reg, v4: Reg, m5: u8, m6: u8) -> [u8; 6] {
1155
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1156
- let opcode2 = (opcode & 0xff) as u8;
1157
- let rxb = rxb(Some(v1), Some(v2), Some(v3), Some(v4));
1158
- let v1 = machreg_to_vr(v1) & 0x0f;
1159
- let v2 = machreg_to_vr(v2) & 0x0f;
1160
- let v3 = machreg_to_vr(v3) & 0x0f;
1161
- let v4 = machreg_to_vr(v4) & 0x0f;
1162
- let m5 = m5 & 0x0f;
1163
- let m6 = m6 & 0x0f;
1164
-
1165
- let mut enc: [u8; 6] = [0; 6];
1166
- enc[0] = opcode1;
1167
- enc[1] = v1 << 4 | v2;
1168
- enc[2] = v3 << 4 | m6;
1169
- enc[3] = m5;
1170
- enc[4] = v4 << 4 | rxb;
1171
- enc[5] = opcode2;
1172
- enc
1173
- }
1174
-
1175
- /// VRRf-type instructions.
1176
- ///
1177
- /// 47 39 35 31 27 11 7
1178
- /// opcode1 v1 r2 r3 - rxb opcode2
1179
- /// 40 36 32 28 12 8 0
1180
- ///
1181
- fn enc_vrr_f(opcode: u16, v1: Reg, r2: Reg, r3: Reg) -> [u8; 6] {
1182
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1183
- let opcode2 = (opcode & 0xff) as u8;
1184
- let rxb = rxb(Some(v1), None, None, None);
1185
- let v1 = machreg_to_vr(v1) & 0x0f;
1186
- let r2 = machreg_to_gpr(r2) & 0x0f;
1187
- let r3 = machreg_to_gpr(r3) & 0x0f;
1188
-
1189
- let mut enc: [u8; 6] = [0; 6];
1190
- enc[0] = opcode1;
1191
- enc[1] = v1 << 4 | r2;
1192
- enc[2] = r3 << 4;
1193
- enc[4] = rxb;
1194
- enc[5] = opcode2;
1195
- enc
1196
- }
1197
-
1198
- /// VRSa-type instructions.
1199
- ///
1200
- /// 47 39 35 31 27 15 11 7
1201
- /// opcode1 v1 v3 b2 d2 m4 rxb opcode2
1202
- /// 40 36 32 28 16 12 8 0
1203
- ///
1204
- fn enc_vrs_a(opcode: u16, v1: Reg, b2: Reg, d2: u32, v3: Reg, m4: u8) -> [u8; 6] {
1205
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1206
- let opcode2 = (opcode & 0xff) as u8;
1207
- let rxb = rxb(Some(v1), Some(v3), None, None);
1208
- let v1 = machreg_to_vr(v1) & 0x0f;
1209
- let b2 = machreg_to_gpr(b2) & 0x0f;
1210
- let v3 = machreg_to_vr(v3) & 0x0f;
1211
- let d2_lo = (d2 & 0xff) as u8;
1212
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
1213
- let m4 = m4 & 0x0f;
1214
-
1215
- let mut enc: [u8; 6] = [0; 6];
1216
- enc[0] = opcode1;
1217
- enc[1] = v1 << 4 | v3;
1218
- enc[2] = b2 << 4 | d2_hi;
1219
- enc[3] = d2_lo;
1220
- enc[4] = m4 << 4 | rxb;
1221
- enc[5] = opcode2;
1222
- enc
1223
- }
1224
-
1225
- /// VRSb-type instructions.
1226
- ///
1227
- /// 47 39 35 31 27 15 11 7
1228
- /// opcode1 v1 r3 b2 d2 m4 rxb opcode2
1229
- /// 40 36 32 28 16 12 8 0
1230
- ///
1231
- fn enc_vrs_b(opcode: u16, v1: Reg, b2: Reg, d2: u32, r3: Reg, m4: u8) -> [u8; 6] {
1232
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1233
- let opcode2 = (opcode & 0xff) as u8;
1234
- let rxb = rxb(Some(v1), None, None, None);
1235
- let v1 = machreg_to_vr(v1) & 0x0f;
1236
- let b2 = machreg_to_gpr(b2) & 0x0f;
1237
- let r3 = machreg_to_gpr(r3) & 0x0f;
1238
- let d2_lo = (d2 & 0xff) as u8;
1239
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
1240
- let m4 = m4 & 0x0f;
1241
-
1242
- let mut enc: [u8; 6] = [0; 6];
1243
- enc[0] = opcode1;
1244
- enc[1] = v1 << 4 | r3;
1245
- enc[2] = b2 << 4 | d2_hi;
1246
- enc[3] = d2_lo;
1247
- enc[4] = m4 << 4 | rxb;
1248
- enc[5] = opcode2;
1249
- enc
1250
- }
1251
-
1252
- /// VRSc-type instructions.
1253
- ///
1254
- /// 47 39 35 31 27 15 11 7
1255
- /// opcode1 r1 v3 b2 d2 m4 rxb opcode2
1256
- /// 40 36 32 28 16 12 8 0
1257
- ///
1258
- fn enc_vrs_c(opcode: u16, r1: Reg, b2: Reg, d2: u32, v3: Reg, m4: u8) -> [u8; 6] {
1259
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1260
- let opcode2 = (opcode & 0xff) as u8;
1261
- let rxb = rxb(None, Some(v3), None, None);
1262
- let r1 = machreg_to_gpr(r1) & 0x0f;
1263
- let b2 = machreg_to_gpr(b2) & 0x0f;
1264
- let v3 = machreg_to_vr(v3) & 0x0f;
1265
- let d2_lo = (d2 & 0xff) as u8;
1266
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
1267
- let m4 = m4 & 0x0f;
1268
-
1269
- let mut enc: [u8; 6] = [0; 6];
1270
- enc[0] = opcode1;
1271
- enc[1] = r1 << 4 | v3;
1272
- enc[2] = b2 << 4 | d2_hi;
1273
- enc[3] = d2_lo;
1274
- enc[4] = m4 << 4 | rxb;
1275
- enc[5] = opcode2;
1276
- enc
1277
- }
1278
-
1279
- /// VRX-type instructions.
1280
- ///
1281
- /// 47 39 35 31 27 15 11 7
1282
- /// opcode1 v1 x2 b2 d2 m3 rxb opcode2
1283
- /// 40 36 32 28 16 12 8 0
1284
- ///
1285
- fn enc_vrx(opcode: u16, v1: Reg, b2: Reg, x2: Reg, d2: u32, m3: u8) -> [u8; 6] {
1286
- let opcode1 = ((opcode >> 8) & 0xff) as u8;
1287
- let opcode2 = (opcode & 0xff) as u8;
1288
- let rxb = rxb(Some(v1), None, None, None);
1289
- let v1 = machreg_to_vr(v1) & 0x0f;
1290
- let b2 = machreg_to_gpr(b2) & 0x0f;
1291
- let x2 = machreg_to_gpr(x2) & 0x0f;
1292
- let d2_lo = (d2 & 0xff) as u8;
1293
- let d2_hi = ((d2 >> 8) & 0x0f) as u8;
1294
- let m3 = m3 & 0x0f;
1295
-
1296
- let mut enc: [u8; 6] = [0; 6];
1297
- enc[0] = opcode1;
1298
- enc[1] = v1 << 4 | x2;
1299
- enc[2] = b2 << 4 | d2_hi;
1300
- enc[3] = d2_lo;
1301
- enc[4] = m3 << 4 | rxb;
1302
- enc[5] = opcode2;
1303
- enc
1304
- }
1305
-
1306
- /// Emit encoding to sink.
1307
- fn put(sink: &mut MachBuffer<Inst>, enc: &[u8]) {
1308
- for byte in enc {
1309
- sink.put1(*byte);
1310
- }
1311
- }
1312
-
1313
- /// Emit encoding to sink, adding a trap on the last byte.
1314
- fn put_with_trap(sink: &mut MachBuffer<Inst>, enc: &[u8], trap_code: TrapCode) {
1315
- let len = enc.len();
1316
- for i in 0..len - 1 {
1317
- sink.put1(enc[i]);
1318
- }
1319
- sink.add_trap(trap_code);
1320
- sink.put1(enc[len - 1]);
1321
- }
1322
-
1323
- /// Emit encoding to sink, adding a relocation at byte offset.
1324
- fn put_with_reloc(
1325
- sink: &mut MachBuffer<Inst>,
1326
- enc: &[u8],
1327
- offset: usize,
1328
- ri2_reloc: Reloc,
1329
- ri2_name: &ExternalName,
1330
- ri2_offset: i64,
1331
- ) {
1332
- let len = enc.len();
1333
- for i in 0..offset {
1334
- sink.put1(enc[i]);
1335
- }
1336
- sink.add_reloc(ri2_reloc, ri2_name, ri2_offset + offset as i64);
1337
- for i in offset..len {
1338
- sink.put1(enc[i]);
1339
- }
1340
- }
1341
-
1342
- /// State carried between emissions of a sequence of instructions.
1343
- #[derive(Default, Clone, Debug)]
1344
- pub struct EmitState {
1345
- pub(crate) initial_sp_offset: i64,
1346
- pub(crate) virtual_sp_offset: i64,
1347
- /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
1348
- stack_map: Option<StackMap>,
1349
- /// Current source-code location corresponding to instruction to be emitted.
1350
- cur_srcloc: RelSourceLoc,
1351
- /// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
1352
- /// optimized away at compiletime. See [cranelift_control].
1353
- ctrl_plane: ControlPlane,
1354
- }
1355
-
1356
- impl MachInstEmitState<Inst> for EmitState {
1357
- fn new(abi: &Callee<S390xMachineDeps>, ctrl_plane: ControlPlane) -> Self {
1358
- EmitState {
1359
- virtual_sp_offset: 0,
1360
- initial_sp_offset: abi.frame_size() as i64,
1361
- stack_map: None,
1362
- cur_srcloc: Default::default(),
1363
- ctrl_plane,
1364
- }
1365
- }
1366
-
1367
- fn pre_safepoint(&mut self, stack_map: StackMap) {
1368
- self.stack_map = Some(stack_map);
1369
- }
1370
-
1371
- fn pre_sourceloc(&mut self, srcloc: RelSourceLoc) {
1372
- self.cur_srcloc = srcloc;
1373
- }
1374
-
1375
- fn ctrl_plane_mut(&mut self) -> &mut ControlPlane {
1376
- &mut self.ctrl_plane
1377
- }
1378
-
1379
- fn take_ctrl_plane(self) -> ControlPlane {
1380
- self.ctrl_plane
1381
- }
1382
- }
1383
-
1384
- impl EmitState {
1385
- fn take_stack_map(&mut self) -> Option<StackMap> {
1386
- self.stack_map.take()
1387
- }
1388
-
1389
- fn clear_post_insn(&mut self) {
1390
- self.stack_map = None;
1391
- }
1392
-
1393
- fn cur_srcloc(&self) -> RelSourceLoc {
1394
- self.cur_srcloc
1395
- }
1396
- }
1397
-
1398
- /// Constant state used during function compilation.
1399
- pub struct EmitInfo {
1400
- isa_flags: s390x_settings::Flags,
1401
- }
1402
-
1403
- impl EmitInfo {
1404
- pub(crate) fn new(isa_flags: s390x_settings::Flags) -> Self {
1405
- Self { isa_flags }
1406
- }
1407
- }
1408
-
1409
- impl MachInstEmit for Inst {
1410
- type State = EmitState;
1411
- type Info = EmitInfo;
1412
-
1413
- fn emit(
1414
- &self,
1415
- allocs: &[Allocation],
1416
- sink: &mut MachBuffer<Inst>,
1417
- emit_info: &Self::Info,
1418
- state: &mut EmitState,
1419
- ) {
1420
- let mut allocs = AllocationConsumer::new(allocs);
1421
- self.emit_with_alloc_consumer(&mut allocs, sink, emit_info, state)
1422
- }
1423
-
1424
- fn pretty_print_inst(&self, allocs: &[Allocation], state: &mut EmitState) -> String {
1425
- let mut allocs = AllocationConsumer::new(allocs);
1426
- self.print_with_state(state, &mut allocs)
1427
- }
1428
- }
1429
-
1430
- impl Inst {
1431
- fn emit_with_alloc_consumer(
1432
- &self,
1433
- allocs: &mut AllocationConsumer<'_>,
1434
- sink: &mut MachBuffer<Inst>,
1435
- emit_info: &EmitInfo,
1436
- state: &mut EmitState,
1437
- ) {
1438
- // Verify that we can emit this Inst in the current ISA
1439
- let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
1440
- match iset_requirement {
1441
- // Baseline ISA is z14
1442
- InstructionSet::Base => true,
1443
- // Miscellaneous-Instruction-Extensions Facility 2 (z15)
1444
- InstructionSet::MIE2 => emit_info.isa_flags.has_mie2(),
1445
- // Vector-Enhancements Facility 2 (z15)
1446
- InstructionSet::VXRS_EXT2 => emit_info.isa_flags.has_vxrs_ext2(),
1447
- }
1448
- };
1449
- let isa_requirements = self.available_in_isa();
1450
- if !matches_isa_flags(&isa_requirements) {
1451
- panic!(
1452
- "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
1453
- self, isa_requirements
1454
- )
1455
- }
1456
-
1457
- // N.B.: we *must* not exceed the "worst-case size" used to compute
1458
- // where to insert islands, except when islands are explicitly triggered
1459
- // (with an `EmitIsland`). We check this in debug builds. This is `mut`
1460
- // to allow disabling the check for `JTSequence`, which is always
1461
- // emitted following an `EmitIsland`.
1462
- let mut start_off = sink.cur_offset();
1463
-
1464
- match self {
1465
- &Inst::AluRRR { alu_op, rd, rn, rm } => {
1466
- let rd = allocs.next_writable(rd);
1467
- let rn = allocs.next(rn);
1468
- let rm = allocs.next(rm);
1469
-
1470
- let (opcode, have_rr) = match alu_op {
1471
- ALUOp::Add32 => (0xb9f8, true), // ARK
1472
- ALUOp::Add64 => (0xb9e8, true), // AGRK
1473
- ALUOp::AddLogical32 => (0xb9fa, true), // ALRK
1474
- ALUOp::AddLogical64 => (0xb9ea, true), // ALGRK
1475
- ALUOp::Sub32 => (0xb9f9, true), // SRK
1476
- ALUOp::Sub64 => (0xb9e9, true), // SGRK
1477
- ALUOp::SubLogical32 => (0xb9fb, true), // SLRK
1478
- ALUOp::SubLogical64 => (0xb9eb, true), // SLGRK
1479
- ALUOp::Mul32 => (0xb9fd, true), // MSRKC
1480
- ALUOp::Mul64 => (0xb9ed, true), // MSGRKC
1481
- ALUOp::And32 => (0xb9f4, true), // NRK
1482
- ALUOp::And64 => (0xb9e4, true), // NGRK
1483
- ALUOp::Orr32 => (0xb9f6, true), // ORK
1484
- ALUOp::Orr64 => (0xb9e6, true), // OGRK
1485
- ALUOp::Xor32 => (0xb9f7, true), // XRK
1486
- ALUOp::Xor64 => (0xb9e7, true), // XGRK
1487
- ALUOp::NotAnd32 => (0xb974, false), // NNRK
1488
- ALUOp::NotAnd64 => (0xb964, false), // NNGRK
1489
- ALUOp::NotOrr32 => (0xb976, false), // NORK
1490
- ALUOp::NotOrr64 => (0xb966, false), // NOGRK
1491
- ALUOp::NotXor32 => (0xb977, false), // NXRK
1492
- ALUOp::NotXor64 => (0xb967, false), // NXGRK
1493
- ALUOp::AndNot32 => (0xb9f5, false), // NCRK
1494
- ALUOp::AndNot64 => (0xb9e5, false), // NCGRK
1495
- ALUOp::OrrNot32 => (0xb975, false), // OCRK
1496
- ALUOp::OrrNot64 => (0xb965, false), // OCGRK
1497
- _ => unreachable!(),
1498
- };
1499
- if have_rr && rd.to_reg() == rn {
1500
- let inst = Inst::AluRR {
1501
- alu_op,
1502
- rd,
1503
- ri: rn,
1504
- rm,
1505
- };
1506
- inst.emit(&[], sink, emit_info, state);
1507
- } else {
1508
- put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0));
1509
- }
1510
- }
1511
- &Inst::AluRRSImm16 {
1512
- alu_op,
1513
- rd,
1514
- rn,
1515
- imm,
1516
- } => {
1517
- let rd = allocs.next_writable(rd);
1518
- let rn = allocs.next(rn);
1519
-
1520
- if rd.to_reg() == rn {
1521
- let inst = Inst::AluRSImm16 {
1522
- alu_op,
1523
- rd,
1524
- ri: rn,
1525
- imm,
1526
- };
1527
- inst.emit(&[], sink, emit_info, state);
1528
- } else {
1529
- let opcode = match alu_op {
1530
- ALUOp::Add32 => 0xecd8, // AHIK
1531
- ALUOp::Add64 => 0xecd9, // AGHIK
1532
- _ => unreachable!(),
1533
- };
1534
- put(sink, &enc_rie_d(opcode, rd.to_reg(), rn, imm as u16));
1535
- }
1536
- }
1537
- &Inst::AluRR { alu_op, rd, ri, rm } => {
1538
- let rd = allocs.next_writable(rd);
1539
- let ri = allocs.next(ri);
1540
- debug_assert_eq!(rd.to_reg(), ri);
1541
- let rm = allocs.next(rm);
1542
-
1543
- let (opcode, is_rre) = match alu_op {
1544
- ALUOp::Add32 => (0x1a, false), // AR
1545
- ALUOp::Add64 => (0xb908, true), // AGR
1546
- ALUOp::Add64Ext32 => (0xb918, true), // AGFR
1547
- ALUOp::AddLogical32 => (0x1e, false), // ALR
1548
- ALUOp::AddLogical64 => (0xb90a, true), // ALGR
1549
- ALUOp::AddLogical64Ext32 => (0xb91a, true), // ALGFR
1550
- ALUOp::Sub32 => (0x1b, false), // SR
1551
- ALUOp::Sub64 => (0xb909, true), // SGR
1552
- ALUOp::Sub64Ext32 => (0xb919, true), // SGFR
1553
- ALUOp::SubLogical32 => (0x1f, false), // SLR
1554
- ALUOp::SubLogical64 => (0xb90b, true), // SLGR
1555
- ALUOp::SubLogical64Ext32 => (0xb91b, true), // SLGFR
1556
- ALUOp::Mul32 => (0xb252, true), // MSR
1557
- ALUOp::Mul64 => (0xb90c, true), // MSGR
1558
- ALUOp::Mul64Ext32 => (0xb91c, true), // MSGFR
1559
- ALUOp::And32 => (0x14, false), // NR
1560
- ALUOp::And64 => (0xb980, true), // NGR
1561
- ALUOp::Orr32 => (0x16, false), // OR
1562
- ALUOp::Orr64 => (0xb981, true), // OGR
1563
- ALUOp::Xor32 => (0x17, false), // XR
1564
- ALUOp::Xor64 => (0xb982, true), // XGR
1565
- _ => unreachable!(),
1566
- };
1567
- if is_rre {
1568
- put(sink, &enc_rre(opcode, rd.to_reg(), rm));
1569
- } else {
1570
- put(sink, &enc_rr(opcode, rd.to_reg(), rm));
1571
- }
1572
- }
1573
- &Inst::AluRX {
1574
- alu_op,
1575
- rd,
1576
- ri,
1577
- ref mem,
1578
- } => {
1579
- let rd = allocs.next_writable(rd);
1580
- let ri = allocs.next(ri);
1581
- debug_assert_eq!(rd.to_reg(), ri);
1582
- let mem = mem.with_allocs(allocs);
1583
-
1584
- let (opcode_rx, opcode_rxy) = match alu_op {
1585
- ALUOp::Add32 => (Some(0x5a), Some(0xe35a)), // A(Y)
1586
- ALUOp::Add32Ext16 => (Some(0x4a), Some(0xe37a)), // AH(Y)
1587
- ALUOp::Add64 => (None, Some(0xe308)), // AG
1588
- ALUOp::Add64Ext16 => (None, Some(0xe338)), // AGH
1589
- ALUOp::Add64Ext32 => (None, Some(0xe318)), // AGF
1590
- ALUOp::AddLogical32 => (Some(0x5e), Some(0xe35e)), // AL(Y)
1591
- ALUOp::AddLogical64 => (None, Some(0xe30a)), // ALG
1592
- ALUOp::AddLogical64Ext32 => (None, Some(0xe31a)), // ALGF
1593
- ALUOp::Sub32 => (Some(0x5b), Some(0xe35b)), // S(Y)
1594
- ALUOp::Sub32Ext16 => (Some(0x4b), Some(0xe37b)), // SH(Y)
1595
- ALUOp::Sub64 => (None, Some(0xe309)), // SG
1596
- ALUOp::Sub64Ext16 => (None, Some(0xe339)), // SGH
1597
- ALUOp::Sub64Ext32 => (None, Some(0xe319)), // SGF
1598
- ALUOp::SubLogical32 => (Some(0x5f), Some(0xe35f)), // SL(Y)
1599
- ALUOp::SubLogical64 => (None, Some(0xe30b)), // SLG
1600
- ALUOp::SubLogical64Ext32 => (None, Some(0xe31b)), // SLGF
1601
- ALUOp::Mul32 => (Some(0x71), Some(0xe351)), // MS(Y)
1602
- ALUOp::Mul32Ext16 => (Some(0x4c), Some(0xe37c)), // MH(Y)
1603
- ALUOp::Mul64 => (None, Some(0xe30c)), // MSG
1604
- ALUOp::Mul64Ext16 => (None, Some(0xe33c)), // MSH
1605
- ALUOp::Mul64Ext32 => (None, Some(0xe31c)), // MSGF
1606
- ALUOp::And32 => (Some(0x54), Some(0xe354)), // N(Y)
1607
- ALUOp::And64 => (None, Some(0xe380)), // NG
1608
- ALUOp::Orr32 => (Some(0x56), Some(0xe356)), // O(Y)
1609
- ALUOp::Orr64 => (None, Some(0xe381)), // OG
1610
- ALUOp::Xor32 => (Some(0x57), Some(0xe357)), // X(Y)
1611
- ALUOp::Xor64 => (None, Some(0xe382)), // XG
1612
- _ => unreachable!(),
1613
- };
1614
- let rd = rd.to_reg();
1615
- mem_emit(
1616
- rd, &mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state,
1617
- );
1618
- }
1619
- &Inst::AluRSImm16 {
1620
- alu_op,
1621
- rd,
1622
- ri,
1623
- imm,
1624
- } => {
1625
- let rd = allocs.next_writable(rd);
1626
- let ri = allocs.next(ri);
1627
- debug_assert_eq!(rd.to_reg(), ri);
1628
-
1629
- let opcode = match alu_op {
1630
- ALUOp::Add32 => 0xa7a, // AHI
1631
- ALUOp::Add64 => 0xa7b, // AGHI
1632
- ALUOp::Mul32 => 0xa7c, // MHI
1633
- ALUOp::Mul64 => 0xa7d, // MGHI
1634
- _ => unreachable!(),
1635
- };
1636
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
1637
- }
1638
- &Inst::AluRSImm32 {
1639
- alu_op,
1640
- rd,
1641
- ri,
1642
- imm,
1643
- } => {
1644
- let rd = allocs.next_writable(rd);
1645
- let ri = allocs.next(ri);
1646
- debug_assert_eq!(rd.to_reg(), ri);
1647
-
1648
- let opcode = match alu_op {
1649
- ALUOp::Add32 => 0xc29, // AFI
1650
- ALUOp::Add64 => 0xc28, // AGFI
1651
- ALUOp::Mul32 => 0xc21, // MSFI
1652
- ALUOp::Mul64 => 0xc20, // MSGFI
1653
- _ => unreachable!(),
1654
- };
1655
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
1656
- }
1657
- &Inst::AluRUImm32 {
1658
- alu_op,
1659
- rd,
1660
- ri,
1661
- imm,
1662
- } => {
1663
- let rd = allocs.next_writable(rd);
1664
- let ri = allocs.next(ri);
1665
- debug_assert_eq!(rd.to_reg(), ri);
1666
-
1667
- let opcode = match alu_op {
1668
- ALUOp::AddLogical32 => 0xc2b, // ALFI
1669
- ALUOp::AddLogical64 => 0xc2a, // ALGFI
1670
- ALUOp::SubLogical32 => 0xc25, // SLFI
1671
- ALUOp::SubLogical64 => 0xc24, // SLGFI
1672
- _ => unreachable!(),
1673
- };
1674
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
1675
- }
1676
- &Inst::AluRUImm16Shifted {
1677
- alu_op,
1678
- rd,
1679
- ri,
1680
- imm,
1681
- } => {
1682
- let rd = allocs.next_writable(rd);
1683
- let ri = allocs.next(ri);
1684
- debug_assert_eq!(rd.to_reg(), ri);
1685
-
1686
- let opcode = match (alu_op, imm.shift) {
1687
- (ALUOp::And32, 0) => 0xa57, // NILL
1688
- (ALUOp::And32, 1) => 0xa56, // NILH
1689
- (ALUOp::And64, 0) => 0xa57, // NILL
1690
- (ALUOp::And64, 1) => 0xa56, // NILH
1691
- (ALUOp::And64, 2) => 0xa55, // NIHL
1692
- (ALUOp::And64, 3) => 0xa54, // NIHL
1693
- (ALUOp::Orr32, 0) => 0xa5b, // OILL
1694
- (ALUOp::Orr32, 1) => 0xa5a, // OILH
1695
- (ALUOp::Orr64, 0) => 0xa5b, // OILL
1696
- (ALUOp::Orr64, 1) => 0xa5a, // OILH
1697
- (ALUOp::Orr64, 2) => 0xa59, // OIHL
1698
- (ALUOp::Orr64, 3) => 0xa58, // OIHH
1699
- _ => unreachable!(),
1700
- };
1701
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
1702
- }
1703
- &Inst::AluRUImm32Shifted {
1704
- alu_op,
1705
- rd,
1706
- ri,
1707
- imm,
1708
- } => {
1709
- let rd = allocs.next_writable(rd);
1710
- let ri = allocs.next(ri);
1711
- debug_assert_eq!(rd.to_reg(), ri);
1712
-
1713
- let opcode = match (alu_op, imm.shift) {
1714
- (ALUOp::And32, 0) => 0xc0b, // NILF
1715
- (ALUOp::And64, 0) => 0xc0b, // NILF
1716
- (ALUOp::And64, 1) => 0xc0a, // NIHF
1717
- (ALUOp::Orr32, 0) => 0xc0d, // OILF
1718
- (ALUOp::Orr64, 0) => 0xc0d, // OILF
1719
- (ALUOp::Orr64, 1) => 0xc0c, // OILF
1720
- (ALUOp::Xor32, 0) => 0xc07, // XILF
1721
- (ALUOp::Xor64, 0) => 0xc07, // XILF
1722
- (ALUOp::Xor64, 1) => 0xc06, // XILH
1723
- _ => unreachable!(),
1724
- };
1725
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
1726
- }
1727
-
1728
- &Inst::SMulWide { rd, rn, rm } => {
1729
- let rn = allocs.next(rn);
1730
- let rm = allocs.next(rm);
1731
- let rd1 = allocs.next_writable(rd.hi);
1732
- let rd2 = allocs.next_writable(rd.lo);
1733
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1734
-
1735
- let opcode = 0xb9ec; // MGRK
1736
- put(sink, &enc_rrf_ab(opcode, rd1.to_reg(), rn, rm, 0));
1737
- }
1738
- &Inst::UMulWide { rd, ri, rn } => {
1739
- let rn = allocs.next(rn);
1740
- let rd1 = allocs.next_writable(rd.hi);
1741
- let rd2 = allocs.next_writable(rd.lo);
1742
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1743
- let ri = allocs.next(ri);
1744
- debug_assert_eq!(rd2.to_reg(), ri);
1745
-
1746
- let opcode = 0xb986; // MLGR
1747
- put(sink, &enc_rre(opcode, rd1.to_reg(), rn));
1748
- }
1749
- &Inst::SDivMod32 { rd, ri, rn } => {
1750
- let rn = allocs.next(rn);
1751
- let rd1 = allocs.next_writable(rd.hi);
1752
- let rd2 = allocs.next_writable(rd.lo);
1753
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1754
- let ri = allocs.next(ri);
1755
- debug_assert_eq!(rd2.to_reg(), ri);
1756
-
1757
- let opcode = 0xb91d; // DSGFR
1758
- let trap_code = TrapCode::IntegerDivisionByZero;
1759
- put_with_trap(sink, &enc_rre(opcode, rd1.to_reg(), rn), trap_code);
1760
- }
1761
- &Inst::SDivMod64 { rd, ri, rn } => {
1762
- let rn = allocs.next(rn);
1763
- let rd1 = allocs.next_writable(rd.hi);
1764
- let rd2 = allocs.next_writable(rd.lo);
1765
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1766
- let ri = allocs.next(ri);
1767
- debug_assert_eq!(rd2.to_reg(), ri);
1768
-
1769
- let opcode = 0xb90d; // DSGR
1770
- let trap_code = TrapCode::IntegerDivisionByZero;
1771
- put_with_trap(sink, &enc_rre(opcode, rd1.to_reg(), rn), trap_code);
1772
- }
1773
- &Inst::UDivMod32 { rd, ri, rn } => {
1774
- let rn = allocs.next(rn);
1775
- let rd1 = allocs.next_writable(rd.hi);
1776
- let rd2 = allocs.next_writable(rd.lo);
1777
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1778
- let ri1 = allocs.next(ri.hi);
1779
- let ri2 = allocs.next(ri.lo);
1780
- debug_assert_eq!(rd1.to_reg(), ri1);
1781
- debug_assert_eq!(rd2.to_reg(), ri2);
1782
-
1783
- let opcode = 0xb997; // DLR
1784
- let trap_code = TrapCode::IntegerDivisionByZero;
1785
- put_with_trap(sink, &enc_rre(opcode, rd1.to_reg(), rn), trap_code);
1786
- }
1787
- &Inst::UDivMod64 { rd, ri, rn } => {
1788
- let rn = allocs.next(rn);
1789
- let rd1 = allocs.next_writable(rd.hi);
1790
- let rd2 = allocs.next_writable(rd.lo);
1791
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1792
- let ri1 = allocs.next(ri.hi);
1793
- let ri2 = allocs.next(ri.lo);
1794
- debug_assert_eq!(rd1.to_reg(), ri1);
1795
- debug_assert_eq!(rd2.to_reg(), ri2);
1796
-
1797
- let opcode = 0xb987; // DLGR
1798
- let trap_code = TrapCode::IntegerDivisionByZero;
1799
- put_with_trap(sink, &enc_rre(opcode, rd1.to_reg(), rn), trap_code);
1800
- }
1801
- &Inst::Flogr { rd, rn } => {
1802
- let rn = allocs.next(rn);
1803
- let rd1 = allocs.next_writable(rd.hi);
1804
- let rd2 = allocs.next_writable(rd.lo);
1805
- debug_assert_valid_regpair!(rd1.to_reg(), rd2.to_reg());
1806
-
1807
- let opcode = 0xb983; // FLOGR
1808
- put(sink, &enc_rre(opcode, rd1.to_reg(), rn));
1809
- }
1810
-
1811
- &Inst::ShiftRR {
1812
- shift_op,
1813
- rd,
1814
- rn,
1815
- shift_imm,
1816
- shift_reg,
1817
- } => {
1818
- let rd = allocs.next_writable(rd);
1819
- let rn = allocs.next(rn);
1820
- let shift_reg = allocs.next(shift_reg);
1821
-
1822
- let opcode = match shift_op {
1823
- ShiftOp::RotL32 => 0xeb1d, // RLL
1824
- ShiftOp::RotL64 => 0xeb1c, // RLLG
1825
- ShiftOp::LShL32 => 0xebdf, // SLLK (SLL ?)
1826
- ShiftOp::LShL64 => 0xeb0d, // SLLG
1827
- ShiftOp::LShR32 => 0xebde, // SRLK (SRL ?)
1828
- ShiftOp::LShR64 => 0xeb0c, // SRLG
1829
- ShiftOp::AShR32 => 0xebdc, // SRAK (SRA ?)
1830
- ShiftOp::AShR64 => 0xeb0a, // SRAG
1831
- };
1832
- put(
1833
- sink,
1834
- &enc_rsy(opcode, rd.to_reg(), rn, shift_reg, shift_imm.into()),
1835
- );
1836
- }
1837
-
1838
- &Inst::RxSBG {
1839
- op,
1840
- rd,
1841
- ri,
1842
- rn,
1843
- start_bit,
1844
- end_bit,
1845
- rotate_amt,
1846
- } => {
1847
- let rd = allocs.next_writable(rd);
1848
- let ri = allocs.next(ri);
1849
- debug_assert_eq!(rd.to_reg(), ri);
1850
- let rn = allocs.next(rn);
1851
-
1852
- let opcode = match op {
1853
- RxSBGOp::Insert => 0xec59, // RISBGN
1854
- RxSBGOp::And => 0xec54, // RNSBG
1855
- RxSBGOp::Or => 0xec56, // ROSBG
1856
- RxSBGOp::Xor => 0xec57, // RXSBG
1857
- };
1858
- put(
1859
- sink,
1860
- &enc_rie_f(
1861
- opcode,
1862
- rd.to_reg(),
1863
- rn,
1864
- start_bit,
1865
- end_bit,
1866
- (rotate_amt as u8) & 63,
1867
- ),
1868
- );
1869
- }
1870
-
1871
- &Inst::RxSBGTest {
1872
- op,
1873
- rd,
1874
- rn,
1875
- start_bit,
1876
- end_bit,
1877
- rotate_amt,
1878
- } => {
1879
- let rd = allocs.next(rd);
1880
- let rn = allocs.next(rn);
1881
-
1882
- let opcode = match op {
1883
- RxSBGOp::And => 0xec54, // RNSBG
1884
- RxSBGOp::Or => 0xec56, // ROSBG
1885
- RxSBGOp::Xor => 0xec57, // RXSBG
1886
- _ => unreachable!(),
1887
- };
1888
- put(
1889
- sink,
1890
- &enc_rie_f(
1891
- opcode,
1892
- rd,
1893
- rn,
1894
- start_bit | 0x80,
1895
- end_bit,
1896
- (rotate_amt as u8) & 63,
1897
- ),
1898
- );
1899
- }
1900
-
1901
- &Inst::UnaryRR { op, rd, rn } => {
1902
- let rd = allocs.next_writable(rd);
1903
- let rn = allocs.next(rn);
1904
-
1905
- match op {
1906
- UnaryOp::Abs32 => {
1907
- let opcode = 0x10; // LPR
1908
- put(sink, &enc_rr(opcode, rd.to_reg(), rn));
1909
- }
1910
- UnaryOp::Abs64 => {
1911
- let opcode = 0xb900; // LPGR
1912
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1913
- }
1914
- UnaryOp::Abs64Ext32 => {
1915
- let opcode = 0xb910; // LPGFR
1916
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1917
- }
1918
- UnaryOp::Neg32 => {
1919
- let opcode = 0x13; // LCR
1920
- put(sink, &enc_rr(opcode, rd.to_reg(), rn));
1921
- }
1922
- UnaryOp::Neg64 => {
1923
- let opcode = 0xb903; // LCGR
1924
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1925
- }
1926
- UnaryOp::Neg64Ext32 => {
1927
- let opcode = 0xb913; // LCGFR
1928
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1929
- }
1930
- UnaryOp::PopcntByte => {
1931
- let opcode = 0xb9e1; // POPCNT
1932
- put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 0, 0));
1933
- }
1934
- UnaryOp::PopcntReg => {
1935
- let opcode = 0xb9e1; // POPCNT
1936
- put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 8, 0));
1937
- }
1938
- UnaryOp::BSwap32 => {
1939
- let opcode = 0xb91f; // LRVR
1940
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1941
- }
1942
- UnaryOp::BSwap64 => {
1943
- let opcode = 0xb90f; // LRVRG
1944
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1945
- }
1946
- }
1947
- }
1948
-
1949
- &Inst::Extend {
1950
- rd,
1951
- rn,
1952
- signed,
1953
- from_bits,
1954
- to_bits,
1955
- } => {
1956
- let rd = allocs.next_writable(rd);
1957
- let rn = allocs.next(rn);
1958
-
1959
- let opcode = match (signed, from_bits, to_bits) {
1960
- (_, 1, 32) => 0xb926, // LBR
1961
- (_, 1, 64) => 0xb906, // LGBR
1962
- (false, 8, 32) => 0xb994, // LLCR
1963
- (false, 8, 64) => 0xb984, // LLGCR
1964
- (true, 8, 32) => 0xb926, // LBR
1965
- (true, 8, 64) => 0xb906, // LGBR
1966
- (false, 16, 32) => 0xb995, // LLHR
1967
- (false, 16, 64) => 0xb985, // LLGHR
1968
- (true, 16, 32) => 0xb927, // LHR
1969
- (true, 16, 64) => 0xb907, // LGHR
1970
- (false, 32, 64) => 0xb916, // LLGFR
1971
- (true, 32, 64) => 0xb914, // LGFR
1972
- _ => panic!(
1973
- "Unsupported extend combination: signed = {}, from_bits = {}, to_bits = {}",
1974
- signed, from_bits, to_bits
1975
- ),
1976
- };
1977
- put(sink, &enc_rre(opcode, rd.to_reg(), rn));
1978
- }
1979
-
1980
- &Inst::CmpRR { op, rn, rm } => {
1981
- let rn = allocs.next(rn);
1982
- let rm = allocs.next(rm);
1983
-
1984
- let (opcode, is_rre) = match op {
1985
- CmpOp::CmpS32 => (0x19, false), // CR
1986
- CmpOp::CmpS64 => (0xb920, true), // CGR
1987
- CmpOp::CmpS64Ext32 => (0xb930, true), // CGFR
1988
- CmpOp::CmpL32 => (0x15, false), // CLR
1989
- CmpOp::CmpL64 => (0xb921, true), // CLGR
1990
- CmpOp::CmpL64Ext32 => (0xb931, true), // CLGFR
1991
- _ => unreachable!(),
1992
- };
1993
- if is_rre {
1994
- put(sink, &enc_rre(opcode, rn, rm));
1995
- } else {
1996
- put(sink, &enc_rr(opcode, rn, rm));
1997
- }
1998
- }
1999
- &Inst::CmpRX { op, rn, ref mem } => {
2000
- let rn = allocs.next(rn);
2001
- let mem = mem.with_allocs(allocs);
2002
-
2003
- let (opcode_rx, opcode_rxy, opcode_ril) = match op {
2004
- CmpOp::CmpS32 => (Some(0x59), Some(0xe359), Some(0xc6d)), // C(Y), CRL
2005
- CmpOp::CmpS32Ext16 => (Some(0x49), Some(0xe379), Some(0xc65)), // CH(Y), CHRL
2006
- CmpOp::CmpS64 => (None, Some(0xe320), Some(0xc68)), // CG, CGRL
2007
- CmpOp::CmpS64Ext16 => (None, Some(0xe334), Some(0xc64)), // CGH, CGHRL
2008
- CmpOp::CmpS64Ext32 => (None, Some(0xe330), Some(0xc6c)), // CGF, CGFRL
2009
- CmpOp::CmpL32 => (Some(0x55), Some(0xe355), Some(0xc6f)), // CL(Y), CLRL
2010
- CmpOp::CmpL32Ext16 => (None, None, Some(0xc67)), // CLHRL
2011
- CmpOp::CmpL64 => (None, Some(0xe321), Some(0xc6a)), // CLG, CLGRL
2012
- CmpOp::CmpL64Ext16 => (None, None, Some(0xc66)), // CLGHRL
2013
- CmpOp::CmpL64Ext32 => (None, Some(0xe331), Some(0xc6e)), // CLGF, CLGFRL
2014
- };
2015
- mem_emit(
2016
- rn, &mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
2017
- );
2018
- }
2019
- &Inst::CmpRSImm16 { op, rn, imm } => {
2020
- let rn = allocs.next(rn);
2021
-
2022
- let opcode = match op {
2023
- CmpOp::CmpS32 => 0xa7e, // CHI
2024
- CmpOp::CmpS64 => 0xa7f, // CGHI
2025
- _ => unreachable!(),
2026
- };
2027
- put(sink, &enc_ri_a(opcode, rn, imm as u16));
2028
- }
2029
- &Inst::CmpRSImm32 { op, rn, imm } => {
2030
- let rn = allocs.next(rn);
2031
-
2032
- let opcode = match op {
2033
- CmpOp::CmpS32 => 0xc2d, // CFI
2034
- CmpOp::CmpS64 => 0xc2c, // CGFI
2035
- _ => unreachable!(),
2036
- };
2037
- put(sink, &enc_ril_a(opcode, rn, imm as u32));
2038
- }
2039
- &Inst::CmpRUImm32 { op, rn, imm } => {
2040
- let rn = allocs.next(rn);
2041
-
2042
- let opcode = match op {
2043
- CmpOp::CmpL32 => 0xc2f, // CLFI
2044
- CmpOp::CmpL64 => 0xc2e, // CLGFI
2045
- _ => unreachable!(),
2046
- };
2047
- put(sink, &enc_ril_a(opcode, rn, imm));
2048
- }
2049
- &Inst::CmpTrapRR {
2050
- op,
2051
- rn,
2052
- rm,
2053
- cond,
2054
- trap_code,
2055
- } => {
2056
- let rn = allocs.next(rn);
2057
- let rm = allocs.next(rm);
2058
-
2059
- let opcode = match op {
2060
- CmpOp::CmpS32 => 0xb972, // CRT
2061
- CmpOp::CmpS64 => 0xb960, // CGRT
2062
- CmpOp::CmpL32 => 0xb973, // CLRT
2063
- CmpOp::CmpL64 => 0xb961, // CLGRT
2064
- _ => unreachable!(),
2065
- };
2066
- put_with_trap(
2067
- sink,
2068
- &enc_rrf_cde(opcode, rn, rm, cond.bits(), 0),
2069
- trap_code,
2070
- );
2071
- }
2072
- &Inst::CmpTrapRSImm16 {
2073
- op,
2074
- rn,
2075
- imm,
2076
- cond,
2077
- trap_code,
2078
- } => {
2079
- let rn = allocs.next(rn);
2080
-
2081
- let opcode = match op {
2082
- CmpOp::CmpS32 => 0xec72, // CIT
2083
- CmpOp::CmpS64 => 0xec70, // CGIT
2084
- _ => unreachable!(),
2085
- };
2086
- put_with_trap(
2087
- sink,
2088
- &enc_rie_a(opcode, rn, imm as u16, cond.bits()),
2089
- trap_code,
2090
- );
2091
- }
2092
- &Inst::CmpTrapRUImm16 {
2093
- op,
2094
- rn,
2095
- imm,
2096
- cond,
2097
- trap_code,
2098
- } => {
2099
- let rn = allocs.next(rn);
2100
-
2101
- let opcode = match op {
2102
- CmpOp::CmpL32 => 0xec73, // CLFIT
2103
- CmpOp::CmpL64 => 0xec71, // CLGIT
2104
- _ => unreachable!(),
2105
- };
2106
- put_with_trap(sink, &enc_rie_a(opcode, rn, imm, cond.bits()), trap_code);
2107
- }
2108
-
2109
- &Inst::AtomicRmw {
2110
- alu_op,
2111
- rd,
2112
- rn,
2113
- ref mem,
2114
- } => {
2115
- let rd = allocs.next_writable(rd);
2116
- let rn = allocs.next(rn);
2117
- let mem = mem.with_allocs(allocs);
2118
-
2119
- let opcode = match alu_op {
2120
- ALUOp::Add32 => 0xebf8, // LAA
2121
- ALUOp::Add64 => 0xebe8, // LAAG
2122
- ALUOp::AddLogical32 => 0xebfa, // LAAL
2123
- ALUOp::AddLogical64 => 0xebea, // LAALG
2124
- ALUOp::And32 => 0xebf4, // LAN
2125
- ALUOp::And64 => 0xebe4, // LANG
2126
- ALUOp::Orr32 => 0xebf6, // LAO
2127
- ALUOp::Orr64 => 0xebe6, // LAOG
2128
- ALUOp::Xor32 => 0xebf7, // LAX
2129
- ALUOp::Xor64 => 0xebe7, // LAXG
2130
- _ => unreachable!(),
2131
- };
2132
-
2133
- let rd = rd.to_reg();
2134
- mem_rs_emit(
2135
- rd,
2136
- rn,
2137
- &mem,
2138
- None,
2139
- Some(opcode),
2140
- true,
2141
- sink,
2142
- emit_info,
2143
- state,
2144
- );
2145
- }
2146
- &Inst::Loop { ref body, cond } => {
2147
- // This sequence is *one* instruction in the vcode, and is expanded only here at
2148
- // emission time, because it requires branching to internal labels.
2149
- let loop_label = sink.get_label();
2150
- let done_label = sink.get_label();
2151
-
2152
- // Emit label at the start of the loop.
2153
- sink.bind_label(loop_label, &mut state.ctrl_plane);
2154
-
2155
- for inst in (&body).into_iter() {
2156
- match &inst {
2157
- // Replace a CondBreak with a branch to done_label.
2158
- &Inst::CondBreak { cond } => {
2159
- let inst = Inst::OneWayCondBr {
2160
- target: done_label,
2161
- cond: *cond,
2162
- };
2163
- inst.emit_with_alloc_consumer(allocs, sink, emit_info, state);
2164
- }
2165
- _ => inst.emit_with_alloc_consumer(allocs, sink, emit_info, state),
2166
- };
2167
- }
2168
-
2169
- let inst = Inst::OneWayCondBr {
2170
- target: loop_label,
2171
- cond,
2172
- };
2173
- inst.emit(&[], sink, emit_info, state);
2174
-
2175
- // Emit label at the end of the loop.
2176
- sink.bind_label(done_label, &mut state.ctrl_plane);
2177
- }
2178
- &Inst::CondBreak { .. } => unreachable!(), // Only valid inside a Loop.
2179
- &Inst::AtomicCas32 {
2180
- rd,
2181
- ri,
2182
- rn,
2183
- ref mem,
2184
- }
2185
- | &Inst::AtomicCas64 {
2186
- rd,
2187
- ri,
2188
- rn,
2189
- ref mem,
2190
- } => {
2191
- let rd = allocs.next_writable(rd);
2192
- let ri = allocs.next(ri);
2193
- debug_assert_eq!(rd.to_reg(), ri);
2194
- let rn = allocs.next(rn);
2195
- let mem = mem.with_allocs(allocs);
2196
-
2197
- let (opcode_rs, opcode_rsy) = match self {
2198
- &Inst::AtomicCas32 { .. } => (Some(0xba), Some(0xeb14)), // CS(Y)
2199
- &Inst::AtomicCas64 { .. } => (None, Some(0xeb30)), // CSG
2200
- _ => unreachable!(),
2201
- };
2202
-
2203
- let rd = rd.to_reg();
2204
- mem_rs_emit(
2205
- rd, rn, &mem, opcode_rs, opcode_rsy, true, sink, emit_info, state,
2206
- );
2207
- }
2208
- &Inst::Fence => {
2209
- put(sink, &enc_e(0x07e0));
2210
- }
2211
-
2212
- &Inst::Load32 { rd, ref mem }
2213
- | &Inst::Load32ZExt8 { rd, ref mem }
2214
- | &Inst::Load32SExt8 { rd, ref mem }
2215
- | &Inst::Load32ZExt16 { rd, ref mem }
2216
- | &Inst::Load32SExt16 { rd, ref mem }
2217
- | &Inst::Load64 { rd, ref mem }
2218
- | &Inst::Load64ZExt8 { rd, ref mem }
2219
- | &Inst::Load64SExt8 { rd, ref mem }
2220
- | &Inst::Load64ZExt16 { rd, ref mem }
2221
- | &Inst::Load64SExt16 { rd, ref mem }
2222
- | &Inst::Load64ZExt32 { rd, ref mem }
2223
- | &Inst::Load64SExt32 { rd, ref mem }
2224
- | &Inst::LoadRev16 { rd, ref mem }
2225
- | &Inst::LoadRev32 { rd, ref mem }
2226
- | &Inst::LoadRev64 { rd, ref mem } => {
2227
- let rd = allocs.next_writable(rd);
2228
- let mem = mem.with_allocs(allocs);
2229
-
2230
- let (opcode_rx, opcode_rxy, opcode_ril) = match self {
2231
- &Inst::Load32 { .. } => (Some(0x58), Some(0xe358), Some(0xc4d)), // L(Y), LRL
2232
- &Inst::Load32ZExt8 { .. } => (None, Some(0xe394), None), // LLC
2233
- &Inst::Load32SExt8 { .. } => (None, Some(0xe376), None), // LB
2234
- &Inst::Load32ZExt16 { .. } => (None, Some(0xe395), Some(0xc42)), // LLH, LLHRL
2235
- &Inst::Load32SExt16 { .. } => (Some(0x48), Some(0xe378), Some(0xc45)), // LH(Y), LHRL
2236
- &Inst::Load64 { .. } => (None, Some(0xe304), Some(0xc48)), // LG, LGRL
2237
- &Inst::Load64ZExt8 { .. } => (None, Some(0xe390), None), // LLGC
2238
- &Inst::Load64SExt8 { .. } => (None, Some(0xe377), None), // LGB
2239
- &Inst::Load64ZExt16 { .. } => (None, Some(0xe391), Some(0xc46)), // LLGH, LLGHRL
2240
- &Inst::Load64SExt16 { .. } => (None, Some(0xe315), Some(0xc44)), // LGH, LGHRL
2241
- &Inst::Load64ZExt32 { .. } => (None, Some(0xe316), Some(0xc4e)), // LLGF, LLGFRL
2242
- &Inst::Load64SExt32 { .. } => (None, Some(0xe314), Some(0xc4c)), // LGF, LGFRL
2243
- &Inst::LoadRev16 { .. } => (None, Some(0xe31f), None), // LRVH
2244
- &Inst::LoadRev32 { .. } => (None, Some(0xe31e), None), // LRV
2245
- &Inst::LoadRev64 { .. } => (None, Some(0xe30f), None), // LRVG
2246
- _ => unreachable!(),
2247
- };
2248
- let rd = rd.to_reg();
2249
- mem_emit(
2250
- rd, &mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
2251
- );
2252
- }
2253
-
2254
- &Inst::Store8 { rd, ref mem }
2255
- | &Inst::Store16 { rd, ref mem }
2256
- | &Inst::Store32 { rd, ref mem }
2257
- | &Inst::Store64 { rd, ref mem }
2258
- | &Inst::StoreRev16 { rd, ref mem }
2259
- | &Inst::StoreRev32 { rd, ref mem }
2260
- | &Inst::StoreRev64 { rd, ref mem } => {
2261
- let rd = allocs.next(rd);
2262
- let mem = mem.with_allocs(allocs);
2263
-
2264
- let (opcode_rx, opcode_rxy, opcode_ril) = match self {
2265
- &Inst::Store8 { .. } => (Some(0x42), Some(0xe372), None), // STC(Y)
2266
- &Inst::Store16 { .. } => (Some(0x40), Some(0xe370), Some(0xc47)), // STH(Y), STHRL
2267
- &Inst::Store32 { .. } => (Some(0x50), Some(0xe350), Some(0xc4f)), // ST(Y), STRL
2268
- &Inst::Store64 { .. } => (None, Some(0xe324), Some(0xc4b)), // STG, STGRL
2269
- &Inst::StoreRev16 { .. } => (None, Some(0xe33f), None), // STRVH
2270
- &Inst::StoreRev32 { .. } => (None, Some(0xe33e), None), // STRV
2271
- &Inst::StoreRev64 { .. } => (None, Some(0xe32f), None), // STRVG
2272
- _ => unreachable!(),
2273
- };
2274
- mem_emit(
2275
- rd, &mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
2276
- );
2277
- }
2278
- &Inst::StoreImm8 { imm, ref mem } => {
2279
- let mem = mem.with_allocs(allocs);
2280
-
2281
- let opcode_si = 0x92; // MVI
2282
- let opcode_siy = 0xeb52; // MVIY
2283
- mem_imm8_emit(
2284
- imm, &mem, opcode_si, opcode_siy, true, sink, emit_info, state,
2285
- );
2286
- }
2287
- &Inst::StoreImm16 { imm, ref mem }
2288
- | &Inst::StoreImm32SExt16 { imm, ref mem }
2289
- | &Inst::StoreImm64SExt16 { imm, ref mem } => {
2290
- let mem = mem.with_allocs(allocs);
2291
-
2292
- let opcode = match self {
2293
- &Inst::StoreImm16 { .. } => 0xe544, // MVHHI
2294
- &Inst::StoreImm32SExt16 { .. } => 0xe54c, // MVHI
2295
- &Inst::StoreImm64SExt16 { .. } => 0xe548, // MVGHI
2296
- _ => unreachable!(),
2297
- };
2298
- mem_imm16_emit(imm, &mem, opcode, true, sink, emit_info, state);
2299
- }
2300
- &Inst::Mvc {
2301
- ref dst,
2302
- ref src,
2303
- len_minus_one,
2304
- } => {
2305
- let dst = dst.with_allocs(allocs);
2306
- let src = src.with_allocs(allocs);
2307
- let opcode = 0xd2; // MVC
2308
- mem_mem_emit(&dst, &src, len_minus_one, opcode, true, sink, state);
2309
- }
2310
-
2311
- &Inst::LoadMultiple64 { rt, rt2, ref mem } => {
2312
- let mem = mem.with_allocs(allocs);
2313
-
2314
- let opcode = 0xeb04; // LMG
2315
- let rt = rt.to_reg();
2316
- let rt2 = rt2.to_reg();
2317
- mem_rs_emit(
2318
- rt,
2319
- rt2,
2320
- &mem,
2321
- None,
2322
- Some(opcode),
2323
- true,
2324
- sink,
2325
- emit_info,
2326
- state,
2327
- );
2328
- }
2329
- &Inst::StoreMultiple64 { rt, rt2, ref mem } => {
2330
- let mem = mem.with_allocs(allocs);
2331
-
2332
- let opcode = 0xeb24; // STMG
2333
- mem_rs_emit(
2334
- rt,
2335
- rt2,
2336
- &mem,
2337
- None,
2338
- Some(opcode),
2339
- true,
2340
- sink,
2341
- emit_info,
2342
- state,
2343
- );
2344
- }
2345
-
2346
- &Inst::LoadAddr { rd, ref mem } => {
2347
- let rd = allocs.next_writable(rd);
2348
- let mem = mem.with_allocs(allocs);
2349
-
2350
- let opcode_rx = Some(0x41); // LA
2351
- let opcode_rxy = Some(0xe371); // LAY
2352
- let opcode_ril = Some(0xc00); // LARL
2353
- let rd = rd.to_reg();
2354
- mem_emit(
2355
- rd, &mem, opcode_rx, opcode_rxy, opcode_ril, false, sink, emit_info, state,
2356
- );
2357
- }
2358
-
2359
- &Inst::Mov64 { rd, rm } => {
2360
- let rd = allocs.next_writable(rd);
2361
- let rm = allocs.next(rm);
2362
-
2363
- let opcode = 0xb904; // LGR
2364
- put(sink, &enc_rre(opcode, rd.to_reg(), rm));
2365
- }
2366
- &Inst::MovPReg { rd, rm } => {
2367
- let rm: Reg = rm.into();
2368
- debug_assert!([regs::gpr(0), regs::gpr(14), regs::gpr(15)].contains(&rm));
2369
- let rd = allocs.next_writable(rd);
2370
- Inst::Mov64 { rd, rm }.emit(&[], sink, emit_info, state);
2371
- }
2372
- &Inst::Mov32 { rd, rm } => {
2373
- let rd = allocs.next_writable(rd);
2374
- let rm = allocs.next(rm);
2375
-
2376
- let opcode = 0x18; // LR
2377
- put(sink, &enc_rr(opcode, rd.to_reg(), rm));
2378
- }
2379
- &Inst::Mov32Imm { rd, imm } => {
2380
- let rd = allocs.next_writable(rd);
2381
-
2382
- let opcode = 0xc09; // IILF
2383
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
2384
- }
2385
- &Inst::Mov32SImm16 { rd, imm } => {
2386
- let rd = allocs.next_writable(rd);
2387
-
2388
- let opcode = 0xa78; // LHI
2389
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
2390
- }
2391
- &Inst::Mov64SImm16 { rd, imm } => {
2392
- let rd = allocs.next_writable(rd);
2393
-
2394
- let opcode = 0xa79; // LGHI
2395
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
2396
- }
2397
- &Inst::Mov64SImm32 { rd, imm } => {
2398
- let rd = allocs.next_writable(rd);
2399
-
2400
- let opcode = 0xc01; // LGFI
2401
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
2402
- }
2403
- &Inst::CMov32 { rd, cond, ri, rm } => {
2404
- let rd = allocs.next_writable(rd);
2405
- let ri = allocs.next(ri);
2406
- debug_assert_eq!(rd.to_reg(), ri);
2407
- let rm = allocs.next(rm);
2408
-
2409
- let opcode = 0xb9f2; // LOCR
2410
- put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
2411
- }
2412
- &Inst::CMov64 { rd, cond, ri, rm } => {
2413
- let rd = allocs.next_writable(rd);
2414
- let ri = allocs.next(ri);
2415
- debug_assert_eq!(rd.to_reg(), ri);
2416
- let rm = allocs.next(rm);
2417
-
2418
- let opcode = 0xb9e2; // LOCGR
2419
- put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
2420
- }
2421
- &Inst::CMov32SImm16 { rd, cond, ri, imm } => {
2422
- let rd = allocs.next_writable(rd);
2423
- let ri = allocs.next(ri);
2424
- debug_assert_eq!(rd.to_reg(), ri);
2425
-
2426
- let opcode = 0xec42; // LOCHI
2427
- put(
2428
- sink,
2429
- &enc_rie_g(opcode, rd.to_reg(), imm as u16, cond.bits()),
2430
- );
2431
- }
2432
- &Inst::CMov64SImm16 { rd, cond, ri, imm } => {
2433
- let rd = allocs.next_writable(rd);
2434
- let ri = allocs.next(ri);
2435
- debug_assert_eq!(rd.to_reg(), ri);
2436
-
2437
- let opcode = 0xec46; // LOCGHI
2438
- put(
2439
- sink,
2440
- &enc_rie_g(opcode, rd.to_reg(), imm as u16, cond.bits()),
2441
- );
2442
- }
2443
- &Inst::Mov64UImm16Shifted { rd, imm } => {
2444
- let rd = allocs.next_writable(rd);
2445
-
2446
- let opcode = match imm.shift {
2447
- 0 => 0xa5f, // LLILL
2448
- 1 => 0xa5e, // LLILH
2449
- 2 => 0xa5d, // LLIHL
2450
- 3 => 0xa5c, // LLIHH
2451
- _ => unreachable!(),
2452
- };
2453
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
2454
- }
2455
- &Inst::Mov64UImm32Shifted { rd, imm } => {
2456
- let rd = allocs.next_writable(rd);
2457
-
2458
- let opcode = match imm.shift {
2459
- 0 => 0xc0f, // LLILF
2460
- 1 => 0xc0e, // LLIHF
2461
- _ => unreachable!(),
2462
- };
2463
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
2464
- }
2465
- &Inst::Insert64UImm16Shifted { rd, ri, imm } => {
2466
- let rd = allocs.next_writable(rd);
2467
- let ri = allocs.next(ri);
2468
- debug_assert_eq!(rd.to_reg(), ri);
2469
-
2470
- let opcode = match imm.shift {
2471
- 0 => 0xa53, // IILL
2472
- 1 => 0xa52, // IILH
2473
- 2 => 0xa51, // IIHL
2474
- 3 => 0xa50, // IIHH
2475
- _ => unreachable!(),
2476
- };
2477
- put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
2478
- }
2479
- &Inst::Insert64UImm32Shifted { rd, ri, imm } => {
2480
- let rd = allocs.next_writable(rd);
2481
- let ri = allocs.next(ri);
2482
- debug_assert_eq!(rd.to_reg(), ri);
2483
-
2484
- let opcode = match imm.shift {
2485
- 0 => 0xc09, // IILF
2486
- 1 => 0xc08, // IIHF
2487
- _ => unreachable!(),
2488
- };
2489
- put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
2490
- }
2491
- &Inst::LoadAR { rd, ar } => {
2492
- let rd = allocs.next_writable(rd);
2493
- let opcode = 0xb24f; // EAR
2494
- put(sink, &enc_rre(opcode, rd.to_reg(), gpr(ar)));
2495
- }
2496
-
2497
- &Inst::InsertAR { rd, ri, ar } => {
2498
- let rd = allocs.next_writable(rd);
2499
- let ri = allocs.next(ri);
2500
- debug_assert_eq!(rd.to_reg(), ri);
2501
-
2502
- let opcode = 0xb24f; // EAR
2503
- put(sink, &enc_rre(opcode, rd.to_reg(), gpr(ar)));
2504
- }
2505
- &Inst::LoadSymbolReloc {
2506
- rd,
2507
- ref symbol_reloc,
2508
- } => {
2509
- let rd = allocs.next_writable(rd);
2510
-
2511
- let opcode = 0xa75; // BRAS
2512
- let reg = writable_spilltmp_reg().to_reg();
2513
- put(sink, &enc_ri_b(opcode, reg, 12));
2514
- let (reloc, name, offset) = match &**symbol_reloc {
2515
- SymbolReloc::Absolute { name, offset } => (Reloc::Abs8, name, *offset),
2516
- SymbolReloc::TlsGd { name } => (Reloc::S390xTlsGd64, name, 0),
2517
- };
2518
- sink.add_reloc(reloc, name, offset);
2519
- sink.put8(0);
2520
- let inst = Inst::Load64 {
2521
- rd,
2522
- mem: MemArg::reg(reg, MemFlags::trusted()),
2523
- };
2524
- inst.emit(&[], sink, emit_info, state);
2525
- }
2526
-
2527
- &Inst::FpuMove32 { rd, rn } => {
2528
- let rd = allocs.next_writable(rd);
2529
- let rn = allocs.next(rn);
2530
-
2531
- if is_fpr(rd.to_reg()) && is_fpr(rn) {
2532
- let opcode = 0x38; // LER
2533
- put(sink, &enc_rr(opcode, rd.to_reg(), rn));
2534
- } else {
2535
- let opcode = 0xe756; // VLR
2536
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, 0, 0, 0));
2537
- }
2538
- }
2539
- &Inst::FpuMove64 { rd, rn } => {
2540
- let rd = allocs.next_writable(rd);
2541
- let rn = allocs.next(rn);
2542
-
2543
- if is_fpr(rd.to_reg()) && is_fpr(rn) {
2544
- let opcode = 0x28; // LDR
2545
- put(sink, &enc_rr(opcode, rd.to_reg(), rn));
2546
- } else {
2547
- let opcode = 0xe756; // VLR
2548
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, 0, 0, 0));
2549
- }
2550
- }
2551
- &Inst::FpuCMov32 { rd, cond, ri, rm } => {
2552
- let rd = allocs.next_writable(rd);
2553
- let ri = allocs.next(ri);
2554
- debug_assert_eq!(rd.to_reg(), ri);
2555
- let rm = allocs.next(rm);
2556
-
2557
- if is_fpr(rd.to_reg()) && is_fpr(rm) {
2558
- let opcode = 0xa74; // BCR
2559
- put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 2));
2560
- let opcode = 0x38; // LER
2561
- put(sink, &enc_rr(opcode, rd.to_reg(), rm));
2562
- } else {
2563
- let opcode = 0xa74; // BCR
2564
- put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 6));
2565
- let opcode = 0xe756; // VLR
2566
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rm, 0, 0, 0));
2567
- }
2568
- }
2569
- &Inst::FpuCMov64 { rd, cond, ri, rm } => {
2570
- let rd = allocs.next_writable(rd);
2571
- let ri = allocs.next(ri);
2572
- debug_assert_eq!(rd.to_reg(), ri);
2573
- let rm = allocs.next(rm);
2574
-
2575
- if is_fpr(rd.to_reg()) && is_fpr(rm) {
2576
- let opcode = 0xa74; // BCR
2577
- put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 2));
2578
- let opcode = 0x28; // LDR
2579
- put(sink, &enc_rr(opcode, rd.to_reg(), rm));
2580
- } else {
2581
- let opcode = 0xa74; // BCR
2582
- put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 6));
2583
- let opcode = 0xe756; // VLR
2584
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rm, 0, 0, 0));
2585
- }
2586
- }
2587
- &Inst::LoadFpuConst32 { rd, const_data } => {
2588
- let rd = allocs.next_writable(rd);
2589
-
2590
- let opcode = 0xa75; // BRAS
2591
- let reg = writable_spilltmp_reg().to_reg();
2592
- put(sink, &enc_ri_b(opcode, reg, 8));
2593
- sink.put4(const_data.swap_bytes());
2594
- let inst = Inst::VecLoadLaneUndef {
2595
- size: 32,
2596
- rd,
2597
- mem: MemArg::reg(reg, MemFlags::trusted()),
2598
- lane_imm: 0,
2599
- };
2600
- inst.emit(&[], sink, emit_info, state);
2601
- }
2602
- &Inst::LoadFpuConst64 { rd, const_data } => {
2603
- let rd = allocs.next_writable(rd);
2604
-
2605
- let opcode = 0xa75; // BRAS
2606
- let reg = writable_spilltmp_reg().to_reg();
2607
- put(sink, &enc_ri_b(opcode, reg, 12));
2608
- sink.put8(const_data.swap_bytes());
2609
- let inst = Inst::VecLoadLaneUndef {
2610
- size: 64,
2611
- rd,
2612
- mem: MemArg::reg(reg, MemFlags::trusted()),
2613
- lane_imm: 0,
2614
- };
2615
- inst.emit(&[], sink, emit_info, state);
2616
- }
2617
- &Inst::FpuRR { fpu_op, rd, rn } => {
2618
- let rd = allocs.next_writable(rd);
2619
- let rn = allocs.next(rn);
2620
-
2621
- let (opcode, m3, m4, m5, opcode_fpr) = match fpu_op {
2622
- FPUOp1::Abs32 => (0xe7cc, 2, 8, 2, Some(0xb300)), // WFPSO, LPEBR
2623
- FPUOp1::Abs64 => (0xe7cc, 3, 8, 2, Some(0xb310)), // WFPSO, LPDBR
2624
- FPUOp1::Abs32x4 => (0xe7cc, 2, 0, 2, None), // VFPSO
2625
- FPUOp1::Abs64x2 => (0xe7cc, 3, 0, 2, None), // VFPSO
2626
- FPUOp1::Neg32 => (0xe7cc, 2, 8, 0, Some(0xb303)), // WFPSO, LCEBR
2627
- FPUOp1::Neg64 => (0xe7cc, 3, 8, 0, Some(0xb313)), // WFPSO, LCDBR
2628
- FPUOp1::Neg32x4 => (0xe7cc, 2, 0, 0, None), // VFPSO
2629
- FPUOp1::Neg64x2 => (0xe7cc, 3, 0, 0, None), // VFPSO
2630
- FPUOp1::NegAbs32 => (0xe7cc, 2, 8, 1, Some(0xb301)), // WFPSO, LNEBR
2631
- FPUOp1::NegAbs64 => (0xe7cc, 3, 8, 1, Some(0xb311)), // WFPSO, LNDBR
2632
- FPUOp1::NegAbs32x4 => (0xe7cc, 2, 0, 1, None), // VFPSO
2633
- FPUOp1::NegAbs64x2 => (0xe7cc, 3, 0, 1, None), // VFPSO
2634
- FPUOp1::Sqrt32 => (0xe7ce, 2, 8, 0, Some(0xb314)), // WFSQ, SQEBR
2635
- FPUOp1::Sqrt64 => (0xe7ce, 3, 8, 0, Some(0xb315)), // WFSQ, SQDBR
2636
- FPUOp1::Sqrt32x4 => (0xe7ce, 2, 0, 0, None), // VFSQ
2637
- FPUOp1::Sqrt64x2 => (0xe7ce, 3, 0, 0, None), // VFSQ
2638
- FPUOp1::Cvt32To64 => (0xe7c4, 2, 8, 0, Some(0xb304)), // WFLL, LDEBR
2639
- FPUOp1::Cvt32x4To64x2 => (0xe7c4, 2, 0, 0, None), // VFLL
2640
- };
2641
- if m4 == 8 && is_fpr(rd.to_reg()) && is_fpr(rn) {
2642
- put(sink, &enc_rre(opcode_fpr.unwrap(), rd.to_reg(), rn));
2643
- } else {
2644
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, m3, m4, m5));
2645
- }
2646
- }
2647
- &Inst::FpuRRR { fpu_op, rd, rn, rm } => {
2648
- let rd = allocs.next_writable(rd);
2649
- let rn = allocs.next(rn);
2650
- let rm = allocs.next(rm);
2651
-
2652
- let (opcode, m4, m5, m6, opcode_fpr) = match fpu_op {
2653
- FPUOp2::Add32 => (0xe7e3, 2, 8, 0, Some(0xb30a)), // WFA, AEBR
2654
- FPUOp2::Add64 => (0xe7e3, 3, 8, 0, Some(0xb31a)), // WFA, ADBR
2655
- FPUOp2::Add32x4 => (0xe7e3, 2, 0, 0, None), // VFA
2656
- FPUOp2::Add64x2 => (0xe7e3, 3, 0, 0, None), // VFA
2657
- FPUOp2::Sub32 => (0xe7e2, 2, 8, 0, Some(0xb30b)), // WFS, SEBR
2658
- FPUOp2::Sub64 => (0xe7e2, 3, 8, 0, Some(0xb31b)), // WFS, SDBR
2659
- FPUOp2::Sub32x4 => (0xe7e2, 2, 0, 0, None), // VFS
2660
- FPUOp2::Sub64x2 => (0xe7e2, 3, 0, 0, None), // VFS
2661
- FPUOp2::Mul32 => (0xe7e7, 2, 8, 0, Some(0xb317)), // WFM, MEEBR
2662
- FPUOp2::Mul64 => (0xe7e7, 3, 8, 0, Some(0xb31c)), // WFM, MDBR
2663
- FPUOp2::Mul32x4 => (0xe7e7, 2, 0, 0, None), // VFM
2664
- FPUOp2::Mul64x2 => (0xe7e7, 3, 0, 0, None), // VFM
2665
- FPUOp2::Div32 => (0xe7e5, 2, 8, 0, Some(0xb30d)), // WFD, DEBR
2666
- FPUOp2::Div64 => (0xe7e5, 3, 8, 0, Some(0xb31d)), // WFD, DDBR
2667
- FPUOp2::Div32x4 => (0xe7e5, 2, 0, 0, None), // VFD
2668
- FPUOp2::Div64x2 => (0xe7e5, 3, 0, 0, None), // VFD
2669
- FPUOp2::Max32 => (0xe7ef, 2, 8, 1, None), // WFMAX
2670
- FPUOp2::Max64 => (0xe7ef, 3, 8, 1, None), // WFMAX
2671
- FPUOp2::Max32x4 => (0xe7ef, 2, 0, 1, None), // VFMAX
2672
- FPUOp2::Max64x2 => (0xe7ef, 3, 0, 1, None), // VFMAX
2673
- FPUOp2::Min32 => (0xe7ee, 2, 8, 1, None), // WFMIN
2674
- FPUOp2::Min64 => (0xe7ee, 3, 8, 1, None), // WFMIN
2675
- FPUOp2::Min32x4 => (0xe7ee, 2, 0, 1, None), // VFMIN
2676
- FPUOp2::Min64x2 => (0xe7ee, 3, 0, 1, None), // VFMIN
2677
- FPUOp2::MaxPseudo32 => (0xe7ef, 2, 8, 3, None), // WFMAX
2678
- FPUOp2::MaxPseudo64 => (0xe7ef, 3, 8, 3, None), // WFMAX
2679
- FPUOp2::MaxPseudo32x4 => (0xe7ef, 2, 0, 3, None), // VFMAX
2680
- FPUOp2::MaxPseudo64x2 => (0xe7ef, 3, 0, 3, None), // VFMAX
2681
- FPUOp2::MinPseudo32 => (0xe7ee, 2, 8, 3, None), // WFMIN
2682
- FPUOp2::MinPseudo64 => (0xe7ee, 3, 8, 3, None), // WFMIN
2683
- FPUOp2::MinPseudo32x4 => (0xe7ee, 2, 0, 3, None), // VFMIN
2684
- FPUOp2::MinPseudo64x2 => (0xe7ee, 3, 0, 3, None), // VFMIN
2685
- };
2686
- if m5 == 8 && opcode_fpr.is_some() && rd.to_reg() == rn && is_fpr(rn) && is_fpr(rm)
2687
- {
2688
- put(sink, &enc_rre(opcode_fpr.unwrap(), rd.to_reg(), rm));
2689
- } else {
2690
- put(sink, &enc_vrr_c(opcode, rd.to_reg(), rn, rm, m4, m5, m6));
2691
- }
2692
- }
2693
- &Inst::FpuRRRR {
2694
- fpu_op,
2695
- rd,
2696
- rn,
2697
- rm,
2698
- ra,
2699
- } => {
2700
- let rd = allocs.next_writable(rd);
2701
- let rn = allocs.next(rn);
2702
- let rm = allocs.next(rm);
2703
- let ra = allocs.next(ra);
2704
-
2705
- let (opcode, m5, m6, opcode_fpr) = match fpu_op {
2706
- FPUOp3::MAdd32 => (0xe78f, 8, 2, Some(0xb30e)), // WFMA, MAEBR
2707
- FPUOp3::MAdd64 => (0xe78f, 8, 3, Some(0xb31e)), // WFMA, MADBR
2708
- FPUOp3::MAdd32x4 => (0xe78f, 0, 2, None), // VFMA
2709
- FPUOp3::MAdd64x2 => (0xe78f, 0, 3, None), // VFMA
2710
- FPUOp3::MSub32 => (0xe78e, 8, 2, Some(0xb30f)), // WFMS, MSEBR
2711
- FPUOp3::MSub64 => (0xe78e, 8, 3, Some(0xb31f)), // WFMS, MSDBR
2712
- FPUOp3::MSub32x4 => (0xe78e, 0, 2, None), // VFMS
2713
- FPUOp3::MSub64x2 => (0xe78e, 0, 3, None), // VFMS
2714
- };
2715
- if m5 == 8 && rd.to_reg() == ra && is_fpr(rn) && is_fpr(rm) && is_fpr(ra) {
2716
- put(sink, &enc_rrd(opcode_fpr.unwrap(), rd.to_reg(), rm, rn));
2717
- } else {
2718
- put(sink, &enc_vrr_e(opcode, rd.to_reg(), rn, rm, ra, m5, m6));
2719
- }
2720
- }
2721
- &Inst::FpuRound { op, mode, rd, rn } => {
2722
- let rd = allocs.next_writable(rd);
2723
- let rn = allocs.next(rn);
2724
-
2725
- let mode = match mode {
2726
- FpuRoundMode::Current => 0,
2727
- FpuRoundMode::ToNearest => 1,
2728
- FpuRoundMode::ShorterPrecision => 3,
2729
- FpuRoundMode::ToNearestTiesToEven => 4,
2730
- FpuRoundMode::ToZero => 5,
2731
- FpuRoundMode::ToPosInfinity => 6,
2732
- FpuRoundMode::ToNegInfinity => 7,
2733
- };
2734
- let (opcode, m3, m4, opcode_fpr) = match op {
2735
- FpuRoundOp::Cvt64To32 => (0xe7c5, 3, 8, Some(0xb344)), // WFLR, LEDBR(A)
2736
- FpuRoundOp::Cvt64x2To32x4 => (0xe7c5, 3, 0, None), // VFLR
2737
- FpuRoundOp::Round32 => (0xe7c7, 2, 8, Some(0xb357)), // WFI, FIEBR
2738
- FpuRoundOp::Round64 => (0xe7c7, 3, 8, Some(0xb35f)), // WFI, FIDBR
2739
- FpuRoundOp::Round32x4 => (0xe7c7, 2, 0, None), // VFI
2740
- FpuRoundOp::Round64x2 => (0xe7c7, 3, 0, None), // VFI
2741
- FpuRoundOp::ToSInt32 => (0xe7c2, 2, 8, None), // WCSFP
2742
- FpuRoundOp::ToSInt64 => (0xe7c2, 3, 8, None), // WCSFP
2743
- FpuRoundOp::ToUInt32 => (0xe7c0, 2, 8, None), // WCLFP
2744
- FpuRoundOp::ToUInt64 => (0xe7c0, 3, 8, None), // WCLFP
2745
- FpuRoundOp::ToSInt32x4 => (0xe7c2, 2, 0, None), // VCSFP
2746
- FpuRoundOp::ToSInt64x2 => (0xe7c2, 3, 0, None), // VCSFP
2747
- FpuRoundOp::ToUInt32x4 => (0xe7c0, 2, 0, None), // VCLFP
2748
- FpuRoundOp::ToUInt64x2 => (0xe7c0, 3, 0, None), // VCLFP
2749
- FpuRoundOp::FromSInt32 => (0xe7c3, 2, 8, None), // WCFPS
2750
- FpuRoundOp::FromSInt64 => (0xe7c3, 3, 8, None), // WCFPS
2751
- FpuRoundOp::FromUInt32 => (0xe7c1, 2, 8, None), // WCFPL
2752
- FpuRoundOp::FromUInt64 => (0xe7c1, 3, 8, None), // WCFPL
2753
- FpuRoundOp::FromSInt32x4 => (0xe7c3, 2, 0, None), // VCFPS
2754
- FpuRoundOp::FromSInt64x2 => (0xe7c3, 3, 0, None), // VCFPS
2755
- FpuRoundOp::FromUInt32x4 => (0xe7c1, 2, 0, None), // VCFPL
2756
- FpuRoundOp::FromUInt64x2 => (0xe7c1, 3, 0, None), // VCFPL
2757
- };
2758
- if m4 == 8 && opcode_fpr.is_some() && is_fpr(rd.to_reg()) && is_fpr(rn) {
2759
- put(
2760
- sink,
2761
- &enc_rrf_cde(opcode_fpr.unwrap(), rd.to_reg(), rn, mode, 0),
2762
- );
2763
- } else {
2764
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, m3, m4, mode));
2765
- }
2766
- }
2767
- &Inst::FpuCmp32 { rn, rm } => {
2768
- let rn = allocs.next(rn);
2769
- let rm = allocs.next(rm);
2770
-
2771
- if is_fpr(rn) && is_fpr(rm) {
2772
- let opcode = 0xb309; // CEBR
2773
- put(sink, &enc_rre(opcode, rn, rm));
2774
- } else {
2775
- let opcode = 0xe7cb; // WFC
2776
- put(sink, &enc_vrr_a(opcode, rn, rm, 2, 0, 0));
2777
- }
2778
- }
2779
- &Inst::FpuCmp64 { rn, rm } => {
2780
- let rn = allocs.next(rn);
2781
- let rm = allocs.next(rm);
2782
-
2783
- if is_fpr(rn) && is_fpr(rm) {
2784
- let opcode = 0xb319; // CDBR
2785
- put(sink, &enc_rre(opcode, rn, rm));
2786
- } else {
2787
- let opcode = 0xe7cb; // WFC
2788
- put(sink, &enc_vrr_a(opcode, rn, rm, 3, 0, 0));
2789
- }
2790
- }
2791
-
2792
- &Inst::VecRRR { op, rd, rn, rm } => {
2793
- let rd = allocs.next_writable(rd);
2794
- let rn = allocs.next(rn);
2795
- let rm = allocs.next(rm);
2796
-
2797
- let (opcode, m4) = match op {
2798
- VecBinaryOp::Add8x16 => (0xe7f3, 0), // VAB
2799
- VecBinaryOp::Add16x8 => (0xe7f3, 1), // VAH
2800
- VecBinaryOp::Add32x4 => (0xe7f3, 2), // VAF
2801
- VecBinaryOp::Add64x2 => (0xe7f3, 3), // VAG
2802
- VecBinaryOp::Add128 => (0xe7f3, 4), // VAQ
2803
- VecBinaryOp::Sub8x16 => (0xe7f7, 0), // VSB
2804
- VecBinaryOp::Sub16x8 => (0xe7f7, 1), // VSH
2805
- VecBinaryOp::Sub32x4 => (0xe7f7, 2), // VSF
2806
- VecBinaryOp::Sub64x2 => (0xe7f7, 3), // VSG
2807
- VecBinaryOp::Sub128 => (0xe7f7, 4), // VSQ
2808
- VecBinaryOp::Mul8x16 => (0xe7a2, 0), // VMLB
2809
- VecBinaryOp::Mul16x8 => (0xe7a2, 1), // VMLHW
2810
- VecBinaryOp::Mul32x4 => (0xe7a2, 2), // VMLF
2811
- VecBinaryOp::UMulHi8x16 => (0xe7a1, 0), // VMLHB
2812
- VecBinaryOp::UMulHi16x8 => (0xe7a1, 1), // VMLHH
2813
- VecBinaryOp::UMulHi32x4 => (0xe7a1, 2), // VMLHF
2814
- VecBinaryOp::SMulHi8x16 => (0xe7a3, 0), // VMHB
2815
- VecBinaryOp::SMulHi16x8 => (0xe7a3, 1), // VMHH
2816
- VecBinaryOp::SMulHi32x4 => (0xe7a3, 2), // VMHF
2817
- VecBinaryOp::UMulEven8x16 => (0xe7a4, 0), // VMLEB
2818
- VecBinaryOp::UMulEven16x8 => (0xe7a4, 1), // VMLEH
2819
- VecBinaryOp::UMulEven32x4 => (0xe7a4, 2), // VMLEF
2820
- VecBinaryOp::SMulEven8x16 => (0xe7a6, 0), // VMEB
2821
- VecBinaryOp::SMulEven16x8 => (0xe7a6, 1), // VMEH
2822
- VecBinaryOp::SMulEven32x4 => (0xe7a6, 2), // VMEF
2823
- VecBinaryOp::UMulOdd8x16 => (0xe7a5, 0), // VMLOB
2824
- VecBinaryOp::UMulOdd16x8 => (0xe7a5, 1), // VMLOH
2825
- VecBinaryOp::UMulOdd32x4 => (0xe7a5, 2), // VMLOF
2826
- VecBinaryOp::SMulOdd8x16 => (0xe7a7, 0), // VMOB
2827
- VecBinaryOp::SMulOdd16x8 => (0xe7a7, 1), // VMOH
2828
- VecBinaryOp::SMulOdd32x4 => (0xe7a7, 2), // VMOF
2829
- VecBinaryOp::UMax8x16 => (0xe7fd, 0), // VMXLB
2830
- VecBinaryOp::UMax16x8 => (0xe7fd, 1), // VMXLH
2831
- VecBinaryOp::UMax32x4 => (0xe7fd, 2), // VMXLF
2832
- VecBinaryOp::UMax64x2 => (0xe7fd, 3), // VMXLG
2833
- VecBinaryOp::SMax8x16 => (0xe7ff, 0), // VMXB
2834
- VecBinaryOp::SMax16x8 => (0xe7ff, 1), // VMXH
2835
- VecBinaryOp::SMax32x4 => (0xe7ff, 2), // VMXF
2836
- VecBinaryOp::SMax64x2 => (0xe7ff, 3), // VMXG
2837
- VecBinaryOp::UMin8x16 => (0xe7fc, 0), // VMNLB
2838
- VecBinaryOp::UMin16x8 => (0xe7fc, 1), // VMNLH
2839
- VecBinaryOp::UMin32x4 => (0xe7fc, 2), // VMNLF
2840
- VecBinaryOp::UMin64x2 => (0xe7fc, 3), // VMNLG
2841
- VecBinaryOp::SMin8x16 => (0xe7fe, 0), // VMNB
2842
- VecBinaryOp::SMin16x8 => (0xe7fe, 1), // VMNH
2843
- VecBinaryOp::SMin32x4 => (0xe7fe, 2), // VMNF
2844
- VecBinaryOp::SMin64x2 => (0xe7fe, 3), // VMNG
2845
- VecBinaryOp::UAvg8x16 => (0xe7f0, 0), // VAVGLB
2846
- VecBinaryOp::UAvg16x8 => (0xe7f0, 1), // VAVGLH
2847
- VecBinaryOp::UAvg32x4 => (0xe7f0, 2), // VAVGLF
2848
- VecBinaryOp::UAvg64x2 => (0xe7f0, 3), // VAVGLG
2849
- VecBinaryOp::SAvg8x16 => (0xe7f2, 0), // VAVGB
2850
- VecBinaryOp::SAvg16x8 => (0xe7f2, 1), // VAVGH
2851
- VecBinaryOp::SAvg32x4 => (0xe7f2, 2), // VAVGF
2852
- VecBinaryOp::SAvg64x2 => (0xe7f2, 3), // VAVGG
2853
- VecBinaryOp::And128 => (0xe768, 0), // VN
2854
- VecBinaryOp::Orr128 => (0xe76a, 0), // VO
2855
- VecBinaryOp::Xor128 => (0xe76d, 0), // VX
2856
- VecBinaryOp::NotAnd128 => (0xe76e, 0), // VNN
2857
- VecBinaryOp::NotOrr128 => (0xe76b, 0), // VNO
2858
- VecBinaryOp::NotXor128 => (0xe76c, 0), // VNX
2859
- VecBinaryOp::AndNot128 => (0xe769, 0), // VNC
2860
- VecBinaryOp::OrrNot128 => (0xe76f, 0), // VOC
2861
- VecBinaryOp::BitPermute128 => (0xe785, 0), // VBPERM
2862
- VecBinaryOp::LShLByByte128 => (0xe775, 0), // VSLB
2863
- VecBinaryOp::LShRByByte128 => (0xe77d, 0), // VSRLB
2864
- VecBinaryOp::AShRByByte128 => (0xe77f, 0), // VSRAB
2865
- VecBinaryOp::LShLByBit128 => (0xe774, 0), // VSL
2866
- VecBinaryOp::LShRByBit128 => (0xe77c, 0), // VSRL
2867
- VecBinaryOp::AShRByBit128 => (0xe77e, 0), // VSRA
2868
- VecBinaryOp::Pack16x8 => (0xe794, 1), // VPKH
2869
- VecBinaryOp::Pack32x4 => (0xe794, 2), // VPKF
2870
- VecBinaryOp::Pack64x2 => (0xe794, 3), // VPKG
2871
- VecBinaryOp::PackUSat16x8 => (0xe795, 1), // VPKLSH
2872
- VecBinaryOp::PackUSat32x4 => (0xe795, 2), // VPKLSF
2873
- VecBinaryOp::PackUSat64x2 => (0xe795, 3), // VPKLSG
2874
- VecBinaryOp::PackSSat16x8 => (0xe797, 1), // VPKSH
2875
- VecBinaryOp::PackSSat32x4 => (0xe797, 2), // VPKSF
2876
- VecBinaryOp::PackSSat64x2 => (0xe797, 3), // VPKSG
2877
- VecBinaryOp::MergeLow8x16 => (0xe760, 0), // VMRLB
2878
- VecBinaryOp::MergeLow16x8 => (0xe760, 1), // VMRLH
2879
- VecBinaryOp::MergeLow32x4 => (0xe760, 2), // VMRLF
2880
- VecBinaryOp::MergeLow64x2 => (0xe760, 3), // VMRLG
2881
- VecBinaryOp::MergeHigh8x16 => (0xe761, 0), // VMRHB
2882
- VecBinaryOp::MergeHigh16x8 => (0xe761, 1), // VMRHH
2883
- VecBinaryOp::MergeHigh32x4 => (0xe761, 2), // VMRHF
2884
- VecBinaryOp::MergeHigh64x2 => (0xe761, 3), // VMRHG
2885
- };
2886
-
2887
- put(sink, &enc_vrr_c(opcode, rd.to_reg(), rn, rm, m4, 0, 0));
2888
- }
2889
- &Inst::VecRR { op, rd, rn } => {
2890
- let rd = allocs.next_writable(rd);
2891
- let rn = allocs.next(rn);
2892
-
2893
- let (opcode, m3) = match op {
2894
- VecUnaryOp::Abs8x16 => (0xe7df, 0), // VLPB
2895
- VecUnaryOp::Abs16x8 => (0xe7df, 1), // VLPH
2896
- VecUnaryOp::Abs32x4 => (0xe7df, 2), // VLPF
2897
- VecUnaryOp::Abs64x2 => (0xe7df, 3), // VLPG
2898
- VecUnaryOp::Neg8x16 => (0xe7de, 0), // VLCB
2899
- VecUnaryOp::Neg16x8 => (0xe7de, 1), // VLCH
2900
- VecUnaryOp::Neg32x4 => (0xe7de, 2), // VLCF
2901
- VecUnaryOp::Neg64x2 => (0xe7de, 3), // VLCG
2902
- VecUnaryOp::Popcnt8x16 => (0xe750, 0), // VPOPCTB
2903
- VecUnaryOp::Popcnt16x8 => (0xe750, 1), // VPOPCTH
2904
- VecUnaryOp::Popcnt32x4 => (0xe750, 2), // VPOPCTF
2905
- VecUnaryOp::Popcnt64x2 => (0xe750, 3), // VPOPCTG
2906
- VecUnaryOp::Clz8x16 => (0xe753, 0), // VCLZB
2907
- VecUnaryOp::Clz16x8 => (0xe753, 1), // VCLZH
2908
- VecUnaryOp::Clz32x4 => (0xe753, 2), // VCLZF
2909
- VecUnaryOp::Clz64x2 => (0xe753, 3), // VCLZG
2910
- VecUnaryOp::Ctz8x16 => (0xe752, 0), // VCTZB
2911
- VecUnaryOp::Ctz16x8 => (0xe752, 1), // VCTZH
2912
- VecUnaryOp::Ctz32x4 => (0xe752, 2), // VCTZF
2913
- VecUnaryOp::Ctz64x2 => (0xe752, 3), // VCTZG
2914
- VecUnaryOp::UnpackULow8x16 => (0xe7d4, 0), // VUPLLB
2915
- VecUnaryOp::UnpackULow16x8 => (0xe7d4, 1), // VUPLLH
2916
- VecUnaryOp::UnpackULow32x4 => (0xe7d4, 2), // VUPLLF
2917
- VecUnaryOp::UnpackUHigh8x16 => (0xe7d5, 0), // VUPLHB
2918
- VecUnaryOp::UnpackUHigh16x8 => (0xe7d5, 1), // VUPLHH
2919
- VecUnaryOp::UnpackUHigh32x4 => (0xe7d5, 2), // VUPLHF
2920
- VecUnaryOp::UnpackSLow8x16 => (0xe7d6, 0), // VUPLB
2921
- VecUnaryOp::UnpackSLow16x8 => (0xe7d6, 1), // VUPLH
2922
- VecUnaryOp::UnpackSLow32x4 => (0xe7d6, 2), // VUPLF
2923
- VecUnaryOp::UnpackSHigh8x16 => (0xe7d7, 0), // VUPHB
2924
- VecUnaryOp::UnpackSHigh16x8 => (0xe7d7, 1), // VUPHH
2925
- VecUnaryOp::UnpackSHigh32x4 => (0xe7d7, 2), // VUPHF
2926
- };
2927
-
2928
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, m3, 0, 0));
2929
- }
2930
- &Inst::VecShiftRR {
2931
- shift_op,
2932
- rd,
2933
- rn,
2934
- shift_imm,
2935
- shift_reg,
2936
- } => {
2937
- let rd = allocs.next_writable(rd);
2938
- let rn = allocs.next(rn);
2939
- let shift_reg = allocs.next(shift_reg);
2940
-
2941
- let (opcode, m4) = match shift_op {
2942
- VecShiftOp::RotL8x16 => (0xe733, 0), // VERLLB
2943
- VecShiftOp::RotL16x8 => (0xe733, 1), // VERLLH
2944
- VecShiftOp::RotL32x4 => (0xe733, 2), // VERLLF
2945
- VecShiftOp::RotL64x2 => (0xe733, 3), // VERLLG
2946
- VecShiftOp::LShL8x16 => (0xe730, 0), // VESLB
2947
- VecShiftOp::LShL16x8 => (0xe730, 1), // VESLH
2948
- VecShiftOp::LShL32x4 => (0xe730, 2), // VESLF
2949
- VecShiftOp::LShL64x2 => (0xe730, 3), // VESLG
2950
- VecShiftOp::LShR8x16 => (0xe738, 0), // VESRLB
2951
- VecShiftOp::LShR16x8 => (0xe738, 1), // VESRLH
2952
- VecShiftOp::LShR32x4 => (0xe738, 2), // VESRLF
2953
- VecShiftOp::LShR64x2 => (0xe738, 3), // VESRLG
2954
- VecShiftOp::AShR8x16 => (0xe73a, 0), // VESRAB
2955
- VecShiftOp::AShR16x8 => (0xe73a, 1), // VESRAH
2956
- VecShiftOp::AShR32x4 => (0xe73a, 2), // VESRAF
2957
- VecShiftOp::AShR64x2 => (0xe73a, 3), // VESRAG
2958
- };
2959
- put(
2960
- sink,
2961
- &enc_vrs_a(opcode, rd.to_reg(), shift_reg, shift_imm.into(), rn, m4),
2962
- );
2963
- }
2964
- &Inst::VecSelect { rd, rn, rm, ra } => {
2965
- let rd = allocs.next_writable(rd);
2966
- let rn = allocs.next(rn);
2967
- let rm = allocs.next(rm);
2968
- let ra = allocs.next(ra);
2969
-
2970
- let opcode = 0xe78d; // VSEL
2971
- put(sink, &enc_vrr_e(opcode, rd.to_reg(), rn, rm, ra, 0, 0));
2972
- }
2973
- &Inst::VecPermute { rd, rn, rm, ra } => {
2974
- let rd = allocs.next_writable(rd);
2975
- let rn = allocs.next(rn);
2976
- let rm = allocs.next(rm);
2977
- let ra = allocs.next(ra);
2978
-
2979
- let opcode = 0xe78c; // VPERM
2980
- put(sink, &enc_vrr_e(opcode, rd.to_reg(), rn, rm, ra, 0, 0));
2981
- }
2982
- &Inst::VecPermuteDWImm {
2983
- rd,
2984
- rn,
2985
- rm,
2986
- idx1,
2987
- idx2,
2988
- } => {
2989
- let rd = allocs.next_writable(rd);
2990
- let rn = allocs.next(rn);
2991
- let rm = allocs.next(rm);
2992
- let m4 = (idx1 & 1) * 4 + (idx2 & 1);
2993
-
2994
- let opcode = 0xe784; // VPDI
2995
- put(sink, &enc_vrr_c(opcode, rd.to_reg(), rn, rm, m4, 0, 0));
2996
- }
2997
- &Inst::VecIntCmp { op, rd, rn, rm } | &Inst::VecIntCmpS { op, rd, rn, rm } => {
2998
- let rd = allocs.next_writable(rd);
2999
- let rn = allocs.next(rn);
3000
- let rm = allocs.next(rm);
3001
-
3002
- let (opcode, m4) = match op {
3003
- VecIntCmpOp::CmpEq8x16 => (0xe7f8, 0), // VCEQB
3004
- VecIntCmpOp::CmpEq16x8 => (0xe7f8, 1), // VCEQH
3005
- VecIntCmpOp::CmpEq32x4 => (0xe7f8, 2), // VCEQF
3006
- VecIntCmpOp::CmpEq64x2 => (0xe7f8, 3), // VCEQG
3007
- VecIntCmpOp::SCmpHi8x16 => (0xe7fb, 0), // VCHB
3008
- VecIntCmpOp::SCmpHi16x8 => (0xe7fb, 1), // VCHH
3009
- VecIntCmpOp::SCmpHi32x4 => (0xe7fb, 2), // VCHG
3010
- VecIntCmpOp::SCmpHi64x2 => (0xe7fb, 3), // VCHG
3011
- VecIntCmpOp::UCmpHi8x16 => (0xe7f9, 0), // VCHLB
3012
- VecIntCmpOp::UCmpHi16x8 => (0xe7f9, 1), // VCHLH
3013
- VecIntCmpOp::UCmpHi32x4 => (0xe7f9, 2), // VCHLG
3014
- VecIntCmpOp::UCmpHi64x2 => (0xe7f9, 3), // VCHLG
3015
- };
3016
- let m5 = match self {
3017
- &Inst::VecIntCmp { .. } => 0,
3018
- &Inst::VecIntCmpS { .. } => 1,
3019
- _ => unreachable!(),
3020
- };
3021
-
3022
- put(sink, &enc_vrr_b(opcode, rd.to_reg(), rn, rm, m4, m5));
3023
- }
3024
- &Inst::VecFloatCmp { op, rd, rn, rm } | &Inst::VecFloatCmpS { op, rd, rn, rm } => {
3025
- let rd = allocs.next_writable(rd);
3026
- let rn = allocs.next(rn);
3027
- let rm = allocs.next(rm);
3028
-
3029
- let (opcode, m4) = match op {
3030
- VecFloatCmpOp::CmpEq32x4 => (0xe7e8, 2), // VFCESB
3031
- VecFloatCmpOp::CmpEq64x2 => (0xe7e8, 3), // VFCEDB
3032
- VecFloatCmpOp::CmpHi32x4 => (0xe7eb, 2), // VFCHSB
3033
- VecFloatCmpOp::CmpHi64x2 => (0xe7eb, 3), // VFCHDB
3034
- VecFloatCmpOp::CmpHiEq32x4 => (0xe7ea, 2), // VFCHESB
3035
- VecFloatCmpOp::CmpHiEq64x2 => (0xe7ea, 3), // VFCHEDB
3036
- };
3037
- let m6 = match self {
3038
- &Inst::VecFloatCmp { .. } => 0,
3039
- &Inst::VecFloatCmpS { .. } => 1,
3040
- _ => unreachable!(),
3041
- };
3042
-
3043
- put(sink, &enc_vrr_c(opcode, rd.to_reg(), rn, rm, m4, 0, m6));
3044
- }
3045
- &Inst::VecInt128SCmpHi { tmp, rn, rm } | &Inst::VecInt128UCmpHi { tmp, rn, rm } => {
3046
- // Synthetic instruction to compare 128-bit values.
3047
- // Sets CC 1 if rn > rm, sets a different CC otherwise.
3048
- let tmp = allocs.next_writable(tmp);
3049
- let rn = allocs.next(rn);
3050
- let rm = allocs.next(rm);
3051
-
3052
- // Use VECTOR ELEMENT COMPARE to compare the high parts.
3053
- // Swap the inputs to get:
3054
- // CC 1 if high(rn) > high(rm)
3055
- // CC 2 if high(rn) < high(rm)
3056
- // CC 0 if high(rn) == high(rm)
3057
- let (opcode, m3) = match self {
3058
- &Inst::VecInt128SCmpHi { .. } => (0xe7db, 3), // VECG
3059
- &Inst::VecInt128UCmpHi { .. } => (0xe7d9, 3), // VECLG
3060
- _ => unreachable!(),
3061
- };
3062
- put(sink, &enc_vrr_a(opcode, rm, rn, m3, 0, 0));
3063
-
3064
- // If CC != 0, we'd done, so jump over the next instruction.
3065
- let opcode = 0xa74; // BCR
3066
- put(sink, &enc_ri_c(opcode, 7, 4 + 6));
3067
-
3068
- // Otherwise, use VECTOR COMPARE HIGH LOGICAL.
3069
- // Since we already know the high parts are equal, the CC
3070
- // result will only depend on the low parts:
3071
- // CC 1 if low(rn) > low(rm)
3072
- // CC 3 if low(rn) <= low(rm)
3073
- let inst = Inst::VecIntCmpS {
3074
- op: VecIntCmpOp::UCmpHi64x2,
3075
- // N.B.: This is the first write to tmp, and it happens
3076
- // after all uses of rn and rm. If this were to ever
3077
- // change, tmp would have to become an early-def.
3078
- rd: tmp,
3079
- rn,
3080
- rm,
3081
- };
3082
- inst.emit(&[], sink, emit_info, state);
3083
- }
3084
-
3085
- &Inst::VecLoad { rd, ref mem }
3086
- | &Inst::VecLoadRev { rd, ref mem }
3087
- | &Inst::VecLoadByte16Rev { rd, ref mem }
3088
- | &Inst::VecLoadByte32Rev { rd, ref mem }
3089
- | &Inst::VecLoadByte64Rev { rd, ref mem }
3090
- | &Inst::VecLoadElt16Rev { rd, ref mem }
3091
- | &Inst::VecLoadElt32Rev { rd, ref mem }
3092
- | &Inst::VecLoadElt64Rev { rd, ref mem } => {
3093
- let rd = allocs.next_writable(rd);
3094
- let mem = mem.with_allocs(allocs);
3095
-
3096
- let (opcode, m3) = match self {
3097
- &Inst::VecLoad { .. } => (0xe706, 0), // VL
3098
- &Inst::VecLoadRev { .. } => (0xe606, 4), // VLBRQ
3099
- &Inst::VecLoadByte16Rev { .. } => (0xe606, 1), // VLBRH
3100
- &Inst::VecLoadByte32Rev { .. } => (0xe606, 2), // VLBRF
3101
- &Inst::VecLoadByte64Rev { .. } => (0xe606, 3), // VLBRG
3102
- &Inst::VecLoadElt16Rev { .. } => (0xe607, 1), // VLERH
3103
- &Inst::VecLoadElt32Rev { .. } => (0xe607, 2), // VLERF
3104
- &Inst::VecLoadElt64Rev { .. } => (0xe607, 3), // VLERG
3105
- _ => unreachable!(),
3106
- };
3107
- mem_vrx_emit(rd.to_reg(), &mem, opcode, m3, true, sink, emit_info, state);
3108
- }
3109
- &Inst::VecStore { rd, ref mem }
3110
- | &Inst::VecStoreRev { rd, ref mem }
3111
- | &Inst::VecStoreByte16Rev { rd, ref mem }
3112
- | &Inst::VecStoreByte32Rev { rd, ref mem }
3113
- | &Inst::VecStoreByte64Rev { rd, ref mem }
3114
- | &Inst::VecStoreElt16Rev { rd, ref mem }
3115
- | &Inst::VecStoreElt32Rev { rd, ref mem }
3116
- | &Inst::VecStoreElt64Rev { rd, ref mem } => {
3117
- let rd = allocs.next(rd);
3118
- let mem = mem.with_allocs(allocs);
3119
-
3120
- let (opcode, m3) = match self {
3121
- &Inst::VecStore { .. } => (0xe70e, 0), // VST
3122
- &Inst::VecStoreRev { .. } => (0xe60e, 4), // VSTBRQ
3123
- &Inst::VecStoreByte16Rev { .. } => (0xe60e, 1), // VSTBRH
3124
- &Inst::VecStoreByte32Rev { .. } => (0xe60e, 2), // VSTBRF
3125
- &Inst::VecStoreByte64Rev { .. } => (0xe60e, 3), // VSTBRG
3126
- &Inst::VecStoreElt16Rev { .. } => (0xe60f, 1), // VSTERH
3127
- &Inst::VecStoreElt32Rev { .. } => (0xe60f, 2), // VSTERF
3128
- &Inst::VecStoreElt64Rev { .. } => (0xe60f, 3), // VSTERG
3129
- _ => unreachable!(),
3130
- };
3131
- mem_vrx_emit(rd, &mem, opcode, m3, true, sink, emit_info, state);
3132
- }
3133
- &Inst::VecLoadReplicate { size, rd, ref mem }
3134
- | &Inst::VecLoadReplicateRev { size, rd, ref mem } => {
3135
- let rd = allocs.next_writable(rd);
3136
- let mem = mem.with_allocs(allocs);
3137
-
3138
- let (opcode, m3) = match (self, size) {
3139
- (&Inst::VecLoadReplicate { .. }, 8) => (0xe705, 0), // VLREPB
3140
- (&Inst::VecLoadReplicate { .. }, 16) => (0xe705, 1), // VLREPH
3141
- (&Inst::VecLoadReplicate { .. }, 32) => (0xe705, 2), // VLREPF
3142
- (&Inst::VecLoadReplicate { .. }, 64) => (0xe705, 3), // VLREPG
3143
- (&Inst::VecLoadReplicateRev { .. }, 16) => (0xe605, 1), // VLREPBRH
3144
- (&Inst::VecLoadReplicateRev { .. }, 32) => (0xe605, 2), // VLREPBRF
3145
- (&Inst::VecLoadReplicateRev { .. }, 64) => (0xe605, 3), // VLREPBRG
3146
- _ => unreachable!(),
3147
- };
3148
- mem_vrx_emit(rd.to_reg(), &mem, opcode, m3, true, sink, emit_info, state);
3149
- }
3150
-
3151
- &Inst::VecMov { rd, rn } => {
3152
- let rd = allocs.next_writable(rd);
3153
- let rn = allocs.next(rn);
3154
-
3155
- let opcode = 0xe756; // VLR
3156
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, 0, 0, 0));
3157
- }
3158
- &Inst::VecCMov { rd, cond, ri, rm } => {
3159
- let rd = allocs.next_writable(rd);
3160
- let ri = allocs.next(ri);
3161
- debug_assert_eq!(rd.to_reg(), ri);
3162
- let rm = allocs.next(rm);
3163
-
3164
- let opcode = 0xa74; // BCR
3165
- put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 6));
3166
- let opcode = 0xe756; // VLR
3167
- put(sink, &enc_vrr_a(opcode, rd.to_reg(), rm, 0, 0, 0));
3168
- }
3169
- &Inst::MovToVec128 { rd, rn, rm } => {
3170
- let rd = allocs.next_writable(rd);
3171
- let rn = allocs.next(rn);
3172
- let rm = allocs.next(rm);
3173
-
3174
- let opcode = 0xe762; // VLVGP
3175
- put(sink, &enc_vrr_f(opcode, rd.to_reg(), rn, rm));
3176
- }
3177
- &Inst::VecLoadConst { rd, const_data } => {
3178
- let rd = allocs.next_writable(rd);
3179
-
3180
- let opcode = 0xa75; // BRAS
3181
- let reg = writable_spilltmp_reg().to_reg();
3182
- put(sink, &enc_ri_b(opcode, reg, 20));
3183
- for i in const_data.to_be_bytes().iter() {
3184
- sink.put1(*i);
3185
- }
3186
- let inst = Inst::VecLoad {
3187
- rd,
3188
- mem: MemArg::reg(reg, MemFlags::trusted()),
3189
- };
3190
- inst.emit(&[], sink, emit_info, state);
3191
- }
3192
- &Inst::VecLoadConstReplicate {
3193
- size,
3194
- rd,
3195
- const_data,
3196
- } => {
3197
- let rd = allocs.next_writable(rd);
3198
-
3199
- let opcode = 0xa75; // BRAS
3200
- let reg = writable_spilltmp_reg().to_reg();
3201
- put(sink, &enc_ri_b(opcode, reg, (4 + size / 8) as i32));
3202
- for i in 0..size / 8 {
3203
- sink.put1((const_data >> (size - 8 - 8 * i)) as u8);
3204
- }
3205
- let inst = Inst::VecLoadReplicate {
3206
- size,
3207
- rd,
3208
- mem: MemArg::reg(reg, MemFlags::trusted()),
3209
- };
3210
- inst.emit(&[], sink, emit_info, state);
3211
- }
3212
- &Inst::VecImmByteMask { rd, mask } => {
3213
- let rd = allocs.next_writable(rd);
3214
- let opcode = 0xe744; // VGBM
3215
- put(sink, &enc_vri_a(opcode, rd.to_reg(), mask, 0));
3216
- }
3217
- &Inst::VecImmBitMask {
3218
- size,
3219
- rd,
3220
- start_bit,
3221
- end_bit,
3222
- } => {
3223
- let rd = allocs.next_writable(rd);
3224
- let (opcode, m4) = match size {
3225
- 8 => (0xe746, 0), // VGMB
3226
- 16 => (0xe746, 1), // VGMH
3227
- 32 => (0xe746, 2), // VGMF
3228
- 64 => (0xe746, 3), // VGMG
3229
- _ => unreachable!(),
3230
- };
3231
- put(
3232
- sink,
3233
- &enc_vri_b(opcode, rd.to_reg(), start_bit, end_bit, m4),
3234
- );
3235
- }
3236
- &Inst::VecImmReplicate { size, rd, imm } => {
3237
- let rd = allocs.next_writable(rd);
3238
- let (opcode, m3) = match size {
3239
- 8 => (0xe745, 0), // VREPIB
3240
- 16 => (0xe745, 1), // VREPIH
3241
- 32 => (0xe745, 2), // VREPIF
3242
- 64 => (0xe745, 3), // VREPIG
3243
- _ => unreachable!(),
3244
- };
3245
- put(sink, &enc_vri_a(opcode, rd.to_reg(), imm as u16, m3));
3246
- }
3247
- &Inst::VecLoadLane {
3248
- size,
3249
- rd,
3250
- ri,
3251
- ref mem,
3252
- lane_imm,
3253
- }
3254
- | &Inst::VecLoadLaneRev {
3255
- size,
3256
- rd,
3257
- ri,
3258
- ref mem,
3259
- lane_imm,
3260
- } => {
3261
- let rd = allocs.next_writable(rd);
3262
- let ri = allocs.next(ri);
3263
- debug_assert_eq!(rd.to_reg(), ri);
3264
- let mem = mem.with_allocs(allocs);
3265
-
3266
- let opcode_vrx = match (self, size) {
3267
- (&Inst::VecLoadLane { .. }, 8) => 0xe700, // VLEB
3268
- (&Inst::VecLoadLane { .. }, 16) => 0xe701, // VLEH
3269
- (&Inst::VecLoadLane { .. }, 32) => 0xe703, // VLEF
3270
- (&Inst::VecLoadLane { .. }, 64) => 0xe702, // VLEG
3271
- (&Inst::VecLoadLaneRev { .. }, 16) => 0xe601, // VLEBRH
3272
- (&Inst::VecLoadLaneRev { .. }, 32) => 0xe603, // VLEBRF
3273
- (&Inst::VecLoadLaneRev { .. }, 64) => 0xe602, // VLEBRG
3274
- _ => unreachable!(),
3275
- };
3276
-
3277
- let rd = rd.to_reg();
3278
- mem_vrx_emit(
3279
- rd,
3280
- &mem,
3281
- opcode_vrx,
3282
- lane_imm.into(),
3283
- true,
3284
- sink,
3285
- emit_info,
3286
- state,
3287
- );
3288
- }
3289
- &Inst::VecLoadLaneUndef {
3290
- size,
3291
- rd,
3292
- ref mem,
3293
- lane_imm,
3294
- }
3295
- | &Inst::VecLoadLaneRevUndef {
3296
- size,
3297
- rd,
3298
- ref mem,
3299
- lane_imm,
3300
- } => {
3301
- let rd = allocs.next_writable(rd);
3302
- let mem = mem.with_allocs(allocs);
3303
-
3304
- let (opcode_vrx, opcode_rx, opcode_rxy) = match (self, size) {
3305
- (&Inst::VecLoadLaneUndef { .. }, 8) => (0xe700, None, None), // VLEB
3306
- (&Inst::VecLoadLaneUndef { .. }, 16) => (0xe701, None, None), // VLEH
3307
- (&Inst::VecLoadLaneUndef { .. }, 32) => (0xe703, Some(0x78), Some(0xed64)), // VLEF, LE(Y)
3308
- (&Inst::VecLoadLaneUndef { .. }, 64) => (0xe702, Some(0x68), Some(0xed65)), // VLEG, LD(Y)
3309
- (&Inst::VecLoadLaneRevUndef { .. }, 16) => (0xe601, None, None), // VLEBRH
3310
- (&Inst::VecLoadLaneRevUndef { .. }, 32) => (0xe603, None, None), // VLEBRF
3311
- (&Inst::VecLoadLaneRevUndef { .. }, 64) => (0xe602, None, None), // VLEBRG
3312
- _ => unreachable!(),
3313
- };
3314
-
3315
- let rd = rd.to_reg();
3316
- if lane_imm == 0 && is_fpr(rd) && opcode_rx.is_some() {
3317
- mem_emit(
3318
- rd, &mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state,
3319
- );
3320
- } else {
3321
- mem_vrx_emit(
3322
- rd,
3323
- &mem,
3324
- opcode_vrx,
3325
- lane_imm.into(),
3326
- true,
3327
- sink,
3328
- emit_info,
3329
- state,
3330
- );
3331
- }
3332
- }
3333
- &Inst::VecStoreLane {
3334
- size,
3335
- rd,
3336
- ref mem,
3337
- lane_imm,
3338
- }
3339
- | &Inst::VecStoreLaneRev {
3340
- size,
3341
- rd,
3342
- ref mem,
3343
- lane_imm,
3344
- } => {
3345
- let rd = allocs.next(rd);
3346
- let mem = mem.with_allocs(allocs);
3347
-
3348
- let (opcode_vrx, opcode_rx, opcode_rxy) = match (self, size) {
3349
- (&Inst::VecStoreLane { .. }, 8) => (0xe708, None, None), // VSTEB
3350
- (&Inst::VecStoreLane { .. }, 16) => (0xe709, None, None), // VSTEH
3351
- (&Inst::VecStoreLane { .. }, 32) => (0xe70b, Some(0x70), Some(0xed66)), // VSTEF, STE(Y)
3352
- (&Inst::VecStoreLane { .. }, 64) => (0xe70a, Some(0x60), Some(0xed67)), // VSTEG, STD(Y)
3353
- (&Inst::VecStoreLaneRev { .. }, 16) => (0xe609, None, None), // VSTEBRH
3354
- (&Inst::VecStoreLaneRev { .. }, 32) => (0xe60b, None, None), // VSTEBRF
3355
- (&Inst::VecStoreLaneRev { .. }, 64) => (0xe60a, None, None), // VSTEBRG
3356
- _ => unreachable!(),
3357
- };
3358
-
3359
- if lane_imm == 0 && is_fpr(rd) && opcode_rx.is_some() {
3360
- mem_emit(
3361
- rd, &mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state,
3362
- );
3363
- } else {
3364
- mem_vrx_emit(
3365
- rd,
3366
- &mem,
3367
- opcode_vrx,
3368
- lane_imm.into(),
3369
- true,
3370
- sink,
3371
- emit_info,
3372
- state,
3373
- );
3374
- }
3375
- }
3376
- &Inst::VecInsertLane {
3377
- size,
3378
- rd,
3379
- ri,
3380
- rn,
3381
- lane_imm,
3382
- lane_reg,
3383
- } => {
3384
- let rd = allocs.next_writable(rd);
3385
- let ri = allocs.next(ri);
3386
- debug_assert_eq!(rd.to_reg(), ri);
3387
- let rn = allocs.next(rn);
3388
- let lane_reg = allocs.next(lane_reg);
3389
-
3390
- let (opcode_vrs, m4) = match size {
3391
- 8 => (0xe722, 0), // VLVGB
3392
- 16 => (0xe722, 1), // VLVGH
3393
- 32 => (0xe722, 2), // VLVGF
3394
- 64 => (0xe722, 3), // VLVGG
3395
- _ => unreachable!(),
3396
- };
3397
- put(
3398
- sink,
3399
- &enc_vrs_b(opcode_vrs, rd.to_reg(), lane_reg, lane_imm.into(), rn, m4),
3400
- );
3401
- }
3402
- &Inst::VecInsertLaneUndef {
3403
- size,
3404
- rd,
3405
- rn,
3406
- lane_imm,
3407
- lane_reg,
3408
- } => {
3409
- let rd = allocs.next_writable(rd);
3410
- let rn = allocs.next(rn);
3411
- let lane_reg = allocs.next(lane_reg);
3412
-
3413
- let (opcode_vrs, m4, opcode_rre) = match size {
3414
- 8 => (0xe722, 0, None), // VLVGB
3415
- 16 => (0xe722, 1, None), // VLVGH
3416
- 32 => (0xe722, 2, None), // VLVGF
3417
- 64 => (0xe722, 3, Some(0xb3c1)), // VLVGG, LDGR
3418
- _ => unreachable!(),
3419
- };
3420
- if opcode_rre.is_some()
3421
- && lane_imm == 0
3422
- && lane_reg == zero_reg()
3423
- && is_fpr(rd.to_reg())
3424
- {
3425
- put(sink, &enc_rre(opcode_rre.unwrap(), rd.to_reg(), rn));
3426
- } else {
3427
- put(
3428
- sink,
3429
- &enc_vrs_b(opcode_vrs, rd.to_reg(), lane_reg, lane_imm.into(), rn, m4),
3430
- );
3431
- }
3432
- }
3433
- &Inst::VecExtractLane {
3434
- size,
3435
- rd,
3436
- rn,
3437
- lane_imm,
3438
- lane_reg,
3439
- } => {
3440
- let rd = allocs.next_writable(rd);
3441
- let rn = allocs.next(rn);
3442
- let lane_reg = allocs.next(lane_reg);
3443
-
3444
- let (opcode_vrs, m4, opcode_rre) = match size {
3445
- 8 => (0xe721, 0, None), // VLGVB
3446
- 16 => (0xe721, 1, None), // VLGVH
3447
- 32 => (0xe721, 2, None), // VLGVF
3448
- 64 => (0xe721, 3, Some(0xb3cd)), // VLGVG, LGDR
3449
- _ => unreachable!(),
3450
- };
3451
- if opcode_rre.is_some() && lane_imm == 0 && lane_reg == zero_reg() && is_fpr(rn) {
3452
- put(sink, &enc_rre(opcode_rre.unwrap(), rd.to_reg(), rn));
3453
- } else {
3454
- put(
3455
- sink,
3456
- &enc_vrs_c(opcode_vrs, rd.to_reg(), lane_reg, lane_imm.into(), rn, m4),
3457
- );
3458
- }
3459
- }
3460
- &Inst::VecInsertLaneImm {
3461
- size,
3462
- rd,
3463
- ri,
3464
- imm,
3465
- lane_imm,
3466
- } => {
3467
- let rd = allocs.next_writable(rd);
3468
- let ri = allocs.next(ri);
3469
- debug_assert_eq!(rd.to_reg(), ri);
3470
-
3471
- let opcode = match size {
3472
- 8 => 0xe740, // VLEIB
3473
- 16 => 0xe741, // LEIVH
3474
- 32 => 0xe743, // VLEIF
3475
- 64 => 0xe742, // VLEIG
3476
- _ => unreachable!(),
3477
- };
3478
- put(
3479
- sink,
3480
- &enc_vri_a(opcode, rd.to_reg(), imm as u16, lane_imm.into()),
3481
- );
3482
- }
3483
- &Inst::VecReplicateLane {
3484
- size,
3485
- rd,
3486
- rn,
3487
- lane_imm,
3488
- } => {
3489
- let rd = allocs.next_writable(rd);
3490
- let rn = allocs.next(rn);
3491
-
3492
- let (opcode, m4) = match size {
3493
- 8 => (0xe74d, 0), // VREPB
3494
- 16 => (0xe74d, 1), // VREPH
3495
- 32 => (0xe74d, 2), // VREPF
3496
- 64 => (0xe74d, 3), // VREPG
3497
- _ => unreachable!(),
3498
- };
3499
- put(
3500
- sink,
3501
- &enc_vri_c(opcode, rd.to_reg(), lane_imm.into(), rn, m4),
3502
- );
3503
- }
3504
-
3505
- &Inst::Call { link, ref info } => {
3506
- debug_assert_eq!(link.to_reg(), gpr(14));
3507
-
3508
- // Add relocation for TLS libcalls to enable linker optimizations.
3509
- match &info.tls_symbol {
3510
- None => {}
3511
- Some(SymbolReloc::TlsGd { name }) => {
3512
- sink.add_reloc(Reloc::S390xTlsGdCall, name, 0)
3513
- }
3514
- _ => unreachable!(),
3515
- }
3516
-
3517
- let opcode = 0xc05; // BRASL
3518
- let reloc = Reloc::S390xPLTRel32Dbl;
3519
- if let Some(s) = state.take_stack_map() {
3520
- sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
3521
- }
3522
- put_with_reloc(
3523
- sink,
3524
- &enc_ril_b(opcode, link.to_reg(), 0),
3525
- 2,
3526
- reloc,
3527
- &info.dest,
3528
- 0,
3529
- );
3530
- if info.opcode.is_call() {
3531
- sink.add_call_site(info.opcode);
3532
- }
3533
- }
3534
- &Inst::CallInd { link, ref info } => {
3535
- debug_assert_eq!(link.to_reg(), gpr(14));
3536
- let rn = allocs.next(info.rn);
3537
-
3538
- let opcode = 0x0d; // BASR
3539
- if let Some(s) = state.take_stack_map() {
3540
- sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
3541
- }
3542
- put(sink, &enc_rr(opcode, link.to_reg(), rn));
3543
- if info.opcode.is_call() {
3544
- sink.add_call_site(info.opcode);
3545
- }
3546
- }
3547
- &Inst::Args { .. } => {}
3548
- &Inst::Ret { link, .. } => {
3549
- debug_assert_eq!(link, gpr(14));
3550
-
3551
- let opcode = 0x07; // BCR
3552
- put(sink, &enc_rr(opcode, gpr(15), link));
3553
- }
3554
- &Inst::Jump { dest } => {
3555
- let off = sink.cur_offset();
3556
- // Indicate that the jump uses a label, if so, so that a fixup can occur later.
3557
- sink.use_label_at_offset(off, dest, LabelUse::BranchRIL);
3558
- sink.add_uncond_branch(off, off + 6, dest);
3559
- // Emit the jump itself.
3560
- let opcode = 0xc04; // BCRL
3561
- put(sink, &enc_ril_c(opcode, 15, 0));
3562
- }
3563
- &Inst::IndirectBr { rn, .. } => {
3564
- let rn = allocs.next(rn);
3565
-
3566
- let opcode = 0x07; // BCR
3567
- put(sink, &enc_rr(opcode, gpr(15), rn));
3568
- }
3569
- &Inst::CondBr {
3570
- taken,
3571
- not_taken,
3572
- cond,
3573
- } => {
3574
- let opcode = 0xc04; // BCRL
3575
-
3576
- // Conditional part first.
3577
- let cond_off = sink.cur_offset();
3578
- sink.use_label_at_offset(cond_off, taken, LabelUse::BranchRIL);
3579
- let inverted = &enc_ril_c(opcode, cond.invert().bits(), 0);
3580
- sink.add_cond_branch(cond_off, cond_off + 6, taken, inverted);
3581
- put(sink, &enc_ril_c(opcode, cond.bits(), 0));
3582
-
3583
- // Unconditional part next.
3584
- let uncond_off = sink.cur_offset();
3585
- sink.use_label_at_offset(uncond_off, not_taken, LabelUse::BranchRIL);
3586
- sink.add_uncond_branch(uncond_off, uncond_off + 6, not_taken);
3587
- put(sink, &enc_ril_c(opcode, 15, 0));
3588
- }
3589
- &Inst::OneWayCondBr { target, cond } => {
3590
- let opcode = 0xc04; // BCRL
3591
- sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
3592
- put(sink, &enc_ril_c(opcode, cond.bits(), 0));
3593
- }
3594
- &Inst::Nop0 => {}
3595
- &Inst::Nop2 => {
3596
- put(sink, &enc_e(0x0707));
3597
- }
3598
- &Inst::Debugtrap => {
3599
- put(sink, &enc_e(0x0001));
3600
- }
3601
- &Inst::Trap { trap_code } => {
3602
- if let Some(s) = state.take_stack_map() {
3603
- sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
3604
- }
3605
- put_with_trap(sink, &enc_e(0x0000), trap_code);
3606
- }
3607
- &Inst::TrapIf { cond, trap_code } => {
3608
- if let Some(s) = state.take_stack_map() {
3609
- sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
3610
- }
3611
- // We implement a TrapIf as a conditional branch into the middle
3612
- // of the branch (BRCL) instruction itself - those middle two bytes
3613
- // are zero, which matches the trap instruction itself.
3614
- let opcode = 0xc04; // BCRL
3615
- let enc = &enc_ril_c(opcode, cond.bits(), 2);
3616
- debug_assert!(enc.len() == 6 && enc[2] == 0 && enc[3] == 0);
3617
- // The trap must be placed on the last byte of the embedded trap
3618
- // instruction, so we need to emit the encoding in two parts.
3619
- put_with_trap(sink, &enc[0..4], trap_code);
3620
- put(sink, &enc[4..6]);
3621
- }
3622
- &Inst::JTSequence { ridx, ref targets } => {
3623
- let ridx = allocs.next(ridx);
3624
-
3625
- let table_label = sink.get_label();
3626
-
3627
- // This sequence is *one* instruction in the vcode, and is expanded only here at
3628
- // emission time, because we cannot allow the regalloc to insert spills/reloads in
3629
- // the middle; we depend on hardcoded PC-rel addressing below.
3630
-
3631
- // Set temp register to address of jump table.
3632
- let rtmp = writable_spilltmp_reg();
3633
- let inst = Inst::LoadAddr {
3634
- rd: rtmp,
3635
- mem: MemArg::Label {
3636
- target: table_label,
3637
- },
3638
- };
3639
- inst.emit(&[], sink, emit_info, state);
3640
-
3641
- // Set temp to target address by adding the value of the jump table entry.
3642
- let inst = Inst::AluRX {
3643
- alu_op: ALUOp::Add64Ext32,
3644
- rd: rtmp,
3645
- ri: rtmp.to_reg(),
3646
- mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()),
3647
- };
3648
- inst.emit(&[], sink, emit_info, state);
3649
-
3650
- // Branch to computed address. (`targets` here is only used for successor queries
3651
- // and is not needed for emission.)
3652
- let inst = Inst::IndirectBr {
3653
- rn: rtmp.to_reg(),
3654
- targets: vec![],
3655
- };
3656
- inst.emit(&[], sink, emit_info, state);
3657
-
3658
- // Emit jump table (table of 32-bit offsets).
3659
- // The first entry is the default target, which is not emitted
3660
- // into the jump table, so we skip it here. It is only in the
3661
- // list so MachTerminator will see the potential target.
3662
- sink.bind_label(table_label, &mut state.ctrl_plane);
3663
- let jt_off = sink.cur_offset();
3664
- for &target in targets.iter().skip(1) {
3665
- let word_off = sink.cur_offset();
3666
- let off_into_table = word_off - jt_off;
3667
- sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
3668
- sink.put4(off_into_table.swap_bytes());
3669
- }
3670
-
3671
- // Lowering produces an EmitIsland before using a JTSequence, so we can safely
3672
- // disable the worst-case-size check in this case.
3673
- start_off = sink.cur_offset();
3674
- }
3675
-
3676
- &Inst::VirtualSPOffsetAdj { offset } => {
3677
- trace!(
3678
- "virtual sp offset adjusted by {} -> {}",
3679
- offset,
3680
- state.virtual_sp_offset + offset
3681
- );
3682
- state.virtual_sp_offset += offset;
3683
- }
3684
-
3685
- &Inst::Unwind { ref inst } => {
3686
- sink.add_unwind(inst.clone());
3687
- }
3688
-
3689
- &Inst::DummyUse { .. } => {}
3690
- }
3691
-
3692
- let end_off = sink.cur_offset();
3693
- debug_assert!((end_off - start_off) <= Inst::worst_case_size());
3694
-
3695
- state.clear_post_insn();
3696
- }
3697
- }