wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
  208. data/ext/cargo-vendor/hashbrown-0.14.0/.cargo-checksum.json +1 -0
  209. data/ext/cargo-vendor/hashbrown-0.14.0/CHANGELOG.md +475 -0
  210. data/ext/cargo-vendor/hashbrown-0.14.0/Cargo.toml +131 -0
  211. data/ext/cargo-vendor/hashbrown-0.14.0/LICENSE-APACHE +201 -0
  212. data/ext/cargo-vendor/hashbrown-0.14.0/LICENSE-MIT +25 -0
  213. data/ext/cargo-vendor/hashbrown-0.14.0/README.md +125 -0
  214. data/ext/cargo-vendor/hashbrown-0.14.0/benches/bench.rs +331 -0
  215. data/ext/cargo-vendor/hashbrown-0.14.0/benches/insert_unique_unchecked.rs +32 -0
  216. data/ext/cargo-vendor/hashbrown-0.14.0/clippy.toml +1 -0
  217. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/mod.rs +6 -0
  218. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rayon/helpers.rs +27 -0
  219. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rayon/map.rs +731 -0
  220. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rayon/mod.rs +4 -0
  221. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rayon/raw.rs +231 -0
  222. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rayon/set.rs +659 -0
  223. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rkyv/hash_map.rs +125 -0
  224. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rkyv/hash_set.rs +123 -0
  225. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/rkyv/mod.rs +2 -0
  226. data/ext/cargo-vendor/hashbrown-0.14.0/src/external_trait_impls/serde.rs +201 -0
  227. data/ext/cargo-vendor/hashbrown-0.14.0/src/lib.rs +165 -0
  228. data/ext/cargo-vendor/hashbrown-0.14.0/src/macros.rs +70 -0
  229. data/ext/cargo-vendor/hashbrown-0.14.0/src/map.rs +8506 -0
  230. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/alloc.rs +86 -0
  231. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/bitmask.rs +133 -0
  232. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/generic.rs +157 -0
  233. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/mod.rs +3378 -0
  234. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/neon.rs +124 -0
  235. data/ext/cargo-vendor/hashbrown-0.14.0/src/raw/sse2.rs +149 -0
  236. data/ext/cargo-vendor/hashbrown-0.14.0/src/rustc_entry.rs +630 -0
  237. data/ext/cargo-vendor/hashbrown-0.14.0/src/scopeguard.rs +72 -0
  238. data/ext/cargo-vendor/hashbrown-0.14.0/src/set.rs +2903 -0
  239. data/ext/cargo-vendor/hashbrown-0.14.0/tests/equivalent_trait.rs +53 -0
  240. data/ext/cargo-vendor/hashbrown-0.14.0/tests/hasher.rs +65 -0
  241. data/ext/cargo-vendor/hashbrown-0.14.0/tests/raw.rs +11 -0
  242. data/ext/cargo-vendor/hashbrown-0.14.0/tests/rayon.rs +535 -0
  243. data/ext/cargo-vendor/hashbrown-0.14.0/tests/serde.rs +65 -0
  244. data/ext/cargo-vendor/hashbrown-0.14.0/tests/set.rs +34 -0
  245. data/ext/cargo-vendor/indexmap-2.0.0/.cargo-checksum.json +1 -0
  246. data/ext/cargo-vendor/indexmap-2.0.0/Cargo.toml +112 -0
  247. data/ext/cargo-vendor/indexmap-2.0.0/LICENSE-APACHE +201 -0
  248. data/ext/cargo-vendor/indexmap-2.0.0/LICENSE-MIT +25 -0
  249. data/ext/cargo-vendor/indexmap-2.0.0/README.md +55 -0
  250. data/ext/cargo-vendor/indexmap-2.0.0/RELEASES.md +424 -0
  251. data/ext/cargo-vendor/indexmap-2.0.0/benches/bench.rs +763 -0
  252. data/ext/cargo-vendor/indexmap-2.0.0/benches/faststring.rs +185 -0
  253. data/ext/cargo-vendor/indexmap-2.0.0/src/arbitrary.rs +77 -0
  254. data/ext/cargo-vendor/indexmap-2.0.0/src/lib.rs +278 -0
  255. data/ext/cargo-vendor/indexmap-2.0.0/src/macros.rs +178 -0
  256. data/ext/cargo-vendor/indexmap-2.0.0/src/map/core/raw.rs +217 -0
  257. data/ext/cargo-vendor/indexmap-2.0.0/src/map/core.rs +742 -0
  258. data/ext/cargo-vendor/indexmap-2.0.0/src/map/iter.rs +541 -0
  259. data/ext/cargo-vendor/indexmap-2.0.0/src/map/serde_seq.rs +138 -0
  260. data/ext/cargo-vendor/indexmap-2.0.0/src/map/slice.rs +471 -0
  261. data/ext/cargo-vendor/indexmap-2.0.0/src/map/tests.rs +449 -0
  262. data/ext/cargo-vendor/indexmap-2.0.0/src/map.rs +1223 -0
  263. data/ext/cargo-vendor/indexmap-2.0.0/src/mutable_keys.rs +91 -0
  264. data/ext/cargo-vendor/indexmap-2.0.0/src/rayon/map.rs +679 -0
  265. data/ext/cargo-vendor/indexmap-2.0.0/src/rayon/mod.rs +27 -0
  266. data/ext/cargo-vendor/indexmap-2.0.0/src/rayon/set.rs +774 -0
  267. data/ext/cargo-vendor/indexmap-2.0.0/src/rustc.rs +158 -0
  268. data/ext/cargo-vendor/indexmap-2.0.0/src/serde.rs +151 -0
  269. data/ext/cargo-vendor/indexmap-2.0.0/src/set/iter.rs +543 -0
  270. data/ext/cargo-vendor/indexmap-2.0.0/src/set/slice.rs +278 -0
  271. data/ext/cargo-vendor/indexmap-2.0.0/src/set/tests.rs +545 -0
  272. data/ext/cargo-vendor/indexmap-2.0.0/src/set.rs +1011 -0
  273. data/ext/cargo-vendor/indexmap-2.0.0/src/util.rs +53 -0
  274. data/ext/cargo-vendor/indexmap-2.0.0/tests/equivalent_trait.rs +53 -0
  275. data/ext/cargo-vendor/indexmap-2.0.0/tests/macros_full_path.rs +19 -0
  276. data/ext/cargo-vendor/indexmap-2.0.0/tests/quick.rs +579 -0
  277. data/ext/cargo-vendor/indexmap-2.0.0/tests/tests.rs +28 -0
  278. data/ext/cargo-vendor/regalloc2-0.9.2/.cargo-checksum.json +1 -0
  279. data/ext/cargo-vendor/regalloc2-0.9.2/Cargo.toml +72 -0
  280. data/ext/cargo-vendor/regalloc2-0.9.2/deny.toml +28 -0
  281. data/ext/cargo-vendor/regalloc2-0.9.2/src/checker.rs +1089 -0
  282. data/ext/cargo-vendor/regalloc2-0.9.2/src/fuzzing/func.rs +702 -0
  283. data/ext/cargo-vendor/regalloc2-0.9.2/src/index.rs +268 -0
  284. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/data_structures.rs +857 -0
  285. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/liveranges.rs +961 -0
  286. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/merge.rs +368 -0
  287. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/mod.rs +150 -0
  288. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/moves.rs +1017 -0
  289. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/process.rs +1307 -0
  290. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/requirement.rs +174 -0
  291. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/spill.rs +165 -0
  292. data/ext/cargo-vendor/regalloc2-0.9.2/src/ion/stackmap.rs +79 -0
  293. data/ext/cargo-vendor/regalloc2-0.9.2/src/lib.rs +1526 -0
  294. data/ext/cargo-vendor/regalloc2-0.9.2/src/moves.rs +439 -0
  295. data/ext/cargo-vendor/regalloc2-0.9.2/src/serialize.rs +311 -0
  296. data/ext/cargo-vendor/semver-1.0.18/.cargo-checksum.json +1 -0
  297. data/ext/cargo-vendor/semver-1.0.18/Cargo.toml +47 -0
  298. data/ext/cargo-vendor/semver-1.0.18/LICENSE-APACHE +176 -0
  299. data/ext/cargo-vendor/semver-1.0.18/LICENSE-MIT +23 -0
  300. data/ext/cargo-vendor/semver-1.0.18/README.md +84 -0
  301. data/ext/cargo-vendor/semver-1.0.18/benches/parse.rs +24 -0
  302. data/ext/cargo-vendor/semver-1.0.18/build.rs +75 -0
  303. data/ext/cargo-vendor/semver-1.0.18/src/backport.rs +23 -0
  304. data/ext/cargo-vendor/semver-1.0.18/src/display.rs +165 -0
  305. data/ext/cargo-vendor/semver-1.0.18/src/error.rs +126 -0
  306. data/ext/cargo-vendor/semver-1.0.18/src/eval.rs +181 -0
  307. data/ext/cargo-vendor/semver-1.0.18/src/identifier.rs +422 -0
  308. data/ext/cargo-vendor/semver-1.0.18/src/impls.rs +156 -0
  309. data/ext/cargo-vendor/semver-1.0.18/src/lib.rs +533 -0
  310. data/ext/cargo-vendor/semver-1.0.18/src/parse.rs +409 -0
  311. data/ext/cargo-vendor/semver-1.0.18/src/serde.rs +109 -0
  312. data/ext/cargo-vendor/semver-1.0.18/tests/node/mod.rs +43 -0
  313. data/ext/cargo-vendor/semver-1.0.18/tests/test_autotrait.rs +14 -0
  314. data/ext/cargo-vendor/semver-1.0.18/tests/test_identifier.rs +45 -0
  315. data/ext/cargo-vendor/semver-1.0.18/tests/test_version.rs +238 -0
  316. data/ext/cargo-vendor/semver-1.0.18/tests/test_version_req.rs +443 -0
  317. data/ext/cargo-vendor/semver-1.0.18/tests/util/mod.rs +39 -0
  318. data/ext/cargo-vendor/sptr-0.3.2/.cargo-checksum.json +1 -0
  319. data/ext/cargo-vendor/sptr-0.3.2/Cargo.toml +28 -0
  320. data/ext/cargo-vendor/sptr-0.3.2/README.md +73 -0
  321. data/ext/cargo-vendor/sptr-0.3.2/src/func.rs +83 -0
  322. data/ext/cargo-vendor/sptr-0.3.2/src/int.rs +364 -0
  323. data/ext/cargo-vendor/sptr-0.3.2/src/lib.rs +756 -0
  324. data/ext/cargo-vendor/wasi-cap-std-sync-10.0.1/.cargo-checksum.json +1 -0
  325. data/ext/cargo-vendor/wasi-cap-std-sync-10.0.1/Cargo.toml +90 -0
  326. data/ext/cargo-vendor/wasi-cap-std-sync-10.0.1/src/dir.rs +464 -0
  327. data/ext/cargo-vendor/wasi-cap-std-sync-10.0.1/src/lib.rs +141 -0
  328. data/ext/cargo-vendor/wasi-common-10.0.1/.cargo-checksum.json +1 -0
  329. data/ext/cargo-vendor/wasi-common-10.0.1/Cargo.toml +87 -0
  330. data/ext/cargo-vendor/wasi-common-10.0.1/src/ctx.rs +128 -0
  331. data/ext/cargo-vendor/wasi-common-10.0.1/src/file.rs +262 -0
  332. data/ext/cargo-vendor/wasi-common-10.0.1/src/snapshots/preview_1.rs +1490 -0
  333. data/ext/cargo-vendor/wasm-encoder-0.29.0/.cargo-checksum.json +1 -0
  334. data/ext/cargo-vendor/wasm-encoder-0.29.0/Cargo.toml +33 -0
  335. data/ext/cargo-vendor/wasm-encoder-0.29.0/README.md +80 -0
  336. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/aliases.rs +160 -0
  337. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/canonicals.rs +159 -0
  338. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/components.rs +29 -0
  339. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/exports.rs +127 -0
  340. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/imports.rs +200 -0
  341. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/instances.rs +200 -0
  342. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/modules.rs +29 -0
  343. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/names.rs +149 -0
  344. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/start.rs +52 -0
  345. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component/types.rs +759 -0
  346. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/component.rs +160 -0
  347. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/code.rs +2913 -0
  348. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/custom.rs +55 -0
  349. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/data.rs +185 -0
  350. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/dump.rs +627 -0
  351. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/elements.rs +224 -0
  352. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/exports.rs +85 -0
  353. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/functions.rs +63 -0
  354. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/globals.rs +90 -0
  355. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/imports.rs +142 -0
  356. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/linking.rs +263 -0
  357. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/memories.rs +99 -0
  358. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/names.rs +265 -0
  359. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/producers.rs +180 -0
  360. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/start.rs +39 -0
  361. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/tables.rs +104 -0
  362. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/tags.rs +85 -0
  363. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core/types.rs +246 -0
  364. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/core.rs +168 -0
  365. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/lib.rs +215 -0
  366. data/ext/cargo-vendor/wasm-encoder-0.29.0/src/raw.rs +30 -0
  367. data/ext/cargo-vendor/wasmparser-0.107.0/.cargo-checksum.json +1 -0
  368. data/ext/cargo-vendor/wasmparser-0.107.0/Cargo.lock +621 -0
  369. data/ext/cargo-vendor/wasmparser-0.107.0/Cargo.toml +54 -0
  370. data/ext/cargo-vendor/wasmparser-0.107.0/benches/benchmark.rs +351 -0
  371. data/ext/cargo-vendor/wasmparser-0.107.0/src/binary_reader.rs +1706 -0
  372. data/ext/cargo-vendor/wasmparser-0.107.0/src/lib.rs +723 -0
  373. data/ext/cargo-vendor/wasmparser-0.107.0/src/parser.rs +1535 -0
  374. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/component/canonicals.rs +119 -0
  375. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/component/exports.rs +117 -0
  376. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/component/imports.rs +137 -0
  377. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/component/instances.rs +163 -0
  378. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/component/types.rs +548 -0
  379. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/core/coredumps.rs +243 -0
  380. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/core/producers.rs +83 -0
  381. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/core/types.rs +874 -0
  382. data/ext/cargo-vendor/wasmparser-0.107.0/src/readers/core.rs +35 -0
  383. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator/component.rs +3082 -0
  384. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator/core.rs +1334 -0
  385. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator/names.rs +606 -0
  386. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator/operators.rs +3463 -0
  387. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator/types.rs +3070 -0
  388. data/ext/cargo-vendor/wasmparser-0.107.0/src/validator.rs +1589 -0
  389. data/ext/cargo-vendor/wasmparser-0.111.0/.cargo-checksum.json +1 -0
  390. data/ext/cargo-vendor/wasmparser-0.111.0/Cargo.lock +644 -0
  391. data/ext/cargo-vendor/wasmparser-0.111.0/Cargo.toml +54 -0
  392. data/ext/cargo-vendor/wasmparser-0.111.0/README.md +36 -0
  393. data/ext/cargo-vendor/wasmparser-0.111.0/benches/benchmark.rs +349 -0
  394. data/ext/cargo-vendor/wasmparser-0.111.0/examples/simple.rs +37 -0
  395. data/ext/cargo-vendor/wasmparser-0.111.0/src/binary_reader.rs +1706 -0
  396. data/ext/cargo-vendor/wasmparser-0.111.0/src/lib.rs +726 -0
  397. data/ext/cargo-vendor/wasmparser-0.111.0/src/limits.rs +59 -0
  398. data/ext/cargo-vendor/wasmparser-0.111.0/src/parser.rs +1612 -0
  399. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/aliases.rs +119 -0
  400. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/canonicals.rs +120 -0
  401. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/exports.rs +117 -0
  402. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/imports.rs +137 -0
  403. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/instances.rs +163 -0
  404. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/names.rs +102 -0
  405. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/start.rs +30 -0
  406. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component/types.rs +548 -0
  407. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/component.rs +17 -0
  408. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/code.rs +146 -0
  409. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/coredumps.rs +243 -0
  410. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/custom.rs +63 -0
  411. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/data.rs +96 -0
  412. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/dylink0.rs +132 -0
  413. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/elements.rs +152 -0
  414. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/exports.rs +65 -0
  415. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/functions.rs +17 -0
  416. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/globals.rs +49 -0
  417. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/imports.rs +76 -0
  418. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/init.rs +51 -0
  419. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/memories.rs +56 -0
  420. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/names.rs +153 -0
  421. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/operators.rs +354 -0
  422. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/producers.rs +83 -0
  423. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/tables.rs +87 -0
  424. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/tags.rs +32 -0
  425. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core/types.rs +1141 -0
  426. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers/core.rs +37 -0
  427. data/ext/cargo-vendor/wasmparser-0.111.0/src/readers.rs +316 -0
  428. data/ext/cargo-vendor/wasmparser-0.111.0/src/resources.rs +398 -0
  429. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/component.rs +3148 -0
  430. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/core.rs +1314 -0
  431. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/func.rs +348 -0
  432. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/names.rs +606 -0
  433. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/operators.rs +3466 -0
  434. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator/types.rs +3283 -0
  435. data/ext/cargo-vendor/wasmparser-0.111.0/src/validator.rs +1568 -0
  436. data/ext/cargo-vendor/wasmparser-0.111.0/tests/big-module.rs +33 -0
  437. data/ext/cargo-vendor/wasmprinter-0.2.63/.cargo-checksum.json +1 -0
  438. data/ext/cargo-vendor/wasmprinter-0.2.63/Cargo.toml +39 -0
  439. data/ext/cargo-vendor/wasmprinter-0.2.63/README.md +47 -0
  440. data/ext/cargo-vendor/wasmprinter-0.2.63/src/lib.rs +2962 -0
  441. data/ext/cargo-vendor/wasmprinter-0.2.63/src/operator.rs +873 -0
  442. data/ext/cargo-vendor/wasmprinter-0.2.63/tests/all.rs +278 -0
  443. data/ext/cargo-vendor/wasmtime-10.0.1/.cargo-checksum.json +1 -0
  444. data/ext/cargo-vendor/wasmtime-10.0.1/Cargo.toml +183 -0
  445. data/ext/cargo-vendor/wasmtime-10.0.1/src/compiler.rs +710 -0
  446. data/ext/cargo-vendor/wasmtime-10.0.1/src/component/component.rs +382 -0
  447. data/ext/cargo-vendor/wasmtime-10.0.1/src/component/instance.rs +727 -0
  448. data/ext/cargo-vendor/wasmtime-10.0.1/src/component/matching.rs +112 -0
  449. data/ext/cargo-vendor/wasmtime-10.0.1/src/component/mod.rs +313 -0
  450. data/ext/cargo-vendor/wasmtime-10.0.1/src/config.rs +2066 -0
  451. data/ext/cargo-vendor/wasmtime-10.0.1/src/engine/serialization.rs +622 -0
  452. data/ext/cargo-vendor/wasmtime-10.0.1/src/engine.rs +757 -0
  453. data/ext/cargo-vendor/wasmtime-10.0.1/src/externals.rs +763 -0
  454. data/ext/cargo-vendor/wasmtime-10.0.1/src/func/typed.rs +638 -0
  455. data/ext/cargo-vendor/wasmtime-10.0.1/src/func.rs +2355 -0
  456. data/ext/cargo-vendor/wasmtime-10.0.1/src/instance.rs +905 -0
  457. data/ext/cargo-vendor/wasmtime-10.0.1/src/lib.rs +486 -0
  458. data/ext/cargo-vendor/wasmtime-10.0.1/src/linker.rs +1479 -0
  459. data/ext/cargo-vendor/wasmtime-10.0.1/src/memory.rs +950 -0
  460. data/ext/cargo-vendor/wasmtime-10.0.1/src/module.rs +1274 -0
  461. data/ext/cargo-vendor/wasmtime-10.0.1/src/ref.rs +109 -0
  462. data/ext/cargo-vendor/wasmtime-10.0.1/src/store/context.rs +243 -0
  463. data/ext/cargo-vendor/wasmtime-10.0.1/src/store/func_refs.rs +85 -0
  464. data/ext/cargo-vendor/wasmtime-10.0.1/src/store.rs +2166 -0
  465. data/ext/cargo-vendor/wasmtime-10.0.1/src/trampoline/func.rs +133 -0
  466. data/ext/cargo-vendor/wasmtime-10.0.1/src/trampoline/global.rs +67 -0
  467. data/ext/cargo-vendor/wasmtime-10.0.1/src/types/matching.rs +312 -0
  468. data/ext/cargo-vendor/wasmtime-10.0.1/src/types.rs +572 -0
  469. data/ext/cargo-vendor/wasmtime-10.0.1/src/values.rs +290 -0
  470. data/ext/cargo-vendor/wasmtime-asm-macros-10.0.1/.cargo-checksum.json +1 -0
  471. data/ext/cargo-vendor/wasmtime-asm-macros-10.0.1/Cargo.toml +22 -0
  472. data/ext/cargo-vendor/wasmtime-cache-10.0.1/.cargo-checksum.json +1 -0
  473. data/ext/cargo-vendor/wasmtime-cache-10.0.1/Cargo.toml +73 -0
  474. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/.cargo-checksum.json +1 -0
  475. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/Cargo.toml +58 -0
  476. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/src/bindgen.rs +316 -0
  477. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/char.wit +13 -0
  478. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/conventions.wit +39 -0
  479. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/direct-import.wit +5 -0
  480. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/empty.wit +2 -0
  481. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/flags.wit +55 -0
  482. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/floats.wit +13 -0
  483. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/function-new.wit +4 -0
  484. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/integers.wit +40 -0
  485. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/lists.wit +85 -0
  486. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/many-arguments.wit +52 -0
  487. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/multi-return.wit +14 -0
  488. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/records.wit +61 -0
  489. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/rename.wit +16 -0
  490. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/share-types.wit +21 -0
  491. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/simple-functions.wit +17 -0
  492. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/simple-lists.wit +13 -0
  493. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/simple-wasi.wit +23 -0
  494. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/small-anonymous.wit +15 -0
  495. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/smoke-default.wit +5 -0
  496. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/smoke-export.wit +7 -0
  497. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/smoke.wit +7 -0
  498. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/strings.wit +12 -0
  499. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/unions.wit +66 -0
  500. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/use-paths.wit +29 -0
  501. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/variants.wit +147 -0
  502. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen/worlds-with-types.wit +16 -0
  503. data/ext/cargo-vendor/wasmtime-component-macro-10.0.1/tests/codegen.rs +24 -0
  504. data/ext/cargo-vendor/wasmtime-component-util-10.0.1/.cargo-checksum.json +1 -0
  505. data/ext/cargo-vendor/wasmtime-component-util-10.0.1/Cargo.toml +25 -0
  506. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/.cargo-checksum.json +1 -0
  507. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/Cargo.toml +90 -0
  508. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/src/compiler.rs +1200 -0
  509. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/src/debug/transform/simulate.rs +410 -0
  510. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/src/func_environ.rs +2206 -0
  511. data/ext/cargo-vendor/wasmtime-cranelift-10.0.1/src/lib.rs +178 -0
  512. data/ext/cargo-vendor/wasmtime-cranelift-shared-10.0.1/.cargo-checksum.json +1 -0
  513. data/ext/cargo-vendor/wasmtime-cranelift-shared-10.0.1/Cargo.toml +57 -0
  514. data/ext/cargo-vendor/wasmtime-cranelift-shared-10.0.1/src/lib.rs +120 -0
  515. data/ext/cargo-vendor/wasmtime-environ-10.0.1/.cargo-checksum.json +1 -0
  516. data/ext/cargo-vendor/wasmtime-environ-10.0.1/Cargo.lock +681 -0
  517. data/ext/cargo-vendor/wasmtime-environ-10.0.1/Cargo.toml +116 -0
  518. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/component/compiler.rs +84 -0
  519. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/component/translate/inline.rs +1067 -0
  520. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/component/translate.rs +1070 -0
  521. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/component/types.rs +1916 -0
  522. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/fact.rs +623 -0
  523. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/module.rs +1083 -0
  524. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/module_environ.rs +884 -0
  525. data/ext/cargo-vendor/wasmtime-environ-10.0.1/src/trap_encoding.rs +238 -0
  526. data/ext/cargo-vendor/wasmtime-fiber-10.0.1/.cargo-checksum.json +1 -0
  527. data/ext/cargo-vendor/wasmtime-fiber-10.0.1/Cargo.toml +46 -0
  528. data/ext/cargo-vendor/wasmtime-fiber-10.0.1/src/lib.rs +305 -0
  529. data/ext/cargo-vendor/wasmtime-fiber-10.0.1/src/unix.rs +212 -0
  530. data/ext/cargo-vendor/wasmtime-fiber-10.0.1/src/windows.rs +161 -0
  531. data/ext/cargo-vendor/wasmtime-jit-10.0.1/.cargo-checksum.json +1 -0
  532. data/ext/cargo-vendor/wasmtime-jit-10.0.1/Cargo.toml +104 -0
  533. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/instantiate.rs +760 -0
  534. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/lib.rs +38 -0
  535. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/profiling/jitdump.rs +66 -0
  536. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/profiling/perfmap.rs +47 -0
  537. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/profiling/vtune.rs +80 -0
  538. data/ext/cargo-vendor/wasmtime-jit-10.0.1/src/profiling.rs +108 -0
  539. data/ext/cargo-vendor/wasmtime-jit-debug-10.0.1/.cargo-checksum.json +1 -0
  540. data/ext/cargo-vendor/wasmtime-jit-debug-10.0.1/Cargo.toml +55 -0
  541. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-10.0.1/.cargo-checksum.json +1 -0
  542. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-10.0.1/Cargo.toml +37 -0
  543. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/.cargo-checksum.json +1 -0
  544. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/Cargo.toml +110 -0
  545. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/component.rs +701 -0
  546. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/cow.rs +1060 -0
  547. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/debug_builtins.rs +58 -0
  548. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/externref.rs +1073 -0
  549. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/instance/allocator/pooling.rs +1368 -0
  550. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/instance/allocator.rs +531 -0
  551. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/instance.rs +1345 -0
  552. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/lib.rs +285 -0
  553. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/libcalls.rs +578 -0
  554. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/memory.rs +958 -0
  555. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/mmap/miri.rs +94 -0
  556. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/mmap/unix.rs +148 -0
  557. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/mmap/windows.rs +208 -0
  558. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/send_sync_ptr.rs +69 -0
  559. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/table.rs +595 -0
  560. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/traphandlers/unix.rs +387 -0
  561. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/traphandlers.rs +749 -0
  562. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/vmcontext/vm_host_func_context.rs +137 -0
  563. data/ext/cargo-vendor/wasmtime-runtime-10.0.1/src/vmcontext.rs +1221 -0
  564. data/ext/cargo-vendor/wasmtime-types-10.0.1/.cargo-checksum.json +1 -0
  565. data/ext/cargo-vendor/wasmtime-types-10.0.1/Cargo.toml +34 -0
  566. data/ext/cargo-vendor/wasmtime-types-10.0.1/src/lib.rs +462 -0
  567. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/.cargo-checksum.json +1 -0
  568. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/Cargo.toml +153 -0
  569. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/lib.rs +131 -0
  570. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/clocks/host.rs +73 -0
  571. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/clocks.rs +17 -0
  572. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/ctx.rs +206 -0
  573. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/error.rs +16 -0
  574. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/filesystem.rs +269 -0
  575. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/mod.rs +44 -0
  576. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/pipe.rs +233 -0
  577. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview1/mod.rs +1860 -0
  578. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/clocks.rs +80 -0
  579. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/env.rs +48 -0
  580. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/exit.rs +12 -0
  581. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/filesystem.rs +1020 -0
  582. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/io.rs +215 -0
  583. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/mod.rs +7 -0
  584. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/poll.rs +84 -0
  585. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/preview2/random.rs +41 -0
  586. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/random.rs +58 -0
  587. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/sched/subscription.rs +104 -0
  588. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/sched/sync.rs +156 -0
  589. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/sched.rs +105 -0
  590. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/stdio.rs +176 -0
  591. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/stream.rs +210 -0
  592. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/table.rs +107 -0
  593. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/wasi/command.rs +43 -0
  594. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/src/preview2/wasi/mod.rs +30 -0
  595. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/clocks/monotonic-clock.wit +34 -0
  596. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/clocks/timezone.wit +63 -0
  597. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/clocks/wall-clock.wit +43 -0
  598. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/filesystem/filesystem.wit +782 -0
  599. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/http/incoming-handler.wit +24 -0
  600. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/http/outgoing-handler.wit +18 -0
  601. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/http/types.wit +159 -0
  602. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/io/streams.wit +215 -0
  603. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/logging/handler.wit +34 -0
  604. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/poll/poll.wit +41 -0
  605. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/preview/command-extended.wit +36 -0
  606. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/preview/command.wit +26 -0
  607. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/preview/proxy.wit +9 -0
  608. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/preview/reactor.wit +24 -0
  609. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/random/insecure-seed.wit +24 -0
  610. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/random/insecure.wit +21 -0
  611. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/random/random.wit +25 -0
  612. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/instance-network.wit +9 -0
  613. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/ip-name-lookup.wit +69 -0
  614. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/network.wit +187 -0
  615. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/tcp-create-socket.wit +27 -0
  616. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/tcp.wit +255 -0
  617. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/udp-create-socket.wit +27 -0
  618. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/sockets/udp.wit +211 -0
  619. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/wasi-cli-base/environment.wit +16 -0
  620. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/wasi-cli-base/exit.wit +4 -0
  621. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/wasi-cli-base/preopens.wit +7 -0
  622. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/deps/wasi-cli-base/stdio.wit +17 -0
  623. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/main.wit +1 -0
  624. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/wit/test.wit +19 -0
  625. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/witx/typenames.witx +750 -0
  626. data/ext/cargo-vendor/wasmtime-wasi-10.0.1/witx/wasi_snapshot_preview1.witx +521 -0
  627. data/ext/cargo-vendor/wasmtime-winch-10.0.1/.cargo-checksum.json +1 -0
  628. data/ext/cargo-vendor/wasmtime-winch-10.0.1/Cargo.toml +63 -0
  629. data/ext/cargo-vendor/wasmtime-winch-10.0.1/src/compiler.rs +220 -0
  630. data/ext/cargo-vendor/wasmtime-wit-bindgen-10.0.1/.cargo-checksum.json +1 -0
  631. data/ext/cargo-vendor/wasmtime-wit-bindgen-10.0.1/Cargo.toml +29 -0
  632. data/ext/cargo-vendor/wasmtime-wit-bindgen-10.0.1/src/lib.rs +1631 -0
  633. data/ext/cargo-vendor/wasmtime-wit-bindgen-10.0.1/src/types.rs +179 -0
  634. data/ext/cargo-vendor/wiggle-10.0.1/.cargo-checksum.json +1 -0
  635. data/ext/cargo-vendor/wiggle-10.0.1/Cargo.toml +106 -0
  636. data/ext/cargo-vendor/wiggle-10.0.1/LICENSE +220 -0
  637. data/ext/cargo-vendor/wiggle-10.0.1/README.md +18 -0
  638. data/ext/cargo-vendor/wiggle-generate-10.0.1/.cargo-checksum.json +1 -0
  639. data/ext/cargo-vendor/wiggle-generate-10.0.1/Cargo.toml +58 -0
  640. data/ext/cargo-vendor/wiggle-generate-10.0.1/LICENSE +220 -0
  641. data/ext/cargo-vendor/wiggle-macro-10.0.1/.cargo-checksum.json +1 -0
  642. data/ext/cargo-vendor/wiggle-macro-10.0.1/Cargo.toml +55 -0
  643. data/ext/cargo-vendor/wiggle-macro-10.0.1/LICENSE +220 -0
  644. data/ext/cargo-vendor/wiggle-macro-10.0.1/src/lib.rs +210 -0
  645. data/ext/cargo-vendor/winch-codegen-0.8.1/.cargo-checksum.json +1 -0
  646. data/ext/cargo-vendor/winch-codegen-0.8.1/Cargo.toml +62 -0
  647. data/ext/cargo-vendor/winch-codegen-0.8.1/src/abi/local.rs +70 -0
  648. data/ext/cargo-vendor/winch-codegen-0.8.1/src/abi/mod.rs +237 -0
  649. data/ext/cargo-vendor/winch-codegen-0.8.1/src/codegen/call.rs +225 -0
  650. data/ext/cargo-vendor/winch-codegen-0.8.1/src/codegen/context.rs +270 -0
  651. data/ext/cargo-vendor/winch-codegen-0.8.1/src/codegen/env.rs +52 -0
  652. data/ext/cargo-vendor/winch-codegen-0.8.1/src/codegen/mod.rs +214 -0
  653. data/ext/cargo-vendor/winch-codegen-0.8.1/src/frame/mod.rs +172 -0
  654. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/aarch64/abi.rs +243 -0
  655. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/aarch64/asm.rs +300 -0
  656. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/aarch64/masm.rs +230 -0
  657. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/aarch64/mod.rs +127 -0
  658. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/aarch64/regs.rs +166 -0
  659. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/mod.rs +215 -0
  660. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/abi.rs +369 -0
  661. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/address.rs +17 -0
  662. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/asm.rs +576 -0
  663. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/masm.rs +288 -0
  664. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/mod.rs +149 -0
  665. data/ext/cargo-vendor/winch-codegen-0.8.1/src/isa/x64/regs.rs +192 -0
  666. data/ext/cargo-vendor/winch-codegen-0.8.1/src/lib.rs +21 -0
  667. data/ext/cargo-vendor/winch-codegen-0.8.1/src/masm.rs +255 -0
  668. data/ext/cargo-vendor/winch-codegen-0.8.1/src/regalloc.rs +70 -0
  669. data/ext/cargo-vendor/winch-codegen-0.8.1/src/stack.rs +235 -0
  670. data/ext/cargo-vendor/winch-codegen-0.8.1/src/trampoline.rs +494 -0
  671. data/ext/cargo-vendor/winch-codegen-0.8.1/src/visitor.rs +353 -0
  672. data/ext/cargo-vendor/wit-parser-0.8.0/.cargo-checksum.json +1 -0
  673. data/ext/cargo-vendor/wit-parser-0.8.0/Cargo.toml +62 -0
  674. data/ext/cargo-vendor/wit-parser-0.8.0/src/ast/lex.rs +679 -0
  675. data/ext/cargo-vendor/wit-parser-0.8.0/src/ast/resolve.rs +1122 -0
  676. data/ext/cargo-vendor/wit-parser-0.8.0/src/ast.rs +1207 -0
  677. data/ext/cargo-vendor/wit-parser-0.8.0/src/lib.rs +622 -0
  678. data/ext/cargo-vendor/wit-parser-0.8.0/src/live.rs +111 -0
  679. data/ext/cargo-vendor/wit-parser-0.8.0/src/resolve.rs +1307 -0
  680. data/ext/cargo-vendor/wit-parser-0.8.0/tests/all.rs +168 -0
  681. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/comments.wit +25 -0
  682. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/diamond1/deps/dep1/types.wit +2 -0
  683. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/diamond1/deps/dep2/types.wit +2 -0
  684. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/diamond1/join.wit +6 -0
  685. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/disambiguate-diamond/shared1.wit +3 -0
  686. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/disambiguate-diamond/shared2.wit +3 -0
  687. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/disambiguate-diamond/world.wit +13 -0
  688. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/embedded.wit.md +34 -0
  689. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/empty.wit +1 -0
  690. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +3 -0
  691. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/corp/saas.wit +4 -0
  692. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +2 -0
  693. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +5 -0
  694. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +13 -0
  695. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/wasi/clocks.wit +5 -0
  696. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/deps/wasi/filesystem.wit +7 -0
  697. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/foreign-deps/root.wit +44 -0
  698. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/functions.wit +14 -0
  699. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/many-names/a.wit +2 -0
  700. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/many-names/b.wit +5 -0
  701. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/multi-file/bar.wit +21 -0
  702. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/multi-file/cycle-a.wit +7 -0
  703. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/multi-file/cycle-b.wit +3 -0
  704. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/multi-file/foo.wit +31 -0
  705. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/package-syntax1.wit +1 -0
  706. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/package-syntax3.wit +1 -0
  707. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/package-syntax4.wit +1 -0
  708. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/alias-no-type.wit.result +1 -0
  709. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-function.wit +7 -0
  710. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-function.wit.result +5 -0
  711. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-function2.wit +7 -0
  712. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-function2.wit.result +5 -0
  713. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg1/root.wit +5 -0
  714. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg1.wit.result +8 -0
  715. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg2/deps/bar/empty.wit +1 -0
  716. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg2/root.wit +5 -0
  717. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg2.wit.result +5 -0
  718. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +2 -0
  719. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg3/root.wit +5 -0
  720. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg3.wit.result +5 -0
  721. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +4 -0
  722. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg4/root.wit +4 -0
  723. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg4.wit.result +5 -0
  724. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +3 -0
  725. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg5/root.wit +4 -0
  726. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg5.wit.result +5 -0
  727. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +4 -0
  728. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg6/root.wit +4 -0
  729. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-pkg6.wit.result +5 -0
  730. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-world-type1.wit +5 -0
  731. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/bad-world-type1.wit.result +5 -0
  732. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/conflicting-package/a.wit +1 -0
  733. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/conflicting-package/b.wit +1 -0
  734. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/conflicting-package.wit.result +8 -0
  735. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle.wit +6 -0
  736. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle.wit.result +5 -0
  737. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle2.wit +7 -0
  738. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle2.wit.result +5 -0
  739. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle3.wit +7 -0
  740. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle3.wit.result +5 -0
  741. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle4.wit +7 -0
  742. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle4.wit.result +5 -0
  743. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle5.wit +7 -0
  744. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/cycle5.wit.result +5 -0
  745. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-functions.wit +8 -0
  746. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-functions.wit.result +5 -0
  747. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-interface.wit +6 -0
  748. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-interface.wit.result +5 -0
  749. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-interface2/foo.wit +3 -0
  750. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-interface2/foo2.wit +3 -0
  751. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-interface2.wit.result +8 -0
  752. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-type.wit +7 -0
  753. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/duplicate-type.wit.result +5 -0
  754. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-enum.wit +6 -0
  755. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-enum.wit.result +5 -0
  756. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-union.wit +6 -0
  757. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-union.wit.result +5 -0
  758. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-variant1.wit +6 -0
  759. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/empty-variant1.wit.result +5 -0
  760. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/export-twice.wit +8 -0
  761. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/export-twice.wit.result +5 -0
  762. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-export-overlap1.wit +5 -0
  763. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-export-overlap1.wit.result +5 -0
  764. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-export-overlap2.wit +5 -0
  765. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-export-overlap2.wit.result +5 -0
  766. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-twice.wit +8 -0
  767. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/import-twice.wit.result +5 -0
  768. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/invalid-md.wit.result +5 -0
  769. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/invalid-type-reference.wit +10 -0
  770. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/invalid-type-reference.wit.result +5 -0
  771. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/invalid-type-reference2.wit +6 -0
  772. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/invalid-type-reference2.wit.result +5 -0
  773. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit.result +1 -0
  774. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/no-access-to-sibling-use/bar.wit +1 -0
  775. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/no-access-to-sibling-use/foo.wit +5 -0
  776. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/no-access-to-sibling-use.wit.result +8 -0
  777. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle/deps/a1/root.wit +4 -0
  778. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle/root.wit +4 -0
  779. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle.wit.result +5 -0
  780. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle2/deps/a1/root.wit +4 -0
  781. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle2/deps/a2/root.wit +4 -0
  782. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle2/root.wit +4 -0
  783. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/pkg-cycle2.wit.result +5 -0
  784. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/undefined-typed.wit +6 -0
  785. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/undefined-typed.wit.result +5 -0
  786. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unknown-interface.wit +7 -0
  787. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unknown-interface.wit.result +5 -0
  788. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface1.wit +7 -0
  789. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface1.wit.result +5 -0
  790. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface2.wit +8 -0
  791. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface2.wit.result +5 -0
  792. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface3.wit +5 -0
  793. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface3.wit.result +5 -0
  794. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface4.wit +7 -0
  795. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-interface4.wit.result +5 -0
  796. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use1.wit +7 -0
  797. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use1.wit.result +5 -0
  798. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use10/bar.wit +5 -0
  799. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use10.wit.result +8 -0
  800. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use2.wit +10 -0
  801. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use2.wit.result +5 -0
  802. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use3.wit +11 -0
  803. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use3.wit.result +5 -0
  804. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use7.wit +10 -0
  805. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use7.wit.result +5 -0
  806. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use8.wit +9 -0
  807. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use8.wit.result +5 -0
  808. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use9.wit +9 -0
  809. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/unresolved-use9.wit.result +5 -0
  810. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict.wit +11 -0
  811. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict.wit.result +5 -0
  812. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict2.wit +13 -0
  813. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict2.wit.result +5 -0
  814. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict3.wit +13 -0
  815. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-conflict3.wit.result +5 -0
  816. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-cycle1.wit +7 -0
  817. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-cycle1.wit.result +5 -0
  818. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-cycle4.wit +14 -0
  819. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-cycle4.wit.result +5 -0
  820. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-shadow1.wit +7 -0
  821. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/use-shadow1.wit.result +5 -0
  822. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-interface-clash.wit +3 -0
  823. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-interface-clash.wit.result +5 -0
  824. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-same-fields2.wit +8 -0
  825. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-same-fields2.wit.result +5 -0
  826. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-same-fields3.wit +8 -0
  827. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-same-fields3.wit.result +5 -0
  828. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-top-level-func.wit +5 -0
  829. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-top-level-func.wit.result +5 -0
  830. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-top-level-func2.wit +4 -0
  831. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/parse-fail/world-top-level-func2.wit.result +5 -0
  832. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/shared-types.wit +10 -0
  833. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/type-then-eof.wit +5 -0
  834. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/types.wit +61 -0
  835. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/use-chain.wit +11 -0
  836. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/use.wit +34 -0
  837. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/versions/deps/a1/foo.wit +5 -0
  838. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/versions/deps/a2/foo.wit +5 -0
  839. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/versions/foo.wit +7 -0
  840. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/wasi.wit +178 -0
  841. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-diamond.wit +22 -0
  842. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-iface-no-collide.wit +11 -0
  843. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-implicit-import1.wit +12 -0
  844. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-implicit-import2.wit +11 -0
  845. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-implicit-import3.wit +11 -0
  846. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-same-fields4.wit +13 -0
  847. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/world-top-level-funcs.wit +9 -0
  848. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/worlds-same-fields5.wit +17 -0
  849. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/worlds-with-types.wit +34 -0
  850. data/ext/cargo-vendor/wit-parser-0.8.0/tests/ui/worlds.wit +37 -0
  851. data/ext/src/ruby_api/global.rs +3 -3
  852. data/ext/src/ruby_api/memory/unsafe_slice.rs +9 -3
  853. data/ext/src/ruby_api/params.rs +14 -12
  854. data/ext/src/ruby_api/table.rs +1 -1
  855. data/lib/wasmtime/version.rb +1 -1
  856. metadata +1418 -1079
  857. data/ext/cargo-vendor/cranelift-bforest-0.96.4/.cargo-checksum.json +0 -1
  858. data/ext/cargo-vendor/cranelift-bforest-0.96.4/Cargo.toml +0 -31
  859. data/ext/cargo-vendor/cranelift-codegen-0.96.4/.cargo-checksum.json +0 -1
  860. data/ext/cargo-vendor/cranelift-codegen-0.96.4/Cargo.toml +0 -159
  861. data/ext/cargo-vendor/cranelift-codegen-0.96.4/benches/x64-evex-encoding.rs +0 -53
  862. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/ir/trapcode.rs +0 -138
  863. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/abi.rs +0 -1281
  864. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/inst/emit.rs +0 -3658
  865. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/inst/emit_tests.rs +0 -7868
  866. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/inst/imms.rs +0 -1215
  867. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/inst/mod.rs +0 -2945
  868. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/inst.isle +0 -4035
  869. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/lower/isle.rs +0 -813
  870. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/lower.isle +0 -2906
  871. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/aarch64/mod.rs +0 -240
  872. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/mod.rs +0 -420
  873. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/abi.rs +0 -726
  874. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/args.rs +0 -1822
  875. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/emit.rs +0 -2914
  876. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/emit_tests.rs +0 -2317
  877. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/encode.rs +0 -188
  878. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/imms.rs +0 -244
  879. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/mod.rs +0 -1823
  880. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/regs.rs +0 -231
  881. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/unwind/systemv.rs +0 -177
  882. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst/vector.rs +0 -354
  883. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst.isle +0 -2746
  884. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/inst_vector.isle +0 -224
  885. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/lower/isle.rs +0 -544
  886. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/lower.isle +0 -1012
  887. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/riscv64/mod.rs +0 -219
  888. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/abi.rs +0 -947
  889. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/inst/emit.rs +0 -3697
  890. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/inst/emit_tests.rs +0 -13397
  891. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/inst/mod.rs +0 -3409
  892. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/inst.isle +0 -5045
  893. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/lower.isle +0 -3991
  894. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/s390x/mod.rs +0 -215
  895. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/abi.rs +0 -978
  896. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/encoding/evex.rs +0 -403
  897. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/encoding/rex.rs +0 -565
  898. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/encoding/vex.rs +0 -498
  899. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/inst/args.rs +0 -2168
  900. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/inst/emit.rs +0 -3938
  901. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/inst/emit_tests.rs +0 -5669
  902. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/inst/mod.rs +0 -2763
  903. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/inst.isle +0 -5186
  904. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/lower/isle.rs +0 -1158
  905. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/lower.isle +0 -4262
  906. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/lower.rs +0 -328
  907. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isa/x64/mod.rs +0 -250
  908. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/isle_prelude.rs +0 -818
  909. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/abi.rs +0 -2410
  910. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/buffer.rs +0 -2219
  911. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/compile.rs +0 -92
  912. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/isle.rs +0 -827
  913. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/lower.rs +0 -1366
  914. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/mod.rs +0 -538
  915. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/reg.rs +0 -532
  916. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/machinst/vcode.rs +0 -1571
  917. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/prelude.isle +0 -552
  918. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/prelude_lower.isle +0 -1012
  919. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/settings.rs +0 -599
  920. data/ext/cargo-vendor/cranelift-codegen-0.96.4/src/verifier/mod.rs +0 -1881
  921. data/ext/cargo-vendor/cranelift-codegen-meta-0.96.4/.cargo-checksum.json +0 -1
  922. data/ext/cargo-vendor/cranelift-codegen-meta-0.96.4/Cargo.toml +0 -23
  923. data/ext/cargo-vendor/cranelift-codegen-meta-0.96.4/src/isa/x86.rs +0 -445
  924. data/ext/cargo-vendor/cranelift-codegen-meta-0.96.4/src/shared/settings.rs +0 -331
  925. data/ext/cargo-vendor/cranelift-codegen-shared-0.96.4/.cargo-checksum.json +0 -1
  926. data/ext/cargo-vendor/cranelift-codegen-shared-0.96.4/Cargo.toml +0 -22
  927. data/ext/cargo-vendor/cranelift-control-0.96.4/.cargo-checksum.json +0 -1
  928. data/ext/cargo-vendor/cranelift-control-0.96.4/Cargo.toml +0 -30
  929. data/ext/cargo-vendor/cranelift-control-0.96.4/src/chaos.rs +0 -78
  930. data/ext/cargo-vendor/cranelift-control-0.96.4/src/lib.rs +0 -30
  931. data/ext/cargo-vendor/cranelift-control-0.96.4/src/zero_sized.rs +0 -42
  932. data/ext/cargo-vendor/cranelift-entity-0.96.4/.cargo-checksum.json +0 -1
  933. data/ext/cargo-vendor/cranelift-entity-0.96.4/Cargo.toml +0 -35
  934. data/ext/cargo-vendor/cranelift-entity-0.96.4/src/list.rs +0 -868
  935. data/ext/cargo-vendor/cranelift-frontend-0.96.4/.cargo-checksum.json +0 -1
  936. data/ext/cargo-vendor/cranelift-frontend-0.96.4/Cargo.toml +0 -53
  937. data/ext/cargo-vendor/cranelift-isle-0.96.4/.cargo-checksum.json +0 -1
  938. data/ext/cargo-vendor/cranelift-isle-0.96.4/Cargo.toml +0 -37
  939. data/ext/cargo-vendor/cranelift-native-0.96.4/.cargo-checksum.json +0 -1
  940. data/ext/cargo-vendor/cranelift-native-0.96.4/Cargo.toml +0 -38
  941. data/ext/cargo-vendor/cranelift-native-0.96.4/src/lib.rs +0 -216
  942. data/ext/cargo-vendor/cranelift-wasm-0.96.4/.cargo-checksum.json +0 -1
  943. data/ext/cargo-vendor/cranelift-wasm-0.96.4/Cargo.toml +0 -85
  944. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/code_translator.rs +0 -3479
  945. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/environ/dummy.rs +0 -901
  946. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/environ/spec.rs +0 -807
  947. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/func_translator.rs +0 -419
  948. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/sections_translator.rs +0 -429
  949. data/ext/cargo-vendor/cranelift-wasm-0.96.4/src/translation_utils.rs +0 -108
  950. data/ext/cargo-vendor/file-per-thread-logger-0.1.6/.cargo-checksum.json +0 -1
  951. data/ext/cargo-vendor/file-per-thread-logger-0.1.6/Cargo.toml +0 -36
  952. data/ext/cargo-vendor/file-per-thread-logger-0.1.6/run-tests.sh +0 -11
  953. data/ext/cargo-vendor/file-per-thread-logger-0.1.6/src/lib.rs +0 -162
  954. data/ext/cargo-vendor/file-per-thread-logger-0.1.6/tests/test.rs +0 -267
  955. data/ext/cargo-vendor/regalloc2-0.8.1/.cargo-checksum.json +0 -1
  956. data/ext/cargo-vendor/regalloc2-0.8.1/Cargo.toml +0 -72
  957. data/ext/cargo-vendor/regalloc2-0.8.1/deny.toml +0 -28
  958. data/ext/cargo-vendor/regalloc2-0.8.1/src/checker.rs +0 -1089
  959. data/ext/cargo-vendor/regalloc2-0.8.1/src/fuzzing/func.rs +0 -673
  960. data/ext/cargo-vendor/regalloc2-0.8.1/src/index.rs +0 -188
  961. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/data_structures.rs +0 -688
  962. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/liveranges.rs +0 -1012
  963. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/merge.rs +0 -394
  964. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/mod.rs +0 -152
  965. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/moves.rs +0 -985
  966. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/process.rs +0 -1322
  967. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/requirement.rs +0 -174
  968. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/spill.rs +0 -198
  969. data/ext/cargo-vendor/regalloc2-0.8.1/src/ion/stackmap.rs +0 -74
  970. data/ext/cargo-vendor/regalloc2-0.8.1/src/lib.rs +0 -1523
  971. data/ext/cargo-vendor/regalloc2-0.8.1/src/moves.rs +0 -438
  972. data/ext/cargo-vendor/wasi-cap-std-sync-9.0.4/.cargo-checksum.json +0 -1
  973. data/ext/cargo-vendor/wasi-cap-std-sync-9.0.4/Cargo.toml +0 -89
  974. data/ext/cargo-vendor/wasi-cap-std-sync-9.0.4/src/dir.rs +0 -465
  975. data/ext/cargo-vendor/wasi-cap-std-sync-9.0.4/src/lib.rs +0 -140
  976. data/ext/cargo-vendor/wasi-common-9.0.4/.cargo-checksum.json +0 -1
  977. data/ext/cargo-vendor/wasi-common-9.0.4/Cargo.toml +0 -86
  978. data/ext/cargo-vendor/wasi-common-9.0.4/src/ctx.rs +0 -127
  979. data/ext/cargo-vendor/wasi-common-9.0.4/src/file.rs +0 -260
  980. data/ext/cargo-vendor/wasi-common-9.0.4/src/snapshots/preview_1.rs +0 -1490
  981. data/ext/cargo-vendor/wasmparser-0.103.0/.cargo-checksum.json +0 -1
  982. data/ext/cargo-vendor/wasmparser-0.103.0/Cargo.lock +0 -692
  983. data/ext/cargo-vendor/wasmparser-0.103.0/Cargo.toml +0 -54
  984. data/ext/cargo-vendor/wasmparser-0.103.0/benches/benchmark.rs +0 -350
  985. data/ext/cargo-vendor/wasmparser-0.103.0/src/binary_reader.rs +0 -1682
  986. data/ext/cargo-vendor/wasmparser-0.103.0/src/lib.rs +0 -712
  987. data/ext/cargo-vendor/wasmparser-0.103.0/src/parser.rs +0 -1496
  988. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/component/canonicals.rs +0 -95
  989. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/component/exports.rs +0 -105
  990. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/component/imports.rs +0 -109
  991. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/component/instances.rs +0 -164
  992. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/component/types.rs +0 -508
  993. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/core/producers.rs +0 -78
  994. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/core/types.rs +0 -511
  995. data/ext/cargo-vendor/wasmparser-0.103.0/src/readers/core.rs +0 -33
  996. data/ext/cargo-vendor/wasmparser-0.103.0/src/validator/component.rs +0 -2097
  997. data/ext/cargo-vendor/wasmparser-0.103.0/src/validator/core.rs +0 -1278
  998. data/ext/cargo-vendor/wasmparser-0.103.0/src/validator/operators.rs +0 -3456
  999. data/ext/cargo-vendor/wasmparser-0.103.0/src/validator/types.rs +0 -2159
  1000. data/ext/cargo-vendor/wasmparser-0.103.0/src/validator.rs +0 -1514
  1001. data/ext/cargo-vendor/wasmtime-9.0.4/.cargo-checksum.json +0 -1
  1002. data/ext/cargo-vendor/wasmtime-9.0.4/Cargo.toml +0 -183
  1003. data/ext/cargo-vendor/wasmtime-9.0.4/build.rs +0 -20
  1004. data/ext/cargo-vendor/wasmtime-9.0.4/src/component/component.rs +0 -519
  1005. data/ext/cargo-vendor/wasmtime-9.0.4/src/component/instance.rs +0 -728
  1006. data/ext/cargo-vendor/wasmtime-9.0.4/src/component/matching.rs +0 -112
  1007. data/ext/cargo-vendor/wasmtime-9.0.4/src/component/mod.rs +0 -313
  1008. data/ext/cargo-vendor/wasmtime-9.0.4/src/config.rs +0 -2036
  1009. data/ext/cargo-vendor/wasmtime-9.0.4/src/engine/serialization.rs +0 -613
  1010. data/ext/cargo-vendor/wasmtime-9.0.4/src/engine.rs +0 -729
  1011. data/ext/cargo-vendor/wasmtime-9.0.4/src/externals.rs +0 -762
  1012. data/ext/cargo-vendor/wasmtime-9.0.4/src/func/typed.rs +0 -638
  1013. data/ext/cargo-vendor/wasmtime-9.0.4/src/func.rs +0 -2385
  1014. data/ext/cargo-vendor/wasmtime-9.0.4/src/instance.rs +0 -905
  1015. data/ext/cargo-vendor/wasmtime-9.0.4/src/lib.rs +0 -481
  1016. data/ext/cargo-vendor/wasmtime-9.0.4/src/linker.rs +0 -1479
  1017. data/ext/cargo-vendor/wasmtime-9.0.4/src/memory.rs +0 -948
  1018. data/ext/cargo-vendor/wasmtime-9.0.4/src/module.rs +0 -1542
  1019. data/ext/cargo-vendor/wasmtime-9.0.4/src/ref.rs +0 -108
  1020. data/ext/cargo-vendor/wasmtime-9.0.4/src/store/context.rs +0 -243
  1021. data/ext/cargo-vendor/wasmtime-9.0.4/src/store/func_refs.rs +0 -110
  1022. data/ext/cargo-vendor/wasmtime-9.0.4/src/store.rs +0 -2059
  1023. data/ext/cargo-vendor/wasmtime-9.0.4/src/trampoline/func.rs +0 -171
  1024. data/ext/cargo-vendor/wasmtime-9.0.4/src/trampoline/global.rs +0 -71
  1025. data/ext/cargo-vendor/wasmtime-9.0.4/src/types/matching.rs +0 -254
  1026. data/ext/cargo-vendor/wasmtime-9.0.4/src/types.rs +0 -551
  1027. data/ext/cargo-vendor/wasmtime-9.0.4/src/values.rs +0 -290
  1028. data/ext/cargo-vendor/wasmtime-asm-macros-9.0.4/.cargo-checksum.json +0 -1
  1029. data/ext/cargo-vendor/wasmtime-asm-macros-9.0.4/Cargo.toml +0 -22
  1030. data/ext/cargo-vendor/wasmtime-cache-9.0.4/.cargo-checksum.json +0 -1
  1031. data/ext/cargo-vendor/wasmtime-cache-9.0.4/Cargo.toml +0 -73
  1032. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/.cargo-checksum.json +0 -1
  1033. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/Cargo.toml +0 -58
  1034. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/src/bindgen.rs +0 -316
  1035. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/char.wit +0 -11
  1036. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/conventions.wit +0 -38
  1037. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/direct-import.wit +0 -3
  1038. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/empty.wit +0 -1
  1039. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/flags.wit +0 -53
  1040. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/floats.wit +0 -11
  1041. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/function-new.wit +0 -3
  1042. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/integers.wit +0 -38
  1043. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/lists.wit +0 -83
  1044. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/many-arguments.wit +0 -50
  1045. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/multi-return.wit +0 -12
  1046. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/records.wit +0 -59
  1047. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/rename.wit +0 -14
  1048. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/share-types.wit +0 -19
  1049. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/simple-functions.wit +0 -15
  1050. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/simple-lists.wit +0 -11
  1051. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/simple-wasi.wit +0 -21
  1052. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/small-anonymous.wit +0 -13
  1053. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/smoke-default.wit +0 -3
  1054. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/smoke-export.wit +0 -5
  1055. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/smoke.wit +0 -5
  1056. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/strings.wit +0 -10
  1057. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/unions.wit +0 -64
  1058. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/use-paths.wit +0 -27
  1059. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/variants.wit +0 -145
  1060. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen/worlds-with-types.wit +0 -14
  1061. data/ext/cargo-vendor/wasmtime-component-macro-9.0.4/tests/codegen.rs +0 -30
  1062. data/ext/cargo-vendor/wasmtime-component-util-9.0.4/.cargo-checksum.json +0 -1
  1063. data/ext/cargo-vendor/wasmtime-component-util-9.0.4/Cargo.toml +0 -25
  1064. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/.cargo-checksum.json +0 -1
  1065. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/Cargo.toml +0 -90
  1066. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/src/compiler.rs +0 -1200
  1067. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/src/debug/transform/simulate.rs +0 -411
  1068. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/src/func_environ.rs +0 -2162
  1069. data/ext/cargo-vendor/wasmtime-cranelift-9.0.4/src/lib.rs +0 -177
  1070. data/ext/cargo-vendor/wasmtime-cranelift-shared-9.0.4/.cargo-checksum.json +0 -1
  1071. data/ext/cargo-vendor/wasmtime-cranelift-shared-9.0.4/Cargo.toml +0 -57
  1072. data/ext/cargo-vendor/wasmtime-cranelift-shared-9.0.4/src/lib.rs +0 -119
  1073. data/ext/cargo-vendor/wasmtime-environ-9.0.4/.cargo-checksum.json +0 -1
  1074. data/ext/cargo-vendor/wasmtime-environ-9.0.4/Cargo.lock +0 -735
  1075. data/ext/cargo-vendor/wasmtime-environ-9.0.4/Cargo.toml +0 -116
  1076. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/component/compiler.rs +0 -84
  1077. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/component/translate/inline.rs +0 -1064
  1078. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/component/translate.rs +0 -1066
  1079. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/component/types.rs +0 -1903
  1080. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/fact.rs +0 -622
  1081. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/module.rs +0 -1043
  1082. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/module_environ.rs +0 -841
  1083. data/ext/cargo-vendor/wasmtime-environ-9.0.4/src/trap_encoding.rs +0 -234
  1084. data/ext/cargo-vendor/wasmtime-fiber-9.0.4/.cargo-checksum.json +0 -1
  1085. data/ext/cargo-vendor/wasmtime-fiber-9.0.4/Cargo.toml +0 -46
  1086. data/ext/cargo-vendor/wasmtime-fiber-9.0.4/src/lib.rs +0 -293
  1087. data/ext/cargo-vendor/wasmtime-fiber-9.0.4/src/unix.rs +0 -199
  1088. data/ext/cargo-vendor/wasmtime-fiber-9.0.4/src/windows.rs +0 -156
  1089. data/ext/cargo-vendor/wasmtime-jit-9.0.4/.cargo-checksum.json +0 -1
  1090. data/ext/cargo-vendor/wasmtime-jit-9.0.4/Cargo.toml +0 -100
  1091. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/instantiate.rs +0 -786
  1092. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/lib.rs +0 -39
  1093. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/jitdump_disabled.rs +0 -32
  1094. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/jitdump_linux.rs +0 -444
  1095. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/perfmap_disabled.rs +0 -28
  1096. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/perfmap_linux.rs +0 -104
  1097. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/vtune.rs +0 -147
  1098. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling/vtune_disabled.rs +0 -32
  1099. data/ext/cargo-vendor/wasmtime-jit-9.0.4/src/profiling.rs +0 -74
  1100. data/ext/cargo-vendor/wasmtime-jit-debug-9.0.4/.cargo-checksum.json +0 -1
  1101. data/ext/cargo-vendor/wasmtime-jit-debug-9.0.4/Cargo.toml +0 -55
  1102. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-9.0.4/.cargo-checksum.json +0 -1
  1103. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-9.0.4/Cargo.toml +0 -37
  1104. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/.cargo-checksum.json +0 -1
  1105. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/Cargo.toml +0 -107
  1106. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/component.rs +0 -724
  1107. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/cow.rs +0 -1063
  1108. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/debug_builtins.rs +0 -56
  1109. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/externref.rs +0 -1078
  1110. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/instance/allocator/pooling.rs +0 -1371
  1111. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/instance/allocator.rs +0 -528
  1112. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/instance.rs +0 -1267
  1113. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/lib.rs +0 -286
  1114. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/libcalls.rs +0 -597
  1115. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/memory.rs +0 -945
  1116. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/mmap/miri.rs +0 -93
  1117. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/mmap/unix.rs +0 -147
  1118. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/mmap/windows.rs +0 -207
  1119. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/table.rs +0 -573
  1120. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/traphandlers/unix.rs +0 -387
  1121. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/traphandlers.rs +0 -664
  1122. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/vmcontext/vm_host_func_context.rs +0 -147
  1123. data/ext/cargo-vendor/wasmtime-runtime-9.0.4/src/vmcontext.rs +0 -1244
  1124. data/ext/cargo-vendor/wasmtime-types-9.0.4/.cargo-checksum.json +0 -1
  1125. data/ext/cargo-vendor/wasmtime-types-9.0.4/Cargo.toml +0 -34
  1126. data/ext/cargo-vendor/wasmtime-types-9.0.4/src/lib.rs +0 -413
  1127. data/ext/cargo-vendor/wasmtime-wasi-9.0.4/.cargo-checksum.json +0 -1
  1128. data/ext/cargo-vendor/wasmtime-wasi-9.0.4/Cargo.toml +0 -67
  1129. data/ext/cargo-vendor/wasmtime-wasi-9.0.4/src/lib.rs +0 -128
  1130. data/ext/cargo-vendor/wasmtime-winch-9.0.4/.cargo-checksum.json +0 -1
  1131. data/ext/cargo-vendor/wasmtime-winch-9.0.4/Cargo.toml +0 -66
  1132. data/ext/cargo-vendor/wasmtime-winch-9.0.4/src/compiler.rs +0 -191
  1133. data/ext/cargo-vendor/wasmtime-wit-bindgen-9.0.4/.cargo-checksum.json +0 -1
  1134. data/ext/cargo-vendor/wasmtime-wit-bindgen-9.0.4/Cargo.toml +0 -29
  1135. data/ext/cargo-vendor/wasmtime-wit-bindgen-9.0.4/src/lib.rs +0 -1488
  1136. data/ext/cargo-vendor/wasmtime-wit-bindgen-9.0.4/src/types.rs +0 -178
  1137. data/ext/cargo-vendor/wiggle-9.0.4/.cargo-checksum.json +0 -1
  1138. data/ext/cargo-vendor/wiggle-9.0.4/Cargo.toml +0 -106
  1139. data/ext/cargo-vendor/wiggle-9.0.4/README.md +0 -18
  1140. data/ext/cargo-vendor/wiggle-generate-9.0.4/.cargo-checksum.json +0 -1
  1141. data/ext/cargo-vendor/wiggle-generate-9.0.4/Cargo.toml +0 -58
  1142. data/ext/cargo-vendor/wiggle-macro-9.0.4/.cargo-checksum.json +0 -1
  1143. data/ext/cargo-vendor/wiggle-macro-9.0.4/Cargo.toml +0 -55
  1144. data/ext/cargo-vendor/wiggle-macro-9.0.4/src/lib.rs +0 -210
  1145. data/ext/cargo-vendor/winch-codegen-0.7.4/.cargo-checksum.json +0 -1
  1146. data/ext/cargo-vendor/winch-codegen-0.7.4/Cargo.toml +0 -59
  1147. data/ext/cargo-vendor/winch-codegen-0.7.4/src/abi/local.rs +0 -69
  1148. data/ext/cargo-vendor/winch-codegen-0.7.4/src/abi/mod.rs +0 -223
  1149. data/ext/cargo-vendor/winch-codegen-0.7.4/src/codegen/call.rs +0 -215
  1150. data/ext/cargo-vendor/winch-codegen-0.7.4/src/codegen/context.rs +0 -259
  1151. data/ext/cargo-vendor/winch-codegen-0.7.4/src/codegen/env.rs +0 -19
  1152. data/ext/cargo-vendor/winch-codegen-0.7.4/src/codegen/mod.rs +0 -183
  1153. data/ext/cargo-vendor/winch-codegen-0.7.4/src/frame/mod.rs +0 -166
  1154. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/aarch64/abi.rs +0 -221
  1155. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/aarch64/asm.rs +0 -244
  1156. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/aarch64/masm.rs +0 -221
  1157. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/aarch64/mod.rs +0 -122
  1158. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/aarch64/regs.rs +0 -160
  1159. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/mod.rs +0 -202
  1160. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/abi.rs +0 -337
  1161. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/address.rs +0 -17
  1162. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/asm.rs +0 -499
  1163. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/masm.rs +0 -267
  1164. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/mod.rs +0 -135
  1165. data/ext/cargo-vendor/winch-codegen-0.7.4/src/isa/x64/regs.rs +0 -178
  1166. data/ext/cargo-vendor/winch-codegen-0.7.4/src/lib.rs +0 -20
  1167. data/ext/cargo-vendor/winch-codegen-0.7.4/src/masm.rs +0 -213
  1168. data/ext/cargo-vendor/winch-codegen-0.7.4/src/regalloc.rs +0 -61
  1169. data/ext/cargo-vendor/winch-codegen-0.7.4/src/stack.rs +0 -230
  1170. data/ext/cargo-vendor/winch-codegen-0.7.4/src/trampoline.rs +0 -206
  1171. data/ext/cargo-vendor/winch-codegen-0.7.4/src/visitor.rs +0 -215
  1172. data/ext/cargo-vendor/winch-environ-0.7.4/.cargo-checksum.json +0 -1
  1173. data/ext/cargo-vendor/winch-environ-0.7.4/Cargo.toml +0 -28
  1174. data/ext/cargo-vendor/winch-environ-0.7.4/src/lib.rs +0 -41
  1175. data/ext/cargo-vendor/wit-parser-0.7.1/.cargo-checksum.json +0 -1
  1176. data/ext/cargo-vendor/wit-parser-0.7.1/Cargo.toml +0 -59
  1177. data/ext/cargo-vendor/wit-parser-0.7.1/src/ast/lex.rs +0 -662
  1178. data/ext/cargo-vendor/wit-parser-0.7.1/src/ast/resolve.rs +0 -1072
  1179. data/ext/cargo-vendor/wit-parser-0.7.1/src/ast.rs +0 -1099
  1180. data/ext/cargo-vendor/wit-parser-0.7.1/src/lib.rs +0 -617
  1181. data/ext/cargo-vendor/wit-parser-0.7.1/src/live.rs +0 -123
  1182. data/ext/cargo-vendor/wit-parser-0.7.1/src/resolve.rs +0 -1478
  1183. data/ext/cargo-vendor/wit-parser-0.7.1/tests/all.rs +0 -168
  1184. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/comments.wit +0 -23
  1185. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/disambiguate-diamond/shared1.wit +0 -3
  1186. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/disambiguate-diamond/shared2.wit +0 -3
  1187. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/disambiguate-diamond/world.wit +0 -11
  1188. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/embedded.wit.md +0 -32
  1189. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/another-pkg/other-doc.wit +0 -1
  1190. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/corp/saas.wit +0 -2
  1191. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/different-pkg/the-doc.wit +0 -1
  1192. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/foreign-pkg/the-doc.wit +0 -3
  1193. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/some-pkg/some-doc.wit +0 -11
  1194. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/wasi/clocks.wit +0 -3
  1195. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/deps/wasi/filesystem.wit +0 -5
  1196. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/foreign-deps/root.wit +0 -31
  1197. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/functions.wit +0 -12
  1198. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/multi-file/bar.wit +0 -19
  1199. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/multi-file/foo.wit +0 -15
  1200. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/alias-no-type.wit.result +0 -5
  1201. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-diamond/a.wit +0 -9
  1202. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-diamond/b.wit +0 -9
  1203. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-diamond/join.wit +0 -4
  1204. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-diamond.wit.result +0 -8
  1205. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-function.wit +0 -5
  1206. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-function.wit.result +0 -5
  1207. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-function2.wit +0 -5
  1208. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-function2.wit.result +0 -5
  1209. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg1/root.wit +0 -3
  1210. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg1.wit.result +0 -5
  1211. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg2/root.wit +0 -3
  1212. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg2.wit.result +0 -5
  1213. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg3/deps/bar/baz.wit +0 -0
  1214. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg3/root.wit +0 -3
  1215. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg3.wit.result +0 -5
  1216. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg4/deps/bar/baz.wit +0 -3
  1217. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg4/root.wit +0 -3
  1218. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg4.wit.result +0 -5
  1219. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg5/deps/bar/baz.wit +0 -2
  1220. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg5/root.wit +0 -3
  1221. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg5.wit.result +0 -5
  1222. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg6/deps/bar/baz.wit +0 -0
  1223. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg6/root.wit +0 -3
  1224. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-pkg6.wit.result +0 -5
  1225. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-world-type1.wit +0 -4
  1226. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-world-type1.wit.result +0 -5
  1227. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-world-type2.wit +0 -9
  1228. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/bad-world-type2.wit.result +0 -5
  1229. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle.wit +0 -5
  1230. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle.wit.result +0 -5
  1231. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle2.wit +0 -6
  1232. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle2.wit.result +0 -5
  1233. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle3.wit +0 -6
  1234. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle3.wit.result +0 -5
  1235. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle4.wit +0 -6
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  1237. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/cycle5.wit +0 -6
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  1239. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/default-interface1.wit +0 -3
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  1241. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/default-world1.wit +0 -3
  1242. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/default-world1.wit.result +0 -5
  1243. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/duplicate-functions.wit +0 -6
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  1247. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/duplicate-type.wit +0 -6
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  1249. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/empty-enum.wit +0 -5
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  1253. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/empty-variant1.wit +0 -5
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  1257. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/import-export-overlap2.wit +0 -4
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  1259. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/parse-fail/import-export-overlap3.wit +0 -11
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,3658 +0,0 @@
1
- //! AArch64 ISA: binary code emission.
2
-
3
- use cranelift_control::ControlPlane;
4
- use regalloc2::Allocation;
5
-
6
- use crate::binemit::{Reloc, StackMap};
7
- use crate::ir::{types::*, RelSourceLoc};
8
- use crate::ir::{LibCall, MemFlags, TrapCode};
9
- use crate::isa::aarch64::inst::*;
10
- use crate::machinst::{ty_bits, Reg, RegClass, Writable};
11
- use crate::trace;
12
- use core::convert::TryFrom;
13
-
14
- /// Memory addressing mode finalization: convert "special" modes (e.g.,
15
- /// generic arbitrary stack offset) into real addressing modes, possibly by
16
- /// emitting some helper instructions that come immediately before the use
17
- /// of this amode.
18
- pub fn mem_finalize(
19
- sink: Option<&mut MachBuffer<Inst>>,
20
- mem: &AMode,
21
- state: &EmitState,
22
- ) -> (SmallVec<[Inst; 4]>, AMode) {
23
- match mem {
24
- &AMode::RegOffset { off, ty, .. }
25
- | &AMode::SPOffset { off, ty }
26
- | &AMode::FPOffset { off, ty }
27
- | &AMode::NominalSPOffset { off, ty } => {
28
- let basereg = match mem {
29
- &AMode::RegOffset { rn, .. } => rn,
30
- &AMode::SPOffset { .. } | &AMode::NominalSPOffset { .. } => stack_reg(),
31
- &AMode::FPOffset { .. } => fp_reg(),
32
- _ => unreachable!(),
33
- };
34
- let adj = match mem {
35
- &AMode::NominalSPOffset { .. } => {
36
- trace!(
37
- "mem_finalize: nominal SP offset {} + adj {} -> {}",
38
- off,
39
- state.virtual_sp_offset,
40
- off + state.virtual_sp_offset
41
- );
42
- state.virtual_sp_offset
43
- }
44
- _ => 0,
45
- };
46
- let off = off + adj;
47
-
48
- if let Some(simm9) = SImm9::maybe_from_i64(off) {
49
- let mem = AMode::Unscaled { rn: basereg, simm9 };
50
- (smallvec![], mem)
51
- } else if let Some(uimm12) = UImm12Scaled::maybe_from_i64(off, ty) {
52
- let mem = AMode::UnsignedOffset {
53
- rn: basereg,
54
- uimm12,
55
- };
56
- (smallvec![], mem)
57
- } else {
58
- let tmp = writable_spilltmp_reg();
59
- (
60
- Inst::load_constant(tmp, off as u64, &mut |_| tmp),
61
- AMode::RegExtended {
62
- rn: basereg,
63
- rm: tmp.to_reg(),
64
- extendop: ExtendOp::SXTX,
65
- },
66
- )
67
- }
68
- }
69
-
70
- AMode::Const { addr } => {
71
- let sink = match sink {
72
- Some(sink) => sink,
73
- None => return (smallvec![], mem.clone()),
74
- };
75
- let label = sink.get_label_for_constant(*addr);
76
- let label = MemLabel::Mach(label);
77
- (smallvec![], AMode::Label { label })
78
- }
79
-
80
- _ => (smallvec![], mem.clone()),
81
- }
82
- }
83
-
84
- //=============================================================================
85
- // Instructions and subcomponents: emission
86
-
87
- pub(crate) fn machreg_to_gpr(m: Reg) -> u32 {
88
- assert_eq!(m.class(), RegClass::Int);
89
- u32::try_from(m.to_real_reg().unwrap().hw_enc() & 31).unwrap()
90
- }
91
-
92
- pub(crate) fn machreg_to_vec(m: Reg) -> u32 {
93
- assert_eq!(m.class(), RegClass::Float);
94
- u32::try_from(m.to_real_reg().unwrap().hw_enc()).unwrap()
95
- }
96
-
97
- fn machreg_to_gpr_or_vec(m: Reg) -> u32 {
98
- u32::try_from(m.to_real_reg().unwrap().hw_enc() & 31).unwrap()
99
- }
100
-
101
- pub(crate) fn enc_arith_rrr(
102
- bits_31_21: u32,
103
- bits_15_10: u32,
104
- rd: Writable<Reg>,
105
- rn: Reg,
106
- rm: Reg,
107
- ) -> u32 {
108
- (bits_31_21 << 21)
109
- | (bits_15_10 << 10)
110
- | machreg_to_gpr(rd.to_reg())
111
- | (machreg_to_gpr(rn) << 5)
112
- | (machreg_to_gpr(rm) << 16)
113
- }
114
-
115
- fn enc_arith_rr_imm12(
116
- bits_31_24: u32,
117
- immshift: u32,
118
- imm12: u32,
119
- rn: Reg,
120
- rd: Writable<Reg>,
121
- ) -> u32 {
122
- (bits_31_24 << 24)
123
- | (immshift << 22)
124
- | (imm12 << 10)
125
- | (machreg_to_gpr(rn) << 5)
126
- | machreg_to_gpr(rd.to_reg())
127
- }
128
-
129
- fn enc_arith_rr_imml(bits_31_23: u32, imm_bits: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
130
- (bits_31_23 << 23) | (imm_bits << 10) | (machreg_to_gpr(rn) << 5) | machreg_to_gpr(rd.to_reg())
131
- }
132
-
133
- fn enc_arith_rrrr(top11: u32, rm: Reg, bit15: u32, ra: Reg, rn: Reg, rd: Writable<Reg>) -> u32 {
134
- (top11 << 21)
135
- | (machreg_to_gpr(rm) << 16)
136
- | (bit15 << 15)
137
- | (machreg_to_gpr(ra) << 10)
138
- | (machreg_to_gpr(rn) << 5)
139
- | machreg_to_gpr(rd.to_reg())
140
- }
141
-
142
- fn enc_jump26(op_31_26: u32, off_26_0: u32) -> u32 {
143
- assert!(off_26_0 < (1 << 26));
144
- (op_31_26 << 26) | off_26_0
145
- }
146
-
147
- fn enc_cmpbr(op_31_24: u32, off_18_0: u32, reg: Reg) -> u32 {
148
- assert!(off_18_0 < (1 << 19));
149
- (op_31_24 << 24) | (off_18_0 << 5) | machreg_to_gpr(reg)
150
- }
151
-
152
- fn enc_cbr(op_31_24: u32, off_18_0: u32, op_4: u32, cond: u32) -> u32 {
153
- assert!(off_18_0 < (1 << 19));
154
- assert!(cond < (1 << 4));
155
- (op_31_24 << 24) | (off_18_0 << 5) | (op_4 << 4) | cond
156
- }
157
-
158
- fn enc_conditional_br(
159
- taken: BranchTarget,
160
- kind: CondBrKind,
161
- allocs: &mut AllocationConsumer<'_>,
162
- ) -> u32 {
163
- match kind {
164
- CondBrKind::Zero(reg) => {
165
- let reg = allocs.next(reg);
166
- enc_cmpbr(0b1_011010_0, taken.as_offset19_or_zero(), reg)
167
- }
168
- CondBrKind::NotZero(reg) => {
169
- let reg = allocs.next(reg);
170
- enc_cmpbr(0b1_011010_1, taken.as_offset19_or_zero(), reg)
171
- }
172
- CondBrKind::Cond(c) => enc_cbr(0b01010100, taken.as_offset19_or_zero(), 0b0, c.bits()),
173
- }
174
- }
175
-
176
- fn enc_move_wide(op: MoveWideOp, rd: Writable<Reg>, imm: MoveWideConst, size: OperandSize) -> u32 {
177
- assert!(imm.shift <= 0b11);
178
- let op = match op {
179
- MoveWideOp::MovN => 0b00,
180
- MoveWideOp::MovZ => 0b10,
181
- };
182
- 0x12800000
183
- | size.sf_bit() << 31
184
- | op << 29
185
- | u32::from(imm.shift) << 21
186
- | u32::from(imm.bits) << 5
187
- | machreg_to_gpr(rd.to_reg())
188
- }
189
-
190
- fn enc_movk(rd: Writable<Reg>, imm: MoveWideConst, size: OperandSize) -> u32 {
191
- assert!(imm.shift <= 0b11);
192
- 0x72800000
193
- | size.sf_bit() << 31
194
- | u32::from(imm.shift) << 21
195
- | u32::from(imm.bits) << 5
196
- | machreg_to_gpr(rd.to_reg())
197
- }
198
-
199
- fn enc_ldst_pair(op_31_22: u32, simm7: SImm7Scaled, rn: Reg, rt: Reg, rt2: Reg) -> u32 {
200
- (op_31_22 << 22)
201
- | (simm7.bits() << 15)
202
- | (machreg_to_gpr(rt2) << 10)
203
- | (machreg_to_gpr(rn) << 5)
204
- | machreg_to_gpr(rt)
205
- }
206
-
207
- fn enc_ldst_simm9(op_31_22: u32, simm9: SImm9, op_11_10: u32, rn: Reg, rd: Reg) -> u32 {
208
- (op_31_22 << 22)
209
- | (simm9.bits() << 12)
210
- | (op_11_10 << 10)
211
- | (machreg_to_gpr(rn) << 5)
212
- | machreg_to_gpr_or_vec(rd)
213
- }
214
-
215
- fn enc_ldst_uimm12(op_31_22: u32, uimm12: UImm12Scaled, rn: Reg, rd: Reg) -> u32 {
216
- (op_31_22 << 22)
217
- | (0b1 << 24)
218
- | (uimm12.bits() << 10)
219
- | (machreg_to_gpr(rn) << 5)
220
- | machreg_to_gpr_or_vec(rd)
221
- }
222
-
223
- fn enc_ldst_reg(
224
- op_31_22: u32,
225
- rn: Reg,
226
- rm: Reg,
227
- s_bit: bool,
228
- extendop: Option<ExtendOp>,
229
- rd: Reg,
230
- ) -> u32 {
231
- let s_bit = if s_bit { 1 } else { 0 };
232
- let extend_bits = match extendop {
233
- Some(ExtendOp::UXTW) => 0b010,
234
- Some(ExtendOp::SXTW) => 0b110,
235
- Some(ExtendOp::SXTX) => 0b111,
236
- None => 0b011, // LSL
237
- _ => panic!("bad extend mode for ld/st AMode"),
238
- };
239
- (op_31_22 << 22)
240
- | (1 << 21)
241
- | (machreg_to_gpr(rm) << 16)
242
- | (extend_bits << 13)
243
- | (s_bit << 12)
244
- | (0b10 << 10)
245
- | (machreg_to_gpr(rn) << 5)
246
- | machreg_to_gpr_or_vec(rd)
247
- }
248
-
249
- pub(crate) fn enc_ldst_imm19(op_31_24: u32, imm19: u32, rd: Reg) -> u32 {
250
- (op_31_24 << 24) | (imm19 << 5) | machreg_to_gpr_or_vec(rd)
251
- }
252
-
253
- fn enc_ldst_vec(q: u32, size: u32, rn: Reg, rt: Writable<Reg>) -> u32 {
254
- debug_assert_eq!(q & 0b1, q);
255
- debug_assert_eq!(size & 0b11, size);
256
- 0b0_0_0011010_10_00000_110_0_00_00000_00000
257
- | q << 30
258
- | size << 10
259
- | machreg_to_gpr(rn) << 5
260
- | machreg_to_vec(rt.to_reg())
261
- }
262
-
263
- fn enc_ldst_vec_pair(
264
- opc: u32,
265
- amode: u32,
266
- is_load: bool,
267
- simm7: SImm7Scaled,
268
- rn: Reg,
269
- rt: Reg,
270
- rt2: Reg,
271
- ) -> u32 {
272
- debug_assert_eq!(opc & 0b11, opc);
273
- debug_assert_eq!(amode & 0b11, amode);
274
-
275
- 0b00_10110_00_0_0000000_00000_00000_00000
276
- | opc << 30
277
- | amode << 23
278
- | (is_load as u32) << 22
279
- | simm7.bits() << 15
280
- | machreg_to_vec(rt2) << 10
281
- | machreg_to_gpr(rn) << 5
282
- | machreg_to_vec(rt)
283
- }
284
-
285
- fn enc_vec_rrr(top11: u32, rm: Reg, bit15_10: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
286
- (top11 << 21)
287
- | (machreg_to_vec(rm) << 16)
288
- | (bit15_10 << 10)
289
- | (machreg_to_vec(rn) << 5)
290
- | machreg_to_vec(rd.to_reg())
291
- }
292
-
293
- fn enc_vec_rrr_long(
294
- q: u32,
295
- u: u32,
296
- size: u32,
297
- bit14: u32,
298
- rm: Reg,
299
- rn: Reg,
300
- rd: Writable<Reg>,
301
- ) -> u32 {
302
- debug_assert_eq!(q & 0b1, q);
303
- debug_assert_eq!(u & 0b1, u);
304
- debug_assert_eq!(size & 0b11, size);
305
- debug_assert_eq!(bit14 & 0b1, bit14);
306
-
307
- 0b0_0_0_01110_00_1_00000_100000_00000_00000
308
- | q << 30
309
- | u << 29
310
- | size << 22
311
- | bit14 << 14
312
- | (machreg_to_vec(rm) << 16)
313
- | (machreg_to_vec(rn) << 5)
314
- | machreg_to_vec(rd.to_reg())
315
- }
316
-
317
- fn enc_bit_rr(size: u32, opcode2: u32, opcode1: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
318
- (0b01011010110 << 21)
319
- | size << 31
320
- | opcode2 << 16
321
- | opcode1 << 10
322
- | machreg_to_gpr(rn) << 5
323
- | machreg_to_gpr(rd.to_reg())
324
- }
325
-
326
- pub(crate) fn enc_br(rn: Reg) -> u32 {
327
- 0b1101011_0000_11111_000000_00000_00000 | (machreg_to_gpr(rn) << 5)
328
- }
329
-
330
- pub(crate) fn enc_adr_inst(opcode: u32, off: i32, rd: Writable<Reg>) -> u32 {
331
- let off = u32::try_from(off).unwrap();
332
- let immlo = off & 3;
333
- let immhi = (off >> 2) & ((1 << 19) - 1);
334
- opcode | (immlo << 29) | (immhi << 5) | machreg_to_gpr(rd.to_reg())
335
- }
336
-
337
- pub(crate) fn enc_adr(off: i32, rd: Writable<Reg>) -> u32 {
338
- let opcode = 0b00010000 << 24;
339
- enc_adr_inst(opcode, off, rd)
340
- }
341
-
342
- pub(crate) fn enc_adrp(off: i32, rd: Writable<Reg>) -> u32 {
343
- let opcode = 0b10010000 << 24;
344
- enc_adr_inst(opcode, off, rd)
345
- }
346
-
347
- fn enc_csel(rd: Writable<Reg>, rn: Reg, rm: Reg, cond: Cond, op: u32, o2: u32) -> u32 {
348
- debug_assert_eq!(op & 0b1, op);
349
- debug_assert_eq!(o2 & 0b1, o2);
350
- 0b100_11010100_00000_0000_00_00000_00000
351
- | (op << 30)
352
- | (machreg_to_gpr(rm) << 16)
353
- | (cond.bits() << 12)
354
- | (o2 << 10)
355
- | (machreg_to_gpr(rn) << 5)
356
- | machreg_to_gpr(rd.to_reg())
357
- }
358
-
359
- fn enc_fcsel(rd: Writable<Reg>, rn: Reg, rm: Reg, cond: Cond, size: ScalarSize) -> u32 {
360
- 0b000_11110_00_1_00000_0000_11_00000_00000
361
- | (size.ftype() << 22)
362
- | (machreg_to_vec(rm) << 16)
363
- | (machreg_to_vec(rn) << 5)
364
- | machreg_to_vec(rd.to_reg())
365
- | (cond.bits() << 12)
366
- }
367
-
368
- fn enc_ccmp(size: OperandSize, rn: Reg, rm: Reg, nzcv: NZCV, cond: Cond) -> u32 {
369
- 0b0_1_1_11010010_00000_0000_00_00000_0_0000
370
- | size.sf_bit() << 31
371
- | machreg_to_gpr(rm) << 16
372
- | cond.bits() << 12
373
- | machreg_to_gpr(rn) << 5
374
- | nzcv.bits()
375
- }
376
-
377
- fn enc_ccmp_imm(size: OperandSize, rn: Reg, imm: UImm5, nzcv: NZCV, cond: Cond) -> u32 {
378
- 0b0_1_1_11010010_00000_0000_10_00000_0_0000
379
- | size.sf_bit() << 31
380
- | imm.bits() << 16
381
- | cond.bits() << 12
382
- | machreg_to_gpr(rn) << 5
383
- | nzcv.bits()
384
- }
385
-
386
- fn enc_bfm(opc: u8, size: OperandSize, rd: Writable<Reg>, rn: Reg, immr: u8, imms: u8) -> u32 {
387
- match size {
388
- OperandSize::Size64 => {
389
- debug_assert!(immr <= 63);
390
- debug_assert!(imms <= 63);
391
- }
392
- OperandSize::Size32 => {
393
- debug_assert!(immr <= 31);
394
- debug_assert!(imms <= 31);
395
- }
396
- }
397
- debug_assert_eq!(opc & 0b11, opc);
398
- let n_bit = size.sf_bit();
399
- 0b0_00_100110_0_000000_000000_00000_00000
400
- | size.sf_bit() << 31
401
- | u32::from(opc) << 29
402
- | n_bit << 22
403
- | u32::from(immr) << 16
404
- | u32::from(imms) << 10
405
- | machreg_to_gpr(rn) << 5
406
- | machreg_to_gpr(rd.to_reg())
407
- }
408
-
409
- fn enc_vecmov(is_16b: bool, rd: Writable<Reg>, rn: Reg) -> u32 {
410
- 0b00001110_101_00000_00011_1_00000_00000
411
- | ((is_16b as u32) << 30)
412
- | machreg_to_vec(rd.to_reg())
413
- | (machreg_to_vec(rn) << 16)
414
- | (machreg_to_vec(rn) << 5)
415
- }
416
-
417
- fn enc_fpurr(top22: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
418
- (top22 << 10) | (machreg_to_vec(rn) << 5) | machreg_to_vec(rd.to_reg())
419
- }
420
-
421
- fn enc_fpurrr(top22: u32, rd: Writable<Reg>, rn: Reg, rm: Reg) -> u32 {
422
- (top22 << 10)
423
- | (machreg_to_vec(rm) << 16)
424
- | (machreg_to_vec(rn) << 5)
425
- | machreg_to_vec(rd.to_reg())
426
- }
427
-
428
- fn enc_fpurrrr(top17: u32, rd: Writable<Reg>, rn: Reg, rm: Reg, ra: Reg) -> u32 {
429
- (top17 << 15)
430
- | (machreg_to_vec(rm) << 16)
431
- | (machreg_to_vec(ra) << 10)
432
- | (machreg_to_vec(rn) << 5)
433
- | machreg_to_vec(rd.to_reg())
434
- }
435
-
436
- fn enc_fcmp(size: ScalarSize, rn: Reg, rm: Reg) -> u32 {
437
- 0b000_11110_00_1_00000_00_1000_00000_00000
438
- | (size.ftype() << 22)
439
- | (machreg_to_vec(rm) << 16)
440
- | (machreg_to_vec(rn) << 5)
441
- }
442
-
443
- fn enc_fputoint(top16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
444
- (top16 << 16) | (machreg_to_vec(rn) << 5) | machreg_to_gpr(rd.to_reg())
445
- }
446
-
447
- fn enc_inttofpu(top16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
448
- (top16 << 16) | (machreg_to_gpr(rn) << 5) | machreg_to_vec(rd.to_reg())
449
- }
450
-
451
- fn enc_fround(top22: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
452
- (top22 << 10) | (machreg_to_vec(rn) << 5) | machreg_to_vec(rd.to_reg())
453
- }
454
-
455
- fn enc_vec_rr_misc(qu: u32, size: u32, bits_12_16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
456
- debug_assert_eq!(qu & 0b11, qu);
457
- debug_assert_eq!(size & 0b11, size);
458
- debug_assert_eq!(bits_12_16 & 0b11111, bits_12_16);
459
- let bits = 0b0_00_01110_00_10000_00000_10_00000_00000;
460
- bits | qu << 29
461
- | size << 22
462
- | bits_12_16 << 12
463
- | machreg_to_vec(rn) << 5
464
- | machreg_to_vec(rd.to_reg())
465
- }
466
-
467
- fn enc_vec_rr_pair(bits_12_16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
468
- debug_assert_eq!(bits_12_16 & 0b11111, bits_12_16);
469
-
470
- 0b010_11110_11_11000_11011_10_00000_00000
471
- | bits_12_16 << 12
472
- | machreg_to_vec(rn) << 5
473
- | machreg_to_vec(rd.to_reg())
474
- }
475
-
476
- fn enc_vec_rr_pair_long(u: u32, enc_size: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
477
- debug_assert_eq!(u & 0b1, u);
478
- debug_assert_eq!(enc_size & 0b1, enc_size);
479
-
480
- 0b0_1_0_01110_00_10000_00_0_10_10_00000_00000
481
- | u << 29
482
- | enc_size << 22
483
- | machreg_to_vec(rn) << 5
484
- | machreg_to_vec(rd.to_reg())
485
- }
486
-
487
- fn enc_vec_lanes(q: u32, u: u32, size: u32, opcode: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
488
- debug_assert_eq!(q & 0b1, q);
489
- debug_assert_eq!(u & 0b1, u);
490
- debug_assert_eq!(size & 0b11, size);
491
- debug_assert_eq!(opcode & 0b11111, opcode);
492
- 0b0_0_0_01110_00_11000_0_0000_10_00000_00000
493
- | q << 30
494
- | u << 29
495
- | size << 22
496
- | opcode << 12
497
- | machreg_to_vec(rn) << 5
498
- | machreg_to_vec(rd.to_reg())
499
- }
500
-
501
- fn enc_tbl(is_extension: bool, len: u32, rd: Writable<Reg>, rn: Reg, rm: Reg) -> u32 {
502
- debug_assert_eq!(len & 0b11, len);
503
- 0b0_1_001110_000_00000_0_00_0_00_00000_00000
504
- | (machreg_to_vec(rm) << 16)
505
- | len << 13
506
- | (is_extension as u32) << 12
507
- | (machreg_to_vec(rn) << 5)
508
- | machreg_to_vec(rd.to_reg())
509
- }
510
-
511
- fn enc_dmb_ish() -> u32 {
512
- 0xD5033BBF
513
- }
514
-
515
- fn enc_acq_rel(ty: Type, op: AtomicRMWOp, rs: Reg, rt: Writable<Reg>, rn: Reg) -> u32 {
516
- assert!(machreg_to_gpr(rt.to_reg()) != 31);
517
- let sz = match ty {
518
- I64 => 0b11,
519
- I32 => 0b10,
520
- I16 => 0b01,
521
- I8 => 0b00,
522
- _ => unreachable!(),
523
- };
524
- let bit15 = match op {
525
- AtomicRMWOp::Swp => 0b1,
526
- _ => 0b0,
527
- };
528
- let op = match op {
529
- AtomicRMWOp::Add => 0b000,
530
- AtomicRMWOp::Clr => 0b001,
531
- AtomicRMWOp::Eor => 0b010,
532
- AtomicRMWOp::Set => 0b011,
533
- AtomicRMWOp::Smax => 0b100,
534
- AtomicRMWOp::Smin => 0b101,
535
- AtomicRMWOp::Umax => 0b110,
536
- AtomicRMWOp::Umin => 0b111,
537
- AtomicRMWOp::Swp => 0b000,
538
- };
539
- 0b00_111_000_111_00000_0_000_00_00000_00000
540
- | (sz << 30)
541
- | (machreg_to_gpr(rs) << 16)
542
- | bit15 << 15
543
- | (op << 12)
544
- | (machreg_to_gpr(rn) << 5)
545
- | machreg_to_gpr(rt.to_reg())
546
- }
547
-
548
- fn enc_ldar(ty: Type, rt: Writable<Reg>, rn: Reg) -> u32 {
549
- let sz = match ty {
550
- I64 => 0b11,
551
- I32 => 0b10,
552
- I16 => 0b01,
553
- I8 => 0b00,
554
- _ => unreachable!(),
555
- };
556
- 0b00_001000_1_1_0_11111_1_11111_00000_00000
557
- | (sz << 30)
558
- | (machreg_to_gpr(rn) << 5)
559
- | machreg_to_gpr(rt.to_reg())
560
- }
561
-
562
- fn enc_stlr(ty: Type, rt: Reg, rn: Reg) -> u32 {
563
- let sz = match ty {
564
- I64 => 0b11,
565
- I32 => 0b10,
566
- I16 => 0b01,
567
- I8 => 0b00,
568
- _ => unreachable!(),
569
- };
570
- 0b00_001000_100_11111_1_11111_00000_00000
571
- | (sz << 30)
572
- | (machreg_to_gpr(rn) << 5)
573
- | machreg_to_gpr(rt)
574
- }
575
-
576
- fn enc_ldaxr(ty: Type, rt: Writable<Reg>, rn: Reg) -> u32 {
577
- let sz = match ty {
578
- I64 => 0b11,
579
- I32 => 0b10,
580
- I16 => 0b01,
581
- I8 => 0b00,
582
- _ => unreachable!(),
583
- };
584
- 0b00_001000_0_1_0_11111_1_11111_00000_00000
585
- | (sz << 30)
586
- | (machreg_to_gpr(rn) << 5)
587
- | machreg_to_gpr(rt.to_reg())
588
- }
589
-
590
- fn enc_stlxr(ty: Type, rs: Writable<Reg>, rt: Reg, rn: Reg) -> u32 {
591
- let sz = match ty {
592
- I64 => 0b11,
593
- I32 => 0b10,
594
- I16 => 0b01,
595
- I8 => 0b00,
596
- _ => unreachable!(),
597
- };
598
- 0b00_001000_000_00000_1_11111_00000_00000
599
- | (sz << 30)
600
- | (machreg_to_gpr(rs.to_reg()) << 16)
601
- | (machreg_to_gpr(rn) << 5)
602
- | machreg_to_gpr(rt)
603
- }
604
-
605
- fn enc_cas(size: u32, rs: Writable<Reg>, rt: Reg, rn: Reg) -> u32 {
606
- debug_assert_eq!(size & 0b11, size);
607
-
608
- 0b00_0010001_1_1_00000_1_11111_00000_00000
609
- | size << 30
610
- | machreg_to_gpr(rs.to_reg()) << 16
611
- | machreg_to_gpr(rn) << 5
612
- | machreg_to_gpr(rt)
613
- }
614
-
615
- fn enc_asimd_mod_imm(rd: Writable<Reg>, q_op: u32, cmode: u32, imm: u8) -> u32 {
616
- let abc = (imm >> 5) as u32;
617
- let defgh = (imm & 0b11111) as u32;
618
-
619
- debug_assert_eq!(cmode & 0b1111, cmode);
620
- debug_assert_eq!(q_op & 0b11, q_op);
621
-
622
- 0b0_0_0_0111100000_000_0000_01_00000_00000
623
- | (q_op << 29)
624
- | (abc << 16)
625
- | (cmode << 12)
626
- | (defgh << 5)
627
- | machreg_to_vec(rd.to_reg())
628
- }
629
-
630
- /// State carried between emissions of a sequence of instructions.
631
- #[derive(Default, Clone, Debug)]
632
- pub struct EmitState {
633
- /// Addend to convert nominal-SP offsets to real-SP offsets at the current
634
- /// program point.
635
- pub(crate) virtual_sp_offset: i64,
636
- /// Offset of FP from nominal-SP.
637
- pub(crate) nominal_sp_to_fp: i64,
638
- /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
639
- stack_map: Option<StackMap>,
640
- /// Current source-code location corresponding to instruction to be emitted.
641
- cur_srcloc: RelSourceLoc,
642
- /// Only used during fuzz-testing. Otherwise, it is a zero-sized struct and
643
- /// optimized away at compiletime. See [cranelift_control].
644
- ctrl_plane: ControlPlane,
645
- }
646
-
647
- impl MachInstEmitState<Inst> for EmitState {
648
- fn new(abi: &Callee<AArch64MachineDeps>, ctrl_plane: ControlPlane) -> Self {
649
- EmitState {
650
- virtual_sp_offset: 0,
651
- nominal_sp_to_fp: abi.frame_size() as i64,
652
- stack_map: None,
653
- cur_srcloc: Default::default(),
654
- ctrl_plane,
655
- }
656
- }
657
-
658
- fn pre_safepoint(&mut self, stack_map: StackMap) {
659
- self.stack_map = Some(stack_map);
660
- }
661
-
662
- fn pre_sourceloc(&mut self, srcloc: RelSourceLoc) {
663
- self.cur_srcloc = srcloc;
664
- }
665
-
666
- fn ctrl_plane_mut(&mut self) -> &mut ControlPlane {
667
- &mut self.ctrl_plane
668
- }
669
-
670
- fn take_ctrl_plane(self) -> ControlPlane {
671
- self.ctrl_plane
672
- }
673
- }
674
-
675
- impl EmitState {
676
- fn take_stack_map(&mut self) -> Option<StackMap> {
677
- self.stack_map.take()
678
- }
679
-
680
- fn clear_post_insn(&mut self) {
681
- self.stack_map = None;
682
- }
683
-
684
- fn cur_srcloc(&self) -> RelSourceLoc {
685
- self.cur_srcloc
686
- }
687
- }
688
-
689
- /// Constant state used during function compilation.
690
- pub struct EmitInfo(settings::Flags);
691
-
692
- impl EmitInfo {
693
- /// Create a constant state for emission of instructions.
694
- pub fn new(flags: settings::Flags) -> Self {
695
- Self(flags)
696
- }
697
- }
698
-
699
- impl MachInstEmit for Inst {
700
- type State = EmitState;
701
- type Info = EmitInfo;
702
-
703
- fn emit(
704
- &self,
705
- allocs: &[Allocation],
706
- sink: &mut MachBuffer<Inst>,
707
- emit_info: &Self::Info,
708
- state: &mut EmitState,
709
- ) {
710
- let mut allocs = AllocationConsumer::new(allocs);
711
-
712
- // N.B.: we *must* not exceed the "worst-case size" used to compute
713
- // where to insert islands, except when islands are explicitly triggered
714
- // (with an `EmitIsland`). We check this in debug builds. This is `mut`
715
- // to allow disabling the check for `JTSequence`, which is always
716
- // emitted following an `EmitIsland`.
717
- let mut start_off = sink.cur_offset();
718
-
719
- match self {
720
- &Inst::AluRRR {
721
- alu_op,
722
- size,
723
- rd,
724
- rn,
725
- rm,
726
- } => {
727
- let rd = allocs.next_writable(rd);
728
- let rn = allocs.next(rn);
729
- let rm = allocs.next(rm);
730
-
731
- debug_assert!(match alu_op {
732
- ALUOp::SDiv | ALUOp::UDiv | ALUOp::SMulH | ALUOp::UMulH =>
733
- size == OperandSize::Size64,
734
- _ => true,
735
- });
736
- let top11 = match alu_op {
737
- ALUOp::Add => 0b00001011_000,
738
- ALUOp::Adc => 0b00011010_000,
739
- ALUOp::AdcS => 0b00111010_000,
740
- ALUOp::Sub => 0b01001011_000,
741
- ALUOp::Sbc => 0b01011010_000,
742
- ALUOp::SbcS => 0b01111010_000,
743
- ALUOp::Orr => 0b00101010_000,
744
- ALUOp::And => 0b00001010_000,
745
- ALUOp::AndS => 0b01101010_000,
746
- ALUOp::Eor => 0b01001010_000,
747
- ALUOp::OrrNot => 0b00101010_001,
748
- ALUOp::AndNot => 0b00001010_001,
749
- ALUOp::EorNot => 0b01001010_001,
750
- ALUOp::AddS => 0b00101011_000,
751
- ALUOp::SubS => 0b01101011_000,
752
- ALUOp::SDiv => 0b10011010_110,
753
- ALUOp::UDiv => 0b10011010_110,
754
- ALUOp::RotR | ALUOp::Lsr | ALUOp::Asr | ALUOp::Lsl => 0b00011010_110,
755
- ALUOp::SMulH => 0b10011011_010,
756
- ALUOp::UMulH => 0b10011011_110,
757
- };
758
- let top11 = top11 | size.sf_bit() << 10;
759
- let bit15_10 = match alu_op {
760
- ALUOp::SDiv => 0b000011,
761
- ALUOp::UDiv => 0b000010,
762
- ALUOp::RotR => 0b001011,
763
- ALUOp::Lsr => 0b001001,
764
- ALUOp::Asr => 0b001010,
765
- ALUOp::Lsl => 0b001000,
766
- ALUOp::SMulH | ALUOp::UMulH => 0b011111,
767
- _ => 0b000000,
768
- };
769
- debug_assert_ne!(writable_stack_reg(), rd);
770
- // The stack pointer is the zero register in this context, so this might be an
771
- // indication that something is wrong.
772
- debug_assert_ne!(stack_reg(), rn);
773
- debug_assert_ne!(stack_reg(), rm);
774
- sink.put4(enc_arith_rrr(top11, bit15_10, rd, rn, rm));
775
- }
776
- &Inst::AluRRRR {
777
- alu_op,
778
- size,
779
- rd,
780
- rm,
781
- rn,
782
- ra,
783
- } => {
784
- let rd = allocs.next_writable(rd);
785
- let rn = allocs.next(rn);
786
- let rm = allocs.next(rm);
787
- let ra = allocs.next(ra);
788
-
789
- let (top11, bit15) = match alu_op {
790
- ALUOp3::MAdd => (0b0_00_11011_000, 0),
791
- ALUOp3::MSub => (0b0_00_11011_000, 1),
792
- ALUOp3::UMAddL => {
793
- debug_assert!(size == OperandSize::Size32);
794
- (0b1_00_11011_1_01, 0)
795
- }
796
- ALUOp3::SMAddL => {
797
- debug_assert!(size == OperandSize::Size32);
798
- (0b1_00_11011_0_01, 0)
799
- }
800
- };
801
- let top11 = top11 | size.sf_bit() << 10;
802
- sink.put4(enc_arith_rrrr(top11, rm, bit15, ra, rn, rd));
803
- }
804
- &Inst::AluRRImm12 {
805
- alu_op,
806
- size,
807
- rd,
808
- rn,
809
- ref imm12,
810
- } => {
811
- let rd = allocs.next_writable(rd);
812
- let rn = allocs.next(rn);
813
- let top8 = match alu_op {
814
- ALUOp::Add => 0b000_10001,
815
- ALUOp::Sub => 0b010_10001,
816
- ALUOp::AddS => 0b001_10001,
817
- ALUOp::SubS => 0b011_10001,
818
- _ => unimplemented!("{:?}", alu_op),
819
- };
820
- let top8 = top8 | size.sf_bit() << 7;
821
- sink.put4(enc_arith_rr_imm12(
822
- top8,
823
- imm12.shift_bits(),
824
- imm12.imm_bits(),
825
- rn,
826
- rd,
827
- ));
828
- }
829
- &Inst::AluRRImmLogic {
830
- alu_op,
831
- size,
832
- rd,
833
- rn,
834
- ref imml,
835
- } => {
836
- let rd = allocs.next_writable(rd);
837
- let rn = allocs.next(rn);
838
- let (top9, inv) = match alu_op {
839
- ALUOp::Orr => (0b001_100100, false),
840
- ALUOp::And => (0b000_100100, false),
841
- ALUOp::AndS => (0b011_100100, false),
842
- ALUOp::Eor => (0b010_100100, false),
843
- ALUOp::OrrNot => (0b001_100100, true),
844
- ALUOp::AndNot => (0b000_100100, true),
845
- ALUOp::EorNot => (0b010_100100, true),
846
- _ => unimplemented!("{:?}", alu_op),
847
- };
848
- let top9 = top9 | size.sf_bit() << 8;
849
- let imml = if inv { imml.invert() } else { imml.clone() };
850
- sink.put4(enc_arith_rr_imml(top9, imml.enc_bits(), rn, rd));
851
- }
852
-
853
- &Inst::AluRRImmShift {
854
- alu_op,
855
- size,
856
- rd,
857
- rn,
858
- ref immshift,
859
- } => {
860
- let rd = allocs.next_writable(rd);
861
- let rn = allocs.next(rn);
862
- let amt = immshift.value();
863
- let (top10, immr, imms) = match alu_op {
864
- ALUOp::RotR => (0b0001001110, machreg_to_gpr(rn), u32::from(amt)),
865
- ALUOp::Lsr => (0b0101001100, u32::from(amt), 0b011111),
866
- ALUOp::Asr => (0b0001001100, u32::from(amt), 0b011111),
867
- ALUOp::Lsl => {
868
- let bits = if size.is64() { 64 } else { 32 };
869
- (
870
- 0b0101001100,
871
- u32::from((bits - amt) % bits),
872
- u32::from(bits - 1 - amt),
873
- )
874
- }
875
- _ => unimplemented!("{:?}", alu_op),
876
- };
877
- let top10 = top10 | size.sf_bit() << 9 | size.sf_bit();
878
- let imms = match alu_op {
879
- ALUOp::Lsr | ALUOp::Asr => imms | size.sf_bit() << 5,
880
- _ => imms,
881
- };
882
- sink.put4(
883
- (top10 << 22)
884
- | (immr << 16)
885
- | (imms << 10)
886
- | (machreg_to_gpr(rn) << 5)
887
- | machreg_to_gpr(rd.to_reg()),
888
- );
889
- }
890
-
891
- &Inst::AluRRRShift {
892
- alu_op,
893
- size,
894
- rd,
895
- rn,
896
- rm,
897
- ref shiftop,
898
- } => {
899
- let rd = allocs.next_writable(rd);
900
- let rn = allocs.next(rn);
901
- let rm = allocs.next(rm);
902
- let top11: u32 = match alu_op {
903
- ALUOp::Add => 0b000_01011000,
904
- ALUOp::AddS => 0b001_01011000,
905
- ALUOp::Sub => 0b010_01011000,
906
- ALUOp::SubS => 0b011_01011000,
907
- ALUOp::Orr => 0b001_01010000,
908
- ALUOp::And => 0b000_01010000,
909
- ALUOp::AndS => 0b011_01010000,
910
- ALUOp::Eor => 0b010_01010000,
911
- ALUOp::OrrNot => 0b001_01010001,
912
- ALUOp::EorNot => 0b010_01010001,
913
- ALUOp::AndNot => 0b000_01010001,
914
- _ => unimplemented!("{:?}", alu_op),
915
- };
916
- let top11 = top11 | size.sf_bit() << 10;
917
- let top11 = top11 | (u32::from(shiftop.op().bits()) << 1);
918
- let bits_15_10 = u32::from(shiftop.amt().value());
919
- sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
920
- }
921
-
922
- &Inst::AluRRRExtend {
923
- alu_op,
924
- size,
925
- rd,
926
- rn,
927
- rm,
928
- extendop,
929
- } => {
930
- let rd = allocs.next_writable(rd);
931
- let rn = allocs.next(rn);
932
- let rm = allocs.next(rm);
933
- let top11: u32 = match alu_op {
934
- ALUOp::Add => 0b00001011001,
935
- ALUOp::Sub => 0b01001011001,
936
- ALUOp::AddS => 0b00101011001,
937
- ALUOp::SubS => 0b01101011001,
938
- _ => unimplemented!("{:?}", alu_op),
939
- };
940
- let top11 = top11 | size.sf_bit() << 10;
941
- let bits_15_10 = u32::from(extendop.bits()) << 3;
942
- sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
943
- }
944
-
945
- &Inst::BitRR {
946
- op, size, rd, rn, ..
947
- } => {
948
- let rd = allocs.next_writable(rd);
949
- let rn = allocs.next(rn);
950
- let (op1, op2) = match op {
951
- BitOp::RBit => (0b00000, 0b000000),
952
- BitOp::Clz => (0b00000, 0b000100),
953
- BitOp::Cls => (0b00000, 0b000101),
954
- BitOp::Rev16 => (0b00000, 0b000001),
955
- BitOp::Rev32 => (0b00000, 0b000010),
956
- BitOp::Rev64 => (0b00000, 0b000011),
957
- };
958
- sink.put4(enc_bit_rr(size.sf_bit(), op1, op2, rn, rd))
959
- }
960
-
961
- &Inst::ULoad8 { rd, ref mem, flags }
962
- | &Inst::SLoad8 { rd, ref mem, flags }
963
- | &Inst::ULoad16 { rd, ref mem, flags }
964
- | &Inst::SLoad16 { rd, ref mem, flags }
965
- | &Inst::ULoad32 { rd, ref mem, flags }
966
- | &Inst::SLoad32 { rd, ref mem, flags }
967
- | &Inst::ULoad64 {
968
- rd, ref mem, flags, ..
969
- }
970
- | &Inst::FpuLoad32 { rd, ref mem, flags }
971
- | &Inst::FpuLoad64 { rd, ref mem, flags }
972
- | &Inst::FpuLoad128 { rd, ref mem, flags } => {
973
- let rd = allocs.next_writable(rd);
974
- let mem = mem.with_allocs(&mut allocs);
975
- let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
976
-
977
- for inst in mem_insts.into_iter() {
978
- inst.emit(&[], sink, emit_info, state);
979
- }
980
-
981
- // ldst encoding helpers take Reg, not Writable<Reg>.
982
- let rd = rd.to_reg();
983
-
984
- // This is the base opcode (top 10 bits) for the "unscaled
985
- // immediate" form (Unscaled). Other addressing modes will OR in
986
- // other values for bits 24/25 (bits 1/2 of this constant).
987
- let (op, bits) = match self {
988
- &Inst::ULoad8 { .. } => (0b0011100001, 8),
989
- &Inst::SLoad8 { .. } => (0b0011100010, 8),
990
- &Inst::ULoad16 { .. } => (0b0111100001, 16),
991
- &Inst::SLoad16 { .. } => (0b0111100010, 16),
992
- &Inst::ULoad32 { .. } => (0b1011100001, 32),
993
- &Inst::SLoad32 { .. } => (0b1011100010, 32),
994
- &Inst::ULoad64 { .. } => (0b1111100001, 64),
995
- &Inst::FpuLoad32 { .. } => (0b1011110001, 32),
996
- &Inst::FpuLoad64 { .. } => (0b1111110001, 64),
997
- &Inst::FpuLoad128 { .. } => (0b0011110011, 128),
998
- _ => unreachable!(),
999
- };
1000
-
1001
- let srcloc = state.cur_srcloc();
1002
- if !srcloc.is_default() && !flags.notrap() {
1003
- // Register the offset at which the actual load instruction starts.
1004
- sink.add_trap(TrapCode::HeapOutOfBounds);
1005
- }
1006
-
1007
- match &mem {
1008
- &AMode::Unscaled { rn, simm9 } => {
1009
- let reg = allocs.next(rn);
1010
- sink.put4(enc_ldst_simm9(op, simm9, 0b00, reg, rd));
1011
- }
1012
- &AMode::UnsignedOffset { rn, uimm12 } => {
1013
- let reg = allocs.next(rn);
1014
- if uimm12.value() != 0 {
1015
- assert_eq!(bits, ty_bits(uimm12.scale_ty()));
1016
- }
1017
- sink.put4(enc_ldst_uimm12(op, uimm12, reg, rd));
1018
- }
1019
- &AMode::RegReg { rn, rm } => {
1020
- let r1 = allocs.next(rn);
1021
- let r2 = allocs.next(rm);
1022
- sink.put4(enc_ldst_reg(
1023
- op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
1024
- ));
1025
- }
1026
- &AMode::RegScaled { rn, rm, ty }
1027
- | &AMode::RegScaledExtended { rn, rm, ty, .. } => {
1028
- let r1 = allocs.next(rn);
1029
- let r2 = allocs.next(rm);
1030
- assert_eq!(bits, ty_bits(ty));
1031
- let extendop = match &mem {
1032
- &AMode::RegScaled { .. } => None,
1033
- &AMode::RegScaledExtended { extendop, .. } => Some(extendop),
1034
- _ => unreachable!(),
1035
- };
1036
- sink.put4(enc_ldst_reg(
1037
- op, r1, r2, /* scaled = */ true, extendop, rd,
1038
- ));
1039
- }
1040
- &AMode::RegExtended { rn, rm, extendop } => {
1041
- let r1 = allocs.next(rn);
1042
- let r2 = allocs.next(rm);
1043
- sink.put4(enc_ldst_reg(
1044
- op,
1045
- r1,
1046
- r2,
1047
- /* scaled = */ false,
1048
- Some(extendop),
1049
- rd,
1050
- ));
1051
- }
1052
- &AMode::Label { ref label } => {
1053
- let offset = match label {
1054
- // cast i32 to u32 (two's-complement)
1055
- MemLabel::PCRel(off) => *off as u32,
1056
- // Emit a relocation into the `MachBuffer`
1057
- // for the label that's being loaded from and
1058
- // encode an address of 0 in its place which will
1059
- // get filled in by relocation resolution later on.
1060
- MemLabel::Mach(label) => {
1061
- sink.use_label_at_offset(
1062
- sink.cur_offset(),
1063
- *label,
1064
- LabelUse::Ldr19,
1065
- );
1066
- 0
1067
- }
1068
- } / 4;
1069
- assert!(offset < (1 << 19));
1070
- match self {
1071
- &Inst::ULoad32 { .. } => {
1072
- sink.put4(enc_ldst_imm19(0b00011000, offset, rd));
1073
- }
1074
- &Inst::SLoad32 { .. } => {
1075
- sink.put4(enc_ldst_imm19(0b10011000, offset, rd));
1076
- }
1077
- &Inst::FpuLoad32 { .. } => {
1078
- sink.put4(enc_ldst_imm19(0b00011100, offset, rd));
1079
- }
1080
- &Inst::ULoad64 { .. } => {
1081
- sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
1082
- }
1083
- &Inst::FpuLoad64 { .. } => {
1084
- sink.put4(enc_ldst_imm19(0b01011100, offset, rd));
1085
- }
1086
- &Inst::FpuLoad128 { .. } => {
1087
- sink.put4(enc_ldst_imm19(0b10011100, offset, rd));
1088
- }
1089
- _ => panic!("Unspported size for LDR from constant pool!"),
1090
- }
1091
- }
1092
- &AMode::SPPreIndexed { simm9 } => {
1093
- let reg = stack_reg();
1094
- sink.put4(enc_ldst_simm9(op, simm9, 0b11, reg, rd));
1095
- }
1096
- &AMode::SPPostIndexed { simm9 } => {
1097
- let reg = stack_reg();
1098
- sink.put4(enc_ldst_simm9(op, simm9, 0b01, reg, rd));
1099
- }
1100
- // Eliminated by `mem_finalize()` above.
1101
- &AMode::SPOffset { .. }
1102
- | &AMode::FPOffset { .. }
1103
- | &AMode::NominalSPOffset { .. }
1104
- | &AMode::Const { .. }
1105
- | &AMode::RegOffset { .. } => {
1106
- panic!("Should not see {:?} here!", mem)
1107
- }
1108
- }
1109
- }
1110
-
1111
- &Inst::Store8 { rd, ref mem, flags }
1112
- | &Inst::Store16 { rd, ref mem, flags }
1113
- | &Inst::Store32 { rd, ref mem, flags }
1114
- | &Inst::Store64 { rd, ref mem, flags }
1115
- | &Inst::FpuStore32 { rd, ref mem, flags }
1116
- | &Inst::FpuStore64 { rd, ref mem, flags }
1117
- | &Inst::FpuStore128 { rd, ref mem, flags } => {
1118
- let rd = allocs.next(rd);
1119
- let mem = mem.with_allocs(&mut allocs);
1120
- let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
1121
-
1122
- for inst in mem_insts.into_iter() {
1123
- inst.emit(&[], sink, emit_info, state);
1124
- }
1125
-
1126
- let (op, bits) = match self {
1127
- &Inst::Store8 { .. } => (0b0011100000, 8),
1128
- &Inst::Store16 { .. } => (0b0111100000, 16),
1129
- &Inst::Store32 { .. } => (0b1011100000, 32),
1130
- &Inst::Store64 { .. } => (0b1111100000, 64),
1131
- &Inst::FpuStore32 { .. } => (0b1011110000, 32),
1132
- &Inst::FpuStore64 { .. } => (0b1111110000, 64),
1133
- &Inst::FpuStore128 { .. } => (0b0011110010, 128),
1134
- _ => unreachable!(),
1135
- };
1136
-
1137
- let srcloc = state.cur_srcloc();
1138
- if !srcloc.is_default() && !flags.notrap() {
1139
- // Register the offset at which the actual store instruction starts.
1140
- sink.add_trap(TrapCode::HeapOutOfBounds);
1141
- }
1142
-
1143
- match &mem {
1144
- &AMode::Unscaled { rn, simm9 } => {
1145
- let reg = allocs.next(rn);
1146
- sink.put4(enc_ldst_simm9(op, simm9, 0b00, reg, rd));
1147
- }
1148
- &AMode::UnsignedOffset { rn, uimm12 } => {
1149
- let reg = allocs.next(rn);
1150
- if uimm12.value() != 0 {
1151
- assert_eq!(bits, ty_bits(uimm12.scale_ty()));
1152
- }
1153
- sink.put4(enc_ldst_uimm12(op, uimm12, reg, rd));
1154
- }
1155
- &AMode::RegReg { rn, rm } => {
1156
- let r1 = allocs.next(rn);
1157
- let r2 = allocs.next(rm);
1158
- sink.put4(enc_ldst_reg(
1159
- op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
1160
- ));
1161
- }
1162
- &AMode::RegScaled { rn, rm, .. } | &AMode::RegScaledExtended { rn, rm, .. } => {
1163
- let r1 = allocs.next(rn);
1164
- let r2 = allocs.next(rm);
1165
- let extendop = match &mem {
1166
- &AMode::RegScaled { .. } => None,
1167
- &AMode::RegScaledExtended { extendop, .. } => Some(extendop),
1168
- _ => unreachable!(),
1169
- };
1170
- sink.put4(enc_ldst_reg(
1171
- op, r1, r2, /* scaled = */ true, extendop, rd,
1172
- ));
1173
- }
1174
- &AMode::RegExtended { rn, rm, extendop } => {
1175
- let r1 = allocs.next(rn);
1176
- let r2 = allocs.next(rm);
1177
- sink.put4(enc_ldst_reg(
1178
- op,
1179
- r1,
1180
- r2,
1181
- /* scaled = */ false,
1182
- Some(extendop),
1183
- rd,
1184
- ));
1185
- }
1186
- &AMode::Label { .. } => {
1187
- panic!("Store to a MemLabel not implemented!");
1188
- }
1189
- &AMode::SPPreIndexed { simm9 } => {
1190
- let reg = stack_reg();
1191
- sink.put4(enc_ldst_simm9(op, simm9, 0b11, reg, rd));
1192
- }
1193
- &AMode::SPPostIndexed { simm9 } => {
1194
- let reg = stack_reg();
1195
- sink.put4(enc_ldst_simm9(op, simm9, 0b01, reg, rd));
1196
- }
1197
- // Eliminated by `mem_finalize()` above.
1198
- &AMode::SPOffset { .. }
1199
- | &AMode::FPOffset { .. }
1200
- | &AMode::NominalSPOffset { .. }
1201
- | &AMode::Const { .. }
1202
- | &AMode::RegOffset { .. } => {
1203
- panic!("Should not see {:?} here!", mem)
1204
- }
1205
- }
1206
- }
1207
-
1208
- &Inst::StoreP64 {
1209
- rt,
1210
- rt2,
1211
- ref mem,
1212
- flags,
1213
- } => {
1214
- let rt = allocs.next(rt);
1215
- let rt2 = allocs.next(rt2);
1216
- let mem = mem.with_allocs(&mut allocs);
1217
- let srcloc = state.cur_srcloc();
1218
- if !srcloc.is_default() && !flags.notrap() {
1219
- // Register the offset at which the actual store instruction starts.
1220
- sink.add_trap(TrapCode::HeapOutOfBounds);
1221
- }
1222
- match &mem {
1223
- &PairAMode::SignedOffset(reg, simm7) => {
1224
- assert_eq!(simm7.scale_ty, I64);
1225
- let reg = allocs.next(reg);
1226
- sink.put4(enc_ldst_pair(0b1010100100, simm7, reg, rt, rt2));
1227
- }
1228
- &PairAMode::SPPreIndexed(simm7) => {
1229
- assert_eq!(simm7.scale_ty, I64);
1230
- let reg = stack_reg();
1231
- sink.put4(enc_ldst_pair(0b1010100110, simm7, reg, rt, rt2));
1232
- }
1233
- &PairAMode::SPPostIndexed(simm7) => {
1234
- assert_eq!(simm7.scale_ty, I64);
1235
- let reg = stack_reg();
1236
- sink.put4(enc_ldst_pair(0b1010100010, simm7, reg, rt, rt2));
1237
- }
1238
- }
1239
- }
1240
- &Inst::LoadP64 {
1241
- rt,
1242
- rt2,
1243
- ref mem,
1244
- flags,
1245
- } => {
1246
- let rt = allocs.next(rt.to_reg());
1247
- let rt2 = allocs.next(rt2.to_reg());
1248
- let mem = mem.with_allocs(&mut allocs);
1249
- let srcloc = state.cur_srcloc();
1250
- if !srcloc.is_default() && !flags.notrap() {
1251
- // Register the offset at which the actual load instruction starts.
1252
- sink.add_trap(TrapCode::HeapOutOfBounds);
1253
- }
1254
-
1255
- match &mem {
1256
- &PairAMode::SignedOffset(reg, simm7) => {
1257
- assert_eq!(simm7.scale_ty, I64);
1258
- let reg = allocs.next(reg);
1259
- sink.put4(enc_ldst_pair(0b1010100101, simm7, reg, rt, rt2));
1260
- }
1261
- &PairAMode::SPPreIndexed(simm7) => {
1262
- assert_eq!(simm7.scale_ty, I64);
1263
- let reg = stack_reg();
1264
- sink.put4(enc_ldst_pair(0b1010100111, simm7, reg, rt, rt2));
1265
- }
1266
- &PairAMode::SPPostIndexed(simm7) => {
1267
- assert_eq!(simm7.scale_ty, I64);
1268
- let reg = stack_reg();
1269
- sink.put4(enc_ldst_pair(0b1010100011, simm7, reg, rt, rt2));
1270
- }
1271
- }
1272
- }
1273
- &Inst::FpuLoadP64 {
1274
- rt,
1275
- rt2,
1276
- ref mem,
1277
- flags,
1278
- }
1279
- | &Inst::FpuLoadP128 {
1280
- rt,
1281
- rt2,
1282
- ref mem,
1283
- flags,
1284
- } => {
1285
- let rt = allocs.next(rt.to_reg());
1286
- let rt2 = allocs.next(rt2.to_reg());
1287
- let mem = mem.with_allocs(&mut allocs);
1288
- let srcloc = state.cur_srcloc();
1289
-
1290
- if !srcloc.is_default() && !flags.notrap() {
1291
- // Register the offset at which the actual load instruction starts.
1292
- sink.add_trap(TrapCode::HeapOutOfBounds);
1293
- }
1294
-
1295
- let opc = match self {
1296
- &Inst::FpuLoadP64 { .. } => 0b01,
1297
- &Inst::FpuLoadP128 { .. } => 0b10,
1298
- _ => unreachable!(),
1299
- };
1300
-
1301
- match &mem {
1302
- &PairAMode::SignedOffset(reg, simm7) => {
1303
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1304
- let reg = allocs.next(reg);
1305
- sink.put4(enc_ldst_vec_pair(opc, 0b10, true, simm7, reg, rt, rt2));
1306
- }
1307
- &PairAMode::SPPreIndexed(simm7) => {
1308
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1309
- let reg = stack_reg();
1310
- sink.put4(enc_ldst_vec_pair(opc, 0b11, true, simm7, reg, rt, rt2));
1311
- }
1312
- &PairAMode::SPPostIndexed(simm7) => {
1313
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1314
- let reg = stack_reg();
1315
- sink.put4(enc_ldst_vec_pair(opc, 0b01, true, simm7, reg, rt, rt2));
1316
- }
1317
- }
1318
- }
1319
- &Inst::FpuStoreP64 {
1320
- rt,
1321
- rt2,
1322
- ref mem,
1323
- flags,
1324
- }
1325
- | &Inst::FpuStoreP128 {
1326
- rt,
1327
- rt2,
1328
- ref mem,
1329
- flags,
1330
- } => {
1331
- let rt = allocs.next(rt);
1332
- let rt2 = allocs.next(rt2);
1333
- let mem = mem.with_allocs(&mut allocs);
1334
- let srcloc = state.cur_srcloc();
1335
-
1336
- if !srcloc.is_default() && !flags.notrap() {
1337
- // Register the offset at which the actual store instruction starts.
1338
- sink.add_trap(TrapCode::HeapOutOfBounds);
1339
- }
1340
-
1341
- let opc = match self {
1342
- &Inst::FpuStoreP64 { .. } => 0b01,
1343
- &Inst::FpuStoreP128 { .. } => 0b10,
1344
- _ => unreachable!(),
1345
- };
1346
-
1347
- match &mem {
1348
- &PairAMode::SignedOffset(reg, simm7) => {
1349
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1350
- let reg = allocs.next(reg);
1351
- sink.put4(enc_ldst_vec_pair(opc, 0b10, false, simm7, reg, rt, rt2));
1352
- }
1353
- &PairAMode::SPPreIndexed(simm7) => {
1354
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1355
- let reg = stack_reg();
1356
- sink.put4(enc_ldst_vec_pair(opc, 0b11, false, simm7, reg, rt, rt2));
1357
- }
1358
- &PairAMode::SPPostIndexed(simm7) => {
1359
- assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
1360
- let reg = stack_reg();
1361
- sink.put4(enc_ldst_vec_pair(opc, 0b01, false, simm7, reg, rt, rt2));
1362
- }
1363
- }
1364
- }
1365
- &Inst::Mov { size, rd, rm } => {
1366
- let rd = allocs.next_writable(rd);
1367
- let rm = allocs.next(rm);
1368
- assert!(rd.to_reg().class() == rm.class());
1369
- assert!(rm.class() == RegClass::Int);
1370
-
1371
- match size {
1372
- OperandSize::Size64 => {
1373
- // MOV to SP is interpreted as MOV to XZR instead. And our codegen
1374
- // should never MOV to XZR.
1375
- assert!(rd.to_reg() != stack_reg());
1376
-
1377
- if rm == stack_reg() {
1378
- // We can't use ORR here, so use an `add rd, sp, #0` instead.
1379
- let imm12 = Imm12::maybe_from_u64(0).unwrap();
1380
- sink.put4(enc_arith_rr_imm12(
1381
- 0b100_10001,
1382
- imm12.shift_bits(),
1383
- imm12.imm_bits(),
1384
- rm,
1385
- rd,
1386
- ));
1387
- } else {
1388
- // Encoded as ORR rd, rm, zero.
1389
- sink.put4(enc_arith_rrr(0b10101010_000, 0b000_000, rd, zero_reg(), rm));
1390
- }
1391
- }
1392
- OperandSize::Size32 => {
1393
- // MOV to SP is interpreted as MOV to XZR instead. And our codegen
1394
- // should never MOV to XZR.
1395
- assert!(machreg_to_gpr(rd.to_reg()) != 31);
1396
- // Encoded as ORR rd, rm, zero.
1397
- sink.put4(enc_arith_rrr(0b00101010_000, 0b000_000, rd, zero_reg(), rm));
1398
- }
1399
- }
1400
- }
1401
- &Inst::MovFromPReg { rd, rm } => {
1402
- let rd = allocs.next_writable(rd);
1403
- allocs.next_fixed_nonallocatable(rm);
1404
- let rm: Reg = rm.into();
1405
- debug_assert!([
1406
- regs::fp_reg(),
1407
- regs::stack_reg(),
1408
- regs::link_reg(),
1409
- regs::pinned_reg()
1410
- ]
1411
- .contains(&rm));
1412
- assert!(rm.class() == RegClass::Int);
1413
- assert!(rd.to_reg().class() == rm.class());
1414
- let size = OperandSize::Size64;
1415
- Inst::Mov { size, rd, rm }.emit(&[], sink, emit_info, state);
1416
- }
1417
- &Inst::MovToPReg { rd, rm } => {
1418
- allocs.next_fixed_nonallocatable(rd);
1419
- let rd: Writable<Reg> = Writable::from_reg(rd.into());
1420
- let rm = allocs.next(rm);
1421
- debug_assert!([
1422
- regs::fp_reg(),
1423
- regs::stack_reg(),
1424
- regs::link_reg(),
1425
- regs::pinned_reg()
1426
- ]
1427
- .contains(&rd.to_reg()));
1428
- assert!(rd.to_reg().class() == RegClass::Int);
1429
- assert!(rm.class() == rd.to_reg().class());
1430
- let size = OperandSize::Size64;
1431
- Inst::Mov { size, rd, rm }.emit(&[], sink, emit_info, state);
1432
- }
1433
- &Inst::MovWide { op, rd, imm, size } => {
1434
- let rd = allocs.next_writable(rd);
1435
- sink.put4(enc_move_wide(op, rd, imm, size));
1436
- }
1437
- &Inst::MovK { rd, rn, imm, size } => {
1438
- let rn = allocs.next(rn);
1439
- let rd = allocs.next_writable(rd);
1440
- debug_assert_eq!(rn, rd.to_reg());
1441
- sink.put4(enc_movk(rd, imm, size));
1442
- }
1443
- &Inst::CSel { rd, rn, rm, cond } => {
1444
- let rd = allocs.next_writable(rd);
1445
- let rn = allocs.next(rn);
1446
- let rm = allocs.next(rm);
1447
- sink.put4(enc_csel(rd, rn, rm, cond, 0, 0));
1448
- }
1449
- &Inst::CSNeg { rd, rn, rm, cond } => {
1450
- let rd = allocs.next_writable(rd);
1451
- let rn = allocs.next(rn);
1452
- let rm = allocs.next(rm);
1453
- sink.put4(enc_csel(rd, rn, rm, cond, 1, 1));
1454
- }
1455
- &Inst::CSet { rd, cond } => {
1456
- let rd = allocs.next_writable(rd);
1457
- sink.put4(enc_csel(rd, zero_reg(), zero_reg(), cond.invert(), 0, 1));
1458
- }
1459
- &Inst::CSetm { rd, cond } => {
1460
- let rd = allocs.next_writable(rd);
1461
- sink.put4(enc_csel(rd, zero_reg(), zero_reg(), cond.invert(), 1, 0));
1462
- }
1463
- &Inst::CCmp {
1464
- size,
1465
- rn,
1466
- rm,
1467
- nzcv,
1468
- cond,
1469
- } => {
1470
- let rn = allocs.next(rn);
1471
- let rm = allocs.next(rm);
1472
- sink.put4(enc_ccmp(size, rn, rm, nzcv, cond));
1473
- }
1474
- &Inst::CCmpImm {
1475
- size,
1476
- rn,
1477
- imm,
1478
- nzcv,
1479
- cond,
1480
- } => {
1481
- let rn = allocs.next(rn);
1482
- sink.put4(enc_ccmp_imm(size, rn, imm, nzcv, cond));
1483
- }
1484
- &Inst::AtomicRMW {
1485
- ty,
1486
- op,
1487
- rs,
1488
- rt,
1489
- rn,
1490
- flags,
1491
- } => {
1492
- let rs = allocs.next(rs);
1493
- let rt = allocs.next_writable(rt);
1494
- let rn = allocs.next(rn);
1495
-
1496
- let srcloc = state.cur_srcloc();
1497
- if !srcloc.is_default() && !flags.notrap() {
1498
- sink.add_trap(TrapCode::HeapOutOfBounds);
1499
- }
1500
-
1501
- sink.put4(enc_acq_rel(ty, op, rs, rt, rn));
1502
- }
1503
- &Inst::AtomicRMWLoop { ty, op, flags, .. } => {
1504
- /* Emit this:
1505
- again:
1506
- ldaxr{,b,h} x/w27, [x25]
1507
- // maybe sign extend
1508
- op x28, x27, x26 // op is add,sub,and,orr,eor
1509
- stlxr{,b,h} w24, x/w28, [x25]
1510
- cbnz x24, again
1511
-
1512
- Operand conventions:
1513
- IN: x25 (addr), x26 (2nd arg for op)
1514
- OUT: x27 (old value), x24 (trashed), x28 (trashed)
1515
-
1516
- It is unfortunate that, per the ARM documentation, x28 cannot be used for
1517
- both the store-data and success-flag operands of stlxr. This causes the
1518
- instruction's behaviour to be "CONSTRAINED UNPREDICTABLE", so we use x24
1519
- instead for the success-flag.
1520
- */
1521
- // TODO: We should not hardcode registers here, a better idea would be to
1522
- // pass some scratch registers in the AtomicRMWLoop pseudo-instruction, and use those
1523
- let xzr = zero_reg();
1524
- let x24 = xreg(24);
1525
- let x25 = xreg(25);
1526
- let x26 = xreg(26);
1527
- let x27 = xreg(27);
1528
- let x28 = xreg(28);
1529
- let x24wr = writable_xreg(24);
1530
- let x27wr = writable_xreg(27);
1531
- let x28wr = writable_xreg(28);
1532
- let again_label = sink.get_label();
1533
-
1534
- // again:
1535
- sink.bind_label(again_label, &mut state.ctrl_plane);
1536
-
1537
- let srcloc = state.cur_srcloc();
1538
- if !srcloc.is_default() && !flags.notrap() {
1539
- sink.add_trap(TrapCode::HeapOutOfBounds);
1540
- }
1541
-
1542
- sink.put4(enc_ldaxr(ty, x27wr, x25)); // ldaxr x27, [x25]
1543
- let size = OperandSize::from_ty(ty);
1544
- let sign_ext = match op {
1545
- AtomicRMWLoopOp::Smin | AtomicRMWLoopOp::Smax => match ty {
1546
- I16 => Some((ExtendOp::SXTH, 16)),
1547
- I8 => Some((ExtendOp::SXTB, 8)),
1548
- _ => None,
1549
- },
1550
- _ => None,
1551
- };
1552
-
1553
- // sxt{b|h} the loaded result if necessary.
1554
- if sign_ext.is_some() {
1555
- let (_, from_bits) = sign_ext.unwrap();
1556
- Inst::Extend {
1557
- rd: x27wr,
1558
- rn: x27,
1559
- signed: true,
1560
- from_bits,
1561
- to_bits: size.bits(),
1562
- }
1563
- .emit(&[], sink, emit_info, state);
1564
- }
1565
-
1566
- match op {
1567
- AtomicRMWLoopOp::Xchg => {} // do nothing
1568
- AtomicRMWLoopOp::Nand => {
1569
- // and x28, x27, x26
1570
- // mvn x28, x28
1571
-
1572
- Inst::AluRRR {
1573
- alu_op: ALUOp::And,
1574
- size,
1575
- rd: x28wr,
1576
- rn: x27,
1577
- rm: x26,
1578
- }
1579
- .emit(&[], sink, emit_info, state);
1580
-
1581
- Inst::AluRRR {
1582
- alu_op: ALUOp::OrrNot,
1583
- size,
1584
- rd: x28wr,
1585
- rn: xzr,
1586
- rm: x28,
1587
- }
1588
- .emit(&[], sink, emit_info, state);
1589
- }
1590
- AtomicRMWLoopOp::Umin
1591
- | AtomicRMWLoopOp::Umax
1592
- | AtomicRMWLoopOp::Smin
1593
- | AtomicRMWLoopOp::Smax => {
1594
- // cmp x27, x26 {?sxt}
1595
- // csel.op x28, x27, x26
1596
-
1597
- let cond = match op {
1598
- AtomicRMWLoopOp::Umin => Cond::Lo,
1599
- AtomicRMWLoopOp::Umax => Cond::Hi,
1600
- AtomicRMWLoopOp::Smin => Cond::Lt,
1601
- AtomicRMWLoopOp::Smax => Cond::Gt,
1602
- _ => unreachable!(),
1603
- };
1604
-
1605
- if sign_ext.is_some() {
1606
- let (extendop, _) = sign_ext.unwrap();
1607
- Inst::AluRRRExtend {
1608
- alu_op: ALUOp::SubS,
1609
- size,
1610
- rd: writable_zero_reg(),
1611
- rn: x27,
1612
- rm: x26,
1613
- extendop,
1614
- }
1615
- .emit(&[], sink, emit_info, state);
1616
- } else {
1617
- Inst::AluRRR {
1618
- alu_op: ALUOp::SubS,
1619
- size,
1620
- rd: writable_zero_reg(),
1621
- rn: x27,
1622
- rm: x26,
1623
- }
1624
- .emit(&[], sink, emit_info, state);
1625
- }
1626
-
1627
- Inst::CSel {
1628
- cond,
1629
- rd: x28wr,
1630
- rn: x27,
1631
- rm: x26,
1632
- }
1633
- .emit(&[], sink, emit_info, state);
1634
- }
1635
- _ => {
1636
- // add/sub/and/orr/eor x28, x27, x26
1637
- let alu_op = match op {
1638
- AtomicRMWLoopOp::Add => ALUOp::Add,
1639
- AtomicRMWLoopOp::Sub => ALUOp::Sub,
1640
- AtomicRMWLoopOp::And => ALUOp::And,
1641
- AtomicRMWLoopOp::Orr => ALUOp::Orr,
1642
- AtomicRMWLoopOp::Eor => ALUOp::Eor,
1643
- AtomicRMWLoopOp::Nand
1644
- | AtomicRMWLoopOp::Umin
1645
- | AtomicRMWLoopOp::Umax
1646
- | AtomicRMWLoopOp::Smin
1647
- | AtomicRMWLoopOp::Smax
1648
- | AtomicRMWLoopOp::Xchg => unreachable!(),
1649
- };
1650
-
1651
- Inst::AluRRR {
1652
- alu_op,
1653
- size,
1654
- rd: x28wr,
1655
- rn: x27,
1656
- rm: x26,
1657
- }
1658
- .emit(&[], sink, emit_info, state);
1659
- }
1660
- }
1661
-
1662
- let srcloc = state.cur_srcloc();
1663
- if !srcloc.is_default() && !flags.notrap() {
1664
- sink.add_trap(TrapCode::HeapOutOfBounds);
1665
- }
1666
- if op == AtomicRMWLoopOp::Xchg {
1667
- sink.put4(enc_stlxr(ty, x24wr, x26, x25)); // stlxr w24, x26, [x25]
1668
- } else {
1669
- sink.put4(enc_stlxr(ty, x24wr, x28, x25)); // stlxr w24, x28, [x25]
1670
- }
1671
-
1672
- // cbnz w24, again
1673
- // Note, we're actually testing x24, and relying on the default zero-high-half
1674
- // rule in the assignment that `stlxr` does.
1675
- let br_offset = sink.cur_offset();
1676
- sink.put4(enc_conditional_br(
1677
- BranchTarget::Label(again_label),
1678
- CondBrKind::NotZero(x24),
1679
- &mut AllocationConsumer::default(),
1680
- ));
1681
- sink.use_label_at_offset(br_offset, again_label, LabelUse::Branch19);
1682
- }
1683
- &Inst::AtomicCAS {
1684
- rd,
1685
- rs,
1686
- rt,
1687
- rn,
1688
- ty,
1689
- flags,
1690
- } => {
1691
- let rd = allocs.next_writable(rd);
1692
- let rs = allocs.next(rs);
1693
- debug_assert_eq!(rd.to_reg(), rs);
1694
- let rt = allocs.next(rt);
1695
- let rn = allocs.next(rn);
1696
- let size = match ty {
1697
- I8 => 0b00,
1698
- I16 => 0b01,
1699
- I32 => 0b10,
1700
- I64 => 0b11,
1701
- _ => panic!("Unsupported type: {}", ty),
1702
- };
1703
-
1704
- let srcloc = state.cur_srcloc();
1705
- if !srcloc.is_default() && !flags.notrap() {
1706
- sink.add_trap(TrapCode::HeapOutOfBounds);
1707
- }
1708
-
1709
- sink.put4(enc_cas(size, rd, rt, rn));
1710
- }
1711
- &Inst::AtomicCASLoop { ty, flags, .. } => {
1712
- /* Emit this:
1713
- again:
1714
- ldaxr{,b,h} x/w27, [x25]
1715
- cmp x27, x/w26 uxt{b,h}
1716
- b.ne out
1717
- stlxr{,b,h} w24, x/w28, [x25]
1718
- cbnz x24, again
1719
- out:
1720
-
1721
- Operand conventions:
1722
- IN: x25 (addr), x26 (expected value), x28 (replacement value)
1723
- OUT: x27 (old value), x24 (trashed)
1724
- */
1725
- let x24 = xreg(24);
1726
- let x25 = xreg(25);
1727
- let x26 = xreg(26);
1728
- let x27 = xreg(27);
1729
- let x28 = xreg(28);
1730
- let xzrwr = writable_zero_reg();
1731
- let x24wr = writable_xreg(24);
1732
- let x27wr = writable_xreg(27);
1733
- let again_label = sink.get_label();
1734
- let out_label = sink.get_label();
1735
-
1736
- // again:
1737
- sink.bind_label(again_label, &mut state.ctrl_plane);
1738
-
1739
- let srcloc = state.cur_srcloc();
1740
- if !srcloc.is_default() && !flags.notrap() {
1741
- sink.add_trap(TrapCode::HeapOutOfBounds);
1742
- }
1743
-
1744
- // ldaxr x27, [x25]
1745
- sink.put4(enc_ldaxr(ty, x27wr, x25));
1746
-
1747
- // The top 32-bits are zero-extended by the ldaxr so we don't
1748
- // have to use UXTW, just the x-form of the register.
1749
- let (bit21, extend_op) = match ty {
1750
- I8 => (0b1, 0b000000),
1751
- I16 => (0b1, 0b001000),
1752
- _ => (0b0, 0b000000),
1753
- };
1754
- let bits_31_21 = 0b111_01011_000 | bit21;
1755
- // cmp x27, x26 (== subs xzr, x27, x26)
1756
- sink.put4(enc_arith_rrr(bits_31_21, extend_op, xzrwr, x27, x26));
1757
-
1758
- // b.ne out
1759
- let br_out_offset = sink.cur_offset();
1760
- sink.put4(enc_conditional_br(
1761
- BranchTarget::Label(out_label),
1762
- CondBrKind::Cond(Cond::Ne),
1763
- &mut AllocationConsumer::default(),
1764
- ));
1765
- sink.use_label_at_offset(br_out_offset, out_label, LabelUse::Branch19);
1766
-
1767
- let srcloc = state.cur_srcloc();
1768
- if !srcloc.is_default() && !flags.notrap() {
1769
- sink.add_trap(TrapCode::HeapOutOfBounds);
1770
- }
1771
-
1772
- sink.put4(enc_stlxr(ty, x24wr, x28, x25)); // stlxr w24, x28, [x25]
1773
-
1774
- // cbnz w24, again.
1775
- // Note, we're actually testing x24, and relying on the default zero-high-half
1776
- // rule in the assignment that `stlxr` does.
1777
- let br_again_offset = sink.cur_offset();
1778
- sink.put4(enc_conditional_br(
1779
- BranchTarget::Label(again_label),
1780
- CondBrKind::NotZero(x24),
1781
- &mut AllocationConsumer::default(),
1782
- ));
1783
- sink.use_label_at_offset(br_again_offset, again_label, LabelUse::Branch19);
1784
-
1785
- // out:
1786
- sink.bind_label(out_label, &mut state.ctrl_plane);
1787
- }
1788
- &Inst::LoadAcquire {
1789
- access_ty,
1790
- rt,
1791
- rn,
1792
- flags,
1793
- } => {
1794
- let rn = allocs.next(rn);
1795
- let rt = allocs.next_writable(rt);
1796
-
1797
- let srcloc = state.cur_srcloc();
1798
- if !srcloc.is_default() && !flags.notrap() {
1799
- sink.add_trap(TrapCode::HeapOutOfBounds);
1800
- }
1801
-
1802
- sink.put4(enc_ldar(access_ty, rt, rn));
1803
- }
1804
- &Inst::StoreRelease {
1805
- access_ty,
1806
- rt,
1807
- rn,
1808
- flags,
1809
- } => {
1810
- let rn = allocs.next(rn);
1811
- let rt = allocs.next(rt);
1812
-
1813
- let srcloc = state.cur_srcloc();
1814
- if !srcloc.is_default() && !flags.notrap() {
1815
- sink.add_trap(TrapCode::HeapOutOfBounds);
1816
- }
1817
-
1818
- sink.put4(enc_stlr(access_ty, rt, rn));
1819
- }
1820
- &Inst::Fence {} => {
1821
- sink.put4(enc_dmb_ish()); // dmb ish
1822
- }
1823
- &Inst::Csdb {} => {
1824
- sink.put4(0xd503229f);
1825
- }
1826
- &Inst::FpuMove64 { rd, rn } => {
1827
- let rd = allocs.next_writable(rd);
1828
- let rn = allocs.next(rn);
1829
- sink.put4(enc_fpurr(0b000_11110_01_1_000000_10000, rd, rn));
1830
- }
1831
- &Inst::FpuMove128 { rd, rn } => {
1832
- let rd = allocs.next_writable(rd);
1833
- let rn = allocs.next(rn);
1834
- sink.put4(enc_vecmov(/* 16b = */ true, rd, rn));
1835
- }
1836
- &Inst::FpuMoveFromVec { rd, rn, idx, size } => {
1837
- let rd = allocs.next_writable(rd);
1838
- let rn = allocs.next(rn);
1839
- let (imm5, shift, mask) = match size.lane_size() {
1840
- ScalarSize::Size32 => (0b00100, 3, 0b011),
1841
- ScalarSize::Size64 => (0b01000, 4, 0b001),
1842
- _ => unimplemented!(),
1843
- };
1844
- debug_assert_eq!(idx & mask, idx);
1845
- let imm5 = imm5 | ((idx as u32) << shift);
1846
- sink.put4(
1847
- 0b010_11110000_00000_000001_00000_00000
1848
- | (imm5 << 16)
1849
- | (machreg_to_vec(rn) << 5)
1850
- | machreg_to_vec(rd.to_reg()),
1851
- );
1852
- }
1853
- &Inst::FpuExtend { rd, rn, size } => {
1854
- let rd = allocs.next_writable(rd);
1855
- let rn = allocs.next(rn);
1856
- sink.put4(enc_fpurr(
1857
- 0b000_11110_00_1_000000_10000 | (size.ftype() << 12),
1858
- rd,
1859
- rn,
1860
- ));
1861
- }
1862
- &Inst::FpuRR {
1863
- fpu_op,
1864
- size,
1865
- rd,
1866
- rn,
1867
- } => {
1868
- let rd = allocs.next_writable(rd);
1869
- let rn = allocs.next(rn);
1870
- let top22 = match fpu_op {
1871
- FPUOp1::Abs => 0b000_11110_00_1_000001_10000,
1872
- FPUOp1::Neg => 0b000_11110_00_1_000010_10000,
1873
- FPUOp1::Sqrt => 0b000_11110_00_1_000011_10000,
1874
- FPUOp1::Cvt32To64 => {
1875
- debug_assert_eq!(size, ScalarSize::Size32);
1876
- 0b000_11110_00_1_000101_10000
1877
- }
1878
- FPUOp1::Cvt64To32 => {
1879
- debug_assert_eq!(size, ScalarSize::Size64);
1880
- 0b000_11110_01_1_000100_10000
1881
- }
1882
- };
1883
- let top22 = top22 | size.ftype() << 12;
1884
- sink.put4(enc_fpurr(top22, rd, rn));
1885
- }
1886
- &Inst::FpuRRR {
1887
- fpu_op,
1888
- size,
1889
- rd,
1890
- rn,
1891
- rm,
1892
- } => {
1893
- let rd = allocs.next_writable(rd);
1894
- let rn = allocs.next(rn);
1895
- let rm = allocs.next(rm);
1896
- let top22 = match fpu_op {
1897
- FPUOp2::Add => 0b000_11110_00_1_00000_001010,
1898
- FPUOp2::Sub => 0b000_11110_00_1_00000_001110,
1899
- FPUOp2::Mul => 0b000_11110_00_1_00000_000010,
1900
- FPUOp2::Div => 0b000_11110_00_1_00000_000110,
1901
- FPUOp2::Max => 0b000_11110_00_1_00000_010010,
1902
- FPUOp2::Min => 0b000_11110_00_1_00000_010110,
1903
- };
1904
- let top22 = top22 | size.ftype() << 12;
1905
- sink.put4(enc_fpurrr(top22, rd, rn, rm));
1906
- }
1907
- &Inst::FpuRRI { fpu_op, rd, rn } => {
1908
- let rd = allocs.next_writable(rd);
1909
- let rn = allocs.next(rn);
1910
- match fpu_op {
1911
- FPUOpRI::UShr32(imm) => {
1912
- debug_assert_eq!(32, imm.lane_size_in_bits);
1913
- sink.put4(
1914
- 0b0_0_1_011110_0000000_00_0_0_0_1_00000_00000
1915
- | imm.enc() << 16
1916
- | machreg_to_vec(rn) << 5
1917
- | machreg_to_vec(rd.to_reg()),
1918
- )
1919
- }
1920
- FPUOpRI::UShr64(imm) => {
1921
- debug_assert_eq!(64, imm.lane_size_in_bits);
1922
- sink.put4(
1923
- 0b01_1_111110_0000000_00_0_0_0_1_00000_00000
1924
- | imm.enc() << 16
1925
- | machreg_to_vec(rn) << 5
1926
- | machreg_to_vec(rd.to_reg()),
1927
- )
1928
- }
1929
- }
1930
- }
1931
- &Inst::FpuRRIMod { fpu_op, rd, ri, rn } => {
1932
- let rd = allocs.next_writable(rd);
1933
- let ri = allocs.next(ri);
1934
- let rn = allocs.next(rn);
1935
- debug_assert_eq!(rd.to_reg(), ri);
1936
- match fpu_op {
1937
- FPUOpRIMod::Sli64(imm) => {
1938
- debug_assert_eq!(64, imm.lane_size_in_bits);
1939
- sink.put4(
1940
- 0b01_1_111110_0000000_010101_00000_00000
1941
- | imm.enc() << 16
1942
- | machreg_to_vec(rn) << 5
1943
- | machreg_to_vec(rd.to_reg()),
1944
- )
1945
- }
1946
- FPUOpRIMod::Sli32(imm) => {
1947
- debug_assert_eq!(32, imm.lane_size_in_bits);
1948
- sink.put4(
1949
- 0b0_0_1_011110_0000000_010101_00000_00000
1950
- | imm.enc() << 16
1951
- | machreg_to_vec(rn) << 5
1952
- | machreg_to_vec(rd.to_reg()),
1953
- )
1954
- }
1955
- }
1956
- }
1957
- &Inst::FpuRRRR {
1958
- fpu_op,
1959
- size,
1960
- rd,
1961
- rn,
1962
- rm,
1963
- ra,
1964
- } => {
1965
- let rd = allocs.next_writable(rd);
1966
- let rn = allocs.next(rn);
1967
- let rm = allocs.next(rm);
1968
- let ra = allocs.next(ra);
1969
- let top17 = match fpu_op {
1970
- FPUOp3::MAdd => 0b000_11111_00_0_00000_0,
1971
- };
1972
- let top17 = top17 | size.ftype() << 7;
1973
- sink.put4(enc_fpurrrr(top17, rd, rn, rm, ra));
1974
- }
1975
- &Inst::VecMisc { op, rd, rn, size } => {
1976
- let rd = allocs.next_writable(rd);
1977
- let rn = allocs.next(rn);
1978
- let (q, enc_size) = size.enc_size();
1979
- let (u, bits_12_16, size) = match op {
1980
- VecMisc2::Not => (0b1, 0b00101, 0b00),
1981
- VecMisc2::Neg => (0b1, 0b01011, enc_size),
1982
- VecMisc2::Abs => (0b0, 0b01011, enc_size),
1983
- VecMisc2::Fabs => {
1984
- debug_assert!(
1985
- size == VectorSize::Size32x2
1986
- || size == VectorSize::Size32x4
1987
- || size == VectorSize::Size64x2
1988
- );
1989
- (0b0, 0b01111, enc_size)
1990
- }
1991
- VecMisc2::Fneg => {
1992
- debug_assert!(
1993
- size == VectorSize::Size32x2
1994
- || size == VectorSize::Size32x4
1995
- || size == VectorSize::Size64x2
1996
- );
1997
- (0b1, 0b01111, enc_size)
1998
- }
1999
- VecMisc2::Fsqrt => {
2000
- debug_assert!(
2001
- size == VectorSize::Size32x2
2002
- || size == VectorSize::Size32x4
2003
- || size == VectorSize::Size64x2
2004
- );
2005
- (0b1, 0b11111, enc_size)
2006
- }
2007
- VecMisc2::Rev16 => {
2008
- debug_assert_eq!(size, VectorSize::Size8x16);
2009
- (0b0, 0b00001, enc_size)
2010
- }
2011
- VecMisc2::Rev32 => {
2012
- debug_assert!(size == VectorSize::Size8x16 || size == VectorSize::Size16x8);
2013
- (0b1, 0b00000, enc_size)
2014
- }
2015
- VecMisc2::Rev64 => {
2016
- debug_assert!(
2017
- size == VectorSize::Size8x16
2018
- || size == VectorSize::Size16x8
2019
- || size == VectorSize::Size32x4
2020
- );
2021
- (0b0, 0b00000, enc_size)
2022
- }
2023
- VecMisc2::Fcvtzs => {
2024
- debug_assert!(
2025
- size == VectorSize::Size32x2
2026
- || size == VectorSize::Size32x4
2027
- || size == VectorSize::Size64x2
2028
- );
2029
- (0b0, 0b11011, enc_size)
2030
- }
2031
- VecMisc2::Fcvtzu => {
2032
- debug_assert!(
2033
- size == VectorSize::Size32x2
2034
- || size == VectorSize::Size32x4
2035
- || size == VectorSize::Size64x2
2036
- );
2037
- (0b1, 0b11011, enc_size)
2038
- }
2039
- VecMisc2::Scvtf => {
2040
- debug_assert!(size == VectorSize::Size32x4 || size == VectorSize::Size64x2);
2041
- (0b0, 0b11101, enc_size & 0b1)
2042
- }
2043
- VecMisc2::Ucvtf => {
2044
- debug_assert!(size == VectorSize::Size32x4 || size == VectorSize::Size64x2);
2045
- (0b1, 0b11101, enc_size & 0b1)
2046
- }
2047
- VecMisc2::Frintn => {
2048
- debug_assert!(
2049
- size == VectorSize::Size32x2
2050
- || size == VectorSize::Size32x4
2051
- || size == VectorSize::Size64x2
2052
- );
2053
- (0b0, 0b11000, enc_size & 0b01)
2054
- }
2055
- VecMisc2::Frintz => {
2056
- debug_assert!(
2057
- size == VectorSize::Size32x2
2058
- || size == VectorSize::Size32x4
2059
- || size == VectorSize::Size64x2
2060
- );
2061
- (0b0, 0b11001, enc_size)
2062
- }
2063
- VecMisc2::Frintm => {
2064
- debug_assert!(
2065
- size == VectorSize::Size32x2
2066
- || size == VectorSize::Size32x4
2067
- || size == VectorSize::Size64x2
2068
- );
2069
- (0b0, 0b11001, enc_size & 0b01)
2070
- }
2071
- VecMisc2::Frintp => {
2072
- debug_assert!(
2073
- size == VectorSize::Size32x2
2074
- || size == VectorSize::Size32x4
2075
- || size == VectorSize::Size64x2
2076
- );
2077
- (0b0, 0b11000, enc_size)
2078
- }
2079
- VecMisc2::Cnt => {
2080
- debug_assert!(size == VectorSize::Size8x8 || size == VectorSize::Size8x16);
2081
- (0b0, 0b00101, enc_size)
2082
- }
2083
- VecMisc2::Cmeq0 => (0b0, 0b01001, enc_size),
2084
- VecMisc2::Cmge0 => (0b1, 0b01000, enc_size),
2085
- VecMisc2::Cmgt0 => (0b0, 0b01000, enc_size),
2086
- VecMisc2::Cmle0 => (0b1, 0b01001, enc_size),
2087
- VecMisc2::Cmlt0 => (0b0, 0b01010, enc_size),
2088
- VecMisc2::Fcmeq0 => {
2089
- debug_assert!(
2090
- size == VectorSize::Size32x2
2091
- || size == VectorSize::Size32x4
2092
- || size == VectorSize::Size64x2
2093
- );
2094
- (0b0, 0b01101, enc_size)
2095
- }
2096
- VecMisc2::Fcmge0 => {
2097
- debug_assert!(
2098
- size == VectorSize::Size32x2
2099
- || size == VectorSize::Size32x4
2100
- || size == VectorSize::Size64x2
2101
- );
2102
- (0b1, 0b01100, enc_size)
2103
- }
2104
- VecMisc2::Fcmgt0 => {
2105
- debug_assert!(
2106
- size == VectorSize::Size32x2
2107
- || size == VectorSize::Size32x4
2108
- || size == VectorSize::Size64x2
2109
- );
2110
- (0b0, 0b01100, enc_size)
2111
- }
2112
- VecMisc2::Fcmle0 => {
2113
- debug_assert!(
2114
- size == VectorSize::Size32x2
2115
- || size == VectorSize::Size32x4
2116
- || size == VectorSize::Size64x2
2117
- );
2118
- (0b1, 0b01101, enc_size)
2119
- }
2120
- VecMisc2::Fcmlt0 => {
2121
- debug_assert!(
2122
- size == VectorSize::Size32x2
2123
- || size == VectorSize::Size32x4
2124
- || size == VectorSize::Size64x2
2125
- );
2126
- (0b0, 0b01110, enc_size)
2127
- }
2128
- };
2129
- sink.put4(enc_vec_rr_misc((q << 1) | u, size, bits_12_16, rd, rn));
2130
- }
2131
- &Inst::VecLanes { op, rd, rn, size } => {
2132
- let rd = allocs.next_writable(rd);
2133
- let rn = allocs.next(rn);
2134
- let (q, size) = match size {
2135
- VectorSize::Size8x8 => (0b0, 0b00),
2136
- VectorSize::Size8x16 => (0b1, 0b00),
2137
- VectorSize::Size16x4 => (0b0, 0b01),
2138
- VectorSize::Size16x8 => (0b1, 0b01),
2139
- VectorSize::Size32x4 => (0b1, 0b10),
2140
- _ => unreachable!(),
2141
- };
2142
- let (u, opcode) = match op {
2143
- VecLanesOp::Uminv => (0b1, 0b11010),
2144
- VecLanesOp::Addv => (0b0, 0b11011),
2145
- };
2146
- sink.put4(enc_vec_lanes(q, u, size, opcode, rd, rn));
2147
- }
2148
- &Inst::VecShiftImm {
2149
- op,
2150
- rd,
2151
- rn,
2152
- size,
2153
- imm,
2154
- } => {
2155
- let rd = allocs.next_writable(rd);
2156
- let rn = allocs.next(rn);
2157
- let (is_shr, mut template) = match op {
2158
- VecShiftImmOp::Ushr => (true, 0b_001_011110_0000_000_000001_00000_00000_u32),
2159
- VecShiftImmOp::Sshr => (true, 0b_000_011110_0000_000_000001_00000_00000_u32),
2160
- VecShiftImmOp::Shl => (false, 0b_000_011110_0000_000_010101_00000_00000_u32),
2161
- };
2162
- if size.is_128bits() {
2163
- template |= 0b1 << 30;
2164
- }
2165
- let imm = imm as u32;
2166
- // Deal with the somewhat strange encoding scheme for, and limits on,
2167
- // the shift amount.
2168
- let immh_immb = match (size.lane_size(), is_shr) {
2169
- (ScalarSize::Size64, true) if imm >= 1 && imm <= 64 => {
2170
- 0b_1000_000_u32 | (64 - imm)
2171
- }
2172
- (ScalarSize::Size32, true) if imm >= 1 && imm <= 32 => {
2173
- 0b_0100_000_u32 | (32 - imm)
2174
- }
2175
- (ScalarSize::Size16, true) if imm >= 1 && imm <= 16 => {
2176
- 0b_0010_000_u32 | (16 - imm)
2177
- }
2178
- (ScalarSize::Size8, true) if imm >= 1 && imm <= 8 => {
2179
- 0b_0001_000_u32 | (8 - imm)
2180
- }
2181
- (ScalarSize::Size64, false) if imm <= 63 => 0b_1000_000_u32 | imm,
2182
- (ScalarSize::Size32, false) if imm <= 31 => 0b_0100_000_u32 | imm,
2183
- (ScalarSize::Size16, false) if imm <= 15 => 0b_0010_000_u32 | imm,
2184
- (ScalarSize::Size8, false) if imm <= 7 => 0b_0001_000_u32 | imm,
2185
- _ => panic!(
2186
- "aarch64: Inst::VecShiftImm: emit: invalid op/size/imm {:?}, {:?}, {:?}",
2187
- op, size, imm
2188
- ),
2189
- };
2190
- let rn_enc = machreg_to_vec(rn);
2191
- let rd_enc = machreg_to_vec(rd.to_reg());
2192
- sink.put4(template | (immh_immb << 16) | (rn_enc << 5) | rd_enc);
2193
- }
2194
- &Inst::VecShiftImmMod {
2195
- op,
2196
- rd,
2197
- ri,
2198
- rn,
2199
- size,
2200
- imm,
2201
- } => {
2202
- let rd = allocs.next_writable(rd);
2203
- let ri = allocs.next(ri);
2204
- debug_assert_eq!(rd.to_reg(), ri);
2205
- let rn = allocs.next(rn);
2206
- let (is_shr, mut template) = match op {
2207
- VecShiftImmModOp::Sli => (false, 0b_001_011110_0000_000_010101_00000_00000_u32),
2208
- };
2209
- if size.is_128bits() {
2210
- template |= 0b1 << 30;
2211
- }
2212
- let imm = imm as u32;
2213
- // Deal with the somewhat strange encoding scheme for, and limits on,
2214
- // the shift amount.
2215
- let immh_immb = match (size.lane_size(), is_shr) {
2216
- (ScalarSize::Size64, true) if imm >= 1 && imm <= 64 => {
2217
- 0b_1000_000_u32 | (64 - imm)
2218
- }
2219
- (ScalarSize::Size32, true) if imm >= 1 && imm <= 32 => {
2220
- 0b_0100_000_u32 | (32 - imm)
2221
- }
2222
- (ScalarSize::Size16, true) if imm >= 1 && imm <= 16 => {
2223
- 0b_0010_000_u32 | (16 - imm)
2224
- }
2225
- (ScalarSize::Size8, true) if imm >= 1 && imm <= 8 => {
2226
- 0b_0001_000_u32 | (8 - imm)
2227
- }
2228
- (ScalarSize::Size64, false) if imm <= 63 => 0b_1000_000_u32 | imm,
2229
- (ScalarSize::Size32, false) if imm <= 31 => 0b_0100_000_u32 | imm,
2230
- (ScalarSize::Size16, false) if imm <= 15 => 0b_0010_000_u32 | imm,
2231
- (ScalarSize::Size8, false) if imm <= 7 => 0b_0001_000_u32 | imm,
2232
- _ => panic!(
2233
- "aarch64: Inst::VecShiftImmMod: emit: invalid op/size/imm {:?}, {:?}, {:?}",
2234
- op, size, imm
2235
- ),
2236
- };
2237
- let rn_enc = machreg_to_vec(rn);
2238
- let rd_enc = machreg_to_vec(rd.to_reg());
2239
- sink.put4(template | (immh_immb << 16) | (rn_enc << 5) | rd_enc);
2240
- }
2241
- &Inst::VecExtract { rd, rn, rm, imm4 } => {
2242
- let rd = allocs.next_writable(rd);
2243
- let rn = allocs.next(rn);
2244
- let rm = allocs.next(rm);
2245
- if imm4 < 16 {
2246
- let template = 0b_01_101110_000_00000_0_0000_0_00000_00000_u32;
2247
- let rm_enc = machreg_to_vec(rm);
2248
- let rn_enc = machreg_to_vec(rn);
2249
- let rd_enc = machreg_to_vec(rd.to_reg());
2250
- sink.put4(
2251
- template | (rm_enc << 16) | ((imm4 as u32) << 11) | (rn_enc << 5) | rd_enc,
2252
- );
2253
- } else {
2254
- panic!(
2255
- "aarch64: Inst::VecExtract: emit: invalid extract index {}",
2256
- imm4
2257
- );
2258
- }
2259
- }
2260
- &Inst::VecTbl { rd, rn, rm } => {
2261
- let rn = allocs.next(rn);
2262
- let rm = allocs.next(rm);
2263
- let rd = allocs.next_writable(rd);
2264
- sink.put4(enc_tbl(/* is_extension = */ false, 0b00, rd, rn, rm));
2265
- }
2266
- &Inst::VecTblExt { rd, ri, rn, rm } => {
2267
- let rn = allocs.next(rn);
2268
- let rm = allocs.next(rm);
2269
- let rd = allocs.next_writable(rd);
2270
- let ri = allocs.next(ri);
2271
- debug_assert_eq!(rd.to_reg(), ri);
2272
- sink.put4(enc_tbl(/* is_extension = */ true, 0b00, rd, rn, rm));
2273
- }
2274
- &Inst::VecTbl2 { rd, rn, rn2, rm } => {
2275
- let rn = allocs.next(rn);
2276
- let rn2 = allocs.next(rn2);
2277
- let rm = allocs.next(rm);
2278
- let rd = allocs.next_writable(rd);
2279
- assert_eq!(machreg_to_vec(rn2), (machreg_to_vec(rn) + 1) % 32);
2280
- sink.put4(enc_tbl(/* is_extension = */ false, 0b01, rd, rn, rm));
2281
- }
2282
- &Inst::VecTbl2Ext {
2283
- rd,
2284
- ri,
2285
- rn,
2286
- rn2,
2287
- rm,
2288
- } => {
2289
- let rn = allocs.next(rn);
2290
- let rn2 = allocs.next(rn2);
2291
- let rm = allocs.next(rm);
2292
- let rd = allocs.next_writable(rd);
2293
- let ri = allocs.next(ri);
2294
- debug_assert_eq!(rd.to_reg(), ri);
2295
- assert_eq!(machreg_to_vec(rn2), (machreg_to_vec(rn) + 1) % 32);
2296
- sink.put4(enc_tbl(/* is_extension = */ true, 0b01, rd, rn, rm));
2297
- }
2298
- &Inst::FpuCmp { size, rn, rm } => {
2299
- let rn = allocs.next(rn);
2300
- let rm = allocs.next(rm);
2301
- sink.put4(enc_fcmp(size, rn, rm));
2302
- }
2303
- &Inst::FpuToInt { op, rd, rn } => {
2304
- let rd = allocs.next_writable(rd);
2305
- let rn = allocs.next(rn);
2306
- let top16 = match op {
2307
- // FCVTZS (32/32-bit)
2308
- FpuToIntOp::F32ToI32 => 0b000_11110_00_1_11_000,
2309
- // FCVTZU (32/32-bit)
2310
- FpuToIntOp::F32ToU32 => 0b000_11110_00_1_11_001,
2311
- // FCVTZS (32/64-bit)
2312
- FpuToIntOp::F32ToI64 => 0b100_11110_00_1_11_000,
2313
- // FCVTZU (32/64-bit)
2314
- FpuToIntOp::F32ToU64 => 0b100_11110_00_1_11_001,
2315
- // FCVTZS (64/32-bit)
2316
- FpuToIntOp::F64ToI32 => 0b000_11110_01_1_11_000,
2317
- // FCVTZU (64/32-bit)
2318
- FpuToIntOp::F64ToU32 => 0b000_11110_01_1_11_001,
2319
- // FCVTZS (64/64-bit)
2320
- FpuToIntOp::F64ToI64 => 0b100_11110_01_1_11_000,
2321
- // FCVTZU (64/64-bit)
2322
- FpuToIntOp::F64ToU64 => 0b100_11110_01_1_11_001,
2323
- };
2324
- sink.put4(enc_fputoint(top16, rd, rn));
2325
- }
2326
- &Inst::IntToFpu { op, rd, rn } => {
2327
- let rd = allocs.next_writable(rd);
2328
- let rn = allocs.next(rn);
2329
- let top16 = match op {
2330
- // SCVTF (32/32-bit)
2331
- IntToFpuOp::I32ToF32 => 0b000_11110_00_1_00_010,
2332
- // UCVTF (32/32-bit)
2333
- IntToFpuOp::U32ToF32 => 0b000_11110_00_1_00_011,
2334
- // SCVTF (64/32-bit)
2335
- IntToFpuOp::I64ToF32 => 0b100_11110_00_1_00_010,
2336
- // UCVTF (64/32-bit)
2337
- IntToFpuOp::U64ToF32 => 0b100_11110_00_1_00_011,
2338
- // SCVTF (32/64-bit)
2339
- IntToFpuOp::I32ToF64 => 0b000_11110_01_1_00_010,
2340
- // UCVTF (32/64-bit)
2341
- IntToFpuOp::U32ToF64 => 0b000_11110_01_1_00_011,
2342
- // SCVTF (64/64-bit)
2343
- IntToFpuOp::I64ToF64 => 0b100_11110_01_1_00_010,
2344
- // UCVTF (64/64-bit)
2345
- IntToFpuOp::U64ToF64 => 0b100_11110_01_1_00_011,
2346
- };
2347
- sink.put4(enc_inttofpu(top16, rd, rn));
2348
- }
2349
- &Inst::FpuCSel32 { rd, rn, rm, cond } => {
2350
- let rd = allocs.next_writable(rd);
2351
- let rn = allocs.next(rn);
2352
- let rm = allocs.next(rm);
2353
- sink.put4(enc_fcsel(rd, rn, rm, cond, ScalarSize::Size32));
2354
- }
2355
- &Inst::FpuCSel64 { rd, rn, rm, cond } => {
2356
- let rd = allocs.next_writable(rd);
2357
- let rn = allocs.next(rn);
2358
- let rm = allocs.next(rm);
2359
- sink.put4(enc_fcsel(rd, rn, rm, cond, ScalarSize::Size64));
2360
- }
2361
- &Inst::FpuRound { op, rd, rn } => {
2362
- let rd = allocs.next_writable(rd);
2363
- let rn = allocs.next(rn);
2364
- let top22 = match op {
2365
- FpuRoundMode::Minus32 => 0b000_11110_00_1_001_010_10000,
2366
- FpuRoundMode::Minus64 => 0b000_11110_01_1_001_010_10000,
2367
- FpuRoundMode::Plus32 => 0b000_11110_00_1_001_001_10000,
2368
- FpuRoundMode::Plus64 => 0b000_11110_01_1_001_001_10000,
2369
- FpuRoundMode::Zero32 => 0b000_11110_00_1_001_011_10000,
2370
- FpuRoundMode::Zero64 => 0b000_11110_01_1_001_011_10000,
2371
- FpuRoundMode::Nearest32 => 0b000_11110_00_1_001_000_10000,
2372
- FpuRoundMode::Nearest64 => 0b000_11110_01_1_001_000_10000,
2373
- };
2374
- sink.put4(enc_fround(top22, rd, rn));
2375
- }
2376
- &Inst::MovToFpu { rd, rn, size } => {
2377
- let rd = allocs.next_writable(rd);
2378
- let rn = allocs.next(rn);
2379
- let template = match size {
2380
- ScalarSize::Size32 => 0b000_11110_00_1_00_111_000000_00000_00000,
2381
- ScalarSize::Size64 => 0b100_11110_01_1_00_111_000000_00000_00000,
2382
- _ => unreachable!(),
2383
- };
2384
- sink.put4(template | (machreg_to_gpr(rn) << 5) | machreg_to_vec(rd.to_reg()));
2385
- }
2386
- &Inst::FpuMoveFPImm { rd, imm, size } => {
2387
- let rd = allocs.next_writable(rd);
2388
- let size_code = match size {
2389
- ScalarSize::Size32 => 0b00,
2390
- ScalarSize::Size64 => 0b01,
2391
- _ => unimplemented!(),
2392
- };
2393
- sink.put4(
2394
- 0b000_11110_00_1_00_000_000100_00000_00000
2395
- | size_code << 22
2396
- | ((imm.enc_bits() as u32) << 13)
2397
- | machreg_to_vec(rd.to_reg()),
2398
- );
2399
- }
2400
- &Inst::MovToVec {
2401
- rd,
2402
- ri,
2403
- rn,
2404
- idx,
2405
- size,
2406
- } => {
2407
- let rd = allocs.next_writable(rd);
2408
- let ri = allocs.next(ri);
2409
- debug_assert_eq!(rd.to_reg(), ri);
2410
- let rn = allocs.next(rn);
2411
- let (imm5, shift) = match size.lane_size() {
2412
- ScalarSize::Size8 => (0b00001, 1),
2413
- ScalarSize::Size16 => (0b00010, 2),
2414
- ScalarSize::Size32 => (0b00100, 3),
2415
- ScalarSize::Size64 => (0b01000, 4),
2416
- _ => unreachable!(),
2417
- };
2418
- debug_assert_eq!(idx & (0b11111 >> shift), idx);
2419
- let imm5 = imm5 | ((idx as u32) << shift);
2420
- sink.put4(
2421
- 0b010_01110000_00000_0_0011_1_00000_00000
2422
- | (imm5 << 16)
2423
- | (machreg_to_gpr(rn) << 5)
2424
- | machreg_to_vec(rd.to_reg()),
2425
- );
2426
- }
2427
- &Inst::MovFromVec { rd, rn, idx, size } => {
2428
- let rd = allocs.next_writable(rd);
2429
- let rn = allocs.next(rn);
2430
- let (q, imm5, shift, mask) = match size {
2431
- ScalarSize::Size8 => (0b0, 0b00001, 1, 0b1111),
2432
- ScalarSize::Size16 => (0b0, 0b00010, 2, 0b0111),
2433
- ScalarSize::Size32 => (0b0, 0b00100, 3, 0b0011),
2434
- ScalarSize::Size64 => (0b1, 0b01000, 4, 0b0001),
2435
- _ => panic!("Unexpected scalar FP operand size: {:?}", size),
2436
- };
2437
- debug_assert_eq!(idx & mask, idx);
2438
- let imm5 = imm5 | ((idx as u32) << shift);
2439
- sink.put4(
2440
- 0b000_01110000_00000_0_0111_1_00000_00000
2441
- | (q << 30)
2442
- | (imm5 << 16)
2443
- | (machreg_to_vec(rn) << 5)
2444
- | machreg_to_gpr(rd.to_reg()),
2445
- );
2446
- }
2447
- &Inst::MovFromVecSigned {
2448
- rd,
2449
- rn,
2450
- idx,
2451
- size,
2452
- scalar_size,
2453
- } => {
2454
- let rd = allocs.next_writable(rd);
2455
- let rn = allocs.next(rn);
2456
- let (imm5, shift, half) = match size {
2457
- VectorSize::Size8x8 => (0b00001, 1, true),
2458
- VectorSize::Size8x16 => (0b00001, 1, false),
2459
- VectorSize::Size16x4 => (0b00010, 2, true),
2460
- VectorSize::Size16x8 => (0b00010, 2, false),
2461
- VectorSize::Size32x2 => {
2462
- debug_assert_ne!(scalar_size, OperandSize::Size32);
2463
- (0b00100, 3, true)
2464
- }
2465
- VectorSize::Size32x4 => {
2466
- debug_assert_ne!(scalar_size, OperandSize::Size32);
2467
- (0b00100, 3, false)
2468
- }
2469
- _ => panic!("Unexpected vector operand size"),
2470
- };
2471
- debug_assert_eq!(idx & (0b11111 >> (half as u32 + shift)), idx);
2472
- let imm5 = imm5 | ((idx as u32) << shift);
2473
- sink.put4(
2474
- 0b000_01110000_00000_0_0101_1_00000_00000
2475
- | (scalar_size.is64() as u32) << 30
2476
- | (imm5 << 16)
2477
- | (machreg_to_vec(rn) << 5)
2478
- | machreg_to_gpr(rd.to_reg()),
2479
- );
2480
- }
2481
- &Inst::VecDup { rd, rn, size } => {
2482
- let rd = allocs.next_writable(rd);
2483
- let rn = allocs.next(rn);
2484
- let q = size.is_128bits() as u32;
2485
- let imm5 = match size.lane_size() {
2486
- ScalarSize::Size8 => 0b00001,
2487
- ScalarSize::Size16 => 0b00010,
2488
- ScalarSize::Size32 => 0b00100,
2489
- ScalarSize::Size64 => 0b01000,
2490
- _ => unreachable!(),
2491
- };
2492
- sink.put4(
2493
- 0b0_0_0_01110000_00000_000011_00000_00000
2494
- | (q << 30)
2495
- | (imm5 << 16)
2496
- | (machreg_to_gpr(rn) << 5)
2497
- | machreg_to_vec(rd.to_reg()),
2498
- );
2499
- }
2500
- &Inst::VecDupFromFpu { rd, rn, size, lane } => {
2501
- let rd = allocs.next_writable(rd);
2502
- let rn = allocs.next(rn);
2503
- let q = size.is_128bits() as u32;
2504
- let imm5 = match size.lane_size() {
2505
- ScalarSize::Size8 => {
2506
- assert!(lane < 16);
2507
- 0b00001 | (u32::from(lane) << 1)
2508
- }
2509
- ScalarSize::Size16 => {
2510
- assert!(lane < 8);
2511
- 0b00010 | (u32::from(lane) << 2)
2512
- }
2513
- ScalarSize::Size32 => {
2514
- assert!(lane < 4);
2515
- 0b00100 | (u32::from(lane) << 3)
2516
- }
2517
- ScalarSize::Size64 => {
2518
- assert!(lane < 2);
2519
- 0b01000 | (u32::from(lane) << 4)
2520
- }
2521
- _ => unimplemented!(),
2522
- };
2523
- sink.put4(
2524
- 0b000_01110000_00000_000001_00000_00000
2525
- | (q << 30)
2526
- | (imm5 << 16)
2527
- | (machreg_to_vec(rn) << 5)
2528
- | machreg_to_vec(rd.to_reg()),
2529
- );
2530
- }
2531
- &Inst::VecDupFPImm { rd, imm, size } => {
2532
- let rd = allocs.next_writable(rd);
2533
- let imm = imm.enc_bits();
2534
- let op = match size.lane_size() {
2535
- ScalarSize::Size32 => 0,
2536
- ScalarSize::Size64 => 1,
2537
- _ => unimplemented!(),
2538
- };
2539
- let q_op = op | ((size.is_128bits() as u32) << 1);
2540
-
2541
- sink.put4(enc_asimd_mod_imm(rd, q_op, 0b1111, imm));
2542
- }
2543
- &Inst::VecDupImm {
2544
- rd,
2545
- imm,
2546
- invert,
2547
- size,
2548
- } => {
2549
- let rd = allocs.next_writable(rd);
2550
- let (imm, shift, shift_ones) = imm.value();
2551
- let (op, cmode) = match size.lane_size() {
2552
- ScalarSize::Size8 => {
2553
- assert!(!invert);
2554
- assert_eq!(shift, 0);
2555
-
2556
- (0, 0b1110)
2557
- }
2558
- ScalarSize::Size16 => {
2559
- let s = shift & 8;
2560
-
2561
- assert!(!shift_ones);
2562
- assert_eq!(s, shift);
2563
-
2564
- (invert as u32, 0b1000 | (s >> 2))
2565
- }
2566
- ScalarSize::Size32 => {
2567
- if shift_ones {
2568
- assert!(shift == 8 || shift == 16);
2569
-
2570
- (invert as u32, 0b1100 | (shift >> 4))
2571
- } else {
2572
- let s = shift & 24;
2573
-
2574
- assert_eq!(s, shift);
2575
-
2576
- (invert as u32, 0b0000 | (s >> 2))
2577
- }
2578
- }
2579
- ScalarSize::Size64 => {
2580
- assert!(!invert);
2581
- assert_eq!(shift, 0);
2582
-
2583
- (1, 0b1110)
2584
- }
2585
- _ => unreachable!(),
2586
- };
2587
- let q_op = op | ((size.is_128bits() as u32) << 1);
2588
-
2589
- sink.put4(enc_asimd_mod_imm(rd, q_op, cmode, imm));
2590
- }
2591
- &Inst::VecExtend {
2592
- t,
2593
- rd,
2594
- rn,
2595
- high_half,
2596
- lane_size,
2597
- } => {
2598
- let rd = allocs.next_writable(rd);
2599
- let rn = allocs.next(rn);
2600
- let immh = match lane_size {
2601
- ScalarSize::Size16 => 0b001,
2602
- ScalarSize::Size32 => 0b010,
2603
- ScalarSize::Size64 => 0b100,
2604
- _ => panic!("Unexpected VecExtend to lane size of {:?}", lane_size),
2605
- };
2606
- let u = match t {
2607
- VecExtendOp::Sxtl => 0b0,
2608
- VecExtendOp::Uxtl => 0b1,
2609
- };
2610
- sink.put4(
2611
- 0b000_011110_0000_000_101001_00000_00000
2612
- | ((high_half as u32) << 30)
2613
- | (u << 29)
2614
- | (immh << 19)
2615
- | (machreg_to_vec(rn) << 5)
2616
- | machreg_to_vec(rd.to_reg()),
2617
- );
2618
- }
2619
- &Inst::VecRRLong {
2620
- op,
2621
- rd,
2622
- rn,
2623
- high_half,
2624
- } => {
2625
- let rd = allocs.next_writable(rd);
2626
- let rn = allocs.next(rn);
2627
- let (u, size, bits_12_16) = match op {
2628
- VecRRLongOp::Fcvtl16 => (0b0, 0b00, 0b10111),
2629
- VecRRLongOp::Fcvtl32 => (0b0, 0b01, 0b10111),
2630
- VecRRLongOp::Shll8 => (0b1, 0b00, 0b10011),
2631
- VecRRLongOp::Shll16 => (0b1, 0b01, 0b10011),
2632
- VecRRLongOp::Shll32 => (0b1, 0b10, 0b10011),
2633
- };
2634
-
2635
- sink.put4(enc_vec_rr_misc(
2636
- ((high_half as u32) << 1) | u,
2637
- size,
2638
- bits_12_16,
2639
- rd,
2640
- rn,
2641
- ));
2642
- }
2643
- &Inst::VecRRNarrowLow {
2644
- op,
2645
- rd,
2646
- rn,
2647
- lane_size,
2648
- }
2649
- | &Inst::VecRRNarrowHigh {
2650
- op,
2651
- rd,
2652
- rn,
2653
- lane_size,
2654
- ..
2655
- } => {
2656
- let rn = allocs.next(rn);
2657
- let rd = allocs.next_writable(rd);
2658
- let high_half = match self {
2659
- &Inst::VecRRNarrowLow { .. } => false,
2660
- &Inst::VecRRNarrowHigh { .. } => true,
2661
- _ => unreachable!(),
2662
- };
2663
-
2664
- let size = match lane_size {
2665
- ScalarSize::Size8 => 0b00,
2666
- ScalarSize::Size16 => 0b01,
2667
- ScalarSize::Size32 => 0b10,
2668
- _ => panic!("unsupported size: {:?}", lane_size),
2669
- };
2670
-
2671
- // Floats use a single bit, to encode either half or single.
2672
- let size = match op {
2673
- VecRRNarrowOp::Fcvtn => size >> 1,
2674
- _ => size,
2675
- };
2676
-
2677
- let (u, bits_12_16) = match op {
2678
- VecRRNarrowOp::Xtn => (0b0, 0b10010),
2679
- VecRRNarrowOp::Sqxtn => (0b0, 0b10100),
2680
- VecRRNarrowOp::Sqxtun => (0b1, 0b10010),
2681
- VecRRNarrowOp::Uqxtn => (0b1, 0b10100),
2682
- VecRRNarrowOp::Fcvtn => (0b0, 0b10110),
2683
- };
2684
-
2685
- sink.put4(enc_vec_rr_misc(
2686
- ((high_half as u32) << 1) | u,
2687
- size,
2688
- bits_12_16,
2689
- rd,
2690
- rn,
2691
- ));
2692
- }
2693
- &Inst::VecMovElement {
2694
- rd,
2695
- ri,
2696
- rn,
2697
- dest_idx,
2698
- src_idx,
2699
- size,
2700
- } => {
2701
- let rd = allocs.next_writable(rd);
2702
- let ri = allocs.next(ri);
2703
- debug_assert_eq!(rd.to_reg(), ri);
2704
- let rn = allocs.next(rn);
2705
- let (imm5, shift) = match size.lane_size() {
2706
- ScalarSize::Size8 => (0b00001, 1),
2707
- ScalarSize::Size16 => (0b00010, 2),
2708
- ScalarSize::Size32 => (0b00100, 3),
2709
- ScalarSize::Size64 => (0b01000, 4),
2710
- _ => unreachable!(),
2711
- };
2712
- let mask = 0b11111 >> shift;
2713
- debug_assert_eq!(dest_idx & mask, dest_idx);
2714
- debug_assert_eq!(src_idx & mask, src_idx);
2715
- let imm4 = (src_idx as u32) << (shift - 1);
2716
- let imm5 = imm5 | ((dest_idx as u32) << shift);
2717
- sink.put4(
2718
- 0b011_01110000_00000_0_0000_1_00000_00000
2719
- | (imm5 << 16)
2720
- | (imm4 << 11)
2721
- | (machreg_to_vec(rn) << 5)
2722
- | machreg_to_vec(rd.to_reg()),
2723
- );
2724
- }
2725
- &Inst::VecRRPair { op, rd, rn } => {
2726
- let rd = allocs.next_writable(rd);
2727
- let rn = allocs.next(rn);
2728
- let bits_12_16 = match op {
2729
- VecPairOp::Addp => 0b11011,
2730
- };
2731
-
2732
- sink.put4(enc_vec_rr_pair(bits_12_16, rd, rn));
2733
- }
2734
- &Inst::VecRRRLong {
2735
- rd,
2736
- rn,
2737
- rm,
2738
- alu_op,
2739
- high_half,
2740
- } => {
2741
- let rd = allocs.next_writable(rd);
2742
- let rn = allocs.next(rn);
2743
- let rm = allocs.next(rm);
2744
- let (u, size, bit14) = match alu_op {
2745
- VecRRRLongOp::Smull8 => (0b0, 0b00, 0b1),
2746
- VecRRRLongOp::Smull16 => (0b0, 0b01, 0b1),
2747
- VecRRRLongOp::Smull32 => (0b0, 0b10, 0b1),
2748
- VecRRRLongOp::Umull8 => (0b1, 0b00, 0b1),
2749
- VecRRRLongOp::Umull16 => (0b1, 0b01, 0b1),
2750
- VecRRRLongOp::Umull32 => (0b1, 0b10, 0b1),
2751
- };
2752
- sink.put4(enc_vec_rrr_long(
2753
- high_half as u32,
2754
- u,
2755
- size,
2756
- bit14,
2757
- rm,
2758
- rn,
2759
- rd,
2760
- ));
2761
- }
2762
- &Inst::VecRRRLongMod {
2763
- rd,
2764
- ri,
2765
- rn,
2766
- rm,
2767
- alu_op,
2768
- high_half,
2769
- } => {
2770
- let rd = allocs.next_writable(rd);
2771
- let ri = allocs.next(ri);
2772
- debug_assert_eq!(rd.to_reg(), ri);
2773
- let rn = allocs.next(rn);
2774
- let rm = allocs.next(rm);
2775
- let (u, size, bit14) = match alu_op {
2776
- VecRRRLongModOp::Umlal8 => (0b1, 0b00, 0b0),
2777
- VecRRRLongModOp::Umlal16 => (0b1, 0b01, 0b0),
2778
- VecRRRLongModOp::Umlal32 => (0b1, 0b10, 0b0),
2779
- };
2780
- sink.put4(enc_vec_rrr_long(
2781
- high_half as u32,
2782
- u,
2783
- size,
2784
- bit14,
2785
- rm,
2786
- rn,
2787
- rd,
2788
- ));
2789
- }
2790
- &Inst::VecRRPairLong { op, rd, rn } => {
2791
- let rd = allocs.next_writable(rd);
2792
- let rn = allocs.next(rn);
2793
- let (u, size) = match op {
2794
- VecRRPairLongOp::Saddlp8 => (0b0, 0b0),
2795
- VecRRPairLongOp::Uaddlp8 => (0b1, 0b0),
2796
- VecRRPairLongOp::Saddlp16 => (0b0, 0b1),
2797
- VecRRPairLongOp::Uaddlp16 => (0b1, 0b1),
2798
- };
2799
-
2800
- sink.put4(enc_vec_rr_pair_long(u, size, rd, rn));
2801
- }
2802
- &Inst::VecRRR {
2803
- rd,
2804
- rn,
2805
- rm,
2806
- alu_op,
2807
- size,
2808
- } => {
2809
- let rd = allocs.next_writable(rd);
2810
- let rn = allocs.next(rn);
2811
- let rm = allocs.next(rm);
2812
- let (q, enc_size) = size.enc_size();
2813
- let is_float = match alu_op {
2814
- VecALUOp::Fcmeq
2815
- | VecALUOp::Fcmgt
2816
- | VecALUOp::Fcmge
2817
- | VecALUOp::Fadd
2818
- | VecALUOp::Fsub
2819
- | VecALUOp::Fdiv
2820
- | VecALUOp::Fmax
2821
- | VecALUOp::Fmin
2822
- | VecALUOp::Fmul => true,
2823
- _ => false,
2824
- };
2825
-
2826
- let (top11, bit15_10) = match alu_op {
2827
- VecALUOp::Sqadd => (0b000_01110_00_1 | enc_size << 1, 0b000011),
2828
- VecALUOp::Sqsub => (0b000_01110_00_1 | enc_size << 1, 0b001011),
2829
- VecALUOp::Uqadd => (0b001_01110_00_1 | enc_size << 1, 0b000011),
2830
- VecALUOp::Uqsub => (0b001_01110_00_1 | enc_size << 1, 0b001011),
2831
- VecALUOp::Cmeq => (0b001_01110_00_1 | enc_size << 1, 0b100011),
2832
- VecALUOp::Cmge => (0b000_01110_00_1 | enc_size << 1, 0b001111),
2833
- VecALUOp::Cmgt => (0b000_01110_00_1 | enc_size << 1, 0b001101),
2834
- VecALUOp::Cmhi => (0b001_01110_00_1 | enc_size << 1, 0b001101),
2835
- VecALUOp::Cmhs => (0b001_01110_00_1 | enc_size << 1, 0b001111),
2836
- VecALUOp::Fcmeq => (0b000_01110_00_1, 0b111001),
2837
- VecALUOp::Fcmgt => (0b001_01110_10_1, 0b111001),
2838
- VecALUOp::Fcmge => (0b001_01110_00_1, 0b111001),
2839
- // The following logical instructions operate on bytes, so are not encoded differently
2840
- // for the different vector types.
2841
- VecALUOp::And => (0b000_01110_00_1, 0b000111),
2842
- VecALUOp::Bic => (0b000_01110_01_1, 0b000111),
2843
- VecALUOp::Orr => (0b000_01110_10_1, 0b000111),
2844
- VecALUOp::Eor => (0b001_01110_00_1, 0b000111),
2845
- VecALUOp::Umaxp => {
2846
- debug_assert_ne!(size, VectorSize::Size64x2);
2847
-
2848
- (0b001_01110_00_1 | enc_size << 1, 0b101001)
2849
- }
2850
- VecALUOp::Add => (0b000_01110_00_1 | enc_size << 1, 0b100001),
2851
- VecALUOp::Sub => (0b001_01110_00_1 | enc_size << 1, 0b100001),
2852
- VecALUOp::Mul => {
2853
- debug_assert_ne!(size, VectorSize::Size64x2);
2854
- (0b000_01110_00_1 | enc_size << 1, 0b100111)
2855
- }
2856
- VecALUOp::Sshl => (0b000_01110_00_1 | enc_size << 1, 0b010001),
2857
- VecALUOp::Ushl => (0b001_01110_00_1 | enc_size << 1, 0b010001),
2858
- VecALUOp::Umin => {
2859
- debug_assert_ne!(size, VectorSize::Size64x2);
2860
-
2861
- (0b001_01110_00_1 | enc_size << 1, 0b011011)
2862
- }
2863
- VecALUOp::Smin => {
2864
- debug_assert_ne!(size, VectorSize::Size64x2);
2865
-
2866
- (0b000_01110_00_1 | enc_size << 1, 0b011011)
2867
- }
2868
- VecALUOp::Umax => {
2869
- debug_assert_ne!(size, VectorSize::Size64x2);
2870
-
2871
- (0b001_01110_00_1 | enc_size << 1, 0b011001)
2872
- }
2873
- VecALUOp::Smax => {
2874
- debug_assert_ne!(size, VectorSize::Size64x2);
2875
-
2876
- (0b000_01110_00_1 | enc_size << 1, 0b011001)
2877
- }
2878
- VecALUOp::Urhadd => {
2879
- debug_assert_ne!(size, VectorSize::Size64x2);
2880
-
2881
- (0b001_01110_00_1 | enc_size << 1, 0b000101)
2882
- }
2883
- VecALUOp::Fadd => (0b000_01110_00_1, 0b110101),
2884
- VecALUOp::Fsub => (0b000_01110_10_1, 0b110101),
2885
- VecALUOp::Fdiv => (0b001_01110_00_1, 0b111111),
2886
- VecALUOp::Fmax => (0b000_01110_00_1, 0b111101),
2887
- VecALUOp::Fmin => (0b000_01110_10_1, 0b111101),
2888
- VecALUOp::Fmul => (0b001_01110_00_1, 0b110111),
2889
- VecALUOp::Addp => (0b000_01110_00_1 | enc_size << 1, 0b101111),
2890
- VecALUOp::Zip1 => (0b01001110_00_0 | enc_size << 1, 0b001110),
2891
- VecALUOp::Zip2 => (0b01001110_00_0 | enc_size << 1, 0b011110),
2892
- VecALUOp::Sqrdmulh => {
2893
- debug_assert!(
2894
- size.lane_size() == ScalarSize::Size16
2895
- || size.lane_size() == ScalarSize::Size32
2896
- );
2897
-
2898
- (0b001_01110_00_1 | enc_size << 1, 0b101101)
2899
- }
2900
- VecALUOp::Uzp1 => (0b01001110_00_0 | enc_size << 1, 0b000110),
2901
- VecALUOp::Uzp2 => (0b01001110_00_0 | enc_size << 1, 0b010110),
2902
- VecALUOp::Trn1 => (0b01001110_00_0 | enc_size << 1, 0b001010),
2903
- VecALUOp::Trn2 => (0b01001110_00_0 | enc_size << 1, 0b011010),
2904
- };
2905
- let top11 = if is_float {
2906
- top11 | size.enc_float_size() << 1
2907
- } else {
2908
- top11
2909
- };
2910
- sink.put4(enc_vec_rrr(top11 | q << 9, rm, bit15_10, rn, rd));
2911
- }
2912
- &Inst::VecRRRMod {
2913
- rd,
2914
- ri,
2915
- rn,
2916
- rm,
2917
- alu_op,
2918
- size,
2919
- } => {
2920
- let rd = allocs.next_writable(rd);
2921
- let ri = allocs.next(ri);
2922
- debug_assert_eq!(rd.to_reg(), ri);
2923
- let rn = allocs.next(rn);
2924
- let rm = allocs.next(rm);
2925
- let (q, _enc_size) = size.enc_size();
2926
-
2927
- let (top11, bit15_10) = match alu_op {
2928
- VecALUModOp::Bsl => (0b001_01110_01_1, 0b000111),
2929
- VecALUModOp::Fmla => {
2930
- (0b000_01110_00_1 | (size.enc_float_size() << 1), 0b110011)
2931
- }
2932
- VecALUModOp::Fmls => {
2933
- (0b000_01110_10_1 | (size.enc_float_size() << 1), 0b110011)
2934
- }
2935
- };
2936
- sink.put4(enc_vec_rrr(top11 | q << 9, rm, bit15_10, rn, rd));
2937
- }
2938
- &Inst::VecFmlaElem {
2939
- rd,
2940
- ri,
2941
- rn,
2942
- rm,
2943
- alu_op,
2944
- size,
2945
- idx,
2946
- } => {
2947
- let rd = allocs.next_writable(rd);
2948
- let ri = allocs.next(ri);
2949
- debug_assert_eq!(rd.to_reg(), ri);
2950
- let rn = allocs.next(rn);
2951
- let rm = allocs.next(rm);
2952
- let idx = u32::from(idx);
2953
-
2954
- let (q, _size) = size.enc_size();
2955
- let o2 = match alu_op {
2956
- VecALUModOp::Fmla => 0b0,
2957
- VecALUModOp::Fmls => 0b1,
2958
- _ => unreachable!(),
2959
- };
2960
-
2961
- let (h, l) = match size {
2962
- VectorSize::Size32x4 => {
2963
- assert!(idx < 4);
2964
- (idx >> 1, idx & 1)
2965
- }
2966
- VectorSize::Size64x2 => {
2967
- assert!(idx < 2);
2968
- (idx, 0)
2969
- }
2970
- _ => unreachable!(),
2971
- };
2972
-
2973
- let top11 = 0b000_011111_00 | (q << 9) | (size.enc_float_size() << 1) | l;
2974
- let bit15_10 = 0b000100 | (o2 << 4) | (h << 1);
2975
- sink.put4(enc_vec_rrr(top11, rm, bit15_10, rn, rd));
2976
- }
2977
- &Inst::VecLoadReplicate {
2978
- rd,
2979
- rn,
2980
- size,
2981
- flags,
2982
- } => {
2983
- let rd = allocs.next_writable(rd);
2984
- let rn = allocs.next(rn);
2985
- let (q, size) = size.enc_size();
2986
-
2987
- let srcloc = state.cur_srcloc();
2988
- if !srcloc.is_default() && !flags.notrap() {
2989
- // Register the offset at which the actual load instruction starts.
2990
- sink.add_trap(TrapCode::HeapOutOfBounds);
2991
- }
2992
-
2993
- sink.put4(enc_ldst_vec(q, size, rn, rd));
2994
- }
2995
- &Inst::VecCSel { rd, rn, rm, cond } => {
2996
- let rd = allocs.next_writable(rd);
2997
- let rn = allocs.next(rn);
2998
- let rm = allocs.next(rm);
2999
- /* Emit this:
3000
- b.cond else
3001
- mov rd, rm
3002
- b out
3003
- else:
3004
- mov rd, rn
3005
- out:
3006
-
3007
- Note, we could do better in the cases where rd == rn or rd == rm.
3008
- */
3009
- let else_label = sink.get_label();
3010
- let out_label = sink.get_label();
3011
-
3012
- // b.cond else
3013
- let br_else_offset = sink.cur_offset();
3014
- sink.put4(enc_conditional_br(
3015
- BranchTarget::Label(else_label),
3016
- CondBrKind::Cond(cond),
3017
- &mut AllocationConsumer::default(),
3018
- ));
3019
- sink.use_label_at_offset(br_else_offset, else_label, LabelUse::Branch19);
3020
-
3021
- // mov rd, rm
3022
- sink.put4(enc_vecmov(/* 16b = */ true, rd, rm));
3023
-
3024
- // b out
3025
- let b_out_offset = sink.cur_offset();
3026
- sink.use_label_at_offset(b_out_offset, out_label, LabelUse::Branch26);
3027
- sink.add_uncond_branch(b_out_offset, b_out_offset + 4, out_label);
3028
- sink.put4(enc_jump26(0b000101, 0 /* will be fixed up later */));
3029
-
3030
- // else:
3031
- sink.bind_label(else_label, &mut state.ctrl_plane);
3032
-
3033
- // mov rd, rn
3034
- sink.put4(enc_vecmov(/* 16b = */ true, rd, rn));
3035
-
3036
- // out:
3037
- sink.bind_label(out_label, &mut state.ctrl_plane);
3038
- }
3039
- &Inst::MovToNZCV { rn } => {
3040
- let rn = allocs.next(rn);
3041
- sink.put4(0xd51b4200 | machreg_to_gpr(rn));
3042
- }
3043
- &Inst::MovFromNZCV { rd } => {
3044
- let rd = allocs.next_writable(rd);
3045
- sink.put4(0xd53b4200 | machreg_to_gpr(rd.to_reg()));
3046
- }
3047
- &Inst::Extend {
3048
- rd,
3049
- rn,
3050
- signed: false,
3051
- from_bits: 1,
3052
- to_bits,
3053
- } => {
3054
- let rd = allocs.next_writable(rd);
3055
- let rn = allocs.next(rn);
3056
- assert!(to_bits <= 64);
3057
- // Reduce zero-extend-from-1-bit to:
3058
- // - and rd, rn, #1
3059
- // Note: This is special cased as UBFX may take more cycles
3060
- // than AND on smaller cores.
3061
- let imml = ImmLogic::maybe_from_u64(1, I32).unwrap();
3062
- Inst::AluRRImmLogic {
3063
- alu_op: ALUOp::And,
3064
- size: OperandSize::Size32,
3065
- rd,
3066
- rn,
3067
- imml,
3068
- }
3069
- .emit(&[], sink, emit_info, state);
3070
- }
3071
- &Inst::Extend {
3072
- rd,
3073
- rn,
3074
- signed: false,
3075
- from_bits: 32,
3076
- to_bits: 64,
3077
- } => {
3078
- let rd = allocs.next_writable(rd);
3079
- let rn = allocs.next(rn);
3080
- let mov = Inst::Mov {
3081
- size: OperandSize::Size32,
3082
- rd,
3083
- rm: rn,
3084
- };
3085
- mov.emit(&[], sink, emit_info, state);
3086
- }
3087
- &Inst::Extend {
3088
- rd,
3089
- rn,
3090
- signed,
3091
- from_bits,
3092
- to_bits,
3093
- } => {
3094
- let rd = allocs.next_writable(rd);
3095
- let rn = allocs.next(rn);
3096
- let (opc, size) = if signed {
3097
- (0b00, OperandSize::from_bits(to_bits))
3098
- } else {
3099
- (0b10, OperandSize::Size32)
3100
- };
3101
- sink.put4(enc_bfm(opc, size, rd, rn, 0, from_bits - 1));
3102
- }
3103
- &Inst::Jump { ref dest } => {
3104
- let off = sink.cur_offset();
3105
- // Indicate that the jump uses a label, if so, so that a fixup can occur later.
3106
- if let Some(l) = dest.as_label() {
3107
- sink.use_label_at_offset(off, l, LabelUse::Branch26);
3108
- sink.add_uncond_branch(off, off + 4, l);
3109
- }
3110
- // Emit the jump itself.
3111
- sink.put4(enc_jump26(0b000101, dest.as_offset26_or_zero()));
3112
- }
3113
- &Inst::Args { .. } => {
3114
- // Nothing: this is a pseudoinstruction that serves
3115
- // only to constrain registers at a certain point.
3116
- }
3117
- &Inst::Ret { .. } => {
3118
- sink.put4(0xd65f03c0);
3119
- }
3120
- &Inst::AuthenticatedRet { key, is_hint, .. } => {
3121
- let key = match key {
3122
- APIKey::A => 0b0,
3123
- APIKey::B => 0b1,
3124
- };
3125
-
3126
- if is_hint {
3127
- sink.put4(0xd50323bf | key << 6); // autiasp / autibsp
3128
- Inst::Ret { rets: vec![] }.emit(&[], sink, emit_info, state);
3129
- } else {
3130
- sink.put4(0xd65f0bff | key << 10); // retaa / retab
3131
- }
3132
- }
3133
- &Inst::Call { ref info } => {
3134
- if let Some(s) = state.take_stack_map() {
3135
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
3136
- }
3137
- sink.add_reloc(Reloc::Arm64Call, &info.dest, 0);
3138
- sink.put4(enc_jump26(0b100101, 0));
3139
- if info.opcode.is_call() {
3140
- sink.add_call_site(info.opcode);
3141
- }
3142
- }
3143
- &Inst::CallInd { ref info } => {
3144
- if let Some(s) = state.take_stack_map() {
3145
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
3146
- }
3147
- let rn = allocs.next(info.rn);
3148
- sink.put4(0b1101011_0001_11111_000000_00000_00000 | (machreg_to_gpr(rn) << 5));
3149
- if info.opcode.is_call() {
3150
- sink.add_call_site(info.opcode);
3151
- }
3152
- }
3153
- &Inst::CondBr {
3154
- taken,
3155
- not_taken,
3156
- kind,
3157
- } => {
3158
- // Conditional part first.
3159
- let cond_off = sink.cur_offset();
3160
- if let Some(l) = taken.as_label() {
3161
- sink.use_label_at_offset(cond_off, l, LabelUse::Branch19);
3162
- let mut allocs_inv = allocs.clone();
3163
- let inverted =
3164
- enc_conditional_br(taken, kind.invert(), &mut allocs_inv).to_le_bytes();
3165
- sink.add_cond_branch(cond_off, cond_off + 4, l, &inverted[..]);
3166
- }
3167
- sink.put4(enc_conditional_br(taken, kind, &mut allocs));
3168
-
3169
- // Unconditional part next.
3170
- let uncond_off = sink.cur_offset();
3171
- if let Some(l) = not_taken.as_label() {
3172
- sink.use_label_at_offset(uncond_off, l, LabelUse::Branch26);
3173
- sink.add_uncond_branch(uncond_off, uncond_off + 4, l);
3174
- }
3175
- sink.put4(enc_jump26(0b000101, not_taken.as_offset26_or_zero()));
3176
- }
3177
- &Inst::TrapIf { kind, trap_code } => {
3178
- let label = sink.defer_trap(trap_code, state.take_stack_map());
3179
- // condbr KIND, LABEL
3180
- let off = sink.cur_offset();
3181
- sink.put4(enc_conditional_br(
3182
- BranchTarget::Label(label),
3183
- kind,
3184
- &mut allocs,
3185
- ));
3186
- sink.use_label_at_offset(off, label, LabelUse::Branch19);
3187
- }
3188
- &Inst::IndirectBr { rn, .. } => {
3189
- let rn = allocs.next(rn);
3190
- sink.put4(enc_br(rn));
3191
- }
3192
- &Inst::Nop0 => {}
3193
- &Inst::Nop4 => {
3194
- sink.put4(0xd503201f);
3195
- }
3196
- &Inst::Brk => {
3197
- sink.put4(0xd4200000);
3198
- }
3199
- &Inst::Udf { trap_code } => {
3200
- sink.add_trap(trap_code);
3201
- if let Some(s) = state.take_stack_map() {
3202
- sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
3203
- }
3204
- sink.put_data(Inst::TRAP_OPCODE);
3205
- }
3206
- &Inst::Adr { rd, off } => {
3207
- let rd = allocs.next_writable(rd);
3208
- assert!(off > -(1 << 20));
3209
- assert!(off < (1 << 20));
3210
- sink.put4(enc_adr(off, rd));
3211
- }
3212
- &Inst::Adrp { rd, off } => {
3213
- let rd = allocs.next_writable(rd);
3214
- assert!(off > -(1 << 20));
3215
- assert!(off < (1 << 20));
3216
- sink.put4(enc_adrp(off, rd));
3217
- }
3218
- &Inst::Word4 { data } => {
3219
- sink.put4(data);
3220
- }
3221
- &Inst::Word8 { data } => {
3222
- sink.put8(data);
3223
- }
3224
- &Inst::JTSequence {
3225
- ridx,
3226
- rtmp1,
3227
- rtmp2,
3228
- ref info,
3229
- ..
3230
- } => {
3231
- let ridx = allocs.next(ridx);
3232
- let rtmp1 = allocs.next_writable(rtmp1);
3233
- let rtmp2 = allocs.next_writable(rtmp2);
3234
- // This sequence is *one* instruction in the vcode, and is expanded only here at
3235
- // emission time, because we cannot allow the regalloc to insert spills/reloads in
3236
- // the middle; we depend on hardcoded PC-rel addressing below.
3237
-
3238
- // Branch to default when condition code from prior comparison indicates.
3239
- let br = enc_conditional_br(
3240
- info.default_target,
3241
- CondBrKind::Cond(Cond::Hs),
3242
- &mut AllocationConsumer::default(),
3243
- );
3244
-
3245
- // No need to inform the sink's branch folding logic about this branch, because it
3246
- // will not be merged with any other branch, flipped, or elided (it is not preceded
3247
- // or succeeded by any other branch). Just emit it with the label use.
3248
- let default_br_offset = sink.cur_offset();
3249
- if let BranchTarget::Label(l) = info.default_target {
3250
- sink.use_label_at_offset(default_br_offset, l, LabelUse::Branch19);
3251
- }
3252
- sink.put4(br);
3253
-
3254
- // Overwrite the index with a zero when the above
3255
- // branch misspeculates (Spectre mitigation). Save the
3256
- // resulting index in rtmp2.
3257
- let inst = Inst::CSel {
3258
- rd: rtmp2,
3259
- cond: Cond::Hs,
3260
- rn: zero_reg(),
3261
- rm: ridx,
3262
- };
3263
- inst.emit(&[], sink, emit_info, state);
3264
- // Prevent any data value speculation.
3265
- Inst::Csdb.emit(&[], sink, emit_info, state);
3266
-
3267
- // Load address of jump table
3268
- let inst = Inst::Adr { rd: rtmp1, off: 16 };
3269
- inst.emit(&[], sink, emit_info, state);
3270
- // Load value out of jump table
3271
- let inst = Inst::SLoad32 {
3272
- rd: rtmp2,
3273
- mem: AMode::reg_plus_reg_scaled_extended(
3274
- rtmp1.to_reg(),
3275
- rtmp2.to_reg(),
3276
- I32,
3277
- ExtendOp::UXTW,
3278
- ),
3279
- flags: MemFlags::trusted(),
3280
- };
3281
- inst.emit(&[], sink, emit_info, state);
3282
- // Add base of jump table to jump-table-sourced block offset
3283
- let inst = Inst::AluRRR {
3284
- alu_op: ALUOp::Add,
3285
- size: OperandSize::Size64,
3286
- rd: rtmp1,
3287
- rn: rtmp1.to_reg(),
3288
- rm: rtmp2.to_reg(),
3289
- };
3290
- inst.emit(&[], sink, emit_info, state);
3291
- // Branch to computed address. (`targets` here is only used for successor queries
3292
- // and is not needed for emission.)
3293
- let inst = Inst::IndirectBr {
3294
- rn: rtmp1.to_reg(),
3295
- targets: vec![],
3296
- };
3297
- inst.emit(&[], sink, emit_info, state);
3298
- // Emit jump table (table of 32-bit offsets).
3299
- let jt_off = sink.cur_offset();
3300
- for &target in info.targets.iter() {
3301
- let word_off = sink.cur_offset();
3302
- // off_into_table is an addend here embedded in the label to be later patched
3303
- // at the end of codegen. The offset is initially relative to this jump table
3304
- // entry; with the extra addend, it'll be relative to the jump table's start,
3305
- // after patching.
3306
- let off_into_table = word_off - jt_off;
3307
- sink.use_label_at_offset(
3308
- word_off,
3309
- target.as_label().unwrap(),
3310
- LabelUse::PCRel32,
3311
- );
3312
- sink.put4(off_into_table);
3313
- }
3314
-
3315
- // Lowering produces an EmitIsland before using a JTSequence, so we can safely
3316
- // disable the worst-case-size check in this case.
3317
- start_off = sink.cur_offset();
3318
- }
3319
- &Inst::LoadExtName {
3320
- rd,
3321
- ref name,
3322
- offset,
3323
- } => {
3324
- let rd = allocs.next_writable(rd);
3325
-
3326
- if emit_info.0.is_pic() {
3327
- // See this CE Example for the variations of this with and without BTI & PAUTH
3328
- // https://godbolt.org/z/ncqjbbvvn
3329
- //
3330
- // Emit the following code:
3331
- // adrp rd, :got:X
3332
- // ldr rd, [rd, :got_lo12:X]
3333
-
3334
- // adrp rd, symbol
3335
- sink.add_reloc(Reloc::Aarch64AdrGotPage21, name, 0);
3336
- let inst = Inst::Adrp { rd, off: 0 };
3337
- inst.emit(&[], sink, emit_info, state);
3338
-
3339
- // ldr rd, [rd, :got_lo12:X]
3340
- sink.add_reloc(Reloc::Aarch64Ld64GotLo12Nc, name, 0);
3341
- let inst = Inst::ULoad64 {
3342
- rd,
3343
- mem: AMode::reg(rd.to_reg()),
3344
- flags: MemFlags::trusted(),
3345
- };
3346
- inst.emit(&[], sink, emit_info, state);
3347
- } else {
3348
- // With absolute offsets we set up a load from a preallocated space, and then jump
3349
- // over it.
3350
- //
3351
- // Emit the following code:
3352
- // ldr rd, #8
3353
- // b #0x10
3354
- // <8 byte space>
3355
-
3356
- let inst = Inst::ULoad64 {
3357
- rd,
3358
- mem: AMode::Label {
3359
- label: MemLabel::PCRel(8),
3360
- },
3361
- flags: MemFlags::trusted(),
3362
- };
3363
- inst.emit(&[], sink, emit_info, state);
3364
- let inst = Inst::Jump {
3365
- dest: BranchTarget::ResolvedOffset(12),
3366
- };
3367
- inst.emit(&[], sink, emit_info, state);
3368
- sink.add_reloc(Reloc::Abs8, name, offset);
3369
- sink.put8(0);
3370
- }
3371
- }
3372
- &Inst::LoadAddr { rd, ref mem } => {
3373
- let rd = allocs.next_writable(rd);
3374
- let mem = mem.with_allocs(&mut allocs);
3375
- let (mem_insts, mem) = mem_finalize(Some(sink), &mem, state);
3376
- for inst in mem_insts.into_iter() {
3377
- inst.emit(&[], sink, emit_info, state);
3378
- }
3379
-
3380
- let (reg, index_reg, offset) = match mem {
3381
- AMode::RegExtended { rn, rm, extendop } => {
3382
- let r = allocs.next(rn);
3383
- (r, Some((rm, extendop)), 0)
3384
- }
3385
- AMode::Unscaled { rn, simm9 } => {
3386
- let r = allocs.next(rn);
3387
- (r, None, simm9.value())
3388
- }
3389
- AMode::UnsignedOffset { rn, uimm12 } => {
3390
- let r = allocs.next(rn);
3391
- (r, None, uimm12.value() as i32)
3392
- }
3393
- _ => panic!("Unsupported case for LoadAddr: {:?}", mem),
3394
- };
3395
- let abs_offset = if offset < 0 {
3396
- -offset as u64
3397
- } else {
3398
- offset as u64
3399
- };
3400
- let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
3401
-
3402
- if let Some((idx, extendop)) = index_reg {
3403
- let add = Inst::AluRRRExtend {
3404
- alu_op: ALUOp::Add,
3405
- size: OperandSize::Size64,
3406
- rd,
3407
- rn: reg,
3408
- rm: idx,
3409
- extendop,
3410
- };
3411
-
3412
- add.emit(&[], sink, emit_info, state);
3413
- } else if offset == 0 {
3414
- if reg != rd.to_reg() {
3415
- let mov = Inst::Mov {
3416
- size: OperandSize::Size64,
3417
- rd,
3418
- rm: reg,
3419
- };
3420
-
3421
- mov.emit(&[], sink, emit_info, state);
3422
- }
3423
- } else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
3424
- let add = Inst::AluRRImm12 {
3425
- alu_op,
3426
- size: OperandSize::Size64,
3427
- rd,
3428
- rn: reg,
3429
- imm12,
3430
- };
3431
- add.emit(&[], sink, emit_info, state);
3432
- } else {
3433
- // Use `tmp2` here: `reg` may be `spilltmp` if the `AMode` on this instruction
3434
- // was initially an `SPOffset`. Assert that `tmp2` is truly free to use. Note
3435
- // that no other instructions will be inserted here (we're emitting directly),
3436
- // and a live range of `tmp2` should not span this instruction, so this use
3437
- // should otherwise be correct.
3438
- debug_assert!(rd.to_reg() != tmp2_reg());
3439
- debug_assert!(reg != tmp2_reg());
3440
- let tmp = writable_tmp2_reg();
3441
- for insn in Inst::load_constant(tmp, abs_offset, &mut |_| tmp).into_iter() {
3442
- insn.emit(&[], sink, emit_info, state);
3443
- }
3444
- let add = Inst::AluRRR {
3445
- alu_op,
3446
- size: OperandSize::Size64,
3447
- rd,
3448
- rn: reg,
3449
- rm: tmp.to_reg(),
3450
- };
3451
- add.emit(&[], sink, emit_info, state);
3452
- }
3453
- }
3454
- &Inst::Pacisp { key } => {
3455
- let key = match key {
3456
- APIKey::A => 0b0,
3457
- APIKey::B => 0b1,
3458
- };
3459
-
3460
- sink.put4(0xd503233f | key << 6);
3461
- }
3462
- &Inst::Xpaclri => sink.put4(0xd50320ff),
3463
- &Inst::Bti { targets } => {
3464
- let targets = match targets {
3465
- BranchTargetType::None => 0b00,
3466
- BranchTargetType::C => 0b01,
3467
- BranchTargetType::J => 0b10,
3468
- BranchTargetType::JC => 0b11,
3469
- };
3470
-
3471
- sink.put4(0xd503241f | targets << 6);
3472
- }
3473
- &Inst::VirtualSPOffsetAdj { offset } => {
3474
- trace!(
3475
- "virtual sp offset adjusted by {} -> {}",
3476
- offset,
3477
- state.virtual_sp_offset + offset,
3478
- );
3479
- state.virtual_sp_offset += offset;
3480
- }
3481
- &Inst::EmitIsland { needed_space } => {
3482
- if sink.island_needed(needed_space + 4) {
3483
- let jump_around_label = sink.get_label();
3484
- let jmp = Inst::Jump {
3485
- dest: BranchTarget::Label(jump_around_label),
3486
- };
3487
- jmp.emit(&[], sink, emit_info, state);
3488
- sink.emit_island(needed_space + 4, &mut state.ctrl_plane);
3489
- sink.bind_label(jump_around_label, &mut state.ctrl_plane);
3490
- }
3491
- }
3492
-
3493
- &Inst::ElfTlsGetAddr { ref symbol, rd } => {
3494
- let rd = allocs.next_writable(rd);
3495
- assert_eq!(xreg(0), rd.to_reg());
3496
-
3497
- // This is the instruction sequence that GCC emits for ELF GD TLS Relocations in aarch64
3498
- // See: https://gcc.godbolt.org/z/KhMh5Gvra
3499
-
3500
- // adrp x0, <label>
3501
- sink.add_reloc(Reloc::Aarch64TlsGdAdrPage21, symbol, 0);
3502
- let inst = Inst::Adrp { rd, off: 0 };
3503
- inst.emit(&[], sink, emit_info, state);
3504
-
3505
- // add x0, x0, <label>
3506
- sink.add_reloc(Reloc::Aarch64TlsGdAddLo12Nc, symbol, 0);
3507
- sink.put4(0x91000000);
3508
-
3509
- // bl __tls_get_addr
3510
- sink.add_reloc(
3511
- Reloc::Arm64Call,
3512
- &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
3513
- 0,
3514
- );
3515
- sink.put4(0x94000000);
3516
-
3517
- // nop
3518
- sink.put4(0xd503201f);
3519
- }
3520
-
3521
- &Inst::MachOTlsGetAddr { ref symbol, rd } => {
3522
- // Each thread local variable gets a descriptor, where the first xword of the descriptor is a pointer
3523
- // to a function that takes the descriptor address in x0, and after the function returns x0
3524
- // contains the address for the thread local variable
3525
- //
3526
- // what we want to emit is basically:
3527
- //
3528
- // adrp x0, <label>@TLVPPAGE ; Load the address of the page of the thread local variable pointer (TLVP)
3529
- // ldr x0, [x0, <label>@TLVPPAGEOFF] ; Load the descriptor's address into x0
3530
- // ldr x1, [x0] ; Load the function pointer (the first part of the descriptor)
3531
- // blr x1 ; Call the function pointer with the descriptor address in x0
3532
- // ; x0 now contains the TLV address
3533
-
3534
- let rd = allocs.next_writable(rd);
3535
- assert_eq!(xreg(0), rd.to_reg());
3536
- let rtmp = writable_xreg(1);
3537
-
3538
- // adrp x0, <label>@TLVPPAGE
3539
- sink.add_reloc(Reloc::MachOAarch64TlsAdrPage21, symbol, 0);
3540
- sink.put4(0x90000000);
3541
-
3542
- // ldr x0, [x0, <label>@TLVPPAGEOFF]
3543
- sink.add_reloc(Reloc::MachOAarch64TlsAdrPageOff12, symbol, 0);
3544
- sink.put4(0xf9400000);
3545
-
3546
- // load [x0] into temp register
3547
- Inst::ULoad64 {
3548
- rd: rtmp,
3549
- mem: AMode::reg(rd.to_reg()),
3550
- flags: MemFlags::trusted(),
3551
- }
3552
- .emit(&[], sink, emit_info, state);
3553
-
3554
- // call function pointer in temp register
3555
- Inst::CallInd {
3556
- info: crate::isa::Box::new(CallIndInfo {
3557
- rn: rtmp.to_reg(),
3558
- uses: smallvec![],
3559
- defs: smallvec![],
3560
- clobbers: PRegSet::empty(),
3561
- opcode: Opcode::CallIndirect,
3562
- caller_callconv: CallConv::AppleAarch64,
3563
- callee_callconv: CallConv::AppleAarch64,
3564
- }),
3565
- }
3566
- .emit(&[], sink, emit_info, state);
3567
- }
3568
-
3569
- &Inst::Unwind { ref inst } => {
3570
- sink.add_unwind(inst.clone());
3571
- }
3572
-
3573
- &Inst::DummyUse { .. } => {}
3574
-
3575
- &Inst::StackProbeLoop { start, end, step } => {
3576
- assert!(emit_info.0.enable_probestack());
3577
- let start = allocs.next_writable(start);
3578
- let end = allocs.next(end);
3579
-
3580
- // The loop generated here uses `start` as a counter register to
3581
- // count backwards until negating it exceeds `end`. In other
3582
- // words `start` is an offset from `sp` we're testing where
3583
- // `end` is the max size we need to test. The loop looks like:
3584
- //
3585
- // loop_start:
3586
- // sub start, start, #step
3587
- // stur xzr, [sp, start]
3588
- // cmn start, end
3589
- // br.gt loop_start
3590
- // loop_end:
3591
- //
3592
- // Note that this loop cannot use the spilltmp and tmp2
3593
- // registers as those are currently used as the input to this
3594
- // loop when generating the instruction. This means that some
3595
- // more flavorful address modes and lowerings need to be
3596
- // avoided.
3597
- //
3598
- // Perhaps someone more clever than I can figure out how to use
3599
- // `subs` or the like and skip the `cmn`, but I can't figure it
3600
- // out at this time.
3601
-
3602
- let loop_start = sink.get_label();
3603
- sink.bind_label(loop_start, &mut state.ctrl_plane);
3604
-
3605
- Inst::AluRRImm12 {
3606
- alu_op: ALUOp::Sub,
3607
- size: OperandSize::Size64,
3608
- rd: start,
3609
- rn: start.to_reg(),
3610
- imm12: step,
3611
- }
3612
- .emit(&[], sink, emit_info, state);
3613
- Inst::Store32 {
3614
- rd: regs::zero_reg(),
3615
- mem: AMode::RegReg {
3616
- rn: regs::stack_reg(),
3617
- rm: start.to_reg(),
3618
- },
3619
- flags: MemFlags::trusted(),
3620
- }
3621
- .emit(&[], sink, emit_info, state);
3622
- Inst::AluRRR {
3623
- alu_op: ALUOp::AddS,
3624
- size: OperandSize::Size64,
3625
- rd: regs::writable_zero_reg(),
3626
- rn: start.to_reg(),
3627
- rm: end,
3628
- }
3629
- .emit(&[], sink, emit_info, state);
3630
-
3631
- let loop_end = sink.get_label();
3632
- Inst::CondBr {
3633
- taken: BranchTarget::Label(loop_start),
3634
- not_taken: BranchTarget::Label(loop_end),
3635
- kind: CondBrKind::Cond(Cond::Gt),
3636
- }
3637
- .emit(&[], sink, emit_info, state);
3638
- sink.bind_label(loop_end, &mut state.ctrl_plane);
3639
- }
3640
- }
3641
-
3642
- let end_off = sink.cur_offset();
3643
- debug_assert!(
3644
- (end_off - start_off) <= Inst::worst_case_size()
3645
- || matches!(self, Inst::EmitIsland { .. }),
3646
- "Worst case size exceed for {:?}: {}",
3647
- self,
3648
- end_off - start_off
3649
- );
3650
-
3651
- state.clear_post_insn();
3652
- }
3653
-
3654
- fn pretty_print_inst(&self, allocs: &[Allocation], state: &mut Self::State) -> String {
3655
- let mut allocs = AllocationConsumer::new(allocs);
3656
- self.print_with_state(state, &mut allocs)
3657
- }
3658
- }