wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -0,0 +1,1526 @@
1
+ /*
2
+ * The following license applies to this file, which derives many
3
+ * details (register and constraint definitions, for example) from the
4
+ * files `BacktrackingAllocator.h`, `BacktrackingAllocator.cpp`,
5
+ * `LIR.h`, and possibly definitions in other related files in
6
+ * `js/src/jit/`:
7
+ *
8
+ * This Source Code Form is subject to the terms of the Mozilla Public
9
+ * License, v. 2.0. If a copy of the MPL was not distributed with this
10
+ * file, You can obtain one at http://mozilla.org/MPL/2.0/.
11
+ */
12
+
13
+ #![allow(dead_code)]
14
+ #![no_std]
15
+
16
+ #[cfg(feature = "std")]
17
+ extern crate std;
18
+
19
+ extern crate alloc;
20
+
21
+ // Even when trace logging is disabled, the trace macro has a significant
22
+ // performance cost so we disable it in release builds.
23
+ macro_rules! trace {
24
+ ($($tt:tt)*) => {
25
+ if cfg!(feature = "trace-log") {
26
+ ::log::trace!($($tt)*);
27
+ }
28
+ };
29
+ }
30
+
31
+ macro_rules! trace_enabled {
32
+ () => {
33
+ cfg!(feature = "trace-log") && ::log::log_enabled!(::log::Level::Trace)
34
+ };
35
+ }
36
+
37
+ use core::hash::BuildHasherDefault;
38
+ use rustc_hash::FxHasher;
39
+ type FxHashMap<K, V> = hashbrown::HashMap<K, V, BuildHasherDefault<FxHasher>>;
40
+ type FxHashSet<V> = hashbrown::HashSet<V, BuildHasherDefault<FxHasher>>;
41
+
42
+ pub(crate) mod cfg;
43
+ pub(crate) mod domtree;
44
+ pub mod indexset;
45
+ pub(crate) mod ion;
46
+ pub(crate) mod moves;
47
+ pub(crate) mod postorder;
48
+ pub mod ssa;
49
+
50
+ #[macro_use]
51
+ mod index;
52
+
53
+ use alloc::vec::Vec;
54
+ pub use index::{Block, Inst, InstRange, InstRangeIter};
55
+
56
+ pub mod checker;
57
+
58
+ #[cfg(feature = "fuzzing")]
59
+ pub mod fuzzing;
60
+
61
+ #[cfg(feature = "enable-serde")]
62
+ pub mod serialize;
63
+
64
+ #[cfg(feature = "enable-serde")]
65
+ use serde::{Deserialize, Serialize};
66
+
67
+ /// Register classes.
68
+ ///
69
+ /// Every value has a "register class", which is like a type at the
70
+ /// register-allocator level. Every register must belong to only one
71
+ /// class; i.e., they are disjoint.
72
+ ///
73
+ /// For tight bit-packing throughout our data structures, we support
74
+ /// only three classes, "int", "float" and "vector". Usually two will
75
+ /// be enough on modern machines, as they have one class of general-purpose
76
+ /// integer registers of machine width (e.g. 64 bits), and another
77
+ /// class of float/vector registers used both for FP and for vector
78
+ /// operations. Additionally for machines with totally separate vector
79
+ /// registers a third class is provided.
80
+ #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
81
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
82
+ pub enum RegClass {
83
+ Int = 0,
84
+ Float = 1,
85
+ Vector = 2,
86
+ }
87
+
88
+ /// A physical register. Contains a physical register number and a class.
89
+ ///
90
+ /// The `hw_enc` field contains the physical register number and is in
91
+ /// a logically separate index space per class; in other words, Int
92
+ /// register 0 is different than Float register 0.
93
+ ///
94
+ /// Because of bit-packed encodings throughout the implementation,
95
+ /// `hw_enc` must fit in 6 bits, i.e., at most 64 registers per class.
96
+ ///
97
+ /// The value returned by `index()`, in contrast, is in a single index
98
+ /// space shared by all classes, in order to enable uniform reasoning
99
+ /// about physical registers. This is done by putting the class bit at
100
+ /// the MSB, or equivalently, declaring that indices 0..=63 are the 64
101
+ /// integer registers and indices 64..=127 are the 64 float registers.
102
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
103
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
104
+ pub struct PReg {
105
+ bits: u8,
106
+ }
107
+
108
+ impl PReg {
109
+ pub const MAX_BITS: usize = 6;
110
+ pub const MAX: usize = (1 << Self::MAX_BITS) - 1;
111
+ pub const NUM_INDEX: usize = 1 << (Self::MAX_BITS + 2); // including RegClass bits
112
+
113
+ /// Create a new PReg. The `hw_enc` range is 6 bits.
114
+ #[inline(always)]
115
+ pub const fn new(hw_enc: usize, class: RegClass) -> Self {
116
+ debug_assert!(hw_enc <= PReg::MAX);
117
+ PReg {
118
+ bits: ((class as u8) << Self::MAX_BITS) | (hw_enc as u8),
119
+ }
120
+ }
121
+
122
+ /// The physical register number, as encoded by the ISA for the particular register class.
123
+ #[inline(always)]
124
+ pub const fn hw_enc(self) -> usize {
125
+ self.bits as usize & Self::MAX
126
+ }
127
+
128
+ /// The register class.
129
+ #[inline(always)]
130
+ pub const fn class(self) -> RegClass {
131
+ match (self.bits >> Self::MAX_BITS) & 0b11 {
132
+ 0 => RegClass::Int,
133
+ 1 => RegClass::Float,
134
+ 2 => RegClass::Vector,
135
+ _ => unreachable!(),
136
+ }
137
+ }
138
+
139
+ /// Get an index into the (not necessarily contiguous) index space of
140
+ /// all physical registers. Allows one to maintain an array of data for
141
+ /// all PRegs and index it efficiently.
142
+ #[inline(always)]
143
+ pub const fn index(self) -> usize {
144
+ self.bits as usize
145
+ }
146
+
147
+ /// Construct a PReg from the value returned from `.index()`.
148
+ #[inline(always)]
149
+ pub const fn from_index(index: usize) -> Self {
150
+ PReg {
151
+ bits: (index & (Self::NUM_INDEX - 1)) as u8,
152
+ }
153
+ }
154
+
155
+ /// Return the "invalid PReg", which can be used to initialize
156
+ /// data structures.
157
+ #[inline(always)]
158
+ pub const fn invalid() -> Self {
159
+ PReg::new(Self::MAX, RegClass::Int)
160
+ }
161
+ }
162
+
163
+ impl core::fmt::Debug for PReg {
164
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
165
+ write!(
166
+ f,
167
+ "PReg(hw = {}, class = {:?}, index = {})",
168
+ self.hw_enc(),
169
+ self.class(),
170
+ self.index()
171
+ )
172
+ }
173
+ }
174
+
175
+ impl core::fmt::Display for PReg {
176
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
177
+ let class = match self.class() {
178
+ RegClass::Int => "i",
179
+ RegClass::Float => "f",
180
+ RegClass::Vector => "v",
181
+ };
182
+ write!(f, "p{}{}", self.hw_enc(), class)
183
+ }
184
+ }
185
+
186
+ /// A physical register set. Used to represent clobbers
187
+ /// efficiently.
188
+ ///
189
+ /// The set is `Copy` and is guaranteed to have constant, and small,
190
+ /// size, as it is based on a bitset internally.
191
+ #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash, Default)]
192
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
193
+ pub struct PRegSet {
194
+ bits: [u128; 2],
195
+ }
196
+
197
+ impl PRegSet {
198
+ /// Create an empty set.
199
+ pub const fn empty() -> Self {
200
+ Self { bits: [0; 2] }
201
+ }
202
+
203
+ /// Returns whether the given register is part of the set.
204
+ pub fn contains(&self, reg: PReg) -> bool {
205
+ debug_assert!(reg.index() < 256);
206
+ let bit = reg.index() & 127;
207
+ let index = reg.index() >> 7;
208
+ self.bits[index] & (1u128 << bit) != 0
209
+ }
210
+
211
+ /// Add a physical register (PReg) to the set, returning the new value.
212
+ pub const fn with(self, reg: PReg) -> Self {
213
+ debug_assert!(reg.index() < 256);
214
+ let bit = reg.index() & 127;
215
+ let index = reg.index() >> 7;
216
+ let mut out = self;
217
+ out.bits[index] |= 1u128 << bit;
218
+ out
219
+ }
220
+
221
+ /// Add a physical register (PReg) to the set.
222
+ pub fn add(&mut self, reg: PReg) {
223
+ debug_assert!(reg.index() < 256);
224
+ let bit = reg.index() & 127;
225
+ let index = reg.index() >> 7;
226
+ self.bits[index] |= 1u128 << bit;
227
+ }
228
+
229
+ /// Remove a physical register (PReg) from the set.
230
+ pub fn remove(&mut self, reg: PReg) {
231
+ debug_assert!(reg.index() < 256);
232
+ let bit = reg.index() & 127;
233
+ let index = reg.index() >> 7;
234
+ self.bits[index] &= !(1u128 << bit);
235
+ }
236
+
237
+ /// Add all of the registers in one set to this one, mutating in
238
+ /// place.
239
+ pub fn union_from(&mut self, other: PRegSet) {
240
+ self.bits[0] |= other.bits[0];
241
+ self.bits[1] |= other.bits[1];
242
+ }
243
+ }
244
+
245
+ impl IntoIterator for PRegSet {
246
+ type Item = PReg;
247
+ type IntoIter = PRegSetIter;
248
+ fn into_iter(self) -> PRegSetIter {
249
+ PRegSetIter { bits: self.bits }
250
+ }
251
+ }
252
+
253
+ pub struct PRegSetIter {
254
+ bits: [u128; 2],
255
+ }
256
+
257
+ impl Iterator for PRegSetIter {
258
+ type Item = PReg;
259
+ fn next(&mut self) -> Option<PReg> {
260
+ if self.bits[0] != 0 {
261
+ let index = self.bits[0].trailing_zeros();
262
+ self.bits[0] &= !(1u128 << index);
263
+ Some(PReg::from_index(index as usize))
264
+ } else if self.bits[1] != 0 {
265
+ let index = self.bits[1].trailing_zeros();
266
+ self.bits[1] &= !(1u128 << index);
267
+ Some(PReg::from_index(index as usize + 128))
268
+ } else {
269
+ None
270
+ }
271
+ }
272
+ }
273
+
274
+ impl From<&MachineEnv> for PRegSet {
275
+ fn from(env: &MachineEnv) -> Self {
276
+ let mut res = Self::default();
277
+
278
+ for class in env.preferred_regs_by_class.iter() {
279
+ for preg in class {
280
+ res.add(*preg)
281
+ }
282
+ }
283
+
284
+ for class in env.non_preferred_regs_by_class.iter() {
285
+ for preg in class {
286
+ res.add(*preg)
287
+ }
288
+ }
289
+
290
+ res
291
+ }
292
+ }
293
+
294
+ /// A virtual register. Contains a virtual register number and a
295
+ /// class.
296
+ ///
297
+ /// A virtual register ("vreg") corresponds to an SSA value. All
298
+ /// dataflow in the input program is specified via flow through a
299
+ /// virtual register; even uses of specially-constrained locations,
300
+ /// such as fixed physical registers, are done by using vregs, because
301
+ /// we need the vreg's live range in order to track the use of that
302
+ /// location.
303
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
304
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
305
+ pub struct VReg {
306
+ bits: u32,
307
+ }
308
+
309
+ impl VReg {
310
+ pub const MAX_BITS: usize = 21;
311
+ pub const MAX: usize = (1 << Self::MAX_BITS) - 1;
312
+
313
+ #[inline(always)]
314
+ pub const fn new(virt_reg: usize, class: RegClass) -> Self {
315
+ debug_assert!(virt_reg <= VReg::MAX);
316
+ VReg {
317
+ bits: ((virt_reg as u32) << 2) | (class as u8 as u32),
318
+ }
319
+ }
320
+
321
+ #[inline(always)]
322
+ pub const fn vreg(self) -> usize {
323
+ let vreg = (self.bits >> 2) as usize;
324
+ vreg
325
+ }
326
+
327
+ #[inline(always)]
328
+ pub const fn class(self) -> RegClass {
329
+ match self.bits & 0b11 {
330
+ 0 => RegClass::Int,
331
+ 1 => RegClass::Float,
332
+ 2 => RegClass::Vector,
333
+ _ => unreachable!(),
334
+ }
335
+ }
336
+
337
+ #[inline(always)]
338
+ pub const fn invalid() -> Self {
339
+ VReg::new(Self::MAX, RegClass::Int)
340
+ }
341
+ }
342
+
343
+ impl core::fmt::Debug for VReg {
344
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
345
+ write!(
346
+ f,
347
+ "VReg(vreg = {}, class = {:?})",
348
+ self.vreg(),
349
+ self.class()
350
+ )
351
+ }
352
+ }
353
+
354
+ impl core::fmt::Display for VReg {
355
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
356
+ write!(f, "v{}", self.vreg())
357
+ }
358
+ }
359
+
360
+ /// A spillslot is a space in the stackframe used by the allocator to
361
+ /// temporarily store a value.
362
+ ///
363
+ /// The allocator is responsible for allocating indices in this space,
364
+ /// and will specify how many spillslots have been used when the
365
+ /// allocation is completed.
366
+ #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
367
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
368
+ pub struct SpillSlot {
369
+ bits: u32,
370
+ }
371
+
372
+ impl SpillSlot {
373
+ /// The maximum spillslot index.
374
+ pub const MAX: usize = (1 << 24) - 1;
375
+
376
+ /// Create a new SpillSlot.
377
+ #[inline(always)]
378
+ pub fn new(slot: usize) -> Self {
379
+ debug_assert!(slot <= Self::MAX);
380
+ SpillSlot { bits: slot as u32 }
381
+ }
382
+
383
+ /// Get the spillslot index for this spillslot.
384
+ #[inline(always)]
385
+ pub fn index(self) -> usize {
386
+ (self.bits & 0x00ffffff) as usize
387
+ }
388
+
389
+ /// Get the spillslot `offset` slots away.
390
+ #[inline(always)]
391
+ pub fn plus(self, offset: usize) -> Self {
392
+ SpillSlot::new(self.index() + offset)
393
+ }
394
+
395
+ /// Get the invalid spillslot, used for initializing data structures.
396
+ #[inline(always)]
397
+ pub fn invalid() -> Self {
398
+ SpillSlot { bits: 0xffff_ffff }
399
+ }
400
+
401
+ /// Is this the invalid spillslot?
402
+ #[inline(always)]
403
+ pub fn is_invalid(self) -> bool {
404
+ self == Self::invalid()
405
+ }
406
+
407
+ /// Is this a valid spillslot (not `SpillSlot::invalid()`)?
408
+ #[inline(always)]
409
+ pub fn is_valid(self) -> bool {
410
+ self != Self::invalid()
411
+ }
412
+ }
413
+
414
+ impl core::fmt::Display for SpillSlot {
415
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
416
+ write!(f, "stack{}", self.index())
417
+ }
418
+ }
419
+
420
+ /// An `OperandConstraint` specifies where a vreg's value must be
421
+ /// placed at a particular reference to that vreg via an
422
+ /// `Operand`. The constraint may be loose -- "any register of a given
423
+ /// class", for example -- or very specific, such as "this particular
424
+ /// physical register". The allocator's result will always satisfy all
425
+ /// given constraints; however, if the input has a combination of
426
+ /// constraints that are impossible to satisfy, then allocation may
427
+ /// fail or the allocator may panic (providing impossible constraints
428
+ /// is usually a programming error in the client, rather than a
429
+ /// function of bad input).
430
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
431
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
432
+ pub enum OperandConstraint {
433
+ /// Any location is fine (register or stack slot).
434
+ Any,
435
+ /// Operand must be in a register. Register is read-only for Uses.
436
+ Reg,
437
+ /// Operand must be on the stack.
438
+ Stack,
439
+ /// Operand must be in a fixed register.
440
+ FixedReg(PReg),
441
+ /// On defs only: reuse a use's register.
442
+ Reuse(usize),
443
+ }
444
+
445
+ impl core::fmt::Display for OperandConstraint {
446
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
447
+ match self {
448
+ Self::Any => write!(f, "any"),
449
+ Self::Reg => write!(f, "reg"),
450
+ Self::Stack => write!(f, "stack"),
451
+ Self::FixedReg(preg) => write!(f, "fixed({})", preg),
452
+ Self::Reuse(idx) => write!(f, "reuse({})", idx),
453
+ }
454
+ }
455
+ }
456
+
457
+ /// The "kind" of the operand: whether it reads a vreg (Use) or writes
458
+ /// a vreg (Def).
459
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
460
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
461
+ pub enum OperandKind {
462
+ Def = 0,
463
+ Use = 1,
464
+ }
465
+
466
+ /// The "position" of the operand: where it has its read/write
467
+ /// effects. These are positions "in" the instruction, and "early" and
468
+ /// "late" are relative to the instruction's main effect or
469
+ /// computation. In other words, the allocator assumes that the
470
+ /// instruction (i) performs all reads and writes of "early" operands,
471
+ /// (ii) does its work, and (iii) performs all reads and writes of its
472
+ /// "late" operands.
473
+ ///
474
+ /// A "write" (def) at "early" or a "read" (use) at "late" may be
475
+ /// slightly nonsensical, given the above, if the read is necessary
476
+ /// for the computation or the write is a result of it. A way to think
477
+ /// of it is that the value (even if a result of execution) *could*
478
+ /// have been read or written at the given location without causing
479
+ /// any register-usage conflicts. In other words, these write-early or
480
+ /// use-late operands ensure that the particular allocations are valid
481
+ /// for longer than usual and that a register is not reused between
482
+ /// the use (normally complete at "Early") and the def (normally
483
+ /// starting at "Late"). See `Operand` for more.
484
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
485
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
486
+ pub enum OperandPos {
487
+ Early = 0,
488
+ Late = 1,
489
+ }
490
+
491
+ /// An `Operand` encodes everything about a mention of a register in
492
+ /// an instruction: virtual register number, and any constraint that
493
+ /// applies to the register at this program point.
494
+ ///
495
+ /// An Operand may be a use or def (this corresponds to `LUse` and
496
+ /// `LAllocation` in Ion).
497
+ ///
498
+ /// Generally, regalloc2 considers operands to have their effects at
499
+ /// one of two points that exist in an instruction: "Early" or
500
+ /// "Late". All operands at a given program-point are assigned
501
+ /// non-conflicting locations based on their constraints. Each operand
502
+ /// has a "kind", one of use/def/mod, corresponding to
503
+ /// read/write/read-write, respectively.
504
+ ///
505
+ /// Usually, an instruction's inputs will be "early uses" and outputs
506
+ /// will be "late defs", though there are valid use-cases for other
507
+ /// combinations too. For example, a single "instruction" seen by the
508
+ /// regalloc that lowers into multiple machine instructions and reads
509
+ /// some of its inputs after it starts to write outputs must either
510
+ /// make those input(s) "late uses" or those output(s) "early defs" so
511
+ /// that the conflict (overlap) is properly accounted for. See
512
+ /// comments on the constructors below for more.
513
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
514
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
515
+ pub struct Operand {
516
+ /// Bit-pack into 32 bits.
517
+ ///
518
+ /// constraint:7 kind:1 pos:1 class:2 vreg:21
519
+ ///
520
+ /// where `constraint` is an `OperandConstraint`, `kind` is an
521
+ /// `OperandKind`, `pos` is an `OperandPos`, `class` is a
522
+ /// `RegClass`, and `vreg` is a vreg index.
523
+ ///
524
+ /// The constraints are encoded as follows:
525
+ /// - 1xxxxxx => FixedReg(preg)
526
+ /// - 01xxxxx => Reuse(index)
527
+ /// - 0000000 => Any
528
+ /// - 0000001 => Reg
529
+ /// - 0000010 => Stack
530
+ /// - _ => Unused for now
531
+ bits: u32,
532
+ }
533
+
534
+ impl Operand {
535
+ /// Construct a new operand.
536
+ #[inline(always)]
537
+ pub fn new(
538
+ vreg: VReg,
539
+ constraint: OperandConstraint,
540
+ kind: OperandKind,
541
+ pos: OperandPos,
542
+ ) -> Self {
543
+ let constraint_field = match constraint {
544
+ OperandConstraint::Any => 0,
545
+ OperandConstraint::Reg => 1,
546
+ OperandConstraint::Stack => 2,
547
+ OperandConstraint::FixedReg(preg) => {
548
+ debug_assert_eq!(preg.class(), vreg.class());
549
+ 0b1000000 | preg.hw_enc() as u32
550
+ }
551
+ OperandConstraint::Reuse(which) => {
552
+ debug_assert!(which <= 31);
553
+ 0b0100000 | which as u32
554
+ }
555
+ };
556
+ let class_field = vreg.class() as u8 as u32;
557
+ let pos_field = pos as u8 as u32;
558
+ let kind_field = kind as u8 as u32;
559
+ Operand {
560
+ bits: vreg.vreg() as u32
561
+ | (class_field << 21)
562
+ | (pos_field << 23)
563
+ | (kind_field << 24)
564
+ | (constraint_field << 25),
565
+ }
566
+ }
567
+
568
+ /// Create an `Operand` that designates a use of a VReg that must
569
+ /// be in a register, and that is used at the "before" point,
570
+ /// i.e., can be overwritten by a result.
571
+ #[inline(always)]
572
+ pub fn reg_use(vreg: VReg) -> Self {
573
+ Operand::new(
574
+ vreg,
575
+ OperandConstraint::Reg,
576
+ OperandKind::Use,
577
+ OperandPos::Early,
578
+ )
579
+ }
580
+
581
+ /// Create an `Operand` that designates a use of a VReg that must
582
+ /// be in a register, and that is used up until the "after" point,
583
+ /// i.e., must not conflict with any results.
584
+ #[inline(always)]
585
+ pub fn reg_use_at_end(vreg: VReg) -> Self {
586
+ Operand::new(
587
+ vreg,
588
+ OperandConstraint::Reg,
589
+ OperandKind::Use,
590
+ OperandPos::Late,
591
+ )
592
+ }
593
+
594
+ /// Create an `Operand` that designates a definition of a VReg
595
+ /// that must be in a register, and that occurs at the "after"
596
+ /// point, i.e. may reuse a register that carried a use into this
597
+ /// instruction.
598
+ #[inline(always)]
599
+ pub fn reg_def(vreg: VReg) -> Self {
600
+ Operand::new(
601
+ vreg,
602
+ OperandConstraint::Reg,
603
+ OperandKind::Def,
604
+ OperandPos::Late,
605
+ )
606
+ }
607
+
608
+ /// Create an `Operand` that designates a definition of a VReg
609
+ /// that must be in a register, and that occurs early at the
610
+ /// "before" point, i.e., must not conflict with any input to the
611
+ /// instruction.
612
+ ///
613
+ /// Note that the register allocator will ensure that such an
614
+ /// early-def operand is live throughout the instruction, i.e., also
615
+ /// at the after-point. Hence it will also avoid conflicts with all
616
+ /// outputs to the instruction. As such, early defs are appropriate
617
+ /// for use as "temporary registers" that an instruction can use
618
+ /// throughout its execution separately from the inputs and outputs.
619
+ #[inline(always)]
620
+ pub fn reg_def_at_start(vreg: VReg) -> Self {
621
+ Operand::new(
622
+ vreg,
623
+ OperandConstraint::Reg,
624
+ OperandKind::Def,
625
+ OperandPos::Early,
626
+ )
627
+ }
628
+
629
+ /// Create an `Operand` that designates a def (and use) of a
630
+ /// temporary *within* the instruction. This register is assumed
631
+ /// to be written by the instruction, and will not conflict with
632
+ /// any input or output, but should not be used after the
633
+ /// instruction completes.
634
+ ///
635
+ /// Note that within a single instruction, the dedicated scratch
636
+ /// register (as specified in the `MachineEnv`) is also always
637
+ /// available for use. The register allocator may use the register
638
+ /// *between* instructions in order to implement certain sequences
639
+ /// of moves, but will never hold a value live in the scratch
640
+ /// register across an instruction.
641
+ #[inline(always)]
642
+ pub fn reg_temp(vreg: VReg) -> Self {
643
+ // For now a temp is equivalent to a def-at-start operand,
644
+ // which gives the desired semantics but does not enforce the
645
+ // "not reused later" constraint.
646
+ Operand::new(
647
+ vreg,
648
+ OperandConstraint::Reg,
649
+ OperandKind::Def,
650
+ OperandPos::Early,
651
+ )
652
+ }
653
+
654
+ /// Create an `Operand` that designates a def of a vreg that must
655
+ /// reuse the register assigned to an input to the
656
+ /// instruction. The input is identified by `idx` (is the `idx`th
657
+ /// `Operand` for the instruction) and must be constraint to a
658
+ /// register, i.e., be the result of `Operand::reg_use(vreg)`.
659
+ #[inline(always)]
660
+ pub fn reg_reuse_def(vreg: VReg, idx: usize) -> Self {
661
+ Operand::new(
662
+ vreg,
663
+ OperandConstraint::Reuse(idx),
664
+ OperandKind::Def,
665
+ OperandPos::Late,
666
+ )
667
+ }
668
+
669
+ /// Create an `Operand` that designates a use of a vreg and
670
+ /// ensures that it is placed in the given, fixed PReg at the
671
+ /// use. It is guaranteed that the `Allocation` resulting for this
672
+ /// operand will be `preg`.
673
+ #[inline(always)]
674
+ pub fn reg_fixed_use(vreg: VReg, preg: PReg) -> Self {
675
+ Operand::new(
676
+ vreg,
677
+ OperandConstraint::FixedReg(preg),
678
+ OperandKind::Use,
679
+ OperandPos::Early,
680
+ )
681
+ }
682
+
683
+ /// Create an `Operand` that designates a def of a vreg and
684
+ /// ensures that it is placed in the given, fixed PReg at the
685
+ /// def. It is guaranteed that the `Allocation` resulting for this
686
+ /// operand will be `preg`.
687
+ #[inline(always)]
688
+ pub fn reg_fixed_def(vreg: VReg, preg: PReg) -> Self {
689
+ Operand::new(
690
+ vreg,
691
+ OperandConstraint::FixedReg(preg),
692
+ OperandKind::Def,
693
+ OperandPos::Late,
694
+ )
695
+ }
696
+
697
+ /// Create an `Operand` that designates a use of a vreg and places
698
+ /// no constraints on its location (i.e., it can be allocated into
699
+ /// either a register or on the stack).
700
+ #[inline(always)]
701
+ pub fn any_use(vreg: VReg) -> Self {
702
+ Operand::new(
703
+ vreg,
704
+ OperandConstraint::Any,
705
+ OperandKind::Use,
706
+ OperandPos::Early,
707
+ )
708
+ }
709
+
710
+ /// Create an `Operand` that designates a def of a vreg and places
711
+ /// no constraints on its location (i.e., it can be allocated into
712
+ /// either a register or on the stack).
713
+ #[inline(always)]
714
+ pub fn any_def(vreg: VReg) -> Self {
715
+ Operand::new(
716
+ vreg,
717
+ OperandConstraint::Any,
718
+ OperandKind::Def,
719
+ OperandPos::Late,
720
+ )
721
+ }
722
+
723
+ /// Create an `Operand` that always results in an assignment to the
724
+ /// given fixed `preg`, *without* tracking liveranges in that
725
+ /// `preg`. Must only be used for non-allocatable registers.
726
+ #[inline(always)]
727
+ pub fn fixed_nonallocatable(preg: PReg) -> Self {
728
+ Operand::new(
729
+ VReg::new(VReg::MAX, preg.class()),
730
+ OperandConstraint::FixedReg(preg),
731
+ OperandKind::Use,
732
+ OperandPos::Early,
733
+ )
734
+ }
735
+
736
+ /// Get the virtual register designated by an operand. Every
737
+ /// operand must name some virtual register, even if it constrains
738
+ /// the operand to a fixed physical register as well; the vregs
739
+ /// are used to track dataflow.
740
+ #[inline(always)]
741
+ pub fn vreg(self) -> VReg {
742
+ let vreg_idx = ((self.bits as usize) & VReg::MAX) as usize;
743
+ VReg::new(vreg_idx, self.class())
744
+ }
745
+
746
+ /// Get the register class used by this operand.
747
+ #[inline(always)]
748
+ pub fn class(self) -> RegClass {
749
+ let class_field = (self.bits >> 21) & 3;
750
+ match class_field {
751
+ 0 => RegClass::Int,
752
+ 1 => RegClass::Float,
753
+ 2 => RegClass::Vector,
754
+ _ => unreachable!(),
755
+ }
756
+ }
757
+
758
+ /// Get the "kind" of this operand: a definition (write) or a use
759
+ /// (read).
760
+ #[inline(always)]
761
+ pub fn kind(self) -> OperandKind {
762
+ let kind_field = (self.bits >> 24) & 1;
763
+ match kind_field {
764
+ 0 => OperandKind::Def,
765
+ 1 => OperandKind::Use,
766
+ _ => unreachable!(),
767
+ }
768
+ }
769
+
770
+ /// Get the "position" of this operand, i.e., where its read
771
+ /// and/or write occurs: either before the instruction executes,
772
+ /// or after it does. Ordinarily, uses occur at "before" and defs
773
+ /// at "after", though there are cases where this is not true.
774
+ #[inline(always)]
775
+ pub fn pos(self) -> OperandPos {
776
+ let pos_field = (self.bits >> 23) & 1;
777
+ match pos_field {
778
+ 0 => OperandPos::Early,
779
+ 1 => OperandPos::Late,
780
+ _ => unreachable!(),
781
+ }
782
+ }
783
+
784
+ /// Get the "constraint" of this operand, i.e., what requirements
785
+ /// its allocation must fulfill.
786
+ #[inline(always)]
787
+ pub fn constraint(self) -> OperandConstraint {
788
+ let constraint_field = ((self.bits >> 25) as usize) & 127;
789
+ if constraint_field & 0b1000000 != 0 {
790
+ OperandConstraint::FixedReg(PReg::new(constraint_field & 0b0111111, self.class()))
791
+ } else if constraint_field & 0b0100000 != 0 {
792
+ OperandConstraint::Reuse(constraint_field & 0b0011111)
793
+ } else {
794
+ match constraint_field {
795
+ 0 => OperandConstraint::Any,
796
+ 1 => OperandConstraint::Reg,
797
+ 2 => OperandConstraint::Stack,
798
+ _ => unreachable!(),
799
+ }
800
+ }
801
+ }
802
+
803
+ /// If this operand is for a fixed non-allocatable register (see
804
+ /// [`Operand::fixed`]), then returns the physical register that it will
805
+ /// be assigned to.
806
+ #[inline(always)]
807
+ pub fn as_fixed_nonallocatable(self) -> Option<PReg> {
808
+ match self.constraint() {
809
+ OperandConstraint::FixedReg(preg) if self.vreg().vreg() == VReg::MAX => Some(preg),
810
+ _ => None,
811
+ }
812
+ }
813
+
814
+ /// Get the raw 32-bit encoding of this operand's fields.
815
+ #[inline(always)]
816
+ pub fn bits(self) -> u32 {
817
+ self.bits
818
+ }
819
+
820
+ /// Construct an `Operand` from the raw 32-bit encoding returned
821
+ /// from `bits()`.
822
+ #[inline(always)]
823
+ pub fn from_bits(bits: u32) -> Self {
824
+ debug_assert!(bits >> 29 <= 4);
825
+ Operand { bits }
826
+ }
827
+ }
828
+
829
+ impl core::fmt::Debug for Operand {
830
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
831
+ core::fmt::Display::fmt(self, f)
832
+ }
833
+ }
834
+
835
+ impl core::fmt::Display for Operand {
836
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
837
+ if let Some(preg) = self.as_fixed_nonallocatable() {
838
+ return write!(f, "Fixed: {preg}");
839
+ }
840
+ match (self.kind(), self.pos()) {
841
+ (OperandKind::Def, OperandPos::Late) | (OperandKind::Use, OperandPos::Early) => {
842
+ write!(f, "{:?}", self.kind())?;
843
+ }
844
+ _ => {
845
+ write!(f, "{:?}@{:?}", self.kind(), self.pos())?;
846
+ }
847
+ }
848
+ write!(
849
+ f,
850
+ ": {}{} {}",
851
+ self.vreg(),
852
+ match self.class() {
853
+ RegClass::Int => "i",
854
+ RegClass::Float => "f",
855
+ RegClass::Vector => "v",
856
+ },
857
+ self.constraint()
858
+ )
859
+ }
860
+ }
861
+
862
+ /// An Allocation represents the end result of regalloc for an
863
+ /// Operand.
864
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
865
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
866
+ pub struct Allocation {
867
+ /// Bit-pack in 32 bits.
868
+ ///
869
+ /// kind:3 unused:1 index:28
870
+ bits: u32,
871
+ }
872
+
873
+ impl core::fmt::Debug for Allocation {
874
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
875
+ core::fmt::Display::fmt(self, f)
876
+ }
877
+ }
878
+
879
+ impl core::fmt::Display for Allocation {
880
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
881
+ match self.kind() {
882
+ AllocationKind::None => write!(f, "none"),
883
+ AllocationKind::Reg => write!(f, "{}", self.as_reg().unwrap()),
884
+ AllocationKind::Stack => write!(f, "{}", self.as_stack().unwrap()),
885
+ }
886
+ }
887
+ }
888
+
889
+ impl Allocation {
890
+ /// Construct a new Allocation.
891
+ #[inline(always)]
892
+ pub(crate) fn new(kind: AllocationKind, index: usize) -> Self {
893
+ debug_assert!(index < (1 << 28));
894
+ Self {
895
+ bits: ((kind as u8 as u32) << 29) | (index as u32),
896
+ }
897
+ }
898
+
899
+ /// Get the "none" allocation, which is distinct from the other
900
+ /// possibilities and is used to initialize data structures.
901
+ #[inline(always)]
902
+ pub fn none() -> Allocation {
903
+ Allocation::new(AllocationKind::None, 0)
904
+ }
905
+
906
+ /// Create an allocation into a register.
907
+ #[inline(always)]
908
+ pub fn reg(preg: PReg) -> Allocation {
909
+ Allocation::new(AllocationKind::Reg, preg.index())
910
+ }
911
+
912
+ /// Create an allocation into a spillslot.
913
+ #[inline(always)]
914
+ pub fn stack(slot: SpillSlot) -> Allocation {
915
+ Allocation::new(AllocationKind::Stack, slot.bits as usize)
916
+ }
917
+
918
+ /// Get the allocation's "kind": none, register, or stack (spillslot).
919
+ #[inline(always)]
920
+ pub fn kind(self) -> AllocationKind {
921
+ match (self.bits >> 29) & 7 {
922
+ 0 => AllocationKind::None,
923
+ 1 => AllocationKind::Reg,
924
+ 2 => AllocationKind::Stack,
925
+ _ => unreachable!(),
926
+ }
927
+ }
928
+
929
+ /// Is the allocation "none"?
930
+ #[inline(always)]
931
+ pub fn is_none(self) -> bool {
932
+ self.kind() == AllocationKind::None
933
+ }
934
+
935
+ /// Is the allocation not "none"?
936
+ #[inline(always)]
937
+ pub fn is_some(self) -> bool {
938
+ self.kind() != AllocationKind::None
939
+ }
940
+
941
+ /// Is the allocation a register?
942
+ #[inline(always)]
943
+ pub fn is_reg(self) -> bool {
944
+ self.kind() == AllocationKind::Reg
945
+ }
946
+
947
+ /// Is the allocation on the stack (a spillslot)?
948
+ #[inline(always)]
949
+ pub fn is_stack(self) -> bool {
950
+ self.kind() == AllocationKind::Stack
951
+ }
952
+
953
+ /// Get the index of the spillslot or register. If register, this
954
+ /// is an index that can be used by `PReg::from_index()`.
955
+ #[inline(always)]
956
+ pub fn index(self) -> usize {
957
+ (self.bits & ((1 << 28) - 1)) as usize
958
+ }
959
+
960
+ /// Get the allocation as a physical register, if any.
961
+ #[inline(always)]
962
+ pub fn as_reg(self) -> Option<PReg> {
963
+ if self.kind() == AllocationKind::Reg {
964
+ Some(PReg::from_index(self.index()))
965
+ } else {
966
+ None
967
+ }
968
+ }
969
+
970
+ /// Get the allocation as a spillslot, if any.
971
+ #[inline(always)]
972
+ pub fn as_stack(self) -> Option<SpillSlot> {
973
+ if self.kind() == AllocationKind::Stack {
974
+ Some(SpillSlot {
975
+ bits: self.index() as u32,
976
+ })
977
+ } else {
978
+ None
979
+ }
980
+ }
981
+
982
+ /// Get the raw bits for the packed encoding of this allocation.
983
+ #[inline(always)]
984
+ pub fn bits(self) -> u32 {
985
+ self.bits
986
+ }
987
+
988
+ /// Construct an allocation from its packed encoding.
989
+ #[inline(always)]
990
+ pub fn from_bits(bits: u32) -> Self {
991
+ debug_assert!(bits >> 29 >= 5);
992
+ Self { bits }
993
+ }
994
+ }
995
+
996
+ /// An allocation is one of two "kinds" (or "none"): register or
997
+ /// spillslot/stack.
998
+ #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
999
+ #[repr(u8)]
1000
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1001
+ pub enum AllocationKind {
1002
+ None = 0,
1003
+ Reg = 1,
1004
+ Stack = 2,
1005
+ }
1006
+
1007
+ /// A trait defined by the regalloc client to provide access to its
1008
+ /// machine-instruction / CFG representation.
1009
+ ///
1010
+ /// (This trait's design is inspired by, and derives heavily from, the
1011
+ /// trait of the same name in regalloc.rs.)
1012
+ pub trait Function {
1013
+ // -------------
1014
+ // CFG traversal
1015
+ // -------------
1016
+
1017
+ /// How many instructions are there?
1018
+ fn num_insts(&self) -> usize;
1019
+
1020
+ /// How many blocks are there?
1021
+ fn num_blocks(&self) -> usize;
1022
+
1023
+ /// Get the index of the entry block.
1024
+ fn entry_block(&self) -> Block;
1025
+
1026
+ /// Provide the range of instruction indices contained in each block.
1027
+ fn block_insns(&self, block: Block) -> InstRange;
1028
+
1029
+ /// Get CFG successors for a given block.
1030
+ fn block_succs(&self, block: Block) -> &[Block];
1031
+
1032
+ /// Get the CFG predecessors for a given block.
1033
+ fn block_preds(&self, block: Block) -> &[Block];
1034
+
1035
+ /// Get the block parameters for a given block.
1036
+ fn block_params(&self, block: Block) -> &[VReg];
1037
+
1038
+ /// Determine whether an instruction is a return instruction.
1039
+ fn is_ret(&self, insn: Inst) -> bool;
1040
+
1041
+ /// Determine whether an instruction is the end-of-block
1042
+ /// branch.
1043
+ fn is_branch(&self, insn: Inst) -> bool;
1044
+
1045
+ /// If `insn` is a branch at the end of `block`, returns the
1046
+ /// outgoing blockparam arguments for the given successor. The
1047
+ /// number of arguments must match the number incoming blockparams
1048
+ /// for each respective successor block.
1049
+ fn branch_blockparams(&self, block: Block, insn: Inst, succ_idx: usize) -> &[VReg];
1050
+
1051
+ /// Determine whether an instruction requires all reference-typed
1052
+ /// values to be placed onto the stack. For these instructions,
1053
+ /// stackmaps will be provided.
1054
+ ///
1055
+ /// This is usually associated with the concept of a "safepoint",
1056
+ /// though strictly speaking, a safepoint could also support
1057
+ /// reference-typed values in registers if there were a way to
1058
+ /// denote their locations and if this were acceptable to the
1059
+ /// client. Usually garbage-collector implementations want to see
1060
+ /// roots on the stack, so we do that for now.
1061
+ fn requires_refs_on_stack(&self, _: Inst) -> bool {
1062
+ false
1063
+ }
1064
+
1065
+ // --------------------------
1066
+ // Instruction register slots
1067
+ // --------------------------
1068
+
1069
+ /// Get the Operands for an instruction.
1070
+ fn inst_operands(&self, insn: Inst) -> &[Operand];
1071
+
1072
+ /// Get the clobbers for an instruction; these are the registers
1073
+ /// that, after the instruction has executed, hold values that are
1074
+ /// arbitrary, separately from the usual outputs to the
1075
+ /// instruction. It is invalid to read a register that has been
1076
+ /// clobbered; the register allocator is free to assume that
1077
+ /// clobbered registers are filled with garbage and available for
1078
+ /// reuse. It will avoid storing any value in a clobbered register
1079
+ /// that must be live across the instruction.
1080
+ ///
1081
+ /// Another way of seeing this is that a clobber is equivalent to
1082
+ /// a "late def" of a fresh vreg that is not used anywhere else
1083
+ /// in the program, with a fixed-register constraint that places
1084
+ /// it in a given PReg chosen by the client prior to regalloc.
1085
+ ///
1086
+ /// Every register written by an instruction must either
1087
+ /// correspond to (be assigned to) an Operand of kind `Def`, or
1088
+ /// else must be a "clobber".
1089
+ ///
1090
+ /// This can be used to, for example, describe ABI-specified
1091
+ /// registers that are not preserved by a call instruction, or
1092
+ /// fixed physical registers written by an instruction but not
1093
+ /// used as a vreg output, or fixed physical registers used as
1094
+ /// temps within an instruction out of necessity.
1095
+ ///
1096
+ /// Note that it is legal for a register to be both a clobber and
1097
+ /// an actual def (via pinned vreg or via operand constrained to
1098
+ /// the reg). This is for convenience: e.g., a call instruction
1099
+ /// might have a constant clobber set determined by the ABI, but
1100
+ /// some of those clobbered registers are sometimes return
1101
+ /// value(s).
1102
+ fn inst_clobbers(&self, insn: Inst) -> PRegSet;
1103
+
1104
+ /// Get the number of `VReg` in use in this function.
1105
+ fn num_vregs(&self) -> usize;
1106
+
1107
+ /// Get the VRegs that are pointer/reference types. This has the
1108
+ /// following effects for each such vreg:
1109
+ ///
1110
+ /// - At all safepoint instructions, the vreg will be in a
1111
+ /// SpillSlot, not in a register.
1112
+ /// - The vreg *may not* be used as a register operand on
1113
+ /// safepoint instructions: this is because a vreg can only live
1114
+ /// in one place at a time. The client should copy the value to an
1115
+ /// integer-typed vreg and use this to pass a pointer as an input
1116
+ /// to a safepoint instruction (such as a function call).
1117
+ /// - At all safepoint instructions, all live vregs' locations
1118
+ /// will be included in a list in the `Output` below, so that
1119
+ /// pointer-inspecting/updating functionality (such as a moving
1120
+ /// garbage collector) may observe and edit their values.
1121
+ fn reftype_vregs(&self) -> &[VReg] {
1122
+ &[]
1123
+ }
1124
+
1125
+ /// Get the VRegs for which we should generate value-location
1126
+ /// metadata for debugging purposes. This can be used to generate
1127
+ /// e.g. DWARF with valid prgram-point ranges for each value
1128
+ /// expression in a way that is more efficient than a post-hoc
1129
+ /// analysis of the allocator's output.
1130
+ ///
1131
+ /// Each tuple is (vreg, inclusive_start, exclusive_end,
1132
+ /// label). In the `Output` there will be (label, inclusive_start,
1133
+ /// exclusive_end, alloc)` tuples. The ranges may not exactly
1134
+ /// match -- specifically, the returned metadata may cover only a
1135
+ /// subset of the requested ranges -- if the value is not live for
1136
+ /// the entire requested ranges.
1137
+ ///
1138
+ /// The instruction indices imply a program point just *before*
1139
+ /// the instruction.
1140
+ ///
1141
+ /// Precondition: we require this slice to be sorted by vreg.
1142
+ fn debug_value_labels(&self) -> &[(VReg, Inst, Inst, u32)] {
1143
+ &[]
1144
+ }
1145
+
1146
+ // --------------
1147
+ // Spills/reloads
1148
+ // --------------
1149
+
1150
+ /// How many logical spill slots does the given regclass require? E.g., on
1151
+ /// a 64-bit machine, spill slots may nominally be 64-bit words, but a
1152
+ /// 128-bit vector value will require two slots. The regalloc will always
1153
+ /// align on this size.
1154
+ ///
1155
+ /// (This trait method's design and doc text derives from
1156
+ /// regalloc.rs' trait of the same name.)
1157
+ fn spillslot_size(&self, regclass: RegClass) -> usize;
1158
+
1159
+ /// When providing a spillslot number for a multi-slot spillslot,
1160
+ /// do we provide the first or the last? This is usually related
1161
+ /// to which direction the stack grows and different clients may
1162
+ /// have different preferences.
1163
+ fn multi_spillslot_named_by_last_slot(&self) -> bool {
1164
+ false
1165
+ }
1166
+
1167
+ // -----------
1168
+ // Misc config
1169
+ // -----------
1170
+
1171
+ /// Allow a single instruction to define a vreg multiple times. If
1172
+ /// allowed, the semantics are as if the definition occurs only
1173
+ /// once, and all defs will get the same alloc. This flexibility is
1174
+ /// meant to allow the embedder to more easily aggregate operands
1175
+ /// together in macro/pseudoinstructions, or e.g. add additional
1176
+ /// clobbered vregs without taking care to deduplicate. This may be
1177
+ /// particularly useful when referring to physical registers via
1178
+ /// pinned vregs. It is optional functionality because a strict mode
1179
+ /// (at most one def per vreg) is also useful for finding bugs in
1180
+ /// other applications.
1181
+ fn allow_multiple_vreg_defs(&self) -> bool {
1182
+ false
1183
+ }
1184
+ }
1185
+
1186
+ /// A position before or after an instruction at which we can make an
1187
+ /// edit.
1188
+ ///
1189
+ /// Note that this differs from `OperandPos` in that the former
1190
+ /// describes specifically a constraint on an operand, while this
1191
+ /// describes a program point. `OperandPos` could grow more options in
1192
+ /// the future, for example if we decide that an "early write" or
1193
+ /// "late read" phase makes sense, while `InstPosition` will always
1194
+ /// describe these two insertion points.
1195
+ #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
1196
+ #[repr(u8)]
1197
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1198
+ pub enum InstPosition {
1199
+ Before = 0,
1200
+ After = 1,
1201
+ }
1202
+
1203
+ /// A program point: a single point before or after a given instruction.
1204
+ #[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
1205
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1206
+ pub struct ProgPoint {
1207
+ bits: u32,
1208
+ }
1209
+
1210
+ impl core::fmt::Debug for ProgPoint {
1211
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1212
+ write!(
1213
+ f,
1214
+ "progpoint{}{}",
1215
+ self.inst().index(),
1216
+ match self.pos() {
1217
+ InstPosition::Before => "-pre",
1218
+ InstPosition::After => "-post",
1219
+ }
1220
+ )
1221
+ }
1222
+ }
1223
+
1224
+ impl ProgPoint {
1225
+ /// Create a new ProgPoint before or after the given instruction.
1226
+ #[inline(always)]
1227
+ pub fn new(inst: Inst, pos: InstPosition) -> Self {
1228
+ let bits = ((inst.0 as u32) << 1) | (pos as u8 as u32);
1229
+ Self { bits }
1230
+ }
1231
+
1232
+ /// Create a new ProgPoint before the given instruction.
1233
+ #[inline(always)]
1234
+ pub fn before(inst: Inst) -> Self {
1235
+ Self::new(inst, InstPosition::Before)
1236
+ }
1237
+
1238
+ /// Create a new ProgPoint after the given instruction.
1239
+ #[inline(always)]
1240
+ pub fn after(inst: Inst) -> Self {
1241
+ Self::new(inst, InstPosition::After)
1242
+ }
1243
+
1244
+ /// Get the instruction that this ProgPoint is before or after.
1245
+ #[inline(always)]
1246
+ pub fn inst(self) -> Inst {
1247
+ // Cast to i32 to do an arithmetic right-shift, which will
1248
+ // preserve an `Inst::invalid()` (which is -1, or all-ones).
1249
+ Inst::new(((self.bits as i32) >> 1) as usize)
1250
+ }
1251
+
1252
+ /// Get the "position" (Before or After) relative to the
1253
+ /// instruction.
1254
+ #[inline(always)]
1255
+ pub fn pos(self) -> InstPosition {
1256
+ match self.bits & 1 {
1257
+ 0 => InstPosition::Before,
1258
+ 1 => InstPosition::After,
1259
+ _ => unreachable!(),
1260
+ }
1261
+ }
1262
+
1263
+ /// Get the "next" program point: for After, this is the Before of
1264
+ /// the next instruction, while for Before, this is After of the
1265
+ /// same instruction.
1266
+ #[inline(always)]
1267
+ pub fn next(self) -> ProgPoint {
1268
+ Self {
1269
+ bits: self.bits + 1,
1270
+ }
1271
+ }
1272
+
1273
+ /// Get the "previous" program point, the inverse of `.next()`
1274
+ /// above.
1275
+ #[inline(always)]
1276
+ pub fn prev(self) -> ProgPoint {
1277
+ Self {
1278
+ bits: self.bits - 1,
1279
+ }
1280
+ }
1281
+
1282
+ /// Convert to a raw encoding in 32 bits.
1283
+ #[inline(always)]
1284
+ pub fn to_index(self) -> u32 {
1285
+ self.bits
1286
+ }
1287
+
1288
+ /// Construct from the raw 32-bit encoding.
1289
+ #[inline(always)]
1290
+ pub fn from_index(index: u32) -> Self {
1291
+ Self { bits: index }
1292
+ }
1293
+ }
1294
+
1295
+ /// An instruction to insert into the program to perform some data movement.
1296
+ #[derive(Clone, Debug)]
1297
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1298
+ pub enum Edit {
1299
+ /// Move one allocation to another. Each allocation may be a
1300
+ /// register or a stack slot (spillslot). However, stack-to-stack
1301
+ /// moves will never be generated.
1302
+ ///
1303
+ /// `Move` edits will be generated even if src and dst allocation
1304
+ /// are the same if the vreg changes; this allows proper metadata
1305
+ /// tracking even when moves are elided.
1306
+ Move { from: Allocation, to: Allocation },
1307
+ }
1308
+
1309
+ /// Wrapper around either an original instruction or an inserted edit.
1310
+ #[derive(Clone, Debug)]
1311
+ pub enum InstOrEdit<'a> {
1312
+ Inst(Inst),
1313
+ Edit(&'a Edit),
1314
+ }
1315
+
1316
+ /// Iterator over the instructions and edits in a block.
1317
+ pub struct OutputIter<'a> {
1318
+ /// List of edits starting at the first for the current block.
1319
+ edits: &'a [(ProgPoint, Edit)],
1320
+
1321
+ /// Remaining instructions in the current block.
1322
+ inst_range: InstRange,
1323
+ }
1324
+
1325
+ impl<'a> Iterator for OutputIter<'a> {
1326
+ type Item = InstOrEdit<'a>;
1327
+
1328
+ fn next(&mut self) -> Option<InstOrEdit<'a>> {
1329
+ // There can't be any edits after the last instruction in a block, so
1330
+ // we don't need to worry about that case.
1331
+ if self.inst_range.len() == 0 {
1332
+ return None;
1333
+ }
1334
+
1335
+ // Return any edits that happen before the next instruction first.
1336
+ let next_inst = self.inst_range.first();
1337
+ if let Some((edit, remaining_edits)) = self.edits.split_first() {
1338
+ if edit.0 <= ProgPoint::before(next_inst) {
1339
+ self.edits = remaining_edits;
1340
+ return Some(InstOrEdit::Edit(&edit.1));
1341
+ }
1342
+ }
1343
+
1344
+ self.inst_range = self.inst_range.rest();
1345
+ Some(InstOrEdit::Inst(next_inst))
1346
+ }
1347
+ }
1348
+
1349
+ /// A machine environment tells the register allocator which registers
1350
+ /// are available to allocate and what register may be used as a
1351
+ /// scratch register for each class, and some other miscellaneous info
1352
+ /// as well.
1353
+ #[derive(Clone, Debug)]
1354
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1355
+ pub struct MachineEnv {
1356
+ /// Preferred physical registers for each class. These are the
1357
+ /// registers that will be allocated first, if free.
1358
+ ///
1359
+ /// If an explicit scratch register is provided in `scratch_by_class` then
1360
+ /// it must not appear in this list.
1361
+ pub preferred_regs_by_class: [Vec<PReg>; 3],
1362
+
1363
+ /// Non-preferred physical registers for each class. These are the
1364
+ /// registers that will be allocated if a preferred register is
1365
+ /// not available; using one of these is considered suboptimal,
1366
+ /// but still better than spilling.
1367
+ ///
1368
+ /// If an explicit scratch register is provided in `scratch_by_class` then
1369
+ /// it must not appear in this list.
1370
+ pub non_preferred_regs_by_class: [Vec<PReg>; 3],
1371
+
1372
+ /// Optional dedicated scratch register per class. This is needed to perform
1373
+ /// moves between registers when cyclic move patterns occur. The
1374
+ /// register should not be placed in either the preferred or
1375
+ /// non-preferred list (i.e., it is not otherwise allocatable).
1376
+ ///
1377
+ /// Note that the register allocator will freely use this register
1378
+ /// between instructions, but *within* the machine code generated
1379
+ /// by a single (regalloc-level) instruction, the client is free
1380
+ /// to use the scratch register. E.g., if one "instruction" causes
1381
+ /// the emission of two machine-code instructions, this lowering
1382
+ /// can use the scratch register between them.
1383
+ ///
1384
+ /// If a scratch register is not provided then the register allocator will
1385
+ /// automatically allocate one as needed, spilling a value to the stack if
1386
+ /// necessary.
1387
+ pub scratch_by_class: [Option<PReg>; 3],
1388
+
1389
+ /// Some `PReg`s can be designated as locations on the stack rather than
1390
+ /// actual registers. These can be used to tell the register allocator about
1391
+ /// pre-defined stack slots used for function arguments and return values.
1392
+ ///
1393
+ /// `PReg`s in this list cannot be used as an allocatable or scratch
1394
+ /// register.
1395
+ pub fixed_stack_slots: Vec<PReg>,
1396
+ }
1397
+
1398
+ /// The output of the register allocator.
1399
+ #[derive(Clone, Debug)]
1400
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1401
+ pub struct Output {
1402
+ /// How many spillslots are needed in the frame?
1403
+ pub num_spillslots: usize,
1404
+
1405
+ /// Edits (insertions or removals). Guaranteed to be sorted by
1406
+ /// program point.
1407
+ pub edits: Vec<(ProgPoint, Edit)>,
1408
+
1409
+ /// Allocations for each operand. Mapping from instruction to
1410
+ /// allocations provided by `inst_alloc_offsets` below.
1411
+ pub allocs: Vec<Allocation>,
1412
+
1413
+ /// Allocation offset in `allocs` for each instruction.
1414
+ pub inst_alloc_offsets: Vec<u32>,
1415
+
1416
+ /// Safepoint records: at a given program point, a reference-typed value
1417
+ /// lives in the given Allocation. Currently these are guaranteed to be
1418
+ /// stack slots, but in the future an option may be added to allow
1419
+ /// reftype value to be kept in registers at safepoints.
1420
+ pub safepoint_slots: Vec<(ProgPoint, Allocation)>,
1421
+
1422
+ /// Debug info: a labeled value (as applied to vregs by
1423
+ /// `Function::debug_value_labels()` on the input side) is located
1424
+ /// in the given allocation from the first program point
1425
+ /// (inclusive) to the second (exclusive). Guaranteed to be sorted
1426
+ /// by label and program point, and the ranges are guaranteed to
1427
+ /// be disjoint.
1428
+ pub debug_locations: Vec<(u32, ProgPoint, ProgPoint, Allocation)>,
1429
+
1430
+ /// Internal stats from the allocator.
1431
+ pub stats: ion::Stats,
1432
+ }
1433
+
1434
+ impl Output {
1435
+ /// Get the allocations assigned to a given instruction.
1436
+ pub fn inst_allocs(&self, inst: Inst) -> &[Allocation] {
1437
+ let start = self.inst_alloc_offsets[inst.index()] as usize;
1438
+ let end = if inst.index() + 1 == self.inst_alloc_offsets.len() {
1439
+ self.allocs.len()
1440
+ } else {
1441
+ self.inst_alloc_offsets[inst.index() + 1] as usize
1442
+ };
1443
+ &self.allocs[start..end]
1444
+ }
1445
+
1446
+ /// Returns an iterator over the instructions and edits in a block, in
1447
+ /// order.
1448
+ pub fn block_insts_and_edits(&self, func: &impl Function, block: Block) -> OutputIter<'_> {
1449
+ let inst_range = func.block_insns(block);
1450
+
1451
+ let edit_idx = self
1452
+ .edits
1453
+ .binary_search_by(|&(pos, _)| {
1454
+ // This predicate effectively searches for a point *just* before
1455
+ // the first ProgPoint. This never returns Ordering::Equal, but
1456
+ // binary_search_by returns the index of where it would have
1457
+ // been inserted in Err.
1458
+ if pos < ProgPoint::before(inst_range.first()) {
1459
+ core::cmp::Ordering::Less
1460
+ } else {
1461
+ core::cmp::Ordering::Greater
1462
+ }
1463
+ })
1464
+ .unwrap_err();
1465
+
1466
+ let edits = &self.edits[edit_idx..];
1467
+ OutputIter { inst_range, edits }
1468
+ }
1469
+ }
1470
+
1471
+ /// An error that prevents allocation.
1472
+ #[derive(Clone, Debug)]
1473
+ #[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
1474
+ pub enum RegAllocError {
1475
+ /// Critical edge is not split between given blocks.
1476
+ CritEdge(Block, Block),
1477
+ /// Invalid SSA for given vreg at given inst: multiple defs or
1478
+ /// illegal use. `inst` may be `Inst::invalid()` if this concerns
1479
+ /// a block param.
1480
+ SSA(VReg, Inst),
1481
+ /// Invalid basic block: does not end in branch/ret, or contains a
1482
+ /// branch/ret in the middle.
1483
+ BB(Block),
1484
+ /// Invalid branch: operand count does not match sum of block
1485
+ /// params of successor blocks.
1486
+ Branch(Inst),
1487
+ /// A VReg is live-in on entry; this is not allowed.
1488
+ EntryLivein,
1489
+ /// A branch has non-blockparam arg(s) and at least one of the
1490
+ /// successor blocks has more than one predecessor, forcing
1491
+ /// edge-moves before this branch. This is disallowed because it
1492
+ /// places a use after the edge moves occur; insert an edge block
1493
+ /// to avoid the situation.
1494
+ DisallowedBranchArg(Inst),
1495
+ /// Too many pinned VRegs + Reg-constrained Operands are live at
1496
+ /// once, making allocation impossible.
1497
+ TooManyLiveRegs,
1498
+ }
1499
+
1500
+ impl core::fmt::Display for RegAllocError {
1501
+ fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1502
+ write!(f, "{:?}", self)
1503
+ }
1504
+ }
1505
+
1506
+ #[cfg(feature = "std")]
1507
+ impl std::error::Error for RegAllocError {}
1508
+
1509
+ /// Run the allocator.
1510
+ pub fn run<F: Function>(
1511
+ func: &F,
1512
+ env: &MachineEnv,
1513
+ options: &RegallocOptions,
1514
+ ) -> Result<Output, RegAllocError> {
1515
+ ion::run(func, env, options.verbose_log, options.validate_ssa)
1516
+ }
1517
+
1518
+ /// Options for allocation.
1519
+ #[derive(Clone, Copy, Debug, Default)]
1520
+ pub struct RegallocOptions {
1521
+ /// Add extra verbosity to debug logs.
1522
+ pub verbose_log: bool,
1523
+
1524
+ /// Run the SSA validator before allocating registers.
1525
+ pub validate_ssa: bool,
1526
+ }