wasmtime 9.0.4 → 10.0.1

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Files changed (1933) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +184 -101
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/build.rs +2 -2
  5. data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
  33. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
  34. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
  35. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
  36. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
  37. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
  38. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
  39. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
  40. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
  41. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
  42. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
  43. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
  44. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
  45. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
  46. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
  47. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
  48. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
  49. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
  50. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
  51. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
  52. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
  53. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
  54. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
  55. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
  56. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
  57. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
  58. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
  59. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
  60. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
  61. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
  62. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
  63. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
  64. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
  65. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
  66. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
  67. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
  68. data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
  69. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
  70. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
  71. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
  72. data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
  73. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
  74. data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
  75. data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
  76. data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
  77. data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
  78. data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
  79. data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
  80. data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
  81. data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
  82. data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
  83. data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
  84. data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
  85. data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
  87. data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
  89. data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
  90. data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
  91. data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
  92. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
  93. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
  94. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
  95. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
  96. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
  97. data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
  98. data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
  99. data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
  100. data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
  101. data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
  102. data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
  103. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
  104. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
  105. data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
  106. data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
  107. data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
  108. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
  109. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
  110. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
  111. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
  112. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
  113. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
  114. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
  115. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
  116. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
  117. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
  118. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
  119. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
  120. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
  121. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
  122. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
  123. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
  124. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
  125. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
  126. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
  127. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
  128. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
  129. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
  130. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
  131. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
  132. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
  133. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
  134. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
  135. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
  136. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
  137. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
  138. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
  139. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
  140. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
  141. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
  142. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
  143. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
  144. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
  145. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
  146. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
  147. data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
  148. data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
  149. data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
  150. data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
  151. data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
  152. data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
  153. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
  154. data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
  155. data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
  156. data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
  157. data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
  158. data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
  159. data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
  160. data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
  161. data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
  162. data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
  163. data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
  164. data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
  165. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
  166. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
  167. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
  168. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
  169. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
  170. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
  171. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
  172. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out_ref.txt +17053 -0
  173. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
  174. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in_ref.txt +23945 -0
  175. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
  176. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out_ref.txt +23944 -0
  177. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in.txt +8841 -0
  178. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_in_ref.txt +8841 -0
  179. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
  180. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out_ref.txt +7404 -0
  181. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in.txt +8841 -0
  182. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_in_ref.txt +8841 -0
  183. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out.txt +7341 -0
  184. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0208_out_ref.txt +7341 -0
  185. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in.txt +8841 -0
  186. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/jis0212_in_ref.txt +8841 -0
  187. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
  188. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in_ref.txt +11285 -0
  189. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out.txt +7355 -0
  190. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_out_ref.txt +7355 -0
  191. data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_labels_names.rs +242 -0
  192. data/ext/cargo-vendor/encoding_rs-0.8.32/src/testing.rs +262 -0
  193. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_16.rs +472 -0
  194. data/ext/cargo-vendor/encoding_rs-0.8.32/src/utf_8.rs +1629 -0
  195. data/ext/cargo-vendor/encoding_rs-0.8.32/src/variant.rs +400 -0
  196. data/ext/cargo-vendor/encoding_rs-0.8.32/src/x_user_defined.rs +249 -0
  197. data/ext/cargo-vendor/equivalent-1.0.1/.cargo-checksum.json +1 -0
  198. data/ext/cargo-vendor/equivalent-1.0.1/Cargo.toml +27 -0
  199. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-APACHE +201 -0
  200. data/ext/cargo-vendor/equivalent-1.0.1/LICENSE-MIT +25 -0
  201. data/ext/cargo-vendor/equivalent-1.0.1/README.md +25 -0
  202. data/ext/cargo-vendor/equivalent-1.0.1/src/lib.rs +113 -0
  203. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/.cargo-checksum.json +1 -0
  204. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/Cargo.toml +36 -0
  205. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/run-tests.sh +12 -0
  206. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/src/lib.rs +200 -0
  207. data/ext/cargo-vendor/file-per-thread-logger-0.2.0/tests/test.rs +323 -0
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  1363. data/ext/cargo-vendor/wit-parser-0.7.1/tests/ui/worlds.wit +0 -40
  1364. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/LICENSE +0 -0
  1365. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/README.md +0 -0
  1366. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/lib.rs +0 -0
  1367. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/map.rs +0 -0
  1368. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/node.rs +0 -0
  1369. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/path.rs +0 -0
  1370. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/pool.rs +0 -0
  1371. /data/ext/cargo-vendor/{cranelift-bforest-0.96.4 → cranelift-bforest-0.97.1}/src/set.rs +0 -0
  1372. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/LICENSE +0 -0
  1373. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/README.md +0 -0
  1374. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/build.rs +0 -0
  1375. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/alias_analysis.rs +0 -0
  1376. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/mod.rs +0 -0
  1377. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/binemit/stack_map.rs +0 -0
  1378. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/bitset.rs +0 -0
  1379. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cfg_printer.rs +0 -0
  1380. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/constant_hash.rs +0 -0
  1381. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/context.rs +0 -0
  1382. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ctxhash.rs +0 -0
  1383. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/cursor.rs +0 -0
  1384. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/data_value.rs +0 -0
  1385. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dbg.rs +0 -0
  1386. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dce.rs +0 -0
  1387. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/dominator_tree.rs +0 -0
  1388. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/cost.rs +0 -0
  1389. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/domtree.rs +0 -0
  1390. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph/elaborate.rs +0 -0
  1391. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/egraph.rs +0 -0
  1392. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/flowgraph.rs +0 -0
  1393. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/fx.rs +0 -0
  1394. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/incremental_cache.rs +0 -0
  1395. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/inst_predicates.rs +0 -0
  1396. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/atomic_rmw_op.rs +0 -0
  1397. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/builder.rs +0 -0
  1398. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/condcodes.rs +0 -0
  1399. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/constant.rs +0 -0
  1400. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dfg.rs +0 -0
  1401. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/dynamic_type.rs +0 -0
  1402. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/entities.rs +0 -0
  1403. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extfunc.rs +0 -0
  1404. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/extname.rs +0 -0
  1405. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/function.rs +0 -0
  1406. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/globalvalue.rs +0 -0
  1407. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/immediates.rs +0 -0
  1408. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/instructions.rs +0 -0
  1409. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/jumptable.rs +0 -0
  1410. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/known_symbol.rs +0 -0
  1411. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/layout.rs +0 -0
  1412. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/libcall.rs +0 -0
  1413. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/memflags.rs +0 -0
  1414. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/mod.rs +0 -0
  1415. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/progpoint.rs +0 -0
  1416. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/sourceloc.rs +0 -0
  1417. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/stackslot.rs +0 -0
  1418. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/table.rs +0 -0
  1419. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/ir/types.rs +0 -0
  1420. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/args.rs +0 -0
  1421. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/regs.rs +0 -0
  1422. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind/systemv.rs +0 -0
  1423. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst/unwind.rs +0 -0
  1424. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/inst_neon.isle +0 -0
  1425. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower/isle/generated_code.rs +0 -0
  1426. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower.rs +0 -0
  1427. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/lower_dynamic_neon.isle +0 -0
  1428. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/aarch64/settings.rs +0 -0
  1429. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/call_conv.rs +0 -0
  1430. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/inst/unwind.rs +0 -0
  1431. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  1432. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/lower.rs +0 -0
  1433. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/riscv64/settings.rs +0 -0
  1434. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/args.rs +0 -0
  1435. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/imms.rs +0 -0
  1436. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/regs.rs +0 -0
  1437. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  1438. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/inst/unwind.rs +0 -0
  1439. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  1440. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower/isle.rs +0 -0
  1441. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/lower.rs +0 -0
  1442. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/s390x/settings.rs +0 -0
  1443. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/systemv.rs +0 -0
  1444. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind/winx64.rs +0 -0
  1445. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/unwind.rs +0 -0
  1446. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/encoding/mod.rs +0 -0
  1447. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/regs.rs +0 -0
  1448. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  1449. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  1450. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/inst/unwind.rs +0 -0
  1451. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  1452. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/isa/x64/settings.rs +0 -0
  1453. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/iterators.rs +0 -0
  1454. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/globalvalue.rs +0 -0
  1455. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/mod.rs +0 -0
  1456. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/legalizer/table.rs +0 -0
  1457. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/lib.rs +0 -0
  1458. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/loop_analysis.rs +0 -0
  1459. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/blockorder.rs +0 -0
  1460. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/helpers.rs +0 -0
  1461. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/inst_common.rs +0 -0
  1462. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/machinst/valueregs.rs +0 -0
  1463. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/nan_canonicalization.rs +0 -0
  1464. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/README.md +0 -0
  1465. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/arithmetic.isle +0 -0
  1466. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/bitops.isle +0 -0
  1467. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/cprop.isle +0 -0
  1468. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/extends.isle +0 -0
  1469. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/generated_code.rs +0 -0
  1470. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/icmp.isle +0 -0
  1471. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/remat.isle +0 -0
  1472. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/selects.isle +0 -0
  1473. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts/shifts.isle +0 -0
  1474. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/opts.rs +0 -0
  1475. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/prelude_opt.isle +0 -0
  1476. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/print_errors.rs +0 -0
  1477. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/remove_constant_phis.rs +0 -0
  1478. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/result.rs +0 -0
  1479. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/scoped_hash_map.rs +0 -0
  1480. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/souper_harvest.rs +0 -0
  1481. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/timing.rs +0 -0
  1482. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unionfind.rs +0 -0
  1483. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/unreachable_code.rs +0 -0
  1484. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/value_label.rs +0 -0
  1485. /data/ext/cargo-vendor/{cranelift-codegen-0.96.4 → cranelift-codegen-0.97.1}/src/write.rs +0 -0
  1486. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/LICENSE +0 -0
  1487. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/README.md +0 -0
  1488. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/formats.rs +0 -0
  1489. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/instructions.rs +0 -0
  1490. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/isa.rs +0 -0
  1491. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/mod.rs +0 -0
  1492. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/operands.rs +0 -0
  1493. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/settings.rs +0 -0
  1494. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/types.rs +0 -0
  1495. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/cdsl/typevar.rs +0 -0
  1496. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/constant_hash.rs +0 -0
  1497. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/error.rs +0 -0
  1498. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_inst.rs +0 -0
  1499. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_settings.rs +0 -0
  1500. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/gen_types.rs +0 -0
  1501. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/arm64.rs +0 -0
  1502. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/mod.rs +0 -0
  1503. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/riscv64.rs +0 -0
  1504. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/isa/s390x.rs +0 -0
  1505. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/lib.rs +0 -0
  1506. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/entities.rs +0 -0
  1507. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/formats.rs +0 -0
  1508. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/immediates.rs +0 -0
  1509. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/instructions.rs +0 -0
  1510. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/mod.rs +0 -0
  1511. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/shared/types.rs +0 -0
  1512. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/srcgen.rs +0 -0
  1513. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.96.4 → cranelift-codegen-meta-0.97.1}/src/unique_table.rs +0 -0
  1514. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/LICENSE +0 -0
  1515. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/README.md +0 -0
  1516. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constant_hash.rs +0 -0
  1517. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/constants.rs +0 -0
  1518. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.96.4 → cranelift-codegen-shared-0.97.1}/src/lib.rs +0 -0
  1519. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/LICENSE +0 -0
  1520. /data/ext/cargo-vendor/{cranelift-control-0.96.4 → cranelift-control-0.97.1}/README.md +0 -0
  1521. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/LICENSE +0 -0
  1522. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/README.md +0 -0
  1523. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/boxed_slice.rs +0 -0
  1524. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/iter.rs +0 -0
  1525. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/keys.rs +0 -0
  1526. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/lib.rs +0 -0
  1527. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/map.rs +0 -0
  1528. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/packed_option.rs +0 -0
  1529. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/primary.rs +0 -0
  1530. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/set.rs +0 -0
  1531. /data/ext/cargo-vendor/{cranelift-entity-0.96.4 → cranelift-entity-0.97.1}/src/sparse.rs +0 -0
  1532. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/LICENSE +0 -0
  1533. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/README.md +0 -0
  1534. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/frontend.rs +0 -0
  1535. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/lib.rs +0 -0
  1536. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/ssa.rs +0 -0
  1537. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/switch.rs +0 -0
  1538. /data/ext/cargo-vendor/{cranelift-frontend-0.96.4 → cranelift-frontend-0.97.1}/src/variable.rs +0 -0
  1539. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/README.md +0 -0
  1540. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/build.rs +0 -0
  1541. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bad_converters.isle +0 -0
  1542. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
  1543. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/converter_extractor_constructor.isle +0 -0
  1544. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/error1.isle +0 -0
  1545. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/extra_parens.isle +0 -0
  1546. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_expression.isle +0 -0
  1547. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/impure_rhs.isle +0 -0
  1548. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_internal_etor.isle +0 -0
  1549. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/fail/multi_prio.isle +0 -0
  1550. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows.isle +0 -0
  1551. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/borrows_main.rs +0 -0
  1552. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets.isle +0 -0
  1553. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/iflets_main.rs +0 -0
  1554. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor.isle +0 -0
  1555. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_constructor_main.rs +0 -0
  1556. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor.isle +0 -0
  1557. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/multi_extractor_main.rs +0 -0
  1558. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test.isle +0 -0
  1559. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/link/test_main.rs +0 -0
  1560. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/bound_var.isle +0 -0
  1561. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/construct_and_extract.isle +0 -0
  1562. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions.isle +0 -0
  1563. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/conversions_extern.isle +0 -0
  1564. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/let.isle +0 -0
  1565. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/nodebug.isle +0 -0
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  1567. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test2.isle +0 -0
  1568. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test3.isle +0 -0
  1569. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/test4.isle +0 -0
  1570. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/pass/tutorial.isle +0 -0
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  1572. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/iconst_main.rs +0 -0
  1573. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing.isle +0 -0
  1574. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/isle_examples/run/let_shadowing_main.rs +0 -0
  1575. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/ast.rs +0 -0
  1576. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/codegen.rs +0 -0
  1577. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/compile.rs +0 -0
  1578. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/error.rs +0 -0
  1579. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lexer.rs +0 -0
  1580. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/lib.rs +0 -0
  1581. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/log.rs +0 -0
  1582. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/overlap.rs +0 -0
  1583. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/parser.rs +0 -0
  1584. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/sema.rs +0 -0
  1585. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/serialize.rs +0 -0
  1586. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/src/trie_again.rs +0 -0
  1587. /data/ext/cargo-vendor/{cranelift-isle-0.96.4 → cranelift-isle-0.97.1}/tests/run_tests.rs +0 -0
  1588. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/LICENSE +0 -0
  1589. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/README.md +0 -0
  1590. /data/ext/cargo-vendor/{cranelift-native-0.96.4 → cranelift-native-0.97.1}/src/riscv.rs +0 -0
  1591. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/LICENSE +0 -0
  1592. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/README.md +0 -0
  1593. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/code_translator/bounds_checks.rs +0 -0
  1594. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/environ/mod.rs +0 -0
  1595. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/heap.rs +0 -0
  1596. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/lib.rs +0 -0
  1597. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/module_translator.rs +0 -0
  1598. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/src/state.rs +0 -0
  1599. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/tests/wasm_testsuite.rs +0 -0
  1600. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/arith.wat +0 -0
  1601. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/br_table.wat +0 -0
  1602. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call-simd.wat +0 -0
  1603. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/call.wat +0 -0
  1604. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fannkuch.wat +0 -0
  1605. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_fasta.wat +0 -0
  1606. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_ifs.wat +0 -0
  1607. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/embenchen_primes.wat +0 -0
  1608. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fac-multi-value.wat +0 -0
  1609. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/fibonacci.wat +0 -0
  1610. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/globals.wat +0 -0
  1611. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall-simd.wat +0 -0
  1612. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/icall.wat +0 -0
  1613. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-0.wat +0 -0
  1614. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-1.wat +0 -0
  1615. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-2.wat +0 -0
  1616. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-3.wat +0 -0
  1617. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-4.wat +0 -0
  1618. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-5.wat +0 -0
  1619. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-reachability-translation-6.wat +0 -0
  1620. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params-2.wat +0 -0
  1621. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/if-unreachable-else-params.wat +0 -0
  1622. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  1623. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/memory.wat +0 -0
  1624. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-0.wat +0 -0
  1625. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-1.wat +0 -0
  1626. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-10.wat +0 -0
  1627. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-11.wat +0 -0
  1628. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-12.wat +0 -0
  1629. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-13.wat +0 -0
  1630. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-14.wat +0 -0
  1631. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-15.wat +0 -0
  1632. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-16.wat +0 -0
  1633. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-17.wat +0 -0
  1634. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-2.wat +0 -0
  1635. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-3.wat +0 -0
  1636. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-4.wat +0 -0
  1637. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-5.wat +0 -0
  1638. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-6.wat +0 -0
  1639. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-7.wat +0 -0
  1640. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-8.wat +0 -0
  1641. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/multi-9.wat +0 -0
  1642. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/nullref.wat +0 -0
  1643. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/passive-data.wat +0 -0
  1644. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2303.wat +0 -0
  1645. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/pr2559.wat +0 -0
  1646. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/ref-func-0.wat +0 -0
  1647. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/rust_fannkuch.wat +0 -0
  1648. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/select.wat +0 -0
  1649. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd-store.wat +0 -0
  1650. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/simd.wat +0 -0
  1651. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/table-copy.wat +0 -0
  1652. /data/ext/cargo-vendor/{cranelift-wasm-0.96.4 → cranelift-wasm-0.97.1}/wasmtests/unreachable_code.wat +0 -0
  1653. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/LICENSE +0 -0
  1654. /data/ext/cargo-vendor/{file-per-thread-logger-0.1.6 → file-per-thread-logger-0.2.0}/README.md +0 -0
  1655. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/LICENSE +0 -0
  1656. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/README.md +0 -0
  1657. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/DESIGN.md +0 -0
  1658. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/doc/TODO +0 -0
  1659. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/cfg.rs +0 -0
  1660. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/domtree.rs +0 -0
  1661. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/fuzzing/mod.rs +0 -0
  1662. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/indexset.rs +0 -0
  1663. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/dump.rs +0 -0
  1664. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/redundant_moves.rs +0 -0
  1665. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ion/reg_traversal.rs +0 -0
  1666. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/postorder.rs +0 -0
  1667. /data/ext/cargo-vendor/{regalloc2-0.8.1 → regalloc2-0.9.2}/src/ssa.rs +0 -0
  1668. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/LICENSE +0 -0
  1669. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/README.md +0 -0
  1670. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/clocks.rs +0 -0
  1671. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/file.rs +0 -0
  1672. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/net.rs +0 -0
  1673. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/unix.rs +0 -0
  1674. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched/windows.rs +0 -0
  1675. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/sched.rs +0 -0
  1676. /data/ext/cargo-vendor/{wasi-cap-std-sync-9.0.4 → wasi-cap-std-sync-10.0.1}/src/stdio.rs +0 -0
  1677. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/LICENSE +0 -0
  1678. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/README.md +0 -0
  1679. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/README.md +0 -0
  1680. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/docs/README.md +0 -0
  1681. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/README.md +0 -0
  1682. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/docs.md +0 -0
  1683. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/typenames.witx +0 -0
  1684. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_args.witx +0 -0
  1685. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_clock.witx +0 -0
  1686. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_environ.witx +0 -0
  1687. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_fd.witx +0 -0
  1688. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_path.witx +0 -0
  1689. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_poll.witx +0 -0
  1690. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_proc.witx +0 -0
  1691. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_random.witx +0 -0
  1692. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sched.witx +0 -0
  1693. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/ephemeral/witx/wasi_ephemeral_sock.witx +0 -0
  1694. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/docs.md +0 -0
  1695. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/typenames.witx +0 -0
  1696. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/old/snapshot_0/witx/wasi_unstable.witx +0 -0
  1697. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.html +0 -0
  1698. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/docs.md +0 -0
  1699. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/typenames.witx +0 -0
  1700. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/phases/snapshot/witx/wasi_snapshot_preview1.witx +0 -0
  1701. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposal-template/README.md +0 -0
  1702. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/proposals/README.md +0 -0
  1703. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/snapshots/README.md +0 -0
  1704. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/WASI/standard/README.md +0 -0
  1705. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/build.rs +0 -0
  1706. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/clocks.rs +0 -0
  1707. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/dir.rs +0 -0
  1708. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/error.rs +0 -0
  1709. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/lib.rs +0 -0
  1710. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/pipe.rs +0 -0
  1711. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/random.rs +0 -0
  1712. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched/subscription.rs +0 -0
  1713. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/sched.rs +0 -0
  1714. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/mod.rs +0 -0
  1715. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_0.rs +0 -0
  1716. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/snapshots/preview_1/error.rs +0 -0
  1717. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/string_array.rs +0 -0
  1718. /data/ext/cargo-vendor/{wasi-common-9.0.4 → wasi-common-10.0.1}/src/table.rs +0 -0
  1719. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasm-encoder-0.29.0}/LICENSE +0 -0
  1720. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmparser-0.107.0}/LICENSE +0 -0
  1721. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/README.md +0 -0
  1722. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/examples/simple.rs +0 -0
  1723. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/limits.rs +0 -0
  1724. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/aliases.rs +0 -0
  1725. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/names.rs +0 -0
  1726. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component/start.rs +0 -0
  1727. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/component.rs +0 -0
  1728. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/code.rs +0 -0
  1729. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/custom.rs +0 -0
  1730. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/data.rs +0 -0
  1731. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/elements.rs +0 -0
  1732. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/exports.rs +0 -0
  1733. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/functions.rs +0 -0
  1734. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/globals.rs +0 -0
  1735. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/imports.rs +0 -0
  1736. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/init.rs +0 -0
  1737. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/memories.rs +0 -0
  1738. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/names.rs +0 -0
  1739. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/operators.rs +0 -0
  1740. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tables.rs +0 -0
  1741. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers/core/tags.rs +0 -0
  1742. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/readers.rs +0 -0
  1743. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/resources.rs +0 -0
  1744. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/src/validator/func.rs +0 -0
  1745. /data/ext/cargo-vendor/{wasmparser-0.103.0 → wasmparser-0.107.0}/tests/big-module.rs +0 -0
  1746. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmparser-0.111.0}/LICENSE +0 -0
  1747. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmprinter-0.2.63}/LICENSE +0 -0
  1748. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-10.0.1}/LICENSE +0 -0
  1749. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/README.md +0 -0
  1750. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/code.rs +0 -0
  1751. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/host.rs +0 -0
  1752. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/options.rs +0 -0
  1753. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func/typed.rs +0 -0
  1754. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/func.rs +0 -0
  1755. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/linker.rs +0 -0
  1756. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/storage.rs +0 -0
  1757. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/store.rs +0 -0
  1758. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/types.rs +0 -0
  1759. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/component/values.rs +0 -0
  1760. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/limits.rs +0 -0
  1761. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/module/registry.rs +0 -0
  1762. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/profiling.rs +0 -0
  1763. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/signatures.rs +0 -0
  1764. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/store/data.rs +0 -0
  1765. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/memory.rs +0 -0
  1766. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline/table.rs +0 -0
  1767. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trampoline.rs +0 -0
  1768. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/trap.rs +0 -0
  1769. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/unix.rs +0 -0
  1770. /data/ext/cargo-vendor/{wasmtime-9.0.4 → wasmtime-10.0.1}/src/windows.rs +0 -0
  1771. /data/ext/cargo-vendor/{wasmtime-asm-macros-9.0.4 → wasmtime-asm-macros-10.0.1}/src/lib.rs +0 -0
  1772. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-cache-10.0.1}/LICENSE +0 -0
  1773. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/build.rs +0 -0
  1774. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config/tests.rs +0 -0
  1775. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/config.rs +0 -0
  1776. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/lib.rs +0 -0
  1777. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/tests.rs +0 -0
  1778. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests/system_time_stub.rs +0 -0
  1779. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker/tests.rs +0 -0
  1780. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/src/worker.rs +0 -0
  1781. /data/ext/cargo-vendor/{wasmtime-cache-9.0.4 → wasmtime-cache-10.0.1}/tests/cache_write_default_config.rs +0 -0
  1782. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/component.rs +0 -0
  1783. /data/ext/cargo-vendor/{wasmtime-component-macro-9.0.4 → wasmtime-component-macro-10.0.1}/src/lib.rs +0 -0
  1784. /data/ext/cargo-vendor/{wasmtime-component-util-9.0.4 → wasmtime-component-util-10.0.1}/src/lib.rs +0 -0
  1785. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-cranelift-10.0.1}/LICENSE +0 -0
  1786. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/SECURITY.md +0 -0
  1787. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/builder.rs +0 -0
  1788. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/compiler/component.rs +0 -0
  1789. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/gc.rs +0 -0
  1790. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/address_transform.rs +0 -0
  1791. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/attr.rs +0 -0
  1792. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/expression.rs +0 -0
  1793. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/line_program.rs +0 -0
  1794. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/mod.rs +0 -0
  1795. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/range_info_builder.rs +0 -0
  1796. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/refs.rs +0 -0
  1797. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/unit.rs +0 -0
  1798. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/transform/utils.rs +0 -0
  1799. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug/write_debuginfo.rs +0 -0
  1800. /data/ext/cargo-vendor/{wasmtime-cranelift-9.0.4 → wasmtime-cranelift-10.0.1}/src/debug.rs +0 -0
  1801. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/compiled_function.rs +0 -0
  1802. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/isa_builder.rs +0 -0
  1803. /data/ext/cargo-vendor/{wasmtime-cranelift-shared-9.0.4 → wasmtime-cranelift-shared-10.0.1}/src/obj.rs +0 -0
  1804. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-environ-10.0.1}/LICENSE +0 -0
  1805. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/examples/factc.rs +0 -0
  1806. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/address_map.rs +0 -0
  1807. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/builtin.rs +0 -0
  1808. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/compilation.rs +0 -0
  1809. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/dfg.rs +0 -0
  1810. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/info.rs +0 -0
  1811. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/translate/adapt.rs +0 -0
  1812. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component/vmcomponent_offsets.rs +0 -0
  1813. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/component.rs +0 -0
  1814. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/core_types.rs +0 -0
  1815. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/signature.rs +0 -0
  1816. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/trampoline.rs +0 -0
  1817. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/transcode.rs +0 -0
  1818. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/fact/traps.rs +0 -0
  1819. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/lib.rs +0 -0
  1820. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/module_types.rs +0 -0
  1821. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/obj.rs +0 -0
  1822. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/ref_bits.rs +0 -0
  1823. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/scopevec.rs +0 -0
  1824. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/stack_map.rs +0 -0
  1825. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/tunables.rs +0 -0
  1826. /data/ext/cargo-vendor/{wasmtime-environ-9.0.4 → wasmtime-environ-10.0.1}/src/vmoffsets.rs +0 -0
  1827. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-fiber-10.0.1}/LICENSE +0 -0
  1828. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/build.rs +0 -0
  1829. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/aarch64.rs +0 -0
  1830. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/arm.rs +0 -0
  1831. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/riscv64.rs +0 -0
  1832. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/s390x.S +0 -0
  1833. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86.rs +0 -0
  1834. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/unix/x86_64.rs +0 -0
  1835. /data/ext/cargo-vendor/{wasmtime-fiber-9.0.4 → wasmtime-fiber-10.0.1}/src/windows.c +0 -0
  1836. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-jit-10.0.1}/LICENSE +0 -0
  1837. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/code_memory.rs +0 -0
  1838. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/debug.rs +0 -0
  1839. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/demangling.rs +0 -0
  1840. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/miri.rs +0 -0
  1841. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/systemv.rs +0 -0
  1842. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind/winx64.rs +0 -0
  1843. /data/ext/cargo-vendor/{wasmtime-jit-9.0.4 → wasmtime-jit-10.0.1}/src/unwind.rs +0 -0
  1844. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/README.md +0 -0
  1845. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/gdb_jit_int.rs +0 -0
  1846. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/lib.rs +0 -0
  1847. /data/ext/cargo-vendor/{wasmtime-jit-debug-9.0.4 → wasmtime-jit-debug-10.0.1}/src/perf_jitdump.rs +0 -0
  1848. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/lib.rs +0 -0
  1849. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/libc.rs +0 -0
  1850. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/miri.rs +0 -0
  1851. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-9.0.4 → wasmtime-jit-icache-coherence-10.0.1}/src/win.rs +0 -0
  1852. /data/ext/cargo-vendor/{wiggle-9.0.4 → wasmtime-runtime-10.0.1}/LICENSE +0 -0
  1853. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/build.rs +0 -0
  1854. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/component/transcode.rs +0 -0
  1855. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/export.rs +0 -0
  1856. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/helpers.c +0 -0
  1857. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/imports.rs +0 -0
  1858. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1859. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/unix.rs +0 -0
  1860. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/instance/allocator/pooling/windows.rs +0 -0
  1861. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap.rs +0 -0
  1862. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/mmap_vec.rs +0 -0
  1863. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/module_id.rs +0 -0
  1864. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/parking_spot.rs +0 -0
  1865. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/store_box.rs +0 -0
  1866. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/aarch64.rs +0 -0
  1867. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/riscv64.rs +0 -0
  1868. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.S +0 -0
  1869. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/s390x.rs +0 -0
  1870. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines/x86_64.rs +0 -0
  1871. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/trampolines.rs +0 -0
  1872. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/aarch64.rs +0 -0
  1873. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/riscv64.rs +0 -0
  1874. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/s390x.rs +0 -0
  1875. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace/x86_64.rs +0 -0
  1876. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/backtrace.rs +0 -0
  1877. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/macos.rs +0 -0
  1878. /data/ext/cargo-vendor/{wasmtime-runtime-9.0.4 → wasmtime-runtime-10.0.1}/src/traphandlers/windows.rs +0 -0
  1879. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wasmtime-types-10.0.1}/LICENSE +0 -0
  1880. /data/ext/cargo-vendor/{wasmtime-types-9.0.4 → wasmtime-types-10.0.1}/src/error.rs +0 -0
  1881. /data/ext/cargo-vendor/{wiggle-macro-9.0.4 → wasmtime-wasi-10.0.1}/LICENSE +0 -0
  1882. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/README.md +0 -0
  1883. /data/ext/cargo-vendor/{wasmtime-wasi-9.0.4 → wasmtime-wasi-10.0.1}/build.rs +0 -0
  1884. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/LICENSE +0 -0
  1885. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/builder.rs +0 -0
  1886. /data/ext/cargo-vendor/{wasmtime-winch-9.0.4 → wasmtime-winch-10.0.1}/src/lib.rs +0 -0
  1887. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/rust.rs +0 -0
  1888. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-9.0.4 → wasmtime-wit-bindgen-10.0.1}/src/source.rs +0 -0
  1889. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/borrow.rs +0 -0
  1890. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/error.rs +0 -0
  1891. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/guest_type.rs +0 -0
  1892. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/lib.rs +0 -0
  1893. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/region.rs +0 -0
  1894. /data/ext/cargo-vendor/{wiggle-9.0.4 → wiggle-10.0.1}/src/wasmtime.rs +0 -0
  1895. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/README.md +0 -0
  1896. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/codegen_settings.rs +0 -0
  1897. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/config.rs +0 -0
  1898. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/funcs.rs +0 -0
  1899. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lib.rs +0 -0
  1900. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/lifetimes.rs +0 -0
  1901. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/module_trait.rs +0 -0
  1902. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/names.rs +0 -0
  1903. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/error.rs +0 -0
  1904. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/flags.rs +0 -0
  1905. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/handle.rs +0 -0
  1906. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/mod.rs +0 -0
  1907. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/record.rs +0 -0
  1908. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/types/variant.rs +0 -0
  1909. /data/ext/cargo-vendor/{wiggle-generate-9.0.4 → wiggle-generate-10.0.1}/src/wasmtime.rs +0 -0
  1910. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/LICENSE +0 -0
  1911. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/build.rs +0 -0
  1912. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/aarch64/address.rs +0 -0
  1913. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/isa/reg.rs +0 -0
  1914. /data/ext/cargo-vendor/{winch-codegen-0.7.4 → winch-codegen-0.8.1}/src/regset.rs +0 -0
  1915. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/README.md +0 -0
  1916. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/abi.rs +0 -0
  1917. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/ast/toposort.rs +0 -0
  1918. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/src/sizealign.rs +0 -0
  1919. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/alias-no-type.wit +0 -0
  1920. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async.wit.result +0 -0
  1921. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/async1.wit.result +0 -0
  1922. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit +0 -0
  1923. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/bad-list.wit.result +0 -0
  1924. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit +0 -0
  1925. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/dangling-type.wit.result +0 -0
  1926. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-md.md +0 -0
  1927. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit +0 -0
  1928. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/invalid-toplevel.wit.result +0 -0
  1929. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit +0 -0
  1930. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/keyword.wit.result +0 -0
  1931. /data/ext/cargo-vendor/{wit-parser-0.7.1/tests/ui/empty.wit → wit-parser-0.8.0/tests/ui/parse-fail/missing-package.wit} +0 -0
  1932. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unresolved-use10/foo.wit +0 -0
  1933. /data/ext/cargo-vendor/{wit-parser-0.7.1 → wit-parser-0.8.0}/tests/ui/parse-fail/unterminated-string.wit.result +0 -0
@@ -1,2906 +0,0 @@
1
- ;; aarch64 instruction selection and CLIF-to-MachInst lowering.
2
-
3
- ;; The main lowering constructor term: takes a clif `Inst` and returns the
4
- ;; register(s) within which the lowered instruction's result values live.
5
- (decl partial lower (Inst) InstOutput)
6
-
7
- ;; Variant of the main lowering constructor term, which receives an
8
- ;; additional argument (a vector of branch targets to be used) for
9
- ;; implementing branches.
10
- ;; For two-branch instructions, the first target is `taken` and the second
11
- ;; `not_taken`, even if it is a Fallthrough instruction: because we reorder
12
- ;; blocks while we lower, the fallthrough in the new order is not (necessarily)
13
- ;; the same as the fallthrough in CLIF. So, we use the explicitly-provided
14
- ;; target.
15
- (decl partial lower_branch (Inst VecMachLabel) Unit)
16
-
17
- ;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18
-
19
- (rule (lower (has_type ty (iconst (u64_from_imm64 n))))
20
- (imm ty (ImmExtend.Zero) n))
21
-
22
- ;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
23
-
24
- (rule (lower (has_type ty (null)))
25
- (imm ty (ImmExtend.Zero) 0))
26
-
27
- ;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
28
-
29
- (rule (lower (f32const (u32_from_ieee32 n)))
30
- (constant_f32 n))
31
-
32
- ;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
33
-
34
- (rule (lower (f64const (u64_from_ieee64 n)))
35
- (constant_f64 n))
36
-
37
- ;;;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
38
-
39
- (rule (lower (nop))
40
- (invalid_reg))
41
-
42
- ;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
43
-
44
- ;; `i64` and smaller
45
-
46
- ;; Base case, simply adding things in registers.
47
- (rule -1 (lower (has_type (fits_in_64 ty) (iadd x y)))
48
- (add ty x y))
49
-
50
- ;; Special cases for when one operand is an immediate that fits in 12 bits.
51
- (rule 4 (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
52
- (add_imm ty x y))
53
-
54
- (rule 5 (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
55
- (add_imm ty y x))
56
-
57
- ;; Same as the previous special cases, except we can switch the addition to a
58
- ;; subtraction if the negated immediate fits in 12 bits.
59
- (rule 2 (lower (has_type (fits_in_64 ty) (iadd x y)))
60
- (if-let imm12_neg (imm12_from_negated_value y))
61
- (sub_imm ty x imm12_neg))
62
-
63
- (rule 3 (lower (has_type (fits_in_64 ty) (iadd x y)))
64
- (if-let imm12_neg (imm12_from_negated_value x))
65
- (sub_imm ty y imm12_neg))
66
-
67
- ;; Special cases for when we're adding an extended register where the extending
68
- ;; operation can get folded into the add itself.
69
- (rule 0 (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
70
- (add_extend ty x y))
71
-
72
- (rule 1 (lower (has_type (fits_in_64 ty) (iadd (extended_value_from_value x) y)))
73
- (add_extend ty y x))
74
-
75
- ;; Special cases for when we're adding the shift of a different
76
- ;; register by a constant amount and the shift can get folded into the add.
77
- (rule 7 (lower (has_type (fits_in_64 ty)
78
- (iadd x (ishl y (iconst k)))))
79
- (if-let amt (lshl_from_imm64 ty k))
80
- (add_shift ty x y amt))
81
-
82
- (rule 6 (lower (has_type (fits_in_64 ty)
83
- (iadd (ishl x (iconst k)) y)))
84
- (if-let amt (lshl_from_imm64 ty k))
85
- (add_shift ty y x amt))
86
-
87
- ;; Fold an `iadd` and `imul` combination into a `madd` instruction.
88
- (rule 7 (lower (has_type (fits_in_64 ty) (iadd x (imul y z))))
89
- (madd ty y z x))
90
-
91
- (rule 6 (lower (has_type (fits_in_64 ty) (iadd (imul x y) z)))
92
- (madd ty x y z))
93
-
94
- ;; Fold an `isub` and `imul` combination into a `msub` instruction.
95
- (rule (lower (has_type (fits_in_64 ty) (isub x (imul y z))))
96
- (msub ty y z x))
97
-
98
- ;; vectors
99
-
100
- (rule -2 (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
101
- (add_vec x y (vector_size ty)))
102
-
103
- ;; `i128`
104
- (rule -3 (lower (has_type $I128 (iadd x y)))
105
- (let
106
- ;; Get the high/low registers for `x`.
107
- ((x_regs ValueRegs x)
108
- (x_lo Reg (value_regs_get x_regs 0))
109
- (x_hi Reg (value_regs_get x_regs 1))
110
-
111
- ;; Get the high/low registers for `y`.
112
- (y_regs ValueRegs y)
113
- (y_lo Reg (value_regs_get y_regs 0))
114
- (y_hi Reg (value_regs_get y_regs 1)))
115
- ;; the actual addition is `adds` followed by `adc` which comprises the
116
- ;; low/high bits of the result
117
- (with_flags
118
- (add_with_flags_paired $I64 x_lo y_lo)
119
- (adc_paired $I64 x_hi y_hi))))
120
-
121
- ;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
122
-
123
- ;; When a single element of one vector is broadcast to all the destination
124
- ;; lanes then the `dup` instruction can be used for this operation. Note that
125
- ;; for now this only matches lane selection from the first vector `a`, but
126
- ;; if necessary in the future rules can be added to select from `b` as well.
127
- (rule 6 (lower (shuffle a b (shuffle_dup8_from_imm n)))
128
- (vec_dup_from_fpu a (VectorSize.Size8x16) n))
129
- (rule 5 (lower (shuffle a b (shuffle_dup16_from_imm n)))
130
- (vec_dup_from_fpu a (VectorSize.Size16x8) n))
131
- (rule 4 (lower (shuffle a b (shuffle_dup32_from_imm n)))
132
- (vec_dup_from_fpu a (VectorSize.Size32x4) n))
133
- (rule 3 (lower (shuffle a b (shuffle_dup64_from_imm n)))
134
- (vec_dup_from_fpu a (VectorSize.Size64x2) n))
135
-
136
- ;; If the `Immediate` specified to the extractor looks like a duplication of the
137
- ;; `n`th lane of the first vector of size K-byte lanes, then each extractor
138
- ;; returns the `n` value as a `u8` to be used as part of a `vec_dup_from_fpu`
139
- ;; instruction. Note that there's a different extractor for each bit-width of
140
- ;; lane.
141
- (decl shuffle_dup8_from_imm (u8) Immediate)
142
- (extern extractor shuffle_dup8_from_imm shuffle_dup8_from_imm)
143
- (decl shuffle_dup16_from_imm (u8) Immediate)
144
- (extern extractor shuffle_dup16_from_imm shuffle_dup16_from_imm)
145
- (decl shuffle_dup32_from_imm (u8) Immediate)
146
- (extern extractor shuffle_dup32_from_imm shuffle_dup32_from_imm)
147
- (decl shuffle_dup64_from_imm (u8) Immediate)
148
- (extern extractor shuffle_dup64_from_imm shuffle_dup64_from_imm)
149
-
150
- ;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
151
- ;; bytes", that's an `ext` instruction.
152
- (rule 2 (lower (shuffle a b (vec_extract_imm4_from_immediate n)))
153
- (vec_extract a b n))
154
-
155
- ;; Attempts to extract `n` from the specified shuffle `Immediate` where each
156
- ;; byte of the `Immediate` is a consecutive sequence starting from `n`. This
157
- ;; value of `n` is used as part of the `vec_extract` instruction which extracts
158
- ;; consecutive bytes from two vectors into one final vector, offset by `n`
159
- ;; bytes.
160
- (decl vec_extract_imm4_from_immediate (u8) Immediate)
161
- (extern extractor vec_extract_imm4_from_immediate vec_extract_imm4_from_immediate)
162
-
163
- ;; Rules for the `uzp1` and `uzp2` instructions which gather even-numbered lanes
164
- ;; or odd-numbered lanes
165
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1e1c_1a18_1614_1210_0e0c_0a08_0604_0200)))
166
- (vec_uzp1 a b (VectorSize.Size8x16)))
167
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1d_1b19_1715_1311_0f0d_0b09_0705_0301)))
168
- (vec_uzp2 a b (VectorSize.Size8x16)))
169
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1d1c_1918_1514_1110_0d0c_0908_0504_0100)))
170
- (vec_uzp1 a b (VectorSize.Size16x8)))
171
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_1b1a_1716_1312_0f0e_0b0a_0706_0302)))
172
- (vec_uzp2 a b (VectorSize.Size16x8)))
173
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1b1a1918_13121110_0b0a0908_03020100)))
174
- (vec_uzp1 a b (VectorSize.Size32x4)))
175
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_17161514_0f0e0d0c_07060504)))
176
- (vec_uzp2 a b (VectorSize.Size32x4)))
177
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1716151413121110_0706050403020100)))
178
- (vec_uzp1 a b (VectorSize.Size64x2)))
179
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c1b1a1918_0f0e0d0c0b0a0908)))
180
- (vec_uzp2 a b (VectorSize.Size64x2)))
181
-
182
- ;; Rules for the `zip1` and `zip2` instructions which interleave lanes in the
183
- ;; low or high halves of the two input vectors.
184
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1707_1606_1505_1404_1303_1202_1101_1000)))
185
- (vec_zip1 a b (VectorSize.Size8x16)))
186
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f0f_1e0e_1d0d_1c0c_1b0b_1a0a_1909_1808)))
187
- (vec_zip2 a b (VectorSize.Size8x16)))
188
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1716_0706_1514_0504_1312_0302_1110_0100)))
189
- (vec_zip1 a b (VectorSize.Size16x8)))
190
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1d1c_0d0c_1b1a_0b0a_1918_0908)))
191
- (vec_zip2 a b (VectorSize.Size16x8)))
192
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x17161514_07060504_13121110_03020100)))
193
- (vec_zip1 a b (VectorSize.Size32x4)))
194
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_1b1a1918_0b0a0908)))
195
- (vec_zip2 a b (VectorSize.Size32x4)))
196
- ;; Note that zip1/zip2 for i64x2 vectors is omitted since it's already covered
197
- ;; by the i64x2 cases of uzp1/uzp2 above where both zip and uzp have the same
198
- ;; semantics for 64-bit lanes.
199
-
200
- ;; Rules for the `trn1` and `trn2` instructions which interleave odd or even
201
- ;; lanes in the two input vectors.
202
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1e0e_1c0c_1a0a_1808_1606_1404_1202_1000)))
203
- (vec_trn1 a b (VectorSize.Size8x16)))
204
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f0f_1d0d_1b0b_1909_1707_1505_1303_1101)))
205
- (vec_trn2 a b (VectorSize.Size8x16)))
206
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1d1c_0d0c_1918_0908_1514_0504_1110_0100)))
207
- (vec_trn1 a b (VectorSize.Size16x8)))
208
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e_0f0e_1b1a_0b0a_1716_0706_1312_0302)))
209
- (vec_trn2 a b (VectorSize.Size16x8)))
210
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1b1a1918_0b0a0908_13121110_03020100)))
211
- (vec_trn1 a b (VectorSize.Size32x4)))
212
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x1f1e1d1c_0f0e0d0c_17161514_07060504)))
213
- (vec_trn2 a b (VectorSize.Size32x4)))
214
- ;; Note that trn1/trn2 for i64x2 vectors is omitted since it's already covered
215
- ;; by the i64x2 cases of uzp1/uzp2 above where both trn and uzp have the same
216
- ;; semantics for 64-bit lanes.
217
-
218
- ;; Rules for the `rev{16,32,64}` instructions where reversals happen at either
219
- ;; the byte level, the 16-bit level, or 32-bit level. Note that all of these
220
- ;; patterns only match reversals in the first operand, but they can
221
- ;; theoretically be extended if necessary to reversals in the second operand.
222
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x0e0f_0c0d_0a0b_0809_0607_0405_0203_0001)))
223
- (rev16 a (VectorSize.Size8x16)))
224
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x0c0d0e0f_08090a0b_04050607_00010203)))
225
- (rev32 a (VectorSize.Size8x16)))
226
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x0d0c0f0e_09080b0a_05040706_01000302)))
227
- (rev32 a (VectorSize.Size16x8)))
228
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x08090a0b0c0d0e0f_0001020304050607)))
229
- (rev64 a (VectorSize.Size8x16)))
230
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x09080b0a0d0c0f0e_0100030205040706)))
231
- (rev64 a (VectorSize.Size16x8)))
232
- (rule 1 (lower (shuffle a b (u128_from_immediate 0x0b0a09080f0e0d0c_0302010007060504)))
233
- (rev64 a (VectorSize.Size32x4)))
234
-
235
- (rule (lower (has_type ty (shuffle rn rn2 (u128_from_immediate mask))))
236
- (let ((mask_reg Reg (constant_f128 mask)))
237
- (vec_tbl2 rn rn2 mask_reg ty)))
238
-
239
- ;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
240
-
241
- (rule (lower (has_type vec_i128_ty (swizzle rn rm)))
242
- (vec_tbl rn rm))
243
-
244
- ;;;; Rules for `isplit` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
245
-
246
- (rule (lower (isplit x @ (value_type $I128)))
247
- (let
248
- ((x_regs ValueRegs x)
249
- (x_lo ValueRegs (value_regs_get x_regs 0))
250
- (x_hi ValueRegs (value_regs_get x_regs 1)))
251
- (output_pair x_lo x_hi)))
252
-
253
- ;;;; Rules for `iconcat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
254
-
255
- (rule (lower (has_type $I128 (iconcat lo hi)))
256
- (output (value_regs lo hi)))
257
-
258
- ;;;; Rules for `scalar_to_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
259
-
260
- (rule (lower (has_type $F32X4 (scalar_to_vector x)))
261
- (fpu_extend x (ScalarSize.Size32)))
262
-
263
- (rule (lower (has_type $F64X2 (scalar_to_vector x)))
264
- (fpu_extend x (ScalarSize.Size64)))
265
-
266
- (rule -1 (lower (scalar_to_vector x @ (value_type $I64)))
267
- (mov_to_fpu x (ScalarSize.Size64)))
268
-
269
- (rule -2 (lower (scalar_to_vector x @ (value_type (int_fits_in_32 _))))
270
- (mov_to_fpu (put_in_reg_zext32 x) (ScalarSize.Size32)))
271
-
272
- ;;;; Rules for `vall_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
273
-
274
- ;; cmeq vtmp.2d, vm.2d, #0
275
- ;; addp dtmp, vtmp.2d
276
- ;; fcmp dtmp, dtmp
277
- ;; cset xd, eq
278
- ;;
279
- ;; Note that after the ADDP the value of the temporary register will be either
280
- ;; 0 when all input elements are true, i.e. non-zero, or a NaN otherwise
281
- ;; (either -1 or -2 when represented as an integer); NaNs are the only
282
- ;; floating-point numbers that compare unequal to themselves.
283
- (rule (lower (vall_true x @ (value_type (multi_lane 64 2))))
284
- (let ((x1 Reg (cmeq0 x (VectorSize.Size64x2)))
285
- (x2 Reg (addp x1 x1 (VectorSize.Size64x2))))
286
- (with_flags (fpu_cmp (ScalarSize.Size64) x2 x2)
287
- (materialize_bool_result (Cond.Eq)))))
288
-
289
- (rule (lower (vall_true x @ (value_type (multi_lane 32 2))))
290
- (let ((x1 Reg (mov_from_vec x 0 (ScalarSize.Size64))))
291
- (with_flags (cmp_rr_shift (OperandSize.Size64) (zero_reg) x1 32)
292
- (ccmp_imm
293
- (OperandSize.Size32)
294
- x1
295
- (u8_into_uimm5 0)
296
- (nzcv $false $true $false $false)
297
- (Cond.Ne)))))
298
-
299
- ;; This operation is implemented by using uminv to create a scalar value, which
300
- ;; is then compared against zero.
301
- ;;
302
- ;; uminv bn, vm.16b
303
- ;; mov xm, vn.d[0]
304
- ;; cmp xm, #0
305
- ;; cset xm, ne
306
- (rule -1 (lower (vall_true x @ (value_type (lane_fits_in_32 ty))))
307
- (if (not_vec32x2 ty))
308
- (let ((x1 Reg (vec_lanes (VecLanesOp.Uminv) x (vector_size ty)))
309
- (x2 Reg (mov_from_vec x1 0 (ScalarSize.Size64))))
310
- (with_flags (cmp_imm (OperandSize.Size64) x2 (u8_into_imm12 0))
311
- (materialize_bool_result (Cond.Ne)))))
312
-
313
- ;;;; Rules for `vany_true` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
314
-
315
- (rule (lower (vany_true x @ (value_type in_ty)))
316
- (with_flags (vanytrue x in_ty)
317
- (materialize_bool_result (Cond.Ne))))
318
-
319
- ;;;; Rules for `iadd_pairwise` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
320
-
321
- ;; special case for the `i16x8.extadd_pairwise_i8x16_s` wasm instruction
322
- (rule (lower (has_type $I16X8 (iadd_pairwise (swiden_low x) (swiden_high x))))
323
- (saddlp8 x))
324
-
325
- ;; special case for the `i32x4.extadd_pairwise_i16x8_s` wasm instruction
326
- (rule (lower (has_type $I32X4 (iadd_pairwise (swiden_low x) (swiden_high x))))
327
- (saddlp16 x))
328
-
329
- ;; special case for the `i16x8.extadd_pairwise_i8x16_u` wasm instruction
330
- (rule (lower (has_type $I16X8 (iadd_pairwise (uwiden_low x) (uwiden_high x))))
331
- (uaddlp8 x))
332
-
333
- ;; special case for the `i32x4.extadd_pairwise_i16x8_u` wasm instruction
334
- (rule (lower (has_type $I32X4 (iadd_pairwise (uwiden_low x) (uwiden_high x))))
335
- (uaddlp16 x))
336
-
337
- (rule -1 (lower (has_type ty (iadd_pairwise x y)))
338
- (addp x y (vector_size ty)))
339
-
340
- ;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
341
-
342
- (rule (lower (has_type ty @ (multi_lane _ _) (iabs x)))
343
- (vec_abs x (vector_size ty)))
344
-
345
- (rule 2 (lower (has_type $I64 (iabs x)))
346
- (abs (OperandSize.Size64) x))
347
-
348
- (rule 1 (lower (has_type (fits_in_32 ty) (iabs x)))
349
- (abs (OperandSize.Size32) (put_in_reg_sext32 x)))
350
-
351
- ;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
352
-
353
- (rule (lower (has_type $I64X2 (avg_round x y)))
354
- (let ((one Reg (splat_const 1 (VectorSize.Size64x2)))
355
- (c Reg (orr_vec x y (VectorSize.Size64x2)))
356
- (c Reg (and_vec c one (VectorSize.Size64x2)))
357
- (x Reg (ushr_vec_imm x 1 (VectorSize.Size64x2)))
358
- (y Reg (ushr_vec_imm y 1 (VectorSize.Size64x2)))
359
- (sum Reg (add_vec x y (VectorSize.Size64x2))))
360
- (add_vec c sum (VectorSize.Size64x2))))
361
-
362
- (rule -1 (lower (has_type (lane_fits_in_32 ty) (avg_round x y)))
363
- (vec_rrr (VecALUOp.Urhadd) x y (vector_size ty)))
364
-
365
- ;;;; Rules for `sqmul_round_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
366
-
367
- (rule (lower (has_type ty @ (multi_lane _ _) (sqmul_round_sat x y)))
368
- (vec_rrr (VecALUOp.Sqrdmulh) x y (vector_size ty)))
369
-
370
- ;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
371
-
372
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fadd rn rm)))
373
- (vec_rrr (VecALUOp.Fadd) rn rm (vector_size ty)))
374
-
375
- (rule (lower (has_type (ty_scalar_float ty) (fadd rn rm)))
376
- (fpu_rrr (FPUOp2.Add) rn rm (scalar_size ty)))
377
-
378
- ;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
379
-
380
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fsub rn rm)))
381
- (vec_rrr (VecALUOp.Fsub) rn rm (vector_size ty)))
382
-
383
- (rule (lower (has_type (ty_scalar_float ty) (fsub rn rm)))
384
- (fpu_rrr (FPUOp2.Sub) rn rm (scalar_size ty)))
385
-
386
- ;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
387
-
388
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fmul rn rm)))
389
- (vec_rrr (VecALUOp.Fmul) rn rm (vector_size ty)))
390
-
391
- (rule (lower (has_type (ty_scalar_float ty) (fmul rn rm)))
392
- (fpu_rrr (FPUOp2.Mul) rn rm (scalar_size ty)))
393
-
394
- ;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
395
-
396
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fdiv rn rm)))
397
- (vec_rrr (VecALUOp.Fdiv) rn rm (vector_size ty)))
398
-
399
- (rule (lower (has_type (ty_scalar_float ty) (fdiv rn rm)))
400
- (fpu_rrr (FPUOp2.Div) rn rm (scalar_size ty)))
401
-
402
- ;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
403
-
404
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fmin rn rm)))
405
- (vec_rrr (VecALUOp.Fmin) rn rm (vector_size ty)))
406
-
407
- (rule (lower (has_type (ty_scalar_float ty) (fmin rn rm)))
408
- (fpu_rrr (FPUOp2.Min) rn rm (scalar_size ty)))
409
-
410
- ;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
411
-
412
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fmax rn rm)))
413
- (vec_rrr (VecALUOp.Fmax) rn rm (vector_size ty)))
414
-
415
- (rule (lower (has_type (ty_scalar_float ty) (fmax rn rm)))
416
- (fpu_rrr (FPUOp2.Max) rn rm (scalar_size ty)))
417
-
418
- ;;;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
419
-
420
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fmin_pseudo rm rn)))
421
- (bsl ty (vec_rrr (VecALUOp.Fcmgt) rm rn (vector_size ty)) rn rm))
422
-
423
- (rule (lower (has_type (ty_scalar_float ty) (fmin_pseudo rm rn)))
424
- (with_flags (fpu_cmp (scalar_size ty) rm rn)
425
- (fpu_csel ty (Cond.Gt) rn rm)))
426
-
427
- ;;;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
428
-
429
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fmax_pseudo rm rn)))
430
- (bsl ty (vec_rrr (VecALUOp.Fcmgt) rn rm (vector_size ty)) rn rm))
431
-
432
- (rule (lower (has_type (ty_scalar_float ty) (fmax_pseudo rm rn)))
433
- (with_flags (fpu_cmp (scalar_size ty) rn rm)
434
- (fpu_csel ty (Cond.Gt) rn rm)))
435
-
436
- ;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
437
-
438
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (sqrt x)))
439
- (vec_misc (VecMisc2.Fsqrt) x (vector_size ty)))
440
-
441
- (rule (lower (has_type (ty_scalar_float ty) (sqrt x)))
442
- (fpu_rr (FPUOp1.Sqrt) x (scalar_size ty)))
443
-
444
- ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
445
-
446
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fneg x)))
447
- (vec_misc (VecMisc2.Fneg) x (vector_size ty)))
448
-
449
- (rule (lower (has_type (ty_scalar_float ty) (fneg x)))
450
- (fpu_rr (FPUOp1.Neg) x (scalar_size ty)))
451
-
452
- ;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
453
-
454
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (fabs x)))
455
- (vec_misc (VecMisc2.Fabs) x (vector_size ty)))
456
-
457
- (rule (lower (has_type (ty_scalar_float ty) (fabs x)))
458
- (fpu_rr (FPUOp1.Abs) x (scalar_size ty)))
459
-
460
- ;;;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
461
-
462
- (rule (lower (has_type $F64 (fpromote x)))
463
- (fpu_rr (FPUOp1.Cvt32To64) x (ScalarSize.Size32)))
464
-
465
- ;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
466
-
467
- (rule (lower (has_type $F32 (fdemote x)))
468
- (fpu_rr (FPUOp1.Cvt64To32) x (ScalarSize.Size64)))
469
-
470
- ;;;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
471
-
472
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (ceil x)))
473
- (vec_misc (VecMisc2.Frintp) x (vector_size ty)))
474
-
475
- (rule (lower (has_type $F32 (ceil x)))
476
- (fpu_round (FpuRoundMode.Plus32) x))
477
-
478
- (rule (lower (has_type $F64 (ceil x)))
479
- (fpu_round (FpuRoundMode.Plus64) x))
480
-
481
- ;;;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
482
-
483
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (floor x)))
484
- (vec_misc (VecMisc2.Frintm) x (vector_size ty)))
485
-
486
- (rule (lower (has_type $F32 (floor x)))
487
- (fpu_round (FpuRoundMode.Minus32) x))
488
-
489
- (rule (lower (has_type $F64 (floor x)))
490
- (fpu_round (FpuRoundMode.Minus64) x))
491
-
492
- ;;;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
493
-
494
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (trunc x)))
495
- (vec_misc (VecMisc2.Frintz) x (vector_size ty)))
496
-
497
- (rule (lower (has_type $F32 (trunc x)))
498
- (fpu_round (FpuRoundMode.Zero32) x))
499
-
500
- (rule (lower (has_type $F64 (trunc x)))
501
- (fpu_round (FpuRoundMode.Zero64) x))
502
-
503
- ;;;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
504
-
505
- (rule -1 (lower (has_type ty @ (multi_lane _ _) (nearest x)))
506
- (vec_misc (VecMisc2.Frintn) x (vector_size ty)))
507
-
508
- (rule (lower (has_type $F32 (nearest x)))
509
- (fpu_round (FpuRoundMode.Nearest32) x))
510
-
511
- (rule (lower (has_type $F64 (nearest x)))
512
- (fpu_round (FpuRoundMode.Nearest64) x))
513
-
514
- ;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
515
-
516
- (rule (lower (has_type (ty_scalar_float ty) (fma x y z)))
517
- (fpu_rrrr (FPUOp3.MAdd) (scalar_size ty) x y z))
518
-
519
- ;; Delegate vector-based lowerings to helpers below
520
- (rule 1 (lower (has_type ty @ (multi_lane _ _) (fma x y z)))
521
- (lower_fmla (VecALUModOp.Fmla) x y z (vector_size ty)))
522
-
523
- ;; Lowers a fused-multiply-add operation handling various forms of the
524
- ;; instruction to get maximal coverage of what's available on AArch64.
525
- (decl lower_fmla (VecALUModOp Value Value Value VectorSize) Reg)
526
-
527
- ;; Base case, emit the op requested.
528
- (rule (lower_fmla op x y z size)
529
- (vec_rrr_mod op z x y size))
530
-
531
- ;; Special case: if one of the multiplicands are a splat then the element-based
532
- ;; fma can be used instead with 0 as the element index.
533
- (rule 1 (lower_fmla op (splat x) y z size)
534
- (vec_fmla_elem op z y x size 0))
535
- (rule 2 (lower_fmla op x (splat y) z size)
536
- (vec_fmla_elem op z x y size 0))
537
-
538
- ;; Special case: if one of the multiplicands is a shuffle to broadcast a
539
- ;; single element of a vector then the element-based fma can be used like splat
540
- ;; above.
541
- ;;
542
- ;; Note that in Cranelift shuffle always has i8x16 inputs and outputs so
543
- ;; a `bitcast` is matched here explicitly since that's the main way a shuffle
544
- ;; output will be fed into this instruction.
545
- (rule 3 (lower_fmla op (bitcast _ (shuffle x x (shuffle32_from_imm n n n n))) y z size @ (VectorSize.Size32x4))
546
- (if-let $true (u64_lt n 4))
547
- (vec_fmla_elem op z y x size n))
548
- (rule 4 (lower_fmla op x (bitcast _ (shuffle y y (shuffle32_from_imm n n n n))) z size @ (VectorSize.Size32x4))
549
- (if-let $true (u64_lt n 4))
550
- (vec_fmla_elem op z x y size n))
551
- (rule 3 (lower_fmla op (bitcast _ (shuffle x x (shuffle64_from_imm n n))) y z size @ (VectorSize.Size64x2))
552
- (if-let $true (u64_lt n 2))
553
- (vec_fmla_elem op z y x size n))
554
- (rule 4 (lower_fmla op x (bitcast _ (shuffle y y (shuffle64_from_imm n n))) z size @ (VectorSize.Size64x2))
555
- (if-let $true (u64_lt n 2))
556
- (vec_fmla_elem op z x y size n))
557
-
558
- ;; Special case: if one of the multiplicands is `fneg` then peel that away,
559
- ;; reverse the operation being performed, and then recurse on `lower_fmla`
560
- ;; again to generate the actual instruction.
561
- ;;
562
- ;; Note that these are the highest priority cases for `lower_fmla` to peel
563
- ;; away as many `fneg` operations as possible.
564
- (rule 5 (lower_fmla op (fneg x) y z size)
565
- (lower_fmla (neg_fmla op) x y z size))
566
- (rule 6 (lower_fmla op x (fneg y) z size)
567
- (lower_fmla (neg_fmla op) x y z size))
568
-
569
- (decl neg_fmla (VecALUModOp) VecALUModOp)
570
- (rule (neg_fmla (VecALUModOp.Fmla)) (VecALUModOp.Fmls))
571
- (rule (neg_fmla (VecALUModOp.Fmls)) (VecALUModOp.Fmla))
572
-
573
- ;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
574
-
575
- (rule (lower (has_type ty (fcopysign x y)))
576
- (fcopy_sign x y ty))
577
-
578
- ;;;; Rules for `fcvt_to_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
579
-
580
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint x @ (value_type $F32))))
581
- (fpu_to_int_cvt (FpuToIntOp.F32ToU32) x $false $F32 out_ty))
582
-
583
- (rule 1 (lower (has_type $I64 (fcvt_to_uint x @ (value_type $F32))))
584
- (fpu_to_int_cvt (FpuToIntOp.F32ToU64) x $false $F32 $I64))
585
-
586
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint x @ (value_type $F64))))
587
- (fpu_to_int_cvt (FpuToIntOp.F64ToU32) x $false $F64 out_ty))
588
-
589
- (rule 1 (lower (has_type $I64 (fcvt_to_uint x @ (value_type $F64))))
590
- (fpu_to_int_cvt (FpuToIntOp.F64ToU64) x $false $F64 $I64))
591
-
592
- ;;;; Rules for `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
593
-
594
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint x @ (value_type $F32))))
595
- (fpu_to_int_cvt (FpuToIntOp.F32ToI32) x $true $F32 out_ty))
596
-
597
- (rule 1 (lower (has_type $I64 (fcvt_to_sint x @ (value_type $F32))))
598
- (fpu_to_int_cvt (FpuToIntOp.F32ToI64) x $true $F32 $I64))
599
-
600
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint x @ (value_type $F64))))
601
- (fpu_to_int_cvt (FpuToIntOp.F64ToI32) x $true $F64 out_ty))
602
-
603
- (rule 1 (lower (has_type $I64 (fcvt_to_sint x @ (value_type $F64))))
604
- (fpu_to_int_cvt (FpuToIntOp.F64ToI64) x $true $F64 $I64))
605
-
606
- ;;;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
607
-
608
- (rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_from_uint x @ (value_type (multi_lane 32 _)))))
609
- (vec_misc (VecMisc2.Ucvtf) x (vector_size ty)))
610
-
611
- (rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_from_uint x @ (value_type (multi_lane 64 _)))))
612
- (vec_misc (VecMisc2.Ucvtf) x (vector_size ty)))
613
-
614
- (rule (lower (has_type $F32 (fcvt_from_uint x @ (value_type (fits_in_32 _)))))
615
- (int_to_fpu (IntToFpuOp.U32ToF32) (put_in_reg_zext32 x)))
616
-
617
- (rule (lower (has_type $F64 (fcvt_from_uint x @ (value_type (fits_in_32 _)))))
618
- (int_to_fpu (IntToFpuOp.U32ToF64) (put_in_reg_zext32 x)))
619
-
620
- (rule 1 (lower (has_type $F32 (fcvt_from_uint x @ (value_type $I64))))
621
- (int_to_fpu (IntToFpuOp.U64ToF32) x))
622
-
623
- (rule 1 (lower (has_type $F64 (fcvt_from_uint x @ (value_type $I64))))
624
- (int_to_fpu (IntToFpuOp.U64ToF64) x))
625
-
626
- ;;;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
627
-
628
- (rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_from_sint x @ (value_type (multi_lane 32 _)))))
629
- (vec_misc (VecMisc2.Scvtf) x (vector_size ty)))
630
-
631
- (rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_from_sint x @ (value_type (multi_lane 64 _)))))
632
- (vec_misc (VecMisc2.Scvtf) x (vector_size ty)))
633
-
634
- (rule (lower (has_type $F32 (fcvt_from_sint x @ (value_type (fits_in_32 _)))))
635
- (int_to_fpu (IntToFpuOp.I32ToF32) (put_in_reg_sext32 x)))
636
-
637
- (rule (lower (has_type $F64 (fcvt_from_sint x @ (value_type (fits_in_32 _)))))
638
- (int_to_fpu (IntToFpuOp.I32ToF64) (put_in_reg_sext32 x)))
639
-
640
- (rule 1 (lower (has_type $F32 (fcvt_from_sint x @ (value_type $I64))))
641
- (int_to_fpu (IntToFpuOp.I64ToF32) x))
642
-
643
- (rule 1 (lower (has_type $F64 (fcvt_from_sint x @ (value_type $I64))))
644
- (int_to_fpu (IntToFpuOp.I64ToF64) x))
645
-
646
- ;;;; Rules for `fcvt_to_uint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
647
-
648
- (rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_to_uint_sat x @ (value_type (multi_lane 32 _)))))
649
- (vec_misc (VecMisc2.Fcvtzu) x (vector_size ty)))
650
-
651
- (rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_to_uint_sat x @ (value_type (multi_lane 64 _)))))
652
- (vec_misc (VecMisc2.Fcvtzu) x (vector_size ty)))
653
-
654
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint_sat x @ (value_type $F32))))
655
- (fpu_to_int_cvt_sat (FpuToIntOp.F32ToU32) x $false out_ty))
656
-
657
- (rule 1 (lower (has_type $I64 (fcvt_to_uint_sat x @ (value_type $F32))))
658
- (fpu_to_int_cvt_sat (FpuToIntOp.F32ToU64) x $false $I64))
659
-
660
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_uint_sat x @ (value_type $F64))))
661
- (fpu_to_int_cvt_sat (FpuToIntOp.F64ToU32) x $false out_ty))
662
-
663
- (rule 1 (lower (has_type $I64 (fcvt_to_uint_sat x @ (value_type $F64))))
664
- (fpu_to_int_cvt_sat (FpuToIntOp.F64ToU64) x $false $I64))
665
-
666
- ;;;; Rules for `fcvt_to_sint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
667
-
668
- (rule -1 (lower (has_type ty @ (multi_lane 32 _) (fcvt_to_sint_sat x @ (value_type (multi_lane 32 _)))))
669
- (vec_misc (VecMisc2.Fcvtzs) x (vector_size ty)))
670
-
671
- (rule -1 (lower (has_type ty @ (multi_lane 64 _) (fcvt_to_sint_sat x @ (value_type (multi_lane 64 _)))))
672
- (vec_misc (VecMisc2.Fcvtzs) x (vector_size ty)))
673
-
674
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint_sat x @ (value_type $F32))))
675
- (fpu_to_int_cvt_sat (FpuToIntOp.F32ToI32) x $true out_ty))
676
-
677
- (rule 1 (lower (has_type $I64 (fcvt_to_sint_sat x @ (value_type $F32))))
678
- (fpu_to_int_cvt_sat (FpuToIntOp.F32ToI64) x $true $I64))
679
-
680
- (rule (lower (has_type (fits_in_32 out_ty) (fcvt_to_sint_sat x @ (value_type $F64))))
681
- (fpu_to_int_cvt_sat (FpuToIntOp.F64ToI32) x $true out_ty))
682
-
683
- (rule 1 (lower (has_type $I64 (fcvt_to_sint_sat x @ (value_type $F64))))
684
- (fpu_to_int_cvt_sat (FpuToIntOp.F64ToI64) x $true $I64))
685
-
686
- ;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
687
-
688
- ;; `i64` and smaller
689
-
690
- ;; Base case, simply subtracting things in registers.
691
- (rule -4 (lower (has_type (fits_in_64 ty) (isub x y)))
692
- (sub ty x y))
693
-
694
- ;; Special case for when one operand is an immediate that fits in 12 bits.
695
- (rule 0 (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
696
- (sub_imm ty x y))
697
-
698
- ;; Same as the previous special case, except we can switch the subtraction to an
699
- ;; addition if the negated immediate fits in 12 bits.
700
- (rule 2 (lower (has_type (fits_in_64 ty) (isub x y)))
701
- (if-let imm12_neg (imm12_from_negated_value y))
702
- (add_imm ty x imm12_neg))
703
-
704
- ;; Special cases for when we're subtracting an extended register where the
705
- ;; extending operation can get folded into the sub itself.
706
- (rule 1 (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
707
- (sub_extend ty x y))
708
-
709
- ;; Finally a special case for when we're subtracting the shift of a different
710
- ;; register by a constant amount and the shift can get folded into the sub.
711
- (rule -3 (lower (has_type (fits_in_64 ty)
712
- (isub x (ishl y (iconst k)))))
713
- (if-let amt (lshl_from_imm64 ty k))
714
- (sub_shift ty x y amt))
715
-
716
- ;; vectors
717
- (rule -2 (lower (has_type ty @ (multi_lane _ _) (isub x y)))
718
- (sub_vec x y (vector_size ty)))
719
-
720
- ;; `i128`
721
- (rule -1 (lower (has_type $I128 (isub x y)))
722
- (sub_i128 x y))
723
-
724
- ;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
725
-
726
- (rule (lower (has_type (ty_vec128 ty) (uadd_sat x y)))
727
- (uqadd x y (vector_size ty)))
728
-
729
- ;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
730
-
731
- (rule (lower (has_type (ty_vec128 ty) (sadd_sat x y)))
732
- (sqadd x y (vector_size ty)))
733
-
734
- ;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
735
-
736
- (rule (lower (has_type (ty_vec128 ty) (usub_sat x y)))
737
- (uqsub x y (vector_size ty)))
738
-
739
- ;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
740
-
741
- (rule (lower (has_type (ty_vec128 ty) (ssub_sat x y)))
742
- (sqsub x y (vector_size ty)))
743
-
744
- ;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
745
-
746
- ;; `i64` and smaller.
747
- (rule 1 (lower (has_type (fits_in_64 ty) (ineg x)))
748
- (sub ty (zero_reg) x))
749
-
750
- ;; `i128`
751
- (rule 2 (lower (has_type $I128 (ineg x)))
752
- (sub_i128 (value_regs_zero) x))
753
-
754
- ;; vectors.
755
- (rule (lower (has_type (ty_vec128 ty) (ineg x)))
756
- (neg x (vector_size ty)))
757
-
758
- ;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
759
-
760
- ;; `i64` and smaller.
761
- (rule -3 (lower (has_type (fits_in_64 ty) (imul x y)))
762
- (madd ty x y (zero_reg)))
763
-
764
- ;; `i128`.
765
- (rule -1 (lower (has_type $I128 (imul x y)))
766
- (let
767
- ;; Get the high/low registers for `x`.
768
- ((x_regs ValueRegs x)
769
- (x_lo Reg (value_regs_get x_regs 0))
770
- (x_hi Reg (value_regs_get x_regs 1))
771
-
772
- ;; Get the high/low registers for `y`.
773
- (y_regs ValueRegs y)
774
- (y_lo Reg (value_regs_get y_regs 0))
775
- (y_hi Reg (value_regs_get y_regs 1))
776
-
777
- ;; 128bit mul formula:
778
- ;; dst_lo = x_lo * y_lo
779
- ;; dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
780
- ;;
781
- ;; We can convert the above formula into the following
782
- ;; umulh dst_hi, x_lo, y_lo
783
- ;; madd dst_hi, x_lo, y_hi, dst_hi
784
- ;; madd dst_hi, x_hi, y_lo, dst_hi
785
- ;; madd dst_lo, x_lo, y_lo, zero
786
- (dst_hi1 Reg (umulh $I64 x_lo y_lo))
787
- (dst_hi2 Reg (madd $I64 x_lo y_hi dst_hi1))
788
- (dst_hi Reg (madd $I64 x_hi y_lo dst_hi2))
789
- (dst_lo Reg (madd $I64 x_lo y_lo (zero_reg))))
790
- (value_regs dst_lo dst_hi)))
791
-
792
- ;; Case for i8x16, i16x8, and i32x4.
793
- (rule -2 (lower (has_type (ty_vec128 ty @ (not_i64x2)) (imul x y)))
794
- (mul x y (vector_size ty)))
795
-
796
- ;; Special lowering for i64x2.
797
- ;;
798
- ;; This I64X2 multiplication is performed with several 32-bit
799
- ;; operations.
800
- ;;
801
- ;; 64-bit numbers x and y, can be represented as:
802
- ;; x = a + 2^32(b)
803
- ;; y = c + 2^32(d)
804
- ;;
805
- ;; A 64-bit multiplication is:
806
- ;; x * y = ac + 2^32(ad + bc) + 2^64(bd)
807
- ;; note: `2^64(bd)` can be ignored, the value is too large to fit in
808
- ;; 64 bits.
809
- ;;
810
- ;; This sequence implements a I64X2 multiply, where the registers
811
- ;; `rn` and `rm` are split up into 32-bit components:
812
- ;; rn = |d|c|b|a|
813
- ;; rm = |h|g|f|e|
814
- ;;
815
- ;; rn * rm = |cg + 2^32(ch + dg)|ae + 2^32(af + be)|
816
- ;;
817
- ;; The sequence is:
818
- ;; rev64 rd.4s, rm.4s
819
- ;; mul rd.4s, rd.4s, rn.4s
820
- ;; xtn tmp1.2s, rn.2d
821
- ;; addp rd.4s, rd.4s, rd.4s
822
- ;; xtn tmp2.2s, rm.2d
823
- ;; shll rd.2d, rd.2s, #32
824
- ;; umlal rd.2d, tmp2.2s, tmp1.2s
825
- (rule -1 (lower (has_type $I64X2 (imul x y)))
826
- (let ((rn Reg x)
827
- (rm Reg y)
828
- ;; Reverse the 32-bit elements in the 64-bit words.
829
- ;; rd = |g|h|e|f|
830
- (rev Reg (rev64 rm (VectorSize.Size32x4)))
831
-
832
- ;; Calculate the high half components.
833
- ;; rd = |dg|ch|be|af|
834
- ;;
835
- ;; Note that this 32-bit multiply of the high half
836
- ;; discards the bits that would overflow, same as
837
- ;; if 64-bit operations were used. Also the Shll
838
- ;; below would shift out the overflow bits anyway.
839
- (mul Reg (mul rev rn (VectorSize.Size32x4)))
840
-
841
- ;; Extract the low half components of rn.
842
- ;; tmp1 = |c|a|
843
- (tmp1 Reg (xtn rn (ScalarSize.Size32)))
844
-
845
- ;; Sum the respective high half components.
846
- ;; rd = |dg+ch|be+af||dg+ch|be+af|
847
- (sum Reg (addp mul mul (VectorSize.Size32x4)))
848
-
849
- ;; Extract the low half components of rm.
850
- ;; tmp2 = |g|e|
851
- (tmp2 Reg (xtn rm (ScalarSize.Size32)))
852
-
853
- ;; Shift the high half components, into the high half.
854
- ;; rd = |dg+ch << 32|be+af << 32|
855
- (shift Reg (shll32 sum $false))
856
-
857
- ;; Multiply the low components together, and accumulate with the high
858
- ;; half.
859
- ;; rd = |rd[1] + cg|rd[0] + ae|
860
- (result Reg (umlal32 shift tmp2 tmp1 $false)))
861
- result))
862
-
863
- ;; Special case for `i16x8.extmul_low_i8x16_s`.
864
- (rule (lower (has_type $I16X8
865
- (imul (swiden_low x @ (value_type $I8X16))
866
- (swiden_low y @ (value_type $I8X16)))))
867
- (smull8 x y $false))
868
-
869
- ;; Special case for `i16x8.extmul_high_i8x16_s`.
870
- (rule (lower (has_type $I16X8
871
- (imul (swiden_high x @ (value_type $I8X16))
872
- (swiden_high y @ (value_type $I8X16)))))
873
- (smull8 x y $true))
874
-
875
- ;; Special case for `i16x8.extmul_low_i8x16_u`.
876
- (rule (lower (has_type $I16X8
877
- (imul (uwiden_low x @ (value_type $I8X16))
878
- (uwiden_low y @ (value_type $I8X16)))))
879
- (umull8 x y $false))
880
-
881
- ;; Special case for `i16x8.extmul_high_i8x16_u`.
882
- (rule (lower (has_type $I16X8
883
- (imul (uwiden_high x @ (value_type $I8X16))
884
- (uwiden_high y @ (value_type $I8X16)))))
885
- (umull8 x y $true))
886
-
887
- ;; Special case for `i32x4.extmul_low_i16x8_s`.
888
- (rule (lower (has_type $I32X4
889
- (imul (swiden_low x @ (value_type $I16X8))
890
- (swiden_low y @ (value_type $I16X8)))))
891
- (smull16 x y $false))
892
-
893
- ;; Special case for `i32x4.extmul_high_i16x8_s`.
894
- (rule (lower (has_type $I32X4
895
- (imul (swiden_high x @ (value_type $I16X8))
896
- (swiden_high y @ (value_type $I16X8)))))
897
- (smull16 x y $true))
898
-
899
- ;; Special case for `i32x4.extmul_low_i16x8_u`.
900
- (rule (lower (has_type $I32X4
901
- (imul (uwiden_low x @ (value_type $I16X8))
902
- (uwiden_low y @ (value_type $I16X8)))))
903
- (umull16 x y $false))
904
-
905
- ;; Special case for `i32x4.extmul_high_i16x8_u`.
906
- (rule (lower (has_type $I32X4
907
- (imul (uwiden_high x @ (value_type $I16X8))
908
- (uwiden_high y @ (value_type $I16X8)))))
909
- (umull16 x y $true))
910
-
911
- ;; Special case for `i64x2.extmul_low_i32x4_s`.
912
- (rule (lower (has_type $I64X2
913
- (imul (swiden_low x @ (value_type $I32X4))
914
- (swiden_low y @ (value_type $I32X4)))))
915
- (smull32 x y $false))
916
-
917
- ;; Special case for `i64x2.extmul_high_i32x4_s`.
918
- (rule (lower (has_type $I64X2
919
- (imul (swiden_high x @ (value_type $I32X4))
920
- (swiden_high y @ (value_type $I32X4)))))
921
- (smull32 x y $true))
922
-
923
- ;; Special case for `i64x2.extmul_low_i32x4_u`.
924
- (rule (lower (has_type $I64X2
925
- (imul (uwiden_low x @ (value_type $I32X4))
926
- (uwiden_low y @ (value_type $I32X4)))))
927
- (umull32 x y $false))
928
-
929
- ;; Special case for `i64x2.extmul_high_i32x4_u`.
930
- (rule (lower (has_type $I64X2
931
- (imul (uwiden_high x @ (value_type $I32X4))
932
- (uwiden_high y @ (value_type $I32X4)))))
933
- (umull32 x y $true))
934
-
935
- ;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
936
-
937
- (rule 1 (lower (has_type $I64 (smulhi x y)))
938
- (smulh $I64 x y))
939
-
940
- (rule (lower (has_type (fits_in_32 ty) (smulhi x y)))
941
- (let ((x64 Reg (put_in_reg_sext64 x))
942
- (y64 Reg (put_in_reg_sext64 y))
943
- (mul Reg (madd $I64 x64 y64 (zero_reg)))
944
- (result Reg (asr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
945
- result))
946
-
947
- ;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
948
-
949
- (rule 1 (lower (has_type $I64 (umulhi x y)))
950
- (umulh $I64 x y))
951
-
952
- (rule (lower (has_type (fits_in_32 ty) (umulhi x y)))
953
- (let (
954
- (x64 Reg (put_in_reg_zext64 x))
955
- (y64 Reg (put_in_reg_zext64 y))
956
- (mul Reg (madd $I64 x64 y64 (zero_reg)))
957
- (result Reg (lsr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty))))
958
- )
959
- (value_reg result)))
960
-
961
- ;;;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
962
-
963
- ;; TODO: Add UDiv32 to implement 32-bit directly, rather
964
- ;; than extending the input.
965
- ;;
966
- ;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of
967
- ;; CLIF's `udiv` the check for zero needs to be manually performed.
968
- (rule (lower (has_type (fits_in_64 ty) (udiv x y)))
969
- (a64_udiv $I64 (put_in_reg_zext64 x) (put_nonzero_in_reg_zext64 y)))
970
-
971
- ;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
972
- (decl put_nonzero_in_reg_zext64 (Value) Reg)
973
- (rule -1 (put_nonzero_in_reg_zext64 val)
974
- (trap_if_zero_divisor (put_in_reg_zext64 val)))
975
-
976
- ;; Special case where if a `Value` is known to be nonzero we can trivially
977
- ;; move it into a register.
978
- (rule (put_nonzero_in_reg_zext64 (and (value_type ty)
979
- (iconst (nonzero_u64_from_imm64 n))))
980
- (imm ty (ImmExtend.Zero) n))
981
-
982
- ;;;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
983
-
984
- ;; TODO: Add SDiv32 to implement 32-bit directly, rather
985
- ;; than extending the input.
986
- ;;
987
- ;; The sequence of checks here should look like:
988
- ;;
989
- ;; cbnz rm, #8
990
- ;; udf ; divide by zero
991
- ;; cmn rm, 1
992
- ;; ccmp rn, 1, #nzcv, eq
993
- ;; b.vc #8
994
- ;; udf ; signed overflow
995
- ;;
996
- ;; Note The div instruction does not trap on divide by zero or overflow, so
997
- ;; checks need to be manually inserted.
998
- ;;
999
- ;; TODO: if `y` is -1 then a check that `x` is not INT_MIN is all that's
1000
- ;; necessary, but right now `y` is checked to not be -1 as well.
1001
- (rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
1002
- (let ((x64 Reg (put_in_reg_sext64 x))
1003
- (y64 Reg (put_nonzero_in_reg_sext64 y))
1004
- (valid_x64 Reg (trap_if_div_overflow ty x64 y64))
1005
- (result Reg (a64_sdiv $I64 valid_x64 y64)))
1006
- result))
1007
-
1008
- ;; Special case for `sdiv` where no checks are needed due to division by a
1009
- ;; constant meaning the checks are always passed.
1010
- (rule 1 (lower (has_type (fits_in_64 ty) (sdiv x (iconst imm))))
1011
- (if-let y (safe_divisor_from_imm64 ty imm))
1012
- (a64_sdiv $I64 (put_in_reg_sext64 x) (imm ty (ImmExtend.Sign) y)))
1013
-
1014
- ;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
1015
- (decl put_nonzero_in_reg_sext64 (Value) Reg)
1016
- (rule -1 (put_nonzero_in_reg_sext64 val)
1017
- (trap_if_zero_divisor (put_in_reg_sext64 val)))
1018
-
1019
- ;; Note that this has a special case where if the `Value` is a constant that's
1020
- ;; not zero we can skip the zero check.
1021
- (rule (put_nonzero_in_reg_sext64 (and (value_type ty)
1022
- (iconst (nonzero_u64_from_imm64 n))))
1023
- (imm ty (ImmExtend.Sign) n))
1024
-
1025
- ;;;; Rules for `urem` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1026
-
1027
- ;; Remainder (x % y) is implemented as:
1028
- ;;
1029
- ;; tmp = x / y
1030
- ;; result = x - (tmp*y)
1031
- ;;
1032
- ;; use 'result' for tmp and you have:
1033
- ;;
1034
- ;; cbnz y, #8 ; branch over trap
1035
- ;; udf ; divide by zero
1036
- ;; div rd, x, y ; rd = x / y
1037
- ;; msub rd, rd, y, x ; rd = x - rd * y
1038
-
1039
- (rule (lower (has_type (fits_in_64 ty) (urem x y)))
1040
- (let ((x64 Reg (put_in_reg_zext64 x))
1041
- (y64 Reg (put_nonzero_in_reg_zext64 y))
1042
- (div Reg (a64_udiv $I64 x64 y64))
1043
- (result Reg (msub $I64 div y64 x64)))
1044
- result))
1045
-
1046
- (rule (lower (has_type (fits_in_64 ty) (srem x y)))
1047
- (let ((x64 Reg (put_in_reg_sext64 x))
1048
- (y64 Reg (put_nonzero_in_reg_sext64 y))
1049
- (div Reg (a64_sdiv $I64 x64 y64))
1050
- (result Reg (msub $I64 div y64 x64)))
1051
- result))
1052
-
1053
- ;;; Rules for integer min/max: umin, smin, umax, smax ;;;;;;;;;;;;;;;;;;;;;;;;;
1054
-
1055
- ;; `i64` and smaller.
1056
-
1057
- ;; cmp $x, $y
1058
- ;; csel .., $x, $y, $cc
1059
- (decl cmp_and_choose (Type Cond bool Value Value) ValueRegs)
1060
- (rule (cmp_and_choose (fits_in_64 ty) cc _ x y)
1061
- (let ((x Reg (put_in_reg x))
1062
- (y Reg (put_in_reg y)))
1063
- (with_flags_reg (cmp (operand_size ty) x y)
1064
- (csel cc x y))))
1065
-
1066
- ;; `i16` and `i8` min/max require sign extension as
1067
- ;; the comparison operates on (at least) 32 bits.
1068
- (rule 1 (cmp_and_choose (fits_in_16 ty) cc signed x y)
1069
- (let ((x Reg (extend (put_in_reg x) signed (ty_bits ty) 32))
1070
- (y Reg (extend (put_in_reg y) signed (ty_bits ty) 32)))
1071
- (with_flags_reg (cmp (operand_size ty) x y)
1072
- (csel cc x y))))
1073
-
1074
- (rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umin x y)))
1075
- (cmp_and_choose ty (Cond.Lo) $false x y))
1076
- (rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smin x y)))
1077
- (cmp_and_choose ty (Cond.Lt) $true x y))
1078
- (rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (umax x y)))
1079
- (cmp_and_choose ty (Cond.Hi) $false x y))
1080
- (rule 2 (lower (has_type (and (fits_in_64 ty) (ty_int _)) (smax x y)))
1081
- (cmp_and_choose ty (Cond.Gt) $true x y))
1082
-
1083
- ;; Vector types.
1084
-
1085
- (rule (lower (has_type ty @ (not_i64x2) (smin x y)))
1086
- (vec_rrr (VecALUOp.Smin) x y (vector_size ty)))
1087
-
1088
- (rule 1 (lower (has_type $I64X2 (smin x y)))
1089
- (bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) y x (VectorSize.Size64x2)) x y))
1090
-
1091
- (rule (lower (has_type ty @ (not_i64x2) (umin x y)))
1092
- (vec_rrr (VecALUOp.Umin) x y (vector_size ty)))
1093
-
1094
- (rule 1 (lower (has_type $I64X2 (umin x y)))
1095
- (bsl $I64X2 (vec_rrr (VecALUOp.Cmhi) y x (VectorSize.Size64x2)) x y))
1096
-
1097
- (rule (lower (has_type ty @ (not_i64x2) (smax x y)))
1098
- (vec_rrr (VecALUOp.Smax) x y (vector_size ty)))
1099
-
1100
- (rule 1 (lower (has_type $I64X2 (smax x y)))
1101
- (bsl $I64X2 (vec_rrr (VecALUOp.Cmgt) x y (VectorSize.Size64x2)) x y))
1102
-
1103
- (rule (lower (has_type ty @ (not_i64x2) (umax x y)))
1104
- (vec_rrr (VecALUOp.Umax) x y (vector_size ty)))
1105
-
1106
- (rule 1 (lower (has_type $I64X2 (umax x y)))
1107
- (bsl $I64X2 (vec_rrr (VecALUOp.Cmhi) x y (VectorSize.Size64x2)) x y))
1108
-
1109
- ;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1110
-
1111
- ;; General rule for extending input to an output which fits in a single
1112
- ;; register.
1113
- (rule -2 (lower (has_type (fits_in_64 out) (uextend x @ (value_type in))))
1114
- (extend x $false (ty_bits in) (ty_bits out)))
1115
-
1116
- ;; Extraction of a vector lane automatically extends as necessary, so we can
1117
- ;; skip an explicit extending instruction.
1118
- (rule 1 (lower (has_type (fits_in_64 out)
1119
- (uextend (extractlane vec @ (value_type in)
1120
- (u8_from_uimm8 lane)))))
1121
- (mov_from_vec (put_in_reg vec) lane (lane_size in)))
1122
-
1123
- ;; Atomic loads will also automatically zero their upper bits so the `uextend`
1124
- ;; instruction can effectively get skipped here.
1125
- (rule 1 (lower (has_type (fits_in_64 out)
1126
- (uextend x @ (and (value_type in) (atomic_load flags _)))))
1127
- (if-let mem_op (is_sinkable_inst x))
1128
- (load_acquire in flags (sink_atomic_load mem_op)))
1129
-
1130
- ;; Conversion to 128-bit needs a zero-extension of the lower bits and the upper
1131
- ;; bits are all zero.
1132
- (rule -1 (lower (has_type $I128 (uextend x)))
1133
- (value_regs (put_in_reg_zext64 x) (imm $I64 (ImmExtend.Zero) 0)))
1134
-
1135
- ;; Like above where vector extraction automatically zero-extends extending to
1136
- ;; i128 only requires generating a 0 constant for the upper bits.
1137
- (rule (lower (has_type $I128
1138
- (uextend (extractlane vec @ (value_type in)
1139
- (u8_from_uimm8 lane)))))
1140
- (value_regs (mov_from_vec (put_in_reg vec) lane (lane_size in)) (imm $I64 (ImmExtend.Zero) 0)))
1141
-
1142
- ;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1143
-
1144
- ;; General rule for extending input to an output which fits in a single
1145
- ;; register.
1146
- (rule -4 (lower (has_type (fits_in_64 out) (sextend x @ (value_type in))))
1147
- (extend x $true (ty_bits in) (ty_bits out)))
1148
-
1149
- ;; Extraction of a vector lane automatically extends as necessary, so we can
1150
- ;; skip an explicit extending instruction.
1151
- (rule -3 (lower (has_type (fits_in_64 out)
1152
- (sextend (extractlane vec @ (value_type in)
1153
- (u8_from_uimm8 lane)))))
1154
- (mov_from_vec_signed (put_in_reg vec)
1155
- lane
1156
- (vector_size in)
1157
- (size_from_ty out)))
1158
-
1159
- ;; 64-bit to 128-bit only needs to sign-extend the input to the upper bits.
1160
- (rule -2 (lower (has_type $I128 (sextend x)))
1161
- (let ((lo Reg (put_in_reg_sext64 x))
1162
- (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
1163
- (value_regs lo hi)))
1164
-
1165
- ;; Like above where vector extraction automatically zero-extends extending to
1166
- ;; i128 only requires generating a 0 constant for the upper bits.
1167
- ;;
1168
- ;; Note that `mov_from_vec_signed` doesn't exist for i64x2, so that's
1169
- ;; specifically excluded here.
1170
- (rule (lower (has_type $I128
1171
- (sextend (extractlane vec @ (value_type in @ (not_i64x2))
1172
- (u8_from_uimm8 lane)))))
1173
- (let ((lo Reg (mov_from_vec_signed (put_in_reg vec)
1174
- lane
1175
- (vector_size in)
1176
- (size_from_ty $I64)))
1177
- (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
1178
- (value_regs lo hi)))
1179
-
1180
- ;; Extension from an extraction of i64x2 into i128.
1181
- (rule -1 (lower (has_type $I128
1182
- (sextend (extractlane vec @ (value_type $I64X2)
1183
- (u8_from_uimm8 lane)))))
1184
- (let ((lo Reg (mov_from_vec (put_in_reg vec)
1185
- lane
1186
- (ScalarSize.Size64)))
1187
- (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
1188
- (value_regs lo hi)))
1189
-
1190
- ;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1191
-
1192
- ;; Base case using `orn` between two registers.
1193
- ;;
1194
- ;; Note that bitwise negation is implemented here as
1195
- ;;
1196
- ;; NOT rd, rm ==> ORR_NOT rd, zero, rm
1197
- (rule -1 (lower (has_type (fits_in_64 ty) (bnot x)))
1198
- (orr_not ty (zero_reg) x))
1199
-
1200
- ;; Special case to use `orr_not_shift` if it's a `bnot` of a const-left-shifted
1201
- ;; value.
1202
- (rule 1 (lower (has_type (fits_in_64 ty)
1203
- (bnot (ishl x (iconst k)))))
1204
- (if-let amt (lshl_from_imm64 ty k))
1205
- (orr_not_shift ty (zero_reg) x amt))
1206
-
1207
- ;; Implementation of `bnot` for `i128`.
1208
- (rule (lower (has_type $I128 (bnot x)))
1209
- (let ((x_regs ValueRegs x)
1210
- (x_lo Reg (value_regs_get x_regs 0))
1211
- (x_hi Reg (value_regs_get x_regs 1))
1212
- (new_lo Reg (orr_not $I64 (zero_reg) x_lo))
1213
- (new_hi Reg (orr_not $I64 (zero_reg) x_hi)))
1214
- (value_regs new_lo new_hi)))
1215
-
1216
- ;; Implementation of `bnot` for vector types.
1217
- (rule -2 (lower (has_type (ty_vec128 ty) (bnot x)))
1218
- (not x (vector_size ty)))
1219
-
1220
- ;; Special-cases for fusing a bnot with bxor
1221
- (rule 2 (lower (has_type (fits_in_64 ty) (bnot (bxor x y))))
1222
- (alu_rs_imm_logic (ALUOp.EorNot) ty x y))
1223
- (rule 3 (lower (has_type $I128 (bnot (bxor x y)))) (i128_alu_bitop (ALUOp.EorNot) $I64 x y))
1224
-
1225
- ;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1226
-
1227
- (rule -1 (lower (has_type (fits_in_64 ty) (band x y)))
1228
- (alu_rs_imm_logic_commutative (ALUOp.And) ty x y))
1229
-
1230
- (rule (lower (has_type $I128 (band x y))) (i128_alu_bitop (ALUOp.And) $I64 x y))
1231
-
1232
- (rule -2 (lower (has_type (ty_vec128 ty) (band x y)))
1233
- (and_vec x y (vector_size ty)))
1234
-
1235
- ;; Specialized lowerings for `(band x (bnot y))` which is additionally produced
1236
- ;; by Cranelift's `band_not` instruction that is legalized into the simpler
1237
- ;; forms early on.
1238
-
1239
- (rule 1 (lower (has_type (fits_in_64 ty) (band x (bnot y))))
1240
- (alu_rs_imm_logic (ALUOp.AndNot) ty x y))
1241
- (rule 2 (lower (has_type (fits_in_64 ty) (band (bnot y) x)))
1242
- (alu_rs_imm_logic (ALUOp.AndNot) ty x y))
1243
-
1244
- (rule 3 (lower (has_type $I128 (band x (bnot y)))) (i128_alu_bitop (ALUOp.AndNot) $I64 x y))
1245
- (rule 4 (lower (has_type $I128 (band (bnot y) x))) (i128_alu_bitop (ALUOp.AndNot) $I64 x y))
1246
-
1247
- (rule 5 (lower (has_type (ty_vec128 ty) (band x (bnot y))))
1248
- (bic_vec x y (vector_size ty)))
1249
- (rule 6 (lower (has_type (ty_vec128 ty) (band (bnot y) x)))
1250
- (bic_vec x y (vector_size ty)))
1251
-
1252
- ;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1253
-
1254
- (rule -1 (lower (has_type (fits_in_64 ty) (bor x y)))
1255
- (alu_rs_imm_logic_commutative (ALUOp.Orr) ty x y))
1256
-
1257
- (rule (lower (has_type $I128 (bor x y))) (i128_alu_bitop (ALUOp.Orr) $I64 x y))
1258
-
1259
- (rule -2 (lower (has_type (ty_vec128 ty) (bor x y)))
1260
- (orr_vec x y (vector_size ty)))
1261
-
1262
- ;; Specialized lowerings for `(bor x (bnot y))` which is additionally produced
1263
- ;; by Cranelift's `bor_not` instruction that is legalized into the simpler
1264
- ;; forms early on.
1265
-
1266
- (rule 1 (lower (has_type (fits_in_64 ty) (bor x (bnot y))))
1267
- (alu_rs_imm_logic (ALUOp.OrrNot) ty x y))
1268
- (rule 2 (lower (has_type (fits_in_64 ty) (bor (bnot y) x)))
1269
- (alu_rs_imm_logic (ALUOp.OrrNot) ty x y))
1270
-
1271
- (rule 3 (lower (has_type $I128 (bor x (bnot y)))) (i128_alu_bitop (ALUOp.OrrNot) $I64 x y))
1272
- (rule 4 (lower (has_type $I128 (bor (bnot y) x))) (i128_alu_bitop (ALUOp.OrrNot) $I64 x y))
1273
-
1274
- ;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1275
-
1276
- (rule -1 (lower (has_type (fits_in_64 ty) (bxor x y)))
1277
- (alu_rs_imm_logic_commutative (ALUOp.Eor) ty x y))
1278
-
1279
- (rule (lower (has_type $I128 (bxor x y))) (i128_alu_bitop (ALUOp.Eor) $I64 x y))
1280
-
1281
- (rule -2 (lower (has_type (ty_vec128 ty) (bxor x y)))
1282
- (eor_vec x y (vector_size ty)))
1283
-
1284
- ;; Specialized lowerings for `(bxor x (bnot y))` which is additionally produced
1285
- ;; by Cranelift's `bxor_not` instruction that is legalized into the simpler
1286
- ;; forms early on.
1287
-
1288
- (rule 1 (lower (has_type (fits_in_64 ty) (bxor x (bnot y))))
1289
- (alu_rs_imm_logic (ALUOp.EorNot) ty x y))
1290
- (rule 2 (lower (has_type (fits_in_64 ty) (bxor (bnot y) x)))
1291
- (alu_rs_imm_logic (ALUOp.EorNot) ty x y))
1292
-
1293
- (rule 3 (lower (has_type $I128 (bxor x (bnot y)))) (i128_alu_bitop (ALUOp.EorNot) $I64 x y))
1294
- (rule 4 (lower (has_type $I128 (bxor (bnot y) x))) (i128_alu_bitop (ALUOp.EorNot) $I64 x y))
1295
-
1296
- ;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1297
-
1298
- ;; Shift for i8/i16/i32.
1299
- (rule -1 (lower (has_type (fits_in_32 ty) (ishl x y)))
1300
- (do_shift (ALUOp.Lsl) ty x y))
1301
-
1302
- ;; Shift for i64.
1303
- (rule (lower (has_type $I64 (ishl x y)))
1304
- (do_shift (ALUOp.Lsl) $I64 x y))
1305
-
1306
- ;; Shift for i128.
1307
- (rule (lower (has_type $I128 (ishl x y)))
1308
- (lower_shl128 x (value_regs_get y 0)))
1309
-
1310
- ;; lsl lo_lshift, src_lo, amt
1311
- ;; lsl hi_lshift, src_hi, amt
1312
- ;; mvn inv_amt, amt
1313
- ;; lsr lo_rshift, src_lo, #1
1314
- ;; lsr lo_rshift, lo_rshift, inv_amt
1315
- ;; orr maybe_hi, hi_lshift, lo_rshift
1316
- ;; tst amt, #0x40
1317
- ;; csel dst_hi, lo_lshift, maybe_hi, ne
1318
- ;; csel dst_lo, xzr, lo_lshift, ne
1319
- (decl lower_shl128 (ValueRegs Reg) ValueRegs)
1320
- (rule (lower_shl128 src amt)
1321
- (let ((src_lo Reg (value_regs_get src 0))
1322
- (src_hi Reg (value_regs_get src 1))
1323
- (lo_lshift Reg (lsl $I64 src_lo amt))
1324
- (hi_lshift Reg (lsl $I64 src_hi amt))
1325
- (inv_amt Reg (orr_not $I32 (zero_reg) amt))
1326
- (lo_rshift Reg (lsr $I64 (lsr_imm $I64 src_lo (imm_shift_from_u8 1))
1327
- inv_amt))
1328
- (maybe_hi Reg (orr $I64 hi_lshift lo_rshift))
1329
- )
1330
- (with_flags
1331
- (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
1332
- (consumes_flags_concat
1333
- (csel (Cond.Ne) (zero_reg) lo_lshift)
1334
- (csel (Cond.Ne) lo_lshift maybe_hi)))))
1335
-
1336
- ;; Shift for vector types.
1337
- (rule -3 (lower (has_type (ty_vec128 ty) (ishl x y)))
1338
- (let ((size VectorSize (vector_size ty))
1339
- (masked_shift_amt Reg (and_imm $I32 y (shift_mask ty)))
1340
- (shift Reg (vec_dup masked_shift_amt size)))
1341
- (sshl x shift size)))
1342
- (rule -2 (lower (has_type (ty_vec128 ty) (ishl x (iconst (u64_from_imm64 n)))))
1343
- (ushl_vec_imm x (shift_masked_imm ty n) (vector_size ty)))
1344
-
1345
- (decl pure shift_masked_imm (Type u64) u8)
1346
- (extern constructor shift_masked_imm shift_masked_imm)
1347
-
1348
- ;; Helper function to emit a shift operation with the opcode specified and
1349
- ;; the output type specified. The `Reg` provided is shifted by the `Value`
1350
- ;; given.
1351
- ;;
1352
- ;; Note that this automatically handles the clif semantics of masking the
1353
- ;; shift amount where necessary.
1354
- (decl do_shift (ALUOp Type Reg Value) Reg)
1355
-
1356
- ;; 8/16-bit shift base case.
1357
- ;;
1358
- ;; When shifting for amounts larger than the size of the type, the CLIF shift
1359
- ;; instructions implement a "wrapping" behaviour, such that an i8 << 8 is
1360
- ;; equivalent to i8 << 0
1361
- ;;
1362
- ;; On i32 and i64 types this matches what the aarch64 spec does, but on smaller
1363
- ;; types (i16, i8) we need to do this manually, so we wrap the shift amount
1364
- ;; with an AND instruction
1365
- (rule -1 (do_shift op (fits_in_16 ty) x y)
1366
- (let ((shift_amt Reg (value_regs_get y 0))
1367
- (masked_shift_amt Reg (and_imm $I32 shift_amt (shift_mask ty))))
1368
- (alu_rrr op $I32 x masked_shift_amt)))
1369
-
1370
- (decl shift_mask (Type) ImmLogic)
1371
- (extern constructor shift_mask shift_mask)
1372
-
1373
- ;; 32/64-bit shift base cases.
1374
- (rule (do_shift op $I32 x y) (alu_rrr op $I32 x (value_regs_get y 0)))
1375
- (rule (do_shift op $I64 x y) (alu_rrr op $I64 x (value_regs_get y 0)))
1376
-
1377
- ;; Special case for shifting by a constant value where the value can fit into an
1378
- ;; `ImmShift`.
1379
- ;;
1380
- ;; Note that this rule explicitly has a higher priority than the others
1381
- ;; to ensure it's attempted first, otherwise the type-based filters on the
1382
- ;; previous rules seem to take priority over this rule.
1383
- (rule 1 (do_shift op ty x (iconst k))
1384
- (if-let shift (imm_shift_from_imm64 ty k))
1385
- (alu_rr_imm_shift op ty x shift))
1386
-
1387
- ;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1388
-
1389
- ;; Shift for i8/i16/i32.
1390
- (rule -1 (lower (has_type (fits_in_32 ty) (ushr x y)))
1391
- (do_shift (ALUOp.Lsr) ty (put_in_reg_zext32 x) y))
1392
-
1393
- ;; Shift for i64.
1394
- (rule (lower (has_type $I64 (ushr x y)))
1395
- (do_shift (ALUOp.Lsr) $I64 (put_in_reg_zext64 x) y))
1396
-
1397
- ;; Shift for i128.
1398
- (rule (lower (has_type $I128 (ushr x y)))
1399
- (lower_ushr128 x (value_regs_get y 0)))
1400
-
1401
- ;; Vector shifts.
1402
- ;;
1403
- ;; Note that for constant shifts a 0-width shift can't be emitted so it's
1404
- ;; special cased to pass through the input as-is since a 0-shift doesn't modify
1405
- ;; the input anyway.
1406
- (rule -4 (lower (has_type (ty_vec128 ty) (ushr x y)))
1407
- (let ((size VectorSize (vector_size ty))
1408
- (masked_shift_amt Reg (and_imm $I32 y (shift_mask ty)))
1409
- (shift Reg (vec_dup (sub $I64 (zero_reg) masked_shift_amt) size)))
1410
- (ushl x shift size)))
1411
- (rule -3 (lower (has_type (ty_vec128 ty) (ushr x (iconst (u64_from_imm64 n)))))
1412
- (ushr_vec_imm x (shift_masked_imm ty n) (vector_size ty)))
1413
- (rule -2 (lower (has_type (ty_vec128 ty) (ushr x (iconst (u64_from_imm64 n)))))
1414
- (if-let 0 (shift_masked_imm ty n))
1415
- x)
1416
-
1417
- ;; lsr lo_rshift, src_lo, amt
1418
- ;; lsr hi_rshift, src_hi, amt
1419
- ;; mvn inv_amt, amt
1420
- ;; lsl hi_lshift, src_hi, #1
1421
- ;; lsl hi_lshift, hi_lshift, inv_amt
1422
- ;; tst amt, #0x40
1423
- ;; orr maybe_lo, lo_rshift, hi_lshift
1424
- ;; csel dst_hi, xzr, hi_rshift, ne
1425
- ;; csel dst_lo, hi_rshift, maybe_lo, ne
1426
- (decl lower_ushr128 (ValueRegs Reg) ValueRegs)
1427
- (rule (lower_ushr128 src amt)
1428
- (let ((src_lo Reg (value_regs_get src 0))
1429
- (src_hi Reg (value_regs_get src 1))
1430
- (lo_rshift Reg (lsr $I64 src_lo amt))
1431
- (hi_rshift Reg (lsr $I64 src_hi amt))
1432
-
1433
- (inv_amt Reg (orr_not $I32 (zero_reg) amt))
1434
- (hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
1435
- inv_amt))
1436
- (maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
1437
- )
1438
- (with_flags
1439
- (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
1440
- (consumes_flags_concat
1441
- (csel (Cond.Ne) hi_rshift maybe_lo)
1442
- (csel (Cond.Ne) (zero_reg) hi_rshift)))))
1443
-
1444
- ;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1445
-
1446
- ;; Shift for i8/i16/i32.
1447
- (rule -4 (lower (has_type (fits_in_32 ty) (sshr x y)))
1448
- (do_shift (ALUOp.Asr) ty (put_in_reg_sext32 x) y))
1449
-
1450
- ;; Shift for i64.
1451
- (rule (lower (has_type $I64 (sshr x y)))
1452
- (do_shift (ALUOp.Asr) $I64 (put_in_reg_sext64 x) y))
1453
-
1454
- ;; Shift for i128.
1455
- (rule (lower (has_type $I128 (sshr x y)))
1456
- (lower_sshr128 x (value_regs_get y 0)))
1457
-
1458
- ;; Vector shifts.
1459
- ;;
1460
- ;; Note that right shifts are implemented with a negative left shift. Also note
1461
- ;; that for constant shifts a 0-width shift can't be emitted so it's special
1462
- ;; cased to pass through the input as-is since a 0-shift doesn't modify the
1463
- ;; input anyway.
1464
- (rule -3 (lower (has_type (ty_vec128 ty) (sshr x y)))
1465
- (let ((size VectorSize (vector_size ty))
1466
- (masked_shift_amt Reg (and_imm $I32 y (shift_mask ty)))
1467
- (shift Reg (vec_dup (sub $I64 (zero_reg) masked_shift_amt) size)))
1468
- (sshl x shift size)))
1469
- (rule -2 (lower (has_type (ty_vec128 ty) (sshr x (iconst (u64_from_imm64 n)))))
1470
- (sshr_vec_imm x (shift_masked_imm ty n) (vector_size ty)))
1471
- (rule -1 (lower (has_type (ty_vec128 ty) (sshr x (iconst (u64_from_imm64 n)))))
1472
- (if-let 0 (shift_masked_imm ty n))
1473
- x)
1474
-
1475
- ;; lsr lo_rshift, src_lo, amt
1476
- ;; asr hi_rshift, src_hi, amt
1477
- ;; mvn inv_amt, amt
1478
- ;; lsl hi_lshift, src_hi, #1
1479
- ;; lsl hi_lshift, hi_lshift, inv_amt
1480
- ;; asr hi_sign, src_hi, #63
1481
- ;; orr maybe_lo, lo_rshift, hi_lshift
1482
- ;; tst amt, #0x40
1483
- ;; csel dst_hi, hi_sign, hi_rshift, ne
1484
- ;; csel dst_lo, hi_rshift, maybe_lo, ne
1485
- (decl lower_sshr128 (ValueRegs Reg) ValueRegs)
1486
- (rule (lower_sshr128 src amt)
1487
- (let ((src_lo Reg (value_regs_get src 0))
1488
- (src_hi Reg (value_regs_get src 1))
1489
- (lo_rshift Reg (lsr $I64 src_lo amt))
1490
- (hi_rshift Reg (asr $I64 src_hi amt))
1491
-
1492
- (inv_amt Reg (orr_not $I32 (zero_reg) amt))
1493
- (hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
1494
- inv_amt))
1495
- (hi_sign Reg (asr_imm $I64 src_hi (imm_shift_from_u8 63)))
1496
- (maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
1497
- )
1498
- (with_flags
1499
- (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
1500
- (consumes_flags_concat
1501
- (csel (Cond.Ne) hi_rshift maybe_lo)
1502
- (csel (Cond.Ne) hi_sign hi_rshift)))))
1503
-
1504
- ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1505
-
1506
- ;; General 8/16-bit case.
1507
- (rule -2 (lower (has_type (fits_in_16 ty) (rotl x y)))
1508
- (let ((amt Reg (value_regs_get y 0))
1509
- (neg_shift Reg (sub $I32 (zero_reg) amt)))
1510
- (small_rotr ty (put_in_reg_zext32 x) neg_shift)))
1511
-
1512
- ;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
1513
- (rule -1 (lower (has_type (fits_in_16 ty) (rotl x (iconst k))))
1514
- (if-let n (imm_shift_from_imm64 ty k))
1515
- (small_rotr_imm ty (put_in_reg_zext32 x) (negate_imm_shift ty n)))
1516
-
1517
- ;; aarch64 doesn't have a left-rotate instruction, but a left rotation of K
1518
- ;; places is effectively a right rotation of N - K places, if N is the integer's
1519
- ;; bit size. We implement left rotations with this trick.
1520
- ;;
1521
- ;; Note that when negating the shift amount here the upper bits are ignored
1522
- ;; by the rotr instruction, meaning that we'll still left-shift by the desired
1523
- ;; amount.
1524
-
1525
- ;; General 32-bit case.
1526
- (rule (lower (has_type $I32 (rotl x y)))
1527
- (let ((amt Reg (value_regs_get y 0))
1528
- (neg_shift Reg (sub $I32 (zero_reg) amt)))
1529
- (a64_rotr $I32 x neg_shift)))
1530
-
1531
- ;; General 64-bit case.
1532
- (rule (lower (has_type $I64 (rotl x y)))
1533
- (let ((amt Reg (value_regs_get y 0))
1534
- (neg_shift Reg (sub $I64 (zero_reg) amt)))
1535
- (a64_rotr $I64 x neg_shift)))
1536
-
1537
- ;; Specialization for the 32-bit case when the rotation amount is an immediate.
1538
- (rule 1 (lower (has_type $I32 (rotl x (iconst k))))
1539
- (if-let n (imm_shift_from_imm64 $I32 k))
1540
- (a64_rotr_imm $I32 x (negate_imm_shift $I32 n)))
1541
-
1542
- ;; Specialization for the 64-bit case when the rotation amount is an immediate.
1543
- (rule 1 (lower (has_type $I64 (rotl x (iconst k))))
1544
- (if-let n (imm_shift_from_imm64 $I64 k))
1545
- (a64_rotr_imm $I64 x (negate_imm_shift $I64 n)))
1546
-
1547
- (decl negate_imm_shift (Type ImmShift) ImmShift)
1548
- (extern constructor negate_imm_shift negate_imm_shift)
1549
-
1550
- ;; General 128-bit case.
1551
- ;;
1552
- ;; TODO: much better codegen is possible with a constant amount.
1553
- (rule (lower (has_type $I128 (rotl x y)))
1554
- (let ((val ValueRegs x)
1555
- (amt Reg (value_regs_get y 0))
1556
- (neg_amt Reg (sub $I64 (imm $I64 (ImmExtend.Zero) 128) amt))
1557
- (lshift ValueRegs (lower_shl128 val amt))
1558
- (rshift ValueRegs (lower_ushr128 val neg_amt)))
1559
- (value_regs
1560
- (orr $I64 (value_regs_get lshift 0) (value_regs_get rshift 0))
1561
- (orr $I64 (value_regs_get lshift 1) (value_regs_get rshift 1)))))
1562
-
1563
- ;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1564
-
1565
- ;; General 8/16-bit case.
1566
- (rule -3 (lower (has_type (fits_in_16 ty) (rotr x y)))
1567
- (small_rotr ty (put_in_reg_zext32 x) (value_regs_get y 0)))
1568
-
1569
- ;; General 32-bit case.
1570
- (rule -1 (lower (has_type $I32 (rotr x y)))
1571
- (a64_rotr $I32 x (value_regs_get y 0)))
1572
-
1573
- ;; General 64-bit case.
1574
- (rule -1 (lower (has_type $I64 (rotr x y)))
1575
- (a64_rotr $I64 x (value_regs_get y 0)))
1576
-
1577
- ;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
1578
- (rule -2 (lower (has_type (fits_in_16 ty) (rotr x (iconst k))))
1579
- (if-let n (imm_shift_from_imm64 ty k))
1580
- (small_rotr_imm ty (put_in_reg_zext32 x) n))
1581
-
1582
- ;; Specialization for the 32-bit case when the rotation amount is an immediate.
1583
- (rule (lower (has_type $I32 (rotr x (iconst k))))
1584
- (if-let n (imm_shift_from_imm64 $I32 k))
1585
- (a64_rotr_imm $I32 x n))
1586
-
1587
- ;; Specialization for the 64-bit case when the rotation amount is an immediate.
1588
- (rule (lower (has_type $I64 (rotr x (iconst k))))
1589
- (if-let n (imm_shift_from_imm64 $I64 k))
1590
- (a64_rotr_imm $I64 x n))
1591
-
1592
- ;; For a < 32-bit rotate-right, we synthesize this as:
1593
- ;;
1594
- ;; rotr rd, val, amt
1595
- ;;
1596
- ;; =>
1597
- ;;
1598
- ;; and masked_amt, amt, <bitwidth - 1>
1599
- ;; sub tmp_sub, masked_amt, <bitwidth>
1600
- ;; sub neg_amt, zero, tmp_sub ; neg
1601
- ;; lsr val_rshift, val, masked_amt
1602
- ;; lsl val_lshift, val, neg_amt
1603
- ;; orr rd, val_lshift val_rshift
1604
- (decl small_rotr (Type Reg Reg) Reg)
1605
- (rule (small_rotr ty val amt)
1606
- (let ((masked_amt Reg (and_imm $I32 amt (rotr_mask ty)))
1607
- (tmp_sub Reg (sub_imm $I32 masked_amt (u8_into_imm12 (ty_bits ty))))
1608
- (neg_amt Reg (sub $I32 (zero_reg) tmp_sub))
1609
- (val_rshift Reg (lsr $I32 val masked_amt))
1610
- (val_lshift Reg (lsl $I32 val neg_amt)))
1611
- (orr $I32 val_lshift val_rshift)))
1612
-
1613
- (decl rotr_mask (Type) ImmLogic)
1614
- (extern constructor rotr_mask rotr_mask)
1615
-
1616
- ;; For a constant amount, we can instead do:
1617
- ;;
1618
- ;; rotr rd, val, #amt
1619
- ;;
1620
- ;; =>
1621
- ;;
1622
- ;; lsr val_rshift, val, #<amt>
1623
- ;; lsl val_lshift, val, <bitwidth - amt>
1624
- ;; orr rd, val_lshift, val_rshift
1625
- (decl small_rotr_imm (Type Reg ImmShift) Reg)
1626
- (rule (small_rotr_imm ty val amt)
1627
- (let ((val_rshift Reg (lsr_imm $I32 val amt))
1628
- (val_lshift Reg (lsl_imm $I32 val (rotr_opposite_amount ty amt))))
1629
- (orr $I32 val_lshift val_rshift)))
1630
-
1631
- (decl rotr_opposite_amount (Type ImmShift) ImmShift)
1632
- (extern constructor rotr_opposite_amount rotr_opposite_amount)
1633
-
1634
- ;; General 128-bit case.
1635
- ;;
1636
- ;; TODO: much better codegen is possible with a constant amount.
1637
- (rule (lower (has_type $I128 (rotr x y)))
1638
- (let ((val ValueRegs x)
1639
- (amt Reg (value_regs_get y 0))
1640
- (neg_amt Reg (sub $I64 (imm $I64 (ImmExtend.Zero) 128) amt))
1641
- (rshift ValueRegs (lower_ushr128 val amt))
1642
- (lshift ValueRegs (lower_shl128 val neg_amt))
1643
- (hi Reg (orr $I64 (value_regs_get rshift 1) (value_regs_get lshift 1)))
1644
- (lo Reg (orr $I64 (value_regs_get rshift 0) (value_regs_get lshift 0))))
1645
- (value_regs lo hi)))
1646
-
1647
- ;;;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1648
-
1649
- ;; Reversing an 8-bit value with a 32-bit bitrev instruction will place
1650
- ;; the reversed result in the highest 8 bits, so we need to shift them down into
1651
- ;; place.
1652
- (rule (lower (has_type $I8 (bitrev x)))
1653
- (lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 24)))
1654
-
1655
- ;; Reversing an 16-bit value with a 32-bit bitrev instruction will place
1656
- ;; the reversed result in the highest 16 bits, so we need to shift them down into
1657
- ;; place.
1658
- (rule (lower (has_type $I16 (bitrev x)))
1659
- (lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 16)))
1660
-
1661
- (rule (lower (has_type $I128 (bitrev x)))
1662
- (let ((val ValueRegs x)
1663
- (lo_rev Reg (rbit $I64 (value_regs_get val 0)))
1664
- (hi_rev Reg (rbit $I64 (value_regs_get val 1))))
1665
- (value_regs hi_rev lo_rev)))
1666
-
1667
- (rule -1 (lower (has_type ty (bitrev x)))
1668
- (rbit ty x))
1669
-
1670
-
1671
- ;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1672
-
1673
- (rule (lower (has_type $I8 (clz x)))
1674
- (sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 24)))
1675
-
1676
- (rule (lower (has_type $I16 (clz x)))
1677
- (sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 16)))
1678
-
1679
- (rule (lower (has_type $I128 (clz x)))
1680
- (lower_clz128 x))
1681
-
1682
- (rule -1 (lower (has_type ty (clz x)))
1683
- (a64_clz ty x))
1684
-
1685
- ;; clz hi_clz, hi
1686
- ;; clz lo_clz, lo
1687
- ;; lsr tmp, hi_clz, #6
1688
- ;; madd dst_lo, lo_clz, tmp, hi_clz
1689
- ;; mov dst_hi, 0
1690
- (decl lower_clz128 (ValueRegs) ValueRegs)
1691
- (rule (lower_clz128 val)
1692
- (let ((hi_clz Reg (a64_clz $I64 (value_regs_get val 1)))
1693
- (lo_clz Reg (a64_clz $I64 (value_regs_get val 0)))
1694
- (tmp Reg (lsr_imm $I64 hi_clz (imm_shift_from_u8 6))))
1695
- (value_regs (madd $I64 lo_clz tmp hi_clz) (imm $I64 (ImmExtend.Zero) 0))))
1696
-
1697
- ;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1698
-
1699
- ;; Note that all `ctz` instructions are implemented by reversing the bits and
1700
- ;; then using a `clz` instruction since the tail zeros are the same as the
1701
- ;; leading zeros of the reversed value.
1702
-
1703
- (rule (lower (has_type $I8 (ctz x)))
1704
- (a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x800000))))
1705
-
1706
- (rule (lower (has_type $I16 (ctz x)))
1707
- (a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x8000))))
1708
-
1709
- (rule (lower (has_type $I128 (ctz x)))
1710
- (let ((val ValueRegs x)
1711
- (lo Reg (rbit $I64 (value_regs_get val 0)))
1712
- (hi Reg (rbit $I64 (value_regs_get val 1))))
1713
- (lower_clz128 (value_regs hi lo))))
1714
-
1715
- (rule -1 (lower (has_type ty (ctz x)))
1716
- (a64_clz ty (rbit ty x)))
1717
-
1718
- ;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1719
-
1720
- (rule (lower (has_type $I8 (cls x)))
1721
- (sub_imm $I32 (a64_cls $I32 (put_in_reg_sext32 x)) (u8_into_imm12 24)))
1722
-
1723
- (rule (lower (has_type $I16 (cls x)))
1724
- (sub_imm $I32 (a64_cls $I32 (put_in_reg_sext32 x)) (u8_into_imm12 16)))
1725
-
1726
- ;; cls lo_cls, lo
1727
- ;; cls hi_cls, hi
1728
- ;; eon sign_eq_eor, hi, lo
1729
- ;; lsr sign_eq, sign_eq_eor, #63
1730
- ;; madd lo_sign_bits, out_lo, sign_eq, sign_eq
1731
- ;; cmp hi_cls, #63
1732
- ;; csel maybe_lo, lo_sign_bits, xzr, eq
1733
- ;; add out_lo, maybe_lo, hi_cls
1734
- ;; mov out_hi, 0
1735
- (rule (lower (has_type $I128 (cls x)))
1736
- (let ((val ValueRegs x)
1737
- (lo Reg (value_regs_get val 0))
1738
- (hi Reg (value_regs_get val 1))
1739
- (lo_cls Reg (a64_cls $I64 lo))
1740
- (hi_cls Reg (a64_cls $I64 hi))
1741
- (sign_eq_eon Reg (eon $I64 hi lo))
1742
- (sign_eq Reg (lsr_imm $I64 sign_eq_eon (imm_shift_from_u8 63)))
1743
- (lo_sign_bits Reg (madd $I64 lo_cls sign_eq sign_eq))
1744
- (maybe_lo Reg (with_flags_reg
1745
- (cmp64_imm hi_cls (u8_into_imm12 63))
1746
- (csel (Cond.Eq) lo_sign_bits (zero_reg)))))
1747
- (value_regs (add $I64 maybe_lo hi_cls) (imm $I64 (ImmExtend.Zero) 0))))
1748
-
1749
- (rule -1 (lower (has_type ty (cls x)))
1750
- (a64_cls ty x))
1751
-
1752
- ;;;; Rules for `bswap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1753
-
1754
- (rule (lower (has_type $I16 (bswap x)))
1755
- (a64_rev16 $I16 x))
1756
-
1757
- (rule (lower (has_type $I32 (bswap x)))
1758
- (a64_rev32 $I32 x))
1759
-
1760
- (rule (lower (has_type $I64 (bswap x)))
1761
- (a64_rev64 $I64 x))
1762
-
1763
- (rule (lower (has_type $I128 (bswap x)))
1764
- (value_regs
1765
- (a64_rev64 $I64 (value_regs_get x 1))
1766
- (a64_rev64 $I64 (value_regs_get x 0))))
1767
-
1768
- ;;;; Rules for `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1769
-
1770
- ;; Bmask tests the value against zero, and uses `csetm` to assert the result.
1771
- (rule (lower (has_type out_ty (bmask x @ (value_type in_ty))))
1772
- (lower_bmask out_ty in_ty x))
1773
-
1774
- ;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1775
-
1776
- ;; The implementation of `popcnt` for scalar types is done by moving the value
1777
- ;; into a vector register, using the `cnt` instruction, and then collating the
1778
- ;; result back into a normal register.
1779
- ;;
1780
- ;; The general sequence emitted here is
1781
- ;;
1782
- ;; fmov tmp, in_lo
1783
- ;; if ty == i128:
1784
- ;; mov tmp.d[1], in_hi
1785
- ;;
1786
- ;; cnt tmp.16b, tmp.16b / cnt tmp.8b, tmp.8b
1787
- ;; addv tmp, tmp.16b / addv tmp, tmp.8b / addp tmp.8b, tmp.8b, tmp.8b / (no instruction for 8-bit inputs)
1788
- ;;
1789
- ;; umov out_lo, tmp.b[0]
1790
- ;; if ty == i128:
1791
- ;; mov out_hi, 0
1792
-
1793
- (rule (lower (has_type $I8 (popcnt x)))
1794
- (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
1795
- (nbits Reg (vec_cnt tmp (VectorSize.Size8x8))))
1796
- (mov_from_vec nbits 0 (ScalarSize.Size8))))
1797
-
1798
- ;; Note that this uses `addp` instead of `addv` as it's usually cheaper.
1799
- (rule (lower (has_type $I16 (popcnt x)))
1800
- (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
1801
- (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
1802
- (added Reg (addp nbits nbits (VectorSize.Size8x8))))
1803
- (mov_from_vec added 0 (ScalarSize.Size8))))
1804
-
1805
- (rule (lower (has_type $I32 (popcnt x)))
1806
- (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
1807
- (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
1808
- (added Reg (addv nbits (VectorSize.Size8x8))))
1809
- (mov_from_vec added 0 (ScalarSize.Size8))))
1810
-
1811
- (rule (lower (has_type $I64 (popcnt x)))
1812
- (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size64)))
1813
- (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
1814
- (added Reg (addv nbits (VectorSize.Size8x8))))
1815
- (mov_from_vec added 0 (ScalarSize.Size8))))
1816
-
1817
- (rule (lower (has_type $I128 (popcnt x)))
1818
- (let ((val ValueRegs x)
1819
- (tmp_half Reg (mov_to_fpu (value_regs_get val 0) (ScalarSize.Size64)))
1820
- (tmp Reg (mov_to_vec tmp_half (value_regs_get val 1) 1 (VectorSize.Size64x2)))
1821
- (nbits Reg (vec_cnt tmp (VectorSize.Size8x16)))
1822
- (added Reg (addv nbits (VectorSize.Size8x16))))
1823
- (value_regs (mov_from_vec added 0 (ScalarSize.Size8)) (imm $I64 (ImmExtend.Zero) 0))))
1824
-
1825
- (rule (lower (has_type $I8X16 (popcnt x)))
1826
- (vec_cnt x (VectorSize.Size8x16)))
1827
-
1828
- ;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1829
-
1830
- (rule (lower (has_type ty (bitselect c x y)))
1831
- (if (ty_int_ref_scalar_64 ty))
1832
- (let ((tmp1 Reg (and_reg ty x c))
1833
- (tmp2 Reg (bic ty y c)))
1834
- (orr ty tmp1 tmp2)))
1835
-
1836
- (rule 1 (lower (has_type (ty_vec128 ty) (bitselect c x y)))
1837
- (bsl ty c x y))
1838
-
1839
- ;;;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1840
-
1841
- ;; T -> I{64,32,16,8}: We can simply pass through the value: values
1842
- ;; are always stored with high bits undefined, so we can just leave
1843
- ;; them be.
1844
- (rule (lower (has_type ty (ireduce src)))
1845
- (if (ty_int_ref_scalar_64 ty))
1846
- (value_regs_get src 0))
1847
-
1848
- ;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1849
-
1850
- (rule 4 (lower (has_type ty @ (multi_lane _ _) (fcmp (fcmp_zero_cond_not_eq cond) x y)))
1851
- (if (zero_value y))
1852
- (let ((rn Reg x)
1853
- (vec_size VectorSize (vector_size ty)))
1854
- (value_reg (not (fcmeq0 rn vec_size) vec_size))))
1855
-
1856
- (rule 3 (lower (has_type ty @ (multi_lane _ _) (fcmp (fcmp_zero_cond cond) x y)))
1857
- (if (zero_value y))
1858
- (let ((rn Reg x)
1859
- (vec_size VectorSize (vector_size ty)))
1860
- (value_reg (float_cmp_zero cond rn vec_size))))
1861
-
1862
- (rule 2 (lower (has_type ty @ (multi_lane _ _) (fcmp (fcmp_zero_cond_not_eq cond) x y)))
1863
- (if (zero_value x))
1864
- (let ((rn Reg y)
1865
- (vec_size VectorSize (vector_size ty)))
1866
- (value_reg (not (fcmeq0 rn vec_size) vec_size))))
1867
-
1868
- (rule 1 (lower (has_type ty @ (multi_lane _ _) (fcmp (fcmp_zero_cond cond) x y)))
1869
- (if (zero_value x))
1870
- (let ((rn Reg y)
1871
- (vec_size VectorSize (vector_size ty)))
1872
- (value_reg (float_cmp_zero_swap cond rn vec_size))))
1873
-
1874
- (rule 0 (lower (has_type out_ty
1875
- (fcmp cond x @ (value_type (ty_scalar_float in_ty)) y)))
1876
- (with_flags (fpu_cmp (scalar_size in_ty) x y)
1877
- (materialize_bool_result (fp_cond_code cond))))
1878
-
1879
- (rule -1 (lower (has_type out_ty (fcmp cond x @ (value_type in_ty) y)))
1880
- (if (ty_vector_float in_ty))
1881
- (vec_cmp x y in_ty (fp_cond_code cond)))
1882
-
1883
- ;;;; Rules for `icmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1884
-
1885
- (rule 3 (lower (has_type ty @ (multi_lane _ _) (icmp (icmp_zero_cond_not_eq cond) x y)))
1886
- (if (zero_value y))
1887
- (let ((rn Reg x)
1888
- (vec_size VectorSize (vector_size ty)))
1889
- (value_reg (not (cmeq0 rn vec_size) vec_size))))
1890
-
1891
- (rule 2 (lower (has_type ty @ (multi_lane _ _) (icmp (icmp_zero_cond cond) x y)))
1892
- (if (zero_value y))
1893
- (let ((rn Reg x)
1894
- (vec_size VectorSize (vector_size ty)))
1895
- (value_reg (int_cmp_zero cond rn vec_size))))
1896
-
1897
- (rule 1 (lower (has_type ty @ (multi_lane _ _) (icmp (icmp_zero_cond_not_eq cond) x y)))
1898
- (if (zero_value x))
1899
- (let ((rn Reg y)
1900
- (vec_size VectorSize (vector_size ty)))
1901
- (value_reg (not (cmeq0 rn vec_size) vec_size))))
1902
-
1903
- (rule 0 (lower (has_type ty @ (multi_lane _ _) (icmp (icmp_zero_cond cond) x y)))
1904
- (if (zero_value x))
1905
- (let ((rn Reg y)
1906
- (vec_size VectorSize (vector_size ty)))
1907
- (value_reg (int_cmp_zero_swap cond rn vec_size))))
1908
-
1909
- (rule -1 (lower (icmp cond x @ (value_type in_ty) y))
1910
- (lower_icmp_into_reg cond x y in_ty $I8))
1911
-
1912
- ;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1913
-
1914
- (rule (lower (trap trap_code))
1915
- (side_effect (udf trap_code)))
1916
-
1917
- ;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1918
-
1919
- (rule (lower (resumable_trap trap_code))
1920
- (side_effect (udf trap_code)))
1921
-
1922
- ;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1923
-
1924
- (rule (lower (has_type ty
1925
- (select (maybe_uextend (icmp cc
1926
- x @ (value_type in_ty)
1927
- y))
1928
- rn
1929
- rm)))
1930
- (let ((comparison FlagsAndCC (lower_icmp_into_flags cc x y in_ty)))
1931
- (lower_select (flags_and_cc_flags comparison)
1932
- (cond_code (flags_and_cc_cc comparison))
1933
- ty
1934
- rn
1935
- rm)))
1936
-
1937
- (rule (lower (has_type ty
1938
- (select (maybe_uextend (fcmp cc x @ (value_type in_ty) y))
1939
- rn
1940
- rm)))
1941
- (let ((cond Cond (fp_cond_code cc)))
1942
- (lower_select
1943
- (fpu_cmp (scalar_size in_ty) x y)
1944
- cond ty rn rm)))
1945
-
1946
- (rule -1 (lower (has_type ty (select rcond @ (value_type $I8) rn rm)))
1947
- (let ((rcond Reg rcond))
1948
- (lower_select
1949
- (tst_imm $I32 rcond (u64_into_imm_logic $I32 255))
1950
- (Cond.Ne) ty rn rm)))
1951
-
1952
- (rule -2 (lower (has_type ty (select rcond @ (value_type (fits_in_32 _)) rn rm)))
1953
- (let ((rcond Reg (put_in_reg_zext32 rcond)))
1954
- (lower_select
1955
- (cmp (OperandSize.Size32) rcond (zero_reg))
1956
- (Cond.Ne) ty rn rm)))
1957
-
1958
- (rule -3 (lower (has_type ty (select rcond @ (value_type (fits_in_64 _)) rn rm)))
1959
- (let ((rcond Reg (put_in_reg_zext64 rcond)))
1960
- (lower_select
1961
- (cmp (OperandSize.Size64) rcond (zero_reg))
1962
- (Cond.Ne) ty rn rm)))
1963
-
1964
- (rule -4 (lower (has_type ty (select rcond @ (value_type $I128) rn rm)))
1965
- (let ((c ValueRegs (put_in_regs rcond))
1966
- (c_lo Reg (value_regs_get c 0))
1967
- (c_hi Reg (value_regs_get c 1))
1968
- (rt Reg (orr $I64 c_lo c_hi)))
1969
- (lower_select
1970
- (cmp (OperandSize.Size64) rt (zero_reg))
1971
- (Cond.Ne) ty rn rm)))
1972
-
1973
- ;;;; Rules for `select_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1974
-
1975
- (rule (lower (has_type ty
1976
- (select_spectre_guard (maybe_uextend (icmp cc x @ (value_type in_ty) y))
1977
- if_true
1978
- if_false)))
1979
- (let ((comparison FlagsAndCC (lower_icmp_into_flags cc x y in_ty))
1980
- (dst ValueRegs (lower_select
1981
- (flags_and_cc_flags comparison)
1982
- (cond_code (flags_and_cc_cc comparison))
1983
- ty
1984
- if_true
1985
- if_false))
1986
- (_ InstOutput (side_effect (csdb))))
1987
- dst))
1988
-
1989
- (rule -1 (lower (has_type ty (select_spectre_guard rcond @ (value_type (fits_in_64 _)) rn rm)))
1990
- (let ((rcond Reg (put_in_reg_zext64 rcond)))
1991
- (lower_select
1992
- (cmp (OperandSize.Size64) rcond (zero_reg))
1993
- (Cond.Ne) ty rn rm)))
1994
-
1995
- (rule -2 (lower (has_type ty (select_spectre_guard rcond @ (value_type $I128) rn rm)))
1996
- (let ((c ValueRegs (put_in_regs rcond))
1997
- (c_lo Reg (value_regs_get c 0))
1998
- (c_hi Reg (value_regs_get c 1))
1999
- (rt Reg (orr $I64 c_lo c_hi)))
2000
- (lower_select
2001
- (cmp (OperandSize.Size64) rt (zero_reg))
2002
- (Cond.Ne) ty rn rm)))
2003
-
2004
- ;;;; Rules for `vconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2005
-
2006
- (rule (lower (has_type (ty_vec128 _) (vconst (u128_from_constant x))))
2007
- (constant_f128 x))
2008
-
2009
- (rule 1 (lower (has_type ty (vconst (u64_from_constant x))))
2010
- (if (ty_vec64 ty))
2011
- (constant_f64 x))
2012
-
2013
- ;;;; Rules for `splat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2014
-
2015
- (rule -1 (lower (has_type ty (splat x @ (value_type in_ty))))
2016
- (if (ty_int_ref_scalar_64 in_ty))
2017
- (vec_dup x (vector_size ty)))
2018
-
2019
- (rule -2 (lower (has_type ty (splat x @ (value_type (ty_scalar_float _)))))
2020
- (vec_dup_from_fpu x (vector_size ty) 0))
2021
-
2022
- (rule (lower (has_type ty (splat (f32const (u32_from_ieee32 n)))))
2023
- (splat_const n (vector_size ty)))
2024
-
2025
- (rule (lower (has_type ty (splat (f64const (u64_from_ieee64 n)))))
2026
- (splat_const n (vector_size ty)))
2027
-
2028
- (rule (lower (has_type ty (splat (iconst (u64_from_imm64 n)))))
2029
- (splat_const n (vector_size ty)))
2030
-
2031
- (rule (lower (has_type ty (splat (ireduce (iconst (u64_from_imm64 n))))))
2032
- (splat_const n (vector_size ty)))
2033
-
2034
- (rule (lower (has_type ty (splat x @ (load flags _ _))))
2035
- (if-let mem_op (is_sinkable_inst x))
2036
- (let ((addr Reg (sink_load_into_addr (lane_type ty) mem_op)))
2037
- (ld1r addr (vector_size ty) flags)))
2038
-
2039
- ;;;; Rules for `AtomicLoad` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2040
- (rule (lower (has_type (valid_atomic_transaction ty) (atomic_load flags addr)))
2041
- (load_acquire ty flags addr))
2042
-
2043
-
2044
- ;;;; Rules for `AtomicStore` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2045
- (rule (lower (atomic_store flags
2046
- src @ (value_type (valid_atomic_transaction ty))
2047
- addr))
2048
- (side_effect (store_release ty flags src addr)))
2049
-
2050
- ;;;; Rules for `AtomicRMW` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2051
-
2052
- (rule 1 (lower (and (use_lse)
2053
- (has_type (valid_atomic_transaction ty)
2054
- (atomic_rmw flags (AtomicRmwOp.Add) addr src))))
2055
- (lse_atomic_rmw (AtomicRMWOp.Add) addr src ty flags))
2056
- (rule 1 (lower (and (use_lse)
2057
- (has_type (valid_atomic_transaction ty)
2058
- (atomic_rmw flags (AtomicRmwOp.Xor) addr src))))
2059
- (lse_atomic_rmw (AtomicRMWOp.Eor) addr src ty flags))
2060
- (rule 1 (lower (and (use_lse)
2061
- (has_type (valid_atomic_transaction ty)
2062
- (atomic_rmw flags (AtomicRmwOp.Or) addr src))))
2063
- (lse_atomic_rmw (AtomicRMWOp.Set) addr src ty flags))
2064
- (rule 1 (lower (and (use_lse)
2065
- (has_type (valid_atomic_transaction ty)
2066
- (atomic_rmw flags (AtomicRmwOp.Smax) addr src))))
2067
- (lse_atomic_rmw (AtomicRMWOp.Smax) addr src ty flags))
2068
- (rule 1 (lower (and (use_lse)
2069
- (has_type (valid_atomic_transaction ty)
2070
- (atomic_rmw flags (AtomicRmwOp.Smin) addr src))))
2071
- (lse_atomic_rmw (AtomicRMWOp.Smin) addr src ty flags))
2072
- (rule 1 (lower (and (use_lse)
2073
- (has_type (valid_atomic_transaction ty)
2074
- (atomic_rmw flags (AtomicRmwOp.Umax) addr src))))
2075
- (lse_atomic_rmw (AtomicRMWOp.Umax) addr src ty flags))
2076
- (rule 1 (lower (and (use_lse)
2077
- (has_type (valid_atomic_transaction ty)
2078
- (atomic_rmw flags (AtomicRmwOp.Umin) addr src))))
2079
- (lse_atomic_rmw (AtomicRMWOp.Umin) addr src ty flags))
2080
- (rule 1 (lower (and (use_lse)
2081
- (has_type (valid_atomic_transaction ty)
2082
- (atomic_rmw flags (AtomicRmwOp.Sub) addr src))))
2083
- (lse_atomic_rmw (AtomicRMWOp.Add) addr (sub ty (zero_reg) src) ty flags))
2084
- (rule 1 (lower (and (use_lse)
2085
- (has_type (valid_atomic_transaction ty)
2086
- (atomic_rmw flags (AtomicRmwOp.And) addr src))))
2087
- (lse_atomic_rmw (AtomicRMWOp.Clr) addr (eon ty src (zero_reg)) ty flags))
2088
-
2089
-
2090
- (rule (lower (has_type (valid_atomic_transaction ty)
2091
- (atomic_rmw flags (AtomicRmwOp.Add) addr src)))
2092
- (atomic_rmw_loop (AtomicRMWLoopOp.Add) addr src ty flags))
2093
- (rule (lower (has_type (valid_atomic_transaction ty)
2094
- (atomic_rmw flags (AtomicRmwOp.Sub) addr src)))
2095
- (atomic_rmw_loop (AtomicRMWLoopOp.Sub) addr src ty flags))
2096
- (rule (lower (has_type (valid_atomic_transaction ty)
2097
- (atomic_rmw flags (AtomicRmwOp.And) addr src)))
2098
- (atomic_rmw_loop (AtomicRMWLoopOp.And) addr src ty flags))
2099
- (rule (lower (has_type (valid_atomic_transaction ty)
2100
- (atomic_rmw flags (AtomicRmwOp.Nand) addr src)))
2101
- (atomic_rmw_loop (AtomicRMWLoopOp.Nand) addr src ty flags))
2102
- (rule (lower (has_type (valid_atomic_transaction ty)
2103
- (atomic_rmw flags (AtomicRmwOp.Or) addr src)))
2104
- (atomic_rmw_loop (AtomicRMWLoopOp.Orr) addr src ty flags))
2105
- (rule (lower (has_type (valid_atomic_transaction ty)
2106
- (atomic_rmw flags (AtomicRmwOp.Xor) addr src)))
2107
- (atomic_rmw_loop (AtomicRMWLoopOp.Eor) addr src ty flags))
2108
- (rule (lower (has_type (valid_atomic_transaction ty)
2109
- (atomic_rmw flags (AtomicRmwOp.Smin) addr src)))
2110
- (atomic_rmw_loop (AtomicRMWLoopOp.Smin) addr src ty flags))
2111
- (rule (lower (has_type (valid_atomic_transaction ty)
2112
- (atomic_rmw flags (AtomicRmwOp.Smax) addr src)))
2113
- (atomic_rmw_loop (AtomicRMWLoopOp.Smax) addr src ty flags))
2114
- (rule (lower (has_type (valid_atomic_transaction ty)
2115
- (atomic_rmw flags (AtomicRmwOp.Umin) addr src)))
2116
- (atomic_rmw_loop (AtomicRMWLoopOp.Umin) addr src ty flags))
2117
- (rule (lower (has_type (valid_atomic_transaction ty)
2118
- (atomic_rmw flags (AtomicRmwOp.Umax) addr src)))
2119
- (atomic_rmw_loop (AtomicRMWLoopOp.Umax) addr src ty flags))
2120
- (rule (lower (has_type (valid_atomic_transaction ty)
2121
- (atomic_rmw flags (AtomicRmwOp.Xchg) addr src)))
2122
- (atomic_rmw_loop (AtomicRMWLoopOp.Xchg) addr src ty flags))
2123
-
2124
- ;;;; Rules for `AtomicCAS` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2125
- (rule 1 (lower (and (use_lse)
2126
- (has_type (valid_atomic_transaction ty)
2127
- (atomic_cas flags addr src1 src2))))
2128
- (lse_atomic_cas addr src1 src2 ty flags))
2129
-
2130
- (rule (lower (and (has_type (valid_atomic_transaction ty)
2131
- (atomic_cas flags addr src1 src2))))
2132
- (atomic_cas_loop addr src1 src2 ty flags))
2133
-
2134
- ;;;; Rules for 'fvdemote' ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2135
- (rule (lower (fvdemote x))
2136
- (fcvtn x (ScalarSize.Size32)))
2137
-
2138
-
2139
- ;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2140
- (rule 1 (lower (has_type (ty_vec128_int ty) (snarrow x y)))
2141
- (if (zero_value y))
2142
- (sqxtn x (lane_size ty)))
2143
-
2144
- (rule 2 (lower (has_type (ty_vec64_int ty) (snarrow x y)))
2145
- (let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
2146
- (sqxtn dst (lane_size ty))))
2147
-
2148
- (rule 0 (lower (has_type (ty_vec128_int ty) (snarrow x y)))
2149
- (let ((low_half Reg (sqxtn x (lane_size ty)))
2150
- (result Reg (sqxtn2 low_half y (lane_size ty))))
2151
- result))
2152
-
2153
-
2154
- ;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2155
- (rule 1 (lower (has_type (ty_vec128_int ty) (unarrow x y)))
2156
- (if (zero_value y))
2157
- (sqxtun x (lane_size ty)))
2158
-
2159
- (rule 2 (lower (has_type (ty_vec64_int ty) (unarrow x y)))
2160
- (let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
2161
- (sqxtun dst (lane_size ty))))
2162
-
2163
- (rule 0 (lower (has_type (ty_vec128_int ty) (unarrow x y)))
2164
- (let ((low_half Reg (sqxtun x (lane_size ty)))
2165
- (result Reg (sqxtun2 low_half y (lane_size ty))))
2166
- result))
2167
-
2168
-
2169
- ;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2170
-
2171
- (rule 1 (lower (has_type (ty_vec128_int ty) (uunarrow x y)))
2172
- (if (zero_value y))
2173
- (uqxtn x (lane_size ty)))
2174
-
2175
- (rule 2 (lower (has_type (ty_vec64_int ty) (uunarrow x y)))
2176
- (let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
2177
- (uqxtn dst (lane_size ty))))
2178
-
2179
- (rule 0 (lower (has_type (ty_vec128_int ty) (uunarrow x y)))
2180
- (let ((low_half Reg (uqxtn x (lane_size ty)))
2181
- (result Reg (uqxtn2 low_half y (lane_size ty))))
2182
- result))
2183
-
2184
- ;;;; Rules for `swiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2185
-
2186
- (rule (lower (has_type ty (swiden_low x)))
2187
- (vec_extend (VecExtendOp.Sxtl) x $false (lane_size ty)))
2188
-
2189
- ;;;; Rules for `swiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2190
-
2191
- (rule 1 (lower (has_type (ty_vec128 ty) (swiden_high x)))
2192
- (vec_extend (VecExtendOp.Sxtl) x $true (lane_size ty)))
2193
-
2194
- (rule (lower (has_type ty (swiden_high x)))
2195
- (if (ty_vec64 ty))
2196
- (let ((tmp Reg (fpu_move_from_vec x 1 (VectorSize.Size32x2))))
2197
- (vec_extend (VecExtendOp.Sxtl) tmp $false (lane_size ty))))
2198
-
2199
- ;;;; Rules for `uwiden_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2200
-
2201
- (rule (lower (has_type ty (uwiden_low x)))
2202
- (vec_extend (VecExtendOp.Uxtl) x $false (lane_size ty)))
2203
-
2204
- ;;;; Rules for `uwiden_high` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2205
-
2206
- (rule 1 (lower (has_type (ty_vec128 ty) (uwiden_high x)))
2207
- (vec_extend (VecExtendOp.Uxtl) x $true (lane_size ty)))
2208
-
2209
- (rule (lower (has_type ty (uwiden_high x)))
2210
- (if (ty_vec64 ty))
2211
- (let ((tmp Reg (fpu_move_from_vec x 1 (VectorSize.Size32x2))))
2212
- (vec_extend (VecExtendOp.Uxtl) tmp $false (lane_size ty))))
2213
-
2214
- ;;;; Rules for `Fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2215
-
2216
- (rule (lower (fence))
2217
- (side_effect (aarch64_fence)))
2218
-
2219
- ;;;; Rules for `IsNull` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2220
-
2221
- (rule (lower (is_null x @ (value_type ty)))
2222
- (with_flags (cmp_imm (operand_size ty) x (u8_into_imm12 0))
2223
- (materialize_bool_result (Cond.Eq))))
2224
-
2225
- ;;;; Rules for `IsInvalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2226
-
2227
- (rule (lower (is_invalid x @ (value_type ty)))
2228
- (with_flags (cmn_imm (operand_size ty) x (u8_into_imm12 1))
2229
- (materialize_bool_result (Cond.Eq))))
2230
-
2231
- ;;;; Rules for `Debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2232
-
2233
- (rule (lower (debugtrap))
2234
- (side_effect (brk)))
2235
-
2236
- ;;;; Rules for `func_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2237
-
2238
- (rule (lower (func_addr (func_ref_data _ extname _)))
2239
- (load_ext_name (box_external_name extname) 0))
2240
-
2241
- ;;;; Rules for `symbol_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2242
-
2243
- (rule (lower (symbol_value (symbol_value_data extname _ offset)))
2244
- (load_ext_name (box_external_name extname) offset))
2245
-
2246
- ;;; Rules for `get_{frame,stack}_pointer` and `get_return_address` ;;;;;;;;;;;;;
2247
-
2248
- (rule (lower (get_frame_pointer))
2249
- (aarch64_fp))
2250
-
2251
- (rule (lower (get_stack_pointer))
2252
- (aarch64_sp))
2253
-
2254
- (rule (lower (get_return_address))
2255
- (aarch64_link))
2256
-
2257
- ;;;; Rules for calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2258
-
2259
- (rule (lower (call (func_ref_data sig_ref extname dist) inputs))
2260
- (gen_call sig_ref extname dist inputs))
2261
-
2262
- (rule (lower (call_indirect sig_ref val inputs))
2263
- (gen_call_indirect sig_ref val inputs))
2264
-
2265
- ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2266
-
2267
- ;; N.B.: the Ret itself is generated by the ABI.
2268
- (rule (lower (return args))
2269
- (lower_return (range 0 (value_slice_len args)) args))
2270
-
2271
- ;;;; Rules for loads ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2272
-
2273
- (rule (lower
2274
- (has_type $I8 (load flags address offset)))
2275
- (aarch64_uload8 (amode $I8 address offset) flags))
2276
- (rule (lower
2277
- (has_type $I16 (load flags address offset)))
2278
- (aarch64_uload16 (amode $I16 address offset) flags))
2279
- (rule (lower
2280
- (has_type $I32 (load flags address offset)))
2281
- (aarch64_uload32 (amode $I32 address offset) flags))
2282
- (rule (lower
2283
- (has_type $I64 (load flags address offset)))
2284
- (aarch64_uload64 (amode $I64 address offset) flags))
2285
- (rule (lower
2286
- (has_type $R64 (load flags address offset)))
2287
- (aarch64_uload64 (amode $I64 address offset) flags))
2288
- (rule (lower
2289
- (has_type $F32 (load flags address offset)))
2290
- (aarch64_fpuload32 (amode $F32 address offset) flags))
2291
- (rule (lower
2292
- (has_type $F64 (load flags address offset)))
2293
- (aarch64_fpuload64 (amode $F64 address offset) flags))
2294
- (rule (lower
2295
- (has_type $I128 (load flags address offset)))
2296
- (aarch64_loadp64 (pair_amode address offset) flags))
2297
- (rule -1 (lower
2298
- (has_type (ty_vec64 _)
2299
- (load flags address offset)))
2300
- (aarch64_fpuload128 (amode $F64 address offset) flags))
2301
- (rule -3 (lower
2302
- (has_type (ty_vec128 _)
2303
- (load flags address offset)))
2304
- (aarch64_fpuload128 (amode $I8X16 address offset) flags))
2305
- (rule -2 (lower
2306
- (has_type (ty_dyn_vec64 _)
2307
- (load flags address offset)))
2308
- (aarch64_fpuload64 (amode $F64 address offset) flags))
2309
- (rule -4 (lower
2310
- (has_type (ty_dyn_vec128 _)
2311
- (load flags address offset)))
2312
- (aarch64_fpuload128 (amode $I8X16 address offset) flags))
2313
-
2314
- (rule (lower
2315
- (uload8 flags address offset))
2316
- (aarch64_uload8 (amode $I8 address offset) flags))
2317
- (rule (lower
2318
- (sload8 flags address offset))
2319
- (aarch64_sload8 (amode $I8 address offset) flags))
2320
- (rule (lower
2321
- (uload16 flags address offset))
2322
- (aarch64_uload16 (amode $I16 address offset) flags))
2323
- (rule (lower
2324
- (sload16 flags address offset))
2325
- (aarch64_sload16 (amode $I16 address offset) flags))
2326
- (rule (lower
2327
- (uload32 flags address offset))
2328
- (aarch64_uload32 (amode $I32 address offset) flags))
2329
- (rule (lower
2330
- (sload32 flags address offset))
2331
- (aarch64_sload32 (amode $I32 address offset) flags))
2332
-
2333
- (rule (lower
2334
- (sload8x8 flags address offset))
2335
- (vec_extend (VecExtendOp.Sxtl)
2336
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2337
- $false
2338
- (ScalarSize.Size16)))
2339
- (rule (lower
2340
- (uload8x8 flags address offset))
2341
- (vec_extend (VecExtendOp.Uxtl)
2342
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2343
- $false
2344
- (ScalarSize.Size16)))
2345
- (rule (lower
2346
- (sload16x4 flags address offset))
2347
- (vec_extend (VecExtendOp.Sxtl)
2348
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2349
- $false
2350
- (ScalarSize.Size32)))
2351
- (rule (lower
2352
- (uload16x4 flags address offset))
2353
- (vec_extend (VecExtendOp.Uxtl)
2354
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2355
- $false
2356
- (ScalarSize.Size32)))
2357
- (rule (lower
2358
- (sload32x2 flags address offset))
2359
- (vec_extend (VecExtendOp.Sxtl)
2360
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2361
- $false
2362
- (ScalarSize.Size64)))
2363
- (rule (lower
2364
- (uload32x2 flags address offset))
2365
- (vec_extend (VecExtendOp.Uxtl)
2366
- (aarch64_fpuload64 (amode $F64 address offset) flags)
2367
- $false
2368
- (ScalarSize.Size64)))
2369
-
2370
- ;;;; Rules for stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2371
-
2372
- (rule (lower
2373
- (store flags value @ (value_type $I8) address offset))
2374
- (side_effect
2375
- (aarch64_store8 (amode $I8 address offset) flags value)))
2376
- (rule (lower
2377
- (store flags value @ (value_type $I16) address offset))
2378
- (side_effect
2379
- (aarch64_store16 (amode $I16 address offset) flags value)))
2380
- (rule (lower
2381
- (store flags value @ (value_type $I32) address offset))
2382
- (side_effect
2383
- (aarch64_store32 (amode $I32 address offset) flags value)))
2384
- (rule (lower
2385
- (store flags value @ (value_type $I64) address offset))
2386
- (side_effect
2387
- (aarch64_store64 (amode $I64 address offset) flags value)))
2388
- (rule (lower
2389
- (store flags value @ (value_type $R64) address offset))
2390
- (side_effect
2391
- (aarch64_store64 (amode $I64 address offset) flags value)))
2392
-
2393
- (rule (lower
2394
- (istore8 flags value address offset))
2395
- (side_effect
2396
- (aarch64_store8 (amode $I8 address offset) flags value)))
2397
- (rule (lower
2398
- (istore16 flags value address offset))
2399
- (side_effect
2400
- (aarch64_store16 (amode $I16 address offset) flags value)))
2401
- (rule (lower
2402
- (istore32 flags value address offset))
2403
- (side_effect
2404
- (aarch64_store32 (amode $I32 address offset) flags value)))
2405
-
2406
- (rule (lower
2407
- (store flags value @ (value_type $F32) address offset))
2408
- (side_effect
2409
- (aarch64_fpustore32 (amode $F32 address offset) flags value)))
2410
- (rule (lower
2411
- (store flags value @ (value_type $F64) address offset))
2412
- (side_effect
2413
- (aarch64_fpustore64 (amode $F64 address offset) flags value)))
2414
-
2415
- (rule (lower
2416
- (store flags value @ (value_type $I128) address offset))
2417
- (side_effect
2418
- (aarch64_storep64 (pair_amode address offset) flags
2419
- (value_regs_get value 0)
2420
- (value_regs_get value 1))))
2421
-
2422
- (rule -1 (lower
2423
- (store flags value @ (value_type (ty_vec64 _)) address offset))
2424
- (side_effect
2425
- (aarch64_fpustore64 (amode $F64 address offset) flags value)))
2426
- (rule -3 (lower
2427
- (store flags value @ (value_type (ty_vec128 _)) address offset))
2428
- (side_effect
2429
- (aarch64_fpustore128 (amode $I8X16 address offset) flags value)))
2430
- (rule -2 (lower
2431
- (store flags value @ (value_type (ty_dyn_vec64 _)) address offset))
2432
- (side_effect
2433
- (aarch64_fpustore64 (amode $F64 address offset) flags value)))
2434
- (rule -4 (lower
2435
- (store flags value @ (value_type (ty_dyn_vec128 _)) address offset))
2436
- (side_effect
2437
- (aarch64_fpustore128 (amode $I8X16 address offset) flags value)))
2438
-
2439
- ;;; Rules for `{get,set}_pinned_reg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2440
-
2441
- (rule (lower (get_pinned_reg))
2442
- (mov_from_preg (preg_pinned)))
2443
-
2444
- (rule (lower (set_pinned_reg val))
2445
- (side_effect (write_pinned_reg val)))
2446
-
2447
- ;;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2448
-
2449
- ; SIMD&FP <=> SIMD&FP
2450
- (rule 5 (lower (has_type (ty_float_or_vec _) (bitcast _ x @ (value_type (ty_float_or_vec _)))))
2451
- x)
2452
-
2453
- ; GPR => SIMD&FP
2454
- (rule 4 (lower (has_type (ty_float_or_vec _) (bitcast _ x @ (value_type in_ty))))
2455
- (if (ty_int_ref_scalar_64 in_ty))
2456
- (mov_to_fpu x (scalar_size in_ty)))
2457
-
2458
- ; SIMD&FP => GPR
2459
- (rule 3 (lower (has_type out_ty (bitcast _ x @ (value_type (fits_in_64 (ty_float_or_vec _))))))
2460
- (if (ty_int_ref_scalar_64 out_ty))
2461
- (mov_from_vec x 0 (scalar_size out_ty)))
2462
-
2463
- ; GPR <=> GPR
2464
- (rule 2 (lower (has_type out_ty (bitcast _ x @ (value_type in_ty))))
2465
- (if (ty_int_ref_scalar_64 out_ty))
2466
- (if (ty_int_ref_scalar_64 in_ty))
2467
- x)
2468
- (rule 1 (lower (has_type $I128 (bitcast _ x @ (value_type $I128)))) x)
2469
-
2470
- ;;; Rules for `extractlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2471
-
2472
- ;; extractlane with lane 0 can pass through the value unchanged; upper
2473
- ;; bits are undefined when a narrower type is in a wider register.
2474
- (rule 2 (lower (has_type (ty_scalar_float _) (extractlane val (u8_from_uimm8 0))))
2475
- val)
2476
-
2477
- (rule 0 (lower (has_type (ty_int ty)
2478
- (extractlane val
2479
- (u8_from_uimm8 lane))))
2480
- (mov_from_vec val lane (scalar_size ty)))
2481
-
2482
- (rule 1 (lower (has_type (ty_scalar_float ty)
2483
- (extractlane val @ (value_type vty)
2484
- (u8_from_uimm8 lane))))
2485
- (fpu_move_from_vec val lane (vector_size vty)))
2486
-
2487
- ;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2488
-
2489
- (rule 1 (lower (insertlane vec @ (value_type vty)
2490
- val @ (value_type (ty_int _))
2491
- (u8_from_uimm8 lane)))
2492
- (mov_to_vec vec val lane (vector_size vty)))
2493
-
2494
- (rule (lower (insertlane vec @ (value_type vty)
2495
- val @ (value_type (ty_scalar_float _))
2496
- (u8_from_uimm8 lane)))
2497
- (mov_vec_elem vec val lane 0 (vector_size vty)))
2498
-
2499
- ;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2500
-
2501
- (rule (lower (stack_addr stack_slot offset))
2502
- (compute_stack_addr stack_slot offset))
2503
-
2504
- ;;; Rules for `vhigh_bits` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2505
-
2506
- ;; All three sequences use one integer temporary and two vector
2507
- ;; temporaries. The shift is done early so as to give the register
2508
- ;; allocator the possibility of using the same reg for `tmp_v1` and
2509
- ;; `src_v` in the case that this is the last use of `src_v`. See
2510
- ;; https://github.com/WebAssembly/simd/pull/201 for the background and
2511
- ;; derivation of these sequences. Alternative sequences are discussed
2512
- ;; in https://github.com/bytecodealliance/wasmtime/issues/2296,
2513
- ;; although they are not used here.
2514
-
2515
- (rule (lower (vhigh_bits vec @ (value_type $I8X16)))
2516
- (let (
2517
- ;; Replicate the MSB of each of the 16 byte lanes across
2518
- ;; the whole lane (sshr is an arithmetic right shift).
2519
- (shifted Reg (sshr_vec_imm vec 7 (VectorSize.Size8x16)))
2520
- ;; Bitwise-and with a mask
2521
- ;; `0x80402010_08040201_80402010_08040201` to get the bit
2522
- ;; in the proper location for each group of 8 lanes.
2523
- (anded Reg (and_vec shifted (constant_f128 0x80402010_08040201_80402010_08040201) (VectorSize.Size8x16)))
2524
- ;; Produce a version of `anded` with upper 8 lanes and
2525
- ;; lower 8 lanes swapped.
2526
- (anded_swapped Reg (vec_extract anded anded 8))
2527
- ;; Zip together the two; with the above this produces the lane permutation:
2528
- ;; 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0
2529
- (zipped Reg (zip1 anded anded_swapped (VectorSize.Size8x16)))
2530
- ;; Add 16-bit lanes together ("add across vector"), so we
2531
- ;; get, in the low 16 bits, 15+14+...+8 in the high byte
2532
- ;; and 7+6+...+0 in the low byte. This effectively puts
2533
- ;; the 16 MSBs together, giving our results.
2534
- ;;
2535
- ;; N.B.: `Size16x8` is not a typo!
2536
- (result Reg (addv zipped (VectorSize.Size16x8))))
2537
- (mov_from_vec result 0 (ScalarSize.Size16))))
2538
-
2539
- (rule (lower (vhigh_bits vec @ (value_type $I16X8)))
2540
- (let (
2541
- ;; Replicate the MSB of each of the 8 16-bit lanes across
2542
- ;; the whole lane (sshr is an arithmetic right shift).
2543
- (shifted Reg (sshr_vec_imm vec 15 (VectorSize.Size16x8)))
2544
- ;; Bitwise-and with a mask
2545
- ;; `0x0080_0040_0020_0010_0008_0004_0002_0001` to get the
2546
- ;; bit in the proper location for each group of 4 lanes.
2547
- (anded Reg (and_vec shifted (constant_f128 0x0080_0040_0020_0010_0008_0004_0002_0001) (VectorSize.Size16x8)))
2548
- ;; Add lanes together to get the 8 MSBs in the low byte.
2549
- (result Reg (addv anded (VectorSize.Size16x8))))
2550
- (mov_from_vec result 0 (ScalarSize.Size16))))
2551
-
2552
- (rule (lower (vhigh_bits vec @ (value_type $I32X4)))
2553
- (let (
2554
- ;; Replicate the MSB of each of the 4 32-bit lanes across
2555
- ;; the whole lane (sshr is an arithmetic right shift).
2556
- (shifted Reg (sshr_vec_imm vec 31 (VectorSize.Size32x4)))
2557
- ;; Bitwise-and with a mask
2558
- ;; `0x00000008_00000004_00000002_00000001` to get the bit
2559
- ;; in the proper location for each group of 4 lanes.
2560
- (anded Reg (and_vec shifted (constant_f128 0x00000008_00000004_00000002_00000001) (VectorSize.Size32x4)))
2561
- ;; Add lanes together to get the 4 MSBs in the low byte.
2562
- (result Reg (addv anded (VectorSize.Size32x4))))
2563
- (mov_from_vec result 0 (ScalarSize.Size32))))
2564
-
2565
- (rule (lower (vhigh_bits vec @ (value_type $I64X2)))
2566
- (let (
2567
- ;; Grab the MSB out of each of the lanes, right-shift to
2568
- ;; LSB, and add with a left-shift of upper lane's MSB back
2569
- ;; to bit 1. the whole lane (sshr is an arithmetic right
2570
- ;; shift).
2571
- (upper_msb Reg (mov_from_vec vec 1 (ScalarSize.Size64)))
2572
- (lower_msb Reg (mov_from_vec vec 0 (ScalarSize.Size64)))
2573
- (upper_msb Reg (lsr_imm $I64 upper_msb (imm_shift_from_u8 63)))
2574
- (lower_msb Reg (lsr_imm $I64 lower_msb (imm_shift_from_u8 63))))
2575
- (add_shift $I64 lower_msb upper_msb (lshl_from_u64 $I64 1))))
2576
-
2577
- ;;; Rules for `uadd_overflow_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2578
-
2579
- (rule (lower (has_type (fits_in_64 ty) (uadd_overflow_trap a b tc)))
2580
- (trap_if_overflow (add_with_flags_paired ty a b) tc))
2581
-
2582
- ;;;; Helpers for `*_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2583
-
2584
- ;; put a narrow value into a register and sign-/zero-extend depending on the ArgumentExtension
2585
- (decl put_in_reg_ext32 (Value ArgumentExtension) Reg)
2586
- (rule (put_in_reg_ext32 val (ArgumentExtension.Sext))
2587
- (put_in_reg_sext32 val))
2588
- (rule (put_in_reg_ext32 val (ArgumentExtension.Uext))
2589
- (put_in_reg_zext32 val))
2590
-
2591
- ;; For narrow values emit a normal op with both arguments zero/sign extended.
2592
- ;; Then check if the output is the same as itself zero/sign extended from the narrower width.
2593
- (decl overflow_op_small (Type Value Value ArgumentExtension ALUOp) InstOutput)
2594
- (rule (overflow_op_small ty a b arg_ext alu_op)
2595
- (let ((extend ExtendOp (lower_extend_op ty arg_ext))
2596
-
2597
- ;; Instead of emitting two `{u,s}xt{b,h}` we do one as an instruction and
2598
- ;; the other as an extend operation in the alu_op.
2599
- ;;
2600
- ;; uxtb a_ext, a
2601
- ;; alu_op out, a_ext, b, {u,s}xtb
2602
- ;; cmp out, out, {u,s}xtb
2603
- ;; cset out_of, ne
2604
- (a_ext Reg (put_in_reg_ext32 a arg_ext))
2605
- (out Reg (alu_rrr_extend alu_op ty a_ext b extend))
2606
- (out_of Reg (with_flags_reg
2607
- (cmp_extend (OperandSize.Size32) out out extend)
2608
- (cset (Cond.Ne)))))
2609
- (output_pair
2610
- (value_reg out)
2611
- (value_reg out_of))))
2612
-
2613
- ;; For register sized op's just emit a op+cset, without further masking.
2614
- ;;
2615
- ;; op out, a, b
2616
- ;; cset out_of, cond
2617
- ;;
2618
- ;; conds expected:
2619
- ;; Hs: Carry set, unsigned overflow; Vs: Signed Over-/Underflow;
2620
- ;; Lo: Carry clear, meaning no unsigned overflow.
2621
- ;; (this is because subtraction is implemented as an add with the two's complement value on aarch64, meaning there is a sub-overflow if the add does not overflow)
2622
- (decl overflow_op_normal (Type Value Value ALUOp Cond) InstOutput)
2623
- (rule (overflow_op_normal ty a b alu_op cond)
2624
- (let ((out ValueRegs
2625
- (with_flags
2626
- (alu_rrr_with_flags_paired ty a b alu_op)
2627
- (cset_paired cond))))
2628
- (output_pair
2629
- (value_regs_get out 0)
2630
- (value_regs_get out 1))))
2631
-
2632
- ;; For 128bit integers emit, for example, add+adcs+cset
2633
- (decl overflow_op_128 (Value Value ALUOp ALUOp Cond) InstOutput)
2634
- (rule (overflow_op_128 x y alu_op1 alu_op2 cond)
2635
- (let
2636
- ;; Get the high/low registers for `x`.
2637
- ((x_regs ValueRegs x)
2638
- (x_lo Reg (value_regs_get x_regs 0))
2639
- (x_hi Reg (value_regs_get x_regs 1))
2640
-
2641
- ;; Get the high/low registers for `y`.
2642
- (y_regs ValueRegs y)
2643
- (y_lo Reg (value_regs_get y_regs 0))
2644
- (y_hi Reg (value_regs_get y_regs 1)))
2645
- ;; cannot use the with_flags helper here but it should be fine right now
2646
- (let
2647
- ((lo_inst ProducesFlags (alu_rrr_with_flags_paired $I64 x_lo y_lo alu_op1))
2648
- (hi_inst ConsumesAndProducesFlags (alu_rrr_with_flags_chained $I64 x_hi y_hi alu_op2))
2649
- (of_inst ConsumesFlags (cset_paired cond))
2650
-
2651
- (result MultiReg (with_flags_chained lo_inst hi_inst of_inst)))
2652
- (multi_reg_to_pair_and_single result)))
2653
- )
2654
-
2655
- ;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2656
-
2657
- ;; For values smaller than a register, we do a normal `add` with both arguments
2658
- ;; zero extended. We then check if the output is the same as itself zero extended.
2659
- (rule 1 (lower (has_type (fits_in_16 ty) (uadd_overflow a b)))
2660
- (overflow_op_small ty a b (ArgumentExtension.Uext) (ALUOp.Add)))
2661
-
2662
- ;; For register sized add's we just emit a adds+cset, without further masking.
2663
- (rule 2 (lower (has_type (ty_32_or_64 ty) (uadd_overflow a b)))
2664
- (overflow_op_normal ty a b (ALUOp.AddS) (Cond.Hs)))
2665
-
2666
- ;; For 128bit integers we emit add+adcs+cset
2667
- (rule 0 (lower (has_type $I128 (uadd_overflow x y)))
2668
- (overflow_op_128 x y (ALUOp.AddS) (ALUOp.AdcS) (Cond.Hs)))
2669
-
2670
- ;;;; Rules for `sadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2671
-
2672
- ;; sxt{b,h} a_ext, a
2673
- ;; add out, a_ext, b, sxt{b,h}
2674
- ;; cmp out, out, sxt{b,h}
2675
- ;; cset of, ne
2676
- (rule 1 (lower (has_type (fits_in_16 ty) (sadd_overflow a b)))
2677
- (overflow_op_small ty a b (ArgumentExtension.Sext) (ALUOp.Add)))
2678
-
2679
- ;; adds a, b
2680
- ;; cset of, vs
2681
- (rule 2 (lower (has_type (ty_32_or_64 ty) (sadd_overflow a b)))
2682
- (overflow_op_normal ty a b (ALUOp.AddS) (Cond.Vs)))
2683
-
2684
- ;; adds x_lo, y_lo
2685
- ;; addcs x_hi, y_hi
2686
- ;; cset of, vs
2687
- (rule 0 (lower (has_type $I128 (sadd_overflow x y)))
2688
- (overflow_op_128 x y (ALUOp.AddS) (ALUOp.AdcS) (Cond.Vs)))
2689
-
2690
- ;;;; Rules for `usub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2691
-
2692
- ;; uxt{b,h} a_ext, a
2693
- ;; sub out, a_ext, b, ext{b,h}
2694
- ;; cmp out, out, uxt{b,h}
2695
- ;; cset of, ne
2696
- (rule 1 (lower (has_type (fits_in_16 ty) (usub_overflow a b)))
2697
- (overflow_op_small ty a b (ArgumentExtension.Uext) (ALUOp.Sub)))
2698
-
2699
- ;; subs a, b
2700
- ;; cset of, lo
2701
- (rule 2 (lower (has_type (ty_32_or_64 ty) (usub_overflow a b)))
2702
- (overflow_op_normal ty a b (ALUOp.SubS) (Cond.Lo)))
2703
-
2704
- ;; subs x_lo, y_lo
2705
- ;; sbcs x_hi, y_hi
2706
- ;; cset of, lo
2707
- (rule 0 (lower (has_type $I128 (usub_overflow x y)))
2708
- (overflow_op_128 x y (ALUOp.SubS) (ALUOp.SbcS) (Cond.Lo)))
2709
-
2710
- ;;;; Rules for `ssub_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2711
-
2712
- ;; sxt{b,h} a_ext, a
2713
- ;; sub out, a_ext, b, sxt{b,h}
2714
- ;; cmp out, out, sxt{b,h}
2715
- ;; cset of, ne
2716
- (rule 1 (lower (has_type (fits_in_16 ty) (ssub_overflow a b)))
2717
- (overflow_op_small ty a b (ArgumentExtension.Sext) (ALUOp.Sub)))
2718
-
2719
- ;; subs a, b
2720
- ;; cset of, vs
2721
- (rule 2 (lower (has_type (ty_32_or_64 ty) (ssub_overflow a b)))
2722
- (overflow_op_normal ty a b (ALUOp.SubS) (Cond.Vs)))
2723
-
2724
- ;; subs x_lo, y_lo
2725
- ;; sbcs x_hi, y_hi
2726
- ;; cset of, vs
2727
- (rule 0 (lower (has_type $I128 (ssub_overflow x y)))
2728
- (overflow_op_128 x y (ALUOp.SubS) (ALUOp.SbcS) (Cond.Vs)))
2729
-
2730
- ;;;; Rules for `umul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2731
-
2732
- ;; uxt{b,h} a_ext, a
2733
- ;; uxt{b,h} b_ext, b
2734
- ;; mul out, a_ext, b_ext
2735
- ;; cmp out, out, uxt{b,h}
2736
- ;; cset of, ne
2737
- (rule 1 (lower (has_type (fits_in_16 ty) (umul_overflow a b)))
2738
- (let ((extend ExtendOp (lower_extend_op ty (ArgumentExtension.Uext)))
2739
-
2740
- (a_uext Reg (put_in_reg_zext32 a))
2741
- (b_uext Reg (put_in_reg_zext32 b))
2742
- (out Reg (madd ty a_uext b_uext (zero_reg)))
2743
- (out_of Reg (with_flags_reg
2744
- (cmp_extend (OperandSize.Size32) out out extend)
2745
- (cset (Cond.Ne)))))
2746
- (output_pair
2747
- (value_reg out)
2748
- (value_reg out_of))))
2749
-
2750
- ;; umull out, a, b
2751
- ;; cmp out, out, uxtw
2752
- ;; cset of, ne
2753
- (rule 2 (lower (has_type $I32 (umul_overflow a b)))
2754
- (let (
2755
- (out Reg (umaddl a b (zero_reg)))
2756
- (out_of Reg (with_flags_reg
2757
- (cmp_extend (OperandSize.Size64) out out (ExtendOp.UXTW))
2758
- (cset (Cond.Ne)))))
2759
- (output_pair
2760
- (value_reg out)
2761
- (value_reg out_of))))
2762
-
2763
- ;; mul out, a, b
2764
- ;; umulh tmp, a, b
2765
- ;; cmp tmp, #0
2766
- ;; cset of, ne
2767
- (rule 2 (lower (has_type $I64 (umul_overflow a b)))
2768
- (let (
2769
- (out Reg (madd $I64 a b (zero_reg)))
2770
- (tmp Reg (umulh $I64 a b))
2771
- (out_of Reg (with_flags_reg
2772
- (cmp64_imm tmp (u8_into_imm12 0))
2773
- (cset (Cond.Ne)))))
2774
- (output_pair
2775
- (value_reg out)
2776
- (value_reg out_of))))
2777
-
2778
- ;;;; Rules for `smul_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2779
-
2780
- ;; sxt{b,h} a_ext, a
2781
- ;; sxt{b,h} b_ext, b
2782
- ;; mul out, a_ext, b_ext
2783
- ;; cmp out, out, sxt{b,h}
2784
- ;; cset of, ne
2785
- (rule 1 (lower (has_type (fits_in_16 ty) (smul_overflow a b)))
2786
- (let ((extend ExtendOp (lower_extend_op ty (ArgumentExtension.Sext)))
2787
-
2788
- (a_sext Reg (put_in_reg_sext32 a))
2789
- (b_sext Reg (put_in_reg_sext32 b))
2790
- (out Reg (madd ty a_sext b_sext (zero_reg)))
2791
- (out_of Reg (with_flags_reg
2792
- (cmp_extend (OperandSize.Size32) out out extend)
2793
- (cset (Cond.Ne)))))
2794
- (output_pair
2795
- (value_reg out)
2796
- (value_reg out_of))))
2797
-
2798
- ;; smull out, a, b
2799
- ;; cmp out, out, sxtw
2800
- ;; cset of, ne
2801
- (rule 2 (lower (has_type $I32 (smul_overflow a b)))
2802
- (let (
2803
- (out Reg (smaddl a b (zero_reg)))
2804
- (out_of Reg (with_flags_reg
2805
- (cmp_extend (OperandSize.Size64) out out (ExtendOp.SXTW))
2806
- (cset (Cond.Ne)))))
2807
- (output_pair
2808
- (value_reg out)
2809
- (value_reg out_of))))
2810
-
2811
- ;; mul out, a, b
2812
- ;; smulh tmp, a, b
2813
- ;; cmp tmp, out, ASR #63
2814
- ;; cset of, ne
2815
- (rule 2 (lower (has_type $I64 (smul_overflow a b)))
2816
- (let (
2817
- (out Reg (madd $I64 a b (zero_reg)))
2818
- (tmp Reg (smulh $I64 a b))
2819
- (out_of Reg (with_flags_reg
2820
- (cmp_rr_shift_asr (OperandSize.Size64) tmp out 63)
2821
- (cset (Cond.Ne)))))
2822
- (output_pair
2823
- (value_reg out)
2824
- (value_reg out_of))))
2825
-
2826
- ;;; Rules for `tls_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2827
-
2828
- (rule (lower (has_type (tls_model (TlsModel.ElfGd)) (tls_value (symbol_value_data name _ _))))
2829
- (elf_tls_get_addr name))
2830
-
2831
- (rule (lower (has_type (tls_model (TlsModel.Macho)) (tls_value (symbol_value_data name _ _))))
2832
- (macho_tls_get_addr name))
2833
-
2834
- ;;; Rules for `fcvt_low_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2835
-
2836
- (rule (lower (has_type $F64X2 (fcvt_low_from_sint val)))
2837
- (let ((extended Reg (vec_extend (VecExtendOp.Sxtl) val $false (ScalarSize.Size64)))
2838
- (converted Reg (vec_misc (VecMisc2.Scvtf) extended (VectorSize.Size64x2))))
2839
- converted))
2840
-
2841
- ;;; Rules for `fvpromote_low` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2842
-
2843
- (rule (lower (fvpromote_low val))
2844
- (vec_rr_long (VecRRLongOp.Fcvtl32) val $false))
2845
-
2846
- ;;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2847
-
2848
- ;; `brif` following `icmp`
2849
- (rule (lower_branch (brif (maybe_uextend (icmp cc x @ (value_type ty) y)) _ _) targets)
2850
- (let ((comparison FlagsAndCC (lower_icmp_into_flags cc x y ty))
2851
- (cond Cond (cond_code (flags_and_cc_cc comparison)))
2852
- (taken BranchTarget (branch_target targets 0))
2853
- (not_taken BranchTarget (branch_target targets 1)))
2854
- (emit_side_effect
2855
- (with_flags_side_effect (flags_and_cc_flags comparison)
2856
- (cond_br taken
2857
- not_taken
2858
- (cond_br_cond cond))))))
2859
-
2860
- ;; `brif` following `fcmp`
2861
- (rule (lower_branch (brif (maybe_uextend (fcmp cc x @ (value_type (ty_scalar_float ty)) y)) _ _) targets)
2862
- (let ((cond Cond (fp_cond_code cc))
2863
- (taken BranchTarget (branch_target targets 0))
2864
- (not_taken BranchTarget (branch_target targets 1)))
2865
- (emit_side_effect
2866
- (with_flags_side_effect (fpu_cmp (scalar_size ty) x y)
2867
- (cond_br taken not_taken
2868
- (cond_br_cond cond))))))
2869
-
2870
- ;; standard `brif`
2871
- (rule -1 (lower_branch (brif c @ (value_type $I128) _ _) targets)
2872
- (let ((flags ProducesFlags (flags_to_producesflags c))
2873
- (c ValueRegs (put_in_regs c))
2874
- (c_lo Reg (value_regs_get c 0))
2875
- (c_hi Reg (value_regs_get c 1))
2876
- (rt Reg (orr $I64 c_lo c_hi))
2877
- (taken BranchTarget (branch_target targets 0))
2878
- (not_taken BranchTarget (branch_target targets 1)))
2879
- (emit_side_effect
2880
- (with_flags_side_effect flags
2881
- (cond_br taken not_taken (cond_br_not_zero rt))))))
2882
- (rule -2 (lower_branch (brif c @ (value_type ty) _ _) targets)
2883
- (if (ty_int_ref_scalar_64 ty))
2884
- (let ((flags ProducesFlags (flags_to_producesflags c))
2885
- (rt Reg (put_in_reg_zext64 c))
2886
- (taken BranchTarget (branch_target targets 0))
2887
- (not_taken BranchTarget (branch_target targets 1)))
2888
- (emit_side_effect
2889
- (with_flags_side_effect flags
2890
- (cond_br taken not_taken (cond_br_not_zero rt))))))
2891
-
2892
- ;;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2893
-
2894
- (rule (lower_branch (jump _) targets)
2895
- (emit_side_effect (aarch64_jump (branch_target targets 0))))
2896
-
2897
- ;;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2898
-
2899
- ;; `targets` contains the default target with the list of branch targets
2900
- ;; concatenated.
2901
- (rule (lower_branch (br_table idx _) targets)
2902
- (let ((jt_size u32 (targets_jt_size targets))
2903
- (_ InstOutput (side_effect
2904
- (emit_island (targets_jt_space targets))))
2905
- (ridx Reg (put_in_reg_zext32 idx)))
2906
- (br_table_impl (u32_as_u64 jt_size) ridx targets)))