wasmtime 9.0.4 → 10.0.1
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- checksums.yaml +4 -4
- data/Cargo.lock +184 -101
- data/ext/Cargo.toml +6 -6
- data/ext/build.rs +2 -2
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.97.1/Cargo.toml +31 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/Cargo.toml +158 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/benches/x64-evex-encoding.rs +52 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/ir/trapcode.rs +144 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/abi.rs +1294 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit.rs +3684 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/emit_tests.rs +7895 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/imms.rs +1210 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst/mod.rs +2966 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/inst.isle +4037 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower/isle.rs +816 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/lower.isle +2906 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/aarch64/mod.rs +238 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/mod.rs +424 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/abi.rs +825 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/args.rs +1812 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit.rs +3008 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/emit_tests.rs +2338 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/encode.rs +262 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/imms.rs +250 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/mod.rs +1963 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/regs.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/unwind/systemv.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst/vector.rs +669 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst.isle +2915 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/inst_vector.isle +760 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower/isle.rs +553 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/lower.isle +1409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/riscv64/mod.rs +216 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/abi.rs +957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit.rs +3707 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/emit_tests.rs +13409 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst/mod.rs +3426 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/inst.isle +5046 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/lower.isle +3991 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/s390x/mod.rs +213 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/abi.rs +985 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/evex.rs +749 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/rex.rs +588 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/encoding/vex.rs +492 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/args.rs +2193 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit.rs +4090 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/emit_tests.rs +5674 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst/mod.rs +2667 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/inst.isle +5104 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower/isle.rs +1148 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.isle +4481 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/lower.rs +328 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isa/x64/mod.rs +251 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/isle_prelude.rs +862 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/abi.rs +2455 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/buffer.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/compile.rs +92 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/isle.rs +827 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/lower.rs +1388 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/mod.rs +549 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/reg.rs +537 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/machinst/vcode.rs +1580 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude.isle +578 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/prelude_lower.isle +1012 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/settings.rs +600 -0
- data/ext/cargo-vendor/cranelift-codegen-0.97.1/src/verifier/mod.rs +1884 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/Cargo.toml +23 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/isa/x86.rs +444 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.97.1/src/shared/settings.rs +348 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.97.1/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/chaos.rs +125 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/lib.rs +45 -0
- data/ext/cargo-vendor/cranelift-control-0.97.1/src/zero_sized.rs +53 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-entity-0.97.1/src/list.rs +955 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.97.1/Cargo.toml +53 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.97.1/Cargo.toml +37 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/Cargo.toml +38 -0
- data/ext/cargo-vendor/cranelift-native-0.97.1/src/lib.rs +215 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/Cargo.toml +85 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/code_translator.rs +3538 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/dummy.rs +924 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/environ/spec.rs +834 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/func_translator.rs +440 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/sections_translator.rs +417 -0
- data/ext/cargo-vendor/cranelift-wasm-0.97.1/src/translation_utils.rs +99 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/CONTRIBUTING.md +48 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/COPYRIGHT +17 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Cargo.toml +84 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/Ideas.md +106 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-APACHE +202 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/LICENSE-WHATWG +26 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/README.md +827 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/ci/miri.sh +14 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Big5.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-JP.txt +12 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/EUC-KR.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/GBK.txt +16 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/IBM866.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-2022-JP.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-10.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-13.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-14.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-15.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-16.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-2.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-3.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-4.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-5.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-6.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-7.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8-I.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/ISO-8859-8.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-R.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/KOI8-U.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/Shift_JIS.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16BE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-16LE.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/UTF-8.txt +5 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/gb18030.txt +9 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/macintosh.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/replacement.txt +10 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1250.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1251.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1252.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1253.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1254.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1255.txt +8 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1256.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1257.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-1258.txt +11 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/windows-874.txt +7 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-mac-cyrillic.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/doc/x-user-defined.txt +6 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/generate-encoding-data.py +2008 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/rustfmt.toml +1 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/ascii.rs +1546 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/big5.rs +427 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/data.rs +114378 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_jp.rs +469 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/euc_kr.rs +442 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/gb18030.rs +767 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/handles.rs +1969 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/iso_2022_jp.rs +1068 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/lib.rs +6133 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/macros.rs +1622 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/mem.rs +3354 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/replacement.rs +104 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/shift_jis.rs +426 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/simd_funcs.rs +453 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/single_byte.rs +714 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_in_ref.txt +19787 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/big5_out_ref.txt +14601 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_in_ref.txt +23945 -0
- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/euc_kr_out.txt +17053 -0
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- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_in.txt +23945 -0
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- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/gb18030_out.txt +23944 -0
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- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/iso_2022_jp_out.txt +7404 -0
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- data/ext/cargo-vendor/encoding_rs-0.8.32/src/test_data/shift_jis_in.txt +11285 -0
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|
-
use crate::ir::ExternalName;
|
7
|
-
use crate::ir::MemFlags;
|
8
|
-
use crate::isa;
|
9
|
-
|
10
|
-
use crate::isa::riscv64::{inst::EmitState, inst::*};
|
11
|
-
use crate::isa::CallConv;
|
12
|
-
use crate::machinst::*;
|
13
|
-
|
14
|
-
use crate::ir::types::I8;
|
15
|
-
use crate::ir::LibCall;
|
16
|
-
use crate::ir::Signature;
|
17
|
-
use crate::isa::riscv64::settings::Flags as RiscvFlags;
|
18
|
-
use crate::isa::unwind::UnwindInst;
|
19
|
-
use crate::settings;
|
20
|
-
use crate::CodegenError;
|
21
|
-
use crate::CodegenResult;
|
22
|
-
use alloc::boxed::Box;
|
23
|
-
use alloc::vec::Vec;
|
24
|
-
use regalloc2::PRegSet;
|
25
|
-
use regs::x_reg;
|
26
|
-
|
27
|
-
use smallvec::{smallvec, SmallVec};
|
28
|
-
|
29
|
-
/// Support for the Riscv64 ABI from the callee side (within a function body).
|
30
|
-
pub(crate) type Riscv64Callee = Callee<Riscv64MachineDeps>;
|
31
|
-
|
32
|
-
/// Support for the Riscv64 ABI from the caller side (at a callsite).
|
33
|
-
pub(crate) type Riscv64ABICaller = Caller<Riscv64MachineDeps>;
|
34
|
-
|
35
|
-
/// This is the limit for the size of argument and return-value areas on the
|
36
|
-
/// stack. We place a reasonable limit here to avoid integer overflow issues
|
37
|
-
/// with 32-bit arithmetic: for now, 128 MB.
|
38
|
-
static STACK_ARG_RET_SIZE_LIMIT: u32 = 128 * 1024 * 1024;
|
39
|
-
|
40
|
-
/// Riscv64-specific ABI behavior. This struct just serves as an implementation
|
41
|
-
/// point for the trait; it is never actually instantiated.
|
42
|
-
pub struct Riscv64MachineDeps;
|
43
|
-
|
44
|
-
impl IsaFlags for RiscvFlags {}
|
45
|
-
|
46
|
-
impl ABIMachineSpec for Riscv64MachineDeps {
|
47
|
-
type I = Inst;
|
48
|
-
type F = RiscvFlags;
|
49
|
-
|
50
|
-
fn word_bits() -> u32 {
|
51
|
-
64
|
52
|
-
}
|
53
|
-
|
54
|
-
/// Return required stack alignment in bytes.
|
55
|
-
fn stack_align(_call_conv: isa::CallConv) -> u32 {
|
56
|
-
16
|
57
|
-
}
|
58
|
-
|
59
|
-
fn compute_arg_locs<'a, I>(
|
60
|
-
call_conv: isa::CallConv,
|
61
|
-
_flags: &settings::Flags,
|
62
|
-
params: I,
|
63
|
-
args_or_rets: ArgsOrRets,
|
64
|
-
add_ret_area_ptr: bool,
|
65
|
-
mut args: ArgsAccumulator<'_>,
|
66
|
-
) -> CodegenResult<(u32, Option<usize>)>
|
67
|
-
where
|
68
|
-
I: IntoIterator<Item = &'a ir::AbiParam>,
|
69
|
-
{
|
70
|
-
// All registers that can be used as parameters or rets.
|
71
|
-
// both start and end are included.
|
72
|
-
let (x_start, x_end, f_start, f_end) = if args_or_rets == ArgsOrRets::Args {
|
73
|
-
(10, 17, 10, 17)
|
74
|
-
} else {
|
75
|
-
let end = if call_conv.extends_wasmtime() { 10 } else { 11 };
|
76
|
-
(10, end, 10, end)
|
77
|
-
};
|
78
|
-
let mut next_x_reg = x_start;
|
79
|
-
let mut next_f_reg = f_start;
|
80
|
-
// Stack space.
|
81
|
-
let mut next_stack: u32 = 0;
|
82
|
-
let mut return_one_register_used = false;
|
83
|
-
|
84
|
-
for param in params {
|
85
|
-
if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
|
86
|
-
let offset = next_stack;
|
87
|
-
assert!(size % 8 == 0, "StructArgument size is not properly aligned");
|
88
|
-
next_stack += size;
|
89
|
-
args.push(ABIArg::StructArg {
|
90
|
-
pointer: None,
|
91
|
-
offset: offset as i64,
|
92
|
-
size: size as u64,
|
93
|
-
purpose: param.purpose,
|
94
|
-
});
|
95
|
-
continue;
|
96
|
-
}
|
97
|
-
|
98
|
-
// Find regclass(es) of the register(s) used to store a value of this type.
|
99
|
-
let (rcs, reg_tys) = Inst::rc_for_type(param.value_type)?;
|
100
|
-
let mut slots = ABIArgSlotVec::new();
|
101
|
-
for (rc, reg_ty) in rcs.iter().zip(reg_tys.iter()) {
|
102
|
-
let next_reg =
|
103
|
-
if (next_x_reg <= x_end) && *rc == RegClass::Int && !return_one_register_used {
|
104
|
-
let x = Some(x_reg(next_x_reg));
|
105
|
-
if args_or_rets == ArgsOrRets::Rets && call_conv.extends_wasmtime() {
|
106
|
-
return_one_register_used = true;
|
107
|
-
}
|
108
|
-
next_x_reg += 1;
|
109
|
-
x
|
110
|
-
} else if (next_f_reg <= f_end)
|
111
|
-
&& *rc == RegClass::Float
|
112
|
-
&& !return_one_register_used
|
113
|
-
{
|
114
|
-
let x = Some(f_reg(next_f_reg));
|
115
|
-
if args_or_rets == ArgsOrRets::Rets && call_conv.extends_wasmtime() {
|
116
|
-
return_one_register_used = true;
|
117
|
-
}
|
118
|
-
next_f_reg += 1;
|
119
|
-
x
|
120
|
-
} else {
|
121
|
-
None
|
122
|
-
};
|
123
|
-
if let Some(reg) = next_reg {
|
124
|
-
slots.push(ABIArgSlot::Reg {
|
125
|
-
reg: reg.to_real_reg().unwrap(),
|
126
|
-
ty: *reg_ty,
|
127
|
-
extension: param.extension,
|
128
|
-
});
|
129
|
-
} else {
|
130
|
-
// Compute size. For the wasmtime ABI it differs from native
|
131
|
-
// ABIs in how multiple values are returned, so we take a
|
132
|
-
// leaf out of arm64's book by not rounding everything up to
|
133
|
-
// 8 bytes. For all ABI arguments, and other ABI returns,
|
134
|
-
// though, each slot takes a minimum of 8 bytes.
|
135
|
-
//
|
136
|
-
// Note that in all cases 16-byte stack alignment happens
|
137
|
-
// separately after all args.
|
138
|
-
let size = reg_ty.bits() / 8;
|
139
|
-
let size = if args_or_rets == ArgsOrRets::Rets && call_conv.extends_wasmtime() {
|
140
|
-
size
|
141
|
-
} else {
|
142
|
-
std::cmp::max(size, 8)
|
143
|
-
};
|
144
|
-
// Align.
|
145
|
-
debug_assert!(size.is_power_of_two());
|
146
|
-
next_stack = align_to(next_stack, size);
|
147
|
-
slots.push(ABIArgSlot::Stack {
|
148
|
-
offset: next_stack as i64,
|
149
|
-
ty: *reg_ty,
|
150
|
-
extension: param.extension,
|
151
|
-
});
|
152
|
-
next_stack += size;
|
153
|
-
}
|
154
|
-
}
|
155
|
-
args.push(ABIArg::Slots {
|
156
|
-
slots,
|
157
|
-
purpose: param.purpose,
|
158
|
-
});
|
159
|
-
}
|
160
|
-
let pos: Option<usize> = if add_ret_area_ptr {
|
161
|
-
assert!(ArgsOrRets::Args == args_or_rets);
|
162
|
-
if next_x_reg <= x_end {
|
163
|
-
let arg = ABIArg::reg(
|
164
|
-
x_reg(next_x_reg).to_real_reg().unwrap(),
|
165
|
-
I64,
|
166
|
-
ir::ArgumentExtension::None,
|
167
|
-
ir::ArgumentPurpose::Normal,
|
168
|
-
);
|
169
|
-
args.push(arg);
|
170
|
-
} else {
|
171
|
-
let arg = ABIArg::stack(
|
172
|
-
next_stack as i64,
|
173
|
-
I64,
|
174
|
-
ir::ArgumentExtension::None,
|
175
|
-
ir::ArgumentPurpose::Normal,
|
176
|
-
);
|
177
|
-
args.push(arg);
|
178
|
-
next_stack += 8;
|
179
|
-
}
|
180
|
-
Some(args.args().len() - 1)
|
181
|
-
} else {
|
182
|
-
None
|
183
|
-
};
|
184
|
-
next_stack = align_to(next_stack, Self::stack_align(call_conv));
|
185
|
-
// To avoid overflow issues, limit the arg/return size to something
|
186
|
-
// reasonable -- here, 128 MB.
|
187
|
-
if next_stack > STACK_ARG_RET_SIZE_LIMIT {
|
188
|
-
return Err(CodegenError::ImplLimitExceeded);
|
189
|
-
}
|
190
|
-
CodegenResult::Ok((next_stack, pos))
|
191
|
-
}
|
192
|
-
|
193
|
-
fn fp_to_arg_offset(_call_conv: isa::CallConv, _flags: &settings::Flags) -> i64 {
|
194
|
-
// lr fp.
|
195
|
-
16
|
196
|
-
}
|
197
|
-
|
198
|
-
fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
|
199
|
-
Inst::gen_load(into_reg, mem.into(), ty, MemFlags::trusted())
|
200
|
-
}
|
201
|
-
|
202
|
-
fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
|
203
|
-
Inst::gen_store(mem.into(), from_reg, ty, MemFlags::trusted())
|
204
|
-
}
|
205
|
-
|
206
|
-
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
|
207
|
-
Inst::gen_move(to_reg, from_reg, ty)
|
208
|
-
}
|
209
|
-
|
210
|
-
fn gen_extend(
|
211
|
-
to_reg: Writable<Reg>,
|
212
|
-
from_reg: Reg,
|
213
|
-
signed: bool,
|
214
|
-
from_bits: u8,
|
215
|
-
to_bits: u8,
|
216
|
-
) -> Inst {
|
217
|
-
assert!(from_bits < to_bits);
|
218
|
-
Inst::Extend {
|
219
|
-
rd: to_reg,
|
220
|
-
rn: from_reg,
|
221
|
-
signed,
|
222
|
-
from_bits,
|
223
|
-
to_bits,
|
224
|
-
}
|
225
|
-
}
|
226
|
-
|
227
|
-
fn get_ext_mode(
|
228
|
-
_call_conv: isa::CallConv,
|
229
|
-
specified: ir::ArgumentExtension,
|
230
|
-
) -> ir::ArgumentExtension {
|
231
|
-
specified
|
232
|
-
}
|
233
|
-
|
234
|
-
fn gen_args(_isa_flags: &crate::isa::riscv64::settings::Flags, args: Vec<ArgPair>) -> Inst {
|
235
|
-
Inst::Args { args }
|
236
|
-
}
|
237
|
-
|
238
|
-
fn gen_ret(_setup_frame: bool, _isa_flags: &Self::F, rets: Vec<RetPair>) -> Inst {
|
239
|
-
Inst::Ret { rets }
|
240
|
-
}
|
241
|
-
|
242
|
-
fn get_stacklimit_reg() -> Reg {
|
243
|
-
spilltmp_reg()
|
244
|
-
}
|
245
|
-
|
246
|
-
fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Inst> {
|
247
|
-
let mut insts = SmallInstVec::new();
|
248
|
-
if let Some(imm12) = Imm12::maybe_from_u64(imm as u64) {
|
249
|
-
insts.push(Inst::AluRRImm12 {
|
250
|
-
alu_op: AluOPRRI::Andi,
|
251
|
-
rd: into_reg,
|
252
|
-
rs: from_reg,
|
253
|
-
imm12,
|
254
|
-
});
|
255
|
-
} else {
|
256
|
-
insts.extend(Inst::load_constant_u32(
|
257
|
-
writable_spilltmp_reg2(),
|
258
|
-
imm as u64,
|
259
|
-
&mut |_| writable_spilltmp_reg2(),
|
260
|
-
));
|
261
|
-
insts.push(Inst::AluRRR {
|
262
|
-
alu_op: AluOPRRR::Add,
|
263
|
-
rd: into_reg,
|
264
|
-
rs1: spilltmp_reg2(),
|
265
|
-
rs2: from_reg,
|
266
|
-
});
|
267
|
-
}
|
268
|
-
insts
|
269
|
-
}
|
270
|
-
|
271
|
-
fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
|
272
|
-
let mut insts = SmallVec::new();
|
273
|
-
insts.push(Inst::TrapIfC {
|
274
|
-
cc: IntCC::UnsignedLessThan,
|
275
|
-
rs1: stack_reg(),
|
276
|
-
rs2: limit_reg,
|
277
|
-
trap_code: ir::TrapCode::StackOverflow,
|
278
|
-
});
|
279
|
-
insts
|
280
|
-
}
|
281
|
-
|
282
|
-
fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
|
283
|
-
Inst::LoadAddr {
|
284
|
-
rd: into_reg,
|
285
|
-
mem: mem.into(),
|
286
|
-
}
|
287
|
-
}
|
288
|
-
|
289
|
-
fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
|
290
|
-
let mem = AMode::RegOffset(base, offset as i64, ty);
|
291
|
-
Inst::gen_load(into_reg, mem, ty, MemFlags::trusted())
|
292
|
-
}
|
293
|
-
|
294
|
-
fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
|
295
|
-
let mem = AMode::RegOffset(base, offset as i64, ty);
|
296
|
-
Inst::gen_store(mem, from_reg, ty, MemFlags::trusted())
|
297
|
-
}
|
298
|
-
|
299
|
-
fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Inst> {
|
300
|
-
let mut insts = SmallVec::new();
|
301
|
-
if amount == 0 {
|
302
|
-
return insts;
|
303
|
-
}
|
304
|
-
insts.push(Inst::AjustSp {
|
305
|
-
amount: amount as i64,
|
306
|
-
});
|
307
|
-
insts
|
308
|
-
}
|
309
|
-
|
310
|
-
fn gen_nominal_sp_adj(offset: i32) -> Inst {
|
311
|
-
Inst::VirtualSPOffsetAdj {
|
312
|
-
amount: offset as i64,
|
313
|
-
}
|
314
|
-
}
|
315
|
-
|
316
|
-
fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Inst> {
|
317
|
-
// add sp,sp,-16 ;; alloc stack space for fp.
|
318
|
-
// sd ra,8(sp) ;; save ra.
|
319
|
-
// sd fp,0(sp) ;; store old fp.
|
320
|
-
// mv fp,sp ;; set fp to sp.
|
321
|
-
let mut insts = SmallVec::new();
|
322
|
-
insts.push(Inst::AjustSp { amount: -16 });
|
323
|
-
insts.push(Self::gen_store_stack(
|
324
|
-
StackAMode::SPOffset(8, I64),
|
325
|
-
link_reg(),
|
326
|
-
I64,
|
327
|
-
));
|
328
|
-
insts.push(Self::gen_store_stack(
|
329
|
-
StackAMode::SPOffset(0, I64),
|
330
|
-
fp_reg(),
|
331
|
-
I64,
|
332
|
-
));
|
333
|
-
if flags.unwind_info() {
|
334
|
-
insts.push(Inst::Unwind {
|
335
|
-
inst: UnwindInst::PushFrameRegs {
|
336
|
-
offset_upward_to_caller_sp: 16, // FP, LR
|
337
|
-
},
|
338
|
-
});
|
339
|
-
}
|
340
|
-
insts.push(Inst::Mov {
|
341
|
-
rd: writable_fp_reg(),
|
342
|
-
rm: stack_reg(),
|
343
|
-
ty: I64,
|
344
|
-
});
|
345
|
-
insts
|
346
|
-
}
|
347
|
-
/// reverse of gen_prologue_frame_setup.
|
348
|
-
fn gen_epilogue_frame_restore(_: &settings::Flags) -> SmallInstVec<Inst> {
|
349
|
-
let mut insts = SmallVec::new();
|
350
|
-
insts.push(Self::gen_load_stack(
|
351
|
-
StackAMode::SPOffset(8, I64),
|
352
|
-
writable_link_reg(),
|
353
|
-
I64,
|
354
|
-
));
|
355
|
-
insts.push(Self::gen_load_stack(
|
356
|
-
StackAMode::SPOffset(0, I64),
|
357
|
-
writable_fp_reg(),
|
358
|
-
I64,
|
359
|
-
));
|
360
|
-
insts.push(Inst::AjustSp { amount: 16 });
|
361
|
-
insts
|
362
|
-
}
|
363
|
-
|
364
|
-
fn gen_probestack(insts: &mut SmallInstVec<Self::I>, frame_size: u32) {
|
365
|
-
insts.extend(Inst::load_constant_u32(
|
366
|
-
writable_a0(),
|
367
|
-
frame_size as u64,
|
368
|
-
&mut |_| writable_a0(),
|
369
|
-
));
|
370
|
-
insts.push(Inst::Call {
|
371
|
-
info: Box::new(CallInfo {
|
372
|
-
dest: ExternalName::LibCall(LibCall::Probestack),
|
373
|
-
uses: smallvec![CallArgPair {
|
374
|
-
vreg: a0(),
|
375
|
-
preg: a0(),
|
376
|
-
}],
|
377
|
-
defs: smallvec![],
|
378
|
-
clobbers: PRegSet::empty(),
|
379
|
-
opcode: Opcode::Call,
|
380
|
-
callee_callconv: CallConv::SystemV,
|
381
|
-
caller_callconv: CallConv::SystemV,
|
382
|
-
}),
|
383
|
-
});
|
384
|
-
}
|
385
|
-
// Returns stack bytes used as well as instructions. Does not adjust
|
386
|
-
// nominal SP offset; abi_impl generic code will do that.
|
387
|
-
fn gen_clobber_save(
|
388
|
-
_call_conv: isa::CallConv,
|
389
|
-
setup_frame: bool,
|
390
|
-
flags: &settings::Flags,
|
391
|
-
clobbered_callee_saves: &[Writable<RealReg>],
|
392
|
-
fixed_frame_storage_size: u32,
|
393
|
-
_outgoing_args_size: u32,
|
394
|
-
) -> (u64, SmallVec<[Inst; 16]>) {
|
395
|
-
let mut insts = SmallVec::new();
|
396
|
-
let clobbered_size = compute_clobber_size(&clobbered_callee_saves);
|
397
|
-
// Adjust the stack pointer downward for clobbers and the function fixed
|
398
|
-
// frame (spillslots and storage slots).
|
399
|
-
let stack_size = fixed_frame_storage_size + clobbered_size;
|
400
|
-
if flags.unwind_info() && setup_frame {
|
401
|
-
// The *unwind* frame (but not the actual frame) starts at the
|
402
|
-
// clobbers, just below the saved FP/LR pair.
|
403
|
-
insts.push(Inst::Unwind {
|
404
|
-
inst: UnwindInst::DefineNewFrame {
|
405
|
-
offset_downward_to_clobbers: clobbered_size,
|
406
|
-
offset_upward_to_caller_sp: 16, // FP, LR
|
407
|
-
},
|
408
|
-
});
|
409
|
-
}
|
410
|
-
// Store each clobbered register in order at offsets from SP,
|
411
|
-
// placing them above the fixed frame slots.
|
412
|
-
if stack_size > 0 {
|
413
|
-
// since we use fp, we didn't need use UnwindInst::StackAlloc.
|
414
|
-
let mut cur_offset = 8;
|
415
|
-
for reg in clobbered_callee_saves {
|
416
|
-
let r_reg = reg.to_reg();
|
417
|
-
let ty = match r_reg.class() {
|
418
|
-
regalloc2::RegClass::Int => I64,
|
419
|
-
regalloc2::RegClass::Float => F64,
|
420
|
-
RegClass::Vector => unreachable!(),
|
421
|
-
};
|
422
|
-
if flags.unwind_info() {
|
423
|
-
insts.push(Inst::Unwind {
|
424
|
-
inst: UnwindInst::SaveReg {
|
425
|
-
clobber_offset: clobbered_size - cur_offset,
|
426
|
-
reg: r_reg,
|
427
|
-
},
|
428
|
-
});
|
429
|
-
}
|
430
|
-
insts.push(Self::gen_store_stack(
|
431
|
-
StackAMode::SPOffset(-(cur_offset as i64), ty),
|
432
|
-
real_reg_to_reg(reg.to_reg()),
|
433
|
-
ty,
|
434
|
-
));
|
435
|
-
cur_offset += 8
|
436
|
-
}
|
437
|
-
insts.push(Inst::AjustSp {
|
438
|
-
amount: -(stack_size as i64),
|
439
|
-
});
|
440
|
-
}
|
441
|
-
(clobbered_size as u64, insts)
|
442
|
-
}
|
443
|
-
|
444
|
-
fn gen_clobber_restore(
|
445
|
-
call_conv: isa::CallConv,
|
446
|
-
sig: &Signature,
|
447
|
-
_flags: &settings::Flags,
|
448
|
-
clobbers: &[Writable<RealReg>],
|
449
|
-
fixed_frame_storage_size: u32,
|
450
|
-
_outgoing_args_size: u32,
|
451
|
-
) -> SmallVec<[Inst; 16]> {
|
452
|
-
let mut insts = SmallVec::new();
|
453
|
-
let clobbered_callee_saves =
|
454
|
-
Self::get_clobbered_callee_saves(call_conv, _flags, sig, clobbers);
|
455
|
-
let stack_size = fixed_frame_storage_size + compute_clobber_size(&clobbered_callee_saves);
|
456
|
-
if stack_size > 0 {
|
457
|
-
insts.push(Inst::AjustSp {
|
458
|
-
amount: stack_size as i64,
|
459
|
-
});
|
460
|
-
}
|
461
|
-
let mut cur_offset = 8;
|
462
|
-
for reg in &clobbered_callee_saves {
|
463
|
-
let rreg = reg.to_reg();
|
464
|
-
let ty = match rreg.class() {
|
465
|
-
regalloc2::RegClass::Int => I64,
|
466
|
-
regalloc2::RegClass::Float => F64,
|
467
|
-
RegClass::Vector => unreachable!(),
|
468
|
-
};
|
469
|
-
insts.push(Self::gen_load_stack(
|
470
|
-
StackAMode::SPOffset(-cur_offset, ty),
|
471
|
-
Writable::from_reg(real_reg_to_reg(reg.to_reg())),
|
472
|
-
ty,
|
473
|
-
));
|
474
|
-
cur_offset += 8
|
475
|
-
}
|
476
|
-
insts
|
477
|
-
}
|
478
|
-
|
479
|
-
fn gen_call(
|
480
|
-
dest: &CallDest,
|
481
|
-
uses: CallArgList,
|
482
|
-
defs: CallRetList,
|
483
|
-
clobbers: PRegSet,
|
484
|
-
opcode: ir::Opcode,
|
485
|
-
tmp: Writable<Reg>,
|
486
|
-
callee_conv: isa::CallConv,
|
487
|
-
caller_conv: isa::CallConv,
|
488
|
-
) -> SmallVec<[Self::I; 2]> {
|
489
|
-
let mut insts = SmallVec::new();
|
490
|
-
match &dest {
|
491
|
-
&CallDest::ExtName(ref name, RelocDistance::Near) => insts.push(Inst::Call {
|
492
|
-
info: Box::new(CallInfo {
|
493
|
-
dest: name.clone(),
|
494
|
-
uses,
|
495
|
-
defs,
|
496
|
-
clobbers,
|
497
|
-
opcode,
|
498
|
-
caller_callconv: caller_conv,
|
499
|
-
callee_callconv: callee_conv,
|
500
|
-
}),
|
501
|
-
}),
|
502
|
-
&CallDest::ExtName(ref name, RelocDistance::Far) => {
|
503
|
-
insts.push(Inst::LoadExtName {
|
504
|
-
rd: tmp,
|
505
|
-
name: Box::new(name.clone()),
|
506
|
-
offset: 0,
|
507
|
-
});
|
508
|
-
insts.push(Inst::CallInd {
|
509
|
-
info: Box::new(CallIndInfo {
|
510
|
-
rn: tmp.to_reg(),
|
511
|
-
uses,
|
512
|
-
defs,
|
513
|
-
clobbers,
|
514
|
-
opcode,
|
515
|
-
caller_callconv: caller_conv,
|
516
|
-
callee_callconv: callee_conv,
|
517
|
-
}),
|
518
|
-
});
|
519
|
-
}
|
520
|
-
&CallDest::Reg(reg) => insts.push(Inst::CallInd {
|
521
|
-
info: Box::new(CallIndInfo {
|
522
|
-
rn: *reg,
|
523
|
-
uses,
|
524
|
-
defs,
|
525
|
-
clobbers,
|
526
|
-
opcode,
|
527
|
-
caller_callconv: caller_conv,
|
528
|
-
callee_callconv: callee_conv,
|
529
|
-
}),
|
530
|
-
}),
|
531
|
-
}
|
532
|
-
insts
|
533
|
-
}
|
534
|
-
|
535
|
-
fn gen_memcpy<F: FnMut(Type) -> Writable<Reg>>(
|
536
|
-
call_conv: isa::CallConv,
|
537
|
-
dst: Reg,
|
538
|
-
src: Reg,
|
539
|
-
size: usize,
|
540
|
-
mut alloc_tmp: F,
|
541
|
-
) -> SmallVec<[Self::I; 8]> {
|
542
|
-
let mut insts = SmallVec::new();
|
543
|
-
let arg0 = Writable::from_reg(x_reg(10));
|
544
|
-
let arg1 = Writable::from_reg(x_reg(11));
|
545
|
-
let arg2 = Writable::from_reg(x_reg(12));
|
546
|
-
let tmp = alloc_tmp(Self::word_type());
|
547
|
-
insts.extend(Inst::load_constant_u64(tmp, size as u64, &mut alloc_tmp).into_iter());
|
548
|
-
insts.push(Inst::Call {
|
549
|
-
info: Box::new(CallInfo {
|
550
|
-
dest: ExternalName::LibCall(LibCall::Memcpy),
|
551
|
-
uses: smallvec![
|
552
|
-
CallArgPair {
|
553
|
-
vreg: dst,
|
554
|
-
preg: arg0.to_reg()
|
555
|
-
},
|
556
|
-
CallArgPair {
|
557
|
-
vreg: src,
|
558
|
-
preg: arg1.to_reg()
|
559
|
-
},
|
560
|
-
CallArgPair {
|
561
|
-
vreg: tmp.to_reg(),
|
562
|
-
preg: arg2.to_reg()
|
563
|
-
}
|
564
|
-
],
|
565
|
-
defs: smallvec![],
|
566
|
-
clobbers: Self::get_regs_clobbered_by_call(call_conv),
|
567
|
-
opcode: Opcode::Call,
|
568
|
-
caller_callconv: call_conv,
|
569
|
-
callee_callconv: call_conv,
|
570
|
-
}),
|
571
|
-
});
|
572
|
-
insts
|
573
|
-
}
|
574
|
-
|
575
|
-
fn get_number_of_spillslots_for_value(rc: RegClass, _target_vector_bytes: u32) -> u32 {
|
576
|
-
// We allocate in terms of 8-byte slots.
|
577
|
-
match rc {
|
578
|
-
RegClass::Int => 1,
|
579
|
-
RegClass::Float => 1,
|
580
|
-
RegClass::Vector => unreachable!(),
|
581
|
-
}
|
582
|
-
}
|
583
|
-
|
584
|
-
/// Get the current virtual-SP offset from an instruction-emission state.
|
585
|
-
fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
|
586
|
-
s.virtual_sp_offset
|
587
|
-
}
|
588
|
-
|
589
|
-
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
|
590
|
-
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
|
591
|
-
s.nominal_sp_to_fp
|
592
|
-
}
|
593
|
-
|
594
|
-
fn get_regs_clobbered_by_call(_call_conv_of_callee: isa::CallConv) -> PRegSet {
|
595
|
-
let mut v = PRegSet::empty();
|
596
|
-
for (k, need_save) in CALLER_SAVE_X_REG.iter().enumerate() {
|
597
|
-
if !*need_save {
|
598
|
-
continue;
|
599
|
-
}
|
600
|
-
v.add(px_reg(k));
|
601
|
-
}
|
602
|
-
for (k, need_save) in CALLER_SAVE_F_REG.iter().enumerate() {
|
603
|
-
if !*need_save {
|
604
|
-
continue;
|
605
|
-
}
|
606
|
-
v.add(pf_reg(k));
|
607
|
-
}
|
608
|
-
v
|
609
|
-
}
|
610
|
-
|
611
|
-
fn get_clobbered_callee_saves(
|
612
|
-
call_conv: isa::CallConv,
|
613
|
-
_flags: &settings::Flags,
|
614
|
-
_sig: &Signature,
|
615
|
-
regs: &[Writable<RealReg>],
|
616
|
-
) -> Vec<Writable<RealReg>> {
|
617
|
-
let mut regs: Vec<Writable<RealReg>> = regs
|
618
|
-
.iter()
|
619
|
-
.cloned()
|
620
|
-
.filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
|
621
|
-
.collect();
|
622
|
-
|
623
|
-
regs.sort();
|
624
|
-
regs
|
625
|
-
}
|
626
|
-
|
627
|
-
fn is_frame_setup_needed(
|
628
|
-
is_leaf: bool,
|
629
|
-
stack_args_size: u32,
|
630
|
-
num_clobbered_callee_saves: usize,
|
631
|
-
fixed_frame_storage_size: u32,
|
632
|
-
) -> bool {
|
633
|
-
!is_leaf
|
634
|
-
// The function arguments that are passed on the stack are addressed
|
635
|
-
// relative to the Frame Pointer.
|
636
|
-
|| stack_args_size > 0
|
637
|
-
|| num_clobbered_callee_saves > 0
|
638
|
-
|| fixed_frame_storage_size > 0
|
639
|
-
}
|
640
|
-
|
641
|
-
fn gen_inline_probestack(insts: &mut SmallInstVec<Self::I>, frame_size: u32, guard_size: u32) {
|
642
|
-
// Unroll at most n consecutive probes, before falling back to using a loop
|
643
|
-
const PROBE_MAX_UNROLL: u32 = 3;
|
644
|
-
// Number of probes that we need to perform
|
645
|
-
let probe_count = align_to(frame_size, guard_size) / guard_size;
|
646
|
-
|
647
|
-
if probe_count <= PROBE_MAX_UNROLL {
|
648
|
-
Self::gen_probestack_unroll(insts, guard_size, probe_count)
|
649
|
-
} else {
|
650
|
-
Self::gen_probestack_loop(insts, guard_size, probe_count)
|
651
|
-
}
|
652
|
-
}
|
653
|
-
}
|
654
|
-
|
655
|
-
const CALLER_SAVE_X_REG: [bool; 32] = [
|
656
|
-
false, true, false, false, false, true, true, true, // 0-7
|
657
|
-
false, false, true, true, true, true, true, true, // 8-15
|
658
|
-
true, true, false, false, false, false, false, false, // 16-23
|
659
|
-
false, false, false, false, true, true, true, true, // 24-31
|
660
|
-
];
|
661
|
-
const CALLEE_SAVE_X_REG: [bool; 32] = [
|
662
|
-
false, false, true, false, false, false, false, false, // 0-7
|
663
|
-
true, true, false, false, false, false, false, false, // 8-15
|
664
|
-
false, false, true, true, true, true, true, true, // 16-23
|
665
|
-
true, true, true, true, false, false, false, false, // 24-31
|
666
|
-
];
|
667
|
-
const CALLER_SAVE_F_REG: [bool; 32] = [
|
668
|
-
true, true, true, true, true, true, true, true, // 0-7
|
669
|
-
false, true, true, true, true, true, true, true, // 8-15
|
670
|
-
true, true, false, false, false, false, false, false, // 16-23
|
671
|
-
false, false, false, false, true, true, true, true, // 24-31
|
672
|
-
];
|
673
|
-
const CALLEE_SAVE_F_REG: [bool; 32] = [
|
674
|
-
false, false, false, false, false, false, false, false, // 0-7
|
675
|
-
true, false, false, false, false, false, false, false, // 8-15
|
676
|
-
false, false, true, true, true, true, true, true, // 16-23
|
677
|
-
true, true, true, true, false, false, false, false, // 24-31
|
678
|
-
];
|
679
|
-
|
680
|
-
/// This should be the registers that must be saved by callee.
|
681
|
-
#[inline]
|
682
|
-
fn is_reg_saved_in_prologue(_conv: CallConv, reg: RealReg) -> bool {
|
683
|
-
if reg.class() == RegClass::Int {
|
684
|
-
CALLEE_SAVE_X_REG[reg.hw_enc() as usize]
|
685
|
-
} else {
|
686
|
-
CALLEE_SAVE_F_REG[reg.hw_enc() as usize]
|
687
|
-
}
|
688
|
-
}
|
689
|
-
|
690
|
-
fn compute_clobber_size(clobbers: &[Writable<RealReg>]) -> u32 {
|
691
|
-
let mut clobbered_size = 0;
|
692
|
-
for reg in clobbers {
|
693
|
-
match reg.to_reg().class() {
|
694
|
-
RegClass::Int => {
|
695
|
-
clobbered_size += 8;
|
696
|
-
}
|
697
|
-
RegClass::Float => {
|
698
|
-
clobbered_size += 8;
|
699
|
-
}
|
700
|
-
RegClass::Vector => unreachable!(),
|
701
|
-
}
|
702
|
-
}
|
703
|
-
align_to(clobbered_size, 16)
|
704
|
-
}
|
705
|
-
|
706
|
-
impl Riscv64MachineDeps {
|
707
|
-
fn gen_probestack_unroll(insts: &mut SmallInstVec<Inst>, guard_size: u32, probe_count: u32) {
|
708
|
-
insts.reserve(probe_count as usize);
|
709
|
-
for i in 0..probe_count {
|
710
|
-
let offset = (guard_size * (i + 1)) as i64;
|
711
|
-
insts.push(Self::gen_store_stack(
|
712
|
-
StackAMode::SPOffset(-offset, I8),
|
713
|
-
zero_reg(),
|
714
|
-
I32,
|
715
|
-
));
|
716
|
-
}
|
717
|
-
}
|
718
|
-
|
719
|
-
fn gen_probestack_loop(insts: &mut SmallInstVec<Inst>, guard_size: u32, probe_count: u32) {
|
720
|
-
insts.push(Inst::StackProbeLoop {
|
721
|
-
guard_size,
|
722
|
-
probe_count,
|
723
|
-
tmp: Writable::from_reg(x_reg(28)), // t3
|
724
|
-
});
|
725
|
-
}
|
726
|
-
}
|