rggen 0.8.2 → 0.9.0

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Files changed (269) hide show
  1. checksums.yaml +4 -4
  2. data/CODE_OF_CONDUCT.md +54 -29
  3. data/{LICENSE.txt → LICENSE} +1 -1
  4. data/README.md +65 -56
  5. data/lib/rggen.rb +4 -63
  6. data/lib/rggen/built_in.rb +53 -0
  7. data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
  8. data/lib/rggen/built_in/bit_field/comment.rb +16 -0
  9. data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
  10. data/lib/rggen/built_in/bit_field/name.rb +39 -0
  11. data/lib/rggen/built_in/bit_field/reference.rb +100 -0
  12. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
  13. data/lib/rggen/built_in/bit_field/type.rb +279 -0
  14. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
  15. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
  16. data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
  17. data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
  18. data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
  19. data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
  20. data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
  21. data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
  22. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
  23. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
  24. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
  25. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
  26. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
  27. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
  28. data/lib/rggen/built_in/global/address_width.rb +32 -0
  29. data/lib/rggen/built_in/global/array_port_format.rb +19 -0
  30. data/lib/rggen/built_in/global/bus_width.rb +33 -0
  31. data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
  32. data/lib/rggen/built_in/register/name.rb +34 -0
  33. data/lib/rggen/built_in/register/offset_address.rb +96 -0
  34. data/lib/rggen/built_in/register/size.rb +49 -0
  35. data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
  36. data/lib/rggen/built_in/register/type.rb +374 -0
  37. data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
  38. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
  39. data/lib/rggen/built_in/register/type/external.erb +11 -0
  40. data/lib/rggen/built_in/register/type/external.rb +141 -0
  41. data/lib/rggen/built_in/register/type/indirect.rb +329 -0
  42. data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
  43. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
  44. data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
  45. data/lib/rggen/built_in/register_block/name.rb +36 -0
  46. data/lib/rggen/built_in/register_block/protocol.rb +71 -0
  47. data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
  48. data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
  49. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
  50. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
  51. data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
  52. data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
  53. data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
  54. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
  55. data/lib/rggen/built_in/version.rb +7 -0
  56. data/lib/rggen/default_setup_file.rb +6 -0
  57. data/lib/rggen/setup/default.rb +26 -0
  58. data/lib/rggen/version.rb +5 -4
  59. data/sample/block_0.rb +85 -0
  60. data/sample/block_0.sv +601 -0
  61. data/sample/block_0.xlsx +0 -0
  62. data/sample/block_0.yml +94 -0
  63. data/sample/block_0_ral_pkg.sv +174 -0
  64. data/sample/block_1.rb +22 -0
  65. data/sample/block_1.sv +136 -0
  66. data/sample/block_1.xlsx +0 -0
  67. data/sample/block_1.yml +26 -0
  68. data/sample/block_1_ral_pkg.sv +68 -0
  69. data/sample/config.json +5 -0
  70. data/sample/config.yml +3 -0
  71. metadata +96 -270
  72. data/bin/rggen +0 -6
  73. data/c_header/LICENSE +0 -21
  74. data/c_header/rggen.h +0 -17
  75. data/lib/rggen/base/component.rb +0 -31
  76. data/lib/rggen/base/component_factory.rb +0 -53
  77. data/lib/rggen/base/hierarchical_accessors.rb +0 -87
  78. data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
  79. data/lib/rggen/base/internal_struct.rb +0 -28
  80. data/lib/rggen/base/item.rb +0 -35
  81. data/lib/rggen/base/item_factory.rb +0 -25
  82. data/lib/rggen/builder/builder.rb +0 -69
  83. data/lib/rggen/builder/category.rb +0 -63
  84. data/lib/rggen/builder/component_entry.rb +0 -50
  85. data/lib/rggen/builder/component_store.rb +0 -42
  86. data/lib/rggen/builder/input_component_store.rb +0 -25
  87. data/lib/rggen/builder/item_store.rb +0 -89
  88. data/lib/rggen/builder/list_item_entry.rb +0 -81
  89. data/lib/rggen/builder/output_component_store.rb +0 -13
  90. data/lib/rggen/builder/simple_item_entry.rb +0 -33
  91. data/lib/rggen/builtins.rb +0 -55
  92. data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
  93. data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
  94. data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
  95. data/lib/rggen/builtins/bit_field/name.rb +0 -26
  96. data/lib/rggen/builtins/bit_field/reference.rb +0 -40
  97. data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
  98. data/lib/rggen/builtins/bit_field/type.rb +0 -244
  99. data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
  100. data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
  101. data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
  102. data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
  103. data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
  104. data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
  105. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
  106. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
  107. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
  108. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
  109. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
  110. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
  111. data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
  112. data/lib/rggen/builtins/global/address_width.rb +0 -17
  113. data/lib/rggen/builtins/global/array_port_format.rb +0 -15
  114. data/lib/rggen/builtins/global/data_width.rb +0 -20
  115. data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
  116. data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
  117. data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
  118. data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
  119. data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
  120. data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
  121. data/lib/rggen/builtins/register/array.rb +0 -30
  122. data/lib/rggen/builtins/register/constructor.rb +0 -17
  123. data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
  124. data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
  125. data/lib/rggen/builtins/register/name.rb +0 -26
  126. data/lib/rggen/builtins/register/offset_address.rb +0 -61
  127. data/lib/rggen/builtins/register/reg_model.rb +0 -107
  128. data/lib/rggen/builtins/register/rtl_top.rb +0 -68
  129. data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
  130. data/lib/rggen/builtins/register/type.rb +0 -283
  131. data/lib/rggen/builtins/register/types/default.erb +0 -10
  132. data/lib/rggen/builtins/register/types/external.erb +0 -11
  133. data/lib/rggen/builtins/register/types/external.rb +0 -77
  134. data/lib/rggen/builtins/register/types/indirect.erb +0 -13
  135. data/lib/rggen/builtins/register/types/indirect.rb +0 -175
  136. data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
  137. data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
  138. data/lib/rggen/builtins/register_block/base_address.rb +0 -64
  139. data/lib/rggen/builtins/register_block/block_model.rb +0 -20
  140. data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
  141. data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
  142. data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
  143. data/lib/rggen/builtins/register_block/constructor.rb +0 -14
  144. data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
  145. data/lib/rggen/builtins/register_block/host_if.rb +0 -64
  146. data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
  147. data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
  148. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
  149. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
  150. data/lib/rggen/builtins/register_block/name.rb +0 -26
  151. data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
  152. data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
  153. data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
  154. data/lib/rggen/commands.rb +0 -23
  155. data/lib/rggen/core_components.rb +0 -54
  156. data/lib/rggen/core_components/c_header/item.rb +0 -8
  157. data/lib/rggen/core_components/c_header/setup.rb +0 -19
  158. data/lib/rggen/core_components/c_utility.rb +0 -19
  159. data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
  160. data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
  161. data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
  162. data/lib/rggen/core_components/code_utility.rb +0 -56
  163. data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
  164. data/lib/rggen/core_components/code_utility/line.rb +0 -28
  165. data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
  166. data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
  167. data/lib/rggen/core_components/configuration/item.rb +0 -11
  168. data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
  169. data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
  170. data/lib/rggen/core_components/configuration/setup.rb +0 -14
  171. data/lib/rggen/core_components/erb_engine.rb +0 -15
  172. data/lib/rggen/core_components/ral/component.rb +0 -24
  173. data/lib/rggen/core_components/ral/item.rb +0 -59
  174. data/lib/rggen/core_components/ral/setup.rb +0 -19
  175. data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
  176. data/lib/rggen/core_components/register_map/component.rb +0 -15
  177. data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
  178. data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
  179. data/lib/rggen/core_components/register_map/item.rb +0 -26
  180. data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
  181. data/lib/rggen/core_components/register_map/loader.rb +0 -11
  182. data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
  183. data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
  184. data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
  185. data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
  186. data/lib/rggen/core_components/register_map/setup.rb +0 -33
  187. data/lib/rggen/core_components/rtl/component.rb +0 -24
  188. data/lib/rggen/core_components/rtl/item.rb +0 -82
  189. data/lib/rggen/core_components/rtl/setup.rb +0 -19
  190. data/lib/rggen/core_components/verilog_utility.rb +0 -88
  191. data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
  192. data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
  193. data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
  194. data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
  195. data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
  196. data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
  197. data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
  198. data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
  199. data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
  200. data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
  201. data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
  202. data/lib/rggen/core_extensions/array.rb +0 -9
  203. data/lib/rggen/core_extensions/facets.rb +0 -22
  204. data/lib/rggen/core_extensions/forwardable.rb +0 -49
  205. data/lib/rggen/core_extensions/integer.rb +0 -5
  206. data/lib/rggen/core_extensions/math.rb +0 -7
  207. data/lib/rggen/core_extensions/roo.rb +0 -17
  208. data/lib/rggen/exceptions.rb +0 -28
  209. data/lib/rggen/generator.rb +0 -67
  210. data/lib/rggen/input_base/component.rb +0 -28
  211. data/lib/rggen/input_base/component_factory.rb +0 -58
  212. data/lib/rggen/input_base/item.rb +0 -171
  213. data/lib/rggen/input_base/item_factory.rb +0 -13
  214. data/lib/rggen/input_base/loader.rb +0 -23
  215. data/lib/rggen/input_base/regexp_patterns.rb +0 -29
  216. data/lib/rggen/option_switches.rb +0 -60
  217. data/lib/rggen/options.rb +0 -97
  218. data/lib/rggen/output_base/code_generator.rb +0 -36
  219. data/lib/rggen/output_base/component.rb +0 -78
  220. data/lib/rggen/output_base/component_factory.rb +0 -32
  221. data/lib/rggen/output_base/file_writer.rb +0 -36
  222. data/lib/rggen/output_base/item.rb +0 -110
  223. data/lib/rggen/output_base/item_factory.rb +0 -9
  224. data/lib/rggen/output_base/template_engine.rb +0 -24
  225. data/lib/rggen/rggen_home.rb +0 -3
  226. data/ral/LICENSE +0 -21
  227. data/ral/compile.f +0 -2
  228. data/ral/rggen_ral_block.svh +0 -83
  229. data/ral/rggen_ral_field.svh +0 -47
  230. data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
  231. data/ral/rggen_ral_indirect_reg.svh +0 -193
  232. data/ral/rggen_ral_macros.svh +0 -27
  233. data/ral/rggen_ral_map.svh +0 -124
  234. data/ral/rggen_ral_pkg.sv +0 -15
  235. data/ral/rggen_ral_reg.svh +0 -88
  236. data/rtl/LICENSE +0 -21
  237. data/rtl/compile.f +0 -18
  238. data/rtl/rggen_address_decoder.sv +0 -23
  239. data/rtl/rggen_apb_if.sv +0 -41
  240. data/rtl/rggen_axi4lite_if.sv +0 -68
  241. data/rtl/rggen_bit_field_if.sv +0 -28
  242. data/rtl/rggen_bit_field_ro.sv +0 -9
  243. data/rtl/rggen_bit_field_rw.sv +0 -25
  244. data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
  245. data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
  246. data/rtl/rggen_bus_if.sv +0 -43
  247. data/rtl/rggen_bus_splitter.sv +0 -86
  248. data/rtl/rggen_default_register.sv +0 -15
  249. data/rtl/rggen_external_register.sv +0 -83
  250. data/rtl/rggen_host_if_apb.sv +0 -29
  251. data/rtl/rggen_host_if_axi4lite.sv +0 -161
  252. data/rtl/rggen_indirect_register.sv +0 -21
  253. data/rtl/rggen_register_base.sv +0 -57
  254. data/rtl/rggen_register_if.sv +0 -42
  255. data/rtl/rggen_rtl_pkg.sv +0 -23
  256. data/sample/LICENSE +0 -21
  257. data/sample/sample.csv +0 -21
  258. data/sample/sample.json +0 -6
  259. data/sample/sample.xls +0 -0
  260. data/sample/sample.xlsx +0 -0
  261. data/sample/sample.yaml +0 -4
  262. data/sample/sample_0.h +0 -17
  263. data/sample/sample_0.sv +0 -402
  264. data/sample/sample_0_ral_pkg.sv +0 -145
  265. data/sample/sample_1.h +0 -9
  266. data/sample/sample_1.sv +0 -128
  267. data/sample/sample_1_ral_pkg.sv +0 -56
  268. data/sample/sample_setup.rb +0 -24
  269. data/setup/default.rb +0 -14
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data/CODE_OF_CONDUCT.md CHANGED
@@ -1,24 +1,41 @@
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- # Contributor Code of Conduct
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+ # Contributor Covenant Code of Conduct
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- As contributors and maintainers of this project, and in the interest of
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- fostering an open and welcoming community, we pledge to respect all people who
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- contribute through reporting issues, posting feature requests, updating
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- documentation, submitting pull requests or patches, and other activities.
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+ ## Our Pledge
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- We are committed to making participation in this project a harassment-free
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- experience for everyone, regardless of level of experience, gender, gender
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- identity and expression, sexual orientation, disability, personal appearance,
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- body size, race, ethnicity, age, religion, or nationality.
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+ In the interest of fostering an open and welcoming environment, we as
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+ contributors and maintainers pledge to making participation in our project and
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+ our community a harassment-free experience for everyone, regardless of age, body
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+ size, disability, ethnicity, gender identity and expression, level of experience,
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+ nationality, personal appearance, race, religion, or sexual identity and
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+ orientation.
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+
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+ ## Our Standards
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+
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+ Examples of behavior that contributes to creating a positive environment
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+ include:
16
+
17
+ * Using welcoming and inclusive language
18
+ * Being respectful of differing viewpoints and experiences
19
+ * Gracefully accepting constructive criticism
20
+ * Focusing on what is best for the community
21
+ * Showing empathy towards other community members
12
22
 
13
23
  Examples of unacceptable behavior by participants include:
14
24
 
15
- * The use of sexualized language or imagery
16
- * Personal attacks
17
- * Trolling or insulting/derogatory comments
25
+ * The use of sexualized language or imagery and unwelcome sexual attention or
26
+ advances
27
+ * Trolling, insulting/derogatory comments, and personal or political attacks
18
28
  * Public or private harassment
19
- * Publishing other's private information, such as physical or electronic
20
- addresses, without explicit permission
21
- * Other unethical or unprofessional conduct
29
+ * Publishing others' private information, such as a physical or electronic
30
+ address, without explicit permission
31
+ * Other conduct which could reasonably be considered inappropriate in a
32
+ professional setting
33
+
34
+ ## Our Responsibilities
35
+
36
+ Project maintainers are responsible for clarifying the standards of acceptable
37
+ behavior and are expected to take appropriate and fair corrective action in
38
+ response to any instances of unacceptable behavior.
22
39
 
23
40
  Project maintainers have the right and responsibility to remove, edit, or
24
41
  reject comments, commits, code, wiki edits, issues, and other contributions
@@ -26,24 +43,32 @@ that are not aligned to this Code of Conduct, or to ban temporarily or
26
43
  permanently any contributor for other behaviors that they deem inappropriate,
27
44
  threatening, offensive, or harmful.
28
45
 
29
- By adopting this Code of Conduct, project maintainers commit themselves to
30
- fairly and consistently applying these principles to every aspect of managing
31
- this project. Project maintainers who do not follow or enforce the Code of
32
- Conduct may be permanently removed from the project team.
46
+ ## Scope
47
+
48
+ This Code of Conduct applies both within project spaces and in public spaces
49
+ when an individual is representing the project or its community. Examples of
50
+ representing a project or community include using an official project e-mail
51
+ address, posting via an official social media account, or acting as an appointed
52
+ representative at an online or offline event. Representation of a project may be
53
+ further defined and clarified by project maintainers.
33
54
 
34
- This code of conduct applies both within project spaces and in public spaces
35
- when an individual is representing the project or its community.
55
+ ## Enforcement
36
56
 
37
57
  Instances of abusive, harassing, or otherwise unacceptable behavior may be
38
- reported by contacting a project maintainer at taichi730@jf6.so-net.ne.jp. All
58
+ reported by contacting the project team at taichi730@gmail.com. All
39
59
  complaints will be reviewed and investigated and will result in a response that
40
- is deemed necessary and appropriate to the circumstances. Maintainers are
41
- obligated to maintain confidentiality with regard to the reporter of an
42
- incident.
60
+ is deemed necessary and appropriate to the circumstances. The project team is
61
+ obligated to maintain confidentiality with regard to the reporter of an incident.
62
+ Further details of specific enforcement policies may be posted separately.
63
+
64
+ Project maintainers who do not follow or enforce the Code of Conduct in good
65
+ faith may face temporary or permanent repercussions as determined by other
66
+ members of the project's leadership.
67
+
68
+ ## Attribution
43
69
 
44
- This Code of Conduct is adapted from the [Contributor Covenant][homepage],
45
- version 1.3.0, available at
46
- [http://contributor-covenant.org/version/1/3/0/][version]
70
+ This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
71
+ available at [http://contributor-covenant.org/version/1/4][version]
47
72
 
48
73
  [homepage]: http://contributor-covenant.org
49
- [version]: http://contributor-covenant.org/version/1/3/0/
74
+ [version]: http://contributor-covenant.org/version/1/4/
@@ -1,6 +1,6 @@
1
1
  The MIT License (MIT)
2
2
 
3
- Copyright (c) 2015-2017 Taichi Ishitani
3
+ Copyright (c) 2019 Taichi Ishitani
4
4
 
5
5
  Permission is hereby granted, free of charge, to any person obtaining a copy
6
6
  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -1,56 +1,65 @@
1
- [![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
2
- [![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
3
- [![Maintainability](https://api.codeclimate.com/v1/badges/8f184e6e714a0fbdb6b0/maintainability)](https://codeclimate.com/github/taichi-ishitani/rggen/maintainability)
4
- [![codecov](https://codecov.io/gh/taichi-ishitani/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/taichi-ishitani/rggen)
5
- [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
6
-
7
- # RgGen
8
-
9
- RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
10
- It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
11
- Also RgGen is customizable so you can build your specific generate tool.
12
-
13
- ## Ruby
14
-
15
- RgGen is written in the [*Ruby*](https://www.ruby-lang.org/en/about/) programing language and supports version 2.3 or later.
16
- If you don't have above version of Ruby, you need to install the Ruby at first.
17
- To install the Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
18
-
19
- ## Installation
20
-
21
- To install RgGen and required libraries, use the following command:
22
-
23
- $ gem install rggen
24
-
25
- RgGen will be installed under your system root.
26
-
27
- If you want to install them on other location, you need to specify the install directory and set the **GEM_PATH** environment variable like below:
28
-
29
- $ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
30
- $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
31
-
32
- ## Usage
33
-
34
- See [this page](https://github.com/taichi-ishitani/rggen/wiki/Getting-Started)
35
-
36
- ## Development
37
-
38
- After checking out the repo, run `bin/setup` to install dependencies. Then, run `rake spec` to run the tests.
39
-
40
- To install this gem onto your local machine, run `bundle exec rake install`. To release a new version, update the version number in `version.rb`, and then run `bundle exec rake release`, which will create a git tag for the version, push git commits and tags, and push the `.gem` file to [rubygems.org](https://rubygems.org).
41
-
42
- ## Contact
43
-
44
- If you have any questions, problems, ideas or somethings, you can post them on the following ways:
45
-
46
- 1. [Issue tracker](https://github.com/taichi-ishitani/rggen/issues)
47
- 2. [Chat room](https://gitter.im/taichi-ishitani/rggen)
48
- 3. [Mail](mailto:taichi730@gmail.com)
49
-
50
- ## Contributing
51
-
52
- Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the [Contributor Covenant](http://contributor-covenant.org) code of conduct.
53
-
54
- ## Copyright
55
-
56
- Copyright © 2015-2018 Taichi Ishitani. See [LICENSE.txt](LICENSE.txt) for further details.
1
+ [![Build Status](https://travis-ci.org/rggen/rggen.svg?branch=master)](https://travis-ci.org/rggen/rggen)
2
+ [![Maintainability](https://api.codeclimate.com/v1/badges/5ee2248300ec0517e597/maintainability)](https://codeclimate.com/github/rggen/rggen/maintainability)
3
+ [![codecov](https://codecov.io/gh/rggen/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen)
4
+ [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=rggen_rggen&metric=alert_status)](https://sonarcloud.io/dashboard?id=rggen_rggen)
5
+
6
+ # RgGen
7
+
8
+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map documents.
9
+
10
+ RgGen has following features:
11
+
12
+ * Generate source files related to CSR from register map documents
13
+ * Source files listed below will be generated:
14
+ * SystemVerilog RTL
15
+ * UVM RAL model
16
+ * Register map documents can be written in human readable format
17
+ * Supported formats are listed below:
18
+ * Ruby with APIs to describe register map information
19
+ * YAML
20
+ * JSON
21
+ * Spreadsheet (XLSX, XLS, OSD, CSV)
22
+ * Costomize RgGen for you environment
23
+ * E.g. add special bit field types
24
+
25
+ ## Installation
26
+
27
+ ### Ruby
28
+
29
+ RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.3 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
30
+
31
+ ### Installatin Command
32
+
33
+ To isnstall RgGen and necessary libraries, use this command:
34
+
35
+ ```
36
+ $ gem install rggen
37
+ ```
38
+
39
+ RgGen and libraries will be installed on your system root.
40
+
41
+ If you want to install them on other location, you need to specify install path and set the `GEM_PATH` environment variable:
42
+
43
+ ```
44
+ $ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
45
+ $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
46
+ ```
47
+
48
+ ## Usage
49
+
50
+ See [Wiki documents](https://github.com/rggen/rggen/wiki).
51
+
52
+ ## Contact
53
+
54
+ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
55
+
56
+ * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
57
+ * [Mail](mailto:taichi730@gmail.com)
58
+
59
+ ## Copyright & License
60
+
61
+ Copyright © 2019 Taichi Ishitani. RgGen is licensed unther the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
62
+
63
+ ## Code of Conduct
64
+
65
+ Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen/blob/master/CODE_OF_CONDUCT.md).
data/lib/rggen.rb CHANGED
@@ -1,64 +1,5 @@
1
- module RgGen
2
- require 'forwardable'
3
- require 'singleton'
4
- require 'pathname'
5
- require 'optparse'
6
- require 'erubi'
7
- require 'csv'
8
- require 'roo'
9
- require 'spreadsheet'
1
+ # frozen_string_literal: true
10
2
 
11
- require_relative 'rggen/version'
12
- require_relative 'rggen/rggen_home'
13
-
14
- require_relative 'rggen/exceptions'
15
-
16
- require_relative 'rggen/core_extensions/array'
17
- require_relative 'rggen/core_extensions/facets'
18
- require_relative 'rggen/core_extensions/forwardable'
19
- require_relative 'rggen/core_extensions/integer'
20
- require_relative 'rggen/core_extensions/math'
21
- require_relative 'rggen/core_extensions/roo'
22
-
23
- require_relative 'rggen/base/hierarchical_accessors'
24
- require_relative 'rggen/base/hierarchical_item_accessors'
25
- require_relative 'rggen/base/internal_struct'
26
- require_relative 'rggen/base/component'
27
- require_relative 'rggen/base/item'
28
- require_relative 'rggen/base/component_factory'
29
- require_relative 'rggen/base/item_factory'
30
-
31
- require_relative 'rggen/input_base/regexp_patterns'
32
- require_relative 'rggen/input_base/component'
33
- require_relative 'rggen/input_base/item'
34
- require_relative 'rggen/input_base/loader'
35
- require_relative 'rggen/input_base/component_factory'
36
- require_relative 'rggen/input_base/item_factory'
37
-
38
- require_relative 'rggen/output_base/code_generator'
39
- require_relative 'rggen/output_base/template_engine'
40
- require_relative 'rggen/output_base/file_writer'
41
- require_relative 'rggen/output_base/component'
42
- require_relative 'rggen/output_base/item'
43
- require_relative 'rggen/output_base/component_factory'
44
- require_relative 'rggen/output_base/item_factory'
45
-
46
- require_relative 'rggen/builder/simple_item_entry'
47
- require_relative 'rggen/builder/list_item_entry'
48
- require_relative 'rggen/builder/item_store'
49
- require_relative 'rggen/builder/component_entry'
50
- require_relative 'rggen/builder/component_store'
51
- require_relative 'rggen/builder/input_component_store'
52
- require_relative 'rggen/builder/output_component_store'
53
- require_relative 'rggen/builder/category'
54
- require_relative 'rggen/builder/builder'
55
-
56
- require_relative 'rggen/options'
57
- require_relative 'rggen/option_switches'
58
- require_relative 'rggen/generator'
59
-
60
- require_relative 'rggen/commands'
61
-
62
- require_relative 'rggen/core_components'
63
- require_relative 'rggen/builtins'
64
- end
3
+ require_relative 'rggen/version'
4
+ require_relative 'rggen/default_setup_file'
5
+ require_relative 'rggen/built_in'
@@ -0,0 +1,53 @@
1
+ # frozen_string_literal: true
2
+
3
+ require_relative 'built_in/version'
4
+
5
+ module RgGen
6
+ module BuiltIn
7
+ BUILT_IN_FILES = [
8
+ 'built_in/global/address_width',
9
+ 'built_in/global/array_port_format',
10
+ 'built_in/global/bus_width',
11
+ 'built_in/global/fold_sv_interface_port',
12
+ 'built_in/register_block/byte_size',
13
+ 'built_in/register_block/name',
14
+ 'built_in/register_block/protocol',
15
+ 'built_in/register_block/protocol/apb',
16
+ 'built_in/register_block/protocol/axi4lite',
17
+ 'built_in/register_block/sv_ral_package',
18
+ 'built_in/register_block/sv_rtl_top',
19
+ 'built_in/register/name',
20
+ 'built_in/register/offset_address',
21
+ 'built_in/register/size',
22
+ 'built_in/register/sv_rtl_top',
23
+ 'built_in/register/type',
24
+ 'built_in/register/type/external',
25
+ 'built_in/register/type/indirect',
26
+ 'built_in/bit_field/bit_assignment',
27
+ 'built_in/bit_field/comment',
28
+ 'built_in/bit_field/initial_value',
29
+ 'built_in/bit_field/name',
30
+ 'built_in/bit_field/reference',
31
+ 'built_in/bit_field/sv_rtl_top',
32
+ 'built_in/bit_field/type',
33
+ 'built_in/bit_field/type/rc_w0c_w1c',
34
+ 'built_in/bit_field/type/reserved',
35
+ 'built_in/bit_field/type/ro',
36
+ 'built_in/bit_field/type/rof',
37
+ 'built_in/bit_field/type/rs_w0s_w1s',
38
+ 'built_in/bit_field/type/rw_wo',
39
+ 'built_in/bit_field/type/rwe_rwl',
40
+ 'built_in/bit_field/type/rwe_rwl'
41
+ ].freeze
42
+
43
+ def self.load_built_in
44
+ BUILT_IN_FILES.each { |file| require_relative file }
45
+ end
46
+
47
+ def self.setup(_builder)
48
+ load_built_in
49
+ end
50
+ end
51
+
52
+ setup :'built-in', BuiltIn
53
+ end
@@ -0,0 +1,108 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
4
+ register_map do
5
+ property :lsb, body: ->(index = 0) { msb_lsb_bit(index, @lsb) }
6
+ property :msb, body: ->(index = 0) { msb_lsb_bit(index, @lsb + width - 1) }
7
+ property :width, body: -> { @width || 1 }
8
+ property :sequence_size
9
+ property :step, body: -> { @step || width }
10
+ property :sequential?, body: -> { !@sequence_size.nil? }
11
+ property :bit_map, body: -> { @bit_map ||= calc_bit_map }
12
+
13
+ input_pattern /#{integer}(?::#{integer}){0,3}/,
14
+ match_automatically: false
15
+
16
+ build do |value|
17
+ input_value = preprocess(value)
18
+ @lsb, @width, @sequence_size, @step =
19
+ KEYS.map { |key| parse_value(input_value, key) }
20
+ end
21
+
22
+ verify(:feature) do
23
+ error_condition { [@lsb, @width, @sequence_size, @step].none? }
24
+ message { 'no bit assignment is given' }
25
+ end
26
+
27
+ verify(:feature) do
28
+ error_condition { !@lsb }
29
+ message { 'no lsb is given' }
30
+ end
31
+
32
+ verify(:feature) do
33
+ error_condition { lsb.negative? }
34
+ message { "lsb is less than 0: #{lsb}" }
35
+ end
36
+
37
+ verify(:feature) do
38
+ error_condition { width < 1 }
39
+ message { "width is less than 1: #{width}" }
40
+ end
41
+
42
+ verify(:feature) do
43
+ error_condition { sequential? && sequence_size < 1 }
44
+ message { "sequence size is less than 1: #{sequence_size}" }
45
+ end
46
+
47
+ verify(:feature) do
48
+ error_condition { sequential? && step < 1 }
49
+ message { "step is less than 1: #{step}" }
50
+ end
51
+
52
+ verify(:feature) do
53
+ error_condition { overlap? }
54
+ message { 'overlap with existing bit field(s)' }
55
+ end
56
+
57
+ private
58
+
59
+ KEYS = [:lsb, :width, :sequence_size, :step].freeze
60
+
61
+ def preprocess(value)
62
+ if value.is_a?(Hash)
63
+ value
64
+ elsif match_pattern(value)
65
+ split_match_data(match_data)
66
+ else
67
+ error "illegal input value for bit assignment: #{value.inspect}"
68
+ end
69
+ end
70
+
71
+ def split_match_data(match_data)
72
+ match_data
73
+ .to_s
74
+ .split(':')
75
+ .map.with_index { |value, i| [KEYS[i], value] }
76
+ .to_h
77
+ end
78
+
79
+ def parse_value(input_value, key)
80
+ (input_value.key?(key) && Integer(input_value[key])) || nil
81
+ rescue ArgumentError, TypeError
82
+ error "cannot convert #{input_value[key].inspect} into " \
83
+ "bit assignment(#{key.to_s.tr('_', ' ')})"
84
+ end
85
+
86
+ def msb_lsb_bit(index, base)
87
+ calc_bit_position((sequential? && index) || 0, base)
88
+ end
89
+
90
+ def calc_bit_position(index, base)
91
+ if index.is_a?(Integer)
92
+ base + step * index
93
+ else
94
+ "#{base}+#{step}*#{index}"
95
+ end
96
+ end
97
+
98
+ def calc_bit_map
99
+ Array.new(sequence_size || 1) { |i| (2**width - 1) << lsb(i) }.inject(:|)
100
+ end
101
+
102
+ def overlap?
103
+ register
104
+ .bit_fields
105
+ .any? { |bit_field| (bit_field.bit_map & bit_map).positive? }
106
+ end
107
+ end
108
+ end