rggen 0.8.2 → 0.9.0

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Files changed (269) hide show
  1. checksums.yaml +4 -4
  2. data/CODE_OF_CONDUCT.md +54 -29
  3. data/{LICENSE.txt → LICENSE} +1 -1
  4. data/README.md +65 -56
  5. data/lib/rggen.rb +4 -63
  6. data/lib/rggen/built_in.rb +53 -0
  7. data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
  8. data/lib/rggen/built_in/bit_field/comment.rb +16 -0
  9. data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
  10. data/lib/rggen/built_in/bit_field/name.rb +39 -0
  11. data/lib/rggen/built_in/bit_field/reference.rb +100 -0
  12. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
  13. data/lib/rggen/built_in/bit_field/type.rb +279 -0
  14. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
  15. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
  16. data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
  17. data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
  18. data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
  19. data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
  20. data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
  21. data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
  22. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
  23. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
  24. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
  25. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
  26. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
  27. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
  28. data/lib/rggen/built_in/global/address_width.rb +32 -0
  29. data/lib/rggen/built_in/global/array_port_format.rb +19 -0
  30. data/lib/rggen/built_in/global/bus_width.rb +33 -0
  31. data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
  32. data/lib/rggen/built_in/register/name.rb +34 -0
  33. data/lib/rggen/built_in/register/offset_address.rb +96 -0
  34. data/lib/rggen/built_in/register/size.rb +49 -0
  35. data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
  36. data/lib/rggen/built_in/register/type.rb +374 -0
  37. data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
  38. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
  39. data/lib/rggen/built_in/register/type/external.erb +11 -0
  40. data/lib/rggen/built_in/register/type/external.rb +141 -0
  41. data/lib/rggen/built_in/register/type/indirect.rb +329 -0
  42. data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
  43. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
  44. data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
  45. data/lib/rggen/built_in/register_block/name.rb +36 -0
  46. data/lib/rggen/built_in/register_block/protocol.rb +71 -0
  47. data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
  48. data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
  49. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
  50. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
  51. data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
  52. data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
  53. data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
  54. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
  55. data/lib/rggen/built_in/version.rb +7 -0
  56. data/lib/rggen/default_setup_file.rb +6 -0
  57. data/lib/rggen/setup/default.rb +26 -0
  58. data/lib/rggen/version.rb +5 -4
  59. data/sample/block_0.rb +85 -0
  60. data/sample/block_0.sv +601 -0
  61. data/sample/block_0.xlsx +0 -0
  62. data/sample/block_0.yml +94 -0
  63. data/sample/block_0_ral_pkg.sv +174 -0
  64. data/sample/block_1.rb +22 -0
  65. data/sample/block_1.sv +136 -0
  66. data/sample/block_1.xlsx +0 -0
  67. data/sample/block_1.yml +26 -0
  68. data/sample/block_1_ral_pkg.sv +68 -0
  69. data/sample/config.json +5 -0
  70. data/sample/config.yml +3 -0
  71. metadata +96 -270
  72. data/bin/rggen +0 -6
  73. data/c_header/LICENSE +0 -21
  74. data/c_header/rggen.h +0 -17
  75. data/lib/rggen/base/component.rb +0 -31
  76. data/lib/rggen/base/component_factory.rb +0 -53
  77. data/lib/rggen/base/hierarchical_accessors.rb +0 -87
  78. data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
  79. data/lib/rggen/base/internal_struct.rb +0 -28
  80. data/lib/rggen/base/item.rb +0 -35
  81. data/lib/rggen/base/item_factory.rb +0 -25
  82. data/lib/rggen/builder/builder.rb +0 -69
  83. data/lib/rggen/builder/category.rb +0 -63
  84. data/lib/rggen/builder/component_entry.rb +0 -50
  85. data/lib/rggen/builder/component_store.rb +0 -42
  86. data/lib/rggen/builder/input_component_store.rb +0 -25
  87. data/lib/rggen/builder/item_store.rb +0 -89
  88. data/lib/rggen/builder/list_item_entry.rb +0 -81
  89. data/lib/rggen/builder/output_component_store.rb +0 -13
  90. data/lib/rggen/builder/simple_item_entry.rb +0 -33
  91. data/lib/rggen/builtins.rb +0 -55
  92. data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
  93. data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
  94. data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
  95. data/lib/rggen/builtins/bit_field/name.rb +0 -26
  96. data/lib/rggen/builtins/bit_field/reference.rb +0 -40
  97. data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
  98. data/lib/rggen/builtins/bit_field/type.rb +0 -244
  99. data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
  100. data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
  101. data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
  102. data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
  103. data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
  104. data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
  105. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
  106. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
  107. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
  108. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
  109. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
  110. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
  111. data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
  112. data/lib/rggen/builtins/global/address_width.rb +0 -17
  113. data/lib/rggen/builtins/global/array_port_format.rb +0 -15
  114. data/lib/rggen/builtins/global/data_width.rb +0 -20
  115. data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
  116. data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
  117. data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
  118. data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
  119. data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
  120. data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
  121. data/lib/rggen/builtins/register/array.rb +0 -30
  122. data/lib/rggen/builtins/register/constructor.rb +0 -17
  123. data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
  124. data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
  125. data/lib/rggen/builtins/register/name.rb +0 -26
  126. data/lib/rggen/builtins/register/offset_address.rb +0 -61
  127. data/lib/rggen/builtins/register/reg_model.rb +0 -107
  128. data/lib/rggen/builtins/register/rtl_top.rb +0 -68
  129. data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
  130. data/lib/rggen/builtins/register/type.rb +0 -283
  131. data/lib/rggen/builtins/register/types/default.erb +0 -10
  132. data/lib/rggen/builtins/register/types/external.erb +0 -11
  133. data/lib/rggen/builtins/register/types/external.rb +0 -77
  134. data/lib/rggen/builtins/register/types/indirect.erb +0 -13
  135. data/lib/rggen/builtins/register/types/indirect.rb +0 -175
  136. data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
  137. data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
  138. data/lib/rggen/builtins/register_block/base_address.rb +0 -64
  139. data/lib/rggen/builtins/register_block/block_model.rb +0 -20
  140. data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
  141. data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
  142. data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
  143. data/lib/rggen/builtins/register_block/constructor.rb +0 -14
  144. data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
  145. data/lib/rggen/builtins/register_block/host_if.rb +0 -64
  146. data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
  147. data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
  148. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
  149. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
  150. data/lib/rggen/builtins/register_block/name.rb +0 -26
  151. data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
  152. data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
  153. data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
  154. data/lib/rggen/commands.rb +0 -23
  155. data/lib/rggen/core_components.rb +0 -54
  156. data/lib/rggen/core_components/c_header/item.rb +0 -8
  157. data/lib/rggen/core_components/c_header/setup.rb +0 -19
  158. data/lib/rggen/core_components/c_utility.rb +0 -19
  159. data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
  160. data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
  161. data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
  162. data/lib/rggen/core_components/code_utility.rb +0 -56
  163. data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
  164. data/lib/rggen/core_components/code_utility/line.rb +0 -28
  165. data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
  166. data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
  167. data/lib/rggen/core_components/configuration/item.rb +0 -11
  168. data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
  169. data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
  170. data/lib/rggen/core_components/configuration/setup.rb +0 -14
  171. data/lib/rggen/core_components/erb_engine.rb +0 -15
  172. data/lib/rggen/core_components/ral/component.rb +0 -24
  173. data/lib/rggen/core_components/ral/item.rb +0 -59
  174. data/lib/rggen/core_components/ral/setup.rb +0 -19
  175. data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
  176. data/lib/rggen/core_components/register_map/component.rb +0 -15
  177. data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
  178. data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
  179. data/lib/rggen/core_components/register_map/item.rb +0 -26
  180. data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
  181. data/lib/rggen/core_components/register_map/loader.rb +0 -11
  182. data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
  183. data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
  184. data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
  185. data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
  186. data/lib/rggen/core_components/register_map/setup.rb +0 -33
  187. data/lib/rggen/core_components/rtl/component.rb +0 -24
  188. data/lib/rggen/core_components/rtl/item.rb +0 -82
  189. data/lib/rggen/core_components/rtl/setup.rb +0 -19
  190. data/lib/rggen/core_components/verilog_utility.rb +0 -88
  191. data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
  192. data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
  193. data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
  194. data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
  195. data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
  196. data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
  197. data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
  198. data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
  199. data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
  200. data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
  201. data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
  202. data/lib/rggen/core_extensions/array.rb +0 -9
  203. data/lib/rggen/core_extensions/facets.rb +0 -22
  204. data/lib/rggen/core_extensions/forwardable.rb +0 -49
  205. data/lib/rggen/core_extensions/integer.rb +0 -5
  206. data/lib/rggen/core_extensions/math.rb +0 -7
  207. data/lib/rggen/core_extensions/roo.rb +0 -17
  208. data/lib/rggen/exceptions.rb +0 -28
  209. data/lib/rggen/generator.rb +0 -67
  210. data/lib/rggen/input_base/component.rb +0 -28
  211. data/lib/rggen/input_base/component_factory.rb +0 -58
  212. data/lib/rggen/input_base/item.rb +0 -171
  213. data/lib/rggen/input_base/item_factory.rb +0 -13
  214. data/lib/rggen/input_base/loader.rb +0 -23
  215. data/lib/rggen/input_base/regexp_patterns.rb +0 -29
  216. data/lib/rggen/option_switches.rb +0 -60
  217. data/lib/rggen/options.rb +0 -97
  218. data/lib/rggen/output_base/code_generator.rb +0 -36
  219. data/lib/rggen/output_base/component.rb +0 -78
  220. data/lib/rggen/output_base/component_factory.rb +0 -32
  221. data/lib/rggen/output_base/file_writer.rb +0 -36
  222. data/lib/rggen/output_base/item.rb +0 -110
  223. data/lib/rggen/output_base/item_factory.rb +0 -9
  224. data/lib/rggen/output_base/template_engine.rb +0 -24
  225. data/lib/rggen/rggen_home.rb +0 -3
  226. data/ral/LICENSE +0 -21
  227. data/ral/compile.f +0 -2
  228. data/ral/rggen_ral_block.svh +0 -83
  229. data/ral/rggen_ral_field.svh +0 -47
  230. data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
  231. data/ral/rggen_ral_indirect_reg.svh +0 -193
  232. data/ral/rggen_ral_macros.svh +0 -27
  233. data/ral/rggen_ral_map.svh +0 -124
  234. data/ral/rggen_ral_pkg.sv +0 -15
  235. data/ral/rggen_ral_reg.svh +0 -88
  236. data/rtl/LICENSE +0 -21
  237. data/rtl/compile.f +0 -18
  238. data/rtl/rggen_address_decoder.sv +0 -23
  239. data/rtl/rggen_apb_if.sv +0 -41
  240. data/rtl/rggen_axi4lite_if.sv +0 -68
  241. data/rtl/rggen_bit_field_if.sv +0 -28
  242. data/rtl/rggen_bit_field_ro.sv +0 -9
  243. data/rtl/rggen_bit_field_rw.sv +0 -25
  244. data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
  245. data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
  246. data/rtl/rggen_bus_if.sv +0 -43
  247. data/rtl/rggen_bus_splitter.sv +0 -86
  248. data/rtl/rggen_default_register.sv +0 -15
  249. data/rtl/rggen_external_register.sv +0 -83
  250. data/rtl/rggen_host_if_apb.sv +0 -29
  251. data/rtl/rggen_host_if_axi4lite.sv +0 -161
  252. data/rtl/rggen_indirect_register.sv +0 -21
  253. data/rtl/rggen_register_base.sv +0 -57
  254. data/rtl/rggen_register_if.sv +0 -42
  255. data/rtl/rggen_rtl_pkg.sv +0 -23
  256. data/sample/LICENSE +0 -21
  257. data/sample/sample.csv +0 -21
  258. data/sample/sample.json +0 -6
  259. data/sample/sample.xls +0 -0
  260. data/sample/sample.xlsx +0 -0
  261. data/sample/sample.yaml +0 -4
  262. data/sample/sample_0.h +0 -17
  263. data/sample/sample_0.sv +0 -402
  264. data/sample/sample_0_ral_pkg.sv +0 -145
  265. data/sample/sample_1.h +0 -9
  266. data/sample/sample_1.sv +0 -128
  267. data/sample/sample_1_ral_pkg.sv +0 -56
  268. data/sample/sample_setup.rb +0 -24
  269. data/setup/default.rb +0 -14
@@ -1,37 +0,0 @@
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- module RgGen
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- module VerilogUtility
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- class InterfaceInstance
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- def initialize(attributes)
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- @attributes = attributes
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- end
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-
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- def to_s
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- "#{interface_type} #{instance_identifier}()"
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- end
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-
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- def identifier
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- Identifier.new(@attributes[:name], nil, nil, nil)
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- end
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-
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- private
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-
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- def interface_type
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- return @attributes[:type] unless @attributes[:parameters]
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- "#{@attributes[:type]} #{parameters}"
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- end
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-
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- def parameters
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- "#(#{@attributes[:parameters].join(', ')})"
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- end
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-
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- def instance_identifier
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- "#{@attributes[:name]}#{dimensions}"
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- end
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-
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- def dimensions
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- return unless @attributes[:dimensions]
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- @attributes[:dimensions].map { |d| "[#{d}]" }.join
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- end
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- end
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- end
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- end
@@ -1,33 +0,0 @@
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- module RgGen
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- module VerilogUtility
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- class InterfacePort
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- def initialize(attributes)
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- @attributes = attributes
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- end
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-
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- def to_s
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- "#{interface_type} #{port_identifier}"
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- end
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-
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- def identifier
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- Identifier.new(@attributes[:name], nil, nil, nil)
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- end
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-
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- private
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-
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- def interface_type
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- return @attributes[:type] unless @attributes[:modport]
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- "#{@attributes[:type]}.#{@attributes[:modport]}"
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- end
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-
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- def port_identifier
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- "#{@attributes[:name]}#{dimensions}"
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- end
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-
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- def dimensions
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- return unless @attributes[:dimensions]
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- @attributes[:dimensions].map { |d| "[#{d}]" }.join
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- end
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- end
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- end
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- end
@@ -1,75 +0,0 @@
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- module RgGen
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- module VerilogUtility
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- class LocalScope < StructureDefinition
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- attr_setter :signals
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- attr_setter :loops
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-
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- def without_generate_keyword
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- @without_generate_keyword = true
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- end
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-
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- def to_code
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- code_block do |c|
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- header_code(c)
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- body_code(c)
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- footer_code(c)
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- end
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- end
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-
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- private
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-
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- def header_code(code)
22
- code << :generate << space unless @without_generate_keyword
23
- code << :'if (1) begin : ' << @name << nl
24
- loops? && generate_for_header(code)
25
- end
26
-
27
- def body_code_blocks
28
- blocks = []
29
- signals? && (blocks << signal_declarations)
30
- blocks.concat(super)
31
- blocks
32
- end
33
-
34
- def footer_code(code)
35
- loops? && generate_for_footer(code)
36
- code << :end
37
- code << space << :endgenerate unless @without_generate_keyword
38
- code << nl
39
- end
40
-
41
- def loops?
42
- !(@loops.nil? || @loops.empty?)
43
- end
44
-
45
- def generate_for_header(code)
46
- loops.each do |genvar, size|
47
- code.indent += 2
48
- code << "genvar #{genvar}" << semicolon << nl
49
- code << generate_for(genvar, size) << nl
50
- end
51
- end
52
-
53
- def generate_for(genvar, size)
54
- "for (#{genvar} = 0;#{genvar} < #{size};++#{genvar}) begin : g"
55
- end
56
-
57
- def generate_for_footer(code)
58
- loops.size.times do
59
- code << :end << nl
60
- code.indent -= 2
61
- end
62
- end
63
-
64
- def signals?
65
- !(@signals.nil? || @signals.empty?)
66
- end
67
-
68
- def signal_declarations
69
- lambda do |code|
70
- signals.each { |signal| code << signal << semicolon << nl }
71
- end
72
- end
73
- end
74
- end
75
- end
@@ -1,82 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class ModuleDefinition < StructureDefinition
4
- attr_setter :parameters
5
- attr_setter :ports
6
- attr_setter :signals
7
-
8
- def include_file(file)
9
- @include_files ||= []
10
- @include_files << "`include #{file.to_s.quote}"
11
- end
12
-
13
- private
14
-
15
- def header_code
16
- code_block do |code|
17
- code << :module << space << @name << space
18
- parameters? && parameter_declarations(code)
19
- port_declarations(code)
20
- code << semicolon
21
- end
22
- end
23
-
24
- def body_code_blocks
25
- blocks = []
26
- @include_files && (blocks << include_files_code)
27
- signals? && (blocks << signal_declarations)
28
- blocks.concat(super)
29
- blocks
30
- end
31
-
32
- def footer_code
33
- :endmodule
34
- end
35
-
36
- def parameters?
37
- !(@parameters.nil? || @parameters.empty?)
38
- end
39
-
40
- def ports?
41
- !(@ports.nil? || @ports.empty?)
42
- end
43
-
44
- def signals?
45
- !(@signals.nil? || @signals.empty?)
46
- end
47
-
48
- def parameter_declarations(code)
49
- wrap(code, '#(', ')') do
50
- declarations(@parameters, code)
51
- end
52
- end
53
-
54
- def port_declarations(code)
55
- wrap(code, '(', ')') do
56
- ports? && declarations(@ports, code)
57
- end
58
- end
59
-
60
- def include_files_code
61
- lambda do |code|
62
- @include_files.each { |file| code << file << nl }
63
- end
64
- end
65
-
66
- def signal_declarations
67
- lambda do |code|
68
- signals.each { |signal| code << signal << semicolon << nl }
69
- end
70
- end
71
-
72
- def declarations(list, code)
73
- indent(code, 2) do
74
- list.each_with_index do |d, i|
75
- code << comma << nl if i > 0
76
- code << d
77
- end
78
- end
79
- end
80
- end
81
- end
82
- end
@@ -1,57 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class PackageDefinition < StructureDefinition
4
- ImportedPackage = Struct.new(:name, :items) do
5
- def to_s
6
- "import #{import_items.join(', ')};"
7
- end
8
-
9
- def import_items
10
- (((items.nil? || items.empty?) && [:*]) || items).map do |item|
11
- "#{name}::#{item}"
12
- end
13
- end
14
- end
15
-
16
- def import_package(name, items = nil)
17
- @import_packages ||= []
18
- @import_packages << ImportedPackage.new(name, items)
19
- end
20
-
21
- def include_file(name)
22
- @include_files ||= []
23
- @include_files << "`include #{name.to_s.quote}"
24
- end
25
-
26
- private
27
-
28
- def header_code
29
- "package #{@name};"
30
- end
31
-
32
- def body_code_blocks
33
- blocks = []
34
- @import_packages && (blocks << import_packges_code)
35
- @include_files && (blocks << include_files_code)
36
- blocks.concat(super)
37
- blocks
38
- end
39
-
40
- def footer_code
41
- :endpackage
42
- end
43
-
44
- def import_packges_code
45
- lambda do |code|
46
- @import_packages.each { |package| code << package << nl }
47
- end
48
- end
49
-
50
- def include_files_code
51
- lambda do |code|
52
- @include_files.each { |file| code << file << nl }
53
- end
54
- end
55
- end
56
- end
57
- end
@@ -1,10 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class SourceFile < CodeUtility::SourceFile
4
- ifndef_keyword :'`ifndef'
5
- endif_keyword :'`endif'
6
- define_keyword :'`define'
7
- include_keyword :'`include'
8
- end
9
- end
10
- end
@@ -1,51 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class StructureDefinition
4
- include CodeUtility
5
-
6
- def initialize(name)
7
- @name = name
8
- yield(self) if block_given?
9
- end
10
-
11
- def body(&block)
12
- @bodies ||= []
13
- @bodies << block if block_given?
14
- end
15
-
16
- def to_code
17
- code_block do |code|
18
- code << header_code << nl
19
- body_code(code) if body_code?
20
- code << footer_code << nl
21
- end
22
- end
23
-
24
- private
25
-
26
- def body_code(code)
27
- body_code_blocks.each do |body|
28
- generate_body_code(code, body)
29
- end
30
- end
31
-
32
- def body_code_blocks
33
- @bodies || []
34
- end
35
-
36
- def generate_body_code(code, body)
37
- indent(code, 2) do
38
- if body.arity.zero?
39
- code << body.call
40
- else
41
- body.call(code)
42
- end
43
- end
44
- end
45
-
46
- def body_code?
47
- !(@bodies.nil? || @bodies.empty?)
48
- end
49
- end
50
- end
51
- end
@@ -1,41 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class SubroutineDefinition < StructureDefinition
4
- def initialize(type, name, &body)
5
- @type = type
6
- super(name, &body)
7
- end
8
-
9
- def return_type(data_type_and_width)
10
- if [Symbol, String].any?(&data_type_and_width.method(:is_a?))
11
- @return_type = data_type_and_width
12
- else
13
- data_type = data_type_and_width[:data_type]
14
- width = data_type_and_width[:width ] || 1
15
- @return_type =
16
- ((width > 1) && "#{data_type} [#{width - 1}:0]") || data_type
17
- end
18
- end
19
-
20
- attr_setter :arguments
21
-
22
- private
23
-
24
- def function?
25
- @type == :function
26
- end
27
-
28
- def header_code
29
- [
30
- (function? && :function ) || :task,
31
- (function? && @return_type) || nil,
32
- "#{@name}(#{Array(@arguments).join(', ')});"
33
- ].compact.join(' ')
34
- end
35
-
36
- def footer_code
37
- (function? && :endfunction) || :endtask
38
- end
39
- end
40
- end
41
- end
@@ -1,115 +0,0 @@
1
- module RgGen
2
- module VerilogUtility
3
- class Variable
4
- def initialize(variable_type, attributes)
5
- @variable_type = variable_type
6
- @attributes = attributes
7
- end
8
-
9
- def to_s
10
- code_snippets.join(' ')
11
- end
12
-
13
- def identifier
14
- name = @attributes[:name]
15
- width = @attributes[:width] || 1
16
- dimensions = @attributes[:dimensions]
17
- array_fomrat = @attributes[:array_format] || :unpacked
18
- Identifier.new(name, width, dimensions, array_fomrat)
19
- end
20
-
21
- private
22
-
23
- def code_snippets
24
- [
25
- rand_keyword,
26
- port_direction,
27
- parameter_keyword,
28
- data_type,
29
- width,
30
- variable_identifier,
31
- default_value_assignment
32
- ].select(&:itself)
33
- end
34
-
35
- def rand_keyword
36
- @variable_type == :variable && @attributes[:random] && :rand
37
- end
38
-
39
- def port_direction
40
- @variable_type == :port && @attributes[:direction]
41
- end
42
-
43
- def parameter_keyword
44
- @variable_type == :parameter && @attributes[:parameter_type]
45
- end
46
-
47
- def data_type
48
- @attributes[:data_type]
49
- end
50
-
51
- def width
52
- vector? || return
53
- msb =
54
- if numerical_width?
55
- vectored_array_size * (@attributes[:width] || 1) - 1
56
- elsif vectored_array?
57
- "#{vectored_array_size}*#{@attributes[:width]}-1"
58
- else
59
- "#{@attributes[:width]}-1"
60
- end
61
- "[#{msb}:0]"
62
- end
63
-
64
- def vectored_array_size
65
- vectored_array? || (return 1)
66
- @attributes[:dimensions].inject(&:*)
67
- end
68
-
69
- def variable_identifier
70
- "#{@attributes[:name]}#{dimensions}"
71
- end
72
-
73
- def dimensions
74
- unpacked_array? || return
75
- @attributes[:dimensions].map { |dimension| "[#{dimension}]" }.join
76
- end
77
-
78
- def default_value_assignment
79
- @attributes[:default] || return
80
- "= #{@attributes[:default]}"
81
- end
82
-
83
- def parameter?
84
- @variable_type == :parameter
85
- end
86
-
87
- def vector?
88
- @attributes[:vector] && (return true)
89
- vectored_array? && (return true)
90
- @attributes[:width] || (return false)
91
- numerical_width? || (return true)
92
- parameter? && (return true)
93
- @attributes[:width] > 1
94
- end
95
-
96
- def numerical_width?
97
- @attributes[:width] || (return true)
98
- @attributes[:width].is_a?(Integer) && (return true)
99
- false
100
- end
101
-
102
- def unpacked_array?
103
- @attributes[:dimensions] || (return false)
104
- @attributes[:array_format] == :vectored && (return false)
105
- true
106
- end
107
-
108
- def vectored_array?
109
- @attributes[:dimensions] || (return false)
110
- @attributes[:array_format] == :vectored && (return true)
111
- false
112
- end
113
- end
114
- end
115
- end