rggen 0.8.2 → 0.9.0

data/sample/block_1_ral_pkg.sv

@@ -0,0 +1,68 @@
+package block_1_ral_pkg;
+  import uvm_pkg::*;
+  import rggen_ral_pkg::*;
+  `include "uvm_macros.svh"
+  `include "rggen_ral_macros.svh"
+  class register_0_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0[4];
+    rand rggen_ral_field bit_field_1[4];
+    function new(string name);
+      super.new(name, 64, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RO, 1, 8'h00, 0)
+    endfunction
+  endclass
+  class register_1_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0[4];
+    rand rggen_ral_field bit_field_1[4];
+    function new(string name);
+      super.new(name, 64, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RO, 1, 8'h00, 0)
+      `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
+    endfunction
+  endclass
+  class block_1_block_model extends rggen_ral_block;
+    rand register_0_reg_model register_0[2][4];
+    rand register_1_reg_model register_1[2][4];
+    function new(string name);
+      super.new(name);
+    endfunction
+    function void build();
+      `rggen_ral_create_reg_model(register_0[0][0], '{0, 0}, 7'h00, RW, 0, g_register_0.g[0].g[0].u_register)
+      `rggen_ral_create_reg_model(register_0[0][1], '{0, 1}, 7'h08, RW, 0, g_register_0.g[0].g[1].u_register)
+      `rggen_ral_create_reg_model(register_0[0][2], '{0, 2}, 7'h10, RW, 0, g_register_0.g[0].g[2].u_register)
+      `rggen_ral_create_reg_model(register_0[0][3], '{0, 3}, 7'h18, RW, 0, g_register_0.g[0].g[3].u_register)
+      `rggen_ral_create_reg_model(register_0[1][0], '{1, 0}, 7'h20, RW, 0, g_register_0.g[1].g[0].u_register)
+      `rggen_ral_create_reg_model(register_0[1][1], '{1, 1}, 7'h28, RW, 0, g_register_0.g[1].g[1].u_register)
+      `rggen_ral_create_reg_model(register_0[1][2], '{1, 2}, 7'h30, RW, 0, g_register_0.g[1].g[2].u_register)
+      `rggen_ral_create_reg_model(register_0[1][3], '{1, 3}, 7'h38, RW, 0, g_register_0.g[1].g[3].u_register)
+      `rggen_ral_create_reg_model(register_1[0][0], '{0, 0}, 7'h40, RW, 0, g_register_1.g[0].g[0].u_register)
+      `rggen_ral_create_reg_model(register_1[0][1], '{0, 1}, 7'h48, RW, 0, g_register_1.g[0].g[1].u_register)
+      `rggen_ral_create_reg_model(register_1[0][2], '{0, 2}, 7'h50, RW, 0, g_register_1.g[0].g[2].u_register)
+      `rggen_ral_create_reg_model(register_1[0][3], '{0, 3}, 7'h58, RW, 0, g_register_1.g[0].g[3].u_register)
+      `rggen_ral_create_reg_model(register_1[1][0], '{1, 0}, 7'h60, RW, 0, g_register_1.g[1].g[0].u_register)
+      `rggen_ral_create_reg_model(register_1[1][1], '{1, 1}, 7'h68, RW, 0, g_register_1.g[1].g[1].u_register)
+      `rggen_ral_create_reg_model(register_1[1][2], '{1, 2}, 7'h70, RW, 0, g_register_1.g[1].g[2].u_register)
+      `rggen_ral_create_reg_model(register_1[1][3], '{1, 3}, 7'h78, RW, 0, g_register_1.g[1].g[3].u_register)
+    endfunction
+    function uvm_reg_map create_default_map();
+      return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
+    endfunction
+  endclass
+endpackage

data/sample/config.json

@@ -0,0 +1,5 @@
+{
+  "bus_width":      32,
+  "address_width":  16,
+  "protocol":       "apb"
+}

data/sample/config.yml

@@ -0,0 +1,3 @@
+bus_width:      32
+address_width:  16
+protocol:       apb

metadata

@@ -1,331 +1,157 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.8.2
+  version: 0.9.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-05-26 00:00:00.000000000 Z
+date: 2019-07-26 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
-  name: erubi
+  name: rggen-core
   requirement: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '1.7'
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '1.7'
-- !ruby/object:Gem::Dependency
-  name: facets
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '3.0'
+        version: '0.9'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '3.0'
+        version: '0.9'
 - !ruby/object:Gem::Dependency
-  name: roo
+  name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: 2.1.1
+        version: '0.9'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: 2.1.1
+        version: '0.9'
 - !ruby/object:Gem::Dependency
-  name: spreadsheet
+  name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: 1.0.3
+        version: '0.9'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.0.3
-- !ruby/object:Gem::Dependency
-  name: rake
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '10.0'
-  type: :development
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '10.0'
-- !ruby/object:Gem::Dependency
-  name: rspec
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: '3.3'
-  type: :development
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
+    - - "~>"
       - !ruby/object:Gem::Version
-        version: '3.3'
+        version: '0.9'
 - !ruby/object:Gem::Dependency
-  name: rubocop
+  name: bundler
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.35'
+        version: '0'
   type: :development
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: '0.35'
-description: |2
-      RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
-      It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
-      Also RgGen is customizable so you can build your specific generate tool.
+        version: '0'
+description: |
+  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
+  It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
+  from human readable register map documents.
 email:
 - taichi730@gmail.com
-executables:
-- rggen
+executables: []
 extensions: []
 extra_rdoc_files: []
 files:
 - CODE_OF_CONDUCT.md
-- LICENSE.txt
+- LICENSE
 - README.md
-- bin/rggen
-- c_header/LICENSE
-- c_header/rggen.h
 - lib/rggen.rb
-- lib/rggen/base/component.rb
-- lib/rggen/base/component_factory.rb
-- lib/rggen/base/hierarchical_accessors.rb
-- lib/rggen/base/hierarchical_item_accessors.rb
-- lib/rggen/base/internal_struct.rb
-- lib/rggen/base/item.rb
-- lib/rggen/base/item_factory.rb
-- lib/rggen/builder/builder.rb
-- lib/rggen/builder/category.rb
-- lib/rggen/builder/component_entry.rb
-- lib/rggen/builder/component_store.rb
-- lib/rggen/builder/input_component_store.rb
-- lib/rggen/builder/item_store.rb
-- lib/rggen/builder/list_item_entry.rb
-- lib/rggen/builder/output_component_store.rb
-- lib/rggen/builder/simple_item_entry.rb
-- lib/rggen/builtins.rb
-- lib/rggen/builtins/bit_field/bit_assignment.rb
-- lib/rggen/builtins/bit_field/field_model.rb
-- lib/rggen/builtins/bit_field/initial_value.rb
-- lib/rggen/builtins/bit_field/name.rb
-- lib/rggen/builtins/bit_field/reference.rb
-- lib/rggen/builtins/bit_field/rtl_top.rb
-- lib/rggen/builtins/bit_field/type.rb
-- lib/rggen/builtins/bit_field/types/reserved.erb
-- lib/rggen/builtins/bit_field/types/reserved.rb
-- lib/rggen/builtins/bit_field/types/ro.erb
-- lib/rggen/builtins/bit_field/types/ro.rb
-- lib/rggen/builtins/bit_field/types/rw.erb
-- lib/rggen/builtins/bit_field/types/rw.rb
-- lib/rggen/builtins/bit_field/types/rwl_rwe.erb
-- lib/rggen/builtins/bit_field/types/rwl_rwe.rb
-- lib/rggen/builtins/bit_field/types/w0c_w1c.erb
-- lib/rggen/builtins/bit_field/types/w0c_w1c.rb
-- lib/rggen/builtins/bit_field/types/w0s_w1s.erb
-- lib/rggen/builtins/bit_field/types/w0s_w1s.rb
-- lib/rggen/builtins/bit_field/types/wo.rb
-- lib/rggen/builtins/global/address_width.rb
-- lib/rggen/builtins/global/array_port_format.rb
-- lib/rggen/builtins/global/data_width.rb
-- lib/rggen/builtins/global/unfold_sv_interface_port.rb
-- lib/rggen/builtins/loaders/configuration/json_loader.rb
-- lib/rggen/builtins/loaders/configuration/yaml_loader.rb
-- lib/rggen/builtins/loaders/register_map/csv_loader.rb
-- lib/rggen/builtins/loaders/register_map/xls_loader.rb
-- lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb
-- lib/rggen/builtins/register/array.rb
-- lib/rggen/builtins/register/constructor.rb
-- lib/rggen/builtins/register/field_model_creator.rb
-- lib/rggen/builtins/register/indirect_index_configurator.rb
-- lib/rggen/builtins/register/name.rb
-- lib/rggen/builtins/register/offset_address.rb
-- lib/rggen/builtins/register/reg_model.rb
-- lib/rggen/builtins/register/rtl_top.rb
-- lib/rggen/builtins/register/sub_block_model.rb
-- lib/rggen/builtins/register/type.rb
-- lib/rggen/builtins/register/types/default.erb
-- lib/rggen/builtins/register/types/external.erb
-- lib/rggen/builtins/register/types/external.rb
-- lib/rggen/builtins/register/types/indirect.erb
-- lib/rggen/builtins/register/types/indirect.rb
-- lib/rggen/builtins/register/uniqueness_validator.rb
-- lib/rggen/builtins/register_block/address_struct.rb
-- lib/rggen/builtins/register_block/base_address.rb
-- lib/rggen/builtins/register_block/block_model.rb
-- lib/rggen/builtins/register_block/byte_size.rb
-- lib/rggen/builtins/register_block/c_header_file.rb
-- lib/rggen/builtins/register_block/clock_reset.rb
-- lib/rggen/builtins/register_block/constructor.rb
-- lib/rggen/builtins/register_block/default_map_creator.rb
-- lib/rggen/builtins/register_block/host_if.rb
-- lib/rggen/builtins/register_block/host_ifs/apb.erb
-- lib/rggen/builtins/register_block/host_ifs/apb.rb
-- lib/rggen/builtins/register_block/host_ifs/axi4lite.erb
-- lib/rggen/builtins/register_block/host_ifs/axi4lite.rb
-- lib/rggen/builtins/register_block/name.rb
-- lib/rggen/builtins/register_block/ral_package.rb
-- lib/rggen/builtins/register_block/rtl_top.rb
-- lib/rggen/builtins/register_block/sub_model_creator.rb
-- lib/rggen/commands.rb
-- lib/rggen/core_components.rb
-- lib/rggen/core_components/c_header/item.rb
-- lib/rggen/core_components/c_header/setup.rb
-- lib/rggen/core_components/c_utility.rb
-- lib/rggen/core_components/c_utility/data_structure_definition.rb
-- lib/rggen/core_components/c_utility/source_file.rb
-- lib/rggen/core_components/c_utility/variable_declaration.rb
-- lib/rggen/core_components/code_utility.rb
-- lib/rggen/core_components/code_utility/code_block.rb
-- lib/rggen/core_components/code_utility/line.rb
-- lib/rggen/core_components/code_utility/source_file.rb
-- lib/rggen/core_components/configuration/configuration_factory.rb
-- lib/rggen/core_components/configuration/item.rb
-- lib/rggen/core_components/configuration/item_factory.rb
-- lib/rggen/core_components/configuration/raise_error.rb
-- lib/rggen/core_components/configuration/setup.rb
-- lib/rggen/core_components/erb_engine.rb
-- lib/rggen/core_components/ral/component.rb
-- lib/rggen/core_components/ral/item.rb
-- lib/rggen/core_components/ral/setup.rb
-- lib/rggen/core_components/register_map/bit_field_factory.rb
-- lib/rggen/core_components/register_map/component.rb
-- lib/rggen/core_components/register_map/component_factory.rb
-- lib/rggen/core_components/register_map/generic_map.rb
-- lib/rggen/core_components/register_map/item.rb
-- lib/rggen/core_components/register_map/item_factory.rb
-- lib/rggen/core_components/register_map/loader.rb
-- lib/rggen/core_components/register_map/raise_error.rb
-- lib/rggen/core_components/register_map/register_block_factory.rb
-- lib/rggen/core_components/register_map/register_factory.rb
-- lib/rggen/core_components/register_map/register_map_factory.rb
-- lib/rggen/core_components/register_map/setup.rb
-- lib/rggen/core_components/rtl/component.rb
-- lib/rggen/core_components/rtl/item.rb
-- lib/rggen/core_components/rtl/setup.rb
-- lib/rggen/core_components/verilog_utility.rb
-- lib/rggen/core_components/verilog_utility/class_definition.rb
-- lib/rggen/core_components/verilog_utility/identifier.rb
-- lib/rggen/core_components/verilog_utility/interface_instance.rb
-- lib/rggen/core_components/verilog_utility/interface_port.rb
-- lib/rggen/core_components/verilog_utility/local_scope.rb
-- lib/rggen/core_components/verilog_utility/module_definition.rb
-- lib/rggen/core_components/verilog_utility/package_definition.rb
-- lib/rggen/core_components/verilog_utility/source_file.rb
-- lib/rggen/core_components/verilog_utility/structure_definition.rb
-- lib/rggen/core_components/verilog_utility/subroutine_definition.rb
-- lib/rggen/core_components/verilog_utility/variable.rb
-- lib/rggen/core_extensions/array.rb
-- lib/rggen/core_extensions/facets.rb
-- lib/rggen/core_extensions/forwardable.rb
-- lib/rggen/core_extensions/integer.rb
-- lib/rggen/core_extensions/math.rb
-- lib/rggen/core_extensions/roo.rb
-- lib/rggen/exceptions.rb
-- lib/rggen/generator.rb
-- lib/rggen/input_base/component.rb
-- lib/rggen/input_base/component_factory.rb
-- lib/rggen/input_base/item.rb
-- lib/rggen/input_base/item_factory.rb
-- lib/rggen/input_base/loader.rb
-- lib/rggen/input_base/regexp_patterns.rb
-- lib/rggen/option_switches.rb
-- lib/rggen/options.rb
-- lib/rggen/output_base/code_generator.rb
-- lib/rggen/output_base/component.rb
-- lib/rggen/output_base/component_factory.rb
-- lib/rggen/output_base/file_writer.rb
-- lib/rggen/output_base/item.rb
-- lib/rggen/output_base/item_factory.rb
-- lib/rggen/output_base/template_engine.rb
-- lib/rggen/rggen_home.rb
+- lib/rggen/built_in.rb
+- lib/rggen/built_in/bit_field/bit_assignment.rb
+- lib/rggen/built_in/bit_field/comment.rb
+- lib/rggen/built_in/bit_field/initial_value.rb
+- lib/rggen/built_in/bit_field/name.rb
+- lib/rggen/built_in/bit_field/reference.rb
+- lib/rggen/built_in/bit_field/sv_rtl_top.rb
+- lib/rggen/built_in/bit_field/type.rb
+- lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb
+- lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/built_in/bit_field/type/reserved.erb
+- lib/rggen/built_in/bit_field/type/reserved.rb
+- lib/rggen/built_in/bit_field/type/ro.erb
+- lib/rggen/built_in/bit_field/type/ro.rb
+- lib/rggen/built_in/bit_field/type/rof.erb
+- lib/rggen/built_in/bit_field/type/rof.rb
+- lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb
+- lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/built_in/bit_field/type/rw_wo.erb
+- lib/rggen/built_in/bit_field/type/rw_wo.rb
+- lib/rggen/built_in/bit_field/type/rwe_rwl.erb
+- lib/rggen/built_in/bit_field/type/rwe_rwl.rb
+- lib/rggen/built_in/global/address_width.rb
+- lib/rggen/built_in/global/array_port_format.rb
+- lib/rggen/built_in/global/bus_width.rb
+- lib/rggen/built_in/global/fold_sv_interface_port.rb
+- lib/rggen/built_in/register/name.rb
+- lib/rggen/built_in/register/offset_address.rb
+- lib/rggen/built_in/register/size.rb
+- lib/rggen/built_in/register/sv_rtl_top.rb
+- lib/rggen/built_in/register/type.rb
+- lib/rggen/built_in/register/type/default_sv_ral.erb
+- lib/rggen/built_in/register/type/default_sv_rtl.erb
+- lib/rggen/built_in/register/type/external.erb
+- lib/rggen/built_in/register/type/external.rb
+- lib/rggen/built_in/register/type/indirect.rb
+- lib/rggen/built_in/register/type/indirect_sv_ral.erb
+- lib/rggen/built_in/register/type/indirect_sv_rtl.erb
+- lib/rggen/built_in/register_block/byte_size.rb
+- lib/rggen/built_in/register_block/name.rb
+- lib/rggen/built_in/register_block/protocol.rb
+- lib/rggen/built_in/register_block/protocol/apb.erb
+- lib/rggen/built_in/register_block/protocol/apb.rb
+- lib/rggen/built_in/register_block/protocol/axi4lite.erb
+- lib/rggen/built_in/register_block/protocol/axi4lite.rb
+- lib/rggen/built_in/register_block/sv_ral_block_model.erb
+- lib/rggen/built_in/register_block/sv_ral_package.rb
+- lib/rggen/built_in/register_block/sv_rtl_macros.erb
+- lib/rggen/built_in/register_block/sv_rtl_top.rb
+- lib/rggen/built_in/version.rb
+- lib/rggen/default_setup_file.rb
+- lib/rggen/setup/default.rb
 - lib/rggen/version.rb
-- ral/LICENSE
-- ral/compile.f
-- ral/rggen_ral_block.svh
-- ral/rggen_ral_field.svh
-- ral/rggen_ral_field_rwl_rwe.svh
-- ral/rggen_ral_indirect_reg.svh
-- ral/rggen_ral_macros.svh
-- ral/rggen_ral_map.svh
-- ral/rggen_ral_pkg.sv
-- ral/rggen_ral_reg.svh
-- rtl/LICENSE
-- rtl/compile.f
-- rtl/rggen_address_decoder.sv
-- rtl/rggen_apb_if.sv
-- rtl/rggen_axi4lite_if.sv
-- rtl/rggen_bit_field_if.sv
-- rtl/rggen_bit_field_ro.sv
-- rtl/rggen_bit_field_rw.sv
-- rtl/rggen_bit_field_rwl_rwe.sv
-- rtl/rggen_bit_field_w01s_w01c.sv
-- rtl/rggen_bus_if.sv
-- rtl/rggen_bus_splitter.sv
-- rtl/rggen_default_register.sv
-- rtl/rggen_external_register.sv
-- rtl/rggen_host_if_apb.sv
-- rtl/rggen_host_if_axi4lite.sv
-- rtl/rggen_indirect_register.sv
-- rtl/rggen_register_base.sv
-- rtl/rggen_register_if.sv
-- rtl/rggen_rtl_pkg.sv
-- sample/LICENSE
-- sample/sample.csv
-- sample/sample.json
-- sample/sample.xls
-- sample/sample.xlsx
-- sample/sample.yaml
-- sample/sample_0.h
-- sample/sample_0.sv
-- sample/sample_0_ral_pkg.sv
-- sample/sample_1.h
-- sample/sample_1.sv
-- sample/sample_1_ral_pkg.sv
-- sample/sample_setup.rb
-- setup/default.rb
-homepage: https://github.com/taichi-ishitani/rggen
+- sample/block_0.rb
+- sample/block_0.sv
+- sample/block_0.xlsx
+- sample/block_0.yml
+- sample/block_0_ral_pkg.sv
+- sample/block_1.rb
+- sample/block_1.sv
+- sample/block_1.xlsx
+- sample/block_1.yml
+- sample/block_1_ral_pkg.sv
+- sample/config.json
+- sample/config.yml
+homepage: https://github.com/rggen/rggen
 licenses:
 - MIT
-metadata: {}
+metadata:
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
+  source_code_uri: https://github.com/rggen/rggen
+  wiki_uri: https://github.com/rggen/rggen/wiki
 post_install_message: 
 rdoc_options: []
 require_paths:
@@ -344,5 +170,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: Code generation tool for control registers in a SoC design.
+summary: Code generation tool for control/status registers
 test_files: []