rggen 0.8.2 → 0.9.0

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb

@@ -0,0 +1,15 @@
+<%= module_name %> #(
+<% if [:w0c, :w1c].include?(bit_field.type) %>
+  .CLEAR_VALUE    (<%= clear_value %>),
+<% end %>
+  .WIDTH          (<%= bit_field.width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk            (<%= register_block.clock %>),
+  .i_rst_n          (<%= register_block.reset%>),
+  .bit_field_if     (<%= bit_field.bit_field_sub_if %>),
+  .i_set            (<%= set[bit_field.loop_variables] %>),
+  .i_mask           (<%= mask %>),
+  .o_value          (<%= value_out[bit_field.loop_variables] %>),
+  .o_value_unmasked (<%= value_out_unmasked %>)
+);

data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rc) do
+  register_map do
+    read_only
+    use_reference
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0c, :w1c]) do
+  register_map do
+    read_write
+    use_reference
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
+  sv_rtl do
+    build do
+      input :register_block, :set, {
+        name: "i_#{full_name}_set",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+      output :register_block, :value_out, {
+        name: "o_#{full_name}",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+      if bit_field.reference?
+        output :register_block, :value_unmasked, {
+          name: "o_#{full_name}_unmasked",
+          data_type: :logic,
+          width: bit_field.width,
+          array_size: bit_field.array_size,
+          array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def module_name
+      if bit_field.type == :rc
+        'rggen_bit_field_rc'
+      else
+        'rggen_bit_field_w01c'
+      end
+    end
+
+    def clear_value
+      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
+    end
+
+    def value_out_unmasked
+      (bit_field.reference? || nil) &&
+        value_unmasked[bit_field.loop_variables]
+    end
+  end
+end

data/lib/rggen/built_in/bit_field/type/reserved.erb

@@ -0,0 +1,3 @@
+rggen_bit_field_reserved u_bit_field (
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>)
+);

data/lib/rggen/built_in/bit_field/type/reserved.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
+  register_map do
+    reserved
+    non_volatile
+  end
+
+  sv_rtl do
+    main_code :bit_field, from_template: true
+  end
+
+  sv_ral do
+    access 'RO'
+  end
+end

data/lib/rggen/built_in/bit_field/type/ro.erb

@@ -0,0 +1,6 @@
+rggen_bit_field_ro #(
+  .WIDTH  (<%= bit_field.width %>)
+) u_bit_field (
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .i_value      (<%= reference_or_value_in %>)
+);

data/lib/rggen/built_in/bit_field/type/ro.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :ro) do
+  register_map do
+    read_only
+    use_reference
+  end
+
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :register_block, :value_in, {
+          name: "i_#{full_name}",
+          data_type: :logic,
+          width: bit_field.width,
+          array_size: bit_field.array_size,
+          array_format: array_port_format
+        }
+      end
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def reference_or_value_in
+      if bit_field.reference?
+        reference_bit_field
+      else
+        value_in[bit_field.loop_variables]
+      end
+    end
+  end
+end

data/lib/rggen/built_in/bit_field/type/rof.erb

@@ -0,0 +1,6 @@
+rggen_bit_field_ro #(
+  .WIDTH  (<%= bit_field.width %>)
+) u_bit_field (
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .i_value      (<%= initial_value %>)
+);

data/lib/rggen/built_in/bit_field/type/rof.rb

@@ -0,0 +1,17 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rof) do
+  register_map do
+    read_only
+    non_volatile
+    need_initial_value
+  end
+
+  sv_rtl do
+    main_code :bit_field, from_template: true
+  end
+
+  sv_ral do
+    access 'RO'
+  end
+end

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb

@@ -0,0 +1,13 @@
+<%= module_name %> #(
+<% if [:w0s, :w1s].include?(bit_field.type) %>
+  .SET_VALUE      (<%= set_value %>),
+<% end %>
+  .WIDTH          (<%= bit_field.width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .i_clear      (<%= clear[bit_field.loop_variables] %>),
+  .o_value      (<%= value_out[bit_field.loop_variables] %>)
+);

data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb

@@ -0,0 +1,52 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rs) do
+  register_map do
+    read_only
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0s, :w1s]) do
+  register_map do
+    read_write
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+  sv_rtl do
+    build do
+      input :register_block, :clear, {
+        name: "i_#{full_name}_clear",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+      output :register_block, :value_out, {
+        name: "o_#{full_name}",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def module_name
+      if bit_field.type == :rs
+        'rggen_bit_field_rs'
+      else
+        'rggen_bit_field_w01s'
+      end
+    end
+
+    def set_value
+      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/built_in/bit_field/type/rw_wo.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= bit_field.width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+  .o_value      (<%= value_out[bit_field.loop_variables] %>)
+);

data/lib/rggen/built_in/bit_field/type/rw_wo.rb

@@ -0,0 +1,33 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rw) do
+  register_map do
+    read_write
+    non_volatile
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, :wo) do
+  register_map do
+    write_only
+    non_volatile
+    need_initial_value
+  end
+end
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :wo]) do
+  sv_rtl do
+    build do
+      output :register_block, :value_out, {
+        name: "o_#{full_name}",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb

@@ -0,0 +1,14 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= bit_field.width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .bit_field_if (<%= bit_field.bit_field_sub_if %>),
+<% if bit_field.type == :rwe %>
+  .i_enable     (<%= reference_bit_field %>),
+<% else %>
+  .i_lock       (<%= reference_bit_field %>),
+<% end %>
+  .o_value      (<%= value_out[bit_field.loop_variables] %>)
+);

data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  register_map do
+    read_write
+    non_volatile
+    need_initial_value
+    use_reference required: true, width: 1
+  end
+
+  sv_rtl do
+    build do
+      output :register_block, :value_out, {
+        name: "o_#{full_name}",
+        data_type: :logic,
+        width: bit_field.width,
+        array_size: bit_field.array_size,
+        array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+
+  sv_ral do
+    model_name do
+      "rggen_ral_#{bit_field.type}_field #(#{reference_names})"
+    end
+
+    private
+
+    def reference_names
+      reference = bit_field.find_reference(register_block.bit_fields)
+      [reference.register.name, reference.name]
+        .map { |name| string(name) }
+        .join(', ')
+    end
+  end
+end

data/lib/rggen/built_in/global/address_width.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :address_width) do
+  configuration do
+    property :address_width, default: 32
+
+    build do |value|
+      @address_width =
+        begin
+          Integer(value)
+        rescue ArgumentError, TypeError
+          error "cannot convert #{value.inspect} into address width"
+        end
+    end
+
+    verify(:component) do
+      error_condition { address_width < min_address_width }
+      message do
+        'input address width is less than minimum address width: ' \
+        "address width #{address_width} " \
+        "minimum address width #{min_address_width}"
+      end
+    end
+
+    private
+
+    def min_address_width
+      byte_width = configuration.byte_width
+      byte_width == 1 ? 1 : (byte_width - 1).bit_length
+    end
+  end
+end

data/lib/rggen/built_in/global/array_port_format.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :array_port_format) do
+  configuration do
+    property :array_port_format, default: :packed
+
+    input_pattern /(packed|unpacked|vectorized)/i
+    ignore_empty_value false
+
+    build do |value|
+      @array_port_format =
+        if pattern_matched?
+          match_data[1].downcase.to_sym
+        else
+          error "illegal input value for array port format: #{value.inspect}"
+        end
+    end
+  end
+end

data/lib/rggen/built_in/global/bus_width.rb

@@ -0,0 +1,33 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :bus_width) do
+  configuration do
+    property :bus_width, default: 32
+    property :byte_width, body: -> { bus_width / 8 }
+
+    build do |value|
+      @bus_width =
+        begin
+          Integer(value)
+        rescue ArgumentError, TypeError
+          error "cannot convert #{value.inspect} into bus width"
+        end
+    end
+
+    verify(:feature) do
+      error_condition { bus_width < 8 }
+      message { "input bus width is less than 8: #{bus_width}" }
+    end
+
+    verify(:feature) do
+      error_condition { !power_of_2?(bus_width) }
+      message { "input bus width is not power of 2: #{bus_width}" }
+    end
+
+    private
+
+    def power_of_2?(value)
+      value.positive? && (value & value.pred).zero?
+    end
+  end
+end

data/lib/rggen/built_in/global/fold_sv_interface_port.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:global, :fold_sv_interface_port) do
+  configuration do
+    property :fold_sv_interface_port?, default: true
+
+    input_pattern [
+      /true|on|yes/i, /false|off|no/i
+    ], match_automatically: false
+
+    ignore_empty_value false
+
+    build do |value|
+      @fold_sv_interface_port =
+        if [true, false].include?(value)
+          value
+        elsif match_pattern(value)
+          [true, false][match_index]
+        else
+          error "cannot convert #{value.inspect} into boolean"
+        end
+    end
+  end
+end