rggen 0.8.2 → 0.9.0

data/lib/rggen/built_in/register/type/indirect_sv_ral.erb

@@ -0,0 +1,13 @@
+function new(string name);
+  super.new(name, <%= register.width%>, 0);
+endfunction
+function void build();
+<% field_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end%>
+endfunction
+function void setup_index_fields();
+<% index_properties.each do |reg_name, field_name, value| %>
+  setup_index_field("<%= reg_name %>", "<%= field_name%>", <%= value %>);
+<% end %>
+endfunction

data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb

@@ -0,0 +1,17 @@
+rggen_indirect_register #(
+  .READABLE             (<%= readable %>),
+  .WRITABLE             (<%= writable %>),
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .OFFSET_ADDRESS       (<%= offset_address %>),
+  .BUS_WIDTH            (<%= configuration.bus_width %>),
+  .DATA_WIDTH           (<%= register.width %>),
+  .VALID_BITS           (<%= valid_bits %>),
+  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
+  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+) u_register (
+  .i_clk            (<%= register_block.clock %>),
+  .i_rst_n          (<%= register_block.reset %>),
+  .register_if      (<%= register_if %>),
+  .i_indirect_index (<%= indirect_index %>),
+  .bit_field_if     (<%= register.bit_field_if %>)
+);

data/lib/rggen/built_in/register_block/byte_size.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :byte_size) do
+  register_map do
+    property :byte_size
+    property :local_address_width
+
+    build do |value|
+      @byte_size =
+        begin
+          Integer(value)
+        rescue ArgumentError, TypeError
+          error "cannot convert #{value.inspect} into byte size"
+        end
+      @local_address_width = (@byte_size - 1).bit_length
+    end
+
+    verify(:feature) do
+      error_condition { !byte_size }
+      message { 'no byte size is given' }
+    end
+
+    verify(:feature) do
+      error_condition { !byte_size.positive? }
+      message do
+        "non positive value is not allowed for byte size: #{byte_size}"
+      end
+    end
+
+    verify(:feature) do
+      error_condition { byte_size > max_byte_size }
+      message do
+        'input byte size is greater than maximum byte size: ' \
+        "input byte size #{byte_size} maximum byte size #{max_byte_size}"
+      end
+    end
+
+    verify(:feature) do
+      error_condition { (byte_size % byte_width).positive? }
+      message do
+        "byte size is not aligned with bus width(#{bus_width}): #{byte_size}"
+      end
+    end
+
+    private
+
+    def max_byte_size
+      2**configuration.address_width
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+  end
+end

data/lib/rggen/built_in/register_block/name.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :name) do
+  register_map do
+    property :name
+
+    input_pattern variable_name
+
+    build do |value|
+      @name =
+        if pattern_matched?
+          match_data.to_s
+        else
+          error "illegal input value for register block name: #{value.inspect}"
+        end
+    end
+
+    verify(:feature) do
+      error_condition { !name }
+      message { 'no register block name is given' }
+    end
+
+    verify(:feature) do
+      error_condition { duplicated_name? }
+      message { "duplicated register block name: #{name}" }
+    end
+
+    private
+
+    def duplicated_name?
+      register_map
+        .register_blocks
+        .any? { |register_block| register_block.name == name }
+    end
+  end
+end

data/lib/rggen/built_in/register_block/protocol.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+RgGen.define_list_feature(:register_block, :protocol) do
+  shared_context do
+    def feature_registry(registry = nil)
+      @registry = registry if registry
+      @registry
+    end
+
+    def available_protocols
+      feature_registry
+        .enabled_features(:protocol)
+        .select(&method(:valid_protocol?))
+    end
+
+    def valid_protocol?(protocol)
+      feature_registry.feature?(:protocol, protocol)
+    end
+  end
+
+  configuration do
+    base_feature do
+      property :protocol
+      build { |protocol| @protocol = protocol }
+    end
+
+    default_feature do
+    end
+
+    factory do
+      convert_value do |value, position|
+        protocol = find_protocol(value)
+        protocol ||
+          (error "unknown protocol: #{value.inspect}", position)
+      end
+
+      default_value do |position|
+        default_protocol ||
+          (error 'no protocols are available', position)
+      end
+
+      def select_feature(data)
+        target_features[data.value]
+      end
+
+      private
+
+      def find_protocol(value)
+        available_protocols.find(&value.to_sym.method(:casecmp?))
+      end
+
+      def default_protocol
+        available_protocols.first
+      end
+
+      def available_protocols
+        @available_protocols ||= shared_context.available_protocols
+      end
+    end
+  end
+
+  sv_rtl do
+    shared_context.feature_registry(registry)
+
+    factory do
+      def select_feature(configuration, _register_block)
+        target_features[configuration.protocol]
+      end
+    end
+  end
+end

data/lib/rggen/built_in/register_block/protocol/apb.erb

@@ -0,0 +1,10 @@
+rggen_apb_adapter #(
+  .ADDRESS_WIDTH  (<%= register_block.local_address_width %>),
+  .BUS_WIDTH      (<%= configuration.bus_width %>),
+  .REGISTERS      (<%= register_block.total_registers %>)
+) u_adapter (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .apb_if       (<%= apb_if %>),
+  .register_if  (<%= register_block.register_if %>)
+);

data/lib/rggen/built_in/register_block/protocol/apb.rb

@@ -0,0 +1,113 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
+  configuration do
+    verify(:component) do
+      error_condition { configuration.bus_width > 32 }
+      message do
+        'bus width over 32 bit is not supported: ' \
+        "#{configuration.bus_width}"
+      end
+    end
+
+    verify(:component) do
+      error_condition { configuration.address_width > 32 }
+      message do
+        'address width over 32 bit is not supported: ' \
+        "#{configuration.address_width}"
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      if configuration.fold_sv_interface_port?
+        interface_port :register_block, :apb_if, {
+          name: 'apb_if',
+          interface_type: 'rggen_apb_if',
+          modport: 'slave'
+        }
+      else
+        input :register_block, :psel, {
+          name: 'i_psel',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :penable, {
+          name: 'i_penable',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :paddr, {
+          name: 'i_paddr',
+          data_type: :logic,
+          width: configuration.address_width
+        }
+        input :register_block, :pprot, {
+          name: 'i_pprot',
+          data_type: :logic,
+          width: 3
+        }
+        input :register_block, :pwrite, {
+          name: 'i_pwrite',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :pstrb, {
+          name: 'i_pstrb',
+          data_type: :logic,
+          width: configuration.byte_width
+        }
+        input :register_block, :pwdata, {
+          name: 'i_pwdata',
+          data_type: :logic,
+          width: configuration.bus_width
+        }
+        output :register_block, :pready, {
+          name: 'o_pready',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :prdata, {
+          name: 'o_prdata',
+          data_type: :logic,
+          width: configuration.bus_width
+        }
+        output :register_block, :pslverr, {
+          name: 'o_pslverr',
+          data_type: :logic,
+          width: 1
+        }
+        interface :register_block, :apb_if, {
+          name: 'apb_if',
+          interface_type: 'rggen_apb_if',
+          parameter_values: [
+            configuration.address_width, configuration.bus_width
+          ],
+          variables: [
+            'psel', 'penable', 'paddr', 'pprot', 'pwrite', 'pstrb', 'pwdata',
+            'pready', 'prdata', 'pslverr'
+          ]
+        }
+      end
+    end
+
+    main_code :register_block, from_template: true
+    main_code :register_block do |code|
+      unless configuration.fold_sv_interface_port?
+        [
+          [apb_if.psel, psel],
+          [apb_if.penable, penable],
+          [apb_if.paddr, paddr],
+          [apb_if.pprot, pprot],
+          [apb_if.pwrite, pwrite],
+          [apb_if.pstrb, pstrb],
+          [apb_if.pwdata, pwdata],
+          [pready, apb_if.pready],
+          [prdata, apb_if.prdata],
+          [pslverr, apb_if.pslverr]
+        ].map { |lhs, rhs| code << assign(lhs, rhs) << nl }
+      end
+    end
+  end
+end

data/lib/rggen/built_in/register_block/protocol/axi4lite.erb

@@ -0,0 +1,11 @@
+rggen_axi4lite_adapter #(
+  .ADDRESS_WIDTH  (<%= register_block.local_address_width %>),
+  .BUS_WIDTH      (<%= configuration.bus_width %>),
+  .REGISTERS      (<%= register_block.total_registers %>),
+  .WRITE_FIRST    (<%= write_first %>)
+) u_adapter (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .axi4lite_if  (<%= axi4lite_if %>),
+  .register_if  (<%= register_block.register_if %>)
+);

data/lib/rggen/built_in/register_block/protocol/axi4lite.rb

@@ -0,0 +1,167 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
+  configuration do
+    verify(:component) do
+      error_condition { ![32, 64].include?(configuration.bus_width) }
+      message do
+        'bus width eigher 32 bit or 64 bit is only supported: ' \
+        "#{configuration.bus_width}"
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      parameter :register_block, :write_first, {
+        name: 'WRITE_FIRST',
+        data_type: :bit,
+        default: 1
+      }
+      if configuration.fold_sv_interface_port?
+        interface_port :register_block, :axi4lite_if, {
+          name: 'axi4lite_if',
+          interface_type: 'rggen_axi4lite_if',
+          modport: 'slave'
+        }
+      else
+        input :register_block, :awvalid, {
+          name: 'i_awvalid',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :awready, {
+          name: 'o_awready',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :awaddr, {
+          name: 'i_awaddr',
+          data_type: :logic,
+          width: configuration.address_width
+        }
+        input :register_block, :awprot, {
+          name: 'i_awprot',
+          data_type: :logic,
+          width: 3
+        }
+        input :register_block, :wvalid, {
+          name: 'i_wvalid',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :wready, {
+          name: 'o_wready',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :wdata, {
+          name: 'i_wdata',
+          data_type: :logic,
+          width: configuration.bus_width
+        }
+        input :register_block, :wstrb, {
+          name: 'i_wstrb',
+          data_type: :logic,
+          width: configuration.byte_width
+        }
+        output :register_block, :bvalid, {
+          name: 'o_bvalid',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :bready, {
+          name: 'i_bready',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :bresp, {
+          name: 'o_bresp',
+          data_type: :logic,
+          width: 2
+        }
+        input :register_block, :arvalid, {
+          name: 'i_arvalid',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :arready, {
+          name: 'o_arready',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :araddr, {
+          name: 'i_araddr',
+          data_type: :logic,
+          width: configuration.address_width
+        }
+        input :register_block, :arprot, {
+          name: 'i_arprot',
+          data_type: :logic,
+          width: 3
+        }
+        output :register_block, :rvalid, {
+          name: 'o_rvalid',
+          data_type: :logic,
+          width: 1
+        }
+        input :register_block, :rready, {
+          name: 'i_rready',
+          data_type: :logic,
+          width: 1
+        }
+        output :register_block, :rdata, {
+          name: 'o_rdata',
+          data_type: :logic,
+          width: configuration.bus_width
+        }
+        output :register_block, :rresp, {
+          name: 'o_rresp',
+          data_type: :logic,
+          width: 2
+        }
+        interface :register_block, :axi4lite_if, {
+          name: 'axi4lite_if',
+          interface_type: 'rggen_axi4lite_if',
+          parameter_values: [
+            configuration.address_width, configuration.bus_width
+          ],
+          variables: [
+            'awvalid', 'awready', 'awaddr', 'awprot',
+            'wvalid', 'wready', 'wdata', 'wstrb',
+            'bvalid', 'bready', 'bresp',
+            'arvalid', 'arready', 'araddr', 'arprot',
+            'rvalid', 'rready', 'rdata', 'rresp'
+          ]
+        }
+      end
+    end
+
+    main_code :register_block, from_template: true
+    main_code :register_block do |code|
+      unless configuration.fold_sv_interface_port?
+        [
+          [axi4lite_if.awvalid, awvalid],
+          [awready, axi4lite_if.awready],
+          [axi4lite_if.awaddr, awaddr],
+          [axi4lite_if.awprot, awprot],
+          [axi4lite_if.wvalid, wvalid],
+          [wready, axi4lite_if.wready],
+          [axi4lite_if.wdata, wdata],
+          [axi4lite_if.wstrb, wstrb],
+          [bvalid, axi4lite_if.bvalid],
+          [axi4lite_if.bready, bready],
+          [bresp, axi4lite_if.bresp],
+          [axi4lite_if.arvalid, arvalid],
+          [arready, axi4lite_if.arready],
+          [axi4lite_if.araddr, araddr],
+          [axi4lite_if.arprot, arprot],
+          [rvalid, axi4lite_if.rvalid],
+          [axi4lite_if.rready, rready],
+          [rdata, axi4lite_if.rdata],
+          [rresp, axi4lite_if.rresp]
+        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
+      end
+    end
+  end
+end