rggen 0.8.2 → 0.9.0
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- checksums.yaml +4 -4
- data/CODE_OF_CONDUCT.md +54 -29
- data/{LICENSE.txt → LICENSE} +1 -1
- data/README.md +65 -56
- data/lib/rggen.rb +4 -63
- data/lib/rggen/built_in.rb +53 -0
- data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
- data/lib/rggen/built_in/bit_field/comment.rb +16 -0
- data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
- data/lib/rggen/built_in/bit_field/name.rb +39 -0
- data/lib/rggen/built_in/bit_field/reference.rb +100 -0
- data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
- data/lib/rggen/built_in/bit_field/type.rb +279 -0
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
- data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
- data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
- data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
- data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
- data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
- data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
- data/lib/rggen/built_in/global/address_width.rb +32 -0
- data/lib/rggen/built_in/global/array_port_format.rb +19 -0
- data/lib/rggen/built_in/global/bus_width.rb +33 -0
- data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/built_in/register/name.rb +34 -0
- data/lib/rggen/built_in/register/offset_address.rb +96 -0
- data/lib/rggen/built_in/register/size.rb +49 -0
- data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/built_in/register/type.rb +374 -0
- data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
- data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
- data/lib/rggen/built_in/register/type/external.erb +11 -0
- data/lib/rggen/built_in/register/type/external.rb +141 -0
- data/lib/rggen/built_in/register/type/indirect.rb +329 -0
- data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
- data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
- data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
- data/lib/rggen/built_in/register_block/name.rb +36 -0
- data/lib/rggen/built_in/register_block/protocol.rb +71 -0
- data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
- data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
- data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
- data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
- data/lib/rggen/built_in/version.rb +7 -0
- data/lib/rggen/default_setup_file.rb +6 -0
- data/lib/rggen/setup/default.rb +26 -0
- data/lib/rggen/version.rb +5 -4
- data/sample/block_0.rb +85 -0
- data/sample/block_0.sv +601 -0
- data/sample/block_0.xlsx +0 -0
- data/sample/block_0.yml +94 -0
- data/sample/block_0_ral_pkg.sv +174 -0
- data/sample/block_1.rb +22 -0
- data/sample/block_1.sv +136 -0
- data/sample/block_1.xlsx +0 -0
- data/sample/block_1.yml +26 -0
- data/sample/block_1_ral_pkg.sv +68 -0
- data/sample/config.json +5 -0
- data/sample/config.yml +3 -0
- metadata +96 -270
- data/bin/rggen +0 -6
- data/c_header/LICENSE +0 -21
- data/c_header/rggen.h +0 -17
- data/lib/rggen/base/component.rb +0 -31
- data/lib/rggen/base/component_factory.rb +0 -53
- data/lib/rggen/base/hierarchical_accessors.rb +0 -87
- data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
- data/lib/rggen/base/internal_struct.rb +0 -28
- data/lib/rggen/base/item.rb +0 -35
- data/lib/rggen/base/item_factory.rb +0 -25
- data/lib/rggen/builder/builder.rb +0 -69
- data/lib/rggen/builder/category.rb +0 -63
- data/lib/rggen/builder/component_entry.rb +0 -50
- data/lib/rggen/builder/component_store.rb +0 -42
- data/lib/rggen/builder/input_component_store.rb +0 -25
- data/lib/rggen/builder/item_store.rb +0 -89
- data/lib/rggen/builder/list_item_entry.rb +0 -81
- data/lib/rggen/builder/output_component_store.rb +0 -13
- data/lib/rggen/builder/simple_item_entry.rb +0 -33
- data/lib/rggen/builtins.rb +0 -55
- data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
- data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
- data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
- data/lib/rggen/builtins/bit_field/name.rb +0 -26
- data/lib/rggen/builtins/bit_field/reference.rb +0 -40
- data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
- data/lib/rggen/builtins/bit_field/type.rb +0 -244
- data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
- data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
- data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
- data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
- data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
- data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
- data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
- data/lib/rggen/builtins/global/address_width.rb +0 -17
- data/lib/rggen/builtins/global/array_port_format.rb +0 -15
- data/lib/rggen/builtins/global/data_width.rb +0 -20
- data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
- data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
- data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
- data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
- data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
- data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
- data/lib/rggen/builtins/register/array.rb +0 -30
- data/lib/rggen/builtins/register/constructor.rb +0 -17
- data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
- data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
- data/lib/rggen/builtins/register/name.rb +0 -26
- data/lib/rggen/builtins/register/offset_address.rb +0 -61
- data/lib/rggen/builtins/register/reg_model.rb +0 -107
- data/lib/rggen/builtins/register/rtl_top.rb +0 -68
- data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
- data/lib/rggen/builtins/register/type.rb +0 -283
- data/lib/rggen/builtins/register/types/default.erb +0 -10
- data/lib/rggen/builtins/register/types/external.erb +0 -11
- data/lib/rggen/builtins/register/types/external.rb +0 -77
- data/lib/rggen/builtins/register/types/indirect.erb +0 -13
- data/lib/rggen/builtins/register/types/indirect.rb +0 -175
- data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
- data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
- data/lib/rggen/builtins/register_block/base_address.rb +0 -64
- data/lib/rggen/builtins/register_block/block_model.rb +0 -20
- data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
- data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
- data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
- data/lib/rggen/builtins/register_block/constructor.rb +0 -14
- data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
- data/lib/rggen/builtins/register_block/host_if.rb +0 -64
- data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
- data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
- data/lib/rggen/builtins/register_block/name.rb +0 -26
- data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
- data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
- data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
- data/lib/rggen/commands.rb +0 -23
- data/lib/rggen/core_components.rb +0 -54
- data/lib/rggen/core_components/c_header/item.rb +0 -8
- data/lib/rggen/core_components/c_header/setup.rb +0 -19
- data/lib/rggen/core_components/c_utility.rb +0 -19
- data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
- data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
- data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
- data/lib/rggen/core_components/code_utility.rb +0 -56
- data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
- data/lib/rggen/core_components/code_utility/line.rb +0 -28
- data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
- data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
- data/lib/rggen/core_components/configuration/item.rb +0 -11
- data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
- data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
- data/lib/rggen/core_components/configuration/setup.rb +0 -14
- data/lib/rggen/core_components/erb_engine.rb +0 -15
- data/lib/rggen/core_components/ral/component.rb +0 -24
- data/lib/rggen/core_components/ral/item.rb +0 -59
- data/lib/rggen/core_components/ral/setup.rb +0 -19
- data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
- data/lib/rggen/core_components/register_map/component.rb +0 -15
- data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
- data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
- data/lib/rggen/core_components/register_map/item.rb +0 -26
- data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
- data/lib/rggen/core_components/register_map/loader.rb +0 -11
- data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
- data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
- data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
- data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
- data/lib/rggen/core_components/register_map/setup.rb +0 -33
- data/lib/rggen/core_components/rtl/component.rb +0 -24
- data/lib/rggen/core_components/rtl/item.rb +0 -82
- data/lib/rggen/core_components/rtl/setup.rb +0 -19
- data/lib/rggen/core_components/verilog_utility.rb +0 -88
- data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
- data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
- data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
- data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
- data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
- data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
- data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
- data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
- data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
- data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
- data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
- data/lib/rggen/core_extensions/array.rb +0 -9
- data/lib/rggen/core_extensions/facets.rb +0 -22
- data/lib/rggen/core_extensions/forwardable.rb +0 -49
- data/lib/rggen/core_extensions/integer.rb +0 -5
- data/lib/rggen/core_extensions/math.rb +0 -7
- data/lib/rggen/core_extensions/roo.rb +0 -17
- data/lib/rggen/exceptions.rb +0 -28
- data/lib/rggen/generator.rb +0 -67
- data/lib/rggen/input_base/component.rb +0 -28
- data/lib/rggen/input_base/component_factory.rb +0 -58
- data/lib/rggen/input_base/item.rb +0 -171
- data/lib/rggen/input_base/item_factory.rb +0 -13
- data/lib/rggen/input_base/loader.rb +0 -23
- data/lib/rggen/input_base/regexp_patterns.rb +0 -29
- data/lib/rggen/option_switches.rb +0 -60
- data/lib/rggen/options.rb +0 -97
- data/lib/rggen/output_base/code_generator.rb +0 -36
- data/lib/rggen/output_base/component.rb +0 -78
- data/lib/rggen/output_base/component_factory.rb +0 -32
- data/lib/rggen/output_base/file_writer.rb +0 -36
- data/lib/rggen/output_base/item.rb +0 -110
- data/lib/rggen/output_base/item_factory.rb +0 -9
- data/lib/rggen/output_base/template_engine.rb +0 -24
- data/lib/rggen/rggen_home.rb +0 -3
- data/ral/LICENSE +0 -21
- data/ral/compile.f +0 -2
- data/ral/rggen_ral_block.svh +0 -83
- data/ral/rggen_ral_field.svh +0 -47
- data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
- data/ral/rggen_ral_indirect_reg.svh +0 -193
- data/ral/rggen_ral_macros.svh +0 -27
- data/ral/rggen_ral_map.svh +0 -124
- data/ral/rggen_ral_pkg.sv +0 -15
- data/ral/rggen_ral_reg.svh +0 -88
- data/rtl/LICENSE +0 -21
- data/rtl/compile.f +0 -18
- data/rtl/rggen_address_decoder.sv +0 -23
- data/rtl/rggen_apb_if.sv +0 -41
- data/rtl/rggen_axi4lite_if.sv +0 -68
- data/rtl/rggen_bit_field_if.sv +0 -28
- data/rtl/rggen_bit_field_ro.sv +0 -9
- data/rtl/rggen_bit_field_rw.sv +0 -25
- data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
- data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
- data/rtl/rggen_bus_if.sv +0 -43
- data/rtl/rggen_bus_splitter.sv +0 -86
- data/rtl/rggen_default_register.sv +0 -15
- data/rtl/rggen_external_register.sv +0 -83
- data/rtl/rggen_host_if_apb.sv +0 -29
- data/rtl/rggen_host_if_axi4lite.sv +0 -161
- data/rtl/rggen_indirect_register.sv +0 -21
- data/rtl/rggen_register_base.sv +0 -57
- data/rtl/rggen_register_if.sv +0 -42
- data/rtl/rggen_rtl_pkg.sv +0 -23
- data/sample/LICENSE +0 -21
- data/sample/sample.csv +0 -21
- data/sample/sample.json +0 -6
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample.yaml +0 -4
- data/sample/sample_0.h +0 -17
- data/sample/sample_0.sv +0 -402
- data/sample/sample_0_ral_pkg.sv +0 -145
- data/sample/sample_1.h +0 -9
- data/sample/sample_1.sv +0 -128
- data/sample/sample_1_ral_pkg.sv +0 -56
- data/sample/sample_setup.rb +0 -24
- data/setup/default.rb +0 -14
@@ -1,10 +0,0 @@
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rggen_default_register #(
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.ADDRESS_WIDTH (<%= local_address_width %>),
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.START_ADDRESS (<%= start_address %>),
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.END_ADDRESS (<%= end_address %>),
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.DATA_WIDTH (<%= data_width %>),
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.VALID_BITS (<%= valid_bits %>)
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) u_register (
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.register_if (<%= register.register_if %>),
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.bit_field_if (<%= bit_field_if %>)
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);
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@@ -1,11 +0,0 @@
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rggen_external_register #(
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.ADDRESS_WIDTH (<%= local_address_width %>),
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.START_ADDRESS (<%= start_address %>),
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.END_ADDRESS (<%= end_address %>),
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.DATA_WIDTH (<%= configuration.data_width %>)
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) u_register (
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.clk (<%= register_block.clock %>),
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.rst_n (<%= register_block.reset %>),
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.register_if (<%= register.register_if %>),
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.bus_if (<%= bus_if %>)
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);
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@@ -1,77 +0,0 @@
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list_item :register, :type, :external do
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register_map do
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read_write
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required_byte_size any_size
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need_no_bit_fields
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end
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rtl do
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delegate [:unfold_sv_interface_port?] => :configuration
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delegate [:name] => :register
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build do
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if unfold_sv_interface_port?
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output :register_block, :request,
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name: "o_#{name}_request", data_type: :logic, width: 1
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output :register_block, :address,
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name: "o_#{name}_address", data_type: :logic, width: address_width
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output :register_block, :direction,
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name: "o_#{name}_direction", data_type: :logic, width: 1
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output :register_block, :write_data,
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name: "o_#{name}_write_data", data_type: :logic, width: data_width
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output :register_block, :strobe,
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name: "o_#{name}_strobe", data_type: :logic, width: data_width / 8
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input :register_block, :done,
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name: "i_#{name}_done", data_type: :logic, width: 1
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input :register_block, :write_done,
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name: "i_#{name}_write_done", data_type: :logic, width: 1
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input :register_block, :read_done,
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name: "i_#{name}_read_done", data_type: :logic, width: 1
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input :register_block, :read_data,
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name: "i_#{name}_read_data", data_type: :logic, width: data_width
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input :register_block, :status,
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name: "i_#{name}_status", data_type: :logic, width: 2
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interface :register, :bus_if,
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type: :rggen_bus_if, parameters: [address_width, data_width]
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else
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-
interface_port :register_block, :bus_if,
|
39
|
-
name: "#{name}_bus_if", type: :rggen_bus_if, modport: :master
|
40
|
-
end
|
41
|
-
end
|
42
|
-
|
43
|
-
def address_width
|
44
|
-
Math.clog2(address_range.end - address_range.begin + 1)
|
45
|
-
end
|
46
|
-
|
47
|
-
generate_code :register do |code|
|
48
|
-
unfold_sv_interface_port? && bus_if_assignment(code)
|
49
|
-
code << process_template
|
50
|
-
end
|
51
|
-
|
52
|
-
def bus_if_assignment(code)
|
53
|
-
code << assign(request , "#{bus_if}.request" ) << nl
|
54
|
-
code << assign(address , "#{bus_if}.address" ) << nl
|
55
|
-
code << assign(direction , "#{bus_if}.direction" ) << nl
|
56
|
-
code << assign(write_data, "#{bus_if}.write_data" ) << nl
|
57
|
-
code << assign(strobe , "#{bus_if}.write_strobe") << nl
|
58
|
-
code << assign("#{bus_if}.done" , done ) << nl
|
59
|
-
code << assign("#{bus_if}.write_done", write_done ) << nl
|
60
|
-
code << assign("#{bus_if}.read_done" , read_done ) << nl
|
61
|
-
code << assign("#{bus_if}.read_data" , read_data ) << nl
|
62
|
-
code << assign("#{bus_if}.status" , casted_status) << nl
|
63
|
-
end
|
64
|
-
|
65
|
-
def casted_status
|
66
|
-
"rggen_rtl_pkg::rggen_status'(#{status})"
|
67
|
-
end
|
68
|
-
end
|
69
|
-
|
70
|
-
c_header do
|
71
|
-
delegate [:name, :byte_size] => :register
|
72
|
-
|
73
|
-
address_struct_member do
|
74
|
-
"RGGEN_EXTERNAL_REGISTERS(#{byte_size}, #{name.upcase}) #{name}"
|
75
|
-
end
|
76
|
-
end
|
77
|
-
end
|
@@ -1,13 +0,0 @@
|
|
1
|
-
rggen_indirect_register #(
|
2
|
-
.ADDRESS_WIDTH (<%= local_address_width %>),
|
3
|
-
.START_ADDRESS (<%= start_address %>),
|
4
|
-
.END_ADDRESS (<%= end_address %>),
|
5
|
-
.INDEX_WIDTH (<%= indirect_index_width %>),
|
6
|
-
.INDEX_VALUE (<%= indirect_index_value %>),
|
7
|
-
.DATA_WIDTH (<%= data_width %>),
|
8
|
-
.VALID_BITS (<%= valid_bits %>)
|
9
|
-
) u_register (
|
10
|
-
.register_if (<%= register.register_if %>),
|
11
|
-
.bit_field_if (<%= bit_field_if %>),
|
12
|
-
.i_index (<%= indirect_index %>)
|
13
|
-
);
|
@@ -1,175 +0,0 @@
|
|
1
|
-
list_item :register, :type, :indirect do
|
2
|
-
register_map do
|
3
|
-
field :indexes
|
4
|
-
|
5
|
-
readable? { register.bit_fields.any?(&:readable?) }
|
6
|
-
writable? { register.bit_fields.any?(&:writable?) }
|
7
|
-
|
8
|
-
need_options
|
9
|
-
support_array_register support_multiple_dimensions: true
|
10
|
-
required_byte_size data_width
|
11
|
-
|
12
|
-
input_pattern %r{(#{variable_name})(?::(#{number}))?}
|
13
|
-
|
14
|
-
define_struct :index_entry, [:name, :value] do
|
15
|
-
def initialize(name, value)
|
16
|
-
self.name = name
|
17
|
-
self.value = value && Integer(value)
|
18
|
-
end
|
19
|
-
|
20
|
-
def ==(other)
|
21
|
-
return false unless name == other.name
|
22
|
-
return true if [value, other.value].any?(&:nil?)
|
23
|
-
value == other.value
|
24
|
-
end
|
25
|
-
end
|
26
|
-
|
27
|
-
build do |cell|
|
28
|
-
@indexes = parse_indexes(cell.options.strip)
|
29
|
-
end
|
30
|
-
|
31
|
-
def parse_indexes(options)
|
32
|
-
options.split(/[,\n]/).map do |entry|
|
33
|
-
if pattern_match(entry)
|
34
|
-
index_entry.new(captures[0], captures[1])
|
35
|
-
else
|
36
|
-
error "invalid value for index: #{options.inspect}"
|
37
|
-
end
|
38
|
-
end
|
39
|
-
end
|
40
|
-
|
41
|
-
validate do
|
42
|
-
check_index_entries
|
43
|
-
check_number_of_array_indexes
|
44
|
-
check_array_index_values
|
45
|
-
check_fixed_value_index_values
|
46
|
-
end
|
47
|
-
|
48
|
-
def check_index_entries
|
49
|
-
indexes.each(&method(:check_index_entry))
|
50
|
-
end
|
51
|
-
|
52
|
-
def check_index_entry(entry)
|
53
|
-
[
|
54
|
-
:check_using_same_index_more_than_once,
|
55
|
-
:check_using_non_existing_index,
|
56
|
-
:check_using_own_bit_field_for_index,
|
57
|
-
:check_using_arrayed_bit_field_for_index
|
58
|
-
].each { |checker| send(checker, entry) }
|
59
|
-
end
|
60
|
-
|
61
|
-
def check_using_same_index_more_than_once(entry)
|
62
|
-
return if indexes.one? { |index| index.name == entry.name }
|
63
|
-
error "not use the same index field more than once: #{entry.name}"
|
64
|
-
end
|
65
|
-
|
66
|
-
def check_using_non_existing_index(entry)
|
67
|
-
return unless index_bit_fields[entry.name].nil?
|
68
|
-
error "no such index field: #{entry.name}"
|
69
|
-
end
|
70
|
-
|
71
|
-
def check_using_own_bit_field_for_index(entry)
|
72
|
-
return unless register.bit_fields.find_by(name: entry.name)
|
73
|
-
error "not use own bit field for index field: #{entry.name}"
|
74
|
-
end
|
75
|
-
|
76
|
-
def check_using_arrayed_bit_field_for_index(entry)
|
77
|
-
return unless index_bit_fields[entry.name].register.array?
|
78
|
-
error "not use arrayed bit field for index field: #{entry.name}"
|
79
|
-
end
|
80
|
-
|
81
|
-
def check_number_of_array_indexes
|
82
|
-
return if array_indexes.size == size_of_dimensions
|
83
|
-
error 'not match size of array dimensions and number of array indexes'
|
84
|
-
end
|
85
|
-
|
86
|
-
def check_array_index_values
|
87
|
-
array_indexes.each_with_index do |entry, i|
|
88
|
-
next if register.dimensions[i] <= (max_value(entry.name) + 1)
|
89
|
-
error "array size(#{register.dimensions[i]}) is greater than " \
|
90
|
-
"maximum value of #{entry.name}(#{max_value(entry.name)})"
|
91
|
-
end
|
92
|
-
end
|
93
|
-
|
94
|
-
def check_fixed_value_index_values
|
95
|
-
fixed_value_indexes.each do |entry|
|
96
|
-
next if entry.value <= max_value(entry.name)
|
97
|
-
error "index value(#{entry.value}) is greater thatn " \
|
98
|
-
"maximum value of #{entry.name}(#{max_value(entry.name)})"
|
99
|
-
end
|
100
|
-
end
|
101
|
-
|
102
|
-
def index_bit_fields
|
103
|
-
@index_bit_fields ||= Hash.new do |h, name|
|
104
|
-
h[name] = register_block.bit_fields.find_by(
|
105
|
-
name: name, reserved?: false
|
106
|
-
)
|
107
|
-
end
|
108
|
-
end
|
109
|
-
|
110
|
-
def array_indexes
|
111
|
-
indexes.select { |entry| entry.value.nil? }
|
112
|
-
end
|
113
|
-
|
114
|
-
def fixed_value_indexes
|
115
|
-
indexes.select(&:value)
|
116
|
-
end
|
117
|
-
|
118
|
-
def size_of_dimensions
|
119
|
-
(register.array? && register.dimensions.size) || 0
|
120
|
-
end
|
121
|
-
|
122
|
-
def max_value(index_name)
|
123
|
-
2**index_bit_fields[index_name].width - 1
|
124
|
-
end
|
125
|
-
end
|
126
|
-
|
127
|
-
rtl do
|
128
|
-
build do
|
129
|
-
logic :register, :indirect_index, width: indirect_index_width
|
130
|
-
end
|
131
|
-
|
132
|
-
generate_code :register do |code|
|
133
|
-
code << indirect_index_assignment << nl
|
134
|
-
code << process_template
|
135
|
-
end
|
136
|
-
|
137
|
-
def indirect_index_fields
|
138
|
-
@indirect_index_fields ||= register.indexes.map do |i|
|
139
|
-
register_block.bit_fields.find_by(name: i.name)
|
140
|
-
end
|
141
|
-
end
|
142
|
-
|
143
|
-
def indirect_index_assignment
|
144
|
-
assign(
|
145
|
-
indirect_index, concat(indirect_index_fields.map(&:value))
|
146
|
-
)
|
147
|
-
end
|
148
|
-
|
149
|
-
def indirect_index_width
|
150
|
-
indirect_index_fields.sum(0, &:width)
|
151
|
-
end
|
152
|
-
|
153
|
-
def indirect_index_value
|
154
|
-
concat(indirect_index_values)
|
155
|
-
end
|
156
|
-
|
157
|
-
def indirect_index_values
|
158
|
-
variables = loop_variables
|
159
|
-
register.indexes.map.with_index do |index, i|
|
160
|
-
if index.value
|
161
|
-
hex(index.value, indirect_index_fields[i].width)
|
162
|
-
else
|
163
|
-
variable = variables.shift
|
164
|
-
variable[indirect_index_fields[i].width - 1, 0]
|
165
|
-
end
|
166
|
-
end
|
167
|
-
end
|
168
|
-
end
|
169
|
-
|
170
|
-
c_header do
|
171
|
-
address_struct_member do
|
172
|
-
variable_declaration(name: register.name, data_type: data_type)
|
173
|
-
end
|
174
|
-
end
|
175
|
-
end
|
@@ -1,51 +0,0 @@
|
|
1
|
-
simple_item :register, :uniqueness_validator do
|
2
|
-
register_map do
|
3
|
-
validate do
|
4
|
-
previous_registers.each do |previous_register|
|
5
|
-
validate_uniqueness(previous_register)
|
6
|
-
end
|
7
|
-
end
|
8
|
-
|
9
|
-
def previous_registers
|
10
|
-
register_block.registers.take_while { |r| !r.equal?(register) }
|
11
|
-
end
|
12
|
-
|
13
|
-
def validate_uniqueness(previous_register)
|
14
|
-
if overlap_offset_address?(previous_register)
|
15
|
-
error 'offset address is not unique', error_position(:start_address)
|
16
|
-
elsif overlap_indirect_indexes?(previous_register)
|
17
|
-
error 'indirect indexes is not unique', error_position(:indexes)
|
18
|
-
end
|
19
|
-
end
|
20
|
-
|
21
|
-
def overlap_offset_address?(previous_register)
|
22
|
-
return false if both_register_indirect?(previous_register)
|
23
|
-
overlap_address_range?(register, previous_register)
|
24
|
-
end
|
25
|
-
|
26
|
-
def overlap_address_range?(lhs, rhs)
|
27
|
-
lhs_range = lhs.start_address..lhs.end_address
|
28
|
-
rhs_range = rhs.start_address..rhs.end_address
|
29
|
-
lhs_range.overlap?(rhs_range)
|
30
|
-
end
|
31
|
-
|
32
|
-
def overlap_indirect_indexes?(previous_register)
|
33
|
-
return false unless overlap_address_range?(register, previous_register)
|
34
|
-
return true unless unique_shadw_indexes?(register, previous_register)
|
35
|
-
return true unless unique_shadw_indexes?(previous_register, register)
|
36
|
-
false
|
37
|
-
end
|
38
|
-
|
39
|
-
def both_register_indirect?(previous_register)
|
40
|
-
[register, previous_register].all? { |r| r.type?(:indirect) }
|
41
|
-
end
|
42
|
-
|
43
|
-
def unique_shadw_indexes?(lhs, rhs)
|
44
|
-
lhs.indexes.any?(&rhs.indexes.method(:exclude?))
|
45
|
-
end
|
46
|
-
|
47
|
-
def error_position(field)
|
48
|
-
register.items.find { |i| i.fields.include?(field) }.position
|
49
|
-
end
|
50
|
-
end
|
51
|
-
end
|
@@ -1,56 +0,0 @@
|
|
1
|
-
simple_item :register_block, :address_struct do
|
2
|
-
c_header do
|
3
|
-
delegate [:data_width, :byte_width] => :configuration
|
4
|
-
delegate [:registers, :name] => :register_block
|
5
|
-
|
6
|
-
generate_code :c_header_item do
|
7
|
-
struct_definition(stuct_name) do |s|
|
8
|
-
s.with_typedef
|
9
|
-
s.members address_struct_members
|
10
|
-
end
|
11
|
-
end
|
12
|
-
|
13
|
-
def stuct_name
|
14
|
-
"s_#{name}_address_struct"
|
15
|
-
end
|
16
|
-
|
17
|
-
def address_struct_members
|
18
|
-
address_struct_entries.each_cons(2).with_object([]) do |entries, members|
|
19
|
-
dummy_size = entries[1].start_address - entries[0].end_address - 1
|
20
|
-
members << dummy_member(dummy_size) if dummy_size > 0
|
21
|
-
members << entries[1].address_struct_member
|
22
|
-
end
|
23
|
-
end
|
24
|
-
|
25
|
-
def dummy_member(size)
|
26
|
-
variable_declaration(
|
27
|
-
data_type: "rggen_uint#{data_width}",
|
28
|
-
name: "__dummy_#{dummy_index}",
|
29
|
-
dimensions: [size / byte_width]
|
30
|
-
)
|
31
|
-
end
|
32
|
-
|
33
|
-
def dummy_index
|
34
|
-
@dummy_index ||= -1
|
35
|
-
@dummy_index += 1
|
36
|
-
end
|
37
|
-
|
38
|
-
def address_struct_entries
|
39
|
-
[].tap do |entries|
|
40
|
-
entries << dummy_entry
|
41
|
-
entries.concat(non_reserved_registers)
|
42
|
-
end
|
43
|
-
end
|
44
|
-
|
45
|
-
def dummy_entry
|
46
|
-
Object.new.tap do |dummy|
|
47
|
-
dummy.attr_singleton_accessor :end_address
|
48
|
-
dummy.end_address = -1
|
49
|
-
end
|
50
|
-
end
|
51
|
-
|
52
|
-
def non_reserved_registers
|
53
|
-
registers.reject(&:reserved?).sort_by(&:start_address)
|
54
|
-
end
|
55
|
-
end
|
56
|
-
end
|
@@ -1,64 +0,0 @@
|
|
1
|
-
simple_item :register_block, :base_address do
|
2
|
-
register_map do
|
3
|
-
field :start_address
|
4
|
-
field :end_address
|
5
|
-
field :byte_size
|
6
|
-
field :local_address_width
|
7
|
-
|
8
|
-
input_pattern %r{(#{number})-(#{number})}
|
9
|
-
|
10
|
-
build do |cell|
|
11
|
-
parse_address(cell)
|
12
|
-
case
|
13
|
-
when @start_address >= @end_address
|
14
|
-
error "start address is equal to or greater than end address: #{cell}"
|
15
|
-
when not_aligned_with_data_width?
|
16
|
-
error 'not aligned with data width' \
|
17
|
-
"(#{configuration.data_width}): #{cell}"
|
18
|
-
when not_aligned_with_local_address_width?
|
19
|
-
error 'not aligned with local address width' \
|
20
|
-
"(#{@local_address_width}): #{cell}"
|
21
|
-
when @end_address > max_address
|
22
|
-
error 'exceeds the maximum base address' \
|
23
|
-
"(0x#{max_address.to_s(16)}): #{cell}"
|
24
|
-
when overlapped_address?
|
25
|
-
error "overlapped base address: #{cell}"
|
26
|
-
end
|
27
|
-
end
|
28
|
-
|
29
|
-
def parse_address(cell)
|
30
|
-
if pattern_matched?
|
31
|
-
@start_address = Integer(captures[0])
|
32
|
-
@end_address = Integer(captures[1])
|
33
|
-
@byte_size = @end_address - @start_address + 1
|
34
|
-
@local_address_width = Math.clog2(@byte_size) if @byte_size > 0
|
35
|
-
else
|
36
|
-
error "invalid value for base address: #{cell.inspect}"
|
37
|
-
end
|
38
|
-
end
|
39
|
-
|
40
|
-
def not_aligned_with_data_width?
|
41
|
-
byte_width = configuration.byte_width
|
42
|
-
return true unless (@start_address + 0).multiple?(byte_width)
|
43
|
-
return true unless (@end_address + 1).multiple?(byte_width)
|
44
|
-
false
|
45
|
-
end
|
46
|
-
|
47
|
-
def not_aligned_with_local_address_width?
|
48
|
-
window_size = 2**@local_address_width
|
49
|
-
return true unless @start_address.multiple?(window_size)
|
50
|
-
false
|
51
|
-
end
|
52
|
-
|
53
|
-
def max_address
|
54
|
-
2**configuration.address_width - 1
|
55
|
-
end
|
56
|
-
|
57
|
-
def overlapped_address?
|
58
|
-
own_range = @start_address..@end_address
|
59
|
-
register_map.register_blocks.any? do |block|
|
60
|
-
own_range.overlap?(block.start_address..block.end_address)
|
61
|
-
end
|
62
|
-
end
|
63
|
-
end
|
64
|
-
end
|