rggen 0.8.2 → 0.9.0

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Files changed (269) hide show
  1. checksums.yaml +4 -4
  2. data/CODE_OF_CONDUCT.md +54 -29
  3. data/{LICENSE.txt → LICENSE} +1 -1
  4. data/README.md +65 -56
  5. data/lib/rggen.rb +4 -63
  6. data/lib/rggen/built_in.rb +53 -0
  7. data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
  8. data/lib/rggen/built_in/bit_field/comment.rb +16 -0
  9. data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
  10. data/lib/rggen/built_in/bit_field/name.rb +39 -0
  11. data/lib/rggen/built_in/bit_field/reference.rb +100 -0
  12. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
  13. data/lib/rggen/built_in/bit_field/type.rb +279 -0
  14. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
  15. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
  16. data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
  17. data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
  18. data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
  19. data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
  20. data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
  21. data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
  22. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
  23. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
  24. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
  25. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
  26. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
  27. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
  28. data/lib/rggen/built_in/global/address_width.rb +32 -0
  29. data/lib/rggen/built_in/global/array_port_format.rb +19 -0
  30. data/lib/rggen/built_in/global/bus_width.rb +33 -0
  31. data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
  32. data/lib/rggen/built_in/register/name.rb +34 -0
  33. data/lib/rggen/built_in/register/offset_address.rb +96 -0
  34. data/lib/rggen/built_in/register/size.rb +49 -0
  35. data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
  36. data/lib/rggen/built_in/register/type.rb +374 -0
  37. data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
  38. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
  39. data/lib/rggen/built_in/register/type/external.erb +11 -0
  40. data/lib/rggen/built_in/register/type/external.rb +141 -0
  41. data/lib/rggen/built_in/register/type/indirect.rb +329 -0
  42. data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
  43. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
  44. data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
  45. data/lib/rggen/built_in/register_block/name.rb +36 -0
  46. data/lib/rggen/built_in/register_block/protocol.rb +71 -0
  47. data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
  48. data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
  49. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
  50. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
  51. data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
  52. data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
  53. data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
  54. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
  55. data/lib/rggen/built_in/version.rb +7 -0
  56. data/lib/rggen/default_setup_file.rb +6 -0
  57. data/lib/rggen/setup/default.rb +26 -0
  58. data/lib/rggen/version.rb +5 -4
  59. data/sample/block_0.rb +85 -0
  60. data/sample/block_0.sv +601 -0
  61. data/sample/block_0.xlsx +0 -0
  62. data/sample/block_0.yml +94 -0
  63. data/sample/block_0_ral_pkg.sv +174 -0
  64. data/sample/block_1.rb +22 -0
  65. data/sample/block_1.sv +136 -0
  66. data/sample/block_1.xlsx +0 -0
  67. data/sample/block_1.yml +26 -0
  68. data/sample/block_1_ral_pkg.sv +68 -0
  69. data/sample/config.json +5 -0
  70. data/sample/config.yml +3 -0
  71. metadata +96 -270
  72. data/bin/rggen +0 -6
  73. data/c_header/LICENSE +0 -21
  74. data/c_header/rggen.h +0 -17
  75. data/lib/rggen/base/component.rb +0 -31
  76. data/lib/rggen/base/component_factory.rb +0 -53
  77. data/lib/rggen/base/hierarchical_accessors.rb +0 -87
  78. data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
  79. data/lib/rggen/base/internal_struct.rb +0 -28
  80. data/lib/rggen/base/item.rb +0 -35
  81. data/lib/rggen/base/item_factory.rb +0 -25
  82. data/lib/rggen/builder/builder.rb +0 -69
  83. data/lib/rggen/builder/category.rb +0 -63
  84. data/lib/rggen/builder/component_entry.rb +0 -50
  85. data/lib/rggen/builder/component_store.rb +0 -42
  86. data/lib/rggen/builder/input_component_store.rb +0 -25
  87. data/lib/rggen/builder/item_store.rb +0 -89
  88. data/lib/rggen/builder/list_item_entry.rb +0 -81
  89. data/lib/rggen/builder/output_component_store.rb +0 -13
  90. data/lib/rggen/builder/simple_item_entry.rb +0 -33
  91. data/lib/rggen/builtins.rb +0 -55
  92. data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
  93. data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
  94. data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
  95. data/lib/rggen/builtins/bit_field/name.rb +0 -26
  96. data/lib/rggen/builtins/bit_field/reference.rb +0 -40
  97. data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
  98. data/lib/rggen/builtins/bit_field/type.rb +0 -244
  99. data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
  100. data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
  101. data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
  102. data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
  103. data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
  104. data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
  105. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
  106. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
  107. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
  108. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
  109. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
  110. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
  111. data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
  112. data/lib/rggen/builtins/global/address_width.rb +0 -17
  113. data/lib/rggen/builtins/global/array_port_format.rb +0 -15
  114. data/lib/rggen/builtins/global/data_width.rb +0 -20
  115. data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
  116. data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
  117. data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
  118. data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
  119. data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
  120. data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
  121. data/lib/rggen/builtins/register/array.rb +0 -30
  122. data/lib/rggen/builtins/register/constructor.rb +0 -17
  123. data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
  124. data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
  125. data/lib/rggen/builtins/register/name.rb +0 -26
  126. data/lib/rggen/builtins/register/offset_address.rb +0 -61
  127. data/lib/rggen/builtins/register/reg_model.rb +0 -107
  128. data/lib/rggen/builtins/register/rtl_top.rb +0 -68
  129. data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
  130. data/lib/rggen/builtins/register/type.rb +0 -283
  131. data/lib/rggen/builtins/register/types/default.erb +0 -10
  132. data/lib/rggen/builtins/register/types/external.erb +0 -11
  133. data/lib/rggen/builtins/register/types/external.rb +0 -77
  134. data/lib/rggen/builtins/register/types/indirect.erb +0 -13
  135. data/lib/rggen/builtins/register/types/indirect.rb +0 -175
  136. data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
  137. data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
  138. data/lib/rggen/builtins/register_block/base_address.rb +0 -64
  139. data/lib/rggen/builtins/register_block/block_model.rb +0 -20
  140. data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
  141. data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
  142. data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
  143. data/lib/rggen/builtins/register_block/constructor.rb +0 -14
  144. data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
  145. data/lib/rggen/builtins/register_block/host_if.rb +0 -64
  146. data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
  147. data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
  148. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
  149. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
  150. data/lib/rggen/builtins/register_block/name.rb +0 -26
  151. data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
  152. data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
  153. data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
  154. data/lib/rggen/commands.rb +0 -23
  155. data/lib/rggen/core_components.rb +0 -54
  156. data/lib/rggen/core_components/c_header/item.rb +0 -8
  157. data/lib/rggen/core_components/c_header/setup.rb +0 -19
  158. data/lib/rggen/core_components/c_utility.rb +0 -19
  159. data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
  160. data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
  161. data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
  162. data/lib/rggen/core_components/code_utility.rb +0 -56
  163. data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
  164. data/lib/rggen/core_components/code_utility/line.rb +0 -28
  165. data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
  166. data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
  167. data/lib/rggen/core_components/configuration/item.rb +0 -11
  168. data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
  169. data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
  170. data/lib/rggen/core_components/configuration/setup.rb +0 -14
  171. data/lib/rggen/core_components/erb_engine.rb +0 -15
  172. data/lib/rggen/core_components/ral/component.rb +0 -24
  173. data/lib/rggen/core_components/ral/item.rb +0 -59
  174. data/lib/rggen/core_components/ral/setup.rb +0 -19
  175. data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
  176. data/lib/rggen/core_components/register_map/component.rb +0 -15
  177. data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
  178. data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
  179. data/lib/rggen/core_components/register_map/item.rb +0 -26
  180. data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
  181. data/lib/rggen/core_components/register_map/loader.rb +0 -11
  182. data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
  183. data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
  184. data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
  185. data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
  186. data/lib/rggen/core_components/register_map/setup.rb +0 -33
  187. data/lib/rggen/core_components/rtl/component.rb +0 -24
  188. data/lib/rggen/core_components/rtl/item.rb +0 -82
  189. data/lib/rggen/core_components/rtl/setup.rb +0 -19
  190. data/lib/rggen/core_components/verilog_utility.rb +0 -88
  191. data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
  192. data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
  193. data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
  194. data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
  195. data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
  196. data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
  197. data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
  198. data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
  199. data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
  200. data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
  201. data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
  202. data/lib/rggen/core_extensions/array.rb +0 -9
  203. data/lib/rggen/core_extensions/facets.rb +0 -22
  204. data/lib/rggen/core_extensions/forwardable.rb +0 -49
  205. data/lib/rggen/core_extensions/integer.rb +0 -5
  206. data/lib/rggen/core_extensions/math.rb +0 -7
  207. data/lib/rggen/core_extensions/roo.rb +0 -17
  208. data/lib/rggen/exceptions.rb +0 -28
  209. data/lib/rggen/generator.rb +0 -67
  210. data/lib/rggen/input_base/component.rb +0 -28
  211. data/lib/rggen/input_base/component_factory.rb +0 -58
  212. data/lib/rggen/input_base/item.rb +0 -171
  213. data/lib/rggen/input_base/item_factory.rb +0 -13
  214. data/lib/rggen/input_base/loader.rb +0 -23
  215. data/lib/rggen/input_base/regexp_patterns.rb +0 -29
  216. data/lib/rggen/option_switches.rb +0 -60
  217. data/lib/rggen/options.rb +0 -97
  218. data/lib/rggen/output_base/code_generator.rb +0 -36
  219. data/lib/rggen/output_base/component.rb +0 -78
  220. data/lib/rggen/output_base/component_factory.rb +0 -32
  221. data/lib/rggen/output_base/file_writer.rb +0 -36
  222. data/lib/rggen/output_base/item.rb +0 -110
  223. data/lib/rggen/output_base/item_factory.rb +0 -9
  224. data/lib/rggen/output_base/template_engine.rb +0 -24
  225. data/lib/rggen/rggen_home.rb +0 -3
  226. data/ral/LICENSE +0 -21
  227. data/ral/compile.f +0 -2
  228. data/ral/rggen_ral_block.svh +0 -83
  229. data/ral/rggen_ral_field.svh +0 -47
  230. data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
  231. data/ral/rggen_ral_indirect_reg.svh +0 -193
  232. data/ral/rggen_ral_macros.svh +0 -27
  233. data/ral/rggen_ral_map.svh +0 -124
  234. data/ral/rggen_ral_pkg.sv +0 -15
  235. data/ral/rggen_ral_reg.svh +0 -88
  236. data/rtl/LICENSE +0 -21
  237. data/rtl/compile.f +0 -18
  238. data/rtl/rggen_address_decoder.sv +0 -23
  239. data/rtl/rggen_apb_if.sv +0 -41
  240. data/rtl/rggen_axi4lite_if.sv +0 -68
  241. data/rtl/rggen_bit_field_if.sv +0 -28
  242. data/rtl/rggen_bit_field_ro.sv +0 -9
  243. data/rtl/rggen_bit_field_rw.sv +0 -25
  244. data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
  245. data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
  246. data/rtl/rggen_bus_if.sv +0 -43
  247. data/rtl/rggen_bus_splitter.sv +0 -86
  248. data/rtl/rggen_default_register.sv +0 -15
  249. data/rtl/rggen_external_register.sv +0 -83
  250. data/rtl/rggen_host_if_apb.sv +0 -29
  251. data/rtl/rggen_host_if_axi4lite.sv +0 -161
  252. data/rtl/rggen_indirect_register.sv +0 -21
  253. data/rtl/rggen_register_base.sv +0 -57
  254. data/rtl/rggen_register_if.sv +0 -42
  255. data/rtl/rggen_rtl_pkg.sv +0 -23
  256. data/sample/LICENSE +0 -21
  257. data/sample/sample.csv +0 -21
  258. data/sample/sample.json +0 -6
  259. data/sample/sample.xls +0 -0
  260. data/sample/sample.xlsx +0 -0
  261. data/sample/sample.yaml +0 -4
  262. data/sample/sample_0.h +0 -17
  263. data/sample/sample_0.sv +0 -402
  264. data/sample/sample_0_ral_pkg.sv +0 -145
  265. data/sample/sample_1.h +0 -9
  266. data/sample/sample_1.sv +0 -128
  267. data/sample/sample_1_ral_pkg.sv +0 -56
  268. data/sample/sample_setup.rb +0 -24
  269. data/setup/default.rb +0 -14
@@ -1,38 +0,0 @@
1
- define_simple_item :register_block, :rtl_top do
2
- rtl do
3
- write_file '<%= register_block.name %>.sv' do |f|
4
- f.body { source_file_body }
5
- end
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-
7
- def source_file_body
8
- module_definition register_block.name do |m|
9
- m.parameters register_block.parameter_declarations(:register_block)
10
- m.ports register_block.port_declarations(:register_block)
11
- m.signals register_block.signal_declarations(:register_block)
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- m.body { |code| module_body(code) }
13
- end
14
- end
15
-
16
- def module_body(code)
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- register_block.generate_code(:register_block, :top_down, code)
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- end
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-
20
- generate_pre_code :register_block do |code|
21
- [
22
- '`define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \\',
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- 'assign FIF.read_access = RIF.read_access; \\',
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- 'assign FIF.write_access = RIF.write_access; \\',
25
- 'assign FIF.write_data = RIF.write_data[MSB:LSB]; \\',
26
- 'assign FIF.write_mask = RIF.write_mask[MSB:LSB]; \\',
27
- 'assign RIF.value[MSB:LSB] = FIF.value; \\',
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- 'assign RIF.read_data[MSB:LSB] = FIF.read_data;'
29
- ].each do |line|
30
- code << line << nl
31
- end
32
- end
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-
34
- generate_post_code :register_block do |code|
35
- code << :'`undef rggen_connect_bit_field_if' << nl
36
- end
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- end
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- end
@@ -1,14 +0,0 @@
1
- simple_item :register_block, :sub_model_creator do
2
- ral do
3
- generate_code :block_model_item do
4
- function_definition :create_sub_models do |f|
5
- f.return_type :void
6
- f.body { |code| function_body(code) }
7
- end
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- end
9
-
10
- def function_body(code)
11
- register_block.registers.each { |r| r.model_creation(code) }
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- end
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- end
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- end
@@ -1,23 +0,0 @@
1
- module RgGen
2
- def self.builder
3
- @builder ||= Builder::Builder.new
4
- end
5
-
6
- module Commands
7
- extend Forwardable
8
-
9
- [
10
- [:input_component_store , :input_component_store ],
11
- [:output_component_store, :output_component_store],
12
- [:define_simple_item , :simple_item ],
13
- [:define_list_item , :list_item ],
14
- [:enable , :enable ],
15
- [:define_loader , :loader ]
16
- ].each do |method_name, alias_name|
17
- def_delegator('RgGen.builder', method_name)
18
- alias_method(alias_name, method_name) if method_name != alias_name
19
- end
20
- end
21
- end
22
-
23
- include RgGen::Commands
@@ -1,54 +0,0 @@
1
- require_relative 'core_components/erb_engine'
2
-
3
- require_relative 'core_components/code_utility/line'
4
- require_relative 'core_components/code_utility/code_block'
5
- require_relative 'core_components/code_utility/source_file'
6
- require_relative 'core_components/code_utility'
7
-
8
- require_relative 'core_components/verilog_utility/identifier'
9
- require_relative 'core_components/verilog_utility/variable'
10
- require_relative 'core_components/verilog_utility/structure_definition'
11
- require_relative 'core_components/verilog_utility/local_scope'
12
- require_relative 'core_components/verilog_utility/module_definition'
13
- require_relative 'core_components/verilog_utility/package_definition'
14
- require_relative 'core_components/verilog_utility/class_definition'
15
- require_relative 'core_components/verilog_utility/subroutine_definition'
16
- require_relative 'core_components/verilog_utility/interface_instance'
17
- require_relative 'core_components/verilog_utility/interface_port'
18
- require_relative 'core_components/verilog_utility/source_file'
19
- require_relative 'core_components/verilog_utility'
20
-
21
- require_relative 'core_components/c_utility/variable_declaration'
22
- require_relative 'core_components/c_utility/data_structure_definition'
23
- require_relative 'core_components/c_utility/source_file'
24
- require_relative 'core_components/c_utility'
25
-
26
- require_relative 'core_components/configuration/raise_error'
27
- require_relative 'core_components/configuration/item'
28
- require_relative 'core_components/configuration/configuration_factory'
29
- require_relative 'core_components/configuration/item_factory'
30
- require_relative 'core_components/configuration/setup'
31
-
32
- require_relative 'core_components/register_map/generic_map'
33
- require_relative 'core_components/register_map/loader'
34
- require_relative 'core_components/register_map/raise_error'
35
- require_relative 'core_components/register_map/component'
36
- require_relative 'core_components/register_map/item'
37
- require_relative 'core_components/register_map/component_factory'
38
- require_relative 'core_components/register_map/register_map_factory'
39
- require_relative 'core_components/register_map/register_block_factory'
40
- require_relative 'core_components/register_map/register_factory'
41
- require_relative 'core_components/register_map/bit_field_factory'
42
- require_relative 'core_components/register_map/item_factory'
43
- require_relative 'core_components/register_map/setup'
44
-
45
- require_relative 'core_components/rtl/component'
46
- require_relative 'core_components/rtl/item'
47
- require_relative 'core_components/rtl/setup'
48
-
49
- require_relative 'core_components/ral/component'
50
- require_relative 'core_components/ral/item'
51
- require_relative 'core_components/ral/setup'
52
-
53
- require_relative 'core_components/c_header/item'
54
- require_relative 'core_components/c_header/setup'
@@ -1,8 +0,0 @@
1
- module RgGen
2
- module CHeader
3
- class Item < OutputBase::Item
4
- include CUtility
5
- template_engine ERBEngine
6
- end
7
- end
8
- end
@@ -1,19 +0,0 @@
1
- module RgGen
2
- module CHeader
3
- output_component_store :c_header do
4
- entry do
5
- component_class OutputBase::Component
6
- component_factory OutputBase::ComponentFactory
7
- end
8
-
9
- entry [:register_block, :register, :bit_field] do
10
- component_class OutputBase::Component
11
- component_factory OutputBase::ComponentFactory
12
- item_base Item
13
- item_factory OutputBase::ItemFactory
14
- end
15
-
16
- output_directory 'c_header'
17
- end
18
- end
19
- end
@@ -1,19 +0,0 @@
1
- module RgGen
2
- module CUtility
3
- include CodeUtility
4
-
5
- def create_blank_file(path)
6
- SourceFile.new(path)
7
- end
8
-
9
- private
10
-
11
- def variable_declaration(attributes)
12
- VariableDeclaration.new(attributes)
13
- end
14
-
15
- def struct_definition(type_name, &body)
16
- DataStructureDefinition.new(:struct, type_name, &body).to_code
17
- end
18
- end
19
- end
@@ -1,60 +0,0 @@
1
- module RgGen
2
- module CUtility
3
- class DataStructureDefinition
4
- include CodeUtility
5
-
6
- def initialize(type_keyword, type_name)
7
- @type_keyword = type_keyword
8
- @type_name = type_name
9
- yield(self) if block_given?
10
- end
11
-
12
- attr_setter :members
13
-
14
- def with_typedef(typedef_name = nil)
15
- @with_typedef = true
16
- @typedef_name = typedef_name
17
- end
18
-
19
- def to_code
20
- code_block do |code|
21
- header_code(code)
22
- body_code(code)
23
- footer_code(code)
24
- end
25
- end
26
-
27
- private
28
-
29
- def header_code(code)
30
- code << [
31
- typedef, @type_keyword, type_name, '{'
32
- ].compact.join(space) << nl
33
- end
34
-
35
- def body_code(code)
36
- indent(code, 2) do
37
- @members.each { |member| code << member << semicolon << nl }
38
- end
39
- end
40
-
41
- def footer_code(code)
42
- code << ['}', typedef_name].compact.join(space) << semicolon << nl
43
- end
44
-
45
- def typedef
46
- @with_typedef && :typedef
47
- end
48
-
49
- def type_name
50
- return @type_name unless @with_typedef
51
- @typedef_name && @type_name
52
- end
53
-
54
- def typedef_name
55
- return nil unless @with_typedef
56
- @typedef_name || @type_name
57
- end
58
- end
59
- end
60
- end
@@ -1,10 +0,0 @@
1
- module RgGen
2
- module CUtility
3
- class SourceFile < CodeUtility::SourceFile
4
- ifndef_keyword :'#ifndef'
5
- endif_keyword :'#endif'
6
- define_keyword :'#define'
7
- include_keyword :'#include'
8
- end
9
- end
10
- end
@@ -1,35 +0,0 @@
1
- module RgGen
2
- module CUtility
3
- class VariableDeclaration
4
- def initialize(attributes)
5
- @attributes = attributes
6
- end
7
-
8
- def to_s
9
- [
10
- data_type, identifier, default_value_assignment
11
- ].compact.join(' ')
12
- end
13
-
14
- private
15
-
16
- def data_type
17
- @attributes[:data_type]
18
- end
19
-
20
- def identifier
21
- "#{@attributes[:name]}#{dimensions}"
22
- end
23
-
24
- def dimensions
25
- return unless @attributes[:dimensions]
26
- @attributes[:dimensions].map { |d| "[#{d}]" }.join
27
- end
28
-
29
- def default_value_assignment
30
- return unless @attributes[:default]
31
- "= #{@attributes[:default]}"
32
- end
33
- end
34
- end
35
- end
@@ -1,56 +0,0 @@
1
- module RgGen
2
- module CodeUtility
3
- def create_blank_code
4
- CodeBlock.new
5
- end
6
-
7
- private
8
-
9
- def newline
10
- :newline
11
- end
12
-
13
- alias_method :nl, :newline
14
-
15
- def comma
16
- ','
17
- end
18
-
19
- def semicolon
20
- ';'
21
- end
22
-
23
- def space(size = 1)
24
- ' ' * size
25
- end
26
-
27
- def string(expression)
28
- "\"#{expression}\""
29
- end
30
-
31
- def code_block(indent_size = 0)
32
- CodeBlock.new.tap do |code|
33
- code.indent = indent_size
34
- yield(code) if block_given?
35
- end
36
- end
37
-
38
- def indent(code_block, indent_size)
39
- code_block << nl unless code_block.last_line_empty?
40
- code_block.indent += indent_size
41
- yield if block_given?
42
- code_block << nl unless code_block.last_line_empty?
43
- code_block.indent -= indent_size
44
- end
45
-
46
- def wrap(code_block, head, tail)
47
- code_block << head
48
- yield if block_given?
49
- code_block << tail
50
- end
51
-
52
- def loop_index(level)
53
- level.times.with_object('i') { |_, index| index.next! }
54
- end
55
- end
56
- end
@@ -1,72 +0,0 @@
1
- module RgGen
2
- module CodeUtility
3
- class CodeBlock
4
- def initialize
5
- @lines = []
6
- @indent = 0
7
- add_newline
8
- end
9
-
10
- attr_reader :indent
11
-
12
- def indent=(value)
13
- @indent = value
14
- @lines.last.indent = @indent
15
- end
16
-
17
- def <<(other)
18
- case other
19
- when CodeBlock
20
- merge_code_block(other)
21
- when /\n/
22
- add_multiple_lines_string(other)
23
- when :newline
24
- add_newline
25
- else
26
- @lines.last << other
27
- end
28
- self
29
- end
30
-
31
- def last_line_empty?
32
- lines.empty? || lines.last.empty?
33
- end
34
-
35
- def to_s
36
- @lines.map(&:to_s).each(&:rstrip!).join("\n")
37
- end
38
-
39
- private
40
-
41
- def add_newline
42
- line = Line.new
43
- line.indent = @indent
44
- @lines << line
45
- end
46
-
47
- def merge_code_block(other_block)
48
- other_block.lines.each_with_index do |line, i|
49
- line.indent += @indent
50
- if i.zero?
51
- @lines.last.indent = line.indent if last_line_empty?
52
- @lines.last.words.concat(line.words)
53
- else
54
- @lines << line
55
- end
56
- end
57
- @lines.last.indent = @indent if other_block.last_line_empty?
58
- end
59
-
60
- def add_multiple_lines_string(other_string)
61
- other_string.each_line.with_index do |line, i|
62
- add_newline if i > 0
63
- @lines.last << line
64
- end
65
- add_newline if other_string.end_with?("\n")
66
- end
67
-
68
- attr_reader :lines
69
- protected :lines
70
- end
71
- end
72
- end
@@ -1,28 +0,0 @@
1
- module RgGen
2
- module CodeUtility
3
- class Line
4
- def initialize
5
- @words = []
6
- @not_empty = false
7
- @indent = 0
8
- end
9
-
10
- attr_reader :words
11
- attr_accessor :indent
12
-
13
- def <<(word)
14
- @words << word.to_s
15
- self
16
- end
17
-
18
- def empty?
19
- @words.all?(&:empty?)
20
- end
21
-
22
- def to_s
23
- return '' if @words.empty?
24
- @words.join.indent(@indent)
25
- end
26
- end
27
- end
28
- end