rggen 0.8.2 → 0.9.0

data/lib/rggen/builtins/register_block/block_model.rb

@@ -1,20 +0,0 @@
-simple_item :register_block, :block_model do
-  ral do
-    generate_code :package_item do
-      class_definition model_name do |c|
-        c.base       :rggen_ral_block
-        c.variables  register_block.variable_declarations(:block_model)
-        c.parameters register_block.parameter_declarations(:block_model)
-        c.body { |code| body_code(code) }
-      end
-    end
-
-    def model_name
-      "#{register_block.name}_block_model"
-    end
-
-    def body_code(code)
-      register_block.generate_code(:block_model_item, :top_down, code)
-    end
-  end
-end

data/lib/rggen/builtins/register_block/byte_size.rb

@@ -1,37 +0,0 @@
-simple_item :register_block, :byte_size do
-  register_map do
-    field :byte_size
-    field :local_address_width
-
-    build do |cell|
-      begin
-        @byte_size  = Integer(cell)
-      rescue
-        error "invalid value for byte size: #{cell.inspect}"
-      end
-
-      case
-      when @byte_size.not.positive?
-        error "zero or negative value is not allowed for byte size: #{cell}"
-      when @byte_size.not.multiple?(configuration.byte_width)
-        error 'not aligned with data width' \
-              "(#{configuration.data_width}): #{cell}"
-      when total_byte_size > upper_bound
-        error 'exceeds upper bound of total byte size' \
-              "(#{upper_bound}): #{total_byte_size}"
-      end
-
-      @local_address_width  = Math.clog2(@byte_size)
-    end
-
-    def upper_bound
-      2**configuration.address_width
-    end
-
-    def total_byte_size
-      register_map.register_blocks.inject(@byte_size) do |total, block|
-        total + block.byte_size
-      end
-    end
-  end
-end

data/lib/rggen/builtins/register_block/c_header_file.rb

@@ -1,15 +0,0 @@
-simple_item :register_block, :c_header_file do
-  c_header do
-    delegate [:name] => :register_block
-
-    write_file '<%= name %>.h' do |f|
-      f.include_guard
-      f.include_file 'rggen.h'
-      f.body { |code| source_file_body(code) }
-    end
-
-    def source_file_body(code)
-      register_block.generate_code(:c_header_item, :top_down, code)
-    end
-  end
-end

data/lib/rggen/builtins/register_block/clock_reset.rb

@@ -1,8 +0,0 @@
-simple_item :register_block, :clock_reset do
-  rtl do
-    build do
-      input :register_block, :clock, name: 'clk'  , data_type: :logic, width: 1
-      input :register_block, :reset, name: 'rst_n', data_type: :logic, width: 1
-    end
-  end
-end

data/lib/rggen/builtins/register_block/constructor.rb

@@ -1,14 +0,0 @@
-simple_item :register_block, :constructor do
-  ral do
-    delegate [:name] => :register_block
-
-    generate_code :block_model_item do
-      function_definition :new do |f|
-        f.arguments [
-          argument(:name, data_type: :string, default: string(name))
-        ]
-        f.body { 'super.new(name);' }
-      end
-    end
-  end
-end

data/lib/rggen/builtins/register_block/default_map_creator.rb

@@ -1,39 +0,0 @@
-simple_item :register_block, :default_map_creator do
-  ral do
-    generate_code :block_model_item do
-      function_definition :create_default_map do |f|
-        f.return_type :uvm_reg_map
-        f.body do |code|
-          code << :return
-          code << space
-          code << subroutine_call(:create_map, arguments)
-          code << semicolon
-        end
-      end
-    end
-
-    def arguments
-      [name, base_address, n_bytes, endian, byte_addressing]
-    end
-
-    def name
-      string(:default_map)
-    end
-
-    def base_address
-      0
-    end
-
-    def n_bytes
-      configuration.byte_width
-    end
-
-    def endian
-      :UVM_LITTLE_ENDIAN
-    end
-
-    def byte_addressing
-      1
-    end
-  end
-end

data/lib/rggen/builtins/register_block/host_if.rb

@@ -1,64 +0,0 @@
-list_item :register_block, :host_if do
-  shared_context do
-    attr_accessor :enabled_host_ifs
-  end
-
-  configuration do
-    item_base do
-      field :host_if do
-        @host_if || shared_context.enabled_host_ifs.first
-      end
-
-      build do |value|
-        @host_if  = value
-      end
-    end
-
-    default_item do
-    end
-
-    factory do
-      def select_target_item(value)
-        @target_items[value]
-      end
-
-      def convert(value)
-        find_host_if(value) do
-          error "unknown host interface: #{value}"
-        end
-      end
-
-      def find_host_if(value, &ifnone)
-        shared_context.enabled_host_ifs.find(ifnone) do |host_if|
-          host_if.to_sym.casecmp(value.to_sym).zero?
-        end
-      end
-    end
-  end
-
-  rtl do
-    shared_context.enabled_host_ifs = @enabled_items
-
-    item_base do
-      delegate [:local_address_width, :clock, :reset] => :register_block
-      delegate [:data_width, :unfold_sv_interface_port?] => :configuration
-
-      build do
-        interface :register_block, :register_if,
-                  type: :rggen_register_if,
-                  parameters: [local_address_width, data_width],
-                  dimensions: [total_registers]
-      end
-
-      def total_registers
-        register_block.registers.sum(0, &:count)
-      end
-    end
-
-    factory do
-      def select_target_item(configuration, _register_block)
-        @target_items[configuration.host_if]
-      end
-    end
-  end
-end

data/lib/rggen/builtins/register_block/host_ifs/apb.erb

@@ -1,10 +0,0 @@
-rggen_host_if_apb #(
-  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
-  .DATA_WIDTH           (<%= data_width %>),
-  .TOTAL_REGISTERS      (<%= total_registers %>)
-) u_host_if (
-  .clk          (<%= clock %>),
-  .rst_n        (<%= reset %>),
-  .apb_if       (<%= apb_if %>),
-  .register_if  (<%= register_if %>)
-);

data/lib/rggen/builtins/register_block/host_ifs/apb.rb

@@ -1,64 +0,0 @@
-list_item :register_block, :host_if, :apb do
-  configuration do
-    validate do
-      if configuration.address_width > 32
-        error 'apb supports 32 or less bits address width only' \
-              ": #{configuration.address_width}"
-      end
-      if configuration.data_width > 32
-        error 'apb supports 32 or less bits data width only' \
-              ": #{configuration.data_width}"
-      end
-    end
-  end
-
-  rtl do
-    build do
-      if unfold_sv_interface_port?
-        input :register_block, :psel,
-          name: 'i_psel', data_type: :logic, width: 1
-        input :register_block, :penable,
-          name: 'i_penable', data_type: :logic, width: 1
-        input :register_block, :paddr,
-          name: 'i_paddr', data_type: :logic, width: local_address_width
-        input :register_block, :pprot,
-          name: 'i_pprot', data_type: :logic, width: 3
-        input :register_block, :pwrite,
-          name: 'i_pwrite', data_type: :logic, width: 1
-        input :register_block, :pwdata,
-          name: 'i_pwdata', data_type: :logic, width: data_width
-        input :register_block, :pstrb,
-          name: 'i_pstrb', data_type: :logic, width: data_width / 8
-        output :register_block, :pready,
-          name: 'o_pready', data_type: :logic, width: 1
-        output :register_block, :prdata,
-          name: 'o_prdata', data_type: :logic, width: data_width
-        output :register_block, :pslverr,
-          name: 'o_pslverr', data_type: :logic, width: 1
-        interface :register_block, :apb_if,
-          type: :rggen_apb_if, parameters: [local_address_width, data_width]
-      else
-        interface_port :register_block, :apb_if,
-          type: :rggen_apb_if, modport:  :slave
-      end
-    end
-
-    generate_code :register_block do |code|
-      unfold_sv_interface_port? && apb_if_assignment(code)
-      code << process_template
-    end
-
-    def apb_if_assignment(code)
-      code << assign("#{apb_if}.psel"   , psel   ) << nl
-      code << assign("#{apb_if}.penable", penable) << nl
-      code << assign("#{apb_if}.paddr"  , paddr  ) << nl
-      code << assign("#{apb_if}.pprot"  , pprot  ) << nl
-      code << assign("#{apb_if}.pwrite" , pwrite ) << nl
-      code << assign("#{apb_if}.pwdata" , pwdata ) << nl
-      code << assign("#{apb_if}.pstrb"  , pstrb  ) << nl
-      code << assign(pready , "#{apb_if}.pready" ) << nl
-      code << assign(prdata , "#{apb_if}.prdata" ) << nl
-      code << assign(pslverr, "#{apb_if}.pslverr") << nl
-    end
-  end
-end

data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb

@@ -1,11 +0,0 @@
-rggen_host_if_axi4lite #(
-  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
-  .DATA_WIDTH           (<%= data_width %>),
-  .TOTAL_REGISTERS      (<%= total_registers %>),
-  .ACCESS_PRIORITY      (<%= access_priority %>)
-) u_host_if (
-  .clk          (<%= clock %>),
-  .rst_n        (<%= reset %>),
-  .axi4lite_if  (<%= axi4lite_if %>),
-  .register_if  (<%= register_if %>)
-);

data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb

@@ -1,93 +0,0 @@
-list_item :register_block, :host_if, :axi4lite do
-  configuration do
-    validate do
-      unless [32, 64].include?(configuration.data_width)
-        error 'axi4lite supports either 32 or 64 bits data width only' \
-              ": #{configuration.data_width}"
-      end
-    end
-  end
-
-  rtl do
-    build do
-      parameter :register_block, :access_priority,
-        name:      'ACCESS_PRIORITY',
-        data_type: :'rggen_rtl_pkg::rggen_direction',
-        default:   :'rggen_rtl_pkg::RGGEN_WRITE'
-      if unfold_sv_interface_port?
-        input :register_block, :awvalid,
-          name: 'i_awvalid', data_type: :logic, width: 1
-        output :register_block, :awready,
-          name: 'o_awready', data_type: :logic, width: 1
-        input :register_block, :awaddr,
-          name: 'i_awaddr', data_type: :logic, width: local_address_width
-        input :register_block, :awprot,
-          name: 'i_awprot', data_type: :logic, width: 3
-        input :register_block, :wvalid,
-          name: 'i_wvalid', data_type: :logic, width: 1
-        output :register_block, :wready,
-          name: 'o_wready', data_type: :logic, width: 1
-        input :register_block, :wdata,
-          name: 'i_wdata', data_type: :logic, width: data_width
-        input :register_block, :wstrb,
-          name: 'i_wstrb', data_type: :logic, width: data_width / 8
-        output :register_block, :bvalid,
-          name: 'o_bvalid', data_type: :logic, width: 1
-        input :register_block, :bready,
-          name: 'i_bready', data_type: :logic, width: 1
-        output :register_block, :bresp,
-          name: 'o_bresp', data_type: :logic, width: 2
-        input :register_block, :arvalid,
-          name: 'i_arvalid', data_type: :logic, width: 1
-        output :register_block, :arready,
-          name: 'o_arready', data_type: :logic, width: 1
-        input :register_block, :araddr,
-          name: 'i_araddr', data_type: :logic, width: local_address_width
-        input :register_block, :arprot,
-          name: 'i_arprot', data_type: :logic, width: 3
-        output :register_block, :rvalid,
-          name: 'o_rvalid', data_type: :logic, width: 1
-        input :register_block, :rready,
-          name: 'i_rready', data_type: :logic, width: 1
-        output :register_block, :rdata,
-          name: 'o_rdata', data_type: :logic, width: data_width
-        output :register_block, :rresp,
-          name: 'o_rresp', data_type: :logic, width: 2
-        interface :register_block, :axi4lite_if,
-          type: :rggen_axi4lite_if,
-          parameters: [local_address_width, data_width]
-      else
-        interface_port :register_block, :axi4lite_if,
-          type:    :rggen_axi4lite_if,
-          modport: :slave
-      end
-    end
-
-    generate_code :register_block do |code|
-      unfold_sv_interface_port? && axi4lite_if_assignment(code)
-      code << process_template
-    end
-
-    def axi4lite_if_assignment(code)
-      code << assign("#{axi4lite_if}.awvalid", awvalid) << nl
-      code << assign(awready, "#{axi4lite_if}.awready") << nl
-      code << assign("#{axi4lite_if}.awaddr" , awaddr ) << nl
-      code << assign("#{axi4lite_if}.awprot" , awprot ) << nl
-      code << assign("#{axi4lite_if}.wvalid" , wvalid ) << nl
-      code << assign(wready , "#{axi4lite_if}.wready" ) << nl
-      code << assign("#{axi4lite_if}.wdata"  , wdata  ) << nl
-      code << assign("#{axi4lite_if}.wstrb"  , wstrb  ) << nl
-      code << assign(bvalid , "#{axi4lite_if}.bvalid" ) << nl
-      code << assign("#{axi4lite_if}.bready" , bready ) << nl
-      code << assign(bresp  , "#{axi4lite_if}.bresp"  ) << nl
-      code << assign("#{axi4lite_if}.arvalid", arvalid) << nl
-      code << assign(arready, "#{axi4lite_if}.arready") << nl
-      code << assign("#{axi4lite_if}.araddr" , araddr ) << nl
-      code << assign("#{axi4lite_if}.arprot" , arprot ) << nl
-      code << assign(rvalid , "#{axi4lite_if}.rvalid" ) << nl
-      code << assign("#{axi4lite_if}.rready" , rready ) << nl
-      code << assign(rdata  , "#{axi4lite_if}.rdata"  ) << nl
-      code << assign(rresp  , "#{axi4lite_if}.rresp"  ) << nl
-    end
-  end
-end

data/lib/rggen/builtins/register_block/name.rb

@@ -1,26 +0,0 @@
-simple_item :register_block, :name do
-  register_map do
-    field :name
-
-    input_pattern %r{(#{variable_name})}
-
-    build do |cell|
-      @name = parse_name(cell)
-      error "repeated register block name: #{@name}" if repeated_name?
-    end
-
-    def parse_name(cell)
-      if pattern_matched?
-        captures.first
-      else
-        error "invalid value for register block name: #{cell.inspect}"
-      end
-    end
-
-    def repeated_name?
-      register_map.register_blocks.any? do |block|
-        @name == block.name
-      end
-    end
-  end
-end

data/lib/rggen/builtins/register_block/ral_package.rb

@@ -1,24 +0,0 @@
-simple_item :register_block, :ral_package do
-  ral do
-    delegate :name => :register_block
-
-    write_file '<%= name %>_ral_pkg.sv' do |f|
-      f.include_guard
-      f.body { source_file_body }
-    end
-
-    def source_file_body
-      package_definition "#{name}_ral_pkg" do |pkg|
-        pkg.import_package :uvm_pkg
-        pkg.import_package :rggen_ral_pkg
-        pkg.include_file   'uvm_macros.svh'
-        pkg.include_file   'rggen_ral_macros.svh'
-        pkg.body { |code| body_code(code) }
-      end
-    end
-
-    def body_code(code)
-      register_block.generate_code(:package_item, :bottom_up, code)
-    end
-  end
-end