rggen 0.8.2 → 0.9.0

data/lib/rggen/built_in/register_block/sv_ral_block_model.erb

@@ -0,0 +1,11 @@
+function new(string name);
+  super.new(name);
+endfunction
+function void build();
+<% reg_model_constructors.each do |constructor| %>
+  <%= constructor %>
+<% end %>
+endfunction
+function uvm_reg_map create_default_map();
+  return create_map("default_map", 0, <%= byte_width %>, UVM_LITTLE_ENDIAN, 1);
+endfunction

data/lib/rggen/built_in/register_block/sv_ral_package.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_ral_package) do
+  sv_ral do
+    write_file '<%= package_name %>.sv' do |file|
+      file.body do
+        package_definition(package_name) do |package|
+          package.package_imports [
+            'uvm_pkg', 'rggen_ral_pkg'
+          ]
+          package.include_files [
+            'uvm_macros.svh', 'rggen_ral_macros.svh'
+          ]
+          package.body do |code|
+            register_block.generate_code(:ral_package, :bottom_up, code)
+          end
+        end
+      end
+    end
+
+    main_code :ral_package do
+      class_definition(model_name) do |sv_class|
+        sv_class.base 'rggen_ral_block'
+        sv_class.parameters parameters
+        sv_class.variables variables
+        sv_class.body do
+          process_template(File.join(__dir__, 'sv_ral_block_model.erb'))
+        end
+      end
+    end
+
+    private
+
+    def package_name
+      "#{register_block.name}_ral_pkg"
+    end
+
+    def model_name
+      "#{register_block.name}_block_model"
+    end
+
+    def parameters
+      register_block.declarations(:register_block, :parameter)
+    end
+
+    def variables
+      register_block.declarations(:register_block, :variable)
+    end
+
+    def reg_model_constructors
+      register_block.registers.flat_map(&:constructors)
+    end
+
+    def byte_width
+      configuration.byte_width
+    end
+  end
+end

data/lib/rggen/built_in/register_block/sv_rtl_macros.erb

@@ -0,0 +1,9 @@
+`ifndef rggen_connect_bit_field_if
+  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
+  assign  FIF.valid                 = RIF.valid; \
+  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
+  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
+  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+`endif

data/lib/rggen/built_in/register_block/sv_rtl_top.rb

@@ -0,0 +1,87 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
+  sv_rtl do
+    export :total_registers
+
+    build do
+      input :register_block, :clock, {
+        name: 'i_clk',
+        data_type: :logic,
+        width: 1
+      }
+      input :register_block, :reset, {
+        name: 'i_rst_n',
+        data_type: :logic,
+        width: 1
+      }
+      interface :register_block, :register_if, {
+        name: 'register_if',
+        interface_type: 'rggen_register_if',
+        parameter_values: [address_width, bus_width, value_width],
+        array_size: [total_registers],
+        variables: ['value']
+      }
+    end
+
+    write_file '<%= register_block.name %>.sv' do |file|
+      file.body(&method(:body_code))
+    end
+
+    def total_registers
+      register_block
+        .registers
+        .map(&:count)
+        .inject(:+)
+    end
+
+    private
+
+    def address_width
+      register_block.local_address_width
+    end
+
+    def bus_width
+      configuration.bus_width
+    end
+
+    def value_width
+      register_block.registers.map(&:width).max
+    end
+
+    def body_code(code)
+      macro_definition(code)
+      sv_module_definition(code)
+    end
+
+    def macro_definition(code)
+      code << process_template(File.join(__dir__, 'sv_rtl_macros.erb'))
+    end
+
+    def sv_module_definition(code)
+      code << module_definition(register_block.name) do |sv_module|
+        sv_module.package_imports [:rggen_rtl_pkg]
+        sv_module.parameters parameters
+        sv_module.ports ports
+        sv_module.variables variables
+        sv_module.body(&method(:sv_module_body))
+      end
+    end
+
+    def parameters
+      register_block.declarations(:register_block, :parameter)
+    end
+
+    def ports
+      register_block.declarations(:register_block, :port)
+    end
+
+    def variables
+      register_block.declarations(:register_block, :variable)
+    end
+
+    def sv_module_body(code)
+      register_block.generate_code(:register_block, :top_down, code)
+    end
+  end
+end

data/lib/rggen/built_in/version.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+module RgGen
+  module BuiltIn
+    VERSION = '0.9.0'
+  end
+end

data/lib/rggen/default_setup_file.rb

@@ -0,0 +1,6 @@
+# frozen_string_literal: true
+
+module RgGen
+  DEFAULT_SETUP_FILE =
+    File.expand_path('setup/default.rb', __dir__).freeze
+end

data/lib/rggen/setup/default.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+require 'rggen/systemverilog'
+require 'rggen/built_in'
+require 'rggen/spreadsheet_loader'
+
+RgGen.enable :global, [
+  :bus_width, :address_width, :array_port_format, :fold_sv_interface_port
+]
+
+RgGen.enable :register_block, [:name, :byte_size]
+RgGen.enable :register, [:name, :offset_address, :size, :type]
+RgGen.enable :register, :type, [:external, :indirect]
+RgGen.enable :bit_field, [
+  :name, :bit_assignment, :type, :initial_value, :reference, :comment
+]
+RgGen.enable :bit_field, :type, [
+  :rc, :reserved, :ro, :rof, :rs, :rw, :rwe, :rwl, :w0c, :w1c, :w0s, :w1s, :wo
+]
+
+RgGen.enable :register_block, [:sv_rtl_top, :protocol]
+RgGen.enable :register_block, :protocol, [:apb, :axi4lite]
+RgGen.enable :register, [:sv_rtl_top]
+RgGen.enable :bit_field, [:sv_rtl_top]
+
+RgGen.enable :register_block, [:sv_ral_package]

data/lib/rggen/version.rb

@@ -1,6 +1,7 @@
+# frozen_string_literal: true
+
+require_relative 'built_in/version'
+
 module RgGen
-  MAJOR   = 0
-  MINOR   = 8
-  TEENY   = 2
-  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
+  VERSION = BuiltIn::VERSION
 end

data/sample/block_0.rb

@@ -0,0 +1,85 @@
+# frozen_string_literal: true
+
+register_block {
+  name 'block_0'
+  byte_size 256
+
+  register {
+    name 'register_0'
+    offset_address 0x00
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rw; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :rw; initial_value 0 }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 1; type :rw; initial_value 0 }
+  }
+
+  register {
+    name 'register_1'
+    offset_address 0x04
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :ro }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :ro }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 16, width: 8; type :rof; initial_value 0xab }
+    bit_field { name 'bit_field_3'; bit_assignment lsb: 24, width: 8; type :reserved }
+  }
+
+  register {
+    name 'register_2'
+    offset_address 0x04
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 4; type :wo; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 4; type :wo; initial_value 0 }
+  }
+
+  register {
+    name 'register_3'
+    offset_address 0x08
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :rc; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8 , width: 4; type :rc; initial_value 0; reference 'register_0.bit_field_0' }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 12, width: 4; type :ro;                  reference 'register_3.bit_field_1' }
+    bit_field { name 'bit_field_3'; bit_assignment lsb: 16, width: 4; type :rs; initial_value 0 }
+  }
+
+  register {
+    name 'register_4'
+    offset_address 0x0C
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 8; type :rwe; initial_value 0; reference 'register_0.bit_field_2' }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 16, width: 8; type :rwl; initial_value 0; reference 'register_0.bit_field_2' }
+  }
+
+  register {
+    name 'register_5'
+    offset_address 0x10
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0 , width: 4; type :w0c; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 4 , width: 4; type :w0c; initial_value 0; reference 'register_0.bit_field_0' }
+    bit_field { name 'bit_field_2'; bit_assignment lsb: 8 , width: 4; type :ro ;                  reference 'register_5.bit_field_1' }
+    bit_field { name 'bit_field_3'; bit_assignment lsb: 12, width: 4; type :w1c; initial_value 0 }
+    bit_field { name 'bit_field_4'; bit_assignment lsb: 16, width: 4; type :w1c; initial_value 0; reference 'register_0.bit_field_0' }
+    bit_field { name 'bit_field_5'; bit_assignment lsb: 20, width: 4; type :ro ;                  reference 'register_5.bit_field_4' }
+    bit_field { name 'bit_field_6'; bit_assignment lsb: 24, width: 4; type :w0s; initial_value 0 }
+    bit_field { name 'bit_field_7'; bit_assignment lsb: 28, width: 4; type :w1s; initial_value 0 }
+  }
+
+  register {
+    name 'register_6'
+    offset_address 0x20
+    size 4
+    # bit assignments: [7:0] [23:16] [39:32] [55:48]
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
+    # bit assignments: [15:8] [31:24] [47:40] [63:56]
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
+  }
+
+  register {
+    name 'register_7'
+    offset_address 0x40
+    size [2, 4]
+    type [:indirect, 'register_0.bit_field_0', 'register_0.bit_field_1', ['register_0.bit_field_2', 1]]
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
+  }
+
+  register {
+    name 'register_8'
+    offset_address 0x80
+    size 32
+    type :external
+  }
+}

data/sample/block_0.sv

@@ -0,0 +1,601 @@
+`ifndef rggen_connect_bit_field_if
+  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
+  assign  FIF.valid                 = RIF.valid; \
+  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
+  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
+  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+`endif
+module block_0
+  import rggen_rtl_pkg::*;
+(
+  input logic i_clk,
+  input logic i_rst_n,
+  rggen_apb_if.slave apb_if,
+  output logic [3:0] o_register_0_bit_field_0,
+  output logic [3:0] o_register_0_bit_field_1,
+  output logic o_register_0_bit_field_2,
+  input logic [3:0] i_register_1_bit_field_0,
+  input logic [3:0] i_register_1_bit_field_1,
+  output logic [3:0] o_register_2_bit_field_0,
+  output logic [3:0] o_register_2_bit_field_1,
+  input logic [3:0] i_register_3_bit_field_0_set,
+  output logic [3:0] o_register_3_bit_field_0,
+  input logic [3:0] i_register_3_bit_field_1_set,
+  output logic [3:0] o_register_3_bit_field_1,
+  output logic [3:0] o_register_3_bit_field_1_unmasked,
+  input logic [3:0] i_register_3_bit_field_3_clear,
+  output logic [3:0] o_register_3_bit_field_3,
+  output logic [7:0] o_register_4_bit_field_0,
+  output logic [7:0] o_register_4_bit_field_1,
+  input logic [3:0] i_register_5_bit_field_0_set,
+  output logic [3:0] o_register_5_bit_field_0,
+  input logic [3:0] i_register_5_bit_field_1_set,
+  output logic [3:0] o_register_5_bit_field_1,
+  output logic [3:0] o_register_5_bit_field_1_unmasked,
+  input logic [3:0] i_register_5_bit_field_3_set,
+  output logic [3:0] o_register_5_bit_field_3,
+  input logic [3:0] i_register_5_bit_field_4_set,
+  output logic [3:0] o_register_5_bit_field_4,
+  output logic [3:0] o_register_5_bit_field_4_unmasked,
+  input logic [3:0] i_register_5_bit_field_6_clear,
+  output logic [3:0] o_register_5_bit_field_6,
+  input logic [3:0] i_register_5_bit_field_7_clear,
+  output logic [3:0] o_register_5_bit_field_7,
+  output logic [3:0][3:0][7:0] o_register_6_bit_field_0,
+  output logic [3:0][3:0][7:0] o_register_6_bit_field_1,
+  output logic [1:0][3:0][3:0][7:0] o_register_7_bit_field_0,
+  output logic [1:0][3:0][3:0][7:0] o_register_7_bit_field_1,
+  rggen_bus_if.master register_8_bus_if
+);
+  rggen_register_if #(8, 32, 64) register_if[19]();
+  rggen_apb_adapter #(
+    .ADDRESS_WIDTH  (8),
+    .BUS_WIDTH      (32),
+    .REGISTERS      (19)
+  ) u_adapter (
+    .i_clk        (i_clk),
+    .i_rst_n      (i_rst_n),
+    .apb_if       (apb_if),
+    .register_if  (register_if)
+  );
+  generate if (1) begin : g_register_0
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (1),
+      .WRITABLE       (1),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h00),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'h000001ff),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[0]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_rw #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_value      (o_register_0_bit_field_0)
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
+      rggen_bit_field_rw #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_value      (o_register_0_bit_field_1)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(1) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 1)
+      rggen_bit_field_rw #(
+        .WIDTH          (1),
+        .INITIAL_VALUE  (1'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_value      (o_register_0_bit_field_2)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_1
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (1),
+      .WRITABLE       (0),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h04),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'hffff0f0f),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[1]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_ro #(
+        .WIDTH  (4)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (i_register_1_bit_field_0)
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
+      rggen_bit_field_ro #(
+        .WIDTH  (4)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (i_register_1_bit_field_1)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(8) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 8)
+      rggen_bit_field_ro #(
+        .WIDTH  (8)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (8'hab)
+      );
+    end
+    if (1) begin : g_bit_field_3
+      rggen_bit_field_if #(8) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 8)
+      rggen_bit_field_reserved u_bit_field (
+        .bit_field_if (bit_field_sub_if)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_2
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (0),
+      .WRITABLE       (1),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h04),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'h00000f0f),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[2]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_wo #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_value      (o_register_2_bit_field_0)
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
+      rggen_bit_field_wo #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .o_value      (o_register_2_bit_field_1)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_3
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (1),
+      .WRITABLE       (0),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h08),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'h000fff0f),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[3]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_rc #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_3_bit_field_0_set),
+        .i_mask           (4'hf),
+        .o_value          (o_register_3_bit_field_0),
+        .o_value_unmasked ()
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
+      rggen_bit_field_rc #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_3_bit_field_1_set),
+        .i_mask           (register_if[0].value[0+:4]),
+        .o_value          (o_register_3_bit_field_1),
+        .o_value_unmasked (o_register_3_bit_field_1_unmasked)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
+      rggen_bit_field_ro #(
+        .WIDTH  (4)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (register_if[3].value[8+:4])
+      );
+    end
+    if (1) begin : g_bit_field_3
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
+      rggen_bit_field_rs #(
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_clear      (i_register_3_bit_field_3_clear),
+        .o_value      (o_register_3_bit_field_3)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_4
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (1),
+      .WRITABLE       (1),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h0c),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'h00ff00ff),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[4]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(8) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 8)
+      rggen_bit_field_rwe #(
+        .WIDTH          (8),
+        .INITIAL_VALUE  (8'h00)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_enable     (register_if[0].value[8+:1]),
+        .o_value      (o_register_4_bit_field_0)
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(8) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 8)
+      rggen_bit_field_rwl #(
+        .WIDTH          (8),
+        .INITIAL_VALUE  (8'h00)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_lock       (register_if[0].value[8+:1]),
+        .o_value      (o_register_4_bit_field_1)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_5
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_default_register #(
+      .READABLE       (1),
+      .WRITABLE       (1),
+      .ADDRESS_WIDTH  (8),
+      .OFFSET_ADDRESS (8'h10),
+      .BUS_WIDTH      (32),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'hffffffff),
+      .REGISTER_INDEX (0)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[5]),
+      .bit_field_if (bit_field_if)
+    );
+    if (1) begin : g_bit_field_0
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 4)
+      rggen_bit_field_w01c #(
+        .CLEAR_VALUE    (1'b0),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_5_bit_field_0_set),
+        .i_mask           (4'hf),
+        .o_value          (o_register_5_bit_field_0),
+        .o_value_unmasked ()
+      );
+    end
+    if (1) begin : g_bit_field_1
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 4, 4)
+      rggen_bit_field_w01c #(
+        .CLEAR_VALUE    (1'b0),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_5_bit_field_1_set),
+        .i_mask           (register_if[0].value[0+:4]),
+        .o_value          (o_register_5_bit_field_1),
+        .o_value_unmasked (o_register_5_bit_field_1_unmasked)
+      );
+    end
+    if (1) begin : g_bit_field_2
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 4)
+      rggen_bit_field_ro #(
+        .WIDTH  (4)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (register_if[5].value[4+:4])
+      );
+    end
+    if (1) begin : g_bit_field_3
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 4)
+      rggen_bit_field_w01c #(
+        .CLEAR_VALUE    (1'b1),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_5_bit_field_3_set),
+        .i_mask           (4'hf),
+        .o_value          (o_register_5_bit_field_3),
+        .o_value_unmasked ()
+      );
+    end
+    if (1) begin : g_bit_field_4
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 4)
+      rggen_bit_field_w01c #(
+        .CLEAR_VALUE    (1'b1),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk            (i_clk),
+        .i_rst_n          (i_rst_n),
+        .bit_field_if     (bit_field_sub_if),
+        .i_set            (i_register_5_bit_field_4_set),
+        .i_mask           (register_if[0].value[0+:4]),
+        .o_value          (o_register_5_bit_field_4),
+        .o_value_unmasked (o_register_5_bit_field_4_unmasked)
+      );
+    end
+    if (1) begin : g_bit_field_5
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 20, 4)
+      rggen_bit_field_ro #(
+        .WIDTH  (4)
+      ) u_bit_field (
+        .bit_field_if (bit_field_sub_if),
+        .i_value      (register_if[5].value[16+:4])
+      );
+    end
+    if (1) begin : g_bit_field_6
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 24, 4)
+      rggen_bit_field_w01s #(
+        .SET_VALUE      (1'b0),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_clear      (i_register_5_bit_field_6_clear),
+        .o_value      (o_register_5_bit_field_6)
+      );
+    end
+    if (1) begin : g_bit_field_7
+      rggen_bit_field_if #(4) bit_field_sub_if();
+      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 28, 4)
+      rggen_bit_field_w01s #(
+        .SET_VALUE      (1'b1),
+        .WIDTH          (4),
+        .INITIAL_VALUE  (4'h0)
+      ) u_bit_field (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .bit_field_if (bit_field_sub_if),
+        .i_clear      (i_register_5_bit_field_7_clear),
+        .o_value      (o_register_5_bit_field_7)
+      );
+    end
+  end endgenerate
+  generate if (1) begin : g_register_6
+    genvar i;
+    for (i = 0;i < 4;++i) begin : g
+      rggen_bit_field_if #(64) bit_field_if();
+      rggen_default_register #(
+        .READABLE       (1),
+        .WRITABLE       (1),
+        .ADDRESS_WIDTH  (8),
+        .OFFSET_ADDRESS (8'h20),
+        .BUS_WIDTH      (32),
+        .DATA_WIDTH     (64),
+        .VALID_BITS     (64'hffffffffffffffff),
+        .REGISTER_INDEX (i)
+      ) u_register (
+        .i_clk        (i_clk),
+        .i_rst_n      (i_rst_n),
+        .register_if  (register_if[6+i]),
+        .bit_field_if (bit_field_if)
+      );
+      if (1) begin : g_bit_field_0
+        genvar j;
+        for (j = 0;j < 4;++j) begin : g
+          rggen_bit_field_if #(8) bit_field_sub_if();
+          `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*j, 8)
+          rggen_bit_field_rw #(
+            .WIDTH          (8),
+            .INITIAL_VALUE  (8'h00)
+          ) u_bit_field (
+            .i_clk        (i_clk),
+            .i_rst_n      (i_rst_n),
+            .bit_field_if (bit_field_sub_if),
+            .o_value      (o_register_6_bit_field_0[i][j])
+          );
+        end
+      end
+      if (1) begin : g_bit_field_1
+        genvar j;
+        for (j = 0;j < 4;++j) begin : g
+          rggen_bit_field_if #(8) bit_field_sub_if();
+          `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*j, 8)
+          rggen_bit_field_rw #(
+            .WIDTH          (8),
+            .INITIAL_VALUE  (8'h00)
+          ) u_bit_field (
+            .i_clk        (i_clk),
+            .i_rst_n      (i_rst_n),
+            .bit_field_if (bit_field_sub_if),
+            .o_value      (o_register_6_bit_field_1[i][j])
+          );
+        end
+      end
+    end
+  end endgenerate
+  generate if (1) begin : g_register_7
+    genvar i;
+    genvar j;
+    for (i = 0;i < 2;++i) begin : g
+      for (j = 0;j < 4;++j) begin : g
+        logic [8:0] indirect_index;
+        rggen_bit_field_if #(64) bit_field_if();
+        assign indirect_index = {register_if[0].value[0+:4], register_if[0].value[4+:4], register_if[0].value[8+:1]};
+        rggen_indirect_register #(
+          .READABLE             (1),
+          .WRITABLE             (1),
+          .ADDRESS_WIDTH        (8),
+          .OFFSET_ADDRESS       (8'h40),
+          .BUS_WIDTH            (32),
+          .DATA_WIDTH           (64),
+          .VALID_BITS           (64'hffffffffffffffff),
+          .INDIRECT_INDEX_WIDTH (9),
+          .INDIRECT_INDEX_VALUE ({i[0+:4], j[0+:4], 1'h1})
+        ) u_register (
+          .i_clk            (i_clk),
+          .i_rst_n          (i_rst_n),
+          .register_if      (register_if[10+4*i+j]),
+          .i_indirect_index (indirect_index),
+          .bit_field_if     (bit_field_if)
+        );
+        if (1) begin : g_bit_field_0
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
+            rggen_bit_field_rw #(
+              .WIDTH          (8),
+              .INITIAL_VALUE  (8'h00)
+            ) u_bit_field (
+              .i_clk        (i_clk),
+              .i_rst_n      (i_rst_n),
+              .bit_field_if (bit_field_sub_if),
+              .o_value      (o_register_7_bit_field_0[i][j][k])
+            );
+          end
+        end
+        if (1) begin : g_bit_field_1
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
+            rggen_bit_field_rw #(
+              .WIDTH          (8),
+              .INITIAL_VALUE  (8'h00)
+            ) u_bit_field (
+              .i_clk        (i_clk),
+              .i_rst_n      (i_rst_n),
+              .bit_field_if (bit_field_sub_if),
+              .o_value      (o_register_7_bit_field_1[i][j][k])
+            );
+          end
+        end
+      end
+    end
+  end endgenerate
+  generate if (1) begin : g_register_8
+    rggen_external_register #(
+      .ADDRESS_WIDTH  (8),
+      .BUS_WIDTH      (32),
+      .START_ADDRESS  (8'h80),
+      .END_ADDRESS    (8'hff)
+    ) u_register (
+      .i_clk        (i_clk),
+      .i_rst_n      (i_rst_n),
+      .register_if  (register_if[18]),
+      .bus_if       (register_8_bus_if)
+    );
+  end endgenerate
+endmodule