rggen 0.8.2 → 0.9.0

data/rtl/rggen_indirect_register.sv

@@ -1,21 +0,0 @@
-module rggen_indirect_register #(
-  parameter int                     ADDRESS_WIDTH = 16,
-  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
-  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
-  parameter int                     INDEX_WIDTH   = 1,
-  parameter bit [INDEX_WIDTH-1:0]   INDEX_VALUE   = '0,
-  parameter int                     DATA_WIDTH    = 32,
-  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
-)(
-  rggen_register_if.slave       register_if,
-  rggen_bit_field_if.master     bit_field_if,
-  input logic [INDEX_WIDTH-1:0] i_index
-);
-  logic index_match;
-
-  assign  index_match = (i_index == INDEX_VALUE) ? 1'b1 : 1'b0;
-  rggen_register_base #(
-    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS,
-    DATA_WIDTH, VALID_BITS
-  ) u_register_base (register_if, bit_field_if, index_match);
-endmodule

data/rtl/rggen_register_base.sv

@@ -1,57 +0,0 @@
-module rggen_register_base #(
-  parameter int                     ADDRESS_WIDTH = 16,
-  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
-  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
-  parameter int                     DATA_WIDTH    = 32,
-  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
-)(
-  rggen_register_if.slave   register_if,
-  rggen_bit_field_if.master bit_field_if,
-  input logic               i_additional_match
-);
-  import  rggen_rtl_pkg::*;
-
-  logic   address_match;
-  logic   select;
-  genvar  g_i;
-
-  //  Decode Address
-  assign  select  = (address_match && i_additional_match) ? 1'b1 : 1'b0;
-  rggen_address_decoder #(
-    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS, DATA_WIDTH
-  ) u_address_decoder (register_if.address, address_match);
-
-  //  Drive Register IF
-  assign  register_if.select    = select;
-  assign  register_if.ready     = (register_if.request && select) ? 1'b1 : 1'b0;
-  assign  register_if.status    = RGGEN_OKAY;
-
-  generate for (g_i = 0;g_i < DATA_WIDTH;++g_i) begin : g
-    if (VALID_BITS[g_i]) begin
-      assign  register_if.value[g_i]      = bit_field_if.value[g_i];
-      assign  register_if.read_data[g_i]  = bit_field_if.read_data[g_i];
-    end
-    else begin
-      assign  register_if.value[g_i]      = '0;
-      assign  register_if.read_data[g_i]  = '0;
-    end
-  end endgenerate
-
-  //  Drive Bit Field IF
-  assign  bit_field_if.read_access  = (
-    register_if.request && select && (register_if.direction == RGGEN_READ)
-  ) ? 1'b1 : 1'b0;
-  assign  bit_field_if.write_access = (
-    register_if.request && select && (register_if.direction == RGGEN_WRITE)
-  ) ? 1'b1 : 1'b0;
-  assign  bit_field_if.write_data   = register_if.write_data;
-  assign  bit_field_if.write_mask   = get_write_mask(register_if.write_strobe);
-
-  function automatic logic [DATA_WIDTH-1:0] get_write_mask(logic [DATA_WIDTH/8-1:0] strobe);
-    logic [DATA_WIDTH-1:0]  mask;
-    for (int i= 0;i < DATA_WIDTH;i += 8) begin
-      mask[i+:8]  = {8{strobe[i/8]}};
-    end
-    return mask;
-  endfunction
-endmodule

data/rtl/rggen_register_if.sv

@@ -1,42 +0,0 @@
-interface rggen_register_if #(
-  parameter int ADDRESS_WIDTH = 16,
-  parameter int DATA_WIDTH    = 32
-)();
-  import  rggen_rtl_pkg::*;
-
-  logic                     request;
-  logic                     select;
-  logic [ADDRESS_WIDTH-1:0] address;
-  rggen_direction           direction;
-  logic [DATA_WIDTH-1:0]    write_data;
-  logic [DATA_WIDTH/8-1:0]  write_strobe;
-  logic                     ready;
-  logic [DATA_WIDTH-1:0]    read_data;
-  logic [DATA_WIDTH-1:0]    value;
-  rggen_status              status;
-
-  modport master (
-    output  request,
-    input   select,
-    output  address,
-    output  direction,
-    output  write_data,
-    output  write_strobe,
-    input   ready,
-    input   read_data,
-    input   status
-  );
-
-  modport slave (
-    input   request,
-    output  select,
-    input   address,
-    input   direction,
-    input   write_data,
-    input   write_strobe,
-    output  ready,
-    output  read_data,
-    output  status,
-    output  value
-  );
-endinterface

data/rtl/rggen_rtl_pkg.sv

@@ -1,23 +0,0 @@
-package rggen_rtl_pkg;
-  typedef enum logic {
-    RGGEN_READ  = 1'b0,
-    RGGEN_WRITE = 1'b1
-  } rggen_direction;
-
-  typedef enum logic [1:0] {
-    RGGEN_OKAY          = 2'b00,
-    RGGEN_EXOKAY        = 2'b01,
-    RGGEN_SLAVE_ERROR   = 2'b10,
-    RGGEN_DECODE_ERROR  = 2'b11
-  } rggen_status;
-
-  typedef enum bit {
-    RGGEN_SET_MODE    = 1'b0,
-    RGGEN_CLEAR_MODE  = 1'b1
-  } rggen_rwsc_mode;
-
-  typedef enum bit {
-    RGGEN_LOCK_MODE   = 1'b0,
-    RGGEN_ENABLE_MODE = 1'b1
-  } rggen_rwle_mode;
-endpackage

data/sample/LICENSE

@@ -1,21 +0,0 @@
-MIT License
-
-Copyright (c) 2017 Taichi Ishitani
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.

data/sample/sample.csv

@@ -1,21 +0,0 @@
-,block name,block_0,,,,,,,
-,byte size,256,,,,,,,
-,,,,,,,,,
-,offset address,registe name,array dimension,type,assignment,field name,type,initial value,reference
-,0x00,register_0,,,[31:16],bit_field_0_0,rw,0,
-,,,,,[15:0],bit_field_0_1,rw,0,
-,0x04,register_1,,,[31:0],bit_field_1_0,rw,0,
-,0x08,register_2,,,[16],bit_field_2_0,ro,,
-,,,,,[0],bit_field_2_1,rw,0,
-,0x0C,register_3,,,[31:0],bit_field_3_0,ro,,
-,0x10 - 0x1F,register_4,[4],,[31:16],bit_field_4_0,ro,,
-,,,,,[15:0],bit_field_4_1,rw,0,
-,0x20,register_5,"[2,4]","indirect: bit_field_2_1:1, bit_field_0_0, bit_field_0_1",[31:16],bit_field_5_0,ro,,
-,,,,,[15:0],bit_field_5_1,rw,0,
-,0x24,register_6,,,[8],bit_field_6_0,w0c,0,bit_field_2_1
-,,,,,[0],bit_field_6_1,w1c,0,bit_field_2_1
-,0x28,register_7,,,[8],bit_field_7_0,w0s,0,
-,,,,,[0],bit_field_7_1,w1s,0,
-,0x2C,register_8,,,[31:16],bit_field_8_0,rwl,0,bit_field_2_1
-,,,,,[15:0],bit_field_8_1,rwe,0,bit_field_2_1
-,0x80-0xFF,register_9,,external,,,,,

data/sample/sample.json

@@ -1,6 +0,0 @@
-{
-  "address_width": 16,
-  "host_if": "apb",
-  "array_port_format": "unpacked",
-  "unfold_sv_interface_port": "no"
-}

data/sample/sample.yaml

@@ -1,4 +0,0 @@
-address_width: 16
-host_if: apb
-array_port_format: unpacked
-unfold_sv_interface_port: no

data/sample/sample_0.h

@@ -1,17 +0,0 @@
-#ifndef SAMPLE_0_H
-#define SAMPLE_0_H
-#include "rggen.h"
-typedef struct {
-  rggen_uint32 register_0;
-  rggen_uint32 register_1;
-  rggen_uint32 register_2;
-  rggen_uint32 register_3;
-  rggen_uint32 register_4[4];
-  rggen_uint32 register_5;
-  rggen_uint32 register_6;
-  rggen_uint32 register_7;
-  rggen_uint32 register_8;
-  rggen_uint32 __dummy_0[20];
-  RGGEN_EXTERNAL_REGISTERS(128, REGISTER_9) register_9;
-} s_sample_0_address_struct;
-#endif

data/sample/sample_0.sv

@@ -1,402 +0,0 @@
-module sample_0 (
-  input logic clk,
-  input logic rst_n,
-  rggen_apb_if.slave apb_if,
-  output logic [15:0] o_bit_field_0_0,
-  output logic [15:0] o_bit_field_0_1,
-  output logic [31:0] o_bit_field_1_0,
-  input logic i_bit_field_2_0,
-  output logic o_bit_field_2_1,
-  input logic [31:0] i_bit_field_3_0,
-  input logic [15:0] i_bit_field_4_0[4],
-  output logic [15:0] o_bit_field_4_1[4],
-  input logic [15:0] i_bit_field_5_0[2][4],
-  output logic [15:0] o_bit_field_5_1[2][4],
-  input logic i_bit_field_6_0_set,
-  output logic o_bit_field_6_0,
-  input logic i_bit_field_6_1_set,
-  output logic o_bit_field_6_1,
-  output logic o_bit_field_7_0,
-  input logic i_bit_field_7_0_clear,
-  output logic o_bit_field_7_1,
-  input logic i_bit_field_7_1_clear,
-  output logic [15:0] o_bit_field_8_0,
-  output logic [15:0] o_bit_field_8_1,
-  rggen_bus_if.master register_9_bus_if
-);
-  rggen_register_if #(8, 32) register_if[20]();
-  `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
-  assign  FIF.read_access         = RIF.read_access; \
-  assign  FIF.write_access        = RIF.write_access; \
-  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
-  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
-  assign  RIF.value[MSB:LSB]      = FIF.value; \
-  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
-  rggen_host_if_apb #(
-    .LOCAL_ADDRESS_WIDTH  (8),
-    .DATA_WIDTH           (32),
-    .TOTAL_REGISTERS      (20)
-  ) u_host_if (
-    .clk          (clk),
-    .rst_n        (rst_n),
-    .apb_if       (apb_if),
-    .register_if  (register_if)
-  );
-  generate if (1) begin : g_register_0
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h00),
-      .END_ADDRESS    (8'h03),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[0]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_0_0
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
-      rggen_bit_field_rw #(
-        .WIDTH          (16),
-        .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_0_0)
-      );
-    end
-    if (1) begin : g_bit_field_0_1
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
-      rggen_bit_field_rw #(
-        .WIDTH          (16),
-        .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_0_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_1
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h04),
-      .END_ADDRESS    (8'h07),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[1]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_1_0
-      rggen_bit_field_if #(32) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
-      rggen_bit_field_rw #(
-        .WIDTH          (32),
-        .INITIAL_VALUE  (32'h00000000)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_1_0)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_2
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h08),
-      .END_ADDRESS    (8'h0b),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00010001)
-    ) u_register (
-      .register_if  (register_if[2]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_2_0
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 16)
-      rggen_bit_field_ro #(
-        .WIDTH  (1)
-      ) u_bit_field (
-        .bit_field_if (bit_field_sub_if),
-        .i_value      (i_bit_field_2_0)
-      );
-    end
-    if (1) begin : g_bit_field_2_1
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
-      rggen_bit_field_rw #(
-        .WIDTH          (1),
-        .INITIAL_VALUE  (1'h0)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_2_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_3
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h0c),
-      .END_ADDRESS    (8'h0f),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[3]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_3_0
-      rggen_bit_field_if #(32) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
-      rggen_bit_field_ro #(
-        .WIDTH  (32)
-      ) u_bit_field (
-        .bit_field_if (bit_field_sub_if),
-        .i_value      (i_bit_field_3_0)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_4
-    genvar g_i;
-    for (g_i = 0;g_i < 4;++g_i) begin : g
-      rggen_bit_field_if #(32) bit_field_if();
-      rggen_default_register #(
-        .ADDRESS_WIDTH  (8),
-        .START_ADDRESS  (8'h10 + 8'h04 * g_i),
-        .END_ADDRESS    (8'h13 + 8'h04 * g_i),
-        .DATA_WIDTH     (32),
-        .VALID_BITS     (32'hffffffff)
-      ) u_register (
-        .register_if  (register_if[4+g_i]),
-        .bit_field_if (bit_field_if)
-      );
-      if (1) begin : g_bit_field_4_0
-        rggen_bit_field_if #(16) bit_field_sub_if();
-        `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
-        rggen_bit_field_ro #(
-          .WIDTH  (16)
-        ) u_bit_field (
-          .bit_field_if (bit_field_sub_if),
-          .i_value      (i_bit_field_4_0[g_i])
-        );
-      end
-      if (1) begin : g_bit_field_4_1
-        rggen_bit_field_if #(16) bit_field_sub_if();
-        `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
-        rggen_bit_field_rw #(
-          .WIDTH          (16),
-          .INITIAL_VALUE  (16'h0000)
-        ) u_bit_field (
-          .clk          (clk),
-          .rst_n        (rst_n),
-          .bit_field_if (bit_field_sub_if),
-          .o_value      (o_bit_field_4_1[g_i])
-        );
-      end
-    end
-  end endgenerate
-  generate if (1) begin : g_register_5
-    genvar g_i;
-    for (g_i = 0;g_i < 2;++g_i) begin : g
-      genvar g_j;
-      for (g_j = 0;g_j < 4;++g_j) begin : g
-        rggen_bit_field_if #(32) bit_field_if();
-        logic [32:0] indirect_index;
-        assign indirect_index = {register_if[2].value[0], register_if[0].value[31:16], register_if[0].value[15:0]};
-        rggen_indirect_register #(
-          .ADDRESS_WIDTH  (8),
-          .START_ADDRESS  (8'h20),
-          .END_ADDRESS    (8'h23),
-          .INDEX_WIDTH    (33),
-          .INDEX_VALUE    ({1'h1, g_i[15:0], g_j[15:0]}),
-          .DATA_WIDTH     (32),
-          .VALID_BITS     (32'hffffffff)
-        ) u_register (
-          .register_if  (register_if[8+4*g_i+g_j]),
-          .bit_field_if (bit_field_if),
-          .i_index      (indirect_index)
-        );
-        if (1) begin : g_bit_field_5_0
-          rggen_bit_field_if #(16) bit_field_sub_if();
-          `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
-          rggen_bit_field_ro #(
-            .WIDTH  (16)
-          ) u_bit_field (
-            .bit_field_if (bit_field_sub_if),
-            .i_value      (i_bit_field_5_0[g_i][g_j])
-          );
-        end
-        if (1) begin : g_bit_field_5_1
-          rggen_bit_field_if #(16) bit_field_sub_if();
-          `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
-          rggen_bit_field_rw #(
-            .WIDTH          (16),
-            .INITIAL_VALUE  (16'h0000)
-          ) u_bit_field (
-            .clk          (clk),
-            .rst_n        (rst_n),
-            .bit_field_if (bit_field_sub_if),
-            .o_value      (o_bit_field_5_1[g_i][g_j])
-          );
-        end
-      end
-    end
-  end endgenerate
-  generate if (1) begin : g_register_6
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h24),
-      .END_ADDRESS    (8'h27),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00000101)
-    ) u_register (
-      .register_if  (register_if[16]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_6_0
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 8)
-      rggen_bit_field_w01s_w01c #(
-        .MODE             (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
-        .SET_CLEAR_VALUE  (0),
-        .WIDTH            (1),
-        .INITIAL_VALUE    (1'h0)
-      ) u_bit_field (
-        .clk            (clk),
-        .rst_n          (rst_n),
-        .i_set_or_clear (i_bit_field_6_0_set),
-        .bit_field_if   (bit_field_sub_if),
-        .o_value        (o_bit_field_6_0)
-      );
-    end
-    if (1) begin : g_bit_field_6_1
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
-      rggen_bit_field_w01s_w01c #(
-        .MODE             (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
-        .SET_CLEAR_VALUE  (1),
-        .WIDTH            (1),
-        .INITIAL_VALUE    (1'h0)
-      ) u_bit_field (
-        .clk            (clk),
-        .rst_n          (rst_n),
-        .i_set_or_clear (i_bit_field_6_1_set),
-        .bit_field_if   (bit_field_sub_if),
-        .o_value        (o_bit_field_6_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_7
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h28),
-      .END_ADDRESS    (8'h2b),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00000101)
-    ) u_register (
-      .register_if  (register_if[17]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_7_0
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 8)
-      rggen_bit_field_w01s_w01c #(
-        .MODE             (rggen_rtl_pkg::RGGEN_SET_MODE),
-        .SET_CLEAR_VALUE  (0),
-        .WIDTH            (1),
-        .INITIAL_VALUE    (1'h0)
-      ) u_bit_field (
-        .clk            (clk),
-        .rst_n          (rst_n),
-        .i_set_or_clear (i_bit_field_7_0_clear),
-        .bit_field_if   (bit_field_sub_if),
-        .o_value        (o_bit_field_7_0)
-      );
-    end
-    if (1) begin : g_bit_field_7_1
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
-      rggen_bit_field_w01s_w01c #(
-        .MODE             (rggen_rtl_pkg::RGGEN_SET_MODE),
-        .SET_CLEAR_VALUE  (1),
-        .WIDTH            (1),
-        .INITIAL_VALUE    (1'h0)
-      ) u_bit_field (
-        .clk            (clk),
-        .rst_n          (rst_n),
-        .i_set_or_clear (i_bit_field_7_1_clear),
-        .bit_field_if   (bit_field_sub_if),
-        .o_value        (o_bit_field_7_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_8
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h2c),
-      .END_ADDRESS    (8'h2f),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[18]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_8_0
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
-      rggen_bit_field_rwl_rwe #(
-        .MODE           (rggen_rtl_pkg::RGGEN_LOCK_MODE),
-        .WIDTH          (16),
-        .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field (
-        .clk              (clk),
-        .rst_n            (rst_n),
-        .i_lock_or_enable (register_if[2].value[0]),
-        .bit_field_if     (bit_field_sub_if),
-        .o_value          (o_bit_field_8_0)
-      );
-    end
-    if (1) begin : g_bit_field_8_1
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
-      rggen_bit_field_rwl_rwe #(
-        .MODE           (rggen_rtl_pkg::RGGEN_ENABLE_MODE),
-        .WIDTH          (16),
-        .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field (
-        .clk              (clk),
-        .rst_n            (rst_n),
-        .i_lock_or_enable (register_if[2].value[0]),
-        .bit_field_if     (bit_field_sub_if),
-        .o_value          (o_bit_field_8_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_9
-    rggen_external_register #(
-      .ADDRESS_WIDTH  (8),
-      .START_ADDRESS  (8'h80),
-      .END_ADDRESS    (8'hff),
-      .DATA_WIDTH     (32)
-    ) u_register (
-      .clk          (clk),
-      .rst_n        (rst_n),
-      .register_if  (register_if[19]),
-      .bus_if       (register_9_bus_if)
-    );
-  end endgenerate
-  `undef rggen_connect_bit_field_if
-endmodule