rggen 0.8.2 → 0.9.0
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- checksums.yaml +4 -4
- data/CODE_OF_CONDUCT.md +54 -29
- data/{LICENSE.txt → LICENSE} +1 -1
- data/README.md +65 -56
- data/lib/rggen.rb +4 -63
- data/lib/rggen/built_in.rb +53 -0
- data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
- data/lib/rggen/built_in/bit_field/comment.rb +16 -0
- data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
- data/lib/rggen/built_in/bit_field/name.rb +39 -0
- data/lib/rggen/built_in/bit_field/reference.rb +100 -0
- data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
- data/lib/rggen/built_in/bit_field/type.rb +279 -0
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
- data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
- data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
- data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
- data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
- data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
- data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
- data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
- data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
- data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
- data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
- data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
- data/lib/rggen/built_in/global/address_width.rb +32 -0
- data/lib/rggen/built_in/global/array_port_format.rb +19 -0
- data/lib/rggen/built_in/global/bus_width.rb +33 -0
- data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
- data/lib/rggen/built_in/register/name.rb +34 -0
- data/lib/rggen/built_in/register/offset_address.rb +96 -0
- data/lib/rggen/built_in/register/size.rb +49 -0
- data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
- data/lib/rggen/built_in/register/type.rb +374 -0
- data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
- data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
- data/lib/rggen/built_in/register/type/external.erb +11 -0
- data/lib/rggen/built_in/register/type/external.rb +141 -0
- data/lib/rggen/built_in/register/type/indirect.rb +329 -0
- data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
- data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
- data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
- data/lib/rggen/built_in/register_block/name.rb +36 -0
- data/lib/rggen/built_in/register_block/protocol.rb +71 -0
- data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
- data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
- data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
- data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
- data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
- data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
- data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
- data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
- data/lib/rggen/built_in/version.rb +7 -0
- data/lib/rggen/default_setup_file.rb +6 -0
- data/lib/rggen/setup/default.rb +26 -0
- data/lib/rggen/version.rb +5 -4
- data/sample/block_0.rb +85 -0
- data/sample/block_0.sv +601 -0
- data/sample/block_0.xlsx +0 -0
- data/sample/block_0.yml +94 -0
- data/sample/block_0_ral_pkg.sv +174 -0
- data/sample/block_1.rb +22 -0
- data/sample/block_1.sv +136 -0
- data/sample/block_1.xlsx +0 -0
- data/sample/block_1.yml +26 -0
- data/sample/block_1_ral_pkg.sv +68 -0
- data/sample/config.json +5 -0
- data/sample/config.yml +3 -0
- metadata +96 -270
- data/bin/rggen +0 -6
- data/c_header/LICENSE +0 -21
- data/c_header/rggen.h +0 -17
- data/lib/rggen/base/component.rb +0 -31
- data/lib/rggen/base/component_factory.rb +0 -53
- data/lib/rggen/base/hierarchical_accessors.rb +0 -87
- data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
- data/lib/rggen/base/internal_struct.rb +0 -28
- data/lib/rggen/base/item.rb +0 -35
- data/lib/rggen/base/item_factory.rb +0 -25
- data/lib/rggen/builder/builder.rb +0 -69
- data/lib/rggen/builder/category.rb +0 -63
- data/lib/rggen/builder/component_entry.rb +0 -50
- data/lib/rggen/builder/component_store.rb +0 -42
- data/lib/rggen/builder/input_component_store.rb +0 -25
- data/lib/rggen/builder/item_store.rb +0 -89
- data/lib/rggen/builder/list_item_entry.rb +0 -81
- data/lib/rggen/builder/output_component_store.rb +0 -13
- data/lib/rggen/builder/simple_item_entry.rb +0 -33
- data/lib/rggen/builtins.rb +0 -55
- data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
- data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
- data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
- data/lib/rggen/builtins/bit_field/name.rb +0 -26
- data/lib/rggen/builtins/bit_field/reference.rb +0 -40
- data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
- data/lib/rggen/builtins/bit_field/type.rb +0 -244
- data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
- data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
- data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
- data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
- data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
- data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
- data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
- data/lib/rggen/builtins/global/address_width.rb +0 -17
- data/lib/rggen/builtins/global/array_port_format.rb +0 -15
- data/lib/rggen/builtins/global/data_width.rb +0 -20
- data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
- data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
- data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
- data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
- data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
- data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
- data/lib/rggen/builtins/register/array.rb +0 -30
- data/lib/rggen/builtins/register/constructor.rb +0 -17
- data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
- data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
- data/lib/rggen/builtins/register/name.rb +0 -26
- data/lib/rggen/builtins/register/offset_address.rb +0 -61
- data/lib/rggen/builtins/register/reg_model.rb +0 -107
- data/lib/rggen/builtins/register/rtl_top.rb +0 -68
- data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
- data/lib/rggen/builtins/register/type.rb +0 -283
- data/lib/rggen/builtins/register/types/default.erb +0 -10
- data/lib/rggen/builtins/register/types/external.erb +0 -11
- data/lib/rggen/builtins/register/types/external.rb +0 -77
- data/lib/rggen/builtins/register/types/indirect.erb +0 -13
- data/lib/rggen/builtins/register/types/indirect.rb +0 -175
- data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
- data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
- data/lib/rggen/builtins/register_block/base_address.rb +0 -64
- data/lib/rggen/builtins/register_block/block_model.rb +0 -20
- data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
- data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
- data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
- data/lib/rggen/builtins/register_block/constructor.rb +0 -14
- data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
- data/lib/rggen/builtins/register_block/host_if.rb +0 -64
- data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
- data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
- data/lib/rggen/builtins/register_block/name.rb +0 -26
- data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
- data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
- data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
- data/lib/rggen/commands.rb +0 -23
- data/lib/rggen/core_components.rb +0 -54
- data/lib/rggen/core_components/c_header/item.rb +0 -8
- data/lib/rggen/core_components/c_header/setup.rb +0 -19
- data/lib/rggen/core_components/c_utility.rb +0 -19
- data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
- data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
- data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
- data/lib/rggen/core_components/code_utility.rb +0 -56
- data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
- data/lib/rggen/core_components/code_utility/line.rb +0 -28
- data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
- data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
- data/lib/rggen/core_components/configuration/item.rb +0 -11
- data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
- data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
- data/lib/rggen/core_components/configuration/setup.rb +0 -14
- data/lib/rggen/core_components/erb_engine.rb +0 -15
- data/lib/rggen/core_components/ral/component.rb +0 -24
- data/lib/rggen/core_components/ral/item.rb +0 -59
- data/lib/rggen/core_components/ral/setup.rb +0 -19
- data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
- data/lib/rggen/core_components/register_map/component.rb +0 -15
- data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
- data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
- data/lib/rggen/core_components/register_map/item.rb +0 -26
- data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
- data/lib/rggen/core_components/register_map/loader.rb +0 -11
- data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
- data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
- data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
- data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
- data/lib/rggen/core_components/register_map/setup.rb +0 -33
- data/lib/rggen/core_components/rtl/component.rb +0 -24
- data/lib/rggen/core_components/rtl/item.rb +0 -82
- data/lib/rggen/core_components/rtl/setup.rb +0 -19
- data/lib/rggen/core_components/verilog_utility.rb +0 -88
- data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
- data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
- data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
- data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
- data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
- data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
- data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
- data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
- data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
- data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
- data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
- data/lib/rggen/core_extensions/array.rb +0 -9
- data/lib/rggen/core_extensions/facets.rb +0 -22
- data/lib/rggen/core_extensions/forwardable.rb +0 -49
- data/lib/rggen/core_extensions/integer.rb +0 -5
- data/lib/rggen/core_extensions/math.rb +0 -7
- data/lib/rggen/core_extensions/roo.rb +0 -17
- data/lib/rggen/exceptions.rb +0 -28
- data/lib/rggen/generator.rb +0 -67
- data/lib/rggen/input_base/component.rb +0 -28
- data/lib/rggen/input_base/component_factory.rb +0 -58
- data/lib/rggen/input_base/item.rb +0 -171
- data/lib/rggen/input_base/item_factory.rb +0 -13
- data/lib/rggen/input_base/loader.rb +0 -23
- data/lib/rggen/input_base/regexp_patterns.rb +0 -29
- data/lib/rggen/option_switches.rb +0 -60
- data/lib/rggen/options.rb +0 -97
- data/lib/rggen/output_base/code_generator.rb +0 -36
- data/lib/rggen/output_base/component.rb +0 -78
- data/lib/rggen/output_base/component_factory.rb +0 -32
- data/lib/rggen/output_base/file_writer.rb +0 -36
- data/lib/rggen/output_base/item.rb +0 -110
- data/lib/rggen/output_base/item_factory.rb +0 -9
- data/lib/rggen/output_base/template_engine.rb +0 -24
- data/lib/rggen/rggen_home.rb +0 -3
- data/ral/LICENSE +0 -21
- data/ral/compile.f +0 -2
- data/ral/rggen_ral_block.svh +0 -83
- data/ral/rggen_ral_field.svh +0 -47
- data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
- data/ral/rggen_ral_indirect_reg.svh +0 -193
- data/ral/rggen_ral_macros.svh +0 -27
- data/ral/rggen_ral_map.svh +0 -124
- data/ral/rggen_ral_pkg.sv +0 -15
- data/ral/rggen_ral_reg.svh +0 -88
- data/rtl/LICENSE +0 -21
- data/rtl/compile.f +0 -18
- data/rtl/rggen_address_decoder.sv +0 -23
- data/rtl/rggen_apb_if.sv +0 -41
- data/rtl/rggen_axi4lite_if.sv +0 -68
- data/rtl/rggen_bit_field_if.sv +0 -28
- data/rtl/rggen_bit_field_ro.sv +0 -9
- data/rtl/rggen_bit_field_rw.sv +0 -25
- data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
- data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
- data/rtl/rggen_bus_if.sv +0 -43
- data/rtl/rggen_bus_splitter.sv +0 -86
- data/rtl/rggen_default_register.sv +0 -15
- data/rtl/rggen_external_register.sv +0 -83
- data/rtl/rggen_host_if_apb.sv +0 -29
- data/rtl/rggen_host_if_axi4lite.sv +0 -161
- data/rtl/rggen_indirect_register.sv +0 -21
- data/rtl/rggen_register_base.sv +0 -57
- data/rtl/rggen_register_if.sv +0 -42
- data/rtl/rggen_rtl_pkg.sv +0 -23
- data/sample/LICENSE +0 -21
- data/sample/sample.csv +0 -21
- data/sample/sample.json +0 -6
- data/sample/sample.xls +0 -0
- data/sample/sample.xlsx +0 -0
- data/sample/sample.yaml +0 -4
- data/sample/sample_0.h +0 -17
- data/sample/sample_0.sv +0 -402
- data/sample/sample_0_ral_pkg.sv +0 -145
- data/sample/sample_1.h +0 -9
- data/sample/sample_1.sv +0 -128
- data/sample/sample_1_ral_pkg.sv +0 -56
- data/sample/sample_setup.rb +0 -24
- data/setup/default.rb +0 -14
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# frozen_string_literal: true
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RgGen.define_simple_feature(:register, :name) do
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register_map do
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property :name
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input_pattern variable_name
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build do |value|
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@name =
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if pattern_matched?
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match_data.to_s
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else
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error "illegal input value for register name: #{value.inspect}"
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end
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end
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verify(:feature) do
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error_condition { !name }
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message { 'no register name is given' }
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end
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verify(:feature) do
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error_condition { duplicated_name? }
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message { "duplicated register name: #{name}" }
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end
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private
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def duplicated_name?
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register_block.registers.any? { |register| register.name == name }
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end
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end
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end
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# frozen_string_literal: true
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RgGen.define_simple_feature(:register, :offset_address) do
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register_map do
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property :offset_address
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property :address_range, body: -> { start_address..end_address }
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property :overlap?, forward_to: :overlap_address_range?
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build do |value|
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@offset_address =
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begin
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Integer(value)
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rescue ArgumentError, TypeError
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error "cannot convert #{value.inspect} into offset address"
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end
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end
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verify(:feature) do
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error_condition { !offset_address }
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message { 'no offset address is given' }
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end
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verify(:feature) do
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error_condition { offset_address.negative? }
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message { "offset address is less than 0: #{offset_address}" }
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end
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verify(:feature) do
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error_condition { (offset_address % byte_width).positive? }
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message do
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"offset address is not aligned with bus width(#{bus_width}): "\
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"0x#{offset_address.to_s(16)}"
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end
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end
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verify(:component) do
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error_condition { end_address > register_block.byte_size }
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message do
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'offset address range exceeds byte size of register block' \
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"(#{register_block.byte_size}): " \
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"0x#{start_address.to_s(16)}-0x#{end_address.to_s(16)}"
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|
+
end
|
43
|
+
end
|
44
|
+
|
45
|
+
verify(:component) do
|
46
|
+
error_condition do
|
47
|
+
register_block.registers.any? do |register|
|
48
|
+
overlap_address_range?(register) &&
|
49
|
+
support_unique_range_only?(register)
|
50
|
+
end
|
51
|
+
end
|
52
|
+
message do
|
53
|
+
'offset address range overlaps with other offset address range: ' \
|
54
|
+
"0x#{start_address.to_s(16)}-0x#{end_address.to_s(16)}"
|
55
|
+
end
|
56
|
+
end
|
57
|
+
|
58
|
+
private
|
59
|
+
|
60
|
+
def bus_width
|
61
|
+
configuration.bus_width
|
62
|
+
end
|
63
|
+
|
64
|
+
def byte_width
|
65
|
+
configuration.byte_width
|
66
|
+
end
|
67
|
+
|
68
|
+
def start_address
|
69
|
+
offset_address
|
70
|
+
end
|
71
|
+
|
72
|
+
def end_address
|
73
|
+
start_address + register.byte_size - 1
|
74
|
+
end
|
75
|
+
|
76
|
+
def overlap_address_range?(other_register)
|
77
|
+
overlap_range?(other_register) && match_access?(other_register)
|
78
|
+
end
|
79
|
+
|
80
|
+
def overlap_range?(other_register)
|
81
|
+
own = address_range
|
82
|
+
other = other_register.address_range
|
83
|
+
own.include?(other.first) || other.include?(own.first)
|
84
|
+
end
|
85
|
+
|
86
|
+
def match_access?(other_register)
|
87
|
+
(register.writable? && other_register.writable?) ||
|
88
|
+
(register.readable? && other_register.readable?)
|
89
|
+
end
|
90
|
+
|
91
|
+
def support_unique_range_only?(other_register)
|
92
|
+
!(register.support_overlapped_address? &&
|
93
|
+
register.match_type?(other_register))
|
94
|
+
end
|
95
|
+
end
|
96
|
+
end
|
@@ -0,0 +1,49 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register, :size) do
|
4
|
+
register_map do
|
5
|
+
property :size
|
6
|
+
|
7
|
+
input_pattern [
|
8
|
+
/(#{integer}(:?,#{integer})*)/,
|
9
|
+
/\[(#{integer}(:?,#{integer})*)\]/
|
10
|
+
], match_automatically: false
|
11
|
+
|
12
|
+
build do |values|
|
13
|
+
@size = parse_values(values)
|
14
|
+
end
|
15
|
+
|
16
|
+
verify(:feature) do
|
17
|
+
error_condition { size && !size.all?(&:positive?) }
|
18
|
+
message do
|
19
|
+
"non positive value(s) are not allowed for register size: #{size}"
|
20
|
+
end
|
21
|
+
end
|
22
|
+
|
23
|
+
private
|
24
|
+
|
25
|
+
def parse_values(values)
|
26
|
+
Array(
|
27
|
+
values.is_a?(String) && parse_string_values(values) || values
|
28
|
+
).map(&method(:convert_value))
|
29
|
+
end
|
30
|
+
|
31
|
+
def parse_string_values(values)
|
32
|
+
if match_pattern(values)
|
33
|
+
split_match_data(match_data)
|
34
|
+
else
|
35
|
+
error "illegal input value for register size: #{values.inspect}"
|
36
|
+
end
|
37
|
+
end
|
38
|
+
|
39
|
+
def split_match_data(match_data)
|
40
|
+
match_data.captures.first.split(',')
|
41
|
+
end
|
42
|
+
|
43
|
+
def convert_value(value)
|
44
|
+
Integer(value)
|
45
|
+
rescue ArgumentError, TypeError
|
46
|
+
error "cannot convert #{value.inspect} into register size"
|
47
|
+
end
|
48
|
+
end
|
49
|
+
end
|
@@ -0,0 +1,82 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_simple_feature(:register, :sv_rtl_top) do
|
4
|
+
sv_rtl do
|
5
|
+
export :index
|
6
|
+
export :local_index
|
7
|
+
export :loop_variables
|
8
|
+
|
9
|
+
pre_build do
|
10
|
+
@base_index =
|
11
|
+
register_block.registers.map(&:count).inject(0, :+)
|
12
|
+
end
|
13
|
+
|
14
|
+
build do
|
15
|
+
if register.bit_fields?
|
16
|
+
interface :register, :bit_field_if, {
|
17
|
+
name: 'bit_field_if',
|
18
|
+
interface_type: 'rggen_bit_field_if',
|
19
|
+
parameter_values: [register.width]
|
20
|
+
}
|
21
|
+
end
|
22
|
+
end
|
23
|
+
|
24
|
+
main_code :register_block do
|
25
|
+
local_scope("g_#{register.name}") do |scope|
|
26
|
+
scope.top_scope
|
27
|
+
scope.loop_size loop_size
|
28
|
+
scope.variables variables
|
29
|
+
scope.body(&method(:body_code))
|
30
|
+
end
|
31
|
+
end
|
32
|
+
|
33
|
+
def index(offset = nil)
|
34
|
+
operands =
|
35
|
+
register.array? ? [@base_index, offset || local_index] : [@base_index]
|
36
|
+
if operands.all? { |operand| operand.is_a?(Integer) }
|
37
|
+
operands.inject(:+)
|
38
|
+
else
|
39
|
+
operands.join('+')
|
40
|
+
end
|
41
|
+
end
|
42
|
+
|
43
|
+
def local_index
|
44
|
+
(register.array? || nil) &&
|
45
|
+
loop_variables
|
46
|
+
.zip(local_index_coefficients)
|
47
|
+
.map { |v, c| [c, v].compact.join('*') }
|
48
|
+
.join('+')
|
49
|
+
end
|
50
|
+
|
51
|
+
def loop_variables
|
52
|
+
(register.array? || nil) &&
|
53
|
+
register.array_size.map.with_index(1) do |_size, i|
|
54
|
+
create_identifier(loop_index(i))
|
55
|
+
end
|
56
|
+
end
|
57
|
+
|
58
|
+
private
|
59
|
+
|
60
|
+
def local_index_coefficients
|
61
|
+
coefficients = []
|
62
|
+
register.array_size.reverse.inject(1) do |total, size|
|
63
|
+
coefficients.unshift(coefficients.size.zero? ? nil : total)
|
64
|
+
total * size
|
65
|
+
end
|
66
|
+
coefficients
|
67
|
+
end
|
68
|
+
|
69
|
+
def loop_size
|
70
|
+
(register.array? || nil) &&
|
71
|
+
loop_variables.zip(register.array_size).to_h
|
72
|
+
end
|
73
|
+
|
74
|
+
def variables
|
75
|
+
register.declarations(:register, :variable)
|
76
|
+
end
|
77
|
+
|
78
|
+
def body_code(code)
|
79
|
+
register.generate_code(:register, :top_down, code)
|
80
|
+
end
|
81
|
+
end
|
82
|
+
end
|
@@ -0,0 +1,374 @@
|
|
1
|
+
# frozen_string_literal: true
|
2
|
+
|
3
|
+
RgGen.define_list_feature(:register, :type) do
|
4
|
+
register_map do
|
5
|
+
base_feature do
|
6
|
+
define_helpers do
|
7
|
+
def writable?(&block)
|
8
|
+
@writability = block
|
9
|
+
end
|
10
|
+
|
11
|
+
def readable?(&block)
|
12
|
+
@readability = block
|
13
|
+
end
|
14
|
+
|
15
|
+
attr_reader :writability
|
16
|
+
attr_reader :readability
|
17
|
+
|
18
|
+
def no_bit_fields
|
19
|
+
@no_bit_fields = true
|
20
|
+
end
|
21
|
+
|
22
|
+
def need_bit_fields?
|
23
|
+
!@no_bit_fields
|
24
|
+
end
|
25
|
+
|
26
|
+
def support_array_register
|
27
|
+
@support_array_register = true
|
28
|
+
end
|
29
|
+
|
30
|
+
def support_array_register?
|
31
|
+
@support_array_register || false
|
32
|
+
end
|
33
|
+
|
34
|
+
def byte_size(&block)
|
35
|
+
@byte_size = block if block_given?
|
36
|
+
@byte_size
|
37
|
+
end
|
38
|
+
|
39
|
+
def support_overlapped_address
|
40
|
+
@support_overlapped_address = true
|
41
|
+
end
|
42
|
+
|
43
|
+
def support_overlapped_address?
|
44
|
+
@support_overlapped_address || false
|
45
|
+
end
|
46
|
+
end
|
47
|
+
|
48
|
+
property :type, body: -> { @type || :default }
|
49
|
+
property :writable?, forward_to: :writability
|
50
|
+
property :readable?, forward_to: :readability
|
51
|
+
property :width, body: -> { @width ||= calc_width }
|
52
|
+
property :byte_width, body: -> { @byte_width ||= width / 8 }
|
53
|
+
property :array?, forward_to: :array_register?
|
54
|
+
property :array_size, body: -> { (array? && register.size) || nil }
|
55
|
+
property :count, body: -> { @count ||= calc_count }
|
56
|
+
property :byte_size, body: -> { @byte_size ||= calc_byte_size }
|
57
|
+
property :match_type?, body: ->(register) { register.type == type }
|
58
|
+
property :support_overlapped_address?, forward_to_helper: true
|
59
|
+
|
60
|
+
build do |value|
|
61
|
+
@type = value[:type]
|
62
|
+
@options = value[:options]
|
63
|
+
helper.need_bit_fields? || register.need_no_children
|
64
|
+
end
|
65
|
+
|
66
|
+
verify(:component) do
|
67
|
+
error_condition do
|
68
|
+
helper.need_bit_fields? && register.bit_fields.empty?
|
69
|
+
end
|
70
|
+
message { 'no bit fields are given' }
|
71
|
+
end
|
72
|
+
|
73
|
+
private
|
74
|
+
|
75
|
+
attr_reader :options
|
76
|
+
|
77
|
+
def writability
|
78
|
+
if @writability.nil?
|
79
|
+
block = helper.writability || default_writability
|
80
|
+
@writability = instance_exec(&block)
|
81
|
+
end
|
82
|
+
@writability
|
83
|
+
end
|
84
|
+
|
85
|
+
def default_writability
|
86
|
+
-> { register.bit_fields.any?(&:writable?) }
|
87
|
+
end
|
88
|
+
|
89
|
+
def readability
|
90
|
+
if @readability.nil?
|
91
|
+
block = helper.readability || default_readability
|
92
|
+
@readability = instance_exec(&block)
|
93
|
+
end
|
94
|
+
@readability
|
95
|
+
end
|
96
|
+
|
97
|
+
def default_readability
|
98
|
+
lambda do
|
99
|
+
block = ->(bit_field) { bit_field.readable? || bit_field.reserved? }
|
100
|
+
register.bit_fields.any?(&block)
|
101
|
+
end
|
102
|
+
end
|
103
|
+
|
104
|
+
def calc_width
|
105
|
+
bus_width = configuration.bus_width
|
106
|
+
if helper.need_bit_fields?
|
107
|
+
((collect_msb.max + bus_width) / bus_width) * bus_width
|
108
|
+
else
|
109
|
+
bus_width
|
110
|
+
end
|
111
|
+
end
|
112
|
+
|
113
|
+
def collect_msb
|
114
|
+
register.bit_fields.collect do |bit_field|
|
115
|
+
bit_field.msb((bit_field.sequence_size || 1) - 1)
|
116
|
+
end
|
117
|
+
end
|
118
|
+
|
119
|
+
def array_register?
|
120
|
+
helper.support_array_register? && !register.size.nil?
|
121
|
+
end
|
122
|
+
|
123
|
+
def calc_count
|
124
|
+
Array(array_size).reduce(1, :*)
|
125
|
+
end
|
126
|
+
|
127
|
+
def calc_byte_size
|
128
|
+
if helper.byte_size
|
129
|
+
instance_exec(&helper.byte_size)
|
130
|
+
else
|
131
|
+
Array(register.size).reduce(1, :*) * byte_width
|
132
|
+
end
|
133
|
+
end
|
134
|
+
end
|
135
|
+
|
136
|
+
default_feature do
|
137
|
+
support_array_register
|
138
|
+
|
139
|
+
verify(:feature) do
|
140
|
+
error_condition { @type }
|
141
|
+
message { "unknown register type: #{@type.inspect}" }
|
142
|
+
end
|
143
|
+
end
|
144
|
+
|
145
|
+
factory do
|
146
|
+
convert_value do |value|
|
147
|
+
type, options = split_input_value(value)
|
148
|
+
{ type: find_type(type), options: Array(options) }
|
149
|
+
end
|
150
|
+
|
151
|
+
def select_feature(cell)
|
152
|
+
if cell.empty_value?
|
153
|
+
target_feature
|
154
|
+
else
|
155
|
+
target_features[cell.value[:type]]
|
156
|
+
end
|
157
|
+
end
|
158
|
+
|
159
|
+
private
|
160
|
+
|
161
|
+
def split_input_value(value)
|
162
|
+
if value.is_a?(String)
|
163
|
+
split_string_value(value)
|
164
|
+
else
|
165
|
+
input_value = Array(value)
|
166
|
+
[input_value[0], input_value[1..-1]]
|
167
|
+
end
|
168
|
+
end
|
169
|
+
|
170
|
+
def split_string_value(value)
|
171
|
+
type, options = split_string(value, ':', 2)
|
172
|
+
[type, split_string(options, /[,\n]/, 0)]
|
173
|
+
end
|
174
|
+
|
175
|
+
def split_string(value, separator, limit)
|
176
|
+
value&.split(separator, limit)&.map(&:strip)
|
177
|
+
end
|
178
|
+
|
179
|
+
def find_type(type)
|
180
|
+
types = target_features.keys
|
181
|
+
types.find(&type.to_sym.method(:casecmp?)) || type
|
182
|
+
end
|
183
|
+
end
|
184
|
+
end
|
185
|
+
|
186
|
+
sv_rtl do
|
187
|
+
base_feature do
|
188
|
+
private
|
189
|
+
|
190
|
+
def readable
|
191
|
+
register.readable? && 1 || 0
|
192
|
+
end
|
193
|
+
|
194
|
+
def writable
|
195
|
+
register.writable? && 1 || 0
|
196
|
+
end
|
197
|
+
|
198
|
+
def address_width
|
199
|
+
register_block.local_address_width
|
200
|
+
end
|
201
|
+
|
202
|
+
def offset_address
|
203
|
+
hex(register.offset_address, address_width)
|
204
|
+
end
|
205
|
+
|
206
|
+
def valid_bits
|
207
|
+
bits = register.bit_fields.map(&:bit_map).inject(:|)
|
208
|
+
hex(bits, register.width)
|
209
|
+
end
|
210
|
+
|
211
|
+
def register_index
|
212
|
+
register.local_index || 0
|
213
|
+
end
|
214
|
+
|
215
|
+
def register_if
|
216
|
+
register_block.register_if[register.index]
|
217
|
+
end
|
218
|
+
end
|
219
|
+
|
220
|
+
default_feature do
|
221
|
+
template_path = File.join(__dir__, 'type', 'default_sv_rtl.erb')
|
222
|
+
main_code :register, from_template: template_path
|
223
|
+
end
|
224
|
+
|
225
|
+
factory do
|
226
|
+
def select_feature(_configuration, register)
|
227
|
+
target_features[register.type]
|
228
|
+
end
|
229
|
+
end
|
230
|
+
end
|
231
|
+
|
232
|
+
sv_ral do
|
233
|
+
base_feature do
|
234
|
+
define_helpers do
|
235
|
+
def model_name(&body)
|
236
|
+
@model_name = body if block_given?
|
237
|
+
@model_name
|
238
|
+
end
|
239
|
+
|
240
|
+
def offset_address(&body)
|
241
|
+
@offset_address = body if block_given?
|
242
|
+
@offset_address
|
243
|
+
end
|
244
|
+
|
245
|
+
def unmapped
|
246
|
+
@unmapped = true
|
247
|
+
end
|
248
|
+
|
249
|
+
def unmapped?
|
250
|
+
!@unmapped.nil?
|
251
|
+
end
|
252
|
+
|
253
|
+
def constructor(&body)
|
254
|
+
@constructor = body if block_given?
|
255
|
+
@constructor
|
256
|
+
end
|
257
|
+
end
|
258
|
+
|
259
|
+
export :constructors
|
260
|
+
|
261
|
+
build do
|
262
|
+
variable :register_block, :ral_model, {
|
263
|
+
name: register.name,
|
264
|
+
data_type: model_name,
|
265
|
+
array_size: register.array_size,
|
266
|
+
random: true
|
267
|
+
}
|
268
|
+
end
|
269
|
+
|
270
|
+
def constructors
|
271
|
+
(array_index_list || [nil]).map.with_index do |array_index, i|
|
272
|
+
constructor_code(array_index, i)
|
273
|
+
end
|
274
|
+
end
|
275
|
+
|
276
|
+
private
|
277
|
+
|
278
|
+
def model_name
|
279
|
+
if helper.model_name
|
280
|
+
instance_eval(&helper.model_name)
|
281
|
+
else
|
282
|
+
"#{register.name}_reg_model"
|
283
|
+
end
|
284
|
+
end
|
285
|
+
|
286
|
+
def array_index_list
|
287
|
+
(register.array? || nil) &&
|
288
|
+
begin
|
289
|
+
index_table = register.array_size.map { |size| (0...size).to_a }
|
290
|
+
index_table[0].product(*index_table[1..-1])
|
291
|
+
end
|
292
|
+
end
|
293
|
+
|
294
|
+
def constructor_code(array_index, index)
|
295
|
+
if helper.constructor
|
296
|
+
instance_exec(array_index, index, &helper.constructor)
|
297
|
+
else
|
298
|
+
macro_call(
|
299
|
+
:rggen_ral_create_reg_model, arguments(array_index, index)
|
300
|
+
)
|
301
|
+
end
|
302
|
+
end
|
303
|
+
|
304
|
+
def arguments(array_index, index)
|
305
|
+
[
|
306
|
+
ral_model[array_index], array(array_index), offset_address(index),
|
307
|
+
access_rights, unmapped, hdl_path(array_index)
|
308
|
+
]
|
309
|
+
end
|
310
|
+
|
311
|
+
def offset_address(index = 0)
|
312
|
+
address =
|
313
|
+
if helper.offset_address
|
314
|
+
instance_exec(index, &helper.offset_address)
|
315
|
+
else
|
316
|
+
register.offset_address + register.byte_width * index
|
317
|
+
end
|
318
|
+
hex(address, register_block.local_address_width)
|
319
|
+
end
|
320
|
+
|
321
|
+
def access_rights
|
322
|
+
if register.writable? && register.readable?
|
323
|
+
'RW'
|
324
|
+
elsif register.writable?
|
325
|
+
'WO'
|
326
|
+
else
|
327
|
+
'RO'
|
328
|
+
end
|
329
|
+
end
|
330
|
+
|
331
|
+
def unmapped
|
332
|
+
helper.unmapped? && 1 || 0
|
333
|
+
end
|
334
|
+
|
335
|
+
def hdl_path(array_index)
|
336
|
+
[
|
337
|
+
"g_#{register.name}",
|
338
|
+
*Array(array_index).map { |i| "g[#{i}]" },
|
339
|
+
'u_register'
|
340
|
+
].join('.')
|
341
|
+
end
|
342
|
+
|
343
|
+
def variables
|
344
|
+
register.declarations(:register, :variable)
|
345
|
+
end
|
346
|
+
|
347
|
+
def field_model_constructors
|
348
|
+
register.bit_fields.flat_map(&:constructors)
|
349
|
+
end
|
350
|
+
end
|
351
|
+
|
352
|
+
default_feature do
|
353
|
+
main_code :ral_package do
|
354
|
+
class_definition(model_name) do |sv_class|
|
355
|
+
sv_class.base 'rggen_ral_reg'
|
356
|
+
sv_class.variables variables
|
357
|
+
sv_class.body { model_body }
|
358
|
+
end
|
359
|
+
end
|
360
|
+
|
361
|
+
private
|
362
|
+
|
363
|
+
def model_body
|
364
|
+
process_template(File.join(__dir__, 'type', 'default_sv_ral.erb'))
|
365
|
+
end
|
366
|
+
end
|
367
|
+
|
368
|
+
factory do
|
369
|
+
def select_feature(_configuration, register)
|
370
|
+
target_features[register.type]
|
371
|
+
end
|
372
|
+
end
|
373
|
+
end
|
374
|
+
end
|