rggen 0.8.2 → 0.9.0

data/sample/sample_0_ral_pkg.sv

@@ -1,145 +0,0 @@
-`ifndef SAMPLE_0_RAL_PKG_SV
-`define SAMPLE_0_RAL_PKG_SV
-package sample_0_ral_pkg;
-  import uvm_pkg::*;
-  import rggen_ral_pkg::*;
-  `include "uvm_macros.svh"
-  `include "rggen_ral_macros.svh"
-  class register_0_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_0_0;
-    rand rggen_ral_field bit_field_0_1;
-    function new(string name = "register_0");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "g_bit_field_0_0.u_bit_field.value")
-      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_0_1.u_bit_field.value")
-    endfunction
-  endclass
-  class register_1_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_1_0;
-    function new(string name = "register_1");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "g_bit_field_1_0.u_bit_field.value")
-    endfunction
-  endclass
-  class register_2_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_2_0;
-    rand rggen_ral_field bit_field_2_1;
-    function new(string name = "register_2");
-      super.new(name, 24, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "g_bit_field_2_0.u_bit_field.i_value")
-      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "g_bit_field_2_1.u_bit_field.value")
-    endfunction
-  endclass
-  class register_3_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_3_0;
-    function new(string name = "register_3");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0, "g_bit_field_3_0.u_bit_field.i_value")
-    endfunction
-  endclass
-  class register_4_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_4_0;
-    rand rggen_ral_field bit_field_4_1;
-    function new(string name = "register_4");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0, "g_bit_field_4_0.u_bit_field.i_value")
-      `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_4_1.u_bit_field.value")
-    endfunction
-  endclass
-  class register_5_reg_model extends rggen_ral_indirect_reg;
-    rand rggen_ral_field bit_field_5_0;
-    rand rggen_ral_field bit_field_5_1;
-    function new(string name = "register_5");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "g_bit_field_5_0.u_bit_field.i_value")
-      `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_5_1.u_bit_field.value")
-    endfunction
-    function void configure_indirect_indexes();
-      set_indirect_index("register_2", "bit_field_2_1", 1);
-      set_indirect_index("register_0", "bit_field_0_0", indexes[0]);
-      set_indirect_index("register_0", "bit_field_0_1", indexes[1]);
-    endfunction
-  endclass
-  class register_6_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_6_0;
-    rand rggen_ral_field bit_field_6_1;
-    function new(string name = "register_6");
-      super.new(name, 16, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_6_0, "bit_field_6_0", 1, 8, "W0C", 0, 1'h0, 1, "g_bit_field_6_0.u_bit_field.value")
-      `rggen_ral_create_field_model(bit_field_6_1, "bit_field_6_1", 1, 0, "W1C", 0, 1'h0, 1, "g_bit_field_6_1.u_bit_field.value")
-    endfunction
-  endclass
-  class register_7_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_7_0;
-    rand rggen_ral_field bit_field_7_1;
-    function new(string name = "register_7");
-      super.new(name, 16, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_7_0, "bit_field_7_0", 1, 8, "W0S", 0, 1'h0, 1, "g_bit_field_7_0.u_bit_field.value")
-      `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "g_bit_field_7_1.u_bit_field.value")
-    endfunction
-  endclass
-  class register_8_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field_rwl#("register_2", "bit_field_2_1") bit_field_8_0;
-    rand rggen_ral_field_rwe#("register_2", "bit_field_2_1") bit_field_8_1;
-    function new(string name = "register_8");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "g_bit_field_8_0.u_bit_field.value")
-      `rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "g_bit_field_8_1.u_bit_field.value")
-    endfunction
-  endclass
-  class sample_0_block_model#(
-    type REGISTER_9 = rggen_ral_block
-  ) extends rggen_ral_block;
-    rand register_0_reg_model register_0;
-    rand register_1_reg_model register_1;
-    rand register_2_reg_model register_2;
-    rand register_3_reg_model register_3;
-    rand register_4_reg_model register_4[4];
-    rand register_5_reg_model register_5[2][4];
-    rand register_6_reg_model register_6;
-    rand register_7_reg_model register_7;
-    rand register_8_reg_model register_8;
-    rand REGISTER_9 register_9;
-    function new(string name = "sample_0");
-      super.new(name);
-    endfunction
-    function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0, "g_register_0")
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0, "g_register_1")
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0, "g_register_2")
-      `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0, "g_register_3")
-      foreach (register_4[i]) begin
-        `rggen_ral_create_reg_model(register_4[i], $sformatf("register_4[%0d]", i), '{i}, 8'h10 + 4 * i, "RW", 0, $sformatf("g_register_4.g[%0d]", i))
-      end
-      foreach (register_5[i, j]) begin
-        `rggen_ral_create_reg_model(register_5[i][j], $sformatf("register_5[%0d][%0d]", i, j), '{i, j}, 8'h20, "RW", 1, $sformatf("g_register_5.g[%0d].g[%0d]", i, j))
-      end
-      `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "g_register_6")
-      `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "g_register_7")
-      `rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "g_register_8")
-      `rggen_ral_create_block_model(register_9, "register_9", 8'h80)
-    endfunction
-    function uvm_reg_map create_default_map();
-      return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
-    endfunction
-  endclass
-endpackage
-`endif

data/sample/sample_1.h

@@ -1,9 +0,0 @@
-#ifndef SAMPLE_1_H
-#define SAMPLE_1_H
-#include "rggen.h"
-typedef struct {
-  rggen_uint32 register_0;
-  rggen_uint32 register_1;
-  rggen_uint32 register_2;
-} s_sample_1_address_struct;
-#endif

data/sample/sample_1.sv

@@ -1,128 +0,0 @@
-module sample_1 (
-  input logic clk,
-  input logic rst_n,
-  rggen_apb_if.slave apb_if,
-  output logic [15:0] o_bit_field_0_0,
-  input logic [15:0] i_bit_field_0_1,
-  output logic [31:0] o_bit_field_1_0,
-  input logic i_bit_field_2_0,
-  output logic o_bit_field_2_1
-);
-  rggen_register_if #(7, 32) register_if[3]();
-  `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
-  assign  FIF.read_access         = RIF.read_access; \
-  assign  FIF.write_access        = RIF.write_access; \
-  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
-  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
-  assign  RIF.value[MSB:LSB]      = FIF.value; \
-  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
-  rggen_host_if_apb #(
-    .LOCAL_ADDRESS_WIDTH  (7),
-    .DATA_WIDTH           (32),
-    .TOTAL_REGISTERS      (3)
-  ) u_host_if (
-    .clk          (clk),
-    .rst_n        (rst_n),
-    .apb_if       (apb_if),
-    .register_if  (register_if)
-  );
-  generate if (1) begin : g_register_0
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (7),
-      .START_ADDRESS  (7'h00),
-      .END_ADDRESS    (7'h03),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[0]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_0_0
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
-      rggen_bit_field_rw #(
-        .WIDTH          (16),
-        .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_0_0)
-      );
-    end
-    if (1) begin : g_bit_field_0_1
-      rggen_bit_field_if #(16) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
-      rggen_bit_field_ro #(
-        .WIDTH  (16)
-      ) u_bit_field (
-        .bit_field_if (bit_field_sub_if),
-        .i_value      (i_bit_field_0_1)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_1
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (7),
-      .START_ADDRESS  (7'h04),
-      .END_ADDRESS    (7'h07),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'hffffffff)
-    ) u_register (
-      .register_if  (register_if[1]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_1_0
-      rggen_bit_field_if #(32) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
-      rggen_bit_field_rw #(
-        .WIDTH          (32),
-        .INITIAL_VALUE  (32'h00000000)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_1_0)
-      );
-    end
-  end endgenerate
-  generate if (1) begin : g_register_2
-    rggen_bit_field_if #(32) bit_field_if();
-    rggen_default_register #(
-      .ADDRESS_WIDTH  (7),
-      .START_ADDRESS  (7'h08),
-      .END_ADDRESS    (7'h0b),
-      .DATA_WIDTH     (32),
-      .VALID_BITS     (32'h00010001)
-    ) u_register (
-      .register_if  (register_if[2]),
-      .bit_field_if (bit_field_if)
-    );
-    if (1) begin : g_bit_field_2_0
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 16)
-      rggen_bit_field_ro #(
-        .WIDTH  (1)
-      ) u_bit_field (
-        .bit_field_if (bit_field_sub_if),
-        .i_value      (i_bit_field_2_0)
-      );
-    end
-    if (1) begin : g_bit_field_2_1
-      rggen_bit_field_if #(1) bit_field_sub_if();
-      `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
-      rggen_bit_field_rw #(
-        .WIDTH          (1),
-        .INITIAL_VALUE  (1'h0)
-      ) u_bit_field (
-        .clk          (clk),
-        .rst_n        (rst_n),
-        .bit_field_if (bit_field_sub_if),
-        .o_value      (o_bit_field_2_1)
-      );
-    end
-  end endgenerate
-  `undef rggen_connect_bit_field_if
-endmodule

data/sample/sample_1_ral_pkg.sv

@@ -1,56 +0,0 @@
-`ifndef SAMPLE_1_RAL_PKG_SV
-`define SAMPLE_1_RAL_PKG_SV
-package sample_1_ral_pkg;
-  import uvm_pkg::*;
-  import rggen_ral_pkg::*;
-  `include "uvm_macros.svh"
-  `include "rggen_ral_macros.svh"
-  class register_0_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_0_0;
-    rand rggen_ral_field bit_field_0_1;
-    function new(string name = "register_0");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "g_bit_field_0_0.u_bit_field.value")
-      `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0, "g_bit_field_0_1.u_bit_field.i_value")
-    endfunction
-  endclass
-  class register_1_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_1_0;
-    function new(string name = "register_1");
-      super.new(name, 32, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "g_bit_field_1_0.u_bit_field.value")
-    endfunction
-  endclass
-  class register_2_reg_model extends rggen_ral_reg;
-    rand rggen_ral_field bit_field_2_0;
-    rand rggen_ral_field bit_field_2_1;
-    function new(string name = "register_2");
-      super.new(name, 24, 0);
-    endfunction
-    function void create_fields();
-      `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "g_bit_field_2_0.u_bit_field.i_value")
-      `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "g_bit_field_2_1.u_bit_field.value")
-    endfunction
-  endclass
-  class sample_1_block_model extends rggen_ral_block;
-    rand register_0_reg_model register_0;
-    rand register_1_reg_model register_1;
-    rand register_2_reg_model register_2;
-    function new(string name = "sample_1");
-      super.new(name);
-    endfunction
-    function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0, "g_register_0")
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0, "g_register_1")
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0, "g_register_2")
-    endfunction
-    function uvm_reg_map create_default_map();
-      return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
-    endfunction
-  endclass
-endpackage
-`endif

data/sample/sample_setup.rb

@@ -1,24 +0,0 @@
-define_list_item :bit_field, :type, :foo do
-  register_map do
-  end
-end
-
-define_list_item :register_block, :host_if, :bar do
-  rtl do
-  end
-end
-
-enable :global        , [:data_width, :address_width, :array_port_format, :unfold_sv_interface_port]
-enable :register_block, [:name, :base_address]
-enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
-enable :register      , :type, [:indirect, :external]
-enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if]
-enable :register_block, :host_if, [:apb, :bar]
-enable :register      , :rtl_top
-enable :bit_field     , :rtl_top
-enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
-enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
-enable :bit_field     , :field_model
-enable :register_block, [:c_header_file, :address_struct]

data/setup/default.rb

@@ -1,14 +0,0 @@
-enable :global        , [:data_width, :address_width, :array_port_format, :unfold_sv_interface_port]
-enable :register_block, [:name, :byte_size]
-enable :register      , [:offset_address, :name, :array, :type, :uniquness_validator]
-enable :register      , :type, [:indirect, :external]
-enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
-enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
-enable :register_block, [:rtl_top, :clock_reset, :host_if]
-enable :register_block, :host_if, [:apb, :axi4lite]
-enable :register      , :rtl_top
-enable :bit_field     , :rtl_top
-enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
-enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
-enable :bit_field     , :field_model
-enable :register_block, [:c_header_file, :address_struct]