rggen 0.8.2 → 0.9.0

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Files changed (269) hide show
  1. checksums.yaml +4 -4
  2. data/CODE_OF_CONDUCT.md +54 -29
  3. data/{LICENSE.txt → LICENSE} +1 -1
  4. data/README.md +65 -56
  5. data/lib/rggen.rb +4 -63
  6. data/lib/rggen/built_in.rb +53 -0
  7. data/lib/rggen/built_in/bit_field/bit_assignment.rb +108 -0
  8. data/lib/rggen/built_in/bit_field/comment.rb +16 -0
  9. data/lib/rggen/built_in/bit_field/initial_value.rb +45 -0
  10. data/lib/rggen/built_in/bit_field/name.rb +39 -0
  11. data/lib/rggen/built_in/bit_field/reference.rb +100 -0
  12. data/lib/rggen/built_in/bit_field/sv_rtl_top.rb +87 -0
  13. data/lib/rggen/built_in/bit_field/type.rb +279 -0
  14. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.erb +15 -0
  15. data/lib/rggen/built_in/bit_field/type/rc_w0c_w1c.rb +68 -0
  16. data/lib/rggen/built_in/bit_field/type/reserved.erb +3 -0
  17. data/lib/rggen/built_in/bit_field/type/reserved.rb +16 -0
  18. data/lib/rggen/built_in/bit_field/type/ro.erb +6 -0
  19. data/lib/rggen/built_in/bit_field/type/ro.rb +34 -0
  20. data/lib/rggen/built_in/bit_field/type/rof.erb +6 -0
  21. data/lib/rggen/built_in/bit_field/type/rof.rb +17 -0
  22. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.erb +13 -0
  23. data/lib/rggen/built_in/bit_field/type/rs_w0s_w1s.rb +52 -0
  24. data/lib/rggen/built_in/bit_field/type/rw_wo.erb +9 -0
  25. data/lib/rggen/built_in/bit_field/type/rw_wo.rb +33 -0
  26. data/lib/rggen/built_in/bit_field/type/rwe_rwl.erb +14 -0
  27. data/lib/rggen/built_in/bit_field/type/rwe_rwl.rb +39 -0
  28. data/lib/rggen/built_in/global/address_width.rb +32 -0
  29. data/lib/rggen/built_in/global/array_port_format.rb +19 -0
  30. data/lib/rggen/built_in/global/bus_width.rb +33 -0
  31. data/lib/rggen/built_in/global/fold_sv_interface_port.rb +24 -0
  32. data/lib/rggen/built_in/register/name.rb +34 -0
  33. data/lib/rggen/built_in/register/offset_address.rb +96 -0
  34. data/lib/rggen/built_in/register/size.rb +49 -0
  35. data/lib/rggen/built_in/register/sv_rtl_top.rb +82 -0
  36. data/lib/rggen/built_in/register/type.rb +374 -0
  37. data/lib/rggen/built_in/register/type/default_sv_ral.erb +8 -0
  38. data/lib/rggen/built_in/register/type/default_sv_rtl.erb +15 -0
  39. data/lib/rggen/built_in/register/type/external.erb +11 -0
  40. data/lib/rggen/built_in/register/type/external.rb +141 -0
  41. data/lib/rggen/built_in/register/type/indirect.rb +329 -0
  42. data/lib/rggen/built_in/register/type/indirect_sv_ral.erb +13 -0
  43. data/lib/rggen/built_in/register/type/indirect_sv_rtl.erb +17 -0
  44. data/lib/rggen/built_in/register_block/byte_size.rb +59 -0
  45. data/lib/rggen/built_in/register_block/name.rb +36 -0
  46. data/lib/rggen/built_in/register_block/protocol.rb +71 -0
  47. data/lib/rggen/built_in/register_block/protocol/apb.erb +10 -0
  48. data/lib/rggen/built_in/register_block/protocol/apb.rb +113 -0
  49. data/lib/rggen/built_in/register_block/protocol/axi4lite.erb +11 -0
  50. data/lib/rggen/built_in/register_block/protocol/axi4lite.rb +167 -0
  51. data/lib/rggen/built_in/register_block/sv_ral_block_model.erb +11 -0
  52. data/lib/rggen/built_in/register_block/sv_ral_package.rb +58 -0
  53. data/lib/rggen/built_in/register_block/sv_rtl_macros.erb +9 -0
  54. data/lib/rggen/built_in/register_block/sv_rtl_top.rb +87 -0
  55. data/lib/rggen/built_in/version.rb +7 -0
  56. data/lib/rggen/default_setup_file.rb +6 -0
  57. data/lib/rggen/setup/default.rb +26 -0
  58. data/lib/rggen/version.rb +5 -4
  59. data/sample/block_0.rb +85 -0
  60. data/sample/block_0.sv +601 -0
  61. data/sample/block_0.xlsx +0 -0
  62. data/sample/block_0.yml +94 -0
  63. data/sample/block_0_ral_pkg.sv +174 -0
  64. data/sample/block_1.rb +22 -0
  65. data/sample/block_1.sv +136 -0
  66. data/sample/block_1.xlsx +0 -0
  67. data/sample/block_1.yml +26 -0
  68. data/sample/block_1_ral_pkg.sv +68 -0
  69. data/sample/config.json +5 -0
  70. data/sample/config.yml +3 -0
  71. metadata +96 -270
  72. data/bin/rggen +0 -6
  73. data/c_header/LICENSE +0 -21
  74. data/c_header/rggen.h +0 -17
  75. data/lib/rggen/base/component.rb +0 -31
  76. data/lib/rggen/base/component_factory.rb +0 -53
  77. data/lib/rggen/base/hierarchical_accessors.rb +0 -87
  78. data/lib/rggen/base/hierarchical_item_accessors.rb +0 -79
  79. data/lib/rggen/base/internal_struct.rb +0 -28
  80. data/lib/rggen/base/item.rb +0 -35
  81. data/lib/rggen/base/item_factory.rb +0 -25
  82. data/lib/rggen/builder/builder.rb +0 -69
  83. data/lib/rggen/builder/category.rb +0 -63
  84. data/lib/rggen/builder/component_entry.rb +0 -50
  85. data/lib/rggen/builder/component_store.rb +0 -42
  86. data/lib/rggen/builder/input_component_store.rb +0 -25
  87. data/lib/rggen/builder/item_store.rb +0 -89
  88. data/lib/rggen/builder/list_item_entry.rb +0 -81
  89. data/lib/rggen/builder/output_component_store.rb +0 -13
  90. data/lib/rggen/builder/simple_item_entry.rb +0 -33
  91. data/lib/rggen/builtins.rb +0 -55
  92. data/lib/rggen/builtins/bit_field/bit_assignment.rb +0 -39
  93. data/lib/rggen/builtins/bit_field/field_model.rb +0 -38
  94. data/lib/rggen/builtins/bit_field/initial_value.rb +0 -36
  95. data/lib/rggen/builtins/bit_field/name.rb +0 -26
  96. data/lib/rggen/builtins/bit_field/reference.rb +0 -40
  97. data/lib/rggen/builtins/bit_field/rtl_top.rb +0 -11
  98. data/lib/rggen/builtins/bit_field/type.rb +0 -244
  99. data/lib/rggen/builtins/bit_field/types/reserved.erb +0 -6
  100. data/lib/rggen/builtins/bit_field/types/reserved.rb +0 -18
  101. data/lib/rggen/builtins/bit_field/types/ro.erb +0 -6
  102. data/lib/rggen/builtins/bit_field/types/ro.rb +0 -22
  103. data/lib/rggen/builtins/bit_field/types/rw.erb +0 -9
  104. data/lib/rggen/builtins/bit_field/types/rw.rb +0 -23
  105. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +0 -11
  106. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +0 -54
  107. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +0 -12
  108. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +0 -33
  109. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +0 -12
  110. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +0 -33
  111. data/lib/rggen/builtins/bit_field/types/wo.rb +0 -5
  112. data/lib/rggen/builtins/global/address_width.rb +0 -17
  113. data/lib/rggen/builtins/global/array_port_format.rb +0 -15
  114. data/lib/rggen/builtins/global/data_width.rb +0 -20
  115. data/lib/rggen/builtins/global/unfold_sv_interface_port.rb +0 -22
  116. data/lib/rggen/builtins/loaders/configuration/json_loader.rb +0 -7
  117. data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb +0 -7
  118. data/lib/rggen/builtins/loaders/register_map/csv_loader.rb +0 -12
  119. data/lib/rggen/builtins/loaders/register_map/xls_loader.rb +0 -17
  120. data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb +0 -21
  121. data/lib/rggen/builtins/register/array.rb +0 -30
  122. data/lib/rggen/builtins/register/constructor.rb +0 -17
  123. data/lib/rggen/builtins/register/field_model_creator.rb +0 -14
  124. data/lib/rggen/builtins/register/indirect_index_configurator.rb +0 -54
  125. data/lib/rggen/builtins/register/name.rb +0 -26
  126. data/lib/rggen/builtins/register/offset_address.rb +0 -61
  127. data/lib/rggen/builtins/register/reg_model.rb +0 -107
  128. data/lib/rggen/builtins/register/rtl_top.rb +0 -68
  129. data/lib/rggen/builtins/register/sub_block_model.rb +0 -34
  130. data/lib/rggen/builtins/register/type.rb +0 -283
  131. data/lib/rggen/builtins/register/types/default.erb +0 -10
  132. data/lib/rggen/builtins/register/types/external.erb +0 -11
  133. data/lib/rggen/builtins/register/types/external.rb +0 -77
  134. data/lib/rggen/builtins/register/types/indirect.erb +0 -13
  135. data/lib/rggen/builtins/register/types/indirect.rb +0 -175
  136. data/lib/rggen/builtins/register/uniqueness_validator.rb +0 -51
  137. data/lib/rggen/builtins/register_block/address_struct.rb +0 -56
  138. data/lib/rggen/builtins/register_block/base_address.rb +0 -64
  139. data/lib/rggen/builtins/register_block/block_model.rb +0 -20
  140. data/lib/rggen/builtins/register_block/byte_size.rb +0 -37
  141. data/lib/rggen/builtins/register_block/c_header_file.rb +0 -15
  142. data/lib/rggen/builtins/register_block/clock_reset.rb +0 -8
  143. data/lib/rggen/builtins/register_block/constructor.rb +0 -14
  144. data/lib/rggen/builtins/register_block/default_map_creator.rb +0 -39
  145. data/lib/rggen/builtins/register_block/host_if.rb +0 -64
  146. data/lib/rggen/builtins/register_block/host_ifs/apb.erb +0 -10
  147. data/lib/rggen/builtins/register_block/host_ifs/apb.rb +0 -64
  148. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +0 -11
  149. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +0 -93
  150. data/lib/rggen/builtins/register_block/name.rb +0 -26
  151. data/lib/rggen/builtins/register_block/ral_package.rb +0 -24
  152. data/lib/rggen/builtins/register_block/rtl_top.rb +0 -38
  153. data/lib/rggen/builtins/register_block/sub_model_creator.rb +0 -14
  154. data/lib/rggen/commands.rb +0 -23
  155. data/lib/rggen/core_components.rb +0 -54
  156. data/lib/rggen/core_components/c_header/item.rb +0 -8
  157. data/lib/rggen/core_components/c_header/setup.rb +0 -19
  158. data/lib/rggen/core_components/c_utility.rb +0 -19
  159. data/lib/rggen/core_components/c_utility/data_structure_definition.rb +0 -60
  160. data/lib/rggen/core_components/c_utility/source_file.rb +0 -10
  161. data/lib/rggen/core_components/c_utility/variable_declaration.rb +0 -35
  162. data/lib/rggen/core_components/code_utility.rb +0 -56
  163. data/lib/rggen/core_components/code_utility/code_block.rb +0 -72
  164. data/lib/rggen/core_components/code_utility/line.rb +0 -28
  165. data/lib/rggen/core_components/code_utility/source_file.rb +0 -97
  166. data/lib/rggen/core_components/configuration/configuration_factory.rb +0 -23
  167. data/lib/rggen/core_components/configuration/item.rb +0 -11
  168. data/lib/rggen/core_components/configuration/item_factory.rb +0 -20
  169. data/lib/rggen/core_components/configuration/raise_error.rb +0 -11
  170. data/lib/rggen/core_components/configuration/setup.rb +0 -14
  171. data/lib/rggen/core_components/erb_engine.rb +0 -15
  172. data/lib/rggen/core_components/ral/component.rb +0 -24
  173. data/lib/rggen/core_components/ral/item.rb +0 -59
  174. data/lib/rggen/core_components/ral/setup.rb +0 -19
  175. data/lib/rggen/core_components/register_map/bit_field_factory.rb +0 -11
  176. data/lib/rggen/core_components/register_map/component.rb +0 -15
  177. data/lib/rggen/core_components/register_map/component_factory.rb +0 -9
  178. data/lib/rggen/core_components/register_map/generic_map.rb +0 -80
  179. data/lib/rggen/core_components/register_map/item.rb +0 -26
  180. data/lib/rggen/core_components/register_map/item_factory.rb +0 -26
  181. data/lib/rggen/core_components/register_map/loader.rb +0 -11
  182. data/lib/rggen/core_components/register_map/raise_error.rb +0 -17
  183. data/lib/rggen/core_components/register_map/register_block_factory.rb +0 -29
  184. data/lib/rggen/core_components/register_map/register_factory.rb +0 -18
  185. data/lib/rggen/core_components/register_map/register_map_factory.rb +0 -18
  186. data/lib/rggen/core_components/register_map/setup.rb +0 -33
  187. data/lib/rggen/core_components/rtl/component.rb +0 -24
  188. data/lib/rggen/core_components/rtl/item.rb +0 -82
  189. data/lib/rggen/core_components/rtl/setup.rb +0 -19
  190. data/lib/rggen/core_components/verilog_utility.rb +0 -88
  191. data/lib/rggen/core_components/verilog_utility/class_definition.rb +0 -56
  192. data/lib/rggen/core_components/verilog_utility/identifier.rb +0 -78
  193. data/lib/rggen/core_components/verilog_utility/interface_instance.rb +0 -37
  194. data/lib/rggen/core_components/verilog_utility/interface_port.rb +0 -33
  195. data/lib/rggen/core_components/verilog_utility/local_scope.rb +0 -75
  196. data/lib/rggen/core_components/verilog_utility/module_definition.rb +0 -82
  197. data/lib/rggen/core_components/verilog_utility/package_definition.rb +0 -57
  198. data/lib/rggen/core_components/verilog_utility/source_file.rb +0 -10
  199. data/lib/rggen/core_components/verilog_utility/structure_definition.rb +0 -51
  200. data/lib/rggen/core_components/verilog_utility/subroutine_definition.rb +0 -41
  201. data/lib/rggen/core_components/verilog_utility/variable.rb +0 -115
  202. data/lib/rggen/core_extensions/array.rb +0 -9
  203. data/lib/rggen/core_extensions/facets.rb +0 -22
  204. data/lib/rggen/core_extensions/forwardable.rb +0 -49
  205. data/lib/rggen/core_extensions/integer.rb +0 -5
  206. data/lib/rggen/core_extensions/math.rb +0 -7
  207. data/lib/rggen/core_extensions/roo.rb +0 -17
  208. data/lib/rggen/exceptions.rb +0 -28
  209. data/lib/rggen/generator.rb +0 -67
  210. data/lib/rggen/input_base/component.rb +0 -28
  211. data/lib/rggen/input_base/component_factory.rb +0 -58
  212. data/lib/rggen/input_base/item.rb +0 -171
  213. data/lib/rggen/input_base/item_factory.rb +0 -13
  214. data/lib/rggen/input_base/loader.rb +0 -23
  215. data/lib/rggen/input_base/regexp_patterns.rb +0 -29
  216. data/lib/rggen/option_switches.rb +0 -60
  217. data/lib/rggen/options.rb +0 -97
  218. data/lib/rggen/output_base/code_generator.rb +0 -36
  219. data/lib/rggen/output_base/component.rb +0 -78
  220. data/lib/rggen/output_base/component_factory.rb +0 -32
  221. data/lib/rggen/output_base/file_writer.rb +0 -36
  222. data/lib/rggen/output_base/item.rb +0 -110
  223. data/lib/rggen/output_base/item_factory.rb +0 -9
  224. data/lib/rggen/output_base/template_engine.rb +0 -24
  225. data/lib/rggen/rggen_home.rb +0 -3
  226. data/ral/LICENSE +0 -21
  227. data/ral/compile.f +0 -2
  228. data/ral/rggen_ral_block.svh +0 -83
  229. data/ral/rggen_ral_field.svh +0 -47
  230. data/ral/rggen_ral_field_rwl_rwe.svh +0 -158
  231. data/ral/rggen_ral_indirect_reg.svh +0 -193
  232. data/ral/rggen_ral_macros.svh +0 -27
  233. data/ral/rggen_ral_map.svh +0 -124
  234. data/ral/rggen_ral_pkg.sv +0 -15
  235. data/ral/rggen_ral_reg.svh +0 -88
  236. data/rtl/LICENSE +0 -21
  237. data/rtl/compile.f +0 -18
  238. data/rtl/rggen_address_decoder.sv +0 -23
  239. data/rtl/rggen_apb_if.sv +0 -41
  240. data/rtl/rggen_axi4lite_if.sv +0 -68
  241. data/rtl/rggen_bit_field_if.sv +0 -28
  242. data/rtl/rggen_bit_field_ro.sv +0 -9
  243. data/rtl/rggen_bit_field_rw.sv +0 -25
  244. data/rtl/rggen_bit_field_rwl_rwe.sv +0 -29
  245. data/rtl/rggen_bit_field_w01s_w01c.sv +0 -55
  246. data/rtl/rggen_bus_if.sv +0 -43
  247. data/rtl/rggen_bus_splitter.sv +0 -86
  248. data/rtl/rggen_default_register.sv +0 -15
  249. data/rtl/rggen_external_register.sv +0 -83
  250. data/rtl/rggen_host_if_apb.sv +0 -29
  251. data/rtl/rggen_host_if_axi4lite.sv +0 -161
  252. data/rtl/rggen_indirect_register.sv +0 -21
  253. data/rtl/rggen_register_base.sv +0 -57
  254. data/rtl/rggen_register_if.sv +0 -42
  255. data/rtl/rggen_rtl_pkg.sv +0 -23
  256. data/sample/LICENSE +0 -21
  257. data/sample/sample.csv +0 -21
  258. data/sample/sample.json +0 -6
  259. data/sample/sample.xls +0 -0
  260. data/sample/sample.xlsx +0 -0
  261. data/sample/sample.yaml +0 -4
  262. data/sample/sample_0.h +0 -17
  263. data/sample/sample_0.sv +0 -402
  264. data/sample/sample_0_ral_pkg.sv +0 -145
  265. data/sample/sample_1.h +0 -9
  266. data/sample/sample_1.sv +0 -128
  267. data/sample/sample_1_ral_pkg.sv +0 -56
  268. data/sample/sample_setup.rb +0 -24
  269. data/setup/default.rb +0 -14
@@ -1,39 +0,0 @@
1
- simple_item :bit_field, :bit_assignment do
2
- register_map do
3
- field :msb
4
- field :lsb
5
- field :width do
6
- msb - lsb + 1
7
- end
8
-
9
- input_pattern %r{\[(#{number})(?::(#{number}))?\]}
10
-
11
- build do |cell|
12
- parse_bit_assignment(cell)
13
- case
14
- when @lsb > @msb
15
- error "lsb is larger than msb: #{cell}"
16
- when @msb >= configuration.data_width
17
- error "exceeds the data width(#{configuration.data_width}): #{cell}"
18
- when overlapped_bit_assignment?
19
- error "overlapped bit assignment: #{cell}"
20
- end
21
- end
22
-
23
- def parse_bit_assignment(cell)
24
- if pattern_matched?
25
- @msb, @lsb = captures.compact.map(&method(:Integer))
26
- @lsb ||= @msb
27
- else
28
- error "invalid value for bit assignment: #{cell.inspect}"
29
- end
30
- end
31
-
32
- def overlapped_bit_assignment?
33
- own_range = @lsb..@msb
34
- register.bit_fields.any? do |bit_field|
35
- own_range.overlap?(bit_field.lsb..bit_field.msb)
36
- end
37
- end
38
- end
39
- end
@@ -1,38 +0,0 @@
1
- simple_item :bit_field, :field_model do
2
- ral do
3
- export :model_creation
4
-
5
- delegate [:name, :width, :lsb, :access, :model_name] => :bit_field
6
-
7
- build do
8
- variable :reg_model, :field_model,
9
- data_type: model_name,
10
- name: name,
11
- random: true
12
- end
13
-
14
- def model_creation(code)
15
- code << subroutine_call('`rggen_ral_create_field_model', arguments) << nl
16
- end
17
-
18
- def arguments
19
- [name, string(name), width, lsb, access, volatile, reset, has_reset, hdl_path]
20
- end
21
-
22
- def volatile
23
- 0
24
- end
25
-
26
- def reset
27
- hex(bit_field.initial_value || 0, width)
28
- end
29
-
30
- def has_reset
31
- (bit_field.initial_value? && 1) || 0
32
- end
33
-
34
- def hdl_path
35
- string(bit_field.hdl_path)
36
- end
37
- end
38
- end
@@ -1,36 +0,0 @@
1
- simple_item :bit_field, :initial_value do
2
- register_map do
3
- field :initial_value
4
- field :initial_value? do
5
- @initial_value.not_nil?
6
- end
7
-
8
- build do |cell|
9
- @initial_value = parse_initial_value(cell)
10
- end
11
-
12
- validate do
13
- if initial_value? && valid_range.exclude?(@initial_value)
14
- error "out of valid initial value range(#{valid_range}):" \
15
- " #{@initial_value}"
16
- end
17
- end
18
-
19
- def parse_initial_value(cell)
20
- return if empty?(cell)
21
- Integer(cell)
22
- rescue
23
- error "invalid value for initial value: #{cell.inspect}"
24
- end
25
-
26
- def empty?(cell)
27
- cell.to_s.strip.empty?
28
- end
29
-
30
- def valid_range
31
- min_value = -1 * (2**bit_field.width) / 2
32
- max_value = 2**bit_field.width - 1
33
- (min_value..max_value)
34
- end
35
- end
36
- end
@@ -1,26 +0,0 @@
1
- simple_item :bit_field, :name do
2
- register_map do
3
- field :name
4
-
5
- input_pattern %r{(#{variable_name})}
6
-
7
- build do |cell|
8
- @name = parse_name(cell)
9
- error "repeated bit field name: #{@name}" if repeated_name?
10
- end
11
-
12
- def parse_name(cell)
13
- if pattern_matched?
14
- captures.first
15
- else
16
- error "invalid value for bit field name: #{cell.inspect}"
17
- end
18
- end
19
-
20
- def repeated_name?
21
- register_block.bit_fields.any? do |bit_field|
22
- @name == bit_field.name
23
- end
24
- end
25
- end
26
- end
@@ -1,40 +0,0 @@
1
- simple_item :bit_field, :reference do
2
- register_map do
3
- field :reference, need_validation: true, forward_to: :find_reference
4
- field :has_reference? do
5
- !(@reference.nil? || @reference.empty?)
6
- end
7
-
8
- build do |cell|
9
- @reference = cell.to_s
10
- end
11
-
12
- validate do
13
- case
14
- when @reference == bit_field.name
15
- error "self reference: #{@reference}"
16
- when not_find_reference?
17
- error "no such reference bit field: #{@reference}"
18
- when refer_reserved_bit_field?
19
- error "reserved bit field is refered: #{@reference}"
20
- end
21
- end
22
-
23
- def not_find_reference?
24
- return false unless has_reference?
25
- find_reference.nil?
26
- end
27
-
28
- def refer_reserved_bit_field?
29
- return false unless has_reference?
30
- find_reference.reserved?
31
- end
32
-
33
- private
34
-
35
- def find_reference
36
- return nil unless has_reference?
37
- @found_reference ||= register_block.bit_fields.find_by(name: @reference)
38
- end
39
- end
40
- end
@@ -1,11 +0,0 @@
1
- simple_item :bit_field, :rtl_top do
2
- rtl do
3
- generate_code :register do
4
- local_scope "g_#{bit_field.name}" do |s|
5
- s.signals bit_field.signal_declarations(:bit_field)
6
- s.without_generate_keyword
7
- s.body { |c| bit_field.generate_code(:bit_field, :top_down, c) }
8
- end
9
- end
10
- end
11
- end
@@ -1,244 +0,0 @@
1
- list_item :bit_field, :type do
2
- register_map do
3
- item_base do
4
- define_helpers do
5
- def read_write
6
- @readable = true
7
- @writable = true
8
- end
9
-
10
- def read_only
11
- @readable = true
12
- @writable = false
13
- end
14
-
15
- def write_only
16
- @readable = false
17
- @writable = true
18
- end
19
-
20
- def reserved
21
- @readable = false
22
- @writable = false
23
- end
24
-
25
- def readable?
26
- @readable.nil? || @readable
27
- end
28
-
29
- def writable?
30
- @writable.nil? || @writable
31
- end
32
-
33
- def read_only?
34
- readable? && !writable?
35
- end
36
-
37
- def write_only?
38
- writable? && !readable?
39
- end
40
-
41
- def reserved?
42
- !(readable? || writable?)
43
- end
44
-
45
- attr_setter :required_width
46
-
47
- def full_width
48
- :full_width
49
- end
50
-
51
- def need_initial_value
52
- @need_initial_value = true
53
- end
54
-
55
- def need_initial_value?
56
- @need_initial_value || false
57
- end
58
-
59
- def use_reference(options = {})
60
- @use_reference = true
61
- @reference_options = options
62
- end
63
-
64
- attr_reader :reference_options
65
-
66
- def use_reference?
67
- @use_reference || false
68
- end
69
-
70
- def same_width
71
- :same_width
72
- end
73
- end
74
-
75
- field :type
76
- field :readable? , forward_to_helper: true
77
- field :writable? , forward_to_helper: true
78
- field :read_only? , forward_to_helper: true
79
- field :write_only?, forward_to_helper: true
80
- field :reserved? , forward_to_helper: true
81
-
82
- class_delegator :full_width
83
- class_delegator :need_initial_value?
84
- class_delegator :use_reference?
85
- class_delegator :reference_options
86
- class_delegator :same_width
87
-
88
- build do |cell|
89
- @type = cell
90
- end
91
-
92
- validate do
93
- case
94
- when width_mismatch?
95
- error "#{required_width} bit(s) width required:" \
96
- " #{bit_field.width} bit(s)"
97
- when need_initial_value? && no_initial_value?
98
- error 'no initial value'
99
- when required_refercne_not_exist?
100
- error 'reference bit field required'
101
- when reference_width_mismatch?
102
- error "#{required_reference_width} bit(s) reference bit field" \
103
- " required: #{bit_field.reference.width}"
104
- end
105
- end
106
-
107
- def width_mismatch?
108
- return false if required_width.nil?
109
- if required_width.respond_to?(:include?)
110
- required_width.not.include?(bit_field.width)
111
- else
112
- bit_field.width != required_width
113
- end
114
- end
115
-
116
- def required_width
117
- width = self.class.required_width
118
- return nil if width.nil?
119
- return configuration.data_width if width == full_width
120
- width
121
- end
122
-
123
- def no_initial_value?
124
- !bit_field.initial_value?
125
- end
126
-
127
- def required_refercne_not_exist?
128
- return false unless use_reference?
129
- return false unless reference_options[:required]
130
- return false if bit_field.has_reference?
131
- true
132
- end
133
-
134
- def reference_width_mismatch?
135
- return false unless use_reference?
136
- return false unless bit_field.has_reference?
137
- bit_field.reference.width != required_reference_width
138
- end
139
-
140
- def required_reference_width
141
- return 1 unless reference_options[:width]
142
- return bit_field.width if reference_options[:width] == same_width
143
- reference_options[:width]
144
- end
145
- end
146
-
147
- factory do
148
- def select_target_item(cell)
149
- @target_items.fetch(cell.value) do
150
- error "unknown bit field type: #{cell.value}", cell
151
- end
152
- end
153
-
154
- def convert(cell)
155
- @target_items.keys.find(proc { cell }) do |type|
156
- type.to_sym.casecmp(cell.to_sym).zero?
157
- end
158
- end
159
- end
160
- end
161
-
162
- rtl do
163
- item_base do
164
- export :value
165
-
166
- delegate [
167
- :name, :width, :msb, :lsb, :type, :reserved?
168
- ] => :bit_field
169
- delegate [
170
- :dimensions, :index, :local_index, :loop_variables
171
- ] => :register
172
- delegate [
173
- :array_port_format
174
- ] => :configuration
175
-
176
- build do
177
- interface :bit_field, :bit_field_sub_if,
178
- type: :rggen_bit_field_if,
179
- name: :bit_field_sub_if,
180
- parameters: [width]
181
- end
182
-
183
- generate_pre_code :bit_field do |c|
184
- c << subroutine_call(:'`rggen_connect_bit_field_if', [
185
- register.bit_field_if, bit_field_sub_if, msb, lsb
186
- ]) << nl
187
- end
188
-
189
- def value
190
- register.register_if.value[msb, lsb]
191
- end
192
- end
193
-
194
- default_item do
195
- end
196
-
197
- factory do
198
- def select_target_item(_, bit_field)
199
- @target_items[bit_field.type]
200
- end
201
- end
202
- end
203
-
204
- ral do
205
- item_base do
206
- export :access
207
- export :model_name
208
- export :hdl_path
209
-
210
- define_helpers do
211
- attr_setter :access
212
-
213
- def model_name(&body)
214
- define_method(:model_name, &body)
215
- end
216
-
217
- def hdl_path(&body)
218
- define_method(:hdl_path, &body)
219
- end
220
- end
221
-
222
- def access
223
- string((self.class.access || bit_field.type).to_s.upcase)
224
- end
225
-
226
- def model_name
227
- :rggen_ral_field
228
- end
229
-
230
- def hdl_path
231
- "g_#{bit_field.name}.u_bit_field.value"
232
- end
233
- end
234
-
235
- default_item do
236
- end
237
-
238
- factory do
239
- def select_target_item(_, bit_field)
240
- @target_items[bit_field.type]
241
- end
242
- end
243
- end
244
- end
@@ -1,6 +0,0 @@
1
- rggen_bit_field_ro #(
2
- .WIDTH (<%= width %>)
3
- ) u_bit_field (
4
- .bit_field_if (<%= bit_field_sub_if %>),
5
- .i_value (<%= default_value %>)
6
- );