rggen 0.8.2 → 0.9.0

data/sample/block_0.yml

@@ -0,0 +1,94 @@
+register_blocks: [
+  {
+    name: block_0,
+    byte_size: 256,
+    registers: [
+      {
+        name: register_0,
+        offset_address: 0x00,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rw, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: rw, initial_value: 0 },
+          { name: bit_field_2, bit_assignment: { lsb: 8 , width: 1 }, type: rw, initial_value: 0 }
+        ]
+      },
+      {
+        name: register_1,
+        offset_address: 0x04,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: ro },
+          { name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: ro },
+          { name: bit_field_2, bit_assignment: { lsb: 16, width: 8 }, type: rof, initial_value: 0xab },
+          { name: bit_field_3, bit_assignment: { lsb: 24, width: 8 }, type: reserved }
+        ]
+      },
+      {
+        name: register_2,
+        offset_address: 0x04,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0, width: 4 }, type: wo, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 8, width: 4 }, type: wo, initial_value: 0 }
+        ]
+      },
+      {
+        name: register_3,
+        offset_address: 0x08,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: rc, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 8 , width: 4 }, type: rc, initial_value: 0, reference: register_0.bit_field_0 },
+          { name: bit_field_2, bit_assignment: { lsb: 12, width: 4 }, type: ro,                   reference: register_3.bit_field_1 },
+          { name: bit_field_3, bit_assignment: { lsb: 16, width: 4 }, type: rs, initial_value: 0 }
+        ]
+      },
+      {
+        name: register_4,
+        offset_address: 0x0C,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 8 }, type: rwe, initial_value: 0, reference: register_0.bit_field_2 },
+          { name: bit_field_1, bit_assignment: { lsb: 16, width: 8 }, type: rwl, initial_value: 0, reference: register_0.bit_field_2 }
+        ]
+      },
+      {
+        name: register_5,
+        offset_address: 0x10,
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 4 }, type: w0c, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 4 , width: 4 }, type: w0c, initial_value: 0, reference: register_0.bit_field_0 },
+          { name: bit_field_2, bit_assignment: { lsb: 8 , width: 4 }, type: ro ,                   reference: register_5.bit_field_1 },
+          { name: bit_field_3, bit_assignment: { lsb: 12, width: 4 }, type: w1c, initial_value: 0 },
+          { name: bit_field_4, bit_assignment: { lsb: 16, width: 4 }, type: w1c, initial_value: 0, reference: register_0.bit_field_0 },
+          { name: bit_field_5, bit_assignment: { lsb: 20, width: 4 }, type: ro ,                   reference: register_5.bit_field_4 },
+          { name: bit_field_6, bit_assignment: { lsb: 24, width: 4 }, type: w0s, initial_value: 0 },
+          { name: bit_field_7, bit_assignment: { lsb: 28, width: 4 }, type: w1s, initial_value: 0 },
+        ]
+      },
+      {
+        name: register_6,
+        offset_address: 0x20,
+        size: 4,
+        bit_fields: [
+          # bit assignments: [7:0] [23:16] [39:32] [55:48]
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 },
+          # bit assignments: [15:8] [31:24] [47:40] [63:56]
+          { name: bit_field_1, bit_assignment: { lsb: 8 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 }
+        ]
+      },
+      {
+        name: register_7,
+        offset_address: 0x40,
+        size: [2, 4],
+        type: [indirect, register_0.bit_field_0, register_0.bit_field_1, [register_0.bit_field_2, 1]],
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 },
+          { name: bit_field_1, bit_assignment: { lsb: 8 , width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0 }
+        ]
+      },
+      {
+        name: register_8,
+        offset_address: 0x80,
+        size: 32,
+        type: external
+      }
+    ]
+  }
+]

data/sample/block_0_ral_pkg.sv

@@ -0,0 +1,174 @@
+package block_0_ral_pkg;
+  import uvm_pkg::*;
+  import rggen_ral_pkg::*;
+  `include "uvm_macros.svh"
+  `include "rggen_ral_macros.svh"
+  class register_0_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_field bit_field_2;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, RW, 0, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 4, 4, RW, 0, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2, 8, 1, RW, 0, 1'h0, 1)
+    endfunction
+  endclass
+  class register_1_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_field bit_field_2;
+    rand rggen_ral_field bit_field_3;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, RO, 1, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_1, 8, 4, RO, 1, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_2, 16, 8, RO, 0, 8'hab, 1)
+      `rggen_ral_create_field_model(bit_field_3, 24, 8, RO, 0, 8'h00, 0)
+    endfunction
+  endclass
+  class register_2_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, WO, 0, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 8, 4, WO, 0, 4'h0, 1)
+    endfunction
+  endclass
+  class register_3_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_field bit_field_2;
+    rand rggen_ral_field bit_field_3;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, RC, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 8, 4, RC, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2, 12, 4, RO, 1, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_3, 16, 4, RS, 1, 4'h0, 1)
+    endfunction
+  endclass
+  class register_4_reg_model extends rggen_ral_reg;
+    rand rggen_ral_rwe_field #("register_0", "bit_field_2") bit_field_0;
+    rand rggen_ral_rwl_field #("register_0", "bit_field_2") bit_field_1;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 8, RWE, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1, 16, 8, RWL, 0, 8'h00, 1)
+    endfunction
+  endclass
+  class register_5_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0;
+    rand rggen_ral_field bit_field_1;
+    rand rggen_ral_field bit_field_2;
+    rand rggen_ral_field bit_field_3;
+    rand rggen_ral_field bit_field_4;
+    rand rggen_ral_field bit_field_5;
+    rand rggen_ral_field bit_field_6;
+    rand rggen_ral_field bit_field_7;
+    function new(string name);
+      super.new(name, 32, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0, 0, 4, W0C, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_1, 4, 4, W0C, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_2, 8, 4, RO, 1, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_3, 12, 4, W1C, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_4, 16, 4, W1C, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_5, 20, 4, RO, 1, 4'h0, 0)
+      `rggen_ral_create_field_model(bit_field_6, 24, 4, W0S, 1, 4'h0, 1)
+      `rggen_ral_create_field_model(bit_field_7, 28, 4, W1S, 1, 4'h0, 1)
+    endfunction
+  endclass
+  class register_6_reg_model extends rggen_ral_reg;
+    rand rggen_ral_field bit_field_0[4];
+    rand rggen_ral_field bit_field_1[4];
+    function new(string name);
+      super.new(name, 64, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
+    endfunction
+  endclass
+  class register_7_reg_model extends rggen_ral_indirect_reg;
+    rand rggen_ral_field bit_field_0[4];
+    rand rggen_ral_field bit_field_1[4];
+    function new(string name);
+      super.new(name, 64, 0);
+    endfunction
+    function void build();
+      `rggen_ral_create_field_model(bit_field_0[0], 0, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[1], 16, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[2], 32, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_0[3], 48, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[0], 8, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[1], 24, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[2], 40, 8, RW, 0, 8'h00, 1)
+      `rggen_ral_create_field_model(bit_field_1[3], 56, 8, RW, 0, 8'h00, 1)
+    endfunction
+    function void setup_index_fields();
+      setup_index_field("register_0", "bit_field_0", array_index[0]);
+      setup_index_field("register_0", "bit_field_1", array_index[1]);
+      setup_index_field("register_0", "bit_field_2", 1'h1);
+    endfunction
+  endclass
+  class block_0_block_model #(
+    type REGISTER_8 = rggen_ral_block,
+    bit INTEGRATE_REGISTER_8 = 1
+  ) extends rggen_ral_block;
+    rand register_0_reg_model register_0;
+    rand register_1_reg_model register_1;
+    rand register_2_reg_model register_2;
+    rand register_3_reg_model register_3;
+    rand register_4_reg_model register_4;
+    rand register_5_reg_model register_5;
+    rand register_6_reg_model register_6[4];
+    rand register_7_reg_model register_7[2][4];
+    rand REGISTER_8 register_8;
+    function new(string name);
+      super.new(name);
+    endfunction
+    function void build();
+      `rggen_ral_create_reg_model(register_0, '{}, 8'h00, RW, 0, g_register_0.u_register)
+      `rggen_ral_create_reg_model(register_1, '{}, 8'h04, RO, 0, g_register_1.u_register)
+      `rggen_ral_create_reg_model(register_2, '{}, 8'h04, WO, 0, g_register_2.u_register)
+      `rggen_ral_create_reg_model(register_3, '{}, 8'h08, RO, 0, g_register_3.u_register)
+      `rggen_ral_create_reg_model(register_4, '{}, 8'h0c, RW, 0, g_register_4.u_register)
+      `rggen_ral_create_reg_model(register_5, '{}, 8'h10, RW, 0, g_register_5.u_register)
+      `rggen_ral_create_reg_model(register_6[0], '{0}, 8'h20, RW, 0, g_register_6.g[0].u_register)
+      `rggen_ral_create_reg_model(register_6[1], '{1}, 8'h28, RW, 0, g_register_6.g[1].u_register)
+      `rggen_ral_create_reg_model(register_6[2], '{2}, 8'h30, RW, 0, g_register_6.g[2].u_register)
+      `rggen_ral_create_reg_model(register_6[3], '{3}, 8'h38, RW, 0, g_register_6.g[3].u_register)
+      `rggen_ral_create_reg_model(register_7[0][0], '{0, 0}, 8'h40, RW, 1, g_register_7.g[0].g[0].u_register)
+      `rggen_ral_create_reg_model(register_7[0][1], '{0, 1}, 8'h40, RW, 1, g_register_7.g[0].g[1].u_register)
+      `rggen_ral_create_reg_model(register_7[0][2], '{0, 2}, 8'h40, RW, 1, g_register_7.g[0].g[2].u_register)
+      `rggen_ral_create_reg_model(register_7[0][3], '{0, 3}, 8'h40, RW, 1, g_register_7.g[0].g[3].u_register)
+      `rggen_ral_create_reg_model(register_7[1][0], '{1, 0}, 8'h40, RW, 1, g_register_7.g[1].g[0].u_register)
+      `rggen_ral_create_reg_model(register_7[1][1], '{1, 1}, 8'h40, RW, 1, g_register_7.g[1].g[1].u_register)
+      `rggen_ral_create_reg_model(register_7[1][2], '{1, 2}, 8'h40, RW, 1, g_register_7.g[1].g[2].u_register)
+      `rggen_ral_create_reg_model(register_7[1][3], '{1, 3}, 8'h40, RW, 1, g_register_7.g[1].g[3].u_register)
+      `rggen_ral_create_block_model(register_8, 8'h80, this, INTEGRATE_REGISTER_8)
+    endfunction
+    function uvm_reg_map create_default_map();
+      return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);
+    endfunction
+  endclass
+endpackage

data/sample/block_1.rb

@@ -0,0 +1,22 @@
+# frozen_string_literal: true
+
+register_block {
+  name 'block_1'
+  byte_size 128
+
+  register {
+    name 'register_0'
+    offset_address 0x00
+    size [2, 4]
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0 }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :ro; reference 'register_1.bit_field_1' }
+  }
+
+  register {
+    name 'register_1'
+    offset_address 0x40
+    size [2, 4]
+    bit_field { name 'bit_field_0'; bit_assignment lsb: 0, width: 8, sequence_size: 4, step: 16; type :ro; reference 'register_0.bit_field_0' }
+    bit_field { name 'bit_field_1'; bit_assignment lsb: 8, width: 8, sequence_size: 4, step: 16; type :rw; initial_value 0  }
+  }
+}

data/sample/block_1.sv

@@ -0,0 +1,136 @@
+`ifndef rggen_connect_bit_field_if
+  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
+  assign  FIF.valid                 = RIF.valid; \
+  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
+  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
+  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
+  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
+  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
+`endif
+module block_1
+  import rggen_rtl_pkg::*;
+(
+  input logic i_clk,
+  input logic i_rst_n,
+  rggen_apb_if.slave apb_if,
+  output logic [1:0][3:0][3:0][7:0] o_register_0_bit_field_0,
+  output logic [1:0][3:0][3:0][7:0] o_register_1_bit_field_1
+);
+  rggen_register_if #(7, 32, 64) register_if[16]();
+  rggen_apb_adapter #(
+    .ADDRESS_WIDTH  (7),
+    .BUS_WIDTH      (32),
+    .REGISTERS      (16)
+  ) u_adapter (
+    .i_clk        (i_clk),
+    .i_rst_n      (i_rst_n),
+    .apb_if       (apb_if),
+    .register_if  (register_if)
+  );
+  generate if (1) begin : g_register_0
+    genvar i;
+    genvar j;
+    for (i = 0;i < 2;++i) begin : g
+      for (j = 0;j < 4;++j) begin : g
+        rggen_bit_field_if #(64) bit_field_if();
+        rggen_default_register #(
+          .READABLE       (1),
+          .WRITABLE       (1),
+          .ADDRESS_WIDTH  (7),
+          .OFFSET_ADDRESS (7'h00),
+          .BUS_WIDTH      (32),
+          .DATA_WIDTH     (64),
+          .VALID_BITS     (64'hffffffffffffffff),
+          .REGISTER_INDEX (4*i+j)
+        ) u_register (
+          .i_clk        (i_clk),
+          .i_rst_n      (i_rst_n),
+          .register_if  (register_if[0+4*i+j]),
+          .bit_field_if (bit_field_if)
+        );
+        if (1) begin : g_bit_field_0
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
+            rggen_bit_field_rw #(
+              .WIDTH          (8),
+              .INITIAL_VALUE  (8'h00)
+            ) u_bit_field (
+              .i_clk        (i_clk),
+              .i_rst_n      (i_rst_n),
+              .bit_field_if (bit_field_sub_if),
+              .o_value      (o_register_0_bit_field_0[i][j][k])
+            );
+          end
+        end
+        if (1) begin : g_bit_field_1
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
+            rggen_bit_field_ro #(
+              .WIDTH  (8)
+            ) u_bit_field (
+              .bit_field_if (bit_field_sub_if),
+              .i_value      (register_if[8+4*i+j].value[8+16*k+:8])
+            );
+          end
+        end
+      end
+    end
+  end endgenerate
+  generate if (1) begin : g_register_1
+    genvar i;
+    genvar j;
+    for (i = 0;i < 2;++i) begin : g
+      for (j = 0;j < 4;++j) begin : g
+        rggen_bit_field_if #(64) bit_field_if();
+        rggen_default_register #(
+          .READABLE       (1),
+          .WRITABLE       (1),
+          .ADDRESS_WIDTH  (7),
+          .OFFSET_ADDRESS (7'h40),
+          .BUS_WIDTH      (32),
+          .DATA_WIDTH     (64),
+          .VALID_BITS     (64'hffffffffffffffff),
+          .REGISTER_INDEX (4*i+j)
+        ) u_register (
+          .i_clk        (i_clk),
+          .i_rst_n      (i_rst_n),
+          .register_if  (register_if[8+4*i+j]),
+          .bit_field_if (bit_field_if)
+        );
+        if (1) begin : g_bit_field_0
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+16*k, 8)
+            rggen_bit_field_ro #(
+              .WIDTH  (8)
+            ) u_bit_field (
+              .bit_field_if (bit_field_sub_if),
+              .i_value      (register_if[0+4*i+j].value[0+16*k+:8])
+            );
+          end
+        end
+        if (1) begin : g_bit_field_1
+          genvar k;
+          for (k = 0;k < 4;++k) begin : g
+            rggen_bit_field_if #(8) bit_field_sub_if();
+            `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8+16*k, 8)
+            rggen_bit_field_rw #(
+              .WIDTH          (8),
+              .INITIAL_VALUE  (8'h00)
+            ) u_bit_field (
+              .i_clk        (i_clk),
+              .i_rst_n      (i_rst_n),
+              .bit_field_if (bit_field_sub_if),
+              .o_value      (o_register_1_bit_field_1[i][j][k])
+            );
+          end
+        end
+      end
+    end
+  end endgenerate
+endmodule

data/sample/block_1.yml

@@ -0,0 +1,26 @@
+register_blocks: [
+  {
+    name: block_1,
+    byte_size: 128,
+    registers: [
+      {
+        name: 'register_0',
+        offset_address: 0x00,
+        size: [2, 4],
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0x00 },
+          { name: bit_field_1, bit_assignment: { lsb: 8, width: 8, sequence_size: 4, step: 16 }, type: ro, reference: register_1.bit_field_1 }
+        ]
+      },
+      {
+        name: 'register_1',
+        offset_address: 0x40,
+        size: [2, 4],
+        bit_fields: [
+          { name: bit_field_0, bit_assignment: { lsb: 0, width: 8, sequence_size: 4, step: 16 }, type: ro, reference: register_0.bit_field_0 },
+          { name: bit_field_1, bit_assignment: { lsb: 8, width: 8, sequence_size: 4, step: 16 }, type: rw, initial_value: 0x00 }
+        ]
+      }
+    ]
+  }
+]