rggen 0.8.2 → 0.9.0

data/rtl/rggen_bit_field_ro.sv

@@ -1,9 +0,0 @@
-module rggen_bit_field_ro #(
-  parameter int WIDTH = 1
-)(
-  rggen_bit_field_if.slave  bit_field_if,
-  input logic [WIDTH-1:0]   i_value
-);
-  assign  bit_field_if.value      = i_value;
-  assign  bit_field_if.read_data  = i_value;
-endmodule

data/rtl/rggen_bit_field_rw.sv

@@ -1,25 +0,0 @@
-module rggen_bit_field_rw #(
-  parameter int             WIDTH         = 1,
-  parameter bit [WIDTH-1:0] INITIAL_VALUE = '0
-)(
-  input   logic             clk,
-  input   logic             rst_n,
-  rggen_bit_field_if.slave  bit_field_if,
-  output  logic [WIDTH-1:0] o_value
-);
-  logic [WIDTH-1:0] value;
-
-  assign  o_value                 = value;
-  assign  bit_field_if.value      = value;
-  assign  bit_field_if.read_data  = value;
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else if (bit_field_if.write_access) begin
-      value <= (value                   & (~bit_field_if.write_mask))
-             | (bit_field_if.write_data &   bit_field_if.write_mask );
-    end
-  end
-endmodule

data/rtl/rggen_bit_field_rwl_rwe.sv

@@ -1,29 +0,0 @@
-module rggen_bit_field_rwl_rwe
-  import rggen_rtl_pkg::*;
-#(
-  parameter rggen_rwle_mode   MODE          = RGGEN_LOCK_MODE,
-  parameter int               WIDTH         = 1,
-  parameter bit [WIDTH-1:0]   INITIAL_VALUE = '0
-)(
-  input   logic             clk,
-  input   logic             rst_n,
-  input   logic             i_lock_or_enable,
-  rggen_bit_field_if.slave  bit_field_if,
-  output  logic [WIDTH-1:0] o_value
-);
-  logic [WIDTH-1:0] value;
-
-  assign  o_value                 = value;
-  assign  bit_field_if.value      = value;
-  assign  bit_field_if.read_data  = value;
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else if ((i_lock_or_enable == MODE) && bit_field_if.write_access) begin
-      value <= (value                   & (~bit_field_if.write_mask))
-             | (bit_field_if.write_data &   bit_field_if.write_mask );
-    end
-  end
-endmodule

data/rtl/rggen_bit_field_w01s_w01c.sv

@@ -1,55 +0,0 @@
-module rggen_bit_field_w01s_w01c
-  import  rggen_rtl_pkg::*;
-#(
-  parameter rggen_rwsc_mode   MODE            = RGGEN_SET_MODE,
-  parameter bit               SET_CLEAR_VALUE = 1'b0,
-  parameter int               WIDTH           = 1,
-  parameter bit [WIDTH-1:0]   INITIAL_VALUE   = '0
-)(
-  input   logic             clk,
-  input   logic             rst_n,
-  input   logic [WIDTH-1:0] i_set_or_clear,
-  rggen_bit_field_if.slave  bit_field_if,
-  output  logic [WIDTH-1:0] o_value
-);
-  logic [WIDTH-1:0] value;
-
-  assign  o_value                           = value;
-  assign  bit_field_if.value[WIDTH-1:0]     = value;
-  assign  bit_field_if.read_data[WIDTH-1:0] = value;
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else begin
-      value <= get_next_value();
-    end
-  end
-
-  function automatic logic [WIDTH-1:0] get_next_value();
-    logic [WIDTH-1:0] write_data;
-    logic [WIDTH-1:0] write_mask;
-    logic [WIDTH-1:0] control_value;
-    logic [WIDTH-1:0] set;
-    logic [WIDTH-1:0] clear;
-
-    write_data  = bit_field_if.write_data;
-    write_mask  = bit_field_if.write_mask;
-    if (bit_field_if.write_access) begin
-      control_value = write_mask & ((SET_CLEAR_VALUE) ? write_data : ~write_data);
-    end
-    else begin
-      control_value = '0;
-    end
-    if (MODE == RGGEN_SET_MODE) begin
-      set   = control_value;
-      clear = i_set_or_clear;
-    end
-    else begin
-      set   = i_set_or_clear;
-      clear = control_value;
-    end
-    return set | (value & (~clear));
-  endfunction
-endmodule

data/rtl/rggen_bus_if.sv

@@ -1,43 +0,0 @@
-interface rggen_bus_if #(
-  parameter int ADDRESS_WIDTH = 16,
-  parameter int DATA_WIDTH    = 32
-)();
-  import  rggen_rtl_pkg::*;
-
-  logic                     request;
-  logic [ADDRESS_WIDTH-1:0] address;
-  rggen_direction           direction;
-  logic [DATA_WIDTH-1:0]    write_data;
-  logic [DATA_WIDTH/8-1:0]  write_strobe;
-  logic                     done;
-  logic                     read_done;
-  logic                     write_done;
-  logic [DATA_WIDTH-1:0]    read_data;
-  rggen_status              status;
-
-  modport master (
-    output  request,
-    output  address,
-    output  direction,
-    output  write_data,
-    output  write_strobe,
-    input   done,
-    input   read_done,
-    input   write_done,
-    input   read_data,
-    input   status
-  );
-
-  modport slave (
-    input   request,
-    input   address,
-    input   direction,
-    input   write_data,
-    input   write_strobe,
-    output  done,
-    output  read_done,
-    output  write_done,
-    output  read_data,
-    output  status
-  );
-endinterface

data/rtl/rggen_bus_splitter.sv

@@ -1,86 +0,0 @@
-module rggen_bus_splitter #(
-  parameter int DATA_WIDTH      = 32,
-  parameter int TOTAL_REGISTERS = 1
-)(
-  input logic               clk,
-  input logic               rst_n,
-  rggen_bus_if.slave        bus_if,
-  rggen_register_if.master  register_if[TOTAL_REGISTERS]
-);
-  import  rggen_rtl_pkg::*;
-
-  localparam  int STATUS_WIDTH  = $bits(rggen_status);
-
-  logic [TOTAL_REGISTERS-1:0] select;
-  logic [TOTAL_REGISTERS-1:0] ready;
-  logic                       response_ready;
-  logic                       register_selected;
-  logic                       done;
-  logic [DATA_WIDTH-1:0]      selected_read_data;
-  rggen_status                selected_status;
-  genvar                      g_i, g_j;
-
-  generate for (g_i = 0;g_i < TOTAL_REGISTERS;++g_i) begin : g
-    assign  register_if[g_i].request      = bus_if.request;
-    assign  register_if[g_i].address      = bus_if.address;
-    assign  register_if[g_i].direction    = bus_if.direction;
-    assign  register_if[g_i].write_data   = bus_if.write_data;
-    assign  register_if[g_i].write_strobe = bus_if.write_strobe;
-    assign  select[g_i]                   = register_if[g_i].select;
-    assign  ready[g_i]                    = register_if[g_i].ready;
-  end endgenerate
-
-  assign  bus_if.done       = done;
-  assign  response_ready    = |ready;
-  assign  register_selected = |select;
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      done              <= '0;
-      bus_if.read_done  <= '0;
-      bus_if.write_done <= '0;
-      bus_if.read_data  <= '0;
-      bus_if.status     <= RGGEN_OKAY;
-    end
-    else if (bus_if.request && (response_ready || (!register_selected)) && (!done)) begin
-      done              <= '1;
-      bus_if.read_done  <= (bus_if.direction == RGGEN_READ ) ? '1 : '0;
-      bus_if.write_done <= (bus_if.direction == RGGEN_WRITE) ? '1 : '0;
-      if (register_selected) begin
-        bus_if.read_data  <= selected_read_data;
-        bus_if.status     <= selected_status;
-      end
-      else begin
-        bus_if.read_data  <= '0;
-        bus_if.status     <= RGGEN_SLAVE_ERROR;
-      end
-    end
-    else begin
-      done              <= '0;
-      bus_if.read_done  <= '0;
-      bus_if.write_done <= '0;
-      bus_if.read_data  <= '0;
-      bus_if.status     <= RGGEN_OKAY;
-    end
-  end
-
-  //  Response Selection
-  generate if (1) begin : read_data_selection
-    for (g_i = 0;g_i < DATA_WIDTH;++g_i) begin : g
-      logic [TOTAL_REGISTERS-1:0] temp;
-      assign  selected_read_data[g_i] = |temp;
-      for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
-        assign  temp[g_j] = register_if[g_j].read_data[g_i] & register_if[g_j].select;
-      end
-    end
-  end endgenerate
-
-  generate if (1) begin : status_selection
-    for (g_i = 0;g_i < STATUS_WIDTH;++g_i) begin : g
-      logic [TOTAL_REGISTERS-1:0] temp;
-      assign  selected_status[g_i]  = |temp;
-      for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
-        assign  temp[g_j] = register_if[g_j].status[g_i] & register_if[g_j].select;
-      end
-    end
-  end endgenerate
-endmodule

data/rtl/rggen_default_register.sv

@@ -1,15 +0,0 @@
-module rggen_default_register #(
-  parameter int                     ADDRESS_WIDTH = 16,
-  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
-  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
-  parameter int                     DATA_WIDTH    = 32,
-  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
-)(
-  rggen_register_if.slave   register_if,
-  rggen_bit_field_if.master bit_field_if
-);
-  rggen_register_base #(
-    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS,
-    DATA_WIDTH, VALID_BITS
-  ) u_register_base (register_if, bit_field_if, 1'b1);
-endmodule

data/rtl/rggen_external_register.sv

@@ -1,83 +0,0 @@
-module rggen_external_register #(
-  parameter int                     ADDRESS_WIDTH = 16,
-  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
-  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
-  parameter int                     DATA_WIDTH    = 32
-)(
-  input logic               clk,
-  input logic               rst_n,
-  rggen_register_if.slave   register_if,
-  rggen_bus_if.master       bus_if
-);
-  import  rggen_rtl_pkg::*;
-
-  localparam  int EXTERNAL_SIZE           = END_ADDRESS - START_ADDRESS + 1;
-  localparam  int EXTERNAL_ADDRESS_WIDTH  = $clog2(EXTERNAL_SIZE);
-
-  logic                               address_match;
-  logic                               request;
-  logic [EXTERNAL_ADDRESS_WIDTH-1:0]  address;
-  rggen_direction                     direction;
-  logic [DATA_WIDTH-1:0]              write_data;
-  logic [DATA_WIDTH/8-1:0]            write_strobe;
-  logic                               access_done;
-
-  rggen_address_decoder #(
-    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS, DATA_WIDTH
-  ) u_address_decoder (register_if.address, address_match);
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      access_done <= '0;
-    end
-    else if (request && bus_if.done) begin
-      access_done <= '1;
-    end
-    else begin
-      access_done <= '0;
-    end
-  end
-
-  //  Local -> External
-  assign  bus_if.request      = request;
-  assign  bus_if.address      = address;
-  assign  bus_if.direction    = direction;
-  assign  bus_if.write_data   = write_data;
-  assign  bus_if.write_strobe = write_strobe;
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      request       <= '0;
-      address       <= '0;
-      direction     <= RGGEN_READ;
-      write_data    <= '0;
-      write_strobe  <= '0;
-    end
-    else if (request && bus_if.done) begin
-      request       <= '0;
-      address       <= '0;
-      direction     <= RGGEN_READ;
-      write_data    <= '0;
-      write_strobe  <= '0;
-    end
-    else if (register_if.request && address_match && (!request) && (!access_done)) begin
-      request       <= '1;
-      address       <= calc_address(register_if.address);
-      direction     <= register_if.direction;
-      write_data    <= register_if.write_data;
-      write_strobe  <= register_if.write_strobe;
-    end
-  end
-
-  function automatic logic [EXTERNAL_ADDRESS_WIDTH-1:0] calc_address(input [ADDRESS_WIDTH-1:0] address);
-    logic [ADDRESS_WIDTH-1:0] external_address;
-    external_address  = address - START_ADDRESS;
-    return external_address[EXTERNAL_ADDRESS_WIDTH-1:0];
-  endfunction
-
-  //  External -> Local
-  assign  register_if.select    = address_match;
-  assign  register_if.ready     = bus_if.done;
-  assign  register_if.value     = bus_if.read_data;
-  assign  register_if.read_data = bus_if.read_data;
-  assign  register_if.status    = bus_if.status;
-endmodule

data/rtl/rggen_host_if_apb.sv

@@ -1,29 +0,0 @@
-module rggen_host_if_apb #(
-  parameter int LOCAL_ADDRESS_WIDTH = 16,
-  parameter int DATA_WIDTH          = 32,
-  parameter int TOTAL_REGISTERS     = 1
-)(
-  input logic               clk,
-  input logic               rst_n,
-  rggen_apb_if.slave        apb_if,
-  rggen_register_if.master  register_if[TOTAL_REGISTERS]
-);
-  import  rggen_rtl_pkg::*;
-
-  rggen_bus_if #(LOCAL_ADDRESS_WIDTH, DATA_WIDTH) bus_if();
-
-  assign  apb_if.pready       = bus_if.done;
-  assign  apb_if.prdata       = bus_if.read_data;
-  assign  apb_if.pslverr      = bus_if.status[1];
-  assign  bus_if.request      = apb_if.psel;
-  assign  bus_if.address      = apb_if.paddr[LOCAL_ADDRESS_WIDTH-1:0];
-  assign  bus_if.direction    = rggen_direction'(apb_if.pwrite);
-  assign  bus_if.write_data   = apb_if.pwdata;
-  assign  bus_if.write_strobe = apb_if.pstrb;
-
-  rggen_bus_splitter #(
-    DATA_WIDTH, TOTAL_REGISTERS
-  ) u_bus_splitter (
-    clk, rst_n, bus_if, register_if
-  );
-endmodule

data/rtl/rggen_host_if_axi4lite.sv

@@ -1,161 +0,0 @@
-module rggen_host_if_axi4lite
-  import  rggen_rtl_pkg::*;
-#(
-  parameter int             LOCAL_ADDRESS_WIDTH = 16,
-  parameter int             DATA_WIDTH          = 32,
-  parameter int             TOTAL_REGISTERS     = 1,
-  parameter rggen_direction ACCESS_PRIORITY     = RGGEN_WRITE
-)(
-  input logic               clk,
-  input logic               rst_n,
-  rggen_axi4lite_if.slave   axi4lite_if,
-  rggen_register_if.master  register_if[TOTAL_REGISTERS]
-);
-  typedef enum logic [4:0] {
-    IDLE              = 5'b00001,
-    WRITE_IN_PROGRESS = 5'b00010,
-    WAIT_FOR_BREADY   = 5'b00100,
-    READ_IN_PROGRESS  = 5'b01000,
-    WAIT_FOR_RREADY   = 5'b10000
-  } e_state;
-
-  rggen_bus_if #(LOCAL_ADDRESS_WIDTH, DATA_WIDTH) bus_if();
-  e_state                                         state;
-
-//--------------------------------------------------------------
-//  AXI4 Lite
-//--------------------------------------------------------------
-  logic                   write_request;
-  logic                   valid_write_request;
-  logic                   write_request_ack;
-  logic                   read_request;
-  logic                   valid_read_request;
-  logic                   read_request_ack;
-  logic [DATA_WIDTH-1:0]  read_data;
-  rggen_status            status;
-
-  assign  axi4lite_if.awready = write_request_ack;
-  assign  axi4lite_if.wready  = write_request_ack;
-  assign  axi4lite_if.bvalid  = state[2];
-  assign  axi4lite_if.bresp   = status;
-  assign  axi4lite_if.arready = read_request_ack;
-  assign  axi4lite_if.rvalid  = state[4];
-  assign  axi4lite_if.rdata   = read_data;
-  assign  axi4lite_if.rresp   = status;
-
-  assign  write_request = (axi4lite_if.awvalid && axi4lite_if.wvalid) ? '1 : '0;
-  assign  read_request  = axi4lite_if.arvalid;
-
-  generate if (ACCESS_PRIORITY == RGGEN_WRITE) begin
-    assign  valid_write_request = (state[0]) ? write_request : '0;
-    assign  valid_read_request  = (state[0] && (!valid_write_request)) ? read_request : '0;
-  end
-  else begin
-    assign  valid_write_request = (state[0] && (!valid_read_request)) ? write_request : '0;
-    assign  valid_read_request  = (state[0]) ? read_request : '0;
-  end endgenerate
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      write_request_ack <= '0;
-      read_request_ack  <= '0;
-    end
-    else begin
-      write_request_ack <= valid_write_request;
-      read_request_ack  <= valid_read_request;
-    end
-  end
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      read_data <= '0;
-      status    <= RGGEN_OKAY;
-    end
-    else if ((state[1] || state[3]) && bus_if.done) begin
-      read_data <= bus_if.read_data;
-      status    <= bus_if.status;
-    end
-  end
-
-//--------------------------------------------------------------
-//  Bus IF
-//--------------------------------------------------------------
-  rggen_direction                 direction;
-  logic [LOCAL_ADDRESS_WIDTH-1:0] address;
-  logic [DATA_WIDTH-1:0]          write_data;
-  logic [DATA_WIDTH/8-1:0]        write_strobe;
-
-  assign  bus_if.request      = (state[1] || state[3]) ? '1 : '0;
-  assign  bus_if.direction    = direction;
-  assign  bus_if.address      = address;
-  assign  bus_if.write_data   = write_data;
-  assign  bus_if.write_strobe = write_strobe;
-
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      direction     <= RGGEN_READ;
-      address       <= '0;
-      write_data    <= '0;
-      write_strobe  <= '0;
-    end
-    else if (state[0]) begin
-      if (valid_write_request) begin
-        direction     <= RGGEN_WRITE;
-        address       <= axi4lite_if.awaddr;
-        write_data    <= axi4lite_if.wdata;
-        write_strobe  <= axi4lite_if.wstrb;
-      end
-      else if (valid_read_request) begin
-        direction <= RGGEN_READ;
-        address   <= axi4lite_if.araddr;
-      end
-    end
-  end
-
-  rggen_bus_splitter #(
-    DATA_WIDTH, TOTAL_REGISTERS
-  ) u_bus_splitter (
-    clk, rst_n, bus_if, register_if
-  );
-
-//--------------------------------------------------------------
-//  State Machine
-//--------------------------------------------------------------
-  always_ff @(posedge clk, negedge rst_n) begin
-    if (!rst_n) begin
-      state <= IDLE;
-    end
-    else begin
-      case (state)
-        IDLE: begin
-          if (valid_write_request) begin
-            state <= WRITE_IN_PROGRESS;
-          end
-          else if (valid_read_request) begin
-            state <= READ_IN_PROGRESS;
-          end
-        end
-        WRITE_IN_PROGRESS: begin
-          if (bus_if.write_done) begin
-            state <= WAIT_FOR_BREADY;
-          end
-        end
-        WAIT_FOR_BREADY: begin
-          if (axi4lite_if.bready) begin
-            state <= IDLE;
-          end
-        end
-        READ_IN_PROGRESS: begin
-          if (bus_if.read_done) begin
-            state <= WAIT_FOR_RREADY;
-          end
-        end
-        WAIT_FOR_RREADY: begin
-          if (axi4lite_if.rready) begin
-            state <= IDLE;
-          end
-        end
-      endcase
-    end
-  end
-endmodule