rggen 0.8.2 → 0.9.0

data/ral/rggen_ral_macros.svh

@@ -1,27 +0,0 @@
-`ifndef __RGGEN_RAL_MACROS_SVH__
-`define __RGGEN_RAL_MACROS_SVH__
-
-`define rggen_ral_create_field_model(handle, name, width, lsb, access, volatile, reset, has_reset, hdl_path) \
-begin \
-  handle  = new(name); \
-  handle.configure(this.cfg, this, width, lsb, access, volatile, reset, has_reset, 1, 1); \
-  this.add_field_hdl_path(hdl_path, lsb, width); \
-end
-
-`define rggen_ral_create_reg_model(handle, name, array_index, offset_address, rights, unmapped, hdl_path) \
-begin \
-  handle  = new(name); \
-  handle.configure(this.cfg, this, null, array_index, hdl_path); \
-  handle.build(); \
-  default_map.add_reg(handle, offset_address, rights, unmapped); \
-end
-
-`define rggen_ral_create_block_model(handle, name, offset_address) \
-begin \
-  handle  = new(name); \
-  handle.configure(this.cfg, this, ""); \
-  handle.build(); \
-  default_map.add_submap(handle.default_map, offset_address); \
-end
-
-`endif

data/ral/rggen_ral_map.svh

@@ -1,124 +0,0 @@
-`ifndef __RGGEN_RAL_MAP_SVH__
-`define __RGGEN_RAL_MAP_SVH__
-class rggen_ral_map extends uvm_reg_map;
-  protected rggen_ral_indirect_reg  m_indirect_regs_by_offset[uvm_reg_addr_t][$];
-
-  extern function new(string name = "rggen_ral_map");
-
-  extern virtual function void add_reg(
-    uvm_reg           rg,
-    uvm_reg_addr_t    offset,
-    string            rights    = "RW",
-    bit               unmapped  = 0,
-    uvm_reg_frontdoor frontdoor = null
-  );
-  extern virtual function void set_base_addr(uvm_reg_addr_t offset);
-  extern virtual function void set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset);
-
-  extern virtual function uvm_reg get_reg_by_offset(uvm_reg_addr_t offset, bit read = 1);
-
-  extern function void Xinit_indirect_reg_address_mapX();
-
-  `uvm_object_utils(rggen_ral_map)
-endclass
-
-function rggen_ral_map::new(string name);
-  super.new(name);
-endfunction
-
-function void rggen_ral_map::add_reg(
-  uvm_reg           rg,
-  uvm_reg_addr_t    offset,
-  string            rights,
-  bit               unmapped,
-  uvm_reg_frontdoor frontdoor
-);
-  rggen_ral_reg           rggen_reg;
-  rggen_ral_indirect_reg  rggen_indirect_reg;
-
-  if ((frontdoor == null) && $cast(rggen_reg, rg)) begin
-    frontdoor = rggen_reg.create_frontdoor();
-  end
-  if ($cast(rggen_indirect_reg, rg)) begin
-    unmapped  = 1;
-  end
-  super.add_reg(rg, offset, rights, unmapped, frontdoor);
-endfunction
-
-function void rggen_ral_map::set_base_addr(uvm_reg_addr_t offset);
-  uvm_reg_block parent_block  = get_parent();
-  uvm_reg_map   parent_map    = get_parent_map();
-  bit           locked        = parent_block.is_locked();
-  super.set_base_addr(offset);
-  if ((parent_map == null) && locked) begin
-    Xinit_indirect_reg_address_mapX();
-  end
-endfunction
-
-function void rggen_ral_map::set_submap_offset(uvm_reg_map submap, uvm_reg_addr_t offset);
-  uvm_reg_block parent_block  = get_parent();
-  bit           locked        = parent_block.is_locked();
-  super.set_submap_offset(submap, offset);
-  if ((submap != null) && locked) begin
-    uvm_reg_map   root_map  = get_root_map();
-    rggen_ral_map rggen_map;
-    if ($cast(rggen_map, root_map)) begin
-      rggen_map.Xinit_indirect_reg_address_mapX();
-    end
-  end
-endfunction
-
-function uvm_reg rggen_ral_map::get_reg_by_offset(uvm_reg_addr_t offset, bit read);
-  uvm_reg       rg      = super.get_reg_by_offset(offset, read);
-  uvm_reg_block parent  = get_parent();
-  if ((rg == null) && parent.is_locked() && m_indirect_regs_by_offset.exists(offset)) begin
-    foreach (m_indirect_regs_by_offset[offset][i]) begin
-      if (m_indirect_regs_by_offset[offset][i].is_active()) begin
-        rg  = m_indirect_regs_by_offset[offset][i];
-        break;
-      end
-    end
-  end
-  return rg;
-endfunction
-
-function void rggen_ral_map::Xinit_indirect_reg_address_mapX();
-  uvm_reg_map   top_map;
-  rggen_ral_map top_rggen_map;
-  uvm_reg_map   submaps[$];
-  uvm_reg       regs[$];
-
-  top_map = get_root_map();
-  if (top_map == this) begin
-    m_indirect_regs_by_offset.delete();
-  end
-  if (!$cast(top_rggen_map, top_map)) begin
-    return;
-  end
-
-  get_submaps(submaps, UVM_NO_HIER);
-  foreach (submaps[i]) begin
-    rggen_ral_map rggen_map;
-    if ($cast(rggen_map, submaps[i])) begin
-      rggen_map.Xinit_indirect_reg_address_mapX();
-    end
-  end
-
-  get_registers(regs, UVM_NO_HIER);
-  foreach (regs[i]) begin
-    rggen_ral_indirect_reg  indirect_reg;
-    uvm_reg_map_info        map_info;
-
-    if (!$cast(indirect_reg, regs[i])) begin
-      continue;
-    end
-
-    map_info          = get_reg_map_info(indirect_reg);
-    map_info.unmapped = 0;
-    void'(get_physical_addresses(map_info.offset, 0, indirect_reg.get_n_bytes(), map_info.addr));
-    foreach (map_info.addr[j]) begin
-      top_rggen_map.m_indirect_regs_by_offset[map_info.addr[j]].push_back(indirect_reg);
-    end
-  end
-endfunction
-`endif

data/ral/rggen_ral_pkg.sv

@@ -1,15 +0,0 @@
-`ifndef __RGGEN_RAL_PKG_SV__
-`define __RGGEN_RAL_PKG_SV__
-package rggen_ral_pkg;
-  import  uvm_pkg::*;
-  `include  "uvm_macros.svh"
-
-  `include  "rggen_ral_macros.svh"
-  `include  "rggen_ral_field.svh"
-  `include  "rggen_ral_field_rwl_rwe.svh"
-  `include  "rggen_ral_reg.svh"
-  `include  "rggen_ral_indirect_reg.svh"
-  `include  "rggen_ral_map.svh"
-  `include  "rggen_ral_block.svh"
-endpackage
-`endif

data/ral/rggen_ral_reg.svh

@@ -1,88 +0,0 @@
-`ifndef __RGGEN_RAL_REG_SVH__
-`define __RGGEN_RAL_REG_SVH__
-class rggen_ral_reg extends uvm_reg;
-  protected int         indexes[$];
-  protected uvm_object  cfg;
-  protected string      hdl_path_scopes[string];
-
-  extern function new(string name, int unsigned n_bits, int has_coverage);
-
-  extern function void configure(
-    uvm_object    cfg,
-    uvm_reg_block blk_parent,
-    uvm_reg_file  regfile_parent,
-    int           indexes[$],
-    string        hdl_path            = "",
-    bit           single_hdl_variable = 0
-  );
-  extern virtual function void build();
-
-  extern virtual function uvm_reg_frontdoor create_frontdoor();
-
-  extern function void set_hdl_path_scope(string hdl_path_scope, string kind = "RTL");
-  extern function void add_field_hdl_path(string name, int offset, int size, string kind = "RTL", string separalor = ".");
-
-  extern protected virtual function void set_cfg(uvm_object cfg);
-  extern protected virtual function void create_fields();
-endclass
-
-function rggen_ral_reg::new(string name, int unsigned n_bits, int has_coverage);
-  super.new(name, n_bits, has_coverage);
-endfunction
-
-function void rggen_ral_reg::configure(
-  uvm_object    cfg,
-  uvm_reg_block blk_parent,
-  uvm_reg_file  regfile_parent,
-  int           indexes[$],
-  string        hdl_path,
-  bit           single_hdl_variable
-);
-  foreach (indexes[i]) begin
-    this.indexes.push_back(indexes[i]);
-  end
-  set_cfg(cfg);
-  if (single_hdl_variable) begin
-    super.configure(blk_parent, regfile_parent, hdl_path);
-  end
-  else begin
-    super.configure(blk_parent, regfile_parent);
-    set_hdl_path_scope(hdl_path);
-  end
-endfunction
-
-function void rggen_ral_reg::build();
-  create_fields();
-endfunction
-
-function uvm_reg_frontdoor rggen_ral_reg::create_frontdoor();
-  return null;
-endfunction
-
-function void rggen_ral_reg::set_hdl_path_scope(string hdl_path_scope, string kind);
-  if (hdl_path_scope.len() > 0) begin
-    hdl_path_scopes[kind] = hdl_path_scope;
-  end
-endfunction
-
-function void rggen_ral_reg::add_field_hdl_path(string name, int offset, int size, string kind, string separalor);
-  string  path;
-  if (name.len() == 0) begin
-    return;
-  end
-  if (hdl_path_scopes.exists(kind) && (hdl_path_scopes[kind].len() > 0)) begin
-    path  = {hdl_path_scopes[kind], separalor, name};
-  end
-  else begin
-    path  = name;
-  end
-  add_hdl_path_slice(path, offset, size, 0, kind);
-endfunction
-
-function void rggen_ral_reg::set_cfg(uvm_object cfg);
-  this.cfg  = cfg;
-endfunction
-
-function void rggen_ral_reg::create_fields();
-endfunction
-`endif

data/rtl/LICENSE

@@ -1,21 +0,0 @@
-MIT License
-
-Copyright (c) 2017 Taichi Ishitani
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.

data/rtl/compile.f

@@ -1,18 +0,0 @@
-${RGGEN_HOME}/rtl/rggen_rtl_pkg.sv
-${RGGEN_HOME}/rtl/rggen_bus_if.sv
-${RGGEN_HOME}/rtl/rggen_register_if.sv
-${RGGEN_HOME}/rtl/rggen_bit_field_if.sv
-${RGGEN_HOME}/rtl/rggen_bus_splitter.sv
-${RGGEN_HOME}/rtl/rggen_address_decoder.sv
-${RGGEN_HOME}/rtl/rggen_register_base.sv
-${RGGEN_HOME}/rtl/rggen_default_register.sv
-${RGGEN_HOME}/rtl/rggen_indirect_register.sv
-${RGGEN_HOME}/rtl/rggen_external_register.sv
-${RGGEN_HOME}/rtl/rggen_bit_field_ro.sv
-${RGGEN_HOME}/rtl/rggen_bit_field_rw.sv
-${RGGEN_HOME}/rtl/rggen_bit_field_rwl_rwe.sv
-${RGGEN_HOME}/rtl/rggen_bit_field_w01s_w01c.sv
-${RGGEN_HOME}/rtl/rggen_apb_if.sv
-${RGGEN_HOME}/rtl/rggen_host_if_apb.sv
-${RGGEN_HOME}/rtl/rggen_axi4lite_if.sv
-${RGGEN_HOME}/rtl/rggen_host_if_axi4lite.sv

data/rtl/rggen_address_decoder.sv

@@ -1,23 +0,0 @@
-module rggen_address_decoder #(
-  parameter int                     ADDRESS_WIDTH = 8,
-  parameter bit [ADDRESS_WIDTH-1:0] STAET_ADDRESS = '0,
-  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
-  parameter int                     DATA_WIDTH    = 32
-)(
-  input   logic [ADDRESS_WIDTH-1:0] i_address,
-  output  logic                     o_match
-);
-  localparam  int                         LSB       = $clog2(DATA_WIDTH / 8);
-  localparam  bit [ADDRESS_WIDTH-LSB-1:0] SADDRESS  = STAET_ADDRESS[ADDRESS_WIDTH-1:LSB];
-  localparam  bit [ADDRESS_WIDTH-LSB-1:0] EADDRESS  = END_ADDRESS[ADDRESS_WIDTH-1:LSB];
-
-  generate if (SADDRESS == EADDRESS) begin
-    assign  o_match = (i_address[ADDRESS_WIDTH-1:LSB] == SADDRESS) ? 1'b1 : 1'b0;
-  end
-  else begin
-    assign  o_match = (
-      (i_address[ADDRESS_WIDTH-1:LSB] >= SADDRESS) &&
-      (i_address[ADDRESS_WIDTH-1:LSB] <= EADDRESS)
-    ) ? 1'b1 : 1'b0;
-  end endgenerate
-endmodule

data/rtl/rggen_apb_if.sv

@@ -1,41 +0,0 @@
-interface rggen_apb_if #(
-  parameter int ADDRESS_WIDTH = 16,
-  parameter int DATA_WIDTH    = 32
-)();
-  logic                     psel;
-  logic                     penable;
-  logic [ADDRESS_WIDTH-1:0] paddr;
-  logic [2:0]               pprot;
-  logic                     pwrite;
-  logic [DATA_WIDTH-1:0]    pwdata;
-  logic [DATA_WIDTH/8-1:0]  pstrb;
-  logic                     pready;
-  logic [DATA_WIDTH-1:0]    prdata;
-  logic                     pslverr;
-
-  modport master (
-    output  psel,
-    output  penable,
-    output  paddr,
-    output  pprot,
-    output  pwrite,
-    output  pwdata,
-    output  pstrb,
-    input   pready,
-    input   prdata,
-    input   pslverr
-  );
-
-  modport slave (
-    input   psel,
-    input   penable,
-    input   paddr,
-    input   pprot,
-    input   pwrite,
-    input   pwdata,
-    input   pstrb,
-    output  pready,
-    output  prdata,
-    output  pslverr
-  );
-endinterface

data/rtl/rggen_axi4lite_if.sv

@@ -1,68 +0,0 @@
-interface rggen_axi4lite_if #(
-  parameter int ADDRESS_WIDTH = 16,
-  parameter int DATA_WIDTH    = 32
-)();
-  logic                     awvalid;
-  logic                     awready;
-  logic [ADDRESS_WIDTH-1:0] awaddr;
-  logic [2:0]               awprot;
-  logic                     wvalid;
-  logic                     wready;
-  logic [DATA_WIDTH-1:0]    wdata;
-  logic [DATA_WIDTH/8-1:0]  wstrb;
-  logic                     bvalid;
-  logic                     bready;
-  logic [1:0]               bresp;
-  logic                     arvalid;
-  logic                     arready;
-  logic [ADDRESS_WIDTH-1:0] araddr;
-  logic [2:0]               arprot;
-  logic                     rvalid;
-  logic                     rready;
-  logic [DATA_WIDTH-1:0]    rdata;
-  logic [1:0]               rresp;
-
-  modport master (
-    output  awvalid,
-    input   awready,
-    output  awaddr,
-    output  awprot,
-    output  wvalid,
-    input   wready,
-    output  wdata,
-    output  wstrb,
-    input   bvalid,
-    output  bready,
-    input   bresp,
-    output  arvalid,
-    input   arready,
-    output  araddr,
-    output  arprot,
-    input   rvalid,
-    output  rready,
-    input   rdata,
-    input   rresp
-  );
-
-  modport slave (
-      input   awvalid,
-      output  awready,
-      input   awaddr,
-      input   awprot,
-      input   wvalid,
-      output  wready,
-      input   wdata,
-      input   wstrb,
-      output  bvalid,
-      input   bready,
-      output  bresp,
-      input   arvalid,
-      output  arready,
-      input   araddr,
-      input   arprot,
-      output  rvalid,
-      input   rready,
-      output  rdata,
-      output  rresp
-    );
-endinterface

data/rtl/rggen_bit_field_if.sv

@@ -1,28 +0,0 @@
-interface rggen_bit_field_if #(
-  parameter int DATA_WIDTH  = 32
-)();
-  logic                   read_access;
-  logic                   write_access;
-  logic [DATA_WIDTH-1:0]  write_data;
-  logic [DATA_WIDTH-1:0]  write_mask;
-  logic [DATA_WIDTH-1:0]  value;
-  logic [DATA_WIDTH-1:0]  read_data;
-
-  modport master (
-    output  read_access,
-    output  write_access,
-    output  write_data,
-    output  write_mask,
-    input   value,
-    input   read_data
-  );
-
-  modport slave (
-    input   read_access,
-    input   write_access,
-    input   write_data,
-    input   write_mask,
-    output  value,
-    output  read_data
-  );
-endinterface