rggen 0.8.2 → 0.9.0

data/lib/rggen/core_components/register_map/item_factory.rb

@@ -1,26 +0,0 @@
-module RgGen
-  module RegisterMap
-    class ItemFactory < InputBase::ItemFactory
-      include RaiseError
-
-      def create(component, cell = nil)
-        convert_cell_value(cell)
-        create_item(component, cell) do |item|
-          item.build(cell) unless cell.nil?
-        end
-      end
-
-      private
-
-      def convert_cell_value(cell)
-        return if cell.nil?
-        return if cell.empty?
-        cell.value  = convert(cell.value)
-      end
-
-      def convert(cell)
-        cell
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/loader.rb

@@ -1,11 +0,0 @@
-module RgGen
-  module RegisterMap
-    class Loader < InputBase::Loader
-      private
-
-      def create_map(file)
-        GenericMap.new(file).tap { |m| yield(m) if block_given? }
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/raise_error.rb

@@ -1,17 +0,0 @@
-module RgGen
-  module RegisterMap
-    module RaiseError
-      private
-
-      def error(message, cell_or_position = nil)
-        error_position  =
-          case cell_or_position
-          when GenericMap::Cell::Position then cell_or_position
-          when GenericMap::Cell then cell_or_position.position
-          else @position
-          end
-        raise RgGen::RegisterMapError.new(message, error_position)
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/register_block_factory.rb

@@ -1,29 +0,0 @@
-module RgGen
-  module RegisterMap
-    class RegisterBlockFactory < ComponentFactory
-      def create_active_items(register_block, sheet)
-        active_item_factories.each_value.with_index do |factory, index|
-          cell  = sheet[index, 2]
-          create_item(factory, register_block, cell)
-        end
-      end
-
-      def create_children(register_block, configuration, sheet)
-        cell_blocks(sheet).each do |block|
-          create_child(register_block, configuration, block)
-        end
-      end
-
-      def cell_blocks(sheet)
-        drop_row_size     = active_item_factories.size + 2
-        drop_column_size  = 1
-        sheet.rows.drop(drop_row_size).each_with_object([]) do |row, blocks|
-          valid_cells = row.drop(drop_column_size)
-          next if valid_cells.all?(&:empty?)
-          blocks      << [] unless valid_cells.first.empty?
-          blocks.last << valid_cells
-        end
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/register_factory.rb

@@ -1,18 +0,0 @@
-module RgGen
-  module RegisterMap
-    class RegisterFactory < ComponentFactory
-      def create_active_items(register, rows)
-        active_item_factories.each_value.with_index do |factory, index|
-          create_item(factory, register, rows.first[index])
-        end
-      end
-
-      def create_children(register, configuration, rows)
-        drop_size = active_item_factories.size
-        rows.each do |row|
-          create_child(register, configuration, row.drop(drop_size))
-        end
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/register_map_factory.rb

@@ -1,18 +0,0 @@
-module RgGen
-  module RegisterMap
-    class RegisterMapFactory < ComponentFactory
-      def create_children(register_map, configuration, map)
-        map.sheets.each do |sheet|
-          create_child(register_map, configuration, sheet)
-        end
-      end
-
-      def load(file)
-        map = load_file(file)
-        return map if map.is_a?(GenericMap)
-        message = "GenericMap type required for register map: #{map.class}"
-        raise RgGen::LoadError, message
-      end
-    end
-  end
-end

data/lib/rggen/core_components/register_map/setup.rb

@@ -1,33 +0,0 @@
-module RgGen
-  module RegisterMap
-    input_component_store :register_map do
-      entry do
-        component_class   Component
-        component_factory RegisterMapFactory
-      end
-
-      entry :register_block do
-        component_class   Component
-        component_factory RegisterBlockFactory
-        item_base         Item
-        item_factory      ItemFactory
-      end
-
-      entry :register do
-        component_class   Component
-        component_factory RegisterFactory
-        item_base         Item
-        item_factory      ItemFactory
-      end
-
-      entry :bit_field do
-        component_class   Component
-        component_factory BitFieldFactory
-        item_base         Item
-        item_factory      ItemFactory
-      end
-
-      loader_base Loader
-    end
-  end
-end

data/lib/rggen/core_components/rtl/component.rb

@@ -1,24 +0,0 @@
-module RgGen
-  module RTL
-    class Component < OutputBase::Component
-      def build
-        super
-        @items.each do |item|
-          def_object_delegators(item, *item.identifiers)
-        end
-      end
-
-      def signal_declarations(domain)
-        [*@items, *@children].flat_map { |o| o.signal_declarations(domain) }
-      end
-
-      def port_declarations(domain)
-        [*@items, *@children].flat_map { |o| o.port_declarations(domain) }
-      end
-
-      def parameter_declarations(domain)
-        [*@items, *@children].flat_map { |o| o.parameter_declarations(domain) }
-      end
-    end
-  end
-end

data/lib/rggen/core_components/rtl/item.rb

@@ -1,82 +0,0 @@
-module RgGen
-  module RTL
-    class Item < OutputBase::Item
-      include         VerilogUtility
-      template_engine ERBEngine
-
-      def initialize(owner)
-        super(owner)
-        @identifiers              = []
-        @signal_declarations      = Hash.new { |h, d| h[d]  = [] }
-        @port_declarations        = Hash.new { |h, d| h[d]  = [] }
-        @parameter_declarations   = Hash.new { |h, d| h[d]  = [] }
-      end
-
-      attr_reader :identifiers
-
-      def_delegator :@signal_declarations   , :[], :signal_declarations
-      def_delegator :@port_declarations     , :[], :port_declarations
-      def_delegator :@parameter_declarations, :[], :parameter_declarations
-
-      class << self
-        private
-
-        def define_declaration_method(method_name)
-          define_method(method_name) do |domain, handle_name, attributes = {}|
-            attributes[:name] ||= handle_name
-            declaration = create_declaration(method_name, attributes)
-            add_declaration(method_name, domain, declaration)
-            add_identifier(handle_name, declaration.identifier)
-          end
-          private method_name
-        end
-      end
-
-      define_declaration_method :wire
-      define_declaration_method :reg
-      define_declaration_method :logic
-      define_declaration_method :interface
-      define_declaration_method :input
-      define_declaration_method :output
-      define_declaration_method :interface_port
-      define_declaration_method :parameter
-      define_declaration_method :localparam
-
-      private
-
-      def create_declaration(type, attributes)
-        case type
-        when :wire, :reg, :logic
-          variable_declaration(attributes.merge(data_type: type))
-        when :interface
-          interface_instance(attributes)
-        when :input, :output
-          port_declaration(attributes.merge(direction: type))
-        when :interface_port
-          interface_port_declaration(attributes)
-        when :parameter, :localparam
-          parameter_declaration(attributes.merge(parameter_type: type))
-        end
-      end
-
-      def add_declaration(type, domain, declaration)
-        declarations  =
-          case type
-          when :wire, :reg, :logic, :interface
-            @signal_declarations[domain]
-          when :input, :output, :interface_port
-            @port_declarations[domain]
-          when :parameter, :localparam
-            @parameter_declarations[domain]
-          end
-        declarations  << declaration
-      end
-
-      def add_identifier(handle_name, identifier)
-        instance_variable_set(handle_name.variablize, identifier)
-        attr_singleton_reader(handle_name)
-        identifiers << handle_name
-      end
-    end
-  end
-end

data/lib/rggen/core_components/rtl/setup.rb

@@ -1,19 +0,0 @@
-module RgGen
-  module RTL
-    output_component_store :rtl do
-      entry do
-        component_class   OutputBase::Component
-        component_factory OutputBase::ComponentFactory
-      end
-
-      entry [:register_block, :register, :bit_field] do
-        component_class   Component
-        component_factory OutputBase::ComponentFactory
-        item_base         Item
-        item_factory      OutputBase::ItemFactory
-      end
-
-      output_directory  'rtl'
-    end
-  end
-end

data/lib/rggen/core_components/verilog_utility.rb

@@ -1,88 +0,0 @@
-module RgGen
-  module VerilogUtility
-    include CodeUtility
-
-    def create_blank_file(path)
-      SourceFile.new(path)
-    end
-
-    private
-
-    def create_identifier(name)
-      Identifier.new(name)
-    end
-
-    def variable_declaration(attributes)
-      Variable.new(:variable, attributes)
-    end
-
-    def interface_instance(attributes)
-      InterfaceInstance.new(attributes)
-    end
-
-    def port_declaration(attributes)
-      Variable.new(:port, attributes)
-    end
-
-    def interface_port_declaration(attributes)
-      InterfacePort.new(attributes)
-    end
-
-    def parameter_declaration(attributes)
-      Variable.new(:parameter, attributes)
-    end
-
-    def module_definition(name, &body)
-      ModuleDefinition.new(name, &body).to_code
-    end
-
-    def package_definition(name, &body)
-      PackageDefinition.new(name, &body).to_code
-    end
-
-    def class_definition(name, &body)
-      ClassDefinition.new(name, &body).to_code
-    end
-
-    def function_definition(name, &body)
-      SubroutineDefinition.new(:function, name, &body).to_code
-    end
-
-    def local_scope(block_name, &body)
-      LocalScope.new(block_name, &body).to_code
-    end
-
-    def argument(name, attributes)
-      port_declaration(attributes.merge(name: name))
-    end
-
-    def assign(lhs, rhs)
-      "assign #{lhs} = #{rhs};"
-    end
-
-    def subroutine_call(subroutine, arguments = nil)
-      "#{subroutine}(#{Array(arguments).join(', ')})"
-    end
-
-    def concat(expression_or_expressions)
-      "{#{Array(expression_or_expressions).join(', ')}}"
-    end
-
-    def array(expression_or_expressions)
-      "'#{concat(expression_or_expressions)}"
-    end
-
-    def bin(value, width)
-      format("%d'b%0*b", width, width, value)
-    end
-
-    def dec(value, width)
-      format("%d'd%d", width, value)
-    end
-
-    def hex(value, width)
-      print_width = (width + 3) / 4
-      format("%d'h%0*x", width, print_width, value)
-    end
-  end
-end

data/lib/rggen/core_components/verilog_utility/class_definition.rb

@@ -1,56 +0,0 @@
-module RgGen
-  module VerilogUtility
-    class ClassDefinition < StructureDefinition
-      attr_setter :base
-      attr_setter :parameters
-      attr_setter :variables
-
-      private
-
-      def header_code
-        code_block do |code|
-          code << :class << space << @name
-          parameters? && paraemter_declarations(code)
-          @base && (code << space <<:extends << space << @base)
-          code << semicolon
-        end
-      end
-
-      def body_code_blocks
-        blocks = []
-        variables? && (blocks << variables_declarations)
-        blocks.concat(super)
-        blocks
-      end
-
-      def footer_code
-        :endclass
-      end
-
-      def parameters?
-        !(@parameters.nil? || @parameters.empty?)
-      end
-
-      def variables?
-        !(@variables.nil? || @variables.empty?)
-      end
-
-      def paraemter_declarations(code)
-        wrap(code, '#(', ')') do
-          indent(code, 2) do
-            @parameters.each_with_index do |d, i|
-              code << comma << nl if i > 0
-              code << d
-            end
-          end
-        end
-      end
-
-      def variables_declarations
-        lambda do |code|
-          variables.each { |variable| code << variable << semicolon << nl }
-        end
-      end
-    end
-  end
-end

data/lib/rggen/core_components/verilog_utility/identifier.rb

@@ -1,78 +0,0 @@
-module RgGen
-  module VerilogUtility
-    class Identifier
-      include InputBase::RegxpPatterns
-
-      def initialize(name, width = nil, array_dimensions = nil, array_format = nil)
-        @name             = name
-        @width            = width
-        @array_dimensions = array_dimensions
-        @array_format     = array_format || :unpacked
-      end
-
-      def to_s
-        @name.to_s
-      end
-
-      def [](array_index_or_msb, lsb = array_index_or_msb)
-        if array_index_or_msb.nil?
-          self
-        else
-          new_name  =
-            if array_index_or_msb.is_a?(Array)
-              "#{@name}#{array_selection(array_index_or_msb)}"
-            elsif array_index_or_msb == lsb
-              "#{@name}[#{array_index_or_msb}]"
-            else
-              "#{@name}[#{array_index_or_msb}:#{lsb}]"
-            end
-          Identifier.new(new_name, nil, nil, nil)
-        end
-      end
-
-      TYPE_CONVERSIONS  = [
-        :to_a, :to_ary, :to_hash, :to_int, :to_io, :to_proc, :to_regexp, :to_str
-      ].freeze
-
-      def method_missing(name, *args)
-        args.size.zero? || (return super)
-        TYPE_CONVERSIONS.include?(name) && (return super)
-        (name =~ variable_name) || (return super)
-        Identifier.new("#{@name}.#{name}", nil, nil, nil)
-      end
-
-      def respond_to_missing?(symbol, include_private)
-        TYPE_CONVERSIONS.include?(symbol) && (return super)
-        symbol =~ variable_name || (return super)
-        true
-      end
-
-      private
-
-      def array_selection(array_index)
-        if @array_format == :unpacked
-          array_index.map { |i| "[#{i}]" }.join
-        else
-          "[#{@width}*(#{vector_index(array_index)})+:#{@width}]"
-        end
-      end
-
-      def vector_index(array_index)
-        index = []
-        array_index.zip(index_factors).reverse_each do |i, f|
-          index << ((index.size.zero? && i.to_s) || "#{f}*#{i}")
-        end
-        index.reverse.join('+')
-      end
-
-      def index_factors
-        factors = []
-        @array_dimensions.reverse.inject(1) do |elements, dimension|
-          factors.unshift(elements)
-          elements * dimension
-        end
-        factors
-      end
-    end
-  end
-end