rggen 0.8.2 → 0.9.0

data/lib/rggen/builtins/bit_field/types/reserved.rb

@@ -1,18 +0,0 @@
-list_item :bit_field, :type, :reserved  do
-  register_map do
-    reserved
-  end
-
-  rtl do
-    generate_code_from_template :bit_field
-
-    def default_value
-      hex(0, width)
-    end
-  end
-
-  ral do
-    access :ro
-    hdl_path { "g_#{bit_field.name}.u_bit_field.i_value" }
-  end
-end

data/lib/rggen/builtins/bit_field/types/ro.erb

@@ -1,6 +0,0 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
-) u_bit_field (
-  .bit_field_if (<%= bit_field_sub_if %>),
-  .i_value      (<%= value_in[loop_variables] %>)
-);

data/lib/rggen/builtins/bit_field/types/ro.rb

@@ -1,22 +0,0 @@
-list_item :bit_field, :type, :ro do
-  register_map do
-    read_only
-  end
-
-  rtl do
-    build do
-      input :register_block, :value_in,
-            name:         "i_#{bit_field.name}",
-            data_type:    :logic,
-            width:        width,
-            dimensions:   dimensions,
-            array_format: array_port_format
-    end
-
-    generate_code_from_template :bit_field
-  end
-
-  ral do
-    hdl_path { "g_#{bit_field.name}.u_bit_field.i_value" }
-  end
-end

data/lib/rggen/builtins/bit_field/types/rw.erb

@@ -1,9 +0,0 @@
-rggen_bit_field_rw #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .clk          (<%= register_block.clock %>),
-  .rst_n        (<%= register_block.reset %>),
-  .bit_field_if (<%= bit_field_sub_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/builtins/bit_field/types/rw.rb

@@ -1,23 +0,0 @@
-list_item :bit_field, :type, :rw do
-  register_map do
-    read_write
-    need_initial_value
-  end
-
-  rtl do
-    build do
-      output :register_block, :value_out,
-             name:          "o_#{bit_field.name}",
-             data_type:     :logic,
-             width:         width,
-             dimensions:    dimensions,
-             array_format:  array_port_format
-    end
-
-    generate_code_from_template :bit_field
-
-    def initial_value
-      hex(bit_field.initial_value, bit_field.width)
-    end
-  end
-end

data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb

@@ -1,11 +0,0 @@
-rggen_bit_field_rwl_rwe #(
-  .MODE           (rggen_rtl_pkg::<%= mode %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .clk              (<%= register_block.clock %>),
-  .rst_n            (<%= register_block.reset %>),
-  .i_lock_or_enable (<%= lock_or_enable %>),
-  .bit_field_if     (<%= bit_field_sub_if %>),
-  .o_value          (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb

@@ -1,54 +0,0 @@
-list_item :bit_field, :type, [:rwl, :rwe] do
-  register_map do
-    read_write
-    need_initial_value
-    use_reference width: 1, required: true
-  end
-
-  rtl do
-    build do
-      output :register_block, :value_out,
-             name:          "o_#{bit_field.name}",
-             data_type:     :logic,
-             width:         width,
-             dimensions:    dimensions,
-             array_format:  array_port_format
-    end
-
-    generate_code_from_template :bit_field
-
-    def mode
-      {
-        rwl: :RGGEN_LOCK_MODE, rwe: :RGGEN_ENABLE_MODE
-      }[bit_field.type]
-    end
-
-    def initial_value
-      hex(bit_field.initial_value, width)
-    end
-
-    def lock_or_enable
-      mode_field.value
-    end
-
-    def mode_field
-      register_block.bit_fields.find_by(name: bit_field.reference.name)
-    end
-  end
-
-  ral do
-    model_name { "#{class_name}#(#{mode_register}, #{mode_field})" }
-
-    def class_name
-      "rggen_ral_field_#{bit_field.type}"
-    end
-
-    def mode_register
-      string(bit_field.reference.register.name)
-    end
-
-    def mode_field
-      string(bit_field.reference.name)
-    end
-  end
-end

data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb

@@ -1,12 +0,0 @@
-rggen_bit_field_w01s_w01c #(
-  .MODE             (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
-  .SET_CLEAR_VALUE  (<%= clear_value %>),
-  .WIDTH            (<%= width %>),
-  .INITIAL_VALUE    (<%= initial_value %>)
-) u_bit_field (
-  .clk            (<%= register_block.clock %>),
-  .rst_n          (<%= register_block.reset %>),
-  .i_set_or_clear (<%= set[loop_variables] %>),
-  .bit_field_if   (<%= bit_field_sub_if %>),
-  .o_value        (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb

@@ -1,33 +0,0 @@
-list_item :bit_field, :type, [:w0c, :w1c] do
-  register_map do
-    read_write
-    need_initial_value
-  end
-
-  rtl do
-    build do
-      input :register_block, :set,
-            name:         "i_#{name}_set",
-            data_type:    :logic,
-            width:        width,
-            dimensions:   dimensions,
-            array_format: array_port_format
-      output :register_block, :value_out,
-             name:          "o_#{name}",
-             data_type:     :logic,
-             width:         width,
-             dimensions:    dimensions,
-             array_format:  array_port_format
-    end
-
-    generate_code_from_template :bit_field
-
-    def initial_value
-      hex(bit_field.initial_value, width)
-    end
-
-    def clear_value
-      { w0c: 0, w1c: 1 }[type]
-    end
-  end
-end

data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb

@@ -1,12 +0,0 @@
-rggen_bit_field_w01s_w01c #(
-  .MODE             (rggen_rtl_pkg::RGGEN_SET_MODE),
-  .SET_CLEAR_VALUE  (<%= set_value %>),
-  .WIDTH            (<%= width %>),
-  .INITIAL_VALUE    (<%= initial_value %>)
-) u_bit_field (
-  .clk            (<%= register_block.clock %>),
-  .rst_n          (<%= register_block.reset %>),
-  .i_set_or_clear (<%= clear[loop_variables] %>),
-  .bit_field_if   (<%= bit_field_sub_if %>),
-  .o_value        (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb

@@ -1,33 +0,0 @@
-list_item :bit_field, :type, [:w0s, :w1s] do
-  register_map do
-    read_write
-    need_initial_value
-  end
-
-  rtl do
-    build do
-      output :register_block, :value_out,
-             name:          "o_#{name}",
-             data_type:     :logic,
-             width:         width,
-             dimensions:    dimensions,
-             array_format:  array_port_format
-       input :register_block, :clear,
-             name:          "i_#{name}_clear",
-             data_type:     :logic,
-             width:         width,
-             dimensions:    dimensions,
-             array_format:  array_port_format
-    end
-
-    generate_code_from_template :bit_field
-
-    def initial_value
-      hex(bit_field.initial_value, width)
-    end
-
-    def set_value
-      { w0s: 0, w1s: 1 }[type]
-    end
-  end
-end

data/lib/rggen/builtins/bit_field/types/wo.rb

@@ -1,5 +0,0 @@
-list_item :bit_field, :type, :wo do
-  register_map do
-    write_only
-  end
-end

data/lib/rggen/builtins/global/address_width.rb

@@ -1,17 +0,0 @@
-simple_item :global, :address_width do
-  configuration do
-    field :address_width, default: 32
-
-    build do |width|
-      begin
-        @address_width  = Integer(width)
-      rescue
-        error "invalid value for address width: #{width.inspect}"
-      end
-
-      unless @address_width.positive?
-        error "zero/negative address width is not allowed: #{@address_width}"
-      end
-    end
-  end
-end

data/lib/rggen/builtins/global/array_port_format.rb

@@ -1,15 +0,0 @@
-simple_item :global, :array_port_format do
-  configuration do
-    field :array_port_format, default: :unpacked
-
-    input_pattern /(unpacked|vectored)/i
-
-    build do |value|
-      pattern_matched? || (
-        error 'invalid array port format; ' \
-              "should be 'unpacked' or 'vectored': #{value.inspect}"
-      )
-      @array_port_format  = captures.first.downcase.to_sym
-    end
-  end
-end

data/lib/rggen/builtins/global/data_width.rb

@@ -1,20 +0,0 @@
-simple_item :global, :data_width do
-  configuration do
-    field :data_width, default: 32
-    field :byte_width do
-      data_width / 8
-    end
-
-    build do |width|
-      begin
-        @data_width = Integer(width)
-      rescue
-        error "invalid value for data width: #{width.inspect}"
-      end
-
-      unless @data_width >= 8 && @data_width.pow2?
-        error "under 8/non-power of 2 data width is not allowed: #{@data_width}"
-      end
-    end
-  end
-end

data/lib/rggen/builtins/global/unfold_sv_interface_port.rb

@@ -1,22 +0,0 @@
-simple_item :global, :unfold_sv_interface_port do
-  configuration do
-    field :unfold_sv_interface_port?, default: false
-
-    build do |value|
-      @unfold_sv_interface_port =
-        case value
-        when true, false
-          value
-        when /\Atrue|on|yes\z/i
-          true
-        when /\Afalse|nil|off|no\z/i
-          false
-        else
-          message =
-            'non boolean value; should be true/false/nil/on/off/yes/no: ' \
-            "#{value.inspect}"
-          error message
-        end
-    end
-  end
-end

data/lib/rggen/builtins/loaders/configuration/json_loader.rb

@@ -1,7 +0,0 @@
-loader :configuration, :json do
-  require 'json'
-
-  def load_file(file)
-    JSON.parse(File.read(file))
-  end
-end

data/lib/rggen/builtins/loaders/configuration/yaml_loader.rb

@@ -1,7 +0,0 @@
-loader :configuration, [:yml, :yaml] do
-  require 'yaml'
-
-  def load_file(file)
-    YAML.load_file(file)
-  end
-end

data/lib/rggen/builtins/loaders/register_map/csv_loader.rb

@@ -1,12 +0,0 @@
-loader :register_map, [:csv, :tsv] do
-  def load_file(file)
-    create_map(file) do |map|
-      sheet_name      = File.basename(file, '.*')
-      map[sheet_name] = CSV.read(file, col_sep: separator(file))
-    end
-  end
-
-  def separator(file)
-    { 'csv' => ',', 'tsv' => "\t" }[File.ext(file).downcase]
-  end
-end

data/lib/rggen/builtins/loaders/register_map/xls_loader.rb

@@ -1,17 +0,0 @@
-loader :register_map, :xls do
-  def load_file(file)
-    create_map(file) do |map|
-      load_spreadsheet(file).each do |worksheet|
-        map[worksheet.name] = worksheet.rows
-      end
-    end
-  end
-
-  def load_spreadsheet(file)
-    Spreadsheet.open(file, 'rb') do |book|
-      book.worksheets.select do |worksheet|
-        worksheet.row_count > 0
-      end
-    end
-  end
-end

data/lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb

@@ -1,21 +0,0 @@
-loader :register_map, [:xlsx, :ods] do
-  def load_file(file)
-    create_map(file) do |map|
-      load_spreadsheet(file).each do |sheet_name, sheet|
-        map[sheet_name] = sheet
-      end
-    end
-  end
-
-  def load_spreadsheet(file)
-    sheets  = {}
-    Roo::Spreadsheet.open(file).each_with_pagename do |sheet_name, sheet|
-      sheet.first_row && (sheets[sheet_name] = process_sheet(sheet))
-    end
-    sheets
-  end
-
-  def process_sheet(sheet)
-    sheet.to_table(from_column: 1)
-  end
-end

data/lib/rggen/builtins/register/array.rb

@@ -1,30 +0,0 @@
-simple_item :register, :array do
-  register_map do
-    field :array?
-    field :dimensions
-    field :count
-
-    input_pattern %r{\[(#{number}(?:,#{number})*)\]},
-                  match_automatically: false
-
-    build do |cell|
-      @dimensions = parse_array_dimensions(cell)
-      @array      = @dimensions.not_nil?
-      @count      = (@dimensions && @dimensions.inject(&:*)) || 1
-      if @dimensions && @dimensions.any?(&:zero?)
-        error "0 is not allowed for array dimension: #{cell.inspect}"
-      end
-    end
-
-    def parse_array_dimensions(cell)
-      case
-      when cell.nil? || cell.empty?
-        nil
-      when pattern_match(cell)
-        captures.first.split(',').map(&method(:Integer))
-      else
-        error "invalid value for array dimension: #{cell.inspect}"
-      end
-    end
-  end
-end