hexcore-capstone 1.2.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (332) hide show
  1. package/LICENSE +26 -0
  2. package/README.md +191 -0
  3. package/binding.gyp +168 -0
  4. package/deps/capstone/LEB128.h +38 -0
  5. package/deps/capstone/MCDisassembler.h +14 -0
  6. package/deps/capstone/MCFixedLenDisassembler.h +32 -0
  7. package/deps/capstone/MCInst.c +270 -0
  8. package/deps/capstone/MCInst.h +165 -0
  9. package/deps/capstone/MCInstrDesc.c +41 -0
  10. package/deps/capstone/MCInstrDesc.h +167 -0
  11. package/deps/capstone/MCRegisterInfo.c +151 -0
  12. package/deps/capstone/MCRegisterInfo.h +116 -0
  13. package/deps/capstone/Mapping.c +254 -0
  14. package/deps/capstone/Mapping.h +174 -0
  15. package/deps/capstone/MathExtras.h +442 -0
  16. package/deps/capstone/SStream.c +181 -0
  17. package/deps/capstone/SStream.h +40 -0
  18. package/deps/capstone/arch/AArch64/AArch64AddressingModes.h +945 -0
  19. package/deps/capstone/arch/AArch64/AArch64BaseInfo.c +77 -0
  20. package/deps/capstone/arch/AArch64/AArch64BaseInfo.h +585 -0
  21. package/deps/capstone/arch/AArch64/AArch64Disassembler.c +2280 -0
  22. package/deps/capstone/arch/AArch64/AArch64Disassembler.h +18 -0
  23. package/deps/capstone/arch/AArch64/AArch64GenAsmWriter.inc +26589 -0
  24. package/deps/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc +27322 -0
  25. package/deps/capstone/arch/AArch64/AArch64GenInstrInfo.inc +13194 -0
  26. package/deps/capstone/arch/AArch64/AArch64GenRegisterInfo.inc +3814 -0
  27. package/deps/capstone/arch/AArch64/AArch64GenRegisterName.inc +714 -0
  28. package/deps/capstone/arch/AArch64/AArch64GenRegisterV.inc +673 -0
  29. package/deps/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc +229 -0
  30. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands.inc +2863 -0
  31. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands_enum.inc +21 -0
  32. package/deps/capstone/arch/AArch64/AArch64InstPrinter.c +3029 -0
  33. package/deps/capstone/arch/AArch64/AArch64InstPrinter.h +28 -0
  34. package/deps/capstone/arch/AArch64/AArch64Mapping.c +883 -0
  35. package/deps/capstone/arch/AArch64/AArch64Mapping.h +43 -0
  36. package/deps/capstone/arch/AArch64/AArch64MappingInsn.inc +37790 -0
  37. package/deps/capstone/arch/AArch64/AArch64MappingInsnName.inc +1282 -0
  38. package/deps/capstone/arch/AArch64/AArch64MappingInsnOp.inc +26994 -0
  39. package/deps/capstone/arch/AArch64/AArch64Module.c +44 -0
  40. package/deps/capstone/arch/AArch64/AArch64Module.h +12 -0
  41. package/deps/capstone/arch/ARM/ARMAddressingModes.h +698 -0
  42. package/deps/capstone/arch/ARM/ARMBaseInfo.h +486 -0
  43. package/deps/capstone/arch/ARM/ARMDisassembler.c +5763 -0
  44. package/deps/capstone/arch/ARM/ARMDisassembler.h +18 -0
  45. package/deps/capstone/arch/ARM/ARMGenAsmWriter.inc +9545 -0
  46. package/deps/capstone/arch/ARM/ARMGenDisassemblerTables.inc +15185 -0
  47. package/deps/capstone/arch/ARM/ARMGenInstrInfo.inc +6632 -0
  48. package/deps/capstone/arch/ARM/ARMGenRegisterInfo.inc +2102 -0
  49. package/deps/capstone/arch/ARM/ARMGenRegisterName.inc +231 -0
  50. package/deps/capstone/arch/ARM/ARMGenRegisterName_digit.inc +231 -0
  51. package/deps/capstone/arch/ARM/ARMGenSubtargetInfo.inc +162 -0
  52. package/deps/capstone/arch/ARM/ARMGenSystemRegister.inc +270 -0
  53. package/deps/capstone/arch/ARM/ARMInstPrinter.c +3364 -0
  54. package/deps/capstone/arch/ARM/ARMInstPrinter.h +43 -0
  55. package/deps/capstone/arch/ARM/ARMMapping.c +551 -0
  56. package/deps/capstone/arch/ARM/ARMMapping.h +40 -0
  57. package/deps/capstone/arch/ARM/ARMMappingInsn.inc +18772 -0
  58. package/deps/capstone/arch/ARM/ARMMappingInsnName.inc +475 -0
  59. package/deps/capstone/arch/ARM/ARMMappingInsnOp.inc +10729 -0
  60. package/deps/capstone/arch/ARM/ARMModule.c +63 -0
  61. package/deps/capstone/arch/ARM/ARMModule.h +12 -0
  62. package/deps/capstone/arch/BPF/BPFConstants.h +88 -0
  63. package/deps/capstone/arch/BPF/BPFDisassembler.c +464 -0
  64. package/deps/capstone/arch/BPF/BPFDisassembler.h +27 -0
  65. package/deps/capstone/arch/BPF/BPFInstPrinter.c +285 -0
  66. package/deps/capstone/arch/BPF/BPFInstPrinter.h +16 -0
  67. package/deps/capstone/arch/BPF/BPFMapping.c +513 -0
  68. package/deps/capstone/arch/BPF/BPFMapping.h +21 -0
  69. package/deps/capstone/arch/BPF/BPFModule.c +34 -0
  70. package/deps/capstone/arch/BPF/BPFModule.h +12 -0
  71. package/deps/capstone/arch/EVM/EVMDisassembler.c +379 -0
  72. package/deps/capstone/arch/EVM/EVMDisassembler.h +12 -0
  73. package/deps/capstone/arch/EVM/EVMInstPrinter.c +20 -0
  74. package/deps/capstone/arch/EVM/EVMInstPrinter.h +17 -0
  75. package/deps/capstone/arch/EVM/EVMMapping.c +344 -0
  76. package/deps/capstone/arch/EVM/EVMMapping.h +8 -0
  77. package/deps/capstone/arch/EVM/EVMMappingInsn.inc +259 -0
  78. package/deps/capstone/arch/EVM/EVMModule.c +33 -0
  79. package/deps/capstone/arch/EVM/EVMModule.h +12 -0
  80. package/deps/capstone/arch/M680X/M680XDisassembler.c +2307 -0
  81. package/deps/capstone/arch/M680X/M680XDisassembler.h +17 -0
  82. package/deps/capstone/arch/M680X/M680XDisassemblerInternals.h +57 -0
  83. package/deps/capstone/arch/M680X/M680XInstPrinter.c +360 -0
  84. package/deps/capstone/arch/M680X/M680XInstPrinter.h +25 -0
  85. package/deps/capstone/arch/M680X/M680XModule.c +77 -0
  86. package/deps/capstone/arch/M680X/M680XModule.h +12 -0
  87. package/deps/capstone/arch/M680X/cpu12.inc +335 -0
  88. package/deps/capstone/arch/M680X/hcs08.inc +60 -0
  89. package/deps/capstone/arch/M680X/hd6301.inc +15 -0
  90. package/deps/capstone/arch/M680X/hd6309.inc +259 -0
  91. package/deps/capstone/arch/M680X/insn_props.inc +367 -0
  92. package/deps/capstone/arch/M680X/m6800.inc +277 -0
  93. package/deps/capstone/arch/M680X/m6801.inc +39 -0
  94. package/deps/capstone/arch/M680X/m6805.inc +277 -0
  95. package/deps/capstone/arch/M680X/m6808.inc +91 -0
  96. package/deps/capstone/arch/M680X/m6809.inc +352 -0
  97. package/deps/capstone/arch/M680X/m6811.inc +105 -0
  98. package/deps/capstone/arch/M68K/M68KDisassembler.c +3668 -0
  99. package/deps/capstone/arch/M68K/M68KDisassembler.h +30 -0
  100. package/deps/capstone/arch/M68K/M68KInstPrinter.c +387 -0
  101. package/deps/capstone/arch/M68K/M68KInstPrinter.h +21 -0
  102. package/deps/capstone/arch/M68K/M68KInstructionTable.inc +65540 -0
  103. package/deps/capstone/arch/M68K/M68KModule.c +42 -0
  104. package/deps/capstone/arch/M68K/M68KModule.h +12 -0
  105. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.c +544 -0
  106. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.h +22 -0
  107. package/deps/capstone/arch/MOS65XX/MOS65XXDisassemblerInternals.h +23 -0
  108. package/deps/capstone/arch/MOS65XX/MOS65XXModule.c +79 -0
  109. package/deps/capstone/arch/MOS65XX/MOS65XXModule.h +12 -0
  110. package/deps/capstone/arch/MOS65XX/instruction_info.inc +106 -0
  111. package/deps/capstone/arch/MOS65XX/m6502.inc +256 -0
  112. package/deps/capstone/arch/MOS65XX/m65816.inc +256 -0
  113. package/deps/capstone/arch/MOS65XX/m65c02.inc +256 -0
  114. package/deps/capstone/arch/MOS65XX/mw65c02.inc +256 -0
  115. package/deps/capstone/arch/Mips/MipsDisassembler.c +1794 -0
  116. package/deps/capstone/arch/Mips/MipsDisassembler.h +16 -0
  117. package/deps/capstone/arch/Mips/MipsGenAsmWriter.inc +5725 -0
  118. package/deps/capstone/arch/Mips/MipsGenDisassemblerTables.inc +6942 -0
  119. package/deps/capstone/arch/Mips/MipsGenInstrInfo.inc +1805 -0
  120. package/deps/capstone/arch/Mips/MipsGenRegisterInfo.inc +1679 -0
  121. package/deps/capstone/arch/Mips/MipsGenSubtargetInfo.inc +52 -0
  122. package/deps/capstone/arch/Mips/MipsInstPrinter.c +424 -0
  123. package/deps/capstone/arch/Mips/MipsInstPrinter.h +25 -0
  124. package/deps/capstone/arch/Mips/MipsMapping.c +1070 -0
  125. package/deps/capstone/arch/Mips/MipsMapping.h +25 -0
  126. package/deps/capstone/arch/Mips/MipsMappingInsn.inc +9315 -0
  127. package/deps/capstone/arch/Mips/MipsModule.c +52 -0
  128. package/deps/capstone/arch/Mips/MipsModule.h +12 -0
  129. package/deps/capstone/arch/PowerPC/PPCDisassembler.c +627 -0
  130. package/deps/capstone/arch/PowerPC/PPCDisassembler.h +17 -0
  131. package/deps/capstone/arch/PowerPC/PPCGenAsmWriter.inc +11451 -0
  132. package/deps/capstone/arch/PowerPC/PPCGenDisassemblerTables.inc +6886 -0
  133. package/deps/capstone/arch/PowerPC/PPCGenInstrInfo.inc +4772 -0
  134. package/deps/capstone/arch/PowerPC/PPCGenRegisterInfo.inc +1122 -0
  135. package/deps/capstone/arch/PowerPC/PPCGenRegisterName.inc +278 -0
  136. package/deps/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc +90 -0
  137. package/deps/capstone/arch/PowerPC/PPCInstPrinter.c +1238 -0
  138. package/deps/capstone/arch/PowerPC/PPCInstPrinter.h +15 -0
  139. package/deps/capstone/arch/PowerPC/PPCMapping.c +570 -0
  140. package/deps/capstone/arch/PowerPC/PPCMapping.h +40 -0
  141. package/deps/capstone/arch/PowerPC/PPCMappingInsn.inc +13220 -0
  142. package/deps/capstone/arch/PowerPC/PPCMappingInsnName.inc +1731 -0
  143. package/deps/capstone/arch/PowerPC/PPCModule.c +45 -0
  144. package/deps/capstone/arch/PowerPC/PPCModule.h +12 -0
  145. package/deps/capstone/arch/PowerPC/PPCPredicates.h +62 -0
  146. package/deps/capstone/arch/RISCV/RISCVBaseInfo.h +106 -0
  147. package/deps/capstone/arch/RISCV/RISCVDisassembler.c +433 -0
  148. package/deps/capstone/arch/RISCV/RISCVDisassembler.h +18 -0
  149. package/deps/capstone/arch/RISCV/RISCVGenAsmWriter.inc +2651 -0
  150. package/deps/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc +1776 -0
  151. package/deps/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc +275 -0
  152. package/deps/capstone/arch/RISCV/RISCVGenInstrInfo.inc +470 -0
  153. package/deps/capstone/arch/RISCV/RISCVGenRegisterInfo.inc +426 -0
  154. package/deps/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc +33 -0
  155. package/deps/capstone/arch/RISCV/RISCVInstPrinter.c +447 -0
  156. package/deps/capstone/arch/RISCV/RISCVInstPrinter.h +24 -0
  157. package/deps/capstone/arch/RISCV/RISCVMapping.c +366 -0
  158. package/deps/capstone/arch/RISCV/RISCVMapping.h +22 -0
  159. package/deps/capstone/arch/RISCV/RISCVMappingInsn.inc +1635 -0
  160. package/deps/capstone/arch/RISCV/RISCVModule.c +42 -0
  161. package/deps/capstone/arch/RISCV/RISCVModule.h +12 -0
  162. package/deps/capstone/arch/SH/SHDisassembler.c +2221 -0
  163. package/deps/capstone/arch/SH/SHDisassembler.h +19 -0
  164. package/deps/capstone/arch/SH/SHInsnTable.inc +66 -0
  165. package/deps/capstone/arch/SH/SHInstPrinter.c +438 -0
  166. package/deps/capstone/arch/SH/SHInstPrinter.h +23 -0
  167. package/deps/capstone/arch/SH/SHModule.c +39 -0
  168. package/deps/capstone/arch/SH/SHModule.h +12 -0
  169. package/deps/capstone/arch/SH/mktable.rb +390 -0
  170. package/deps/capstone/arch/Sparc/Sparc.h +63 -0
  171. package/deps/capstone/arch/Sparc/SparcDisassembler.c +500 -0
  172. package/deps/capstone/arch/Sparc/SparcDisassembler.h +17 -0
  173. package/deps/capstone/arch/Sparc/SparcGenAsmWriter.inc +5709 -0
  174. package/deps/capstone/arch/Sparc/SparcGenDisassemblerTables.inc +2028 -0
  175. package/deps/capstone/arch/Sparc/SparcGenInstrInfo.inc +514 -0
  176. package/deps/capstone/arch/Sparc/SparcGenRegisterInfo.inc +451 -0
  177. package/deps/capstone/arch/Sparc/SparcGenSubtargetInfo.inc +27 -0
  178. package/deps/capstone/arch/Sparc/SparcInstPrinter.c +446 -0
  179. package/deps/capstone/arch/Sparc/SparcInstPrinter.h +17 -0
  180. package/deps/capstone/arch/Sparc/SparcMapping.c +665 -0
  181. package/deps/capstone/arch/Sparc/SparcMapping.h +34 -0
  182. package/deps/capstone/arch/Sparc/SparcMappingInsn.inc +2643 -0
  183. package/deps/capstone/arch/Sparc/SparcModule.c +45 -0
  184. package/deps/capstone/arch/Sparc/SparcModule.h +12 -0
  185. package/deps/capstone/arch/SystemZ/SystemZDisassembler.c +484 -0
  186. package/deps/capstone/arch/SystemZ/SystemZDisassembler.h +17 -0
  187. package/deps/capstone/arch/SystemZ/SystemZGenAsmWriter.inc +11575 -0
  188. package/deps/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc +10262 -0
  189. package/deps/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc +2348 -0
  190. package/deps/capstone/arch/SystemZ/SystemZGenInstrInfo.inc +2820 -0
  191. package/deps/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc +741 -0
  192. package/deps/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc +49 -0
  193. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.c +433 -0
  194. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.h +15 -0
  195. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.c +195 -0
  196. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.h +51 -0
  197. package/deps/capstone/arch/SystemZ/SystemZMapping.c +479 -0
  198. package/deps/capstone/arch/SystemZ/SystemZMapping.h +23 -0
  199. package/deps/capstone/arch/SystemZ/SystemZMappingInsn.inc +14175 -0
  200. package/deps/capstone/arch/SystemZ/SystemZModule.c +44 -0
  201. package/deps/capstone/arch/SystemZ/SystemZModule.h +12 -0
  202. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c +628 -0
  203. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h +19 -0
  204. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +684 -0
  205. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc +1352 -0
  206. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc +298 -0
  207. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc +277 -0
  208. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c +572 -0
  209. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h +15 -0
  210. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.c +1926 -0
  211. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.h +26 -0
  212. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.c +39 -0
  213. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.h +12 -0
  214. package/deps/capstone/arch/TriCore/TriCore.td +134 -0
  215. package/deps/capstone/arch/TriCore/TriCoreCallingConv.td +61 -0
  216. package/deps/capstone/arch/TriCore/TriCoreDisassembler.c +1655 -0
  217. package/deps/capstone/arch/TriCore/TriCoreDisassembler.h +18 -0
  218. package/deps/capstone/arch/TriCore/TriCoreGenAsmWriter.inc +3691 -0
  219. package/deps/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc +22 -0
  220. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc +8938 -0
  221. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc +404 -0
  222. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc +7994 -0
  223. package/deps/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc +32 -0
  224. package/deps/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc +4044 -0
  225. package/deps/capstone/arch/TriCore/TriCoreGenInstrInfo.inc +2693 -0
  226. package/deps/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc +295 -0
  227. package/deps/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc +40 -0
  228. package/deps/capstone/arch/TriCore/TriCoreInstPrinter.c +488 -0
  229. package/deps/capstone/arch/TriCore/TriCoreInstrFormats.td +773 -0
  230. package/deps/capstone/arch/TriCore/TriCoreInstrInfo.td +1873 -0
  231. package/deps/capstone/arch/TriCore/TriCoreLinkage.h +21 -0
  232. package/deps/capstone/arch/TriCore/TriCoreMapping.c +241 -0
  233. package/deps/capstone/arch/TriCore/TriCoreMapping.h +32 -0
  234. package/deps/capstone/arch/TriCore/TriCoreModule.c +44 -0
  235. package/deps/capstone/arch/TriCore/TriCoreModule.h +11 -0
  236. package/deps/capstone/arch/TriCore/TriCoreRegisterInfo.td +153 -0
  237. package/deps/capstone/arch/WASM/WASMDisassembler.c +1009 -0
  238. package/deps/capstone/arch/WASM/WASMDisassembler.h +12 -0
  239. package/deps/capstone/arch/WASM/WASMInstPrinter.c +47 -0
  240. package/deps/capstone/arch/WASM/WASMInstPrinter.h +18 -0
  241. package/deps/capstone/arch/WASM/WASMMapping.c +333 -0
  242. package/deps/capstone/arch/WASM/WASMMapping.h +9 -0
  243. package/deps/capstone/arch/WASM/WASMModule.c +33 -0
  244. package/deps/capstone/arch/WASM/WASMModule.h +12 -0
  245. package/deps/capstone/arch/X86/X86ATTInstPrinter.c +997 -0
  246. package/deps/capstone/arch/X86/X86BaseInfo.h +50 -0
  247. package/deps/capstone/arch/X86/X86Disassembler.c +1033 -0
  248. package/deps/capstone/arch/X86/X86Disassembler.h +28 -0
  249. package/deps/capstone/arch/X86/X86DisassemblerDecoder.c +2358 -0
  250. package/deps/capstone/arch/X86/X86DisassemblerDecoder.h +725 -0
  251. package/deps/capstone/arch/X86/X86DisassemblerDecoderCommon.h +483 -0
  252. package/deps/capstone/arch/X86/X86GenAsmWriter.inc +49199 -0
  253. package/deps/capstone/arch/X86/X86GenAsmWriter1.inc +33196 -0
  254. package/deps/capstone/arch/X86/X86GenAsmWriter1_reduce.inc +2531 -0
  255. package/deps/capstone/arch/X86/X86GenAsmWriter_reduce.inc +2855 -0
  256. package/deps/capstone/arch/X86/X86GenDisassemblerTables.inc +112961 -0
  257. package/deps/capstone/arch/X86/X86GenDisassemblerTables2.inc +102151 -0
  258. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc +28047 -0
  259. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc +18827 -0
  260. package/deps/capstone/arch/X86/X86GenInstrInfo.inc +15158 -0
  261. package/deps/capstone/arch/X86/X86GenInstrInfo_reduce.inc +1564 -0
  262. package/deps/capstone/arch/X86/X86GenRegisterInfo.inc +1549 -0
  263. package/deps/capstone/arch/X86/X86GenRegisterName.inc +292 -0
  264. package/deps/capstone/arch/X86/X86GenRegisterName1.inc +291 -0
  265. package/deps/capstone/arch/X86/X86ImmSize.inc +335 -0
  266. package/deps/capstone/arch/X86/X86InstPrinter.h +26 -0
  267. package/deps/capstone/arch/X86/X86InstPrinterCommon.c +116 -0
  268. package/deps/capstone/arch/X86/X86InstPrinterCommon.h +16 -0
  269. package/deps/capstone/arch/X86/X86IntelInstPrinter.c +1061 -0
  270. package/deps/capstone/arch/X86/X86Lookup16.inc +16874 -0
  271. package/deps/capstone/arch/X86/X86Lookup16_reduce.inc +2308 -0
  272. package/deps/capstone/arch/X86/X86Mapping.c +2266 -0
  273. package/deps/capstone/arch/X86/X86Mapping.h +96 -0
  274. package/deps/capstone/arch/X86/X86MappingInsn.inc +105977 -0
  275. package/deps/capstone/arch/X86/X86MappingInsnName.inc +1527 -0
  276. package/deps/capstone/arch/X86/X86MappingInsnName_reduce.inc +348 -0
  277. package/deps/capstone/arch/X86/X86MappingInsnOp.inc +75700 -0
  278. package/deps/capstone/arch/X86/X86MappingInsnOp_reduce.inc +7729 -0
  279. package/deps/capstone/arch/X86/X86MappingInsn_reduce.inc +10819 -0
  280. package/deps/capstone/arch/X86/X86MappingReg.inc +280 -0
  281. package/deps/capstone/arch/X86/X86Module.c +94 -0
  282. package/deps/capstone/arch/X86/X86Module.h +12 -0
  283. package/deps/capstone/arch/XCore/XCoreDisassembler.c +794 -0
  284. package/deps/capstone/arch/XCore/XCoreDisassembler.h +17 -0
  285. package/deps/capstone/arch/XCore/XCoreGenAsmWriter.inc +772 -0
  286. package/deps/capstone/arch/XCore/XCoreGenDisassemblerTables.inc +853 -0
  287. package/deps/capstone/arch/XCore/XCoreGenInstrInfo.inc +267 -0
  288. package/deps/capstone/arch/XCore/XCoreGenRegisterInfo.inc +110 -0
  289. package/deps/capstone/arch/XCore/XCoreInstPrinter.c +250 -0
  290. package/deps/capstone/arch/XCore/XCoreInstPrinter.h +18 -0
  291. package/deps/capstone/arch/XCore/XCoreMapping.c +297 -0
  292. package/deps/capstone/arch/XCore/XCoreMapping.h +26 -0
  293. package/deps/capstone/arch/XCore/XCoreMappingInsn.inc +1287 -0
  294. package/deps/capstone/arch/XCore/XCoreModule.c +41 -0
  295. package/deps/capstone/arch/XCore/XCoreModule.h +12 -0
  296. package/deps/capstone/cs.c +1664 -0
  297. package/deps/capstone/cs_priv.h +101 -0
  298. package/deps/capstone/cs_simple_types.h +886 -0
  299. package/deps/capstone/include/capstone/arm.h +991 -0
  300. package/deps/capstone/include/capstone/arm64.h +3159 -0
  301. package/deps/capstone/include/capstone/bpf.h +209 -0
  302. package/deps/capstone/include/capstone/capstone.h +875 -0
  303. package/deps/capstone/include/capstone/evm.h +188 -0
  304. package/deps/capstone/include/capstone/m680x.h +537 -0
  305. package/deps/capstone/include/capstone/m68k.h +613 -0
  306. package/deps/capstone/include/capstone/mips.h +956 -0
  307. package/deps/capstone/include/capstone/mos65xx.h +204 -0
  308. package/deps/capstone/include/capstone/platform.h +122 -0
  309. package/deps/capstone/include/capstone/ppc.h +2108 -0
  310. package/deps/capstone/include/capstone/riscv.h +531 -0
  311. package/deps/capstone/include/capstone/sh.h +465 -0
  312. package/deps/capstone/include/capstone/sparc.h +520 -0
  313. package/deps/capstone/include/capstone/systemz.h +2601 -0
  314. package/deps/capstone/include/capstone/tms320c64x.h +359 -0
  315. package/deps/capstone/include/capstone/tricore.h +567 -0
  316. package/deps/capstone/include/capstone/wasm.h +250 -0
  317. package/deps/capstone/include/capstone/x86.h +1986 -0
  318. package/deps/capstone/include/capstone/xcore.h +235 -0
  319. package/deps/capstone/include/platform.h +110 -0
  320. package/deps/capstone/include/windowsce/intrin.h +12 -0
  321. package/deps/capstone/include/windowsce/stdint.h +133 -0
  322. package/deps/capstone/utils.c +140 -0
  323. package/deps/capstone/utils.h +54 -0
  324. package/index.d.ts +448 -0
  325. package/index.js +64 -0
  326. package/index.mjs +25 -0
  327. package/package.json +82 -0
  328. package/prebuilds/win32-x64/hexcore-capstone.node +0 -0
  329. package/src/capstone_wrapper.cpp +910 -0
  330. package/src/capstone_wrapper.h +147 -0
  331. package/src/disasm_async_worker.h +215 -0
  332. package/src/main.cpp +145 -0
@@ -0,0 +1,2643 @@
1
+ // This is auto-gen data for Capstone engine (www.capstone-engine.org)
2
+ // By Nguyen Anh Quynh <aquynh@gmail.com>
3
+
4
+ {
5
+ SP_ADDCCri, SPARC_INS_ADDCC,
6
+ #ifndef CAPSTONE_DIET
7
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
8
+ #endif
9
+ },
10
+ {
11
+ SP_ADDCCrr, SPARC_INS_ADDCC,
12
+ #ifndef CAPSTONE_DIET
13
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
14
+ #endif
15
+ },
16
+ {
17
+ SP_ADDCri, SPARC_INS_ADDX,
18
+ #ifndef CAPSTONE_DIET
19
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
20
+ #endif
21
+ },
22
+ {
23
+ SP_ADDCrr, SPARC_INS_ADDX,
24
+ #ifndef CAPSTONE_DIET
25
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
26
+ #endif
27
+ },
28
+ {
29
+ SP_ADDEri, SPARC_INS_ADDXCC,
30
+ #ifndef CAPSTONE_DIET
31
+ { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
32
+ #endif
33
+ },
34
+ {
35
+ SP_ADDErr, SPARC_INS_ADDXCC,
36
+ #ifndef CAPSTONE_DIET
37
+ { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
38
+ #endif
39
+ },
40
+ {
41
+ SP_ADDXC, SPARC_INS_ADDXC,
42
+ #ifndef CAPSTONE_DIET
43
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
44
+ #endif
45
+ },
46
+ {
47
+ SP_ADDXCCC, SPARC_INS_ADDXCCC,
48
+ #ifndef CAPSTONE_DIET
49
+ { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
50
+ #endif
51
+ },
52
+ {
53
+ SP_ADDXri, SPARC_INS_ADD,
54
+ #ifndef CAPSTONE_DIET
55
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
56
+ #endif
57
+ },
58
+ {
59
+ SP_ADDXrr, SPARC_INS_ADD,
60
+ #ifndef CAPSTONE_DIET
61
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
62
+ #endif
63
+ },
64
+ {
65
+ SP_ADDri, SPARC_INS_ADD,
66
+ #ifndef CAPSTONE_DIET
67
+ { 0 }, { 0 }, { 0 }, 0, 0
68
+ #endif
69
+ },
70
+ {
71
+ SP_ADDrr, SPARC_INS_ADD,
72
+ #ifndef CAPSTONE_DIET
73
+ { 0 }, { 0 }, { 0 }, 0, 0
74
+ #endif
75
+ },
76
+ {
77
+ SP_ALIGNADDR, SPARC_INS_ALIGNADDR,
78
+ #ifndef CAPSTONE_DIET
79
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
80
+ #endif
81
+ },
82
+ {
83
+ SP_ALIGNADDRL, SPARC_INS_ALIGNADDRL,
84
+ #ifndef CAPSTONE_DIET
85
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
86
+ #endif
87
+ },
88
+ {
89
+ SP_ANDCCri, SPARC_INS_ANDCC,
90
+ #ifndef CAPSTONE_DIET
91
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
92
+ #endif
93
+ },
94
+ {
95
+ SP_ANDCCrr, SPARC_INS_ANDCC,
96
+ #ifndef CAPSTONE_DIET
97
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
98
+ #endif
99
+ },
100
+ {
101
+ SP_ANDNCCri, SPARC_INS_ANDNCC,
102
+ #ifndef CAPSTONE_DIET
103
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
104
+ #endif
105
+ },
106
+ {
107
+ SP_ANDNCCrr, SPARC_INS_ANDNCC,
108
+ #ifndef CAPSTONE_DIET
109
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
110
+ #endif
111
+ },
112
+ {
113
+ SP_ANDNri, SPARC_INS_ANDN,
114
+ #ifndef CAPSTONE_DIET
115
+ { 0 }, { 0 }, { 0 }, 0, 0
116
+ #endif
117
+ },
118
+ {
119
+ SP_ANDNrr, SPARC_INS_ANDN,
120
+ #ifndef CAPSTONE_DIET
121
+ { 0 }, { 0 }, { 0 }, 0, 0
122
+ #endif
123
+ },
124
+ {
125
+ SP_ANDXNrr, SPARC_INS_ANDN,
126
+ #ifndef CAPSTONE_DIET
127
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
128
+ #endif
129
+ },
130
+ {
131
+ SP_ANDXri, SPARC_INS_AND,
132
+ #ifndef CAPSTONE_DIET
133
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
134
+ #endif
135
+ },
136
+ {
137
+ SP_ANDXrr, SPARC_INS_AND,
138
+ #ifndef CAPSTONE_DIET
139
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
140
+ #endif
141
+ },
142
+ {
143
+ SP_ANDri, SPARC_INS_AND,
144
+ #ifndef CAPSTONE_DIET
145
+ { 0 }, { 0 }, { 0 }, 0, 0
146
+ #endif
147
+ },
148
+ {
149
+ SP_ANDrr, SPARC_INS_AND,
150
+ #ifndef CAPSTONE_DIET
151
+ { 0 }, { 0 }, { 0 }, 0, 0
152
+ #endif
153
+ },
154
+ {
155
+ SP_ARRAY16, SPARC_INS_ARRAY16,
156
+ #ifndef CAPSTONE_DIET
157
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
158
+ #endif
159
+ },
160
+ {
161
+ SP_ARRAY32, SPARC_INS_ARRAY32,
162
+ #ifndef CAPSTONE_DIET
163
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
164
+ #endif
165
+ },
166
+ {
167
+ SP_ARRAY8, SPARC_INS_ARRAY8,
168
+ #ifndef CAPSTONE_DIET
169
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
170
+ #endif
171
+ },
172
+ {
173
+ SP_BA, SPARC_INS_B,
174
+ #ifndef CAPSTONE_DIET
175
+ { 0 }, { 0 }, { 0 }, 1, 0
176
+ #endif
177
+ },
178
+ {
179
+ SP_BCOND, SPARC_INS_B,
180
+ #ifndef CAPSTONE_DIET
181
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0
182
+ #endif
183
+ },
184
+ {
185
+ SP_BCONDA, SPARC_INS_B,
186
+ #ifndef CAPSTONE_DIET
187
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 1, 0
188
+ #endif
189
+ },
190
+ {
191
+ SP_BINDri, SPARC_INS_JMP,
192
+ #ifndef CAPSTONE_DIET
193
+ { 0 }, { 0 }, { 0 }, 1, 1
194
+ #endif
195
+ },
196
+ {
197
+ SP_BINDrr, SPARC_INS_JMP,
198
+ #ifndef CAPSTONE_DIET
199
+ { 0 }, { 0 }, { 0 }, 1, 1
200
+ #endif
201
+ },
202
+ {
203
+ SP_BMASK, SPARC_INS_BMASK,
204
+ #ifndef CAPSTONE_DIET
205
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
206
+ #endif
207
+ },
208
+ {
209
+ SP_BPFCC, SPARC_INS_FB,
210
+ #ifndef CAPSTONE_DIET
211
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
212
+ #endif
213
+ },
214
+ {
215
+ SP_BPFCCA, SPARC_INS_FB,
216
+ #ifndef CAPSTONE_DIET
217
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
218
+ #endif
219
+ },
220
+ {
221
+ SP_BPFCCANT, SPARC_INS_FB,
222
+ #ifndef CAPSTONE_DIET
223
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
224
+ #endif
225
+ },
226
+ {
227
+ SP_BPFCCNT, SPARC_INS_FB,
228
+ #ifndef CAPSTONE_DIET
229
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
230
+ #endif
231
+ },
232
+ {
233
+ SP_BPGEZapn, SPARC_INS_BRGEZ,
234
+ #ifndef CAPSTONE_DIET
235
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
236
+ #endif
237
+ },
238
+ {
239
+ SP_BPGEZapt, SPARC_INS_BRGEZ,
240
+ #ifndef CAPSTONE_DIET
241
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
242
+ #endif
243
+ },
244
+ {
245
+ SP_BPGEZnapn, SPARC_INS_BRGEZ,
246
+ #ifndef CAPSTONE_DIET
247
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
248
+ #endif
249
+ },
250
+ {
251
+ SP_BPGEZnapt, SPARC_INS_BRGEZ,
252
+ #ifndef CAPSTONE_DIET
253
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
254
+ #endif
255
+ },
256
+ {
257
+ SP_BPGZapn, SPARC_INS_BRGZ,
258
+ #ifndef CAPSTONE_DIET
259
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
260
+ #endif
261
+ },
262
+ {
263
+ SP_BPGZapt, SPARC_INS_BRGZ,
264
+ #ifndef CAPSTONE_DIET
265
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
266
+ #endif
267
+ },
268
+ {
269
+ SP_BPGZnapn, SPARC_INS_BRGZ,
270
+ #ifndef CAPSTONE_DIET
271
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
272
+ #endif
273
+ },
274
+ {
275
+ SP_BPGZnapt, SPARC_INS_BRGZ,
276
+ #ifndef CAPSTONE_DIET
277
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
278
+ #endif
279
+ },
280
+ {
281
+ SP_BPICC, SPARC_INS_B,
282
+ #ifndef CAPSTONE_DIET
283
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
284
+ #endif
285
+ },
286
+ {
287
+ SP_BPICCA, SPARC_INS_B,
288
+ #ifndef CAPSTONE_DIET
289
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
290
+ #endif
291
+ },
292
+ {
293
+ SP_BPICCANT, SPARC_INS_B,
294
+ #ifndef CAPSTONE_DIET
295
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
296
+ #endif
297
+ },
298
+ {
299
+ SP_BPICCNT, SPARC_INS_B,
300
+ #ifndef CAPSTONE_DIET
301
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 1, 0
302
+ #endif
303
+ },
304
+ {
305
+ SP_BPLEZapn, SPARC_INS_BRLEZ,
306
+ #ifndef CAPSTONE_DIET
307
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
308
+ #endif
309
+ },
310
+ {
311
+ SP_BPLEZapt, SPARC_INS_BRLEZ,
312
+ #ifndef CAPSTONE_DIET
313
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
314
+ #endif
315
+ },
316
+ {
317
+ SP_BPLEZnapn, SPARC_INS_BRLEZ,
318
+ #ifndef CAPSTONE_DIET
319
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
320
+ #endif
321
+ },
322
+ {
323
+ SP_BPLEZnapt, SPARC_INS_BRLEZ,
324
+ #ifndef CAPSTONE_DIET
325
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
326
+ #endif
327
+ },
328
+ {
329
+ SP_BPLZapn, SPARC_INS_BRLZ,
330
+ #ifndef CAPSTONE_DIET
331
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
332
+ #endif
333
+ },
334
+ {
335
+ SP_BPLZapt, SPARC_INS_BRLZ,
336
+ #ifndef CAPSTONE_DIET
337
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
338
+ #endif
339
+ },
340
+ {
341
+ SP_BPLZnapn, SPARC_INS_BRLZ,
342
+ #ifndef CAPSTONE_DIET
343
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
344
+ #endif
345
+ },
346
+ {
347
+ SP_BPLZnapt, SPARC_INS_BRLZ,
348
+ #ifndef CAPSTONE_DIET
349
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
350
+ #endif
351
+ },
352
+ {
353
+ SP_BPNZapn, SPARC_INS_BRNZ,
354
+ #ifndef CAPSTONE_DIET
355
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
356
+ #endif
357
+ },
358
+ {
359
+ SP_BPNZapt, SPARC_INS_BRNZ,
360
+ #ifndef CAPSTONE_DIET
361
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
362
+ #endif
363
+ },
364
+ {
365
+ SP_BPNZnapn, SPARC_INS_BRNZ,
366
+ #ifndef CAPSTONE_DIET
367
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
368
+ #endif
369
+ },
370
+ {
371
+ SP_BPNZnapt, SPARC_INS_BRNZ,
372
+ #ifndef CAPSTONE_DIET
373
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
374
+ #endif
375
+ },
376
+ {
377
+ SP_BPXCC, SPARC_INS_B,
378
+ #ifndef CAPSTONE_DIET
379
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
380
+ #endif
381
+ },
382
+ {
383
+ SP_BPXCCA, SPARC_INS_B,
384
+ #ifndef CAPSTONE_DIET
385
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
386
+ #endif
387
+ },
388
+ {
389
+ SP_BPXCCANT, SPARC_INS_B,
390
+ #ifndef CAPSTONE_DIET
391
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
392
+ #endif
393
+ },
394
+ {
395
+ SP_BPXCCNT, SPARC_INS_B,
396
+ #ifndef CAPSTONE_DIET
397
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
398
+ #endif
399
+ },
400
+ {
401
+ SP_BPZapn, SPARC_INS_BRZ,
402
+ #ifndef CAPSTONE_DIET
403
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
404
+ #endif
405
+ },
406
+ {
407
+ SP_BPZapt, SPARC_INS_BRZ,
408
+ #ifndef CAPSTONE_DIET
409
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
410
+ #endif
411
+ },
412
+ {
413
+ SP_BPZnapn, SPARC_INS_BRZ,
414
+ #ifndef CAPSTONE_DIET
415
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
416
+ #endif
417
+ },
418
+ {
419
+ SP_BPZnapt, SPARC_INS_BRZ,
420
+ #ifndef CAPSTONE_DIET
421
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 1, 0
422
+ #endif
423
+ },
424
+ {
425
+ SP_BSHUFFLE, SPARC_INS_BSHUFFLE,
426
+ #ifndef CAPSTONE_DIET
427
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
428
+ #endif
429
+ },
430
+ {
431
+ SP_CALL, SPARC_INS_CALL,
432
+ #ifndef CAPSTONE_DIET
433
+ { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0
434
+ #endif
435
+ },
436
+ {
437
+ SP_CALLri, SPARC_INS_CALL,
438
+ #ifndef CAPSTONE_DIET
439
+ { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0
440
+ #endif
441
+ },
442
+ {
443
+ SP_CALLrr, SPARC_INS_CALL,
444
+ #ifndef CAPSTONE_DIET
445
+ { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0
446
+ #endif
447
+ },
448
+ {
449
+ SP_CASXrr, SPARC_INS_CASX,
450
+ #ifndef CAPSTONE_DIET
451
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
452
+ #endif
453
+ },
454
+ {
455
+ SP_CASrr, SPARC_INS_CAS,
456
+ #ifndef CAPSTONE_DIET
457
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
458
+ #endif
459
+ },
460
+ {
461
+ SP_CMASK16, SPARC_INS_CMASK16,
462
+ #ifndef CAPSTONE_DIET
463
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
464
+ #endif
465
+ },
466
+ {
467
+ SP_CMASK32, SPARC_INS_CMASK32,
468
+ #ifndef CAPSTONE_DIET
469
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
470
+ #endif
471
+ },
472
+ {
473
+ SP_CMASK8, SPARC_INS_CMASK8,
474
+ #ifndef CAPSTONE_DIET
475
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
476
+ #endif
477
+ },
478
+ {
479
+ SP_CMPri, SPARC_INS_CMP,
480
+ #ifndef CAPSTONE_DIET
481
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
482
+ #endif
483
+ },
484
+ {
485
+ SP_CMPrr, SPARC_INS_CMP,
486
+ #ifndef CAPSTONE_DIET
487
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
488
+ #endif
489
+ },
490
+ {
491
+ SP_EDGE16, SPARC_INS_EDGE16,
492
+ #ifndef CAPSTONE_DIET
493
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
494
+ #endif
495
+ },
496
+ {
497
+ SP_EDGE16L, SPARC_INS_EDGE16L,
498
+ #ifndef CAPSTONE_DIET
499
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
500
+ #endif
501
+ },
502
+ {
503
+ SP_EDGE16LN, SPARC_INS_EDGE16LN,
504
+ #ifndef CAPSTONE_DIET
505
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
506
+ #endif
507
+ },
508
+ {
509
+ SP_EDGE16N, SPARC_INS_EDGE16N,
510
+ #ifndef CAPSTONE_DIET
511
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
512
+ #endif
513
+ },
514
+ {
515
+ SP_EDGE32, SPARC_INS_EDGE32,
516
+ #ifndef CAPSTONE_DIET
517
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
518
+ #endif
519
+ },
520
+ {
521
+ SP_EDGE32L, SPARC_INS_EDGE32L,
522
+ #ifndef CAPSTONE_DIET
523
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
524
+ #endif
525
+ },
526
+ {
527
+ SP_EDGE32LN, SPARC_INS_EDGE32LN,
528
+ #ifndef CAPSTONE_DIET
529
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
530
+ #endif
531
+ },
532
+ {
533
+ SP_EDGE32N, SPARC_INS_EDGE32N,
534
+ #ifndef CAPSTONE_DIET
535
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
536
+ #endif
537
+ },
538
+ {
539
+ SP_EDGE8, SPARC_INS_EDGE8,
540
+ #ifndef CAPSTONE_DIET
541
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
542
+ #endif
543
+ },
544
+ {
545
+ SP_EDGE8L, SPARC_INS_EDGE8L,
546
+ #ifndef CAPSTONE_DIET
547
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
548
+ #endif
549
+ },
550
+ {
551
+ SP_EDGE8LN, SPARC_INS_EDGE8LN,
552
+ #ifndef CAPSTONE_DIET
553
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
554
+ #endif
555
+ },
556
+ {
557
+ SP_EDGE8N, SPARC_INS_EDGE8N,
558
+ #ifndef CAPSTONE_DIET
559
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
560
+ #endif
561
+ },
562
+ {
563
+ SP_FABSD, SPARC_INS_FABSD,
564
+ #ifndef CAPSTONE_DIET
565
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
566
+ #endif
567
+ },
568
+ {
569
+ SP_FABSQ, SPARC_INS_FABSQ,
570
+ #ifndef CAPSTONE_DIET
571
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
572
+ #endif
573
+ },
574
+ {
575
+ SP_FABSS, SPARC_INS_FABSS,
576
+ #ifndef CAPSTONE_DIET
577
+ { 0 }, { 0 }, { 0 }, 0, 0
578
+ #endif
579
+ },
580
+ {
581
+ SP_FADDD, SPARC_INS_FADDD,
582
+ #ifndef CAPSTONE_DIET
583
+ { 0 }, { 0 }, { 0 }, 0, 0
584
+ #endif
585
+ },
586
+ {
587
+ SP_FADDQ, SPARC_INS_FADDQ,
588
+ #ifndef CAPSTONE_DIET
589
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
590
+ #endif
591
+ },
592
+ {
593
+ SP_FADDS, SPARC_INS_FADDS,
594
+ #ifndef CAPSTONE_DIET
595
+ { 0 }, { 0 }, { 0 }, 0, 0
596
+ #endif
597
+ },
598
+ {
599
+ SP_FALIGNADATA, SPARC_INS_FALIGNDATA,
600
+ #ifndef CAPSTONE_DIET
601
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
602
+ #endif
603
+ },
604
+ {
605
+ SP_FAND, SPARC_INS_FAND,
606
+ #ifndef CAPSTONE_DIET
607
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
608
+ #endif
609
+ },
610
+ {
611
+ SP_FANDNOT1, SPARC_INS_FANDNOT1,
612
+ #ifndef CAPSTONE_DIET
613
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
614
+ #endif
615
+ },
616
+ {
617
+ SP_FANDNOT1S, SPARC_INS_FANDNOT1S,
618
+ #ifndef CAPSTONE_DIET
619
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
620
+ #endif
621
+ },
622
+ {
623
+ SP_FANDNOT2, SPARC_INS_FANDNOT2,
624
+ #ifndef CAPSTONE_DIET
625
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
626
+ #endif
627
+ },
628
+ {
629
+ SP_FANDNOT2S, SPARC_INS_FANDNOT2S,
630
+ #ifndef CAPSTONE_DIET
631
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
632
+ #endif
633
+ },
634
+ {
635
+ SP_FANDS, SPARC_INS_FANDS,
636
+ #ifndef CAPSTONE_DIET
637
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
638
+ #endif
639
+ },
640
+ {
641
+ SP_FBCOND, SPARC_INS_FB,
642
+ #ifndef CAPSTONE_DIET
643
+ { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0
644
+ #endif
645
+ },
646
+ {
647
+ SP_FBCONDA, SPARC_INS_FB,
648
+ #ifndef CAPSTONE_DIET
649
+ { SPARC_REG_FCC0, 0 }, { 0 }, { 0 }, 1, 0
650
+ #endif
651
+ },
652
+ {
653
+ SP_FCHKSM16, SPARC_INS_FCHKSM16,
654
+ #ifndef CAPSTONE_DIET
655
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
656
+ #endif
657
+ },
658
+ {
659
+ SP_FCMPD, SPARC_INS_FCMPD,
660
+ #ifndef CAPSTONE_DIET
661
+ { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0
662
+ #endif
663
+ },
664
+ {
665
+ SP_FCMPEQ16, SPARC_INS_FCMPEQ16,
666
+ #ifndef CAPSTONE_DIET
667
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
668
+ #endif
669
+ },
670
+ {
671
+ SP_FCMPEQ32, SPARC_INS_FCMPEQ32,
672
+ #ifndef CAPSTONE_DIET
673
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
674
+ #endif
675
+ },
676
+ {
677
+ SP_FCMPGT16, SPARC_INS_FCMPGT16,
678
+ #ifndef CAPSTONE_DIET
679
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
680
+ #endif
681
+ },
682
+ {
683
+ SP_FCMPGT32, SPARC_INS_FCMPGT32,
684
+ #ifndef CAPSTONE_DIET
685
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
686
+ #endif
687
+ },
688
+ {
689
+ SP_FCMPLE16, SPARC_INS_FCMPLE16,
690
+ #ifndef CAPSTONE_DIET
691
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
692
+ #endif
693
+ },
694
+ {
695
+ SP_FCMPLE32, SPARC_INS_FCMPLE32,
696
+ #ifndef CAPSTONE_DIET
697
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
698
+ #endif
699
+ },
700
+ {
701
+ SP_FCMPNE16, SPARC_INS_FCMPNE16,
702
+ #ifndef CAPSTONE_DIET
703
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
704
+ #endif
705
+ },
706
+ {
707
+ SP_FCMPNE32, SPARC_INS_FCMPNE32,
708
+ #ifndef CAPSTONE_DIET
709
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
710
+ #endif
711
+ },
712
+ {
713
+ SP_FCMPQ, SPARC_INS_FCMPQ,
714
+ #ifndef CAPSTONE_DIET
715
+ { 0 }, { SPARC_REG_FCC0, 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
716
+ #endif
717
+ },
718
+ {
719
+ SP_FCMPS, SPARC_INS_FCMPS,
720
+ #ifndef CAPSTONE_DIET
721
+ { 0 }, { SPARC_REG_FCC0, 0 }, { 0 }, 0, 0
722
+ #endif
723
+ },
724
+ {
725
+ SP_FDIVD, SPARC_INS_FDIVD,
726
+ #ifndef CAPSTONE_DIET
727
+ { 0 }, { 0 }, { 0 }, 0, 0
728
+ #endif
729
+ },
730
+ {
731
+ SP_FDIVQ, SPARC_INS_FDIVQ,
732
+ #ifndef CAPSTONE_DIET
733
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
734
+ #endif
735
+ },
736
+ {
737
+ SP_FDIVS, SPARC_INS_FDIVS,
738
+ #ifndef CAPSTONE_DIET
739
+ { 0 }, { 0 }, { 0 }, 0, 0
740
+ #endif
741
+ },
742
+ {
743
+ SP_FDMULQ, SPARC_INS_FDMULQ,
744
+ #ifndef CAPSTONE_DIET
745
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
746
+ #endif
747
+ },
748
+ {
749
+ SP_FDTOI, SPARC_INS_FDTOI,
750
+ #ifndef CAPSTONE_DIET
751
+ { 0 }, { 0 }, { 0 }, 0, 0
752
+ #endif
753
+ },
754
+ {
755
+ SP_FDTOQ, SPARC_INS_FDTOQ,
756
+ #ifndef CAPSTONE_DIET
757
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
758
+ #endif
759
+ },
760
+ {
761
+ SP_FDTOS, SPARC_INS_FDTOS,
762
+ #ifndef CAPSTONE_DIET
763
+ { 0 }, { 0 }, { 0 }, 0, 0
764
+ #endif
765
+ },
766
+ {
767
+ SP_FDTOX, SPARC_INS_FDTOX,
768
+ #ifndef CAPSTONE_DIET
769
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
770
+ #endif
771
+ },
772
+ {
773
+ SP_FEXPAND, SPARC_INS_FEXPAND,
774
+ #ifndef CAPSTONE_DIET
775
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
776
+ #endif
777
+ },
778
+ {
779
+ SP_FHADDD, SPARC_INS_FHADDD,
780
+ #ifndef CAPSTONE_DIET
781
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
782
+ #endif
783
+ },
784
+ {
785
+ SP_FHADDS, SPARC_INS_FHADDS,
786
+ #ifndef CAPSTONE_DIET
787
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
788
+ #endif
789
+ },
790
+ {
791
+ SP_FHSUBD, SPARC_INS_FHSUBD,
792
+ #ifndef CAPSTONE_DIET
793
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
794
+ #endif
795
+ },
796
+ {
797
+ SP_FHSUBS, SPARC_INS_FHSUBS,
798
+ #ifndef CAPSTONE_DIET
799
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
800
+ #endif
801
+ },
802
+ {
803
+ SP_FITOD, SPARC_INS_FITOD,
804
+ #ifndef CAPSTONE_DIET
805
+ { 0 }, { 0 }, { 0 }, 0, 0
806
+ #endif
807
+ },
808
+ {
809
+ SP_FITOQ, SPARC_INS_FITOQ,
810
+ #ifndef CAPSTONE_DIET
811
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
812
+ #endif
813
+ },
814
+ {
815
+ SP_FITOS, SPARC_INS_FITOS,
816
+ #ifndef CAPSTONE_DIET
817
+ { 0 }, { 0 }, { 0 }, 0, 0
818
+ #endif
819
+ },
820
+ {
821
+ SP_FLCMPD, SPARC_INS_FLCMPD,
822
+ #ifndef CAPSTONE_DIET
823
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
824
+ #endif
825
+ },
826
+ {
827
+ SP_FLCMPS, SPARC_INS_FLCMPS,
828
+ #ifndef CAPSTONE_DIET
829
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
830
+ #endif
831
+ },
832
+ {
833
+ SP_FLUSHW, SPARC_INS_FLUSHW,
834
+ #ifndef CAPSTONE_DIET
835
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
836
+ #endif
837
+ },
838
+ {
839
+ SP_FMEAN16, SPARC_INS_FMEAN16,
840
+ #ifndef CAPSTONE_DIET
841
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
842
+ #endif
843
+ },
844
+ {
845
+ SP_FMOVD, SPARC_INS_FMOVD,
846
+ #ifndef CAPSTONE_DIET
847
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
848
+ #endif
849
+ },
850
+ {
851
+ SP_FMOVD_FCC, SPARC_INS_FMOVD,
852
+ #ifndef CAPSTONE_DIET
853
+ { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
854
+ #endif
855
+ },
856
+ {
857
+ SP_FMOVD_ICC, SPARC_INS_FMOVD,
858
+ #ifndef CAPSTONE_DIET
859
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
860
+ #endif
861
+ },
862
+ {
863
+ SP_FMOVD_XCC, SPARC_INS_FMOVD,
864
+ #ifndef CAPSTONE_DIET
865
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
866
+ #endif
867
+ },
868
+ {
869
+ SP_FMOVQ, SPARC_INS_FMOVQ,
870
+ #ifndef CAPSTONE_DIET
871
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
872
+ #endif
873
+ },
874
+ {
875
+ SP_FMOVQ_FCC, SPARC_INS_FMOVQ,
876
+ #ifndef CAPSTONE_DIET
877
+ { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
878
+ #endif
879
+ },
880
+ {
881
+ SP_FMOVQ_ICC, SPARC_INS_FMOVQ,
882
+ #ifndef CAPSTONE_DIET
883
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
884
+ #endif
885
+ },
886
+ {
887
+ SP_FMOVQ_XCC, SPARC_INS_FMOVQ,
888
+ #ifndef CAPSTONE_DIET
889
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
890
+ #endif
891
+ },
892
+ {
893
+ SP_FMOVRGEZD, SPARC_INS_FMOVRDGEZ,
894
+ #ifndef CAPSTONE_DIET
895
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
896
+ #endif
897
+ },
898
+ {
899
+ SP_FMOVRGEZQ, SPARC_INS_FMOVRQGEZ,
900
+ #ifndef CAPSTONE_DIET
901
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
902
+ #endif
903
+ },
904
+ {
905
+ SP_FMOVRGEZS, SPARC_INS_FMOVRSGEZ,
906
+ #ifndef CAPSTONE_DIET
907
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
908
+ #endif
909
+ },
910
+ {
911
+ SP_FMOVRGZD, SPARC_INS_FMOVRDGZ,
912
+ #ifndef CAPSTONE_DIET
913
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
914
+ #endif
915
+ },
916
+ {
917
+ SP_FMOVRGZQ, SPARC_INS_FMOVRQGZ,
918
+ #ifndef CAPSTONE_DIET
919
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
920
+ #endif
921
+ },
922
+ {
923
+ SP_FMOVRGZS, SPARC_INS_FMOVRSGZ,
924
+ #ifndef CAPSTONE_DIET
925
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
926
+ #endif
927
+ },
928
+ {
929
+ SP_FMOVRLEZD, SPARC_INS_FMOVRDLEZ,
930
+ #ifndef CAPSTONE_DIET
931
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
932
+ #endif
933
+ },
934
+ {
935
+ SP_FMOVRLEZQ, SPARC_INS_FMOVRQLEZ,
936
+ #ifndef CAPSTONE_DIET
937
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
938
+ #endif
939
+ },
940
+ {
941
+ SP_FMOVRLEZS, SPARC_INS_FMOVRSLEZ,
942
+ #ifndef CAPSTONE_DIET
943
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
944
+ #endif
945
+ },
946
+ {
947
+ SP_FMOVRLZD, SPARC_INS_FMOVRDLZ,
948
+ #ifndef CAPSTONE_DIET
949
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
950
+ #endif
951
+ },
952
+ {
953
+ SP_FMOVRLZQ, SPARC_INS_FMOVRQLZ,
954
+ #ifndef CAPSTONE_DIET
955
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
956
+ #endif
957
+ },
958
+ {
959
+ SP_FMOVRLZS, SPARC_INS_FMOVRSLZ,
960
+ #ifndef CAPSTONE_DIET
961
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
962
+ #endif
963
+ },
964
+ {
965
+ SP_FMOVRNZD, SPARC_INS_FMOVRDNZ,
966
+ #ifndef CAPSTONE_DIET
967
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
968
+ #endif
969
+ },
970
+ {
971
+ SP_FMOVRNZQ, SPARC_INS_FMOVRQNZ,
972
+ #ifndef CAPSTONE_DIET
973
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
974
+ #endif
975
+ },
976
+ {
977
+ SP_FMOVRNZS, SPARC_INS_FMOVRSNZ,
978
+ #ifndef CAPSTONE_DIET
979
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
980
+ #endif
981
+ },
982
+ {
983
+ SP_FMOVRZD, SPARC_INS_FMOVRDZ,
984
+ #ifndef CAPSTONE_DIET
985
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
986
+ #endif
987
+ },
988
+ {
989
+ SP_FMOVRZQ, SPARC_INS_FMOVRQZ,
990
+ #ifndef CAPSTONE_DIET
991
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
992
+ #endif
993
+ },
994
+ {
995
+ SP_FMOVRZS, SPARC_INS_FMOVRSZ,
996
+ #ifndef CAPSTONE_DIET
997
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
998
+ #endif
999
+ },
1000
+ {
1001
+ SP_FMOVS, SPARC_INS_FMOVS,
1002
+ #ifndef CAPSTONE_DIET
1003
+ { 0 }, { 0 }, { 0 }, 0, 0
1004
+ #endif
1005
+ },
1006
+ {
1007
+ SP_FMOVS_FCC, SPARC_INS_FMOVS,
1008
+ #ifndef CAPSTONE_DIET
1009
+ { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1010
+ #endif
1011
+ },
1012
+ {
1013
+ SP_FMOVS_ICC, SPARC_INS_FMOVS,
1014
+ #ifndef CAPSTONE_DIET
1015
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1016
+ #endif
1017
+ },
1018
+ {
1019
+ SP_FMOVS_XCC, SPARC_INS_FMOVS,
1020
+ #ifndef CAPSTONE_DIET
1021
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1022
+ #endif
1023
+ },
1024
+ {
1025
+ SP_FMUL8SUX16, SPARC_INS_FMUL8SUX16,
1026
+ #ifndef CAPSTONE_DIET
1027
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1028
+ #endif
1029
+ },
1030
+ {
1031
+ SP_FMUL8ULX16, SPARC_INS_FMUL8ULX16,
1032
+ #ifndef CAPSTONE_DIET
1033
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1034
+ #endif
1035
+ },
1036
+ {
1037
+ SP_FMUL8X16, SPARC_INS_FMUL8X16,
1038
+ #ifndef CAPSTONE_DIET
1039
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1040
+ #endif
1041
+ },
1042
+ {
1043
+ SP_FMUL8X16AL, SPARC_INS_FMUL8X16AL,
1044
+ #ifndef CAPSTONE_DIET
1045
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1046
+ #endif
1047
+ },
1048
+ {
1049
+ SP_FMUL8X16AU, SPARC_INS_FMUL8X16AU,
1050
+ #ifndef CAPSTONE_DIET
1051
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1052
+ #endif
1053
+ },
1054
+ {
1055
+ SP_FMULD, SPARC_INS_FMULD,
1056
+ #ifndef CAPSTONE_DIET
1057
+ { 0 }, { 0 }, { 0 }, 0, 0
1058
+ #endif
1059
+ },
1060
+ {
1061
+ SP_FMULD8SUX16, SPARC_INS_FMULD8SUX16,
1062
+ #ifndef CAPSTONE_DIET
1063
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1064
+ #endif
1065
+ },
1066
+ {
1067
+ SP_FMULD8ULX16, SPARC_INS_FMULD8ULX16,
1068
+ #ifndef CAPSTONE_DIET
1069
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1070
+ #endif
1071
+ },
1072
+ {
1073
+ SP_FMULQ, SPARC_INS_FMULQ,
1074
+ #ifndef CAPSTONE_DIET
1075
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1076
+ #endif
1077
+ },
1078
+ {
1079
+ SP_FMULS, SPARC_INS_FMULS,
1080
+ #ifndef CAPSTONE_DIET
1081
+ { 0 }, { 0 }, { 0 }, 0, 0
1082
+ #endif
1083
+ },
1084
+ {
1085
+ SP_FNADDD, SPARC_INS_FNADDD,
1086
+ #ifndef CAPSTONE_DIET
1087
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1088
+ #endif
1089
+ },
1090
+ {
1091
+ SP_FNADDS, SPARC_INS_FNADDS,
1092
+ #ifndef CAPSTONE_DIET
1093
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1094
+ #endif
1095
+ },
1096
+ {
1097
+ SP_FNAND, SPARC_INS_FNAND,
1098
+ #ifndef CAPSTONE_DIET
1099
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1100
+ #endif
1101
+ },
1102
+ {
1103
+ SP_FNANDS, SPARC_INS_FNANDS,
1104
+ #ifndef CAPSTONE_DIET
1105
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1106
+ #endif
1107
+ },
1108
+ {
1109
+ SP_FNEGD, SPARC_INS_FNEGD,
1110
+ #ifndef CAPSTONE_DIET
1111
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1112
+ #endif
1113
+ },
1114
+ {
1115
+ SP_FNEGQ, SPARC_INS_FNEGQ,
1116
+ #ifndef CAPSTONE_DIET
1117
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1118
+ #endif
1119
+ },
1120
+ {
1121
+ SP_FNEGS, SPARC_INS_FNEGS,
1122
+ #ifndef CAPSTONE_DIET
1123
+ { 0 }, { 0 }, { 0 }, 0, 0
1124
+ #endif
1125
+ },
1126
+ {
1127
+ SP_FNHADDD, SPARC_INS_FNHADDD,
1128
+ #ifndef CAPSTONE_DIET
1129
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1130
+ #endif
1131
+ },
1132
+ {
1133
+ SP_FNHADDS, SPARC_INS_FNHADDS,
1134
+ #ifndef CAPSTONE_DIET
1135
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1136
+ #endif
1137
+ },
1138
+ {
1139
+ SP_FNMULD, SPARC_INS_FNHADDD,
1140
+ #ifndef CAPSTONE_DIET
1141
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1142
+ #endif
1143
+ },
1144
+ {
1145
+ SP_FNMULS, SPARC_INS_FNHADDS,
1146
+ #ifndef CAPSTONE_DIET
1147
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1148
+ #endif
1149
+ },
1150
+ {
1151
+ SP_FNOR, SPARC_INS_FNOR,
1152
+ #ifndef CAPSTONE_DIET
1153
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1154
+ #endif
1155
+ },
1156
+ {
1157
+ SP_FNORS, SPARC_INS_FNORS,
1158
+ #ifndef CAPSTONE_DIET
1159
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1160
+ #endif
1161
+ },
1162
+ {
1163
+ SP_FNOT1, SPARC_INS_FNOT1,
1164
+ #ifndef CAPSTONE_DIET
1165
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1166
+ #endif
1167
+ },
1168
+ {
1169
+ SP_FNOT1S, SPARC_INS_FNOT1S,
1170
+ #ifndef CAPSTONE_DIET
1171
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1172
+ #endif
1173
+ },
1174
+ {
1175
+ SP_FNOT2, SPARC_INS_FNOT2,
1176
+ #ifndef CAPSTONE_DIET
1177
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1178
+ #endif
1179
+ },
1180
+ {
1181
+ SP_FNOT2S, SPARC_INS_FNOT2S,
1182
+ #ifndef CAPSTONE_DIET
1183
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1184
+ #endif
1185
+ },
1186
+ {
1187
+ SP_FNSMULD, SPARC_INS_FNHADDS,
1188
+ #ifndef CAPSTONE_DIET
1189
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1190
+ #endif
1191
+ },
1192
+ {
1193
+ SP_FONE, SPARC_INS_FONE,
1194
+ #ifndef CAPSTONE_DIET
1195
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1196
+ #endif
1197
+ },
1198
+ {
1199
+ SP_FONES, SPARC_INS_FONES,
1200
+ #ifndef CAPSTONE_DIET
1201
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1202
+ #endif
1203
+ },
1204
+ {
1205
+ SP_FOR, SPARC_INS_FOR,
1206
+ #ifndef CAPSTONE_DIET
1207
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1208
+ #endif
1209
+ },
1210
+ {
1211
+ SP_FORNOT1, SPARC_INS_FORNOT1,
1212
+ #ifndef CAPSTONE_DIET
1213
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1214
+ #endif
1215
+ },
1216
+ {
1217
+ SP_FORNOT1S, SPARC_INS_FORNOT1S,
1218
+ #ifndef CAPSTONE_DIET
1219
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1220
+ #endif
1221
+ },
1222
+ {
1223
+ SP_FORNOT2, SPARC_INS_FORNOT2,
1224
+ #ifndef CAPSTONE_DIET
1225
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1226
+ #endif
1227
+ },
1228
+ {
1229
+ SP_FORNOT2S, SPARC_INS_FORNOT2S,
1230
+ #ifndef CAPSTONE_DIET
1231
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1232
+ #endif
1233
+ },
1234
+ {
1235
+ SP_FORS, SPARC_INS_FORS,
1236
+ #ifndef CAPSTONE_DIET
1237
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1238
+ #endif
1239
+ },
1240
+ {
1241
+ SP_FPACK16, SPARC_INS_FPACK16,
1242
+ #ifndef CAPSTONE_DIET
1243
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1244
+ #endif
1245
+ },
1246
+ {
1247
+ SP_FPACK32, SPARC_INS_FPACK32,
1248
+ #ifndef CAPSTONE_DIET
1249
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1250
+ #endif
1251
+ },
1252
+ {
1253
+ SP_FPACKFIX, SPARC_INS_FPACKFIX,
1254
+ #ifndef CAPSTONE_DIET
1255
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1256
+ #endif
1257
+ },
1258
+ {
1259
+ SP_FPADD16, SPARC_INS_FPADD16,
1260
+ #ifndef CAPSTONE_DIET
1261
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1262
+ #endif
1263
+ },
1264
+ {
1265
+ SP_FPADD16S, SPARC_INS_FPADD16S,
1266
+ #ifndef CAPSTONE_DIET
1267
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1268
+ #endif
1269
+ },
1270
+ {
1271
+ SP_FPADD32, SPARC_INS_FPADD32,
1272
+ #ifndef CAPSTONE_DIET
1273
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1274
+ #endif
1275
+ },
1276
+ {
1277
+ SP_FPADD32S, SPARC_INS_FPADD32S,
1278
+ #ifndef CAPSTONE_DIET
1279
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1280
+ #endif
1281
+ },
1282
+ {
1283
+ SP_FPADD64, SPARC_INS_FPADD64,
1284
+ #ifndef CAPSTONE_DIET
1285
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1286
+ #endif
1287
+ },
1288
+ {
1289
+ SP_FPMERGE, SPARC_INS_FPMERGE,
1290
+ #ifndef CAPSTONE_DIET
1291
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1292
+ #endif
1293
+ },
1294
+ {
1295
+ SP_FPSUB16, SPARC_INS_FPSUB16,
1296
+ #ifndef CAPSTONE_DIET
1297
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1298
+ #endif
1299
+ },
1300
+ {
1301
+ SP_FPSUB16S, SPARC_INS_FPSUB16S,
1302
+ #ifndef CAPSTONE_DIET
1303
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1304
+ #endif
1305
+ },
1306
+ {
1307
+ SP_FPSUB32, SPARC_INS_FPSUB32,
1308
+ #ifndef CAPSTONE_DIET
1309
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1310
+ #endif
1311
+ },
1312
+ {
1313
+ SP_FPSUB32S, SPARC_INS_FPSUB32S,
1314
+ #ifndef CAPSTONE_DIET
1315
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1316
+ #endif
1317
+ },
1318
+ {
1319
+ SP_FQTOD, SPARC_INS_FQTOD,
1320
+ #ifndef CAPSTONE_DIET
1321
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1322
+ #endif
1323
+ },
1324
+ {
1325
+ SP_FQTOI, SPARC_INS_FQTOI,
1326
+ #ifndef CAPSTONE_DIET
1327
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1328
+ #endif
1329
+ },
1330
+ {
1331
+ SP_FQTOS, SPARC_INS_FQTOS,
1332
+ #ifndef CAPSTONE_DIET
1333
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1334
+ #endif
1335
+ },
1336
+ {
1337
+ SP_FQTOX, SPARC_INS_FQTOX,
1338
+ #ifndef CAPSTONE_DIET
1339
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1340
+ #endif
1341
+ },
1342
+ {
1343
+ SP_FSLAS16, SPARC_INS_FSLAS16,
1344
+ #ifndef CAPSTONE_DIET
1345
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1346
+ #endif
1347
+ },
1348
+ {
1349
+ SP_FSLAS32, SPARC_INS_FSLAS32,
1350
+ #ifndef CAPSTONE_DIET
1351
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1352
+ #endif
1353
+ },
1354
+ {
1355
+ SP_FSLL16, SPARC_INS_FSLL16,
1356
+ #ifndef CAPSTONE_DIET
1357
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1358
+ #endif
1359
+ },
1360
+ {
1361
+ SP_FSLL32, SPARC_INS_FSLL32,
1362
+ #ifndef CAPSTONE_DIET
1363
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1364
+ #endif
1365
+ },
1366
+ {
1367
+ SP_FSMULD, SPARC_INS_FSMULD,
1368
+ #ifndef CAPSTONE_DIET
1369
+ { 0 }, { 0 }, { 0 }, 0, 0
1370
+ #endif
1371
+ },
1372
+ {
1373
+ SP_FSQRTD, SPARC_INS_FSQRTD,
1374
+ #ifndef CAPSTONE_DIET
1375
+ { 0 }, { 0 }, { 0 }, 0, 0
1376
+ #endif
1377
+ },
1378
+ {
1379
+ SP_FSQRTQ, SPARC_INS_FSQRTQ,
1380
+ #ifndef CAPSTONE_DIET
1381
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1382
+ #endif
1383
+ },
1384
+ {
1385
+ SP_FSQRTS, SPARC_INS_FSQRTS,
1386
+ #ifndef CAPSTONE_DIET
1387
+ { 0 }, { 0 }, { 0 }, 0, 0
1388
+ #endif
1389
+ },
1390
+ {
1391
+ SP_FSRA16, SPARC_INS_FSRA16,
1392
+ #ifndef CAPSTONE_DIET
1393
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1394
+ #endif
1395
+ },
1396
+ {
1397
+ SP_FSRA32, SPARC_INS_FSRA32,
1398
+ #ifndef CAPSTONE_DIET
1399
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1400
+ #endif
1401
+ },
1402
+ {
1403
+ SP_FSRC1, SPARC_INS_FSRC1,
1404
+ #ifndef CAPSTONE_DIET
1405
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1406
+ #endif
1407
+ },
1408
+ {
1409
+ SP_FSRC1S, SPARC_INS_FSRC1S,
1410
+ #ifndef CAPSTONE_DIET
1411
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1412
+ #endif
1413
+ },
1414
+ {
1415
+ SP_FSRC2, SPARC_INS_FSRC2,
1416
+ #ifndef CAPSTONE_DIET
1417
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1418
+ #endif
1419
+ },
1420
+ {
1421
+ SP_FSRC2S, SPARC_INS_FSRC2S,
1422
+ #ifndef CAPSTONE_DIET
1423
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1424
+ #endif
1425
+ },
1426
+ {
1427
+ SP_FSRL16, SPARC_INS_FSRL16,
1428
+ #ifndef CAPSTONE_DIET
1429
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1430
+ #endif
1431
+ },
1432
+ {
1433
+ SP_FSRL32, SPARC_INS_FSRL32,
1434
+ #ifndef CAPSTONE_DIET
1435
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1436
+ #endif
1437
+ },
1438
+ {
1439
+ SP_FSTOD, SPARC_INS_FSTOD,
1440
+ #ifndef CAPSTONE_DIET
1441
+ { 0 }, { 0 }, { 0 }, 0, 0
1442
+ #endif
1443
+ },
1444
+ {
1445
+ SP_FSTOI, SPARC_INS_FSTOI,
1446
+ #ifndef CAPSTONE_DIET
1447
+ { 0 }, { 0 }, { 0 }, 0, 0
1448
+ #endif
1449
+ },
1450
+ {
1451
+ SP_FSTOQ, SPARC_INS_FSTOQ,
1452
+ #ifndef CAPSTONE_DIET
1453
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1454
+ #endif
1455
+ },
1456
+ {
1457
+ SP_FSTOX, SPARC_INS_FSTOX,
1458
+ #ifndef CAPSTONE_DIET
1459
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1460
+ #endif
1461
+ },
1462
+ {
1463
+ SP_FSUBD, SPARC_INS_FSUBD,
1464
+ #ifndef CAPSTONE_DIET
1465
+ { 0 }, { 0 }, { 0 }, 0, 0
1466
+ #endif
1467
+ },
1468
+ {
1469
+ SP_FSUBQ, SPARC_INS_FSUBQ,
1470
+ #ifndef CAPSTONE_DIET
1471
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
1472
+ #endif
1473
+ },
1474
+ {
1475
+ SP_FSUBS, SPARC_INS_FSUBS,
1476
+ #ifndef CAPSTONE_DIET
1477
+ { 0 }, { 0 }, { 0 }, 0, 0
1478
+ #endif
1479
+ },
1480
+ {
1481
+ SP_FXNOR, SPARC_INS_FXNOR,
1482
+ #ifndef CAPSTONE_DIET
1483
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1484
+ #endif
1485
+ },
1486
+ {
1487
+ SP_FXNORS, SPARC_INS_FXNORS,
1488
+ #ifndef CAPSTONE_DIET
1489
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1490
+ #endif
1491
+ },
1492
+ {
1493
+ SP_FXOR, SPARC_INS_FXOR,
1494
+ #ifndef CAPSTONE_DIET
1495
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1496
+ #endif
1497
+ },
1498
+ {
1499
+ SP_FXORS, SPARC_INS_FXORS,
1500
+ #ifndef CAPSTONE_DIET
1501
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1502
+ #endif
1503
+ },
1504
+ {
1505
+ SP_FXTOD, SPARC_INS_FXTOD,
1506
+ #ifndef CAPSTONE_DIET
1507
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1508
+ #endif
1509
+ },
1510
+ {
1511
+ SP_FXTOQ, SPARC_INS_FXTOQ,
1512
+ #ifndef CAPSTONE_DIET
1513
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1514
+ #endif
1515
+ },
1516
+ {
1517
+ SP_FXTOS, SPARC_INS_FXTOS,
1518
+ #ifndef CAPSTONE_DIET
1519
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1520
+ #endif
1521
+ },
1522
+ {
1523
+ SP_FZERO, SPARC_INS_FZERO,
1524
+ #ifndef CAPSTONE_DIET
1525
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1526
+ #endif
1527
+ },
1528
+ {
1529
+ SP_FZEROS, SPARC_INS_FZEROS,
1530
+ #ifndef CAPSTONE_DIET
1531
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1532
+ #endif
1533
+ },
1534
+ {
1535
+ SP_JMPLri, SPARC_INS_JMPL,
1536
+ #ifndef CAPSTONE_DIET
1537
+ { 0 }, { 0 }, { 0 }, 0, 0
1538
+ #endif
1539
+ },
1540
+ {
1541
+ SP_JMPLrr, SPARC_INS_JMPL,
1542
+ #ifndef CAPSTONE_DIET
1543
+ { 0 }, { 0 }, { 0 }, 0, 0
1544
+ #endif
1545
+ },
1546
+ {
1547
+ SP_LDDFri, SPARC_INS_LDD,
1548
+ #ifndef CAPSTONE_DIET
1549
+ { 0 }, { 0 }, { 0 }, 0, 0
1550
+ #endif
1551
+ },
1552
+ {
1553
+ SP_LDDFrr, SPARC_INS_LDD,
1554
+ #ifndef CAPSTONE_DIET
1555
+ { 0 }, { 0 }, { 0 }, 0, 0
1556
+ #endif
1557
+ },
1558
+ {
1559
+ SP_LDFri, SPARC_INS_LD,
1560
+ #ifndef CAPSTONE_DIET
1561
+ { 0 }, { 0 }, { 0 }, 0, 0
1562
+ #endif
1563
+ },
1564
+ {
1565
+ SP_LDFrr, SPARC_INS_LD,
1566
+ #ifndef CAPSTONE_DIET
1567
+ { 0 }, { 0 }, { 0 }, 0, 0
1568
+ #endif
1569
+ },
1570
+ {
1571
+ SP_LDQFri, SPARC_INS_LDQ,
1572
+ #ifndef CAPSTONE_DIET
1573
+ { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0
1574
+ #endif
1575
+ },
1576
+ {
1577
+ SP_LDQFrr, SPARC_INS_LDQ,
1578
+ #ifndef CAPSTONE_DIET
1579
+ { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0
1580
+ #endif
1581
+ },
1582
+ {
1583
+ SP_LDSBri, SPARC_INS_LDSB,
1584
+ #ifndef CAPSTONE_DIET
1585
+ { 0 }, { 0 }, { 0 }, 0, 0
1586
+ #endif
1587
+ },
1588
+ {
1589
+ SP_LDSBrr, SPARC_INS_LDSB,
1590
+ #ifndef CAPSTONE_DIET
1591
+ { 0 }, { 0 }, { 0 }, 0, 0
1592
+ #endif
1593
+ },
1594
+ {
1595
+ SP_LDSHri, SPARC_INS_LDSH,
1596
+ #ifndef CAPSTONE_DIET
1597
+ { 0 }, { 0 }, { 0 }, 0, 0
1598
+ #endif
1599
+ },
1600
+ {
1601
+ SP_LDSHrr, SPARC_INS_LDSH,
1602
+ #ifndef CAPSTONE_DIET
1603
+ { 0 }, { 0 }, { 0 }, 0, 0
1604
+ #endif
1605
+ },
1606
+ {
1607
+ SP_LDSWri, SPARC_INS_LDSW,
1608
+ #ifndef CAPSTONE_DIET
1609
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1610
+ #endif
1611
+ },
1612
+ {
1613
+ SP_LDSWrr, SPARC_INS_LDSW,
1614
+ #ifndef CAPSTONE_DIET
1615
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1616
+ #endif
1617
+ },
1618
+ {
1619
+ SP_LDUBri, SPARC_INS_LDUB,
1620
+ #ifndef CAPSTONE_DIET
1621
+ { 0 }, { 0 }, { 0 }, 0, 0
1622
+ #endif
1623
+ },
1624
+ {
1625
+ SP_LDUBrr, SPARC_INS_LDUB,
1626
+ #ifndef CAPSTONE_DIET
1627
+ { 0 }, { 0 }, { 0 }, 0, 0
1628
+ #endif
1629
+ },
1630
+ {
1631
+ SP_LDUHri, SPARC_INS_LDUH,
1632
+ #ifndef CAPSTONE_DIET
1633
+ { 0 }, { 0 }, { 0 }, 0, 0
1634
+ #endif
1635
+ },
1636
+ {
1637
+ SP_LDUHrr, SPARC_INS_LDUH,
1638
+ #ifndef CAPSTONE_DIET
1639
+ { 0 }, { 0 }, { 0 }, 0, 0
1640
+ #endif
1641
+ },
1642
+ {
1643
+ SP_LDXri, SPARC_INS_LDX,
1644
+ #ifndef CAPSTONE_DIET
1645
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1646
+ #endif
1647
+ },
1648
+ {
1649
+ SP_LDXrr, SPARC_INS_LDX,
1650
+ #ifndef CAPSTONE_DIET
1651
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1652
+ #endif
1653
+ },
1654
+ {
1655
+ SP_LDri, SPARC_INS_LD,
1656
+ #ifndef CAPSTONE_DIET
1657
+ { 0 }, { 0 }, { 0 }, 0, 0
1658
+ #endif
1659
+ },
1660
+ {
1661
+ SP_LDrr, SPARC_INS_LD,
1662
+ #ifndef CAPSTONE_DIET
1663
+ { 0 }, { 0 }, { 0 }, 0, 0
1664
+ #endif
1665
+ },
1666
+ {
1667
+ SP_LEAX_ADDri, SPARC_INS_ADD,
1668
+ #ifndef CAPSTONE_DIET
1669
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1670
+ #endif
1671
+ },
1672
+ {
1673
+ SP_LEA_ADDri, SPARC_INS_ADD,
1674
+ #ifndef CAPSTONE_DIET
1675
+ { 0 }, { 0 }, { SPARC_GRP_32BIT, 0 }, 0, 0
1676
+ #endif
1677
+ },
1678
+ {
1679
+ SP_LZCNT, SPARC_INS_LZCNT,
1680
+ #ifndef CAPSTONE_DIET
1681
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1682
+ #endif
1683
+ },
1684
+ {
1685
+ SP_MEMBARi, SPARC_INS_MEMBAR,
1686
+ #ifndef CAPSTONE_DIET
1687
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1688
+ #endif
1689
+ },
1690
+ {
1691
+ SP_MOVDTOX, SPARC_INS_MOVDTOX,
1692
+ #ifndef CAPSTONE_DIET
1693
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1694
+ #endif
1695
+ },
1696
+ {
1697
+ SP_MOVFCCri, SPARC_INS_MOV,
1698
+ #ifndef CAPSTONE_DIET
1699
+ { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1700
+ #endif
1701
+ },
1702
+ {
1703
+ SP_MOVFCCrr, SPARC_INS_MOV,
1704
+ #ifndef CAPSTONE_DIET
1705
+ { SPARC_REG_FCC0, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1706
+ #endif
1707
+ },
1708
+ {
1709
+ SP_MOVICCri, SPARC_INS_MOV,
1710
+ #ifndef CAPSTONE_DIET
1711
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1712
+ #endif
1713
+ },
1714
+ {
1715
+ SP_MOVICCrr, SPARC_INS_MOV,
1716
+ #ifndef CAPSTONE_DIET
1717
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1718
+ #endif
1719
+ },
1720
+ {
1721
+ SP_MOVRGEZri, SPARC_INS_MOVRGEZ,
1722
+ #ifndef CAPSTONE_DIET
1723
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1724
+ #endif
1725
+ },
1726
+ {
1727
+ SP_MOVRGEZrr, SPARC_INS_MOVRGEZ,
1728
+ #ifndef CAPSTONE_DIET
1729
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1730
+ #endif
1731
+ },
1732
+ {
1733
+ SP_MOVRGZri, SPARC_INS_MOVRGZ,
1734
+ #ifndef CAPSTONE_DIET
1735
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1736
+ #endif
1737
+ },
1738
+ {
1739
+ SP_MOVRGZrr, SPARC_INS_MOVRGZ,
1740
+ #ifndef CAPSTONE_DIET
1741
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1742
+ #endif
1743
+ },
1744
+ {
1745
+ SP_MOVRLEZri, SPARC_INS_MOVRLEZ,
1746
+ #ifndef CAPSTONE_DIET
1747
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1748
+ #endif
1749
+ },
1750
+ {
1751
+ SP_MOVRLEZrr, SPARC_INS_MOVRLEZ,
1752
+ #ifndef CAPSTONE_DIET
1753
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1754
+ #endif
1755
+ },
1756
+ {
1757
+ SP_MOVRLZri, SPARC_INS_MOVRLZ,
1758
+ #ifndef CAPSTONE_DIET
1759
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1760
+ #endif
1761
+ },
1762
+ {
1763
+ SP_MOVRLZrr, SPARC_INS_MOVRLZ,
1764
+ #ifndef CAPSTONE_DIET
1765
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1766
+ #endif
1767
+ },
1768
+ {
1769
+ SP_MOVRNZri, SPARC_INS_MOVRNZ,
1770
+ #ifndef CAPSTONE_DIET
1771
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1772
+ #endif
1773
+ },
1774
+ {
1775
+ SP_MOVRNZrr, SPARC_INS_MOVRNZ,
1776
+ #ifndef CAPSTONE_DIET
1777
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1778
+ #endif
1779
+ },
1780
+ {
1781
+ SP_MOVRRZri, SPARC_INS_MOVRZ,
1782
+ #ifndef CAPSTONE_DIET
1783
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1784
+ #endif
1785
+ },
1786
+ {
1787
+ SP_MOVRRZrr, SPARC_INS_MOVRZ,
1788
+ #ifndef CAPSTONE_DIET
1789
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1790
+ #endif
1791
+ },
1792
+ {
1793
+ SP_MOVSTOSW, SPARC_INS_MOVSTOSW,
1794
+ #ifndef CAPSTONE_DIET
1795
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1796
+ #endif
1797
+ },
1798
+ {
1799
+ SP_MOVSTOUW, SPARC_INS_MOVSTOUW,
1800
+ #ifndef CAPSTONE_DIET
1801
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1802
+ #endif
1803
+ },
1804
+ {
1805
+ SP_MOVWTOS, SPARC_INS_MOVDTOX,
1806
+ #ifndef CAPSTONE_DIET
1807
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1808
+ #endif
1809
+ },
1810
+ {
1811
+ SP_MOVXCCri, SPARC_INS_MOV,
1812
+ #ifndef CAPSTONE_DIET
1813
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1814
+ #endif
1815
+ },
1816
+ {
1817
+ SP_MOVXCCrr, SPARC_INS_MOV,
1818
+ #ifndef CAPSTONE_DIET
1819
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1820
+ #endif
1821
+ },
1822
+ {
1823
+ SP_MOVXTOD, SPARC_INS_MOVDTOX,
1824
+ #ifndef CAPSTONE_DIET
1825
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1826
+ #endif
1827
+ },
1828
+ {
1829
+ SP_MULXri, SPARC_INS_MULX,
1830
+ #ifndef CAPSTONE_DIET
1831
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1832
+ #endif
1833
+ },
1834
+ {
1835
+ SP_MULXrr, SPARC_INS_MULX,
1836
+ #ifndef CAPSTONE_DIET
1837
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1838
+ #endif
1839
+ },
1840
+ {
1841
+ SP_NOP, SPARC_INS_NOP,
1842
+ #ifndef CAPSTONE_DIET
1843
+ { 0 }, { 0 }, { 0 }, 0, 0
1844
+ #endif
1845
+ },
1846
+ {
1847
+ SP_ORCCri, SPARC_INS_ORCC,
1848
+ #ifndef CAPSTONE_DIET
1849
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1850
+ #endif
1851
+ },
1852
+ {
1853
+ SP_ORCCrr, SPARC_INS_ORCC,
1854
+ #ifndef CAPSTONE_DIET
1855
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1856
+ #endif
1857
+ },
1858
+ {
1859
+ SP_ORNCCri, SPARC_INS_ORNCC,
1860
+ #ifndef CAPSTONE_DIET
1861
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1862
+ #endif
1863
+ },
1864
+ {
1865
+ SP_ORNCCrr, SPARC_INS_ORNCC,
1866
+ #ifndef CAPSTONE_DIET
1867
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1868
+ #endif
1869
+ },
1870
+ {
1871
+ SP_ORNri, SPARC_INS_ORN,
1872
+ #ifndef CAPSTONE_DIET
1873
+ { 0 }, { 0 }, { 0 }, 0, 0
1874
+ #endif
1875
+ },
1876
+ {
1877
+ SP_ORNrr, SPARC_INS_ORN,
1878
+ #ifndef CAPSTONE_DIET
1879
+ { 0 }, { 0 }, { 0 }, 0, 0
1880
+ #endif
1881
+ },
1882
+ {
1883
+ SP_ORXNrr, SPARC_INS_ORN,
1884
+ #ifndef CAPSTONE_DIET
1885
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1886
+ #endif
1887
+ },
1888
+ {
1889
+ SP_ORXri, SPARC_INS_OR,
1890
+ #ifndef CAPSTONE_DIET
1891
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1892
+ #endif
1893
+ },
1894
+ {
1895
+ SP_ORXrr, SPARC_INS_OR,
1896
+ #ifndef CAPSTONE_DIET
1897
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
1898
+ #endif
1899
+ },
1900
+ {
1901
+ SP_ORri, SPARC_INS_OR,
1902
+ #ifndef CAPSTONE_DIET
1903
+ { 0 }, { 0 }, { 0 }, 0, 0
1904
+ #endif
1905
+ },
1906
+ {
1907
+ SP_ORrr, SPARC_INS_OR,
1908
+ #ifndef CAPSTONE_DIET
1909
+ { 0 }, { 0 }, { 0 }, 0, 0
1910
+ #endif
1911
+ },
1912
+ {
1913
+ SP_PDIST, SPARC_INS_PDIST,
1914
+ #ifndef CAPSTONE_DIET
1915
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
1916
+ #endif
1917
+ },
1918
+ {
1919
+ SP_PDISTN, SPARC_INS_PDISTN,
1920
+ #ifndef CAPSTONE_DIET
1921
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
1922
+ #endif
1923
+ },
1924
+ {
1925
+ SP_POPCrr, SPARC_INS_POPC,
1926
+ #ifndef CAPSTONE_DIET
1927
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
1928
+ #endif
1929
+ },
1930
+ {
1931
+ SP_RDY, SPARC_INS_RD,
1932
+ #ifndef CAPSTONE_DIET
1933
+ { SPARC_REG_Y, 0 }, { 0 }, { 0 }, 0, 0
1934
+ #endif
1935
+ },
1936
+ {
1937
+ SP_RESTOREri, SPARC_INS_RESTORE,
1938
+ #ifndef CAPSTONE_DIET
1939
+ { 0 }, { 0 }, { 0 }, 0, 0
1940
+ #endif
1941
+ },
1942
+ {
1943
+ SP_RESTORErr, SPARC_INS_RESTORE,
1944
+ #ifndef CAPSTONE_DIET
1945
+ { 0 }, { 0 }, { 0 }, 0, 0
1946
+ #endif
1947
+ },
1948
+ {
1949
+ SP_RET, SPARC_INS_JMP,
1950
+ #ifndef CAPSTONE_DIET
1951
+ { 0 }, { 0 }, { 0 }, 0, 0
1952
+ #endif
1953
+ },
1954
+ {
1955
+ SP_RETL, SPARC_INS_JMP,
1956
+ #ifndef CAPSTONE_DIET
1957
+ { 0 }, { 0 }, { 0 }, 0, 0
1958
+ #endif
1959
+ },
1960
+ {
1961
+ SP_RETTri, SPARC_INS_RETT,
1962
+ #ifndef CAPSTONE_DIET
1963
+ { 0 }, { 0 }, { 0 }, 0, 0
1964
+ #endif
1965
+ },
1966
+ {
1967
+ SP_RETTrr, SPARC_INS_RETT,
1968
+ #ifndef CAPSTONE_DIET
1969
+ { 0 }, { 0 }, { 0 }, 0, 0
1970
+ #endif
1971
+ },
1972
+ {
1973
+ SP_SAVEri, SPARC_INS_SAVE,
1974
+ #ifndef CAPSTONE_DIET
1975
+ { 0 }, { 0 }, { 0 }, 0, 0
1976
+ #endif
1977
+ },
1978
+ {
1979
+ SP_SAVErr, SPARC_INS_SAVE,
1980
+ #ifndef CAPSTONE_DIET
1981
+ { 0 }, { 0 }, { 0 }, 0, 0
1982
+ #endif
1983
+ },
1984
+ {
1985
+ SP_SDIVCCri, SPARC_INS_SDIVCC,
1986
+ #ifndef CAPSTONE_DIET
1987
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1988
+ #endif
1989
+ },
1990
+ {
1991
+ SP_SDIVCCrr, SPARC_INS_SDIVCC,
1992
+ #ifndef CAPSTONE_DIET
1993
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
1994
+ #endif
1995
+ },
1996
+ {
1997
+ SP_SDIVXri, SPARC_INS_SDIVX,
1998
+ #ifndef CAPSTONE_DIET
1999
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2000
+ #endif
2001
+ },
2002
+ {
2003
+ SP_SDIVXrr, SPARC_INS_SDIVX,
2004
+ #ifndef CAPSTONE_DIET
2005
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2006
+ #endif
2007
+ },
2008
+ {
2009
+ SP_SDIVri, SPARC_INS_SDIV,
2010
+ #ifndef CAPSTONE_DIET
2011
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2012
+ #endif
2013
+ },
2014
+ {
2015
+ SP_SDIVrr, SPARC_INS_SDIV,
2016
+ #ifndef CAPSTONE_DIET
2017
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2018
+ #endif
2019
+ },
2020
+ {
2021
+ SP_SETHIXi, SPARC_INS_SETHI,
2022
+ #ifndef CAPSTONE_DIET
2023
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2024
+ #endif
2025
+ },
2026
+ {
2027
+ SP_SETHIi, SPARC_INS_SETHI,
2028
+ #ifndef CAPSTONE_DIET
2029
+ { 0 }, { 0 }, { 0 }, 0, 0
2030
+ #endif
2031
+ },
2032
+ {
2033
+ SP_SHUTDOWN, SPARC_INS_SHUTDOWN,
2034
+ #ifndef CAPSTONE_DIET
2035
+ { 0 }, { 0 }, { SPARC_GRP_VIS, 0 }, 0, 0
2036
+ #endif
2037
+ },
2038
+ {
2039
+ SP_SIAM, SPARC_INS_SIAM,
2040
+ #ifndef CAPSTONE_DIET
2041
+ { 0 }, { 0 }, { SPARC_GRP_VIS2, 0 }, 0, 0
2042
+ #endif
2043
+ },
2044
+ {
2045
+ SP_SLLXri, SPARC_INS_SLLX,
2046
+ #ifndef CAPSTONE_DIET
2047
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2048
+ #endif
2049
+ },
2050
+ {
2051
+ SP_SLLXrr, SPARC_INS_SLLX,
2052
+ #ifndef CAPSTONE_DIET
2053
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2054
+ #endif
2055
+ },
2056
+ {
2057
+ SP_SLLri, SPARC_INS_SLL,
2058
+ #ifndef CAPSTONE_DIET
2059
+ { 0 }, { 0 }, { 0 }, 0, 0
2060
+ #endif
2061
+ },
2062
+ {
2063
+ SP_SLLrr, SPARC_INS_SLL,
2064
+ #ifndef CAPSTONE_DIET
2065
+ { 0 }, { 0 }, { 0 }, 0, 0
2066
+ #endif
2067
+ },
2068
+ {
2069
+ SP_SMULCCri, SPARC_INS_SMULCC,
2070
+ #ifndef CAPSTONE_DIET
2071
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2072
+ #endif
2073
+ },
2074
+ {
2075
+ SP_SMULCCrr, SPARC_INS_SMULCC,
2076
+ #ifndef CAPSTONE_DIET
2077
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2078
+ #endif
2079
+ },
2080
+ {
2081
+ SP_SMULri, SPARC_INS_SMUL,
2082
+ #ifndef CAPSTONE_DIET
2083
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2084
+ #endif
2085
+ },
2086
+ {
2087
+ SP_SMULrr, SPARC_INS_SMUL,
2088
+ #ifndef CAPSTONE_DIET
2089
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2090
+ #endif
2091
+ },
2092
+ {
2093
+ SP_SRAXri, SPARC_INS_SRAX,
2094
+ #ifndef CAPSTONE_DIET
2095
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2096
+ #endif
2097
+ },
2098
+ {
2099
+ SP_SRAXrr, SPARC_INS_SRAX,
2100
+ #ifndef CAPSTONE_DIET
2101
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2102
+ #endif
2103
+ },
2104
+ {
2105
+ SP_SRAri, SPARC_INS_SRA,
2106
+ #ifndef CAPSTONE_DIET
2107
+ { 0 }, { 0 }, { 0 }, 0, 0
2108
+ #endif
2109
+ },
2110
+ {
2111
+ SP_SRArr, SPARC_INS_SRA,
2112
+ #ifndef CAPSTONE_DIET
2113
+ { 0 }, { 0 }, { 0 }, 0, 0
2114
+ #endif
2115
+ },
2116
+ {
2117
+ SP_SRLXri, SPARC_INS_SRLX,
2118
+ #ifndef CAPSTONE_DIET
2119
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2120
+ #endif
2121
+ },
2122
+ {
2123
+ SP_SRLXrr, SPARC_INS_SRLX,
2124
+ #ifndef CAPSTONE_DIET
2125
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2126
+ #endif
2127
+ },
2128
+ {
2129
+ SP_SRLri, SPARC_INS_SRL,
2130
+ #ifndef CAPSTONE_DIET
2131
+ { 0 }, { 0 }, { 0 }, 0, 0
2132
+ #endif
2133
+ },
2134
+ {
2135
+ SP_SRLrr, SPARC_INS_SRL,
2136
+ #ifndef CAPSTONE_DIET
2137
+ { 0 }, { 0 }, { 0 }, 0, 0
2138
+ #endif
2139
+ },
2140
+ {
2141
+ SP_STBAR, SPARC_INS_STBAR,
2142
+ #ifndef CAPSTONE_DIET
2143
+ { 0 }, { 0 }, { 0 }, 0, 0
2144
+ #endif
2145
+ },
2146
+ {
2147
+ SP_STBri, SPARC_INS_STB,
2148
+ #ifndef CAPSTONE_DIET
2149
+ { 0 }, { 0 }, { 0 }, 0, 0
2150
+ #endif
2151
+ },
2152
+ {
2153
+ SP_STBrr, SPARC_INS_STB,
2154
+ #ifndef CAPSTONE_DIET
2155
+ { 0 }, { 0 }, { 0 }, 0, 0
2156
+ #endif
2157
+ },
2158
+ {
2159
+ SP_STDFri, SPARC_INS_STD,
2160
+ #ifndef CAPSTONE_DIET
2161
+ { 0 }, { 0 }, { 0 }, 0, 0
2162
+ #endif
2163
+ },
2164
+ {
2165
+ SP_STDFrr, SPARC_INS_STD,
2166
+ #ifndef CAPSTONE_DIET
2167
+ { 0 }, { 0 }, { 0 }, 0, 0
2168
+ #endif
2169
+ },
2170
+ {
2171
+ SP_STFri, SPARC_INS_ST,
2172
+ #ifndef CAPSTONE_DIET
2173
+ { 0 }, { 0 }, { 0 }, 0, 0
2174
+ #endif
2175
+ },
2176
+ {
2177
+ SP_STFrr, SPARC_INS_ST,
2178
+ #ifndef CAPSTONE_DIET
2179
+ { 0 }, { 0 }, { 0 }, 0, 0
2180
+ #endif
2181
+ },
2182
+ {
2183
+ SP_STHri, SPARC_INS_STH,
2184
+ #ifndef CAPSTONE_DIET
2185
+ { 0 }, { 0 }, { 0 }, 0, 0
2186
+ #endif
2187
+ },
2188
+ {
2189
+ SP_STHrr, SPARC_INS_STH,
2190
+ #ifndef CAPSTONE_DIET
2191
+ { 0 }, { 0 }, { 0 }, 0, 0
2192
+ #endif
2193
+ },
2194
+ {
2195
+ SP_STQFri, SPARC_INS_STQ,
2196
+ #ifndef CAPSTONE_DIET
2197
+ { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0
2198
+ #endif
2199
+ },
2200
+ {
2201
+ SP_STQFrr, SPARC_INS_STQ,
2202
+ #ifndef CAPSTONE_DIET
2203
+ { 0 }, { 0 }, { SPARC_GRP_V9, SPARC_GRP_HARDQUAD, 0 }, 0, 0
2204
+ #endif
2205
+ },
2206
+ {
2207
+ SP_STXri, SPARC_INS_STX,
2208
+ #ifndef CAPSTONE_DIET
2209
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2210
+ #endif
2211
+ },
2212
+ {
2213
+ SP_STXrr, SPARC_INS_STX,
2214
+ #ifndef CAPSTONE_DIET
2215
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2216
+ #endif
2217
+ },
2218
+ {
2219
+ SP_STri, SPARC_INS_ST,
2220
+ #ifndef CAPSTONE_DIET
2221
+ { 0 }, { 0 }, { 0 }, 0, 0
2222
+ #endif
2223
+ },
2224
+ {
2225
+ SP_STrr, SPARC_INS_ST,
2226
+ #ifndef CAPSTONE_DIET
2227
+ { 0 }, { 0 }, { 0 }, 0, 0
2228
+ #endif
2229
+ },
2230
+ {
2231
+ SP_SUBCCri, SPARC_INS_SUBCC,
2232
+ #ifndef CAPSTONE_DIET
2233
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2234
+ #endif
2235
+ },
2236
+ {
2237
+ SP_SUBCCrr, SPARC_INS_SUBCC,
2238
+ #ifndef CAPSTONE_DIET
2239
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2240
+ #endif
2241
+ },
2242
+ {
2243
+ SP_SUBCri, SPARC_INS_SUBX,
2244
+ #ifndef CAPSTONE_DIET
2245
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
2246
+ #endif
2247
+ },
2248
+ {
2249
+ SP_SUBCrr, SPARC_INS_SUBX,
2250
+ #ifndef CAPSTONE_DIET
2251
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
2252
+ #endif
2253
+ },
2254
+ {
2255
+ SP_SUBEri, SPARC_INS_SUBXCC,
2256
+ #ifndef CAPSTONE_DIET
2257
+ { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2258
+ #endif
2259
+ },
2260
+ {
2261
+ SP_SUBErr, SPARC_INS_SUBXCC,
2262
+ #ifndef CAPSTONE_DIET
2263
+ { SPARC_REG_ICC, 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2264
+ #endif
2265
+ },
2266
+ {
2267
+ SP_SUBXri, SPARC_INS_SUB,
2268
+ #ifndef CAPSTONE_DIET
2269
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2270
+ #endif
2271
+ },
2272
+ {
2273
+ SP_SUBXrr, SPARC_INS_SUB,
2274
+ #ifndef CAPSTONE_DIET
2275
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2276
+ #endif
2277
+ },
2278
+ {
2279
+ SP_SUBri, SPARC_INS_SUB,
2280
+ #ifndef CAPSTONE_DIET
2281
+ { 0 }, { 0 }, { 0 }, 0, 0
2282
+ #endif
2283
+ },
2284
+ {
2285
+ SP_SUBrr, SPARC_INS_SUB,
2286
+ #ifndef CAPSTONE_DIET
2287
+ { 0 }, { 0 }, { 0 }, 0, 0
2288
+ #endif
2289
+ },
2290
+ {
2291
+ SP_SWAPri, SPARC_INS_SWAP,
2292
+ #ifndef CAPSTONE_DIET
2293
+ { 0 }, { 0 }, { 0 }, 0, 0
2294
+ #endif
2295
+ },
2296
+ {
2297
+ SP_SWAPrr, SPARC_INS_SWAP,
2298
+ #ifndef CAPSTONE_DIET
2299
+ { 0 }, { 0 }, { 0 }, 0, 0
2300
+ #endif
2301
+ },
2302
+ {
2303
+ SP_TA3, SPARC_INS_T,
2304
+ #ifndef CAPSTONE_DIET
2305
+ { 0 }, { 0 }, { 0 }, 0, 0
2306
+ #endif
2307
+ },
2308
+ {
2309
+ SP_TA5, SPARC_INS_T,
2310
+ #ifndef CAPSTONE_DIET
2311
+ { 0 }, { 0 }, { 0 }, 0, 0
2312
+ #endif
2313
+ },
2314
+ {
2315
+ SP_TADDCCTVri, SPARC_INS_TADDCCTV,
2316
+ #ifndef CAPSTONE_DIET
2317
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2318
+ #endif
2319
+ },
2320
+ {
2321
+ SP_TADDCCTVrr, SPARC_INS_TADDCCTV,
2322
+ #ifndef CAPSTONE_DIET
2323
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2324
+ #endif
2325
+ },
2326
+ {
2327
+ SP_TADDCCri, SPARC_INS_TADDCC,
2328
+ #ifndef CAPSTONE_DIET
2329
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2330
+ #endif
2331
+ },
2332
+ {
2333
+ SP_TADDCCrr, SPARC_INS_TADDCC,
2334
+ #ifndef CAPSTONE_DIET
2335
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2336
+ #endif
2337
+ },
2338
+ {
2339
+ SP_TICCri, SPARC_INS_T,
2340
+ #ifndef CAPSTONE_DIET
2341
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
2342
+ #endif
2343
+ },
2344
+ {
2345
+ SP_TICCrr, SPARC_INS_T,
2346
+ #ifndef CAPSTONE_DIET
2347
+ { SPARC_REG_ICC, 0 }, { 0 }, { 0 }, 0, 0
2348
+ #endif
2349
+ },
2350
+ {
2351
+ SP_TLS_ADDXrr, SPARC_INS_ADD,
2352
+ #ifndef CAPSTONE_DIET
2353
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2354
+ #endif
2355
+ },
2356
+ {
2357
+ SP_TLS_ADDrr, SPARC_INS_ADD,
2358
+ #ifndef CAPSTONE_DIET
2359
+ { 0 }, { 0 }, { 0 }, 0, 0
2360
+ #endif
2361
+ },
2362
+ {
2363
+ SP_TLS_CALL, SPARC_INS_CALL,
2364
+ #ifndef CAPSTONE_DIET
2365
+ { SPARC_REG_O6, 0 }, { 0 }, { 0 }, 0, 0
2366
+ #endif
2367
+ },
2368
+ {
2369
+ SP_TLS_LDXrr, SPARC_INS_LDX,
2370
+ #ifndef CAPSTONE_DIET
2371
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2372
+ #endif
2373
+ },
2374
+ {
2375
+ SP_TLS_LDrr, SPARC_INS_LD,
2376
+ #ifndef CAPSTONE_DIET
2377
+ { 0 }, { 0 }, { 0 }, 0, 0
2378
+ #endif
2379
+ },
2380
+ {
2381
+ SP_TSUBCCTVri, SPARC_INS_TSUBCCTV,
2382
+ #ifndef CAPSTONE_DIET
2383
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2384
+ #endif
2385
+ },
2386
+ {
2387
+ SP_TSUBCCTVrr, SPARC_INS_TSUBCCTV,
2388
+ #ifndef CAPSTONE_DIET
2389
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2390
+ #endif
2391
+ },
2392
+ {
2393
+ SP_TSUBCCri, SPARC_INS_TSUBCC,
2394
+ #ifndef CAPSTONE_DIET
2395
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2396
+ #endif
2397
+ },
2398
+ {
2399
+ SP_TSUBCCrr, SPARC_INS_TSUBCC,
2400
+ #ifndef CAPSTONE_DIET
2401
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2402
+ #endif
2403
+ },
2404
+ {
2405
+ SP_TXCCri, SPARC_INS_T,
2406
+ #ifndef CAPSTONE_DIET
2407
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2408
+ #endif
2409
+ },
2410
+ {
2411
+ SP_TXCCrr, SPARC_INS_T,
2412
+ #ifndef CAPSTONE_DIET
2413
+ { SPARC_REG_ICC, 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2414
+ #endif
2415
+ },
2416
+ {
2417
+ SP_UDIVCCri, SPARC_INS_UDIVCC,
2418
+ #ifndef CAPSTONE_DIET
2419
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2420
+ #endif
2421
+ },
2422
+ {
2423
+ SP_UDIVCCrr, SPARC_INS_UDIVCC,
2424
+ #ifndef CAPSTONE_DIET
2425
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2426
+ #endif
2427
+ },
2428
+ {
2429
+ SP_UDIVXri, SPARC_INS_UDIVX,
2430
+ #ifndef CAPSTONE_DIET
2431
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2432
+ #endif
2433
+ },
2434
+ {
2435
+ SP_UDIVXrr, SPARC_INS_UDIVX,
2436
+ #ifndef CAPSTONE_DIET
2437
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2438
+ #endif
2439
+ },
2440
+ {
2441
+ SP_UDIVri, SPARC_INS_UDIV,
2442
+ #ifndef CAPSTONE_DIET
2443
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2444
+ #endif
2445
+ },
2446
+ {
2447
+ SP_UDIVrr, SPARC_INS_UDIV,
2448
+ #ifndef CAPSTONE_DIET
2449
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2450
+ #endif
2451
+ },
2452
+ {
2453
+ SP_UMULCCri, SPARC_INS_UMULCC,
2454
+ #ifndef CAPSTONE_DIET
2455
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2456
+ #endif
2457
+ },
2458
+ {
2459
+ SP_UMULCCrr, SPARC_INS_UMULCC,
2460
+ #ifndef CAPSTONE_DIET
2461
+ { 0 }, { SPARC_REG_Y, SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2462
+ #endif
2463
+ },
2464
+ {
2465
+ SP_UMULXHI, SPARC_INS_UMULXHI,
2466
+ #ifndef CAPSTONE_DIET
2467
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
2468
+ #endif
2469
+ },
2470
+ {
2471
+ SP_UMULri, SPARC_INS_UMUL,
2472
+ #ifndef CAPSTONE_DIET
2473
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2474
+ #endif
2475
+ },
2476
+ {
2477
+ SP_UMULrr, SPARC_INS_UMUL,
2478
+ #ifndef CAPSTONE_DIET
2479
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2480
+ #endif
2481
+ },
2482
+ {
2483
+ SP_UNIMP, SPARC_INS_UNIMP,
2484
+ #ifndef CAPSTONE_DIET
2485
+ { 0 }, { 0 }, { 0 }, 0, 0
2486
+ #endif
2487
+ },
2488
+ {
2489
+ SP_V9FCMPD, SPARC_INS_FCMPD,
2490
+ #ifndef CAPSTONE_DIET
2491
+ { 0 }, { 0 }, { 0 }, 0, 0
2492
+ #endif
2493
+ },
2494
+ {
2495
+ SP_V9FCMPED, SPARC_INS_FCMPED,
2496
+ #ifndef CAPSTONE_DIET
2497
+ { 0 }, { 0 }, { 0 }, 0, 0
2498
+ #endif
2499
+ },
2500
+ {
2501
+ SP_V9FCMPEQ, SPARC_INS_FCMPEQ,
2502
+ #ifndef CAPSTONE_DIET
2503
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
2504
+ #endif
2505
+ },
2506
+ {
2507
+ SP_V9FCMPES, SPARC_INS_FCMPES,
2508
+ #ifndef CAPSTONE_DIET
2509
+ { 0 }, { 0 }, { 0 }, 0, 0
2510
+ #endif
2511
+ },
2512
+ {
2513
+ SP_V9FCMPQ, SPARC_INS_FCMPQ,
2514
+ #ifndef CAPSTONE_DIET
2515
+ { 0 }, { 0 }, { SPARC_GRP_HARDQUAD, 0 }, 0, 0
2516
+ #endif
2517
+ },
2518
+ {
2519
+ SP_V9FCMPS, SPARC_INS_FCMPS,
2520
+ #ifndef CAPSTONE_DIET
2521
+ { 0 }, { 0 }, { 0 }, 0, 0
2522
+ #endif
2523
+ },
2524
+ {
2525
+ SP_V9FMOVD_FCC, SPARC_INS_FMOVD,
2526
+ #ifndef CAPSTONE_DIET
2527
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
2528
+ #endif
2529
+ },
2530
+ {
2531
+ SP_V9FMOVQ_FCC, SPARC_INS_FMOVQ,
2532
+ #ifndef CAPSTONE_DIET
2533
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
2534
+ #endif
2535
+ },
2536
+ {
2537
+ SP_V9FMOVS_FCC, SPARC_INS_FMOVS,
2538
+ #ifndef CAPSTONE_DIET
2539
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
2540
+ #endif
2541
+ },
2542
+ {
2543
+ SP_V9MOVFCCri, SPARC_INS_MOV,
2544
+ #ifndef CAPSTONE_DIET
2545
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
2546
+ #endif
2547
+ },
2548
+ {
2549
+ SP_V9MOVFCCrr, SPARC_INS_MOV,
2550
+ #ifndef CAPSTONE_DIET
2551
+ { 0 }, { 0 }, { SPARC_GRP_V9, 0 }, 0, 0
2552
+ #endif
2553
+ },
2554
+ {
2555
+ SP_WRYri, SPARC_INS_WR,
2556
+ #ifndef CAPSTONE_DIET
2557
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2558
+ #endif
2559
+ },
2560
+ {
2561
+ SP_WRYrr, SPARC_INS_WR,
2562
+ #ifndef CAPSTONE_DIET
2563
+ { 0 }, { SPARC_REG_Y, 0 }, { 0 }, 0, 0
2564
+ #endif
2565
+ },
2566
+ {
2567
+ SP_XMULX, SPARC_INS_XMULX,
2568
+ #ifndef CAPSTONE_DIET
2569
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
2570
+ #endif
2571
+ },
2572
+ {
2573
+ SP_XMULXHI, SPARC_INS_XMULXHI,
2574
+ #ifndef CAPSTONE_DIET
2575
+ { 0 }, { 0 }, { SPARC_GRP_VIS3, 0 }, 0, 0
2576
+ #endif
2577
+ },
2578
+ {
2579
+ SP_XNORCCri, SPARC_INS_XNORCC,
2580
+ #ifndef CAPSTONE_DIET
2581
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2582
+ #endif
2583
+ },
2584
+ {
2585
+ SP_XNORCCrr, SPARC_INS_XNORCC,
2586
+ #ifndef CAPSTONE_DIET
2587
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2588
+ #endif
2589
+ },
2590
+ {
2591
+ SP_XNORXrr, SPARC_INS_XNOR,
2592
+ #ifndef CAPSTONE_DIET
2593
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2594
+ #endif
2595
+ },
2596
+ {
2597
+ SP_XNORri, SPARC_INS_XNOR,
2598
+ #ifndef CAPSTONE_DIET
2599
+ { 0 }, { 0 }, { 0 }, 0, 0
2600
+ #endif
2601
+ },
2602
+ {
2603
+ SP_XNORrr, SPARC_INS_XNOR,
2604
+ #ifndef CAPSTONE_DIET
2605
+ { 0 }, { 0 }, { 0 }, 0, 0
2606
+ #endif
2607
+ },
2608
+ {
2609
+ SP_XORCCri, SPARC_INS_XORCC,
2610
+ #ifndef CAPSTONE_DIET
2611
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2612
+ #endif
2613
+ },
2614
+ {
2615
+ SP_XORCCrr, SPARC_INS_XORCC,
2616
+ #ifndef CAPSTONE_DIET
2617
+ { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
2618
+ #endif
2619
+ },
2620
+ {
2621
+ SP_XORXri, SPARC_INS_XOR,
2622
+ #ifndef CAPSTONE_DIET
2623
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2624
+ #endif
2625
+ },
2626
+ {
2627
+ SP_XORXrr, SPARC_INS_XOR,
2628
+ #ifndef CAPSTONE_DIET
2629
+ { 0 }, { 0 }, { SPARC_GRP_64BIT, 0 }, 0, 0
2630
+ #endif
2631
+ },
2632
+ {
2633
+ SP_XORri, SPARC_INS_XOR,
2634
+ #ifndef CAPSTONE_DIET
2635
+ { 0 }, { 0 }, { 0 }, 0, 0
2636
+ #endif
2637
+ },
2638
+ {
2639
+ SP_XORrr, SPARC_INS_XOR,
2640
+ #ifndef CAPSTONE_DIET
2641
+ { 0 }, { 0 }, { 0 }, 0, 0
2642
+ #endif
2643
+ },