hexcore-capstone 1.2.0

package/deps/capstone/arch/X86/X86ImmSize.inc

@@ -0,0 +1,335 @@
+{1, 1, X86_AAD8i8},
+{1, 1, X86_AAM8i8},
+{2, 2, X86_ADC16i16},
+{2, 2, X86_ADC16mi},
+{1, 2, X86_ADC16mi8},
+{2, 2, X86_ADC16ri},
+{1, 2, X86_ADC16ri8},
+{4, 4, X86_ADC32i32},
+{4, 4, X86_ADC32mi},
+{1, 4, X86_ADC32mi8},
+{4, 4, X86_ADC32ri},
+{1, 4, X86_ADC32ri8},
+{4, 8, X86_ADC64i32},
+{4, 8, X86_ADC64mi32},
+{1, 8, X86_ADC64mi8},
+{4, 8, X86_ADC64ri32},
+{1, 8, X86_ADC64ri8},
+{1, 1, X86_ADC8i8},
+{1, 1, X86_ADC8mi},
+{1, 1, X86_ADC8mi8},
+{1, 1, X86_ADC8ri},
+{1, 1, X86_ADC8ri8},
+{2, 2, X86_ADD16i16},
+{2, 2, X86_ADD16mi},
+{1, 2, X86_ADD16mi8},
+{2, 2, X86_ADD16ri},
+{1, 2, X86_ADD16ri8},
+{4, 4, X86_ADD32i32},
+{4, 4, X86_ADD32mi},
+{1, 4, X86_ADD32mi8},
+{4, 4, X86_ADD32ri},
+{1, 4, X86_ADD32ri8},
+{4, 8, X86_ADD64i32},
+{4, 8, X86_ADD64mi32},
+{1, 8, X86_ADD64mi8},
+{4, 8, X86_ADD64ri32},
+{1, 8, X86_ADD64ri8},
+{1, 1, X86_ADD8i8},
+{1, 1, X86_ADD8mi},
+{1, 1, X86_ADD8mi8},
+{1, 1, X86_ADD8ri},
+{1, 1, X86_ADD8ri8},
+{2, 2, X86_AND16i16},
+{2, 2, X86_AND16mi},
+{1, 2, X86_AND16mi8},
+{2, 2, X86_AND16ri},
+{1, 2, X86_AND16ri8},
+{4, 4, X86_AND32i32},
+{4, 4, X86_AND32mi},
+{1, 4, X86_AND32mi8},
+{4, 4, X86_AND32ri},
+{1, 4, X86_AND32ri8},
+{4, 8, X86_AND64i32},
+{4, 8, X86_AND64mi32},
+{1, 8, X86_AND64mi8},
+{4, 8, X86_AND64ri32},
+{1, 8, X86_AND64ri8},
+{1, 1, X86_AND8i8},
+{1, 1, X86_AND8mi},
+{1, 1, X86_AND8mi8},
+{1, 1, X86_AND8ri},
+{1, 1, X86_AND8ri8},
+{1, 1, X86_BT16mi8},
+{1, 1, X86_BT16ri8},
+{1, 1, X86_BT32mi8},
+{1, 1, X86_BT32ri8},
+{1, 1, X86_BT64mi8},
+{1, 1, X86_BT64ri8},
+{1, 1, X86_BTC16mi8},
+{1, 1, X86_BTC16ri8},
+{1, 1, X86_BTC32mi8},
+{1, 1, X86_BTC32ri8},
+{1, 1, X86_BTC64mi8},
+{1, 1, X86_BTC64ri8},
+{1, 1, X86_BTR16mi8},
+{1, 1, X86_BTR16ri8},
+{1, 1, X86_BTR32mi8},
+{1, 1, X86_BTR32ri8},
+{1, 1, X86_BTR64mi8},
+{1, 1, X86_BTR64ri8},
+{1, 1, X86_BTS16mi8},
+{1, 1, X86_BTS16ri8},
+{1, 1, X86_BTS32mi8},
+{1, 1, X86_BTS32ri8},
+{1, 1, X86_BTS64mi8},
+{1, 1, X86_BTS64ri8},
+{2, 2, X86_CALLpcrel16},
+{2, 4, X86_CALLpcrel32},
+{2, 2, X86_CMP16i16},
+{2, 2, X86_CMP16mi},
+{1, 2, X86_CMP16mi8},
+{2, 2, X86_CMP16ri},
+{1, 2, X86_CMP16ri8},
+{4, 4, X86_CMP32i32},
+{4, 4, X86_CMP32mi},
+{1, 4, X86_CMP32mi8},
+{4, 4, X86_CMP32ri},
+{1, 4, X86_CMP32ri8},
+{4, 8, X86_CMP64i32},
+{4, 8, X86_CMP64mi32},
+{1, 8, X86_CMP64mi8},
+{4, 8, X86_CMP64ri32},
+{1, 8, X86_CMP64ri8},
+{1, 1, X86_CMP8i8},
+{1, 1, X86_CMP8mi},
+{1, 1, X86_CMP8mi8},
+{1, 1, X86_CMP8ri},
+{1, 1, X86_CMP8ri8},
+{1, 2, X86_IMUL16rmi8},
+{1, 2, X86_IMUL16rri8},
+{1, 4, X86_IMUL32rmi8},
+{1, 4, X86_IMUL32rri8},
+{4, 8, X86_IMUL64rmi32},
+{1, 8, X86_IMUL64rmi8},
+{4, 8, X86_IMUL64rri32},
+{1, 8, X86_IMUL64rri8},
+{2, 2, X86_IN16ri},
+{4, 4, X86_IN32ri},
+{1, 1, X86_IN8ri},
+{2, 2, X86_JMP_2},
+{2, 2, X86_MOV16mi},
+{2, 2, X86_MOV16ri},
+{2, 2, X86_MOV16ri_alt},
+{4, 4, X86_MOV32mi},
+{4, 4, X86_MOV32ri},
+{4, 4, X86_MOV32ri_alt},
+{4, 8, X86_MOV64mi32},
+{8, 8, X86_MOV64ri},
+{4, 8, X86_MOV64ri32},
+{1, 1, X86_MOV8mi},
+{1, 1, X86_MOV8ri},
+{1, 1, X86_MOV8ri_alt},
+{2, 2, X86_OR16i16},
+{2, 2, X86_OR16mi},
+{1, 2, X86_OR16mi8},
+{2, 2, X86_OR16ri},
+{1, 2, X86_OR16ri8},
+{4, 4, X86_OR32i32},
+{4, 4, X86_OR32mi},
+{1, 4, X86_OR32mi8},
+{4, 4, X86_OR32ri},
+{1, 4, X86_OR32ri8},
+{4, 8, X86_OR64i32},
+{4, 8, X86_OR64mi32},
+{1, 8, X86_OR64mi8},
+{4, 8, X86_OR64ri32},
+{1, 8, X86_OR64ri8},
+{1, 1, X86_OR8i8},
+{1, 1, X86_OR8mi},
+{1, 1, X86_OR8mi8},
+{1, 1, X86_OR8ri},
+{1, 1, X86_OR8ri8},
+{1, 2, X86_PUSH16i8},
+{1, 4, X86_PUSH32i8},
+{4, 8, X86_PUSH64i32},
+{1, 8, X86_PUSH64i8},
+{2, 2, X86_PUSHi16},
+{4, 4, X86_PUSHi32},
+{1, 1, X86_RCL16mi},
+{1, 1, X86_RCL16ri},
+{1, 1, X86_RCL32mi},
+{1, 1, X86_RCL32ri},
+{1, 1, X86_RCL64mi},
+{1, 1, X86_RCL64ri},
+{1, 1, X86_RCL8mi},
+{1, 1, X86_RCL8ri},
+{1, 1, X86_RCR16mi},
+{1, 1, X86_RCR16ri},
+{1, 1, X86_RCR32mi},
+{1, 1, X86_RCR32ri},
+{1, 1, X86_RCR64mi},
+{1, 1, X86_RCR64ri},
+{1, 1, X86_RCR8mi},
+{1, 1, X86_RCR8ri},
+//{4, 4, X86_RELEASE_ADD32mi},
+//{4, 8, X86_RELEASE_ADD64mi32},
+//{1, 1, X86_RELEASE_ADD8mi},
+//{4, 4, X86_RELEASE_AND32mi},
+//{4, 8, X86_RELEASE_AND64mi32},
+//{1, 1, X86_RELEASE_AND8mi},
+//{2, 2, X86_RELEASE_MOV16mi},
+//{4, 4, X86_RELEASE_MOV32mi},
+//{4, 8, X86_RELEASE_MOV64mi32},
+//{1, 1, X86_RELEASE_MOV8mi},
+//{4, 4, X86_RELEASE_OR32mi},
+//{4, 8, X86_RELEASE_OR64mi32},
+//{1, 1, X86_RELEASE_OR8mi},
+//{4, 4, X86_RELEASE_XOR32mi},
+//{4, 8, X86_RELEASE_XOR64mi32},
+//{1, 1, X86_RELEASE_XOR8mi},
+{1, 1, X86_ROL16mi},
+{1, 1, X86_ROL16ri},
+{1, 1, X86_ROL32mi},
+{1, 1, X86_ROL32ri},
+{1, 1, X86_ROL64mi},
+{1, 1, X86_ROL64ri},
+{1, 1, X86_ROL8mi},
+{1, 1, X86_ROL8ri},
+{1, 1, X86_ROR16mi},
+{1, 1, X86_ROR16ri},
+{1, 1, X86_ROR32mi},
+{1, 1, X86_ROR32ri},
+{1, 1, X86_ROR64mi},
+{1, 1, X86_ROR64ri},
+{1, 1, X86_ROR8mi},
+{1, 1, X86_ROR8ri},
+{4, 4, X86_RORX32mi},
+{4, 4, X86_RORX32ri},
+{8, 8, X86_RORX64mi},
+{8, 8, X86_RORX64ri},
+{1, 1, X86_SAL16mi},
+{1, 1, X86_SAL16ri},
+{1, 1, X86_SAL32mi},
+{1, 1, X86_SAL32ri},
+{1, 1, X86_SAL64mi},
+{1, 1, X86_SAL64ri},
+{1, 1, X86_SAL8mi},
+{1, 1, X86_SAL8ri},
+{1, 1, X86_SAR16mi},
+{1, 1, X86_SAR16ri},
+{1, 1, X86_SAR32mi},
+{1, 1, X86_SAR32ri},
+{1, 1, X86_SAR64mi},
+{1, 1, X86_SAR64ri},
+{1, 1, X86_SAR8mi},
+{1, 1, X86_SAR8ri},
+{2, 2, X86_SBB16i16},
+{2, 2, X86_SBB16mi},
+{1, 2, X86_SBB16mi8},
+{2, 2, X86_SBB16ri},
+{1, 2, X86_SBB16ri8},
+{4, 4, X86_SBB32i32},
+{4, 4, X86_SBB32mi},
+{1, 4, X86_SBB32mi8},
+{4, 4, X86_SBB32ri},
+{1, 4, X86_SBB32ri8},
+{4, 8, X86_SBB64i32},
+{4, 8, X86_SBB64mi32},
+{1, 8, X86_SBB64mi8},
+{4, 8, X86_SBB64ri32},
+{1, 8, X86_SBB64ri8},
+{1, 1, X86_SBB8i8},
+{1, 1, X86_SBB8mi},
+{1, 1, X86_SBB8mi8},
+{1, 1, X86_SBB8ri},
+{1, 1, X86_SBB8ri8},
+{1, 1, X86_SHL16mi},
+{1, 1, X86_SHL16ri},
+{1, 1, X86_SHL32mi},
+{1, 1, X86_SHL32ri},
+{1, 1, X86_SHL64mi},
+{1, 1, X86_SHL64ri},
+{1, 1, X86_SHL8mi},
+{1, 1, X86_SHL8ri},
+{1, 1, X86_SHLD16mri8},
+{1, 1, X86_SHLD16rri8},
+{1, 1, X86_SHLD32mri8},
+{1, 1, X86_SHLD32rri8},
+{1, 1, X86_SHLD64mri8},
+{1, 1, X86_SHLD64rri8},
+{1, 1, X86_SHR16mi},
+{1, 1, X86_SHR16ri},
+{1, 1, X86_SHR32mi},
+{1, 1, X86_SHR32ri},
+{1, 1, X86_SHR64mi},
+{1, 1, X86_SHR64ri},
+{1, 1, X86_SHR8mi},
+{1, 1, X86_SHR8ri},
+{1, 1, X86_SHRD16mri8},
+{1, 1, X86_SHRD16rri8},
+{1, 1, X86_SHRD32mri8},
+{1, 1, X86_SHRD32rri8},
+{1, 1, X86_SHRD64mri8},
+{1, 1, X86_SHRD64rri8},
+{2, 2, X86_SUB16i16},
+{2, 2, X86_SUB16mi},
+{1, 2, X86_SUB16mi8},
+{2, 2, X86_SUB16ri},
+{1, 2, X86_SUB16ri8},
+{4, 4, X86_SUB32i32},
+{4, 4, X86_SUB32mi},
+{1, 4, X86_SUB32mi8},
+{4, 4, X86_SUB32ri},
+{1, 4, X86_SUB32ri8},
+{4, 8, X86_SUB64i32},
+{4, 8, X86_SUB64mi32},
+{1, 8, X86_SUB64mi8},
+{4, 8, X86_SUB64ri32},
+{1, 8, X86_SUB64ri8},
+{1, 1, X86_SUB8i8},
+{1, 1, X86_SUB8mi},
+{1, 1, X86_SUB8mi8},
+{1, 1, X86_SUB8ri},
+{1, 1, X86_SUB8ri8},
+{2, 2, X86_TEST16i16},
+{2, 2, X86_TEST16mi},
+// {2, 2, X86_TEST16mi_alt},
+{2, 2, X86_TEST16ri},
+//{2, 2, X86_TEST16ri_alt},
+{4, 4, X86_TEST32i32},
+{4, 4, X86_TEST32mi},
+//{4, 4, X86_TEST32mi_alt},
+{4, 4, X86_TEST32ri},
+//{4, 4, X86_TEST32ri_alt},
+{4, 8, X86_TEST64i32},
+{4, 8, X86_TEST64mi32},
+//{4, 4, X86_TEST64mi32_alt},
+{4, 8, X86_TEST64ri32},
+//{4, 4, X86_TEST64ri32_alt},
+{1, 1, X86_TEST8i8},
+{1, 1, X86_TEST8mi},
+//{1, 1, X86_TEST8mi_alt},
+{1, 1, X86_TEST8ri},
+//{1, 1, X86_TEST8ri_NOREX},
+//{1, 1, X86_TEST8ri_alt},
+{2, 2, X86_XOR16i16},
+{2, 2, X86_XOR16mi},
+{1, 2, X86_XOR16mi8},
+{2, 2, X86_XOR16ri},
+{1, 2, X86_XOR16ri8},
+{4, 4, X86_XOR32i32},
+{4, 4, X86_XOR32mi},
+{1, 4, X86_XOR32mi8},
+{4, 4, X86_XOR32ri},
+{1, 4, X86_XOR32ri8},
+{4, 8, X86_XOR64i32},
+{4, 8, X86_XOR64mi32},
+{1, 8, X86_XOR64mi8},
+{4, 8, X86_XOR64ri32},
+{1, 8, X86_XOR64ri8},
+{1, 1, X86_XOR8i8},
+{1, 1, X86_XOR8mi},
+{1, 1, X86_XOR8mi8},
+{1, 1, X86_XOR8ri},
+{1, 1, X86_XOR8ri8},

package/deps/capstone/arch/X86/X86InstPrinter.h

@@ -0,0 +1,26 @@
+//= X86IntelInstPrinter.h - Convert X86 MCInst to assembly syntax -*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an X86 MCInst to Intel style .s file syntax.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_X86_INSTPRINTER_H
+#define CS_X86_INSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+void X86_Intel_printInst(MCInst *MI, SStream *OS, void *Info);
+void X86_ATT_printInst(MCInst *MI, SStream *OS, void *Info);
+
+#endif

package/deps/capstone/arch/X86/X86InstPrinterCommon.c

@@ -0,0 +1,116 @@
+//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file includes common code for rendering MCInst instances as Intel-style
+// and Intel-style assembly.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#pragma warning(disable:4996)			// disable MSVC's warning on strncpy()
+#pragma warning(disable:28719)		// disable MSVC's warning on strncpy()
+#endif
+
+#if !defined(CAPSTONE_HAS_OSXKERNEL)
+#include <ctype.h>
+#endif
+#include <capstone/platform.h>
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+#include <string.h>
+
+#include "../../utils.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+#include "X86InstPrinterCommon.h"
+#include "X86Mapping.h"
+
+#ifndef CAPSTONE_X86_REDUCE
+void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O)
+{
+	uint8_t Imm = (uint8_t)(MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f);
+	switch (Imm) {
+		default: break;//printf("Invalid avxcc argument!\n"); break;
+		case    0: SStream_concat0(O, "eq"); op_addAvxCC(MI, X86_AVX_CC_EQ); break;
+		case    1: SStream_concat0(O, "lt"); op_addAvxCC(MI, X86_AVX_CC_LT); break;
+		case    2: SStream_concat0(O, "le"); op_addAvxCC(MI, X86_AVX_CC_LE); break;
+		case    3: SStream_concat0(O, "unord"); op_addAvxCC(MI, X86_AVX_CC_UNORD); break;
+		case    4: SStream_concat0(O, "neq"); op_addAvxCC(MI, X86_AVX_CC_NEQ); break;
+		case    5: SStream_concat0(O, "nlt"); op_addAvxCC(MI, X86_AVX_CC_NLT); break;
+		case    6: SStream_concat0(O, "nle"); op_addAvxCC(MI, X86_AVX_CC_NLE); break;
+		case    7: SStream_concat0(O, "ord"); op_addAvxCC(MI, X86_AVX_CC_ORD); break;
+		case    8: SStream_concat0(O, "eq_uq"); op_addAvxCC(MI, X86_AVX_CC_EQ_UQ); break;
+		case    9: SStream_concat0(O, "nge"); op_addAvxCC(MI, X86_AVX_CC_NGE); break;
+		case  0xa: SStream_concat0(O, "ngt"); op_addAvxCC(MI, X86_AVX_CC_NGT); break;
+		case  0xb: SStream_concat0(O, "false"); op_addAvxCC(MI, X86_AVX_CC_FALSE); break;
+		case  0xc: SStream_concat0(O, "neq_oq"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OQ); break;
+		case  0xd: SStream_concat0(O, "ge"); op_addAvxCC(MI, X86_AVX_CC_GE); break;
+		case  0xe: SStream_concat0(O, "gt"); op_addAvxCC(MI, X86_AVX_CC_GT); break;
+		case  0xf: SStream_concat0(O, "true"); op_addAvxCC(MI, X86_AVX_CC_TRUE); break;
+		case 0x10: SStream_concat0(O, "eq_os"); op_addAvxCC(MI, X86_AVX_CC_EQ_OS); break;
+		case 0x11: SStream_concat0(O, "lt_oq"); op_addAvxCC(MI, X86_AVX_CC_LT_OQ); break;
+		case 0x12: SStream_concat0(O, "le_oq"); op_addAvxCC(MI, X86_AVX_CC_LE_OQ); break;
+		case 0x13: SStream_concat0(O, "unord_s"); op_addAvxCC(MI, X86_AVX_CC_UNORD_S); break;
+		case 0x14: SStream_concat0(O, "neq_us"); op_addAvxCC(MI, X86_AVX_CC_NEQ_US); break;
+		case 0x15: SStream_concat0(O, "nlt_uq"); op_addAvxCC(MI, X86_AVX_CC_NLT_UQ); break;
+		case 0x16: SStream_concat0(O, "nle_uq"); op_addAvxCC(MI, X86_AVX_CC_NLE_UQ); break;
+		case 0x17: SStream_concat0(O, "ord_s"); op_addAvxCC(MI, X86_AVX_CC_ORD_S); break;
+		case 0x18: SStream_concat0(O, "eq_us"); op_addAvxCC(MI, X86_AVX_CC_EQ_US); break;
+		case 0x19: SStream_concat0(O, "nge_uq"); op_addAvxCC(MI, X86_AVX_CC_NGE_UQ); break;
+		case 0x1a: SStream_concat0(O, "ngt_uq"); op_addAvxCC(MI, X86_AVX_CC_NGT_UQ); break;
+		case 0x1b: SStream_concat0(O, "false_os"); op_addAvxCC(MI, X86_AVX_CC_FALSE_OS); break;
+		case 0x1c: SStream_concat0(O, "neq_os"); op_addAvxCC(MI, X86_AVX_CC_NEQ_OS); break;
+		case 0x1d: SStream_concat0(O, "ge_oq"); op_addAvxCC(MI, X86_AVX_CC_GE_OQ); break;
+		case 0x1e: SStream_concat0(O, "gt_oq"); op_addAvxCC(MI, X86_AVX_CC_GT_OQ); break;
+		case 0x1f: SStream_concat0(O, "true_us"); op_addAvxCC(MI, X86_AVX_CC_TRUE_US); break;
+	}
+
+	MI->popcode_adjust = Imm + 1;
+}
+
+void printXOPCC(MCInst *MI, unsigned Op, SStream *O)
+{
+	int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op));
+
+	switch (Imm) {
+		default: // llvm_unreachable("Invalid xopcc argument!");
+		case 0: SStream_concat0(O, "lt"); op_addXopCC(MI, X86_XOP_CC_LT); break;
+		case 1: SStream_concat0(O, "le"); op_addXopCC(MI, X86_XOP_CC_LE); break;
+		case 2: SStream_concat0(O, "gt"); op_addXopCC(MI, X86_XOP_CC_GT); break;
+		case 3: SStream_concat0(O, "ge"); op_addXopCC(MI, X86_XOP_CC_GE); break;
+		case 4: SStream_concat0(O, "eq"); op_addXopCC(MI, X86_XOP_CC_EQ); break;
+		case 5: SStream_concat0(O, "neq"); op_addXopCC(MI, X86_XOP_CC_NEQ); break;
+		case 6: SStream_concat0(O, "false"); op_addXopCC(MI, X86_XOP_CC_FALSE); break;
+		case 7: SStream_concat0(O, "true"); op_addXopCC(MI, X86_XOP_CC_TRUE); break;
+	}
+}
+
+void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
+{
+	int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
+	switch (Imm) {
+		case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break;
+		case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break;
+		case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break;
+		case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break;
+		default: break;	// never reach
+	}
+}
+#endif

package/deps/capstone/arch/X86/X86InstPrinterCommon.h

@@ -0,0 +1,16 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_X86_INSTPRINTERCOMMON_H
+#define CS_X86_INSTPRINTERCOMMON_H
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+
+
+void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O);
+void printXOPCC(MCInst *MI, unsigned Op, SStream *O);
+void printRoundingControl(MCInst *MI, unsigned Op, SStream *O);
+
+#endif
+