hexcore-capstone 1.2.0

package/deps/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc

@@ -0,0 +1,49 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|* Subtarget Enumeration Source Fragment                                      *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  SystemZ_FeatureDFPPackedConversion = 1ULL << 0,
+  SystemZ_FeatureDFPZonedConversion = 1ULL << 1,
+  SystemZ_FeatureDistinctOps = 1ULL << 2,
+  SystemZ_FeatureEnhancedDAT2 = 1ULL << 3,
+  SystemZ_FeatureExecutionHint = 1ULL << 4,
+  SystemZ_FeatureFPExtension = 1ULL << 5,
+  SystemZ_FeatureFastSerialization = 1ULL << 6,
+  SystemZ_FeatureGuardedStorage = 1ULL << 7,
+  SystemZ_FeatureHighWord = 1ULL << 8,
+  SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9,
+  SystemZ_FeatureInterlockedAccess1 = 1ULL << 10,
+  SystemZ_FeatureLoadAndTrap = 1ULL << 11,
+  SystemZ_FeatureLoadAndZeroRightmostByte = 1ULL << 12,
+  SystemZ_FeatureLoadStoreOnCond = 1ULL << 13,
+  SystemZ_FeatureLoadStoreOnCond2 = 1ULL << 14,
+  SystemZ_FeatureMessageSecurityAssist3 = 1ULL << 15,
+  SystemZ_FeatureMessageSecurityAssist4 = 1ULL << 16,
+  SystemZ_FeatureMessageSecurityAssist5 = 1ULL << 17,
+  SystemZ_FeatureMessageSecurityAssist7 = 1ULL << 18,
+  SystemZ_FeatureMessageSecurityAssist8 = 1ULL << 19,
+  SystemZ_FeatureMiscellaneousExtensions = 1ULL << 20,
+  SystemZ_FeatureMiscellaneousExtensions2 = 1ULL << 21,
+  SystemZ_FeaturePopulationCount = 1ULL << 22,
+  SystemZ_FeatureProcessorAssist = 1ULL << 23,
+  SystemZ_FeatureResetReferenceBitsMultiple = 1ULL << 24,
+  SystemZ_FeatureTransactionalExecution = 1ULL << 25,
+  SystemZ_FeatureVector = 1ULL << 26,
+  SystemZ_FeatureVectorEnhancements1 = 1ULL << 27,
+  SystemZ_FeatureVectorPackedDecimal = 1ULL << 28,
+};
+
+#endif // GET_SUBTARGETINFO_ENUM
+

package/deps/capstone/arch/SystemZ/SystemZInstPrinter.c

@@ -0,0 +1,433 @@
+//===-- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an SystemZ MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "SystemZInstPrinter.h"
+#include "../../MCInst.h"
+#include "../../utils.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "SystemZMapping.h"
+
+static const char *getRegisterName(unsigned RegNo);
+
+void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+{
+	/*
+	   if (((cs_struct *)ud)->detail != CS_OPT_ON)
+	   return;
+	 */
+}
+
+static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O)
+{
+	printInt64(O, Disp);
+
+	if (Base) {
+		SStream_concat0(O, "(");
+		if (Index)
+			SStream_concat(O, "%%%s, ", getRegisterName(Index));
+		SStream_concat(O, "%%%s)", getRegisterName(Base));
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else if (!Index) {
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else {
+		SStream_concat(O, "(%%%s)", getRegisterName(Index));
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)SystemZ_map_register(Index);
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
+{
+	if (MCOperand_isReg(MO)) {
+		unsigned reg;
+
+		reg = MCOperand_getReg(MO);
+		SStream_concat(O, "%%%s", getRegisterName(reg));
+		reg = SystemZ_map_register(reg);
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	} else if (MCOperand_isImm(MO)) {
+		int64_t Imm = MCOperand_getImm(MO);
+
+		printInt64(O, Imm);
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<1>(Value) && "Invalid u1imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<2>(Value) && "Invalid u2imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<3>(Value) && "Invalid u4imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<4>(Value) && "Invalid u4imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<6>(Value) && "Invalid u6imm argument");
+
+	printUInt32(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<8>(Value) && "Invalid s8imm argument");
+
+	if (Value >= 0) {
+		if (Value > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", Value);
+		else
+			SStream_concat(O, "%u", Value);
+	} else {
+		if (Value < -HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -Value);
+		else
+			SStream_concat(O, "-%u", -Value);
+	}
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<8>(Value) && "Invalid u8imm argument");
+
+	if (Value > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", Value);
+	else
+		SStream_concat(O, "%u", Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<12>(Value) && "Invalid u12imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<16>(Value) && "Invalid s16imm argument");
+
+	if (Value >= 0) {
+		if (Value > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", Value);
+		else
+			SStream_concat(O, "%u", Value);
+	} else {
+		if (Value < -HEX_THRESHOLD)
+			SStream_concat(O, "-0x%x", -Value);
+		else
+			SStream_concat(O, "-%u", -Value);
+	}
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<16>(Value) && "Invalid u16imm argument");
+
+	if (Value > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", Value);
+	else
+		SStream_concat(O, "%u", Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isInt<32>(Value) && "Invalid s32imm argument");
+
+	printInt32(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<32>(Value) && "Invalid u32imm argument");
+
+	printUInt32(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(isUInt<48>(Value) && "Invalid u48imm argument");
+	printInt64(O, Value);
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Value;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	MCOperand *MO = MCInst_getOperand(MI, OpNum);
+
+	if (MCOperand_isImm(MO)) {
+		int64_t imm = (int64_t)MCOperand_getImm(MO);
+
+		printInt64(O, imm);
+
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
+			MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = imm;
+			MI->flat_insn->detail->sysz.op_count++;
+		}
+	}
+}
+
+static void printPCRelTLSOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	// Output the PC-relative operand.
+	printPCRelOperand(MI, OpNum, O);
+}
+
+static void printOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
+}
+
+static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)), 0, O);
+}
+
+static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)),
+			MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O);
+}
+
+static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
+	uint64_t Length = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2));
+
+	if (Disp > HEX_THRESHOLD)
+		SStream_concat(O, "0x%"PRIx64, Disp);
+	else
+		SStream_concat(O, "%"PRIu64, Disp);
+
+	if (Length > HEX_THRESHOLD)
+		SStream_concat(O, "(0x%"PRIx64, Length);
+	else
+		SStream_concat(O, "(%"PRIu64, Length);
+
+	if (Base)
+		SStream_concat(O, ", %%%s", getRegisterName(Base));
+	SStream_concat0(O, ")");
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = Length;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
+	uint64_t Length = MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2));
+
+	if (Disp > HEX_THRESHOLD)
+		SStream_concat(O, "0x%"PRIx64, Disp);
+	else
+		SStream_concat(O, "%"PRIu64, Disp);
+
+	SStream_concat0(O, "(");
+	SStream_concat(O, "%%%s", getRegisterName(Length));
+
+	if (Base)
+		SStream_concat(O, ", %%%s", getRegisterName(Base));
+	SStream_concat0(O, ")");
+
+	if (MI->csh->detail) {
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM;
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)SystemZ_map_register(Base);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.length = (uint8_t)SystemZ_map_register(Length);
+		MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = (int64_t)Disp;
+		MI->flat_insn->detail->sysz.op_count++;
+	}
+}
+
+static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	printAddress(MI, MCOperand_getReg(MCInst_getOperand(MI, OpNum)),
+			MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)),
+			MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)), O);
+}
+
+static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
+{
+	static const char *const CondNames[] = {
+		"o", "h", "nle", "l", "nhe", "lh", "ne",
+		"e", "nlh", "he", "nl", "le", "nh", "no"
+	};
+
+	uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	// assert(Imm > 0 && Imm < 15 && "Invalid condition");
+	SStream_concat0(O, CondNames[Imm - 1]);
+
+	if (MI->csh->detail)
+		MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm;
+}
+
+#define PRINT_ALIAS_INSTR
+#include "SystemZGenAsmWriter.inc"
+
+void SystemZ_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	printInstruction(MI, O, Info);
+}
+
+#endif

package/deps/capstone/arch/SystemZ/SystemZInstPrinter.h

@@ -0,0 +1,15 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SYSZINSTPRINTER_H
+#define CS_SYSZINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void SystemZ_printInst(MCInst *MI, SStream *O, void *Info);
+
+void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
+
+#endif

package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.c

@@ -0,0 +1,195 @@
+//===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_SYSZ
+
+#include <capstone/platform.h>
+#include "SystemZMCTargetDesc.h"
+
+#define GET_REGINFO_ENUM
+#include "SystemZGenRegisterInfo.inc"
+
+const unsigned SystemZMC_GR32Regs[16] = {
+	SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L,
+	SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L,
+	SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L,
+	SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L
+};
+
+const unsigned SystemZMC_GRH32Regs[16] = {
+	SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H,
+	SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H,
+	SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H,
+	SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H
+};
+
+const unsigned SystemZMC_GR64Regs[16] = {
+	SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D,
+	SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D,
+	SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D,
+	SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D
+};
+
+const unsigned SystemZMC_GR128Regs[16] = {
+	SystemZ_R0Q, 0, SystemZ_R2Q, 0,
+	SystemZ_R4Q, 0, SystemZ_R6Q, 0,
+	SystemZ_R8Q, 0, SystemZ_R10Q, 0,
+	SystemZ_R12Q, 0, SystemZ_R14Q, 0
+};
+
+const unsigned SystemZMC_FP32Regs[16] = {
+	SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
+	SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
+	SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
+	SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S
+};
+
+const unsigned SystemZMC_FP64Regs[16] = {
+	SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
+	SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
+	SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
+	SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D
+};
+
+const unsigned SystemZMC_FP128Regs[16] = {
+	SystemZ_F0Q, SystemZ_F1Q, 0, 0,
+	SystemZ_F4Q, SystemZ_F5Q, 0, 0,
+	SystemZ_F8Q, SystemZ_F9Q, 0, 0,
+	SystemZ_F12Q, SystemZ_F13Q, 0, 0
+};
+
+const unsigned SystemZMC_VR32Regs[32] = {
+  SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
+  SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
+  SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
+  SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
+  SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,
+  SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S,
+  SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S,
+  SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S
+};
+
+const unsigned SystemZMC_VR64Regs[32] = {
+  SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
+  SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
+  SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
+  SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
+  SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,
+  SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D,
+  SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D,
+  SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D
+};
+
+const unsigned SystemZMC_VR128Regs[32] = {
+  SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3,
+  SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7,
+  SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11,
+  SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
+  SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,
+  SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23,
+  SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27,
+  SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31
+};
+
+const unsigned SystemZMC_AR32Regs[16] = {
+  SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3,
+  SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7,
+  SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11,
+  SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15
+};
+
+const unsigned SystemZMC_CR64Regs[16] = {
+  SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3,
+  SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7,
+  SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11,
+  SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
+};
+
+/* All register classes that have 0-15.  */
+#define DEF_REG16(N) \
+    [SystemZ_R ## N ## L] = N, \
+    [SystemZ_R ## N ## H] = N, \
+    [SystemZ_R ## N ## D] = N, \
+    [SystemZ_F ## N ## S] = N, \
+    [SystemZ_F ## N ## D] = N, \
+    [SystemZ_V ## N] = N, \
+    [SystemZ_A ## N] = N, \
+    [SystemZ_C ## N] = N
+
+/* All register classes that (also) have 16-31.  */
+#define DEF_REG32(N) \
+    [SystemZ_F ## N ## S] = N, \
+    [SystemZ_F ## N ## D] = N, \
+    [SystemZ_V ## N] = N
+
+static const uint8_t Map[SystemZ_NUM_TARGET_REGS] = {
+    DEF_REG16(0),
+    DEF_REG16(1),
+    DEF_REG16(2),
+    DEF_REG16(3),
+    DEF_REG16(4),
+    DEF_REG16(5),
+    DEF_REG16(6),
+    DEF_REG16(8),
+    DEF_REG16(9),
+    DEF_REG16(10),
+    DEF_REG16(11),
+    DEF_REG16(12),
+    DEF_REG16(13),
+    DEF_REG16(14),
+    DEF_REG16(15),
+
+    DEF_REG32(16),
+    DEF_REG32(17),
+    DEF_REG32(18),
+    DEF_REG32(19),
+    DEF_REG32(20),
+    DEF_REG32(21),
+    DEF_REG32(22),
+    DEF_REG32(23),
+    DEF_REG32(24),
+    DEF_REG32(25),
+    DEF_REG32(26),
+    DEF_REG32(27),
+    DEF_REG32(28),
+    DEF_REG32(29),
+    DEF_REG32(30),
+    DEF_REG32(31),
+
+    /* The float Q registers are non-sequential.  */
+    [SystemZ_F0Q] = 0,
+    [SystemZ_F1Q] = 1,
+    [SystemZ_F4Q] = 4,
+    [SystemZ_F5Q] = 5,
+    [SystemZ_F8Q] = 8,
+    [SystemZ_F9Q] = 9,
+    [SystemZ_F12Q] = 12,
+    [SystemZ_F13Q] = 13,
+
+    /* The integer Q registers are all even.  */
+    [SystemZ_R0Q] = 0,
+    [SystemZ_R2Q] = 2,
+    [SystemZ_R4Q] = 4,
+    [SystemZ_R6Q] = 6,
+    [SystemZ_R8Q] = 8,
+    [SystemZ_R10Q] = 10,
+    [SystemZ_R12Q] = 12,
+    [SystemZ_R14Q] = 14,
+};
+
+unsigned SystemZMC_getFirstReg(unsigned Reg)
+{
+	// assert(Reg < SystemZ_NUM_TARGET_REGS);
+	return Map[Reg];
+}
+
+#endif