hexcore-capstone 1.2.0

package/deps/capstone/arch/TriCore/TriCoreLinkage.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_TRICORE_LINKAGE_H
+#define CS_TRICORE_LINKAGE_H
+
+// Function defintions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+bool TriCore_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
+				 size_t ByteLen, MCInst *MI, uint16_t *Size,
+				 uint64_t Address, void *Info);
+const char *TriCore_LLVM_getRegisterName(unsigned RegNo);
+void TriCore_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O);
+
+#endif // CS_TRICORE_LINKAGE_H

package/deps/capstone/arch/TriCore/TriCoreMapping.c

@@ -0,0 +1,241 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include <stdio.h> // debug
+#include <string.h>
+#include <assert.h>
+
+#include "../../utils.h"
+#include "../../cs_simple_types.h"
+
+#include "TriCoreMapping.h"
+#include "TriCoreLinkage.h"
+
+#define GET_INSTRINFO_ENUM
+
+#include "TriCoreGenInstrInfo.inc"
+
+static const insn_map insns[] = {
+	// dummy item
+	{ 0,
+	  0,
+#ifndef CAPSTONE_DIET
+	  { 0 },
+	  { 0 },
+	  { 0 },
+	  0,
+	  0
+#endif
+	},
+
+#include "TriCoreGenCSMappingInsn.inc"
+};
+
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	// Not used. Information is set after disassembly.
+}
+
+#ifndef CAPSTONE_DIET
+static const tricore_reg flag_regs[] = { TRICORE_REG_PSW };
+#endif // CAPSTONE_DIET
+
+static inline void check_updates_flags(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+	cs_detail *detail = MI->flat_insn->detail;
+	for (int i = 0; i < detail->regs_write_count; ++i) {
+		if (detail->regs_write[i] == 0)
+			return;
+		for (int j = 0; j < ARR_SIZE(flag_regs); ++j) {
+			if (detail->regs_write[i] == flag_regs[j]) {
+				detail->tricore.update_flags = true;
+				return;
+			}
+		}
+	}
+#endif // CAPSTONE_DIET
+}
+
+void TriCore_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, insns, ARR_SIZE(insns));
+	map_implicit_reads(MI, insns);
+	map_implicit_writes(MI, insns);
+	check_updates_flags(MI);
+	map_groups(MI, insns);
+}
+
+#ifndef CAPSTONE_DIET
+
+static const char * const insn_names[] = {
+	NULL,
+
+#include "TriCoreGenCSMappingInsnName.inc"
+};
+
+// special alias insn
+static const name_map alias_insn_names[] = { { 0, NULL } };
+#endif
+
+const char *TriCore_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int i;
+
+	if (id >= TRICORE_INS_ENDING)
+		return NULL;
+
+	// handle special alias first
+	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
+		if (alias_insn_names[i].id == id)
+			return alias_insn_names[i].name;
+	}
+
+	return insn_names[id];
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	{ TRICORE_GRP_INVALID, NULL },
+	{ TRICORE_GRP_CALL, "call" },
+	{ TRICORE_GRP_JUMP, "jump" },
+};
+#endif
+
+const char *TriCore_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= TRICORE_GRP_ENDING)
+		return NULL;
+
+	return group_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+/// A LLVM<->CS Mapping entry of an operand.
+typedef struct insn_op {
+	uint8_t /* cs_op_type */ type;	 ///< Operand type (e.g.: reg, imm, mem)
+	uint8_t /* cs_ac_type */ access; ///< The access type (read, write)
+	uint8_t				 /* cs_data_type */
+		dtypes[10]; ///< List of op types. Terminated by CS_DATA_TYPE_LAST
+} insn_op;
+
+///< Operands of an instruction.
+typedef struct {
+	insn_op ops[16]; ///< NULL terminated array of operands.
+} insn_ops;
+
+const insn_ops insn_operands[] = {
+#include "TriCoreGenCSMappingInsnOp.inc"
+};
+#endif
+
+void TriCore_set_access(MCInst *MI)
+{
+#ifndef CAPSTONE_DIET
+	if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail))
+		return;
+
+	assert(MI->Opcode < ARR_SIZE(insn_operands));
+
+	cs_detail *detail = MI->flat_insn->detail;
+	cs_tricore *tc = &(detail->tricore);
+	for (int i = 0; i < tc->op_count; ++i) {
+		cs_ac_type ac = map_get_op_access(MI, i);
+		cs_tricore_op *op = &tc->operands[i];
+		op->access = ac;
+		cs_op_type op_type = map_get_op_type(MI, i);
+		if (op_type != CS_OP_REG) {
+			continue;
+		}
+		if (ac & CS_AC_READ) {
+			detail->regs_read[detail->regs_read_count++] = op->reg;
+		}
+		if (ac & CS_AC_WRITE) {
+			detail->regs_write[detail->regs_write_count++] =
+				op->reg;
+		}
+	}
+#endif
+}
+
+void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count)
+{
+#ifndef CAPSTONE_DIET
+	uint8_t read_count, write_count;
+	cs_detail *detail = insn->detail;
+	read_count = detail->regs_read_count;
+	write_count = detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, detail->regs_read,
+	       read_count * sizeof(detail->regs_read[0]));
+	memcpy(regs_write, detail->regs_write,
+	       write_count * sizeof(detail->regs_write[0]));
+
+	// explicit registers
+	cs_tricore *tc = &detail->tricore;
+	for (uint8_t i = 0; i < tc->op_count; i++) {
+		cs_tricore_op *op = &(tc->operands[i]);
+		switch ((int)op->type) {
+		case TRICORE_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+			    !arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+			    !arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		case TRICORE_OP_MEM:
+			// registers appeared in memory references always being read
+			if ((op->mem.base != ARM_REG_INVALID) &&
+			    !arr_exist(regs_read, read_count, op->mem.base)) {
+				regs_read[read_count] = (uint16_t)op->mem.base;
+				read_count++;
+			}
+		default:
+			break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+#endif
+}
+
+bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info)
+{
+	return TriCore_LLVM_getInstruction(handle, Bytes, ByteLen, MI, Size,
+					   Address, Info);
+}
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
+{
+	TriCore_LLVM_printInst(MI, MI->address, O);
+}
+
+const char *TriCore_getRegisterName(csh handle, unsigned int RegNo)
+{
+	return TriCore_LLVM_getRegisterName(RegNo);
+}
+
+#endif // CAPSTONE_HAS_TRICORE

package/deps/capstone/arch/TriCore/TriCoreMapping.h

@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifndef CS_TRICORE_MAP_H
+#define CS_TRICORE_MAP_H
+
+#include <capstone/capstone.h>
+
+// given internal insn id, return public instruction info
+void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *TriCore_insn_name(csh handle, unsigned int id);
+
+const char *TriCore_group_name(csh handle, unsigned int id);
+
+void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read,
+			uint8_t *regs_read_count, cs_regs regs_write,
+			uint8_t *regs_write_count);
+
+void TriCore_set_access(MCInst *MI);
+
+void TriCore_set_instr_map_data(MCInst *MI);
+
+bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+			    MCInst *MI, uint16_t *Size, uint64_t Address,
+			    void *Info);
+
+void TriCore_printInst(MCInst *MI, SStream *O, void *Info);
+
+const char *TriCore_getRegisterName(csh handle, unsigned int RegNo);
+
+#endif

package/deps/capstone/arch/TriCore/TriCoreModule.c

@@ -0,0 +1,44 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+
+#ifdef CAPSTONE_HAS_TRICORE
+
+#include "../../utils.h"
+#include "TriCoreMapping.h"
+#include "TriCoreModule.h"
+#include "TriCoreDisassembler.h"
+
+cs_err TRICORE_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	TriCore_init_mri(mri);
+	ud->printer = TriCore_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = TriCore_getInstruction;
+	ud->post_printer = NULL;
+
+	ud->reg_name = TriCore_getRegisterName;
+	ud->insn_id = TriCore_get_insn_id;
+	ud->insn_name = TriCore_insn_name;
+	ud->group_name = TriCore_group_name;
+
+#ifndef CAPSTONE_DIET
+	ud->reg_access = TriCore_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_SYNTAX)
+		handle->syntax = (int)value;
+
+	return CS_ERR_OK;
+}
+
+#endif

package/deps/capstone/arch/TriCore/TriCoreModule.h

@@ -0,0 +1,11 @@
+//
+// Created by aya on 3/4/23.
+//
+
+#ifndef CAPSTONE_TRICODEMODULE_H
+#define CAPSTONE_TRICODEMODULE_H
+
+cs_err TRICORE_global_init(cs_struct *ud);
+cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif // CAPSTONE_TRICODEMODULE_H

package/deps/capstone/arch/TriCore/TriCoreRegisterInfo.td

@@ -0,0 +1,153 @@
+//==-- TriCoreRegisterInfo.td - TriCore Register defs ------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the TriCore register file
+//===----------------------------------------------------------------------===//
+
+class TriCoreReg<string n, list<string> altNames = []> : Register<n, altNames> {
+  field bits<16> Num;
+  let Namespace = "TriCore";
+  let HWEncoding = Num;
+}
+
+// General Purpose Data Registers
+class TriCoreDataReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// General Purpose Address Registers
+class TriCoreAddrReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+// Program Status Register
+class TriCorePSReg<bits<16> num, string n, list<string> altNames = []> : TriCoreReg<n, altNames> {
+  let Num = num;
+}
+
+class TriCoreRegWithSubregs<bits<16> num, string n, list<Register> subregs>
+: RegisterWithSubRegs<n, subregs> {
+  field bits<16> Num;
+
+  let Num = num;
+  let Namespace = "TriCore";
+}
+
+//===----------------------------------------------------------------------===//
+//@Registers
+//===----------------------------------------------------------------------===//
+// The register string, such as "d0" or "d13" will show on "llvm-objdump -d"
+
+def D0 : TriCoreDataReg<0, "d0">, DwarfRegNum<[0]>;
+def D1 : TriCoreDataReg<1, "d1">, DwarfRegNum<[1]>;
+def D2 : TriCoreDataReg<2, "d2">, DwarfRegNum<[2]>;
+def D3 : TriCoreDataReg<3, "d3">, DwarfRegNum<[3]>;
+def D4 : TriCoreDataReg<4, "d4">, DwarfRegNum<[4]>;
+def D5 : TriCoreDataReg<5, "d5">, DwarfRegNum<[5]>;
+def D6 : TriCoreDataReg<6, "d6">, DwarfRegNum<[6]>;
+def D7 : TriCoreDataReg<7, "d7">, DwarfRegNum<[7]>;
+def D8 : TriCoreDataReg<8, "d8">, DwarfRegNum<[8]>;
+def D9 : TriCoreDataReg<9, "d9">, DwarfRegNum<[9]>;
+def D10 : TriCoreDataReg<10, "d10">, DwarfRegNum<[10]>;
+def D11 : TriCoreDataReg<11, "d11">, DwarfRegNum<[11]>;
+def D12 : TriCoreDataReg<12, "d12">, DwarfRegNum<[12]>;
+def D13 : TriCoreDataReg<13, "d13">, DwarfRegNum<[13]>;
+def D14 : TriCoreDataReg<14, "d14">, DwarfRegNum<[14]>;
+def D15 : TriCoreDataReg<15, "d15">, DwarfRegNum<[15]>;
+
+
+def A0 : TriCoreAddrReg<0, "a0">, DwarfRegNum<[16]>;
+def A1 : TriCoreAddrReg<1, "a1">, DwarfRegNum<[17]>;
+def A2 : TriCoreAddrReg<2, "a2">, DwarfRegNum<[18]>;
+def A3 : TriCoreAddrReg<3, "a3">, DwarfRegNum<[19]>;
+def A4 : TriCoreAddrReg<4, "a4">, DwarfRegNum<[20]>;
+def A5 : TriCoreAddrReg<5, "a5">, DwarfRegNum<[21]>;
+def A6 : TriCoreAddrReg<6, "a6">, DwarfRegNum<[22]>;
+def A7 : TriCoreAddrReg<7, "a7">, DwarfRegNum<[23]>;
+def A8 : TriCoreAddrReg<8, "a8">, DwarfRegNum<[24]>;
+def A9 : TriCoreAddrReg<9, "a9">, DwarfRegNum<[25]>;
+def A10 : TriCoreAddrReg<10, "sp", ["a10"]>, DwarfRegNum<[26]>;
+def A11 : TriCoreAddrReg<11, "a11">, DwarfRegNum<[27]>;
+def A12 : TriCoreAddrReg<12, "a12">, DwarfRegNum<[28]>;
+def A13 : TriCoreAddrReg<13, "a13">, DwarfRegNum<[29]>;
+def A14 : TriCoreAddrReg<14, "a14">, DwarfRegNum<[30]>;
+def A15 : TriCoreAddrReg<15, "a15">, DwarfRegNum<[31]>;
+
+let Namespace = "TriCore" in {
+def subreg_even : SubRegIndex<32>;
+def subreg_odd  : SubRegIndex<32, 32>;
+}
+
+//Extended 64-bit registers
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def E0 : TriCoreRegWithSubregs<0,   "e0",  [D0,D1]   >, DwarfRegNum<[32]>;
+def E2 : TriCoreRegWithSubregs<2,   "e2",  [D2,D3]   >, DwarfRegNum<[33]>;
+def E4 : TriCoreRegWithSubregs<4,   "e4",  [D4,D5]   >, DwarfRegNum<[34]>;
+def E6 : TriCoreRegWithSubregs<6,   "e6",  [D6,D7]   >, DwarfRegNum<[35]>;
+def E8 : TriCoreRegWithSubregs<8,   "e8",  [D8,D9]   >, DwarfRegNum<[36]>;
+def E10 : TriCoreRegWithSubregs<10, "e10", [D10,D11] >, DwarfRegNum<[37]>;
+def E12 : TriCoreRegWithSubregs<12, "e12", [D12,D13] >, DwarfRegNum<[38]>;
+def E14 : TriCoreRegWithSubregs<14, "e14", [D14,D15] >, DwarfRegNum<[39]>;
+}
+
+let SubRegIndices = [subreg_even, subreg_odd] in {
+def P0 : TriCoreRegWithSubregs<0,   "p0",  [A0,A1]   >, DwarfRegNum<[40]>;
+def P2 : TriCoreRegWithSubregs<2,   "p2",  [A2,A3]   >, DwarfRegNum<[41]>;
+def P4 : TriCoreRegWithSubregs<4,   "p4",  [A4,A5]   >, DwarfRegNum<[42]>;
+def P6 : TriCoreRegWithSubregs<6,   "p6",  [A6,A7]   >, DwarfRegNum<[43]>;
+def P8 : TriCoreRegWithSubregs<8,   "p8",  [A8,A9]   >, DwarfRegNum<[44]>;
+def P10 : TriCoreRegWithSubregs<10, "p10", [A10,A11] >, DwarfRegNum<[45]>;
+def P12 : TriCoreRegWithSubregs<12, "p12", [A12,A13] >, DwarfRegNum<[46]>;
+def P14 : TriCoreRegWithSubregs<14, "p14", [A14,A15] >, DwarfRegNum<[47]>;
+}
+
+//Program Status Information Registers
+def PSW  : TriCorePSReg<0, "psw">, DwarfRegNum<[40]>;
+def PCXI : TriCorePSReg<1, "pcxi">, DwarfRegNum<[41]>;
+def PC   : TriCorePSReg<2, "pc">, DwarfRegNum<[42]>;
+def FCX  : TriCorePSReg<3, "fcx">, DwarfRegNum<[43]>;
+
+//===----------------------------------------------------------------------===//
+//@Register Classes
+//===----------------------------------------------------------------------===//
+
+def RD : RegisterClass<"TriCore", [i32], 32, (add
+    D0,  D1,  D2,  D3,  D4,
+    D5,  D6,  D7,  D8,  D9,
+    D10, D11, D12, D13, D14,
+    D15)>;
+
+def RA : RegisterClass<"TriCore", [i32], 32, (add
+    A0,  A1,  A2,  A3,  A4,
+    A5,  A6,  A7,  A8,  A9,
+    A10, A11, A12, A13, A14,
+    A15)>;
+
+def RE : RegisterClass<"TriCore", [i64], 64, (add
+    E0, E2, E4,
+    E6, E8, E10,
+    E12, E14)>;
+
+def RP : RegisterClass<"TriCore", [i64], 64, (add
+    P0, P2, P4,
+    P6, P8, P10,
+    P12, P14)>;
+
+def PSRegs : RegisterClass<"TriCore", [i32], 32, (add
+    PSW, PCXI, PC, FCX)>;
+
+def TuplesPairAddrRegs : RegisterTuples<[subreg_even, subreg_odd],
+                                        [(add A0,A2,A4,A6,A8,A10,A12,A14),
+                                        (add A1,A3,A5,A7,A9,A11,A13,A15)]>;
+
+def PairAddrRegs : RegisterClass<"TriCore", [i64], 64,
+                                (add TuplesPairAddrRegs)> {
+    let Size = 64;
+}