hexcore-capstone 1.2.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/LICENSE +26 -0
- package/README.md +191 -0
- package/binding.gyp +168 -0
- package/deps/capstone/LEB128.h +38 -0
- package/deps/capstone/MCDisassembler.h +14 -0
- package/deps/capstone/MCFixedLenDisassembler.h +32 -0
- package/deps/capstone/MCInst.c +270 -0
- package/deps/capstone/MCInst.h +165 -0
- package/deps/capstone/MCInstrDesc.c +41 -0
- package/deps/capstone/MCInstrDesc.h +167 -0
- package/deps/capstone/MCRegisterInfo.c +151 -0
- package/deps/capstone/MCRegisterInfo.h +116 -0
- package/deps/capstone/Mapping.c +254 -0
- package/deps/capstone/Mapping.h +174 -0
- package/deps/capstone/MathExtras.h +442 -0
- package/deps/capstone/SStream.c +181 -0
- package/deps/capstone/SStream.h +40 -0
- package/deps/capstone/arch/AArch64/AArch64AddressingModes.h +945 -0
- package/deps/capstone/arch/AArch64/AArch64BaseInfo.c +77 -0
- package/deps/capstone/arch/AArch64/AArch64BaseInfo.h +585 -0
- package/deps/capstone/arch/AArch64/AArch64Disassembler.c +2280 -0
- package/deps/capstone/arch/AArch64/AArch64Disassembler.h +18 -0
- package/deps/capstone/arch/AArch64/AArch64GenAsmWriter.inc +26589 -0
- package/deps/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc +27322 -0
- package/deps/capstone/arch/AArch64/AArch64GenInstrInfo.inc +13194 -0
- package/deps/capstone/arch/AArch64/AArch64GenRegisterInfo.inc +3814 -0
- package/deps/capstone/arch/AArch64/AArch64GenRegisterName.inc +714 -0
- package/deps/capstone/arch/AArch64/AArch64GenRegisterV.inc +673 -0
- package/deps/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc +229 -0
- package/deps/capstone/arch/AArch64/AArch64GenSystemOperands.inc +2863 -0
- package/deps/capstone/arch/AArch64/AArch64GenSystemOperands_enum.inc +21 -0
- package/deps/capstone/arch/AArch64/AArch64InstPrinter.c +3029 -0
- package/deps/capstone/arch/AArch64/AArch64InstPrinter.h +28 -0
- package/deps/capstone/arch/AArch64/AArch64Mapping.c +883 -0
- package/deps/capstone/arch/AArch64/AArch64Mapping.h +43 -0
- package/deps/capstone/arch/AArch64/AArch64MappingInsn.inc +37790 -0
- package/deps/capstone/arch/AArch64/AArch64MappingInsnName.inc +1282 -0
- package/deps/capstone/arch/AArch64/AArch64MappingInsnOp.inc +26994 -0
- package/deps/capstone/arch/AArch64/AArch64Module.c +44 -0
- package/deps/capstone/arch/AArch64/AArch64Module.h +12 -0
- package/deps/capstone/arch/ARM/ARMAddressingModes.h +698 -0
- package/deps/capstone/arch/ARM/ARMBaseInfo.h +486 -0
- package/deps/capstone/arch/ARM/ARMDisassembler.c +5763 -0
- package/deps/capstone/arch/ARM/ARMDisassembler.h +18 -0
- package/deps/capstone/arch/ARM/ARMGenAsmWriter.inc +9545 -0
- package/deps/capstone/arch/ARM/ARMGenDisassemblerTables.inc +15185 -0
- package/deps/capstone/arch/ARM/ARMGenInstrInfo.inc +6632 -0
- package/deps/capstone/arch/ARM/ARMGenRegisterInfo.inc +2102 -0
- package/deps/capstone/arch/ARM/ARMGenRegisterName.inc +231 -0
- package/deps/capstone/arch/ARM/ARMGenRegisterName_digit.inc +231 -0
- package/deps/capstone/arch/ARM/ARMGenSubtargetInfo.inc +162 -0
- package/deps/capstone/arch/ARM/ARMGenSystemRegister.inc +270 -0
- package/deps/capstone/arch/ARM/ARMInstPrinter.c +3364 -0
- package/deps/capstone/arch/ARM/ARMInstPrinter.h +43 -0
- package/deps/capstone/arch/ARM/ARMMapping.c +551 -0
- package/deps/capstone/arch/ARM/ARMMapping.h +40 -0
- package/deps/capstone/arch/ARM/ARMMappingInsn.inc +18772 -0
- package/deps/capstone/arch/ARM/ARMMappingInsnName.inc +475 -0
- package/deps/capstone/arch/ARM/ARMMappingInsnOp.inc +10729 -0
- package/deps/capstone/arch/ARM/ARMModule.c +63 -0
- package/deps/capstone/arch/ARM/ARMModule.h +12 -0
- package/deps/capstone/arch/BPF/BPFConstants.h +88 -0
- package/deps/capstone/arch/BPF/BPFDisassembler.c +464 -0
- package/deps/capstone/arch/BPF/BPFDisassembler.h +27 -0
- package/deps/capstone/arch/BPF/BPFInstPrinter.c +285 -0
- package/deps/capstone/arch/BPF/BPFInstPrinter.h +16 -0
- package/deps/capstone/arch/BPF/BPFMapping.c +513 -0
- package/deps/capstone/arch/BPF/BPFMapping.h +21 -0
- package/deps/capstone/arch/BPF/BPFModule.c +34 -0
- package/deps/capstone/arch/BPF/BPFModule.h +12 -0
- package/deps/capstone/arch/EVM/EVMDisassembler.c +379 -0
- package/deps/capstone/arch/EVM/EVMDisassembler.h +12 -0
- package/deps/capstone/arch/EVM/EVMInstPrinter.c +20 -0
- package/deps/capstone/arch/EVM/EVMInstPrinter.h +17 -0
- package/deps/capstone/arch/EVM/EVMMapping.c +344 -0
- package/deps/capstone/arch/EVM/EVMMapping.h +8 -0
- package/deps/capstone/arch/EVM/EVMMappingInsn.inc +259 -0
- package/deps/capstone/arch/EVM/EVMModule.c +33 -0
- package/deps/capstone/arch/EVM/EVMModule.h +12 -0
- package/deps/capstone/arch/M680X/M680XDisassembler.c +2307 -0
- package/deps/capstone/arch/M680X/M680XDisassembler.h +17 -0
- package/deps/capstone/arch/M680X/M680XDisassemblerInternals.h +57 -0
- package/deps/capstone/arch/M680X/M680XInstPrinter.c +360 -0
- package/deps/capstone/arch/M680X/M680XInstPrinter.h +25 -0
- package/deps/capstone/arch/M680X/M680XModule.c +77 -0
- package/deps/capstone/arch/M680X/M680XModule.h +12 -0
- package/deps/capstone/arch/M680X/cpu12.inc +335 -0
- package/deps/capstone/arch/M680X/hcs08.inc +60 -0
- package/deps/capstone/arch/M680X/hd6301.inc +15 -0
- package/deps/capstone/arch/M680X/hd6309.inc +259 -0
- package/deps/capstone/arch/M680X/insn_props.inc +367 -0
- package/deps/capstone/arch/M680X/m6800.inc +277 -0
- package/deps/capstone/arch/M680X/m6801.inc +39 -0
- package/deps/capstone/arch/M680X/m6805.inc +277 -0
- package/deps/capstone/arch/M680X/m6808.inc +91 -0
- package/deps/capstone/arch/M680X/m6809.inc +352 -0
- package/deps/capstone/arch/M680X/m6811.inc +105 -0
- package/deps/capstone/arch/M68K/M68KDisassembler.c +3668 -0
- package/deps/capstone/arch/M68K/M68KDisassembler.h +30 -0
- package/deps/capstone/arch/M68K/M68KInstPrinter.c +387 -0
- package/deps/capstone/arch/M68K/M68KInstPrinter.h +21 -0
- package/deps/capstone/arch/M68K/M68KInstructionTable.inc +65540 -0
- package/deps/capstone/arch/M68K/M68KModule.c +42 -0
- package/deps/capstone/arch/M68K/M68KModule.h +12 -0
- package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.c +544 -0
- package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.h +22 -0
- package/deps/capstone/arch/MOS65XX/MOS65XXDisassemblerInternals.h +23 -0
- package/deps/capstone/arch/MOS65XX/MOS65XXModule.c +79 -0
- package/deps/capstone/arch/MOS65XX/MOS65XXModule.h +12 -0
- package/deps/capstone/arch/MOS65XX/instruction_info.inc +106 -0
- package/deps/capstone/arch/MOS65XX/m6502.inc +256 -0
- package/deps/capstone/arch/MOS65XX/m65816.inc +256 -0
- package/deps/capstone/arch/MOS65XX/m65c02.inc +256 -0
- package/deps/capstone/arch/MOS65XX/mw65c02.inc +256 -0
- package/deps/capstone/arch/Mips/MipsDisassembler.c +1794 -0
- package/deps/capstone/arch/Mips/MipsDisassembler.h +16 -0
- package/deps/capstone/arch/Mips/MipsGenAsmWriter.inc +5725 -0
- package/deps/capstone/arch/Mips/MipsGenDisassemblerTables.inc +6942 -0
- package/deps/capstone/arch/Mips/MipsGenInstrInfo.inc +1805 -0
- package/deps/capstone/arch/Mips/MipsGenRegisterInfo.inc +1679 -0
- package/deps/capstone/arch/Mips/MipsGenSubtargetInfo.inc +52 -0
- package/deps/capstone/arch/Mips/MipsInstPrinter.c +424 -0
- package/deps/capstone/arch/Mips/MipsInstPrinter.h +25 -0
- package/deps/capstone/arch/Mips/MipsMapping.c +1070 -0
- package/deps/capstone/arch/Mips/MipsMapping.h +25 -0
- package/deps/capstone/arch/Mips/MipsMappingInsn.inc +9315 -0
- package/deps/capstone/arch/Mips/MipsModule.c +52 -0
- package/deps/capstone/arch/Mips/MipsModule.h +12 -0
- package/deps/capstone/arch/PowerPC/PPCDisassembler.c +627 -0
- package/deps/capstone/arch/PowerPC/PPCDisassembler.h +17 -0
- package/deps/capstone/arch/PowerPC/PPCGenAsmWriter.inc +11451 -0
- package/deps/capstone/arch/PowerPC/PPCGenDisassemblerTables.inc +6886 -0
- package/deps/capstone/arch/PowerPC/PPCGenInstrInfo.inc +4772 -0
- package/deps/capstone/arch/PowerPC/PPCGenRegisterInfo.inc +1122 -0
- package/deps/capstone/arch/PowerPC/PPCGenRegisterName.inc +278 -0
- package/deps/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc +90 -0
- package/deps/capstone/arch/PowerPC/PPCInstPrinter.c +1238 -0
- package/deps/capstone/arch/PowerPC/PPCInstPrinter.h +15 -0
- package/deps/capstone/arch/PowerPC/PPCMapping.c +570 -0
- package/deps/capstone/arch/PowerPC/PPCMapping.h +40 -0
- package/deps/capstone/arch/PowerPC/PPCMappingInsn.inc +13220 -0
- package/deps/capstone/arch/PowerPC/PPCMappingInsnName.inc +1731 -0
- package/deps/capstone/arch/PowerPC/PPCModule.c +45 -0
- package/deps/capstone/arch/PowerPC/PPCModule.h +12 -0
- package/deps/capstone/arch/PowerPC/PPCPredicates.h +62 -0
- package/deps/capstone/arch/RISCV/RISCVBaseInfo.h +106 -0
- package/deps/capstone/arch/RISCV/RISCVDisassembler.c +433 -0
- package/deps/capstone/arch/RISCV/RISCVDisassembler.h +18 -0
- package/deps/capstone/arch/RISCV/RISCVGenAsmWriter.inc +2651 -0
- package/deps/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc +1776 -0
- package/deps/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc +275 -0
- package/deps/capstone/arch/RISCV/RISCVGenInstrInfo.inc +470 -0
- package/deps/capstone/arch/RISCV/RISCVGenRegisterInfo.inc +426 -0
- package/deps/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc +33 -0
- package/deps/capstone/arch/RISCV/RISCVInstPrinter.c +447 -0
- package/deps/capstone/arch/RISCV/RISCVInstPrinter.h +24 -0
- package/deps/capstone/arch/RISCV/RISCVMapping.c +366 -0
- package/deps/capstone/arch/RISCV/RISCVMapping.h +22 -0
- package/deps/capstone/arch/RISCV/RISCVMappingInsn.inc +1635 -0
- package/deps/capstone/arch/RISCV/RISCVModule.c +42 -0
- package/deps/capstone/arch/RISCV/RISCVModule.h +12 -0
- package/deps/capstone/arch/SH/SHDisassembler.c +2221 -0
- package/deps/capstone/arch/SH/SHDisassembler.h +19 -0
- package/deps/capstone/arch/SH/SHInsnTable.inc +66 -0
- package/deps/capstone/arch/SH/SHInstPrinter.c +438 -0
- package/deps/capstone/arch/SH/SHInstPrinter.h +23 -0
- package/deps/capstone/arch/SH/SHModule.c +39 -0
- package/deps/capstone/arch/SH/SHModule.h +12 -0
- package/deps/capstone/arch/SH/mktable.rb +390 -0
- package/deps/capstone/arch/Sparc/Sparc.h +63 -0
- package/deps/capstone/arch/Sparc/SparcDisassembler.c +500 -0
- package/deps/capstone/arch/Sparc/SparcDisassembler.h +17 -0
- package/deps/capstone/arch/Sparc/SparcGenAsmWriter.inc +5709 -0
- package/deps/capstone/arch/Sparc/SparcGenDisassemblerTables.inc +2028 -0
- package/deps/capstone/arch/Sparc/SparcGenInstrInfo.inc +514 -0
- package/deps/capstone/arch/Sparc/SparcGenRegisterInfo.inc +451 -0
- package/deps/capstone/arch/Sparc/SparcGenSubtargetInfo.inc +27 -0
- package/deps/capstone/arch/Sparc/SparcInstPrinter.c +446 -0
- package/deps/capstone/arch/Sparc/SparcInstPrinter.h +17 -0
- package/deps/capstone/arch/Sparc/SparcMapping.c +665 -0
- package/deps/capstone/arch/Sparc/SparcMapping.h +34 -0
- package/deps/capstone/arch/Sparc/SparcMappingInsn.inc +2643 -0
- package/deps/capstone/arch/Sparc/SparcModule.c +45 -0
- package/deps/capstone/arch/Sparc/SparcModule.h +12 -0
- package/deps/capstone/arch/SystemZ/SystemZDisassembler.c +484 -0
- package/deps/capstone/arch/SystemZ/SystemZDisassembler.h +17 -0
- package/deps/capstone/arch/SystemZ/SystemZGenAsmWriter.inc +11575 -0
- package/deps/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc +10262 -0
- package/deps/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc +2348 -0
- package/deps/capstone/arch/SystemZ/SystemZGenInstrInfo.inc +2820 -0
- package/deps/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc +741 -0
- package/deps/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc +49 -0
- package/deps/capstone/arch/SystemZ/SystemZInstPrinter.c +433 -0
- package/deps/capstone/arch/SystemZ/SystemZInstPrinter.h +15 -0
- package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.c +195 -0
- package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.h +51 -0
- package/deps/capstone/arch/SystemZ/SystemZMapping.c +479 -0
- package/deps/capstone/arch/SystemZ/SystemZMapping.h +23 -0
- package/deps/capstone/arch/SystemZ/SystemZMappingInsn.inc +14175 -0
- package/deps/capstone/arch/SystemZ/SystemZModule.c +44 -0
- package/deps/capstone/arch/SystemZ/SystemZModule.h +12 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c +628 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h +19 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +684 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc +1352 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc +298 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc +277 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c +572 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h +15 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.c +1926 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.h +26 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.c +39 -0
- package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.h +12 -0
- package/deps/capstone/arch/TriCore/TriCore.td +134 -0
- package/deps/capstone/arch/TriCore/TriCoreCallingConv.td +61 -0
- package/deps/capstone/arch/TriCore/TriCoreDisassembler.c +1655 -0
- package/deps/capstone/arch/TriCore/TriCoreDisassembler.h +18 -0
- package/deps/capstone/arch/TriCore/TriCoreGenAsmWriter.inc +3691 -0
- package/deps/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc +22 -0
- package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc +8938 -0
- package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc +404 -0
- package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc +7994 -0
- package/deps/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc +32 -0
- package/deps/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc +4044 -0
- package/deps/capstone/arch/TriCore/TriCoreGenInstrInfo.inc +2693 -0
- package/deps/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc +295 -0
- package/deps/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc +40 -0
- package/deps/capstone/arch/TriCore/TriCoreInstPrinter.c +488 -0
- package/deps/capstone/arch/TriCore/TriCoreInstrFormats.td +773 -0
- package/deps/capstone/arch/TriCore/TriCoreInstrInfo.td +1873 -0
- package/deps/capstone/arch/TriCore/TriCoreLinkage.h +21 -0
- package/deps/capstone/arch/TriCore/TriCoreMapping.c +241 -0
- package/deps/capstone/arch/TriCore/TriCoreMapping.h +32 -0
- package/deps/capstone/arch/TriCore/TriCoreModule.c +44 -0
- package/deps/capstone/arch/TriCore/TriCoreModule.h +11 -0
- package/deps/capstone/arch/TriCore/TriCoreRegisterInfo.td +153 -0
- package/deps/capstone/arch/WASM/WASMDisassembler.c +1009 -0
- package/deps/capstone/arch/WASM/WASMDisassembler.h +12 -0
- package/deps/capstone/arch/WASM/WASMInstPrinter.c +47 -0
- package/deps/capstone/arch/WASM/WASMInstPrinter.h +18 -0
- package/deps/capstone/arch/WASM/WASMMapping.c +333 -0
- package/deps/capstone/arch/WASM/WASMMapping.h +9 -0
- package/deps/capstone/arch/WASM/WASMModule.c +33 -0
- package/deps/capstone/arch/WASM/WASMModule.h +12 -0
- package/deps/capstone/arch/X86/X86ATTInstPrinter.c +997 -0
- package/deps/capstone/arch/X86/X86BaseInfo.h +50 -0
- package/deps/capstone/arch/X86/X86Disassembler.c +1033 -0
- package/deps/capstone/arch/X86/X86Disassembler.h +28 -0
- package/deps/capstone/arch/X86/X86DisassemblerDecoder.c +2358 -0
- package/deps/capstone/arch/X86/X86DisassemblerDecoder.h +725 -0
- package/deps/capstone/arch/X86/X86DisassemblerDecoderCommon.h +483 -0
- package/deps/capstone/arch/X86/X86GenAsmWriter.inc +49199 -0
- package/deps/capstone/arch/X86/X86GenAsmWriter1.inc +33196 -0
- package/deps/capstone/arch/X86/X86GenAsmWriter1_reduce.inc +2531 -0
- package/deps/capstone/arch/X86/X86GenAsmWriter_reduce.inc +2855 -0
- package/deps/capstone/arch/X86/X86GenDisassemblerTables.inc +112961 -0
- package/deps/capstone/arch/X86/X86GenDisassemblerTables2.inc +102151 -0
- package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc +28047 -0
- package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc +18827 -0
- package/deps/capstone/arch/X86/X86GenInstrInfo.inc +15158 -0
- package/deps/capstone/arch/X86/X86GenInstrInfo_reduce.inc +1564 -0
- package/deps/capstone/arch/X86/X86GenRegisterInfo.inc +1549 -0
- package/deps/capstone/arch/X86/X86GenRegisterName.inc +292 -0
- package/deps/capstone/arch/X86/X86GenRegisterName1.inc +291 -0
- package/deps/capstone/arch/X86/X86ImmSize.inc +335 -0
- package/deps/capstone/arch/X86/X86InstPrinter.h +26 -0
- package/deps/capstone/arch/X86/X86InstPrinterCommon.c +116 -0
- package/deps/capstone/arch/X86/X86InstPrinterCommon.h +16 -0
- package/deps/capstone/arch/X86/X86IntelInstPrinter.c +1061 -0
- package/deps/capstone/arch/X86/X86Lookup16.inc +16874 -0
- package/deps/capstone/arch/X86/X86Lookup16_reduce.inc +2308 -0
- package/deps/capstone/arch/X86/X86Mapping.c +2266 -0
- package/deps/capstone/arch/X86/X86Mapping.h +96 -0
- package/deps/capstone/arch/X86/X86MappingInsn.inc +105977 -0
- package/deps/capstone/arch/X86/X86MappingInsnName.inc +1527 -0
- package/deps/capstone/arch/X86/X86MappingInsnName_reduce.inc +348 -0
- package/deps/capstone/arch/X86/X86MappingInsnOp.inc +75700 -0
- package/deps/capstone/arch/X86/X86MappingInsnOp_reduce.inc +7729 -0
- package/deps/capstone/arch/X86/X86MappingInsn_reduce.inc +10819 -0
- package/deps/capstone/arch/X86/X86MappingReg.inc +280 -0
- package/deps/capstone/arch/X86/X86Module.c +94 -0
- package/deps/capstone/arch/X86/X86Module.h +12 -0
- package/deps/capstone/arch/XCore/XCoreDisassembler.c +794 -0
- package/deps/capstone/arch/XCore/XCoreDisassembler.h +17 -0
- package/deps/capstone/arch/XCore/XCoreGenAsmWriter.inc +772 -0
- package/deps/capstone/arch/XCore/XCoreGenDisassemblerTables.inc +853 -0
- package/deps/capstone/arch/XCore/XCoreGenInstrInfo.inc +267 -0
- package/deps/capstone/arch/XCore/XCoreGenRegisterInfo.inc +110 -0
- package/deps/capstone/arch/XCore/XCoreInstPrinter.c +250 -0
- package/deps/capstone/arch/XCore/XCoreInstPrinter.h +18 -0
- package/deps/capstone/arch/XCore/XCoreMapping.c +297 -0
- package/deps/capstone/arch/XCore/XCoreMapping.h +26 -0
- package/deps/capstone/arch/XCore/XCoreMappingInsn.inc +1287 -0
- package/deps/capstone/arch/XCore/XCoreModule.c +41 -0
- package/deps/capstone/arch/XCore/XCoreModule.h +12 -0
- package/deps/capstone/cs.c +1664 -0
- package/deps/capstone/cs_priv.h +101 -0
- package/deps/capstone/cs_simple_types.h +886 -0
- package/deps/capstone/include/capstone/arm.h +991 -0
- package/deps/capstone/include/capstone/arm64.h +3159 -0
- package/deps/capstone/include/capstone/bpf.h +209 -0
- package/deps/capstone/include/capstone/capstone.h +875 -0
- package/deps/capstone/include/capstone/evm.h +188 -0
- package/deps/capstone/include/capstone/m680x.h +537 -0
- package/deps/capstone/include/capstone/m68k.h +613 -0
- package/deps/capstone/include/capstone/mips.h +956 -0
- package/deps/capstone/include/capstone/mos65xx.h +204 -0
- package/deps/capstone/include/capstone/platform.h +122 -0
- package/deps/capstone/include/capstone/ppc.h +2108 -0
- package/deps/capstone/include/capstone/riscv.h +531 -0
- package/deps/capstone/include/capstone/sh.h +465 -0
- package/deps/capstone/include/capstone/sparc.h +520 -0
- package/deps/capstone/include/capstone/systemz.h +2601 -0
- package/deps/capstone/include/capstone/tms320c64x.h +359 -0
- package/deps/capstone/include/capstone/tricore.h +567 -0
- package/deps/capstone/include/capstone/wasm.h +250 -0
- package/deps/capstone/include/capstone/x86.h +1986 -0
- package/deps/capstone/include/capstone/xcore.h +235 -0
- package/deps/capstone/include/platform.h +110 -0
- package/deps/capstone/include/windowsce/intrin.h +12 -0
- package/deps/capstone/include/windowsce/stdint.h +133 -0
- package/deps/capstone/utils.c +140 -0
- package/deps/capstone/utils.h +54 -0
- package/index.d.ts +448 -0
- package/index.js +64 -0
- package/index.mjs +25 -0
- package/package.json +82 -0
- package/prebuilds/win32-x64/hexcore-capstone.node +0 -0
- package/src/capstone_wrapper.cpp +910 -0
- package/src/capstone_wrapper.h +147 -0
- package/src/disasm_async_worker.h +215 -0
- package/src/main.cpp +145 -0
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@@ -0,0 +1,1926 @@
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/* Capstone Disassembly Engine */
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/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
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#ifdef CAPSTONE_HAS_TMS320C64X
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../utils.h"
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#include "TMS320C64xMapping.h"
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#define GET_INSTRINFO_ENUM
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#include "TMS320C64xGenInstrInfo.inc"
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static const name_map reg_name_maps[] = {
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{ TMS320C64X_REG_INVALID, NULL },
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{ TMS320C64X_REG_AMR, "amr" },
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{ TMS320C64X_REG_CSR, "csr" },
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{ TMS320C64X_REG_DIER, "dier" },
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22
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{ TMS320C64X_REG_DNUM, "dnum" },
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{ TMS320C64X_REG_ECR, "ecr" },
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{ TMS320C64X_REG_GFPGFR, "gfpgfr" },
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{ TMS320C64X_REG_GPLYA, "gplya" },
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{ TMS320C64X_REG_GPLYB, "gplyb" },
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{ TMS320C64X_REG_ICR, "icr" },
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{ TMS320C64X_REG_IER, "ier" },
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{ TMS320C64X_REG_IERR, "ierr" },
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{ TMS320C64X_REG_ILC, "ilc" },
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{ TMS320C64X_REG_IRP, "irp" },
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{ TMS320C64X_REG_ISR, "isr" },
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33
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{ TMS320C64X_REG_ISTP, "istp" },
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{ TMS320C64X_REG_ITSR, "itsr" },
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{ TMS320C64X_REG_NRP, "nrp" },
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{ TMS320C64X_REG_NTSR, "ntsr" },
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{ TMS320C64X_REG_REP, "rep" },
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{ TMS320C64X_REG_RILC, "rilc" },
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{ TMS320C64X_REG_SSR, "ssr" },
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{ TMS320C64X_REG_TSCH, "tsch" },
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{ TMS320C64X_REG_TSCL, "tscl" },
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{ TMS320C64X_REG_TSR, "tsr" },
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{ TMS320C64X_REG_A0, "a0" },
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{ TMS320C64X_REG_A1, "a1" },
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{ TMS320C64X_REG_A2, "a2" },
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{ TMS320C64X_REG_A3, "a3" },
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{ TMS320C64X_REG_A4, "a4" },
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{ TMS320C64X_REG_A5, "a5" },
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{ TMS320C64X_REG_A6, "a6" },
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{ TMS320C64X_REG_A7, "a7" },
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{ TMS320C64X_REG_A8, "a8" },
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{ TMS320C64X_REG_A9, "a9" },
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{ TMS320C64X_REG_A10, "a10" },
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{ TMS320C64X_REG_A11, "a11" },
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{ TMS320C64X_REG_A12, "a12" },
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{ TMS320C64X_REG_A13, "a13" },
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{ TMS320C64X_REG_A14, "a14" },
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{ TMS320C64X_REG_A15, "a15" },
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{ TMS320C64X_REG_A16, "a16" },
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{ TMS320C64X_REG_A17, "a17" },
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{ TMS320C64X_REG_A18, "a18" },
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{ TMS320C64X_REG_A19, "a19" },
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{ TMS320C64X_REG_A20, "a20" },
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{ TMS320C64X_REG_A21, "a21" },
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{ TMS320C64X_REG_A22, "a22" },
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{ TMS320C64X_REG_A23, "a23" },
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{ TMS320C64X_REG_A24, "a24" },
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{ TMS320C64X_REG_A25, "a25" },
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{ TMS320C64X_REG_A26, "a26" },
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{ TMS320C64X_REG_A27, "a27" },
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{ TMS320C64X_REG_A28, "a28" },
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{ TMS320C64X_REG_A29, "a29" },
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{ TMS320C64X_REG_A30, "a30" },
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{ TMS320C64X_REG_A31, "a31" },
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{ TMS320C64X_REG_B0, "b0" },
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{ TMS320C64X_REG_B1, "b1" },
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{ TMS320C64X_REG_B2, "b2" },
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{ TMS320C64X_REG_B3, "b3" },
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{ TMS320C64X_REG_B4, "b4" },
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{ TMS320C64X_REG_B5, "b5" },
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{ TMS320C64X_REG_B6, "b6" },
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{ TMS320C64X_REG_B7, "b7" },
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{ TMS320C64X_REG_B8, "b8" },
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{ TMS320C64X_REG_B9, "b9" },
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{ TMS320C64X_REG_B10, "b10" },
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{ TMS320C64X_REG_B11, "b11" },
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{ TMS320C64X_REG_B12, "b12" },
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{ TMS320C64X_REG_B13, "b13" },
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{ TMS320C64X_REG_B14, "b14" },
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{ TMS320C64X_REG_B15, "b15" },
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{ TMS320C64X_REG_B16, "b16" },
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{ TMS320C64X_REG_B17, "b17" },
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{ TMS320C64X_REG_B18, "b18" },
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{ TMS320C64X_REG_B19, "b19" },
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{ TMS320C64X_REG_B20, "b20" },
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{ TMS320C64X_REG_B21, "b21" },
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{ TMS320C64X_REG_B22, "b22" },
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{ TMS320C64X_REG_B23, "b23" },
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{ TMS320C64X_REG_B24, "b24" },
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{ TMS320C64X_REG_B25, "b25" },
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{ TMS320C64X_REG_B26, "b26" },
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{ TMS320C64X_REG_B27, "b27" },
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{ TMS320C64X_REG_B28, "b28" },
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{ TMS320C64X_REG_B29, "b29" },
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{ TMS320C64X_REG_B30, "b30" },
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{ TMS320C64X_REG_B31, "b31" },
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{ TMS320C64X_REG_PCE1, "pce1" },
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};
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const char *TMS320C64x_reg_name(csh handle, unsigned int reg)
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{
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#ifndef CAPSTONE_DIET
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if (reg >= ARR_SIZE(reg_name_maps))
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return NULL;
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return reg_name_maps[reg].name;
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#else
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return NULL;
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#endif
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}
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tms320c64x_reg TMS320C64x_reg_id(char *name)
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{
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int i;
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for(i = 1; i < ARR_SIZE(reg_name_maps); i++) {
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if (!strcmp(name, reg_name_maps[i].name))
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return reg_name_maps[i].id;
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}
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return 0;
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}
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static const insn_map insns[] = {
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{
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0, 0,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ABS2_l2_rr, TMS320C64X_INS_ABS2,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ABS_l1_pp, TMS320C64X_INS_ABS,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ABS_l1_rr, TMS320C64X_INS_ABS,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADD2_d2_rrr, TMS320C64X_INS_ADD2,
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162
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADD2_l1_rrr_x2, TMS320C64X_INS_ADD2,
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168
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADD2_s1_rrr, TMS320C64X_INS_ADD2,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADD4_l1_rrr_x2, TMS320C64X_INS_ADD4,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADDAB_d1_rir, TMS320C64X_INS_ADDAB,
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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188
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#endif
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},
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190
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{
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TMS320C64x_ADDAB_d1_rrr, TMS320C64X_INS_ADDAB,
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192
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#ifndef CAPSTONE_DIET
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193
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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#endif
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},
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{
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TMS320C64x_ADDAD_d1_rir, TMS320C64X_INS_ADDAD,
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198
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#ifndef CAPSTONE_DIET
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199
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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200
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#endif
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},
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{
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TMS320C64x_ADDAD_d1_rrr, TMS320C64X_INS_ADDAD,
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204
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#ifndef CAPSTONE_DIET
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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206
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#endif
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},
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208
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{
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209
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TMS320C64x_ADDAH_d1_rir, TMS320C64X_INS_ADDAH,
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210
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#ifndef CAPSTONE_DIET
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211
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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212
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#endif
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213
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},
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214
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{
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215
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TMS320C64x_ADDAH_d1_rrr, TMS320C64X_INS_ADDAH,
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216
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#ifndef CAPSTONE_DIET
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217
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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218
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#endif
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219
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},
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220
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{
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221
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TMS320C64x_ADDAW_d1_rir, TMS320C64X_INS_ADDAW,
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222
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#ifndef CAPSTONE_DIET
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223
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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224
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+
#endif
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225
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},
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226
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{
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227
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TMS320C64x_ADDAW_d1_rrr, TMS320C64X_INS_ADDAW,
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228
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#ifndef CAPSTONE_DIET
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229
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
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230
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+
#endif
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231
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},
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232
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{
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233
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TMS320C64x_ADDKPC_s3_iir, TMS320C64X_INS_ADDKPC,
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234
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#ifndef CAPSTONE_DIET
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235
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
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236
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#endif
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237
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},
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238
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{
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239
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+
TMS320C64x_ADDK_s2_ir, TMS320C64X_INS_ADDK,
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240
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+
#ifndef CAPSTONE_DIET
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241
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{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
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242
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+
#endif
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243
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+
},
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244
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{
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245
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+
TMS320C64x_ADDU_l1_rpp, TMS320C64X_INS_ADDU,
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246
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+
#ifndef CAPSTONE_DIET
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247
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
248
|
+
#endif
|
|
249
|
+
},
|
|
250
|
+
{
|
|
251
|
+
TMS320C64x_ADDU_l1_rrp_x2, TMS320C64X_INS_ADDU,
|
|
252
|
+
#ifndef CAPSTONE_DIET
|
|
253
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
254
|
+
#endif
|
|
255
|
+
},
|
|
256
|
+
{
|
|
257
|
+
TMS320C64x_ADD_d1_rir, TMS320C64X_INS_ADD,
|
|
258
|
+
#ifndef CAPSTONE_DIET
|
|
259
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
260
|
+
#endif
|
|
261
|
+
},
|
|
262
|
+
{
|
|
263
|
+
TMS320C64x_ADD_d1_rrr, TMS320C64X_INS_ADD,
|
|
264
|
+
#ifndef CAPSTONE_DIET
|
|
265
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
266
|
+
#endif
|
|
267
|
+
},
|
|
268
|
+
{
|
|
269
|
+
TMS320C64x_ADD_d2_rir, TMS320C64X_INS_ADD,
|
|
270
|
+
#ifndef CAPSTONE_DIET
|
|
271
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
272
|
+
#endif
|
|
273
|
+
},
|
|
274
|
+
{
|
|
275
|
+
TMS320C64x_ADD_d2_rrr, TMS320C64X_INS_ADD,
|
|
276
|
+
#ifndef CAPSTONE_DIET
|
|
277
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
278
|
+
#endif
|
|
279
|
+
},
|
|
280
|
+
{
|
|
281
|
+
TMS320C64x_ADD_l1_ipp, TMS320C64X_INS_ADD,
|
|
282
|
+
#ifndef CAPSTONE_DIET
|
|
283
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
284
|
+
#endif
|
|
285
|
+
},
|
|
286
|
+
{
|
|
287
|
+
TMS320C64x_ADD_l1_irr, TMS320C64X_INS_ADD,
|
|
288
|
+
#ifndef CAPSTONE_DIET
|
|
289
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
290
|
+
#endif
|
|
291
|
+
},
|
|
292
|
+
{
|
|
293
|
+
TMS320C64x_ADD_l1_rpp, TMS320C64X_INS_ADD,
|
|
294
|
+
#ifndef CAPSTONE_DIET
|
|
295
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
296
|
+
#endif
|
|
297
|
+
},
|
|
298
|
+
{
|
|
299
|
+
TMS320C64x_ADD_l1_rrp_x2, TMS320C64X_INS_ADD,
|
|
300
|
+
#ifndef CAPSTONE_DIET
|
|
301
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
302
|
+
#endif
|
|
303
|
+
},
|
|
304
|
+
{
|
|
305
|
+
TMS320C64x_ADD_l1_rrr_x2, TMS320C64X_INS_ADD,
|
|
306
|
+
#ifndef CAPSTONE_DIET
|
|
307
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
308
|
+
#endif
|
|
309
|
+
},
|
|
310
|
+
{
|
|
311
|
+
TMS320C64x_ADD_s1_irr, TMS320C64X_INS_ADD,
|
|
312
|
+
#ifndef CAPSTONE_DIET
|
|
313
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
314
|
+
#endif
|
|
315
|
+
},
|
|
316
|
+
{
|
|
317
|
+
TMS320C64x_ADD_s1_rrr, TMS320C64X_INS_ADD,
|
|
318
|
+
#ifndef CAPSTONE_DIET
|
|
319
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
320
|
+
#endif
|
|
321
|
+
},
|
|
322
|
+
{
|
|
323
|
+
TMS320C64x_ANDN_d2_rrr, TMS320C64X_INS_ANDN,
|
|
324
|
+
#ifndef CAPSTONE_DIET
|
|
325
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
326
|
+
#endif
|
|
327
|
+
},
|
|
328
|
+
{
|
|
329
|
+
TMS320C64x_ANDN_l1_rrr_x2, TMS320C64X_INS_ANDN,
|
|
330
|
+
#ifndef CAPSTONE_DIET
|
|
331
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
332
|
+
#endif
|
|
333
|
+
},
|
|
334
|
+
{
|
|
335
|
+
TMS320C64x_ANDN_s4_rrr, TMS320C64X_INS_ANDN,
|
|
336
|
+
#ifndef CAPSTONE_DIET
|
|
337
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
338
|
+
#endif
|
|
339
|
+
},
|
|
340
|
+
{
|
|
341
|
+
TMS320C64x_AND_d2_rir, TMS320C64X_INS_AND,
|
|
342
|
+
#ifndef CAPSTONE_DIET
|
|
343
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
344
|
+
#endif
|
|
345
|
+
},
|
|
346
|
+
{
|
|
347
|
+
TMS320C64x_AND_d2_rrr, TMS320C64X_INS_AND,
|
|
348
|
+
#ifndef CAPSTONE_DIET
|
|
349
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
350
|
+
#endif
|
|
351
|
+
},
|
|
352
|
+
{
|
|
353
|
+
TMS320C64x_AND_l1_irr, TMS320C64X_INS_AND,
|
|
354
|
+
#ifndef CAPSTONE_DIET
|
|
355
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
356
|
+
#endif
|
|
357
|
+
},
|
|
358
|
+
{
|
|
359
|
+
TMS320C64x_AND_l1_rrr_x2, TMS320C64X_INS_AND,
|
|
360
|
+
#ifndef CAPSTONE_DIET
|
|
361
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
362
|
+
#endif
|
|
363
|
+
},
|
|
364
|
+
{
|
|
365
|
+
TMS320C64x_AND_s1_irr, TMS320C64X_INS_AND,
|
|
366
|
+
#ifndef CAPSTONE_DIET
|
|
367
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
368
|
+
#endif
|
|
369
|
+
},
|
|
370
|
+
{
|
|
371
|
+
TMS320C64x_AND_s1_rrr, TMS320C64X_INS_AND,
|
|
372
|
+
#ifndef CAPSTONE_DIET
|
|
373
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
374
|
+
#endif
|
|
375
|
+
},
|
|
376
|
+
{
|
|
377
|
+
TMS320C64x_AVG2_m1_rrr, TMS320C64X_INS_AVG2,
|
|
378
|
+
#ifndef CAPSTONE_DIET
|
|
379
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
380
|
+
#endif
|
|
381
|
+
},
|
|
382
|
+
{
|
|
383
|
+
TMS320C64x_AVGU4_m1_rrr, TMS320C64X_INS_AVGU4,
|
|
384
|
+
#ifndef CAPSTONE_DIET
|
|
385
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
386
|
+
#endif
|
|
387
|
+
},
|
|
388
|
+
{
|
|
389
|
+
TMS320C64x_BDEC_s8_ir, TMS320C64X_INS_BDEC,
|
|
390
|
+
#ifndef CAPSTONE_DIET
|
|
391
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
392
|
+
#endif
|
|
393
|
+
},
|
|
394
|
+
{
|
|
395
|
+
TMS320C64x_BITC4_m2_rr, TMS320C64X_INS_BITC4,
|
|
396
|
+
#ifndef CAPSTONE_DIET
|
|
397
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
398
|
+
#endif
|
|
399
|
+
},
|
|
400
|
+
{
|
|
401
|
+
TMS320C64x_BNOP_s10_ri, TMS320C64X_INS_BNOP,
|
|
402
|
+
#ifndef CAPSTONE_DIET
|
|
403
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
404
|
+
#endif
|
|
405
|
+
},
|
|
406
|
+
{
|
|
407
|
+
TMS320C64x_BNOP_s9_ii, TMS320C64X_INS_BNOP,
|
|
408
|
+
#ifndef CAPSTONE_DIET
|
|
409
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
410
|
+
#endif
|
|
411
|
+
},
|
|
412
|
+
{
|
|
413
|
+
TMS320C64x_BPOS_s8_ir, TMS320C64X_INS_BPOS,
|
|
414
|
+
#ifndef CAPSTONE_DIET
|
|
415
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
416
|
+
#endif
|
|
417
|
+
},
|
|
418
|
+
{
|
|
419
|
+
TMS320C64x_B_s5_i, TMS320C64X_INS_B,
|
|
420
|
+
#ifndef CAPSTONE_DIET
|
|
421
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
422
|
+
#endif
|
|
423
|
+
},
|
|
424
|
+
{
|
|
425
|
+
TMS320C64x_B_s6_r, TMS320C64X_INS_B,
|
|
426
|
+
#ifndef CAPSTONE_DIET
|
|
427
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
428
|
+
#endif
|
|
429
|
+
},
|
|
430
|
+
{
|
|
431
|
+
TMS320C64x_B_s7_irp, TMS320C64X_INS_B,
|
|
432
|
+
#ifndef CAPSTONE_DIET
|
|
433
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
434
|
+
#endif
|
|
435
|
+
},
|
|
436
|
+
{
|
|
437
|
+
TMS320C64x_B_s7_nrp, TMS320C64X_INS_B,
|
|
438
|
+
#ifndef CAPSTONE_DIET
|
|
439
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 1, 0
|
|
440
|
+
#endif
|
|
441
|
+
},
|
|
442
|
+
{
|
|
443
|
+
TMS320C64x_CLR_s15_riir, TMS320C64X_INS_CLR,
|
|
444
|
+
#ifndef CAPSTONE_DIET
|
|
445
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
446
|
+
#endif
|
|
447
|
+
},
|
|
448
|
+
{
|
|
449
|
+
TMS320C64x_CLR_s1_rrr, TMS320C64X_INS_CLR,
|
|
450
|
+
#ifndef CAPSTONE_DIET
|
|
451
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
452
|
+
#endif
|
|
453
|
+
},
|
|
454
|
+
{
|
|
455
|
+
TMS320C64x_CMPEQ2_s1_rrr, TMS320C64X_INS_CMPEQ2,
|
|
456
|
+
#ifndef CAPSTONE_DIET
|
|
457
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
458
|
+
#endif
|
|
459
|
+
},
|
|
460
|
+
{
|
|
461
|
+
TMS320C64x_CMPEQ4_s1_rrr, TMS320C64X_INS_CMPEQ4,
|
|
462
|
+
#ifndef CAPSTONE_DIET
|
|
463
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
464
|
+
#endif
|
|
465
|
+
},
|
|
466
|
+
{
|
|
467
|
+
TMS320C64x_CMPEQ_l1_ipr, TMS320C64X_INS_CMPEQ,
|
|
468
|
+
#ifndef CAPSTONE_DIET
|
|
469
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
470
|
+
#endif
|
|
471
|
+
},
|
|
472
|
+
{
|
|
473
|
+
TMS320C64x_CMPEQ_l1_irr, TMS320C64X_INS_CMPEQ,
|
|
474
|
+
#ifndef CAPSTONE_DIET
|
|
475
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
476
|
+
#endif
|
|
477
|
+
},
|
|
478
|
+
{
|
|
479
|
+
TMS320C64x_CMPEQ_l1_rpr, TMS320C64X_INS_CMPEQ,
|
|
480
|
+
#ifndef CAPSTONE_DIET
|
|
481
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
482
|
+
#endif
|
|
483
|
+
},
|
|
484
|
+
{
|
|
485
|
+
TMS320C64x_CMPEQ_l1_rrr_x2, TMS320C64X_INS_CMPEQ,
|
|
486
|
+
#ifndef CAPSTONE_DIET
|
|
487
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
488
|
+
#endif
|
|
489
|
+
},
|
|
490
|
+
{
|
|
491
|
+
TMS320C64x_CMPGT2_s1_rrr, TMS320C64X_INS_CMPGT2,
|
|
492
|
+
#ifndef CAPSTONE_DIET
|
|
493
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
494
|
+
#endif
|
|
495
|
+
},
|
|
496
|
+
{
|
|
497
|
+
TMS320C64x_CMPGTU4_s1_rrr, TMS320C64X_INS_CMPGTU4,
|
|
498
|
+
#ifndef CAPSTONE_DIET
|
|
499
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
500
|
+
#endif
|
|
501
|
+
},
|
|
502
|
+
{
|
|
503
|
+
TMS320C64x_CMPGT_l1_ipr, TMS320C64X_INS_CMPGT,
|
|
504
|
+
#ifndef CAPSTONE_DIET
|
|
505
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
506
|
+
#endif
|
|
507
|
+
},
|
|
508
|
+
{
|
|
509
|
+
TMS320C64x_CMPGT_l1_irr, TMS320C64X_INS_CMPGT,
|
|
510
|
+
#ifndef CAPSTONE_DIET
|
|
511
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
512
|
+
#endif
|
|
513
|
+
},
|
|
514
|
+
{
|
|
515
|
+
TMS320C64x_CMPGT_l1_rpr, TMS320C64X_INS_CMPGT,
|
|
516
|
+
#ifndef CAPSTONE_DIET
|
|
517
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
518
|
+
#endif
|
|
519
|
+
},
|
|
520
|
+
{
|
|
521
|
+
TMS320C64x_CMPGT_l1_rrr_x2, TMS320C64X_INS_CMPGT,
|
|
522
|
+
#ifndef CAPSTONE_DIET
|
|
523
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
524
|
+
#endif
|
|
525
|
+
},
|
|
526
|
+
{
|
|
527
|
+
TMS320C64x_CMPLTU_l1_ipr, TMS320C64X_INS_CMPLTU,
|
|
528
|
+
#ifndef CAPSTONE_DIET
|
|
529
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
530
|
+
#endif
|
|
531
|
+
},
|
|
532
|
+
{
|
|
533
|
+
TMS320C64x_CMPLTU_l1_irr, TMS320C64X_INS_CMPLTU,
|
|
534
|
+
#ifndef CAPSTONE_DIET
|
|
535
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
536
|
+
#endif
|
|
537
|
+
},
|
|
538
|
+
{
|
|
539
|
+
TMS320C64x_CMPLTU_l1_rpr, TMS320C64X_INS_CMPLTU,
|
|
540
|
+
#ifndef CAPSTONE_DIET
|
|
541
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
542
|
+
#endif
|
|
543
|
+
},
|
|
544
|
+
{
|
|
545
|
+
TMS320C64x_CMPLTU_l1_rrr_x2, TMS320C64X_INS_CMPLTU,
|
|
546
|
+
#ifndef CAPSTONE_DIET
|
|
547
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
548
|
+
#endif
|
|
549
|
+
},
|
|
550
|
+
{
|
|
551
|
+
TMS320C64x_CMPLT_l1_ipr, TMS320C64X_INS_CMPLT,
|
|
552
|
+
#ifndef CAPSTONE_DIET
|
|
553
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
554
|
+
#endif
|
|
555
|
+
},
|
|
556
|
+
{
|
|
557
|
+
TMS320C64x_CMPLT_l1_irr, TMS320C64X_INS_CMPLT,
|
|
558
|
+
#ifndef CAPSTONE_DIET
|
|
559
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
560
|
+
#endif
|
|
561
|
+
},
|
|
562
|
+
{
|
|
563
|
+
TMS320C64x_CMPLT_l1_rpr, TMS320C64X_INS_CMPLT,
|
|
564
|
+
#ifndef CAPSTONE_DIET
|
|
565
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
566
|
+
#endif
|
|
567
|
+
},
|
|
568
|
+
{
|
|
569
|
+
TMS320C64x_CMPLT_l1_rrr_x2, TMS320C64X_INS_CMPLT,
|
|
570
|
+
#ifndef CAPSTONE_DIET
|
|
571
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
572
|
+
#endif
|
|
573
|
+
},
|
|
574
|
+
{
|
|
575
|
+
TMS320C64x_DEAL_m2_rr, TMS320C64X_INS_DEAL,
|
|
576
|
+
#ifndef CAPSTONE_DIET
|
|
577
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
578
|
+
#endif
|
|
579
|
+
},
|
|
580
|
+
{
|
|
581
|
+
TMS320C64x_DOTP2_m1_rrp, TMS320C64X_INS_DOTP2,
|
|
582
|
+
#ifndef CAPSTONE_DIET
|
|
583
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
584
|
+
#endif
|
|
585
|
+
},
|
|
586
|
+
{
|
|
587
|
+
TMS320C64x_DOTP2_m1_rrr, TMS320C64X_INS_DOTP2,
|
|
588
|
+
#ifndef CAPSTONE_DIET
|
|
589
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
590
|
+
#endif
|
|
591
|
+
},
|
|
592
|
+
{
|
|
593
|
+
TMS320C64x_DOTPN2_m1_rrr, TMS320C64X_INS_DOTPN2,
|
|
594
|
+
#ifndef CAPSTONE_DIET
|
|
595
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
596
|
+
#endif
|
|
597
|
+
},
|
|
598
|
+
{
|
|
599
|
+
TMS320C64x_DOTPNRSU2_m1_rrr, TMS320C64X_INS_DOTPNRSU2,
|
|
600
|
+
#ifndef CAPSTONE_DIET
|
|
601
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
602
|
+
#endif
|
|
603
|
+
},
|
|
604
|
+
{
|
|
605
|
+
TMS320C64x_DOTPRSU2_m1_rrr, TMS320C64X_INS_DOTPRSU2,
|
|
606
|
+
#ifndef CAPSTONE_DIET
|
|
607
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
608
|
+
#endif
|
|
609
|
+
},
|
|
610
|
+
{
|
|
611
|
+
TMS320C64x_DOTPSU4_m1_rrr, TMS320C64X_INS_DOTPSU4,
|
|
612
|
+
#ifndef CAPSTONE_DIET
|
|
613
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
614
|
+
#endif
|
|
615
|
+
},
|
|
616
|
+
{
|
|
617
|
+
TMS320C64x_DOTPU4_m1_rrr, TMS320C64X_INS_DOTPU4,
|
|
618
|
+
#ifndef CAPSTONE_DIET
|
|
619
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
620
|
+
#endif
|
|
621
|
+
},
|
|
622
|
+
{
|
|
623
|
+
TMS320C64x_EXTU_s15_riir, TMS320C64X_INS_EXTU,
|
|
624
|
+
#ifndef CAPSTONE_DIET
|
|
625
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
626
|
+
#endif
|
|
627
|
+
},
|
|
628
|
+
{
|
|
629
|
+
TMS320C64x_EXTU_s1_rrr, TMS320C64X_INS_EXTU,
|
|
630
|
+
#ifndef CAPSTONE_DIET
|
|
631
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
632
|
+
#endif
|
|
633
|
+
},
|
|
634
|
+
{
|
|
635
|
+
TMS320C64x_EXT_s15_riir, TMS320C64X_INS_EXT,
|
|
636
|
+
#ifndef CAPSTONE_DIET
|
|
637
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
638
|
+
#endif
|
|
639
|
+
},
|
|
640
|
+
{
|
|
641
|
+
TMS320C64x_EXT_s1_rrr, TMS320C64X_INS_EXT,
|
|
642
|
+
#ifndef CAPSTONE_DIET
|
|
643
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
644
|
+
#endif
|
|
645
|
+
},
|
|
646
|
+
{
|
|
647
|
+
TMS320C64x_GMPGTU_l1_ipr, TMS320C64X_INS_GMPGTU,
|
|
648
|
+
#ifndef CAPSTONE_DIET
|
|
649
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
650
|
+
#endif
|
|
651
|
+
},
|
|
652
|
+
{
|
|
653
|
+
TMS320C64x_GMPGTU_l1_irr, TMS320C64X_INS_GMPGTU,
|
|
654
|
+
#ifndef CAPSTONE_DIET
|
|
655
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
656
|
+
#endif
|
|
657
|
+
},
|
|
658
|
+
{
|
|
659
|
+
TMS320C64x_GMPGTU_l1_rpr, TMS320C64X_INS_GMPGTU,
|
|
660
|
+
#ifndef CAPSTONE_DIET
|
|
661
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
662
|
+
#endif
|
|
663
|
+
},
|
|
664
|
+
{
|
|
665
|
+
TMS320C64x_GMPGTU_l1_rrr_x2, TMS320C64X_INS_GMPGTU,
|
|
666
|
+
#ifndef CAPSTONE_DIET
|
|
667
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
668
|
+
#endif
|
|
669
|
+
},
|
|
670
|
+
{
|
|
671
|
+
TMS320C64x_GMPY4_m1_rrr, TMS320C64X_INS_GMPY4,
|
|
672
|
+
#ifndef CAPSTONE_DIET
|
|
673
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
674
|
+
#endif
|
|
675
|
+
},
|
|
676
|
+
{
|
|
677
|
+
TMS320C64x_LDBU_d5_mr, TMS320C64X_INS_LDBU,
|
|
678
|
+
#ifndef CAPSTONE_DIET
|
|
679
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
680
|
+
#endif
|
|
681
|
+
},
|
|
682
|
+
{
|
|
683
|
+
TMS320C64x_LDBU_d6_mr, TMS320C64X_INS_LDBU,
|
|
684
|
+
#ifndef CAPSTONE_DIET
|
|
685
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
686
|
+
#endif
|
|
687
|
+
},
|
|
688
|
+
{
|
|
689
|
+
TMS320C64x_LDB_d5_mr, TMS320C64X_INS_LDB,
|
|
690
|
+
#ifndef CAPSTONE_DIET
|
|
691
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
692
|
+
#endif
|
|
693
|
+
},
|
|
694
|
+
{
|
|
695
|
+
TMS320C64x_LDB_d6_mr, TMS320C64X_INS_LDB,
|
|
696
|
+
#ifndef CAPSTONE_DIET
|
|
697
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
698
|
+
#endif
|
|
699
|
+
},
|
|
700
|
+
{
|
|
701
|
+
TMS320C64x_LDDW_d7_mp, TMS320C64X_INS_LDDW,
|
|
702
|
+
#ifndef CAPSTONE_DIET
|
|
703
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
704
|
+
#endif
|
|
705
|
+
},
|
|
706
|
+
{
|
|
707
|
+
TMS320C64x_LDHU_d5_mr, TMS320C64X_INS_LDHU,
|
|
708
|
+
#ifndef CAPSTONE_DIET
|
|
709
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
710
|
+
#endif
|
|
711
|
+
},
|
|
712
|
+
{
|
|
713
|
+
TMS320C64x_LDHU_d6_mr, TMS320C64X_INS_LDHU,
|
|
714
|
+
#ifndef CAPSTONE_DIET
|
|
715
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
716
|
+
#endif
|
|
717
|
+
},
|
|
718
|
+
{
|
|
719
|
+
TMS320C64x_LDH_d5_mr, TMS320C64X_INS_LDH,
|
|
720
|
+
#ifndef CAPSTONE_DIET
|
|
721
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
722
|
+
#endif
|
|
723
|
+
},
|
|
724
|
+
{
|
|
725
|
+
TMS320C64x_LDH_d6_mr, TMS320C64X_INS_LDH,
|
|
726
|
+
#ifndef CAPSTONE_DIET
|
|
727
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
728
|
+
#endif
|
|
729
|
+
},
|
|
730
|
+
{
|
|
731
|
+
TMS320C64x_LDNDW_d8_mp, TMS320C64X_INS_LDNDW,
|
|
732
|
+
#ifndef CAPSTONE_DIET
|
|
733
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
734
|
+
#endif
|
|
735
|
+
},
|
|
736
|
+
{
|
|
737
|
+
TMS320C64x_LDNW_d5_mr, TMS320C64X_INS_LDNW,
|
|
738
|
+
#ifndef CAPSTONE_DIET
|
|
739
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
740
|
+
#endif
|
|
741
|
+
},
|
|
742
|
+
{
|
|
743
|
+
TMS320C64x_LDW_d5_mr, TMS320C64X_INS_LDW,
|
|
744
|
+
#ifndef CAPSTONE_DIET
|
|
745
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
746
|
+
#endif
|
|
747
|
+
},
|
|
748
|
+
{
|
|
749
|
+
TMS320C64x_LDW_d6_mr, TMS320C64X_INS_LDW,
|
|
750
|
+
#ifndef CAPSTONE_DIET
|
|
751
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
752
|
+
#endif
|
|
753
|
+
},
|
|
754
|
+
{
|
|
755
|
+
TMS320C64x_LMBD_l1_irr, TMS320C64X_INS_LMBD,
|
|
756
|
+
#ifndef CAPSTONE_DIET
|
|
757
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
758
|
+
#endif
|
|
759
|
+
},
|
|
760
|
+
{
|
|
761
|
+
TMS320C64x_LMBD_l1_rrr_x2, TMS320C64X_INS_LMBD,
|
|
762
|
+
#ifndef CAPSTONE_DIET
|
|
763
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
764
|
+
#endif
|
|
765
|
+
},
|
|
766
|
+
{
|
|
767
|
+
TMS320C64x_MAX2_l1_rrr_x2, TMS320C64X_INS_MAX2,
|
|
768
|
+
#ifndef CAPSTONE_DIET
|
|
769
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
770
|
+
#endif
|
|
771
|
+
},
|
|
772
|
+
{
|
|
773
|
+
TMS320C64x_MAXU4_l1_rrr_x2, TMS320C64X_INS_MAXU4,
|
|
774
|
+
#ifndef CAPSTONE_DIET
|
|
775
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
776
|
+
#endif
|
|
777
|
+
},
|
|
778
|
+
{
|
|
779
|
+
TMS320C64x_MIN2_l1_rrr_x2, TMS320C64X_INS_MIN2,
|
|
780
|
+
#ifndef CAPSTONE_DIET
|
|
781
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
782
|
+
#endif
|
|
783
|
+
},
|
|
784
|
+
{
|
|
785
|
+
TMS320C64x_MINU4_l1_rrr_x2, TMS320C64X_INS_MINU4,
|
|
786
|
+
#ifndef CAPSTONE_DIET
|
|
787
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
788
|
+
#endif
|
|
789
|
+
},
|
|
790
|
+
{
|
|
791
|
+
TMS320C64x_MPY2_m1_rrp, TMS320C64X_INS_MPY2,
|
|
792
|
+
#ifndef CAPSTONE_DIET
|
|
793
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
794
|
+
#endif
|
|
795
|
+
},
|
|
796
|
+
{
|
|
797
|
+
TMS320C64x_MPYHIR_m1_rrr, TMS320C64X_INS_MPYHIR,
|
|
798
|
+
#ifndef CAPSTONE_DIET
|
|
799
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
800
|
+
#endif
|
|
801
|
+
},
|
|
802
|
+
{
|
|
803
|
+
TMS320C64x_MPYHI_m1_rrp, TMS320C64X_INS_MPYHI,
|
|
804
|
+
#ifndef CAPSTONE_DIET
|
|
805
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
806
|
+
#endif
|
|
807
|
+
},
|
|
808
|
+
{
|
|
809
|
+
TMS320C64x_MPYHLU_m4_rrr, TMS320C64X_INS_MPYHLU,
|
|
810
|
+
#ifndef CAPSTONE_DIET
|
|
811
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
812
|
+
#endif
|
|
813
|
+
},
|
|
814
|
+
{
|
|
815
|
+
TMS320C64x_MPYHL_m4_rrr, TMS320C64X_INS_MPYHL,
|
|
816
|
+
#ifndef CAPSTONE_DIET
|
|
817
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
818
|
+
#endif
|
|
819
|
+
},
|
|
820
|
+
{
|
|
821
|
+
TMS320C64x_MPYHSLU_m4_rrr, TMS320C64X_INS_MPYHSLU,
|
|
822
|
+
#ifndef CAPSTONE_DIET
|
|
823
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
824
|
+
#endif
|
|
825
|
+
},
|
|
826
|
+
{
|
|
827
|
+
TMS320C64x_MPYHSU_m4_rrr, TMS320C64X_INS_MPYHSU,
|
|
828
|
+
#ifndef CAPSTONE_DIET
|
|
829
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
830
|
+
#endif
|
|
831
|
+
},
|
|
832
|
+
{
|
|
833
|
+
TMS320C64x_MPYHULS_m4_rrr, TMS320C64X_INS_MPYHULS,
|
|
834
|
+
#ifndef CAPSTONE_DIET
|
|
835
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
836
|
+
#endif
|
|
837
|
+
},
|
|
838
|
+
{
|
|
839
|
+
TMS320C64x_MPYHUS_m4_rrr, TMS320C64X_INS_MPYHUS,
|
|
840
|
+
#ifndef CAPSTONE_DIET
|
|
841
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
842
|
+
#endif
|
|
843
|
+
},
|
|
844
|
+
{
|
|
845
|
+
TMS320C64x_MPYHU_m4_rrr, TMS320C64X_INS_MPYHU,
|
|
846
|
+
#ifndef CAPSTONE_DIET
|
|
847
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
848
|
+
#endif
|
|
849
|
+
},
|
|
850
|
+
{
|
|
851
|
+
TMS320C64x_MPYH_m4_rrr, TMS320C64X_INS_MPYH,
|
|
852
|
+
#ifndef CAPSTONE_DIET
|
|
853
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
854
|
+
#endif
|
|
855
|
+
},
|
|
856
|
+
{
|
|
857
|
+
TMS320C64x_MPYLHU_m4_rrr, TMS320C64X_INS_MPYLHU,
|
|
858
|
+
#ifndef CAPSTONE_DIET
|
|
859
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
860
|
+
#endif
|
|
861
|
+
},
|
|
862
|
+
{
|
|
863
|
+
TMS320C64x_MPYLH_m4_rrr, TMS320C64X_INS_MPYLH,
|
|
864
|
+
#ifndef CAPSTONE_DIET
|
|
865
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
866
|
+
#endif
|
|
867
|
+
},
|
|
868
|
+
{
|
|
869
|
+
TMS320C64x_MPYLIR_m1_rrr, TMS320C64X_INS_MPYLIR,
|
|
870
|
+
#ifndef CAPSTONE_DIET
|
|
871
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
872
|
+
#endif
|
|
873
|
+
},
|
|
874
|
+
{
|
|
875
|
+
TMS320C64x_MPYLI_m1_rrp, TMS320C64X_INS_MPYLI,
|
|
876
|
+
#ifndef CAPSTONE_DIET
|
|
877
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
878
|
+
#endif
|
|
879
|
+
},
|
|
880
|
+
{
|
|
881
|
+
TMS320C64x_MPYLSHU_m4_rrr, TMS320C64X_INS_MPYLSHU,
|
|
882
|
+
#ifndef CAPSTONE_DIET
|
|
883
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
884
|
+
#endif
|
|
885
|
+
},
|
|
886
|
+
{
|
|
887
|
+
TMS320C64x_MPYLUHS_m4_rrr, TMS320C64X_INS_MPYLUHS,
|
|
888
|
+
#ifndef CAPSTONE_DIET
|
|
889
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
890
|
+
#endif
|
|
891
|
+
},
|
|
892
|
+
{
|
|
893
|
+
TMS320C64x_MPYSU4_m1_rrp, TMS320C64X_INS_MPYSU4,
|
|
894
|
+
#ifndef CAPSTONE_DIET
|
|
895
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
896
|
+
#endif
|
|
897
|
+
},
|
|
898
|
+
{
|
|
899
|
+
TMS320C64x_MPYSU_m4_irr, TMS320C64X_INS_MPYSU,
|
|
900
|
+
#ifndef CAPSTONE_DIET
|
|
901
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
902
|
+
#endif
|
|
903
|
+
},
|
|
904
|
+
{
|
|
905
|
+
TMS320C64x_MPYSU_m4_rrr, TMS320C64X_INS_MPYSU,
|
|
906
|
+
#ifndef CAPSTONE_DIET
|
|
907
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
908
|
+
#endif
|
|
909
|
+
},
|
|
910
|
+
{
|
|
911
|
+
TMS320C64x_MPYU4_m1_rrp, TMS320C64X_INS_MPYU4,
|
|
912
|
+
#ifndef CAPSTONE_DIET
|
|
913
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
914
|
+
#endif
|
|
915
|
+
},
|
|
916
|
+
{
|
|
917
|
+
TMS320C64x_MPYUS_m4_rrr, TMS320C64X_INS_MPYUS,
|
|
918
|
+
#ifndef CAPSTONE_DIET
|
|
919
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
920
|
+
#endif
|
|
921
|
+
},
|
|
922
|
+
{
|
|
923
|
+
TMS320C64x_MPYU_m4_rrr, TMS320C64X_INS_MPYU,
|
|
924
|
+
#ifndef CAPSTONE_DIET
|
|
925
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
926
|
+
#endif
|
|
927
|
+
},
|
|
928
|
+
{
|
|
929
|
+
TMS320C64x_MPY_m4_irr, TMS320C64X_INS_MPY,
|
|
930
|
+
#ifndef CAPSTONE_DIET
|
|
931
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
932
|
+
#endif
|
|
933
|
+
},
|
|
934
|
+
{
|
|
935
|
+
TMS320C64x_MPY_m4_rrr, TMS320C64X_INS_MPY,
|
|
936
|
+
#ifndef CAPSTONE_DIET
|
|
937
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
938
|
+
#endif
|
|
939
|
+
},
|
|
940
|
+
{
|
|
941
|
+
TMS320C64x_MVC_s1_rr, TMS320C64X_INS_MVC,
|
|
942
|
+
#ifndef CAPSTONE_DIET
|
|
943
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
944
|
+
#endif
|
|
945
|
+
},
|
|
946
|
+
{
|
|
947
|
+
TMS320C64x_MVC_s1_rr2, TMS320C64X_INS_MVC,
|
|
948
|
+
#ifndef CAPSTONE_DIET
|
|
949
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
950
|
+
#endif
|
|
951
|
+
},
|
|
952
|
+
{
|
|
953
|
+
TMS320C64x_MVD_m2_rr, TMS320C64X_INS_MVD,
|
|
954
|
+
#ifndef CAPSTONE_DIET
|
|
955
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
956
|
+
#endif
|
|
957
|
+
},
|
|
958
|
+
{
|
|
959
|
+
TMS320C64x_MVKLH_s12_ir, TMS320C64X_INS_MVKLH,
|
|
960
|
+
#ifndef CAPSTONE_DIET
|
|
961
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
962
|
+
#endif
|
|
963
|
+
},
|
|
964
|
+
{
|
|
965
|
+
TMS320C64x_MVKL_s12_ir, TMS320C64X_INS_MVKL,
|
|
966
|
+
#ifndef CAPSTONE_DIET
|
|
967
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
968
|
+
#endif
|
|
969
|
+
},
|
|
970
|
+
{
|
|
971
|
+
TMS320C64x_MVK_d1_rr, TMS320C64X_INS_MVK,
|
|
972
|
+
#ifndef CAPSTONE_DIET
|
|
973
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
974
|
+
#endif
|
|
975
|
+
},
|
|
976
|
+
{
|
|
977
|
+
TMS320C64x_MVK_l2_ir, TMS320C64X_INS_MVK,
|
|
978
|
+
#ifndef CAPSTONE_DIET
|
|
979
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
980
|
+
#endif
|
|
981
|
+
},
|
|
982
|
+
{
|
|
983
|
+
TMS320C64x_NOP_n, TMS320C64X_INS_NOP,
|
|
984
|
+
#ifndef CAPSTONE_DIET
|
|
985
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_NO, 0 }, 0, 0
|
|
986
|
+
#endif
|
|
987
|
+
},
|
|
988
|
+
{
|
|
989
|
+
TMS320C64x_NORM_l1_pr, TMS320C64X_INS_NORM,
|
|
990
|
+
#ifndef CAPSTONE_DIET
|
|
991
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
992
|
+
#endif
|
|
993
|
+
},
|
|
994
|
+
{
|
|
995
|
+
TMS320C64x_NORM_l1_rr, TMS320C64X_INS_NORM,
|
|
996
|
+
#ifndef CAPSTONE_DIET
|
|
997
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
998
|
+
#endif
|
|
999
|
+
},
|
|
1000
|
+
{
|
|
1001
|
+
TMS320C64x_OR_d2_rir, TMS320C64X_INS_OR,
|
|
1002
|
+
#ifndef CAPSTONE_DIET
|
|
1003
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1004
|
+
#endif
|
|
1005
|
+
},
|
|
1006
|
+
{
|
|
1007
|
+
TMS320C64x_OR_d2_rrr, TMS320C64X_INS_OR,
|
|
1008
|
+
#ifndef CAPSTONE_DIET
|
|
1009
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1010
|
+
#endif
|
|
1011
|
+
},
|
|
1012
|
+
{
|
|
1013
|
+
TMS320C64x_OR_l1_irr, TMS320C64X_INS_OR,
|
|
1014
|
+
#ifndef CAPSTONE_DIET
|
|
1015
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1016
|
+
#endif
|
|
1017
|
+
},
|
|
1018
|
+
{
|
|
1019
|
+
TMS320C64x_OR_l1_rrr_x2, TMS320C64X_INS_OR,
|
|
1020
|
+
#ifndef CAPSTONE_DIET
|
|
1021
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1022
|
+
#endif
|
|
1023
|
+
},
|
|
1024
|
+
{
|
|
1025
|
+
TMS320C64x_OR_s1_irr, TMS320C64X_INS_OR,
|
|
1026
|
+
#ifndef CAPSTONE_DIET
|
|
1027
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1028
|
+
#endif
|
|
1029
|
+
},
|
|
1030
|
+
{
|
|
1031
|
+
TMS320C64x_OR_s1_rrr, TMS320C64X_INS_OR,
|
|
1032
|
+
#ifndef CAPSTONE_DIET
|
|
1033
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1034
|
+
#endif
|
|
1035
|
+
},
|
|
1036
|
+
{
|
|
1037
|
+
TMS320C64x_PACK2_l1_rrr_x2, TMS320C64X_INS_PACK2,
|
|
1038
|
+
#ifndef CAPSTONE_DIET
|
|
1039
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1040
|
+
#endif
|
|
1041
|
+
},
|
|
1042
|
+
{
|
|
1043
|
+
TMS320C64x_PACK2_s4_rrr, TMS320C64X_INS_PACK2,
|
|
1044
|
+
#ifndef CAPSTONE_DIET
|
|
1045
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1046
|
+
#endif
|
|
1047
|
+
},
|
|
1048
|
+
{
|
|
1049
|
+
TMS320C64x_PACKH2_l1_rrr_x2, TMS320C64X_INS_PACKH2,
|
|
1050
|
+
#ifndef CAPSTONE_DIET
|
|
1051
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1052
|
+
#endif
|
|
1053
|
+
},
|
|
1054
|
+
{
|
|
1055
|
+
TMS320C64x_PACKH2_s1_rrr, TMS320C64X_INS_PACKH2,
|
|
1056
|
+
#ifndef CAPSTONE_DIET
|
|
1057
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1058
|
+
#endif
|
|
1059
|
+
},
|
|
1060
|
+
{
|
|
1061
|
+
TMS320C64x_PACKH4_l1_rrr_x2, TMS320C64X_INS_PACKH4,
|
|
1062
|
+
#ifndef CAPSTONE_DIET
|
|
1063
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1064
|
+
#endif
|
|
1065
|
+
},
|
|
1066
|
+
{
|
|
1067
|
+
TMS320C64x_PACKHL2_l1_rrr_x2, TMS320C64X_INS_PACKHL2,
|
|
1068
|
+
#ifndef CAPSTONE_DIET
|
|
1069
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1070
|
+
#endif
|
|
1071
|
+
},
|
|
1072
|
+
{
|
|
1073
|
+
TMS320C64x_PACKHL2_s1_rrr, TMS320C64X_INS_PACKHL2,
|
|
1074
|
+
#ifndef CAPSTONE_DIET
|
|
1075
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1076
|
+
#endif
|
|
1077
|
+
},
|
|
1078
|
+
{
|
|
1079
|
+
TMS320C64x_PACKL4_l1_rrr_x2, TMS320C64X_INS_PACKL4,
|
|
1080
|
+
#ifndef CAPSTONE_DIET
|
|
1081
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1082
|
+
#endif
|
|
1083
|
+
},
|
|
1084
|
+
{
|
|
1085
|
+
TMS320C64x_PACKLH2_l1_rrr_x2, TMS320C64X_INS_PACKLH2,
|
|
1086
|
+
#ifndef CAPSTONE_DIET
|
|
1087
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1088
|
+
#endif
|
|
1089
|
+
},
|
|
1090
|
+
{
|
|
1091
|
+
TMS320C64x_PACKLH2_s1_rrr, TMS320C64X_INS_PACKLH2,
|
|
1092
|
+
#ifndef CAPSTONE_DIET
|
|
1093
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1094
|
+
#endif
|
|
1095
|
+
},
|
|
1096
|
+
{
|
|
1097
|
+
TMS320C64x_ROTL_m1_rir, TMS320C64X_INS_ROTL,
|
|
1098
|
+
#ifndef CAPSTONE_DIET
|
|
1099
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1100
|
+
#endif
|
|
1101
|
+
},
|
|
1102
|
+
{
|
|
1103
|
+
TMS320C64x_ROTL_m1_rrr, TMS320C64X_INS_ROTL,
|
|
1104
|
+
#ifndef CAPSTONE_DIET
|
|
1105
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1106
|
+
#endif
|
|
1107
|
+
},
|
|
1108
|
+
{
|
|
1109
|
+
TMS320C64x_SADD2_s4_rrr, TMS320C64X_INS_SADD2,
|
|
1110
|
+
#ifndef CAPSTONE_DIET
|
|
1111
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1112
|
+
#endif
|
|
1113
|
+
},
|
|
1114
|
+
{
|
|
1115
|
+
TMS320C64x_SADDU4_s4_rrr, TMS320C64X_INS_SADDU4,
|
|
1116
|
+
#ifndef CAPSTONE_DIET
|
|
1117
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1118
|
+
#endif
|
|
1119
|
+
},
|
|
1120
|
+
{
|
|
1121
|
+
TMS320C64x_SADDUS2_s4_rrr, TMS320C64X_INS_SADDUS2,
|
|
1122
|
+
#ifndef CAPSTONE_DIET
|
|
1123
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1124
|
+
#endif
|
|
1125
|
+
},
|
|
1126
|
+
{
|
|
1127
|
+
TMS320C64x_SADD_l1_ipp, TMS320C64X_INS_SADD,
|
|
1128
|
+
#ifndef CAPSTONE_DIET
|
|
1129
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1130
|
+
#endif
|
|
1131
|
+
},
|
|
1132
|
+
{
|
|
1133
|
+
TMS320C64x_SADD_l1_irr, TMS320C64X_INS_SADD,
|
|
1134
|
+
#ifndef CAPSTONE_DIET
|
|
1135
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1136
|
+
#endif
|
|
1137
|
+
},
|
|
1138
|
+
{
|
|
1139
|
+
TMS320C64x_SADD_l1_rpp, TMS320C64X_INS_SADD,
|
|
1140
|
+
#ifndef CAPSTONE_DIET
|
|
1141
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1142
|
+
#endif
|
|
1143
|
+
},
|
|
1144
|
+
{
|
|
1145
|
+
TMS320C64x_SADD_l1_rrr_x2, TMS320C64X_INS_SADD,
|
|
1146
|
+
#ifndef CAPSTONE_DIET
|
|
1147
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1148
|
+
#endif
|
|
1149
|
+
},
|
|
1150
|
+
{
|
|
1151
|
+
TMS320C64x_SADD_s1_rrr, TMS320C64X_INS_SADD,
|
|
1152
|
+
#ifndef CAPSTONE_DIET
|
|
1153
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1154
|
+
#endif
|
|
1155
|
+
},
|
|
1156
|
+
{
|
|
1157
|
+
TMS320C64x_SAT_l1_pr, TMS320C64X_INS_SAT,
|
|
1158
|
+
#ifndef CAPSTONE_DIET
|
|
1159
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1160
|
+
#endif
|
|
1161
|
+
},
|
|
1162
|
+
{
|
|
1163
|
+
TMS320C64x_SET_s15_riir, TMS320C64X_INS_SET,
|
|
1164
|
+
#ifndef CAPSTONE_DIET
|
|
1165
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1166
|
+
#endif
|
|
1167
|
+
},
|
|
1168
|
+
{
|
|
1169
|
+
TMS320C64x_SET_s1_rrr, TMS320C64X_INS_SET,
|
|
1170
|
+
#ifndef CAPSTONE_DIET
|
|
1171
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1172
|
+
#endif
|
|
1173
|
+
},
|
|
1174
|
+
{
|
|
1175
|
+
TMS320C64x_SHFL_m2_rr, TMS320C64X_INS_SHFL,
|
|
1176
|
+
#ifndef CAPSTONE_DIET
|
|
1177
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1178
|
+
#endif
|
|
1179
|
+
},
|
|
1180
|
+
{
|
|
1181
|
+
TMS320C64x_SHLMB_l1_rrr_x2, TMS320C64X_INS_SHLMB,
|
|
1182
|
+
#ifndef CAPSTONE_DIET
|
|
1183
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1184
|
+
#endif
|
|
1185
|
+
},
|
|
1186
|
+
{
|
|
1187
|
+
TMS320C64x_SHLMB_s4_rrr, TMS320C64X_INS_SHLMB,
|
|
1188
|
+
#ifndef CAPSTONE_DIET
|
|
1189
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1190
|
+
#endif
|
|
1191
|
+
},
|
|
1192
|
+
{
|
|
1193
|
+
TMS320C64x_SHL_s1_pip, TMS320C64X_INS_SHL,
|
|
1194
|
+
#ifndef CAPSTONE_DIET
|
|
1195
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1196
|
+
#endif
|
|
1197
|
+
},
|
|
1198
|
+
{
|
|
1199
|
+
TMS320C64x_SHL_s1_prp, TMS320C64X_INS_SHL,
|
|
1200
|
+
#ifndef CAPSTONE_DIET
|
|
1201
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1202
|
+
#endif
|
|
1203
|
+
},
|
|
1204
|
+
{
|
|
1205
|
+
TMS320C64x_SHL_s1_rip, TMS320C64X_INS_SHL,
|
|
1206
|
+
#ifndef CAPSTONE_DIET
|
|
1207
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1208
|
+
#endif
|
|
1209
|
+
},
|
|
1210
|
+
{
|
|
1211
|
+
TMS320C64x_SHL_s1_rir, TMS320C64X_INS_SHL,
|
|
1212
|
+
#ifndef CAPSTONE_DIET
|
|
1213
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1214
|
+
#endif
|
|
1215
|
+
},
|
|
1216
|
+
{
|
|
1217
|
+
TMS320C64x_SHL_s1_rrp, TMS320C64X_INS_SHL,
|
|
1218
|
+
#ifndef CAPSTONE_DIET
|
|
1219
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1220
|
+
#endif
|
|
1221
|
+
},
|
|
1222
|
+
{
|
|
1223
|
+
TMS320C64x_SHL_s1_rrr, TMS320C64X_INS_SHL,
|
|
1224
|
+
#ifndef CAPSTONE_DIET
|
|
1225
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1226
|
+
#endif
|
|
1227
|
+
},
|
|
1228
|
+
{
|
|
1229
|
+
TMS320C64x_SHR2_s1_rir, TMS320C64X_INS_SHR2,
|
|
1230
|
+
#ifndef CAPSTONE_DIET
|
|
1231
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1232
|
+
#endif
|
|
1233
|
+
},
|
|
1234
|
+
{
|
|
1235
|
+
TMS320C64x_SHR2_s4_rrr, TMS320C64X_INS_SHR2,
|
|
1236
|
+
#ifndef CAPSTONE_DIET
|
|
1237
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1238
|
+
#endif
|
|
1239
|
+
},
|
|
1240
|
+
{
|
|
1241
|
+
TMS320C64x_SHRMB_l1_rrr_x2, TMS320C64X_INS_SHRMB,
|
|
1242
|
+
#ifndef CAPSTONE_DIET
|
|
1243
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1244
|
+
#endif
|
|
1245
|
+
},
|
|
1246
|
+
{
|
|
1247
|
+
TMS320C64x_SHRMB_s4_rrr, TMS320C64X_INS_SHRMB,
|
|
1248
|
+
#ifndef CAPSTONE_DIET
|
|
1249
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1250
|
+
#endif
|
|
1251
|
+
},
|
|
1252
|
+
{
|
|
1253
|
+
TMS320C64x_SHRU2_s1_rir, TMS320C64X_INS_SHRU2,
|
|
1254
|
+
#ifndef CAPSTONE_DIET
|
|
1255
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1256
|
+
#endif
|
|
1257
|
+
},
|
|
1258
|
+
{
|
|
1259
|
+
TMS320C64x_SHRU2_s4_rrr, TMS320C64X_INS_SHRU2,
|
|
1260
|
+
#ifndef CAPSTONE_DIET
|
|
1261
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1262
|
+
#endif
|
|
1263
|
+
},
|
|
1264
|
+
{
|
|
1265
|
+
TMS320C64x_SHRU_s1_pip, TMS320C64X_INS_SHRU,
|
|
1266
|
+
#ifndef CAPSTONE_DIET
|
|
1267
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1268
|
+
#endif
|
|
1269
|
+
},
|
|
1270
|
+
{
|
|
1271
|
+
TMS320C64x_SHRU_s1_prp, TMS320C64X_INS_SHRU,
|
|
1272
|
+
#ifndef CAPSTONE_DIET
|
|
1273
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1274
|
+
#endif
|
|
1275
|
+
},
|
|
1276
|
+
{
|
|
1277
|
+
TMS320C64x_SHRU_s1_rir, TMS320C64X_INS_SHRU,
|
|
1278
|
+
#ifndef CAPSTONE_DIET
|
|
1279
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1280
|
+
#endif
|
|
1281
|
+
},
|
|
1282
|
+
{
|
|
1283
|
+
TMS320C64x_SHRU_s1_rrr, TMS320C64X_INS_SHRU,
|
|
1284
|
+
#ifndef CAPSTONE_DIET
|
|
1285
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1286
|
+
#endif
|
|
1287
|
+
},
|
|
1288
|
+
{
|
|
1289
|
+
TMS320C64x_SHR_s1_pip, TMS320C64X_INS_SHR,
|
|
1290
|
+
#ifndef CAPSTONE_DIET
|
|
1291
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1292
|
+
#endif
|
|
1293
|
+
},
|
|
1294
|
+
{
|
|
1295
|
+
TMS320C64x_SHR_s1_prp, TMS320C64X_INS_SHR,
|
|
1296
|
+
#ifndef CAPSTONE_DIET
|
|
1297
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1298
|
+
#endif
|
|
1299
|
+
},
|
|
1300
|
+
{
|
|
1301
|
+
TMS320C64x_SHR_s1_rir, TMS320C64X_INS_SHR,
|
|
1302
|
+
#ifndef CAPSTONE_DIET
|
|
1303
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1304
|
+
#endif
|
|
1305
|
+
},
|
|
1306
|
+
{
|
|
1307
|
+
TMS320C64x_SHR_s1_rrr, TMS320C64X_INS_SHR,
|
|
1308
|
+
#ifndef CAPSTONE_DIET
|
|
1309
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1310
|
+
#endif
|
|
1311
|
+
},
|
|
1312
|
+
{
|
|
1313
|
+
TMS320C64x_SMPY2_m1_rrp, TMS320C64X_INS_SMPY2,
|
|
1314
|
+
#ifndef CAPSTONE_DIET
|
|
1315
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1316
|
+
#endif
|
|
1317
|
+
},
|
|
1318
|
+
{
|
|
1319
|
+
TMS320C64x_SMPYHL_m4_rrr, TMS320C64X_INS_SMPYHL,
|
|
1320
|
+
#ifndef CAPSTONE_DIET
|
|
1321
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1322
|
+
#endif
|
|
1323
|
+
},
|
|
1324
|
+
{
|
|
1325
|
+
TMS320C64x_SMPYH_m4_rrr, TMS320C64X_INS_SMPYH,
|
|
1326
|
+
#ifndef CAPSTONE_DIET
|
|
1327
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1328
|
+
#endif
|
|
1329
|
+
},
|
|
1330
|
+
{
|
|
1331
|
+
TMS320C64x_SMPYLH_m4_rrr, TMS320C64X_INS_SMPYLH,
|
|
1332
|
+
#ifndef CAPSTONE_DIET
|
|
1333
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1334
|
+
#endif
|
|
1335
|
+
},
|
|
1336
|
+
{
|
|
1337
|
+
TMS320C64x_SMPY_m4_rrr, TMS320C64X_INS_SMPY,
|
|
1338
|
+
#ifndef CAPSTONE_DIET
|
|
1339
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1340
|
+
#endif
|
|
1341
|
+
},
|
|
1342
|
+
{
|
|
1343
|
+
TMS320C64x_SPACK2_s4_rrr, TMS320C64X_INS_SPACK2,
|
|
1344
|
+
#ifndef CAPSTONE_DIET
|
|
1345
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1346
|
+
#endif
|
|
1347
|
+
},
|
|
1348
|
+
{
|
|
1349
|
+
TMS320C64x_SPACKU4_s4_rrr, TMS320C64X_INS_SPACKU4,
|
|
1350
|
+
#ifndef CAPSTONE_DIET
|
|
1351
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1352
|
+
#endif
|
|
1353
|
+
},
|
|
1354
|
+
{
|
|
1355
|
+
TMS320C64x_SSHL_s1_rir, TMS320C64X_INS_SSHL,
|
|
1356
|
+
#ifndef CAPSTONE_DIET
|
|
1357
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1358
|
+
#endif
|
|
1359
|
+
},
|
|
1360
|
+
{
|
|
1361
|
+
TMS320C64x_SSHL_s1_rrr, TMS320C64X_INS_SSHL,
|
|
1362
|
+
#ifndef CAPSTONE_DIET
|
|
1363
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1364
|
+
#endif
|
|
1365
|
+
},
|
|
1366
|
+
{
|
|
1367
|
+
TMS320C64x_SSHVL_m1_rrr, TMS320C64X_INS_SSHVL,
|
|
1368
|
+
#ifndef CAPSTONE_DIET
|
|
1369
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1370
|
+
#endif
|
|
1371
|
+
},
|
|
1372
|
+
{
|
|
1373
|
+
TMS320C64x_SSHVR_m1_rrr, TMS320C64X_INS_SSHVR,
|
|
1374
|
+
#ifndef CAPSTONE_DIET
|
|
1375
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1376
|
+
#endif
|
|
1377
|
+
},
|
|
1378
|
+
{
|
|
1379
|
+
TMS320C64x_SSUB_l1_ipp, TMS320C64X_INS_SSUB,
|
|
1380
|
+
#ifndef CAPSTONE_DIET
|
|
1381
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1382
|
+
#endif
|
|
1383
|
+
},
|
|
1384
|
+
{
|
|
1385
|
+
TMS320C64x_SSUB_l1_irr, TMS320C64X_INS_SSUB,
|
|
1386
|
+
#ifndef CAPSTONE_DIET
|
|
1387
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1388
|
+
#endif
|
|
1389
|
+
},
|
|
1390
|
+
{
|
|
1391
|
+
TMS320C64x_SSUB_l1_rrr_x1, TMS320C64X_INS_SSUB,
|
|
1392
|
+
#ifndef CAPSTONE_DIET
|
|
1393
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1394
|
+
#endif
|
|
1395
|
+
},
|
|
1396
|
+
{
|
|
1397
|
+
TMS320C64x_SSUB_l1_rrr_x2, TMS320C64X_INS_SSUB,
|
|
1398
|
+
#ifndef CAPSTONE_DIET
|
|
1399
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1400
|
+
#endif
|
|
1401
|
+
},
|
|
1402
|
+
{
|
|
1403
|
+
TMS320C64x_STB_d5_rm, TMS320C64X_INS_STB,
|
|
1404
|
+
#ifndef CAPSTONE_DIET
|
|
1405
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1406
|
+
#endif
|
|
1407
|
+
},
|
|
1408
|
+
{
|
|
1409
|
+
TMS320C64x_STB_d6_rm, TMS320C64X_INS_STB,
|
|
1410
|
+
#ifndef CAPSTONE_DIET
|
|
1411
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1412
|
+
#endif
|
|
1413
|
+
},
|
|
1414
|
+
{
|
|
1415
|
+
TMS320C64x_STDW_d7_pm, TMS320C64X_INS_STDW,
|
|
1416
|
+
#ifndef CAPSTONE_DIET
|
|
1417
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1418
|
+
#endif
|
|
1419
|
+
},
|
|
1420
|
+
{
|
|
1421
|
+
TMS320C64x_STH_d5_rm, TMS320C64X_INS_STH,
|
|
1422
|
+
#ifndef CAPSTONE_DIET
|
|
1423
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1424
|
+
#endif
|
|
1425
|
+
},
|
|
1426
|
+
{
|
|
1427
|
+
TMS320C64x_STH_d6_rm, TMS320C64X_INS_STH,
|
|
1428
|
+
#ifndef CAPSTONE_DIET
|
|
1429
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1430
|
+
#endif
|
|
1431
|
+
},
|
|
1432
|
+
{
|
|
1433
|
+
TMS320C64x_STNDW_d8_pm, TMS320C64X_INS_STNDW,
|
|
1434
|
+
#ifndef CAPSTONE_DIET
|
|
1435
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1436
|
+
#endif
|
|
1437
|
+
},
|
|
1438
|
+
{
|
|
1439
|
+
TMS320C64x_STNW_d5_rm, TMS320C64X_INS_STNW,
|
|
1440
|
+
#ifndef CAPSTONE_DIET
|
|
1441
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1442
|
+
#endif
|
|
1443
|
+
},
|
|
1444
|
+
{
|
|
1445
|
+
TMS320C64x_STW_d5_rm, TMS320C64X_INS_STW,
|
|
1446
|
+
#ifndef CAPSTONE_DIET
|
|
1447
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1448
|
+
#endif
|
|
1449
|
+
},
|
|
1450
|
+
{
|
|
1451
|
+
TMS320C64x_STW_d6_rm, TMS320C64X_INS_STW,
|
|
1452
|
+
#ifndef CAPSTONE_DIET
|
|
1453
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1454
|
+
#endif
|
|
1455
|
+
},
|
|
1456
|
+
{
|
|
1457
|
+
TMS320C64x_SUB2_d2_rrr, TMS320C64X_INS_SUB2,
|
|
1458
|
+
#ifndef CAPSTONE_DIET
|
|
1459
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1460
|
+
#endif
|
|
1461
|
+
},
|
|
1462
|
+
{
|
|
1463
|
+
TMS320C64x_SUB2_l1_rrr_x2, TMS320C64X_INS_SUB2,
|
|
1464
|
+
#ifndef CAPSTONE_DIET
|
|
1465
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1466
|
+
#endif
|
|
1467
|
+
},
|
|
1468
|
+
{
|
|
1469
|
+
TMS320C64x_SUB2_s1_rrr, TMS320C64X_INS_SUB2,
|
|
1470
|
+
#ifndef CAPSTONE_DIET
|
|
1471
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1472
|
+
#endif
|
|
1473
|
+
},
|
|
1474
|
+
{
|
|
1475
|
+
TMS320C64x_SUB4_l1_rrr_x2, TMS320C64X_INS_SUB4,
|
|
1476
|
+
#ifndef CAPSTONE_DIET
|
|
1477
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1478
|
+
#endif
|
|
1479
|
+
},
|
|
1480
|
+
{
|
|
1481
|
+
TMS320C64x_SUBABS4_l1_rrr_x2, TMS320C64X_INS_SUBABS4,
|
|
1482
|
+
#ifndef CAPSTONE_DIET
|
|
1483
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1484
|
+
#endif
|
|
1485
|
+
},
|
|
1486
|
+
{
|
|
1487
|
+
TMS320C64x_SUBAB_d1_rir, TMS320C64X_INS_SUBAB,
|
|
1488
|
+
#ifndef CAPSTONE_DIET
|
|
1489
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1490
|
+
#endif
|
|
1491
|
+
},
|
|
1492
|
+
{
|
|
1493
|
+
TMS320C64x_SUBAB_d1_rrr, TMS320C64X_INS_SUBAB,
|
|
1494
|
+
#ifndef CAPSTONE_DIET
|
|
1495
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1496
|
+
#endif
|
|
1497
|
+
},
|
|
1498
|
+
{
|
|
1499
|
+
TMS320C64x_SUBAH_d1_rir, TMS320C64X_INS_SUBAH,
|
|
1500
|
+
#ifndef CAPSTONE_DIET
|
|
1501
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1502
|
+
#endif
|
|
1503
|
+
},
|
|
1504
|
+
{
|
|
1505
|
+
TMS320C64x_SUBAH_d1_rrr, TMS320C64X_INS_SUBAH,
|
|
1506
|
+
#ifndef CAPSTONE_DIET
|
|
1507
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1508
|
+
#endif
|
|
1509
|
+
},
|
|
1510
|
+
{
|
|
1511
|
+
TMS320C64x_SUBAW_d1_rir, TMS320C64X_INS_SUBAW,
|
|
1512
|
+
#ifndef CAPSTONE_DIET
|
|
1513
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1514
|
+
#endif
|
|
1515
|
+
},
|
|
1516
|
+
{
|
|
1517
|
+
TMS320C64x_SUBAW_d1_rrr, TMS320C64X_INS_SUBAW,
|
|
1518
|
+
#ifndef CAPSTONE_DIET
|
|
1519
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1520
|
+
#endif
|
|
1521
|
+
},
|
|
1522
|
+
{
|
|
1523
|
+
TMS320C64x_SUBC_l1_rrr_x2, TMS320C64X_INS_SUBC,
|
|
1524
|
+
#ifndef CAPSTONE_DIET
|
|
1525
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1526
|
+
#endif
|
|
1527
|
+
},
|
|
1528
|
+
{
|
|
1529
|
+
TMS320C64x_SUBU_l1_rrp_x1, TMS320C64X_INS_SUBU,
|
|
1530
|
+
#ifndef CAPSTONE_DIET
|
|
1531
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1532
|
+
#endif
|
|
1533
|
+
},
|
|
1534
|
+
{
|
|
1535
|
+
TMS320C64x_SUBU_l1_rrp_x2, TMS320C64X_INS_SUBU,
|
|
1536
|
+
#ifndef CAPSTONE_DIET
|
|
1537
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1538
|
+
#endif
|
|
1539
|
+
},
|
|
1540
|
+
{
|
|
1541
|
+
TMS320C64x_SUB_d1_rir, TMS320C64X_INS_SUB,
|
|
1542
|
+
#ifndef CAPSTONE_DIET
|
|
1543
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1544
|
+
#endif
|
|
1545
|
+
},
|
|
1546
|
+
{
|
|
1547
|
+
TMS320C64x_SUB_d1_rrr, TMS320C64X_INS_SUB,
|
|
1548
|
+
#ifndef CAPSTONE_DIET
|
|
1549
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1550
|
+
#endif
|
|
1551
|
+
},
|
|
1552
|
+
{
|
|
1553
|
+
TMS320C64x_SUB_d2_rrr, TMS320C64X_INS_SUB,
|
|
1554
|
+
#ifndef CAPSTONE_DIET
|
|
1555
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1556
|
+
#endif
|
|
1557
|
+
},
|
|
1558
|
+
{
|
|
1559
|
+
TMS320C64x_SUB_l1_ipp, TMS320C64X_INS_SUB,
|
|
1560
|
+
#ifndef CAPSTONE_DIET
|
|
1561
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1562
|
+
#endif
|
|
1563
|
+
},
|
|
1564
|
+
{
|
|
1565
|
+
TMS320C64x_SUB_l1_irr, TMS320C64X_INS_SUB,
|
|
1566
|
+
#ifndef CAPSTONE_DIET
|
|
1567
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1568
|
+
#endif
|
|
1569
|
+
},
|
|
1570
|
+
{
|
|
1571
|
+
TMS320C64x_SUB_l1_rrp_x1, TMS320C64X_INS_SUB,
|
|
1572
|
+
#ifndef CAPSTONE_DIET
|
|
1573
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1574
|
+
#endif
|
|
1575
|
+
},
|
|
1576
|
+
{
|
|
1577
|
+
TMS320C64x_SUB_l1_rrp_x2, TMS320C64X_INS_SUB,
|
|
1578
|
+
#ifndef CAPSTONE_DIET
|
|
1579
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1580
|
+
#endif
|
|
1581
|
+
},
|
|
1582
|
+
{
|
|
1583
|
+
TMS320C64x_SUB_l1_rrr_x1, TMS320C64X_INS_SUB,
|
|
1584
|
+
#ifndef CAPSTONE_DIET
|
|
1585
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1586
|
+
#endif
|
|
1587
|
+
},
|
|
1588
|
+
{
|
|
1589
|
+
TMS320C64x_SUB_l1_rrr_x2, TMS320C64X_INS_SUB,
|
|
1590
|
+
#ifndef CAPSTONE_DIET
|
|
1591
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1592
|
+
#endif
|
|
1593
|
+
},
|
|
1594
|
+
{
|
|
1595
|
+
TMS320C64x_SUB_s1_irr, TMS320C64X_INS_SUB,
|
|
1596
|
+
#ifndef CAPSTONE_DIET
|
|
1597
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1598
|
+
#endif
|
|
1599
|
+
},
|
|
1600
|
+
{
|
|
1601
|
+
TMS320C64x_SUB_s1_rrr, TMS320C64X_INS_SUB,
|
|
1602
|
+
#ifndef CAPSTONE_DIET
|
|
1603
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1604
|
+
#endif
|
|
1605
|
+
},
|
|
1606
|
+
{
|
|
1607
|
+
TMS320C64x_SUB_s4_rrr, TMS320C64X_INS_SUB,
|
|
1608
|
+
#ifndef CAPSTONE_DIET
|
|
1609
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1610
|
+
#endif
|
|
1611
|
+
},
|
|
1612
|
+
{
|
|
1613
|
+
TMS320C64x_SWAP4_l2_rr, TMS320C64X_INS_SWAP4,
|
|
1614
|
+
#ifndef CAPSTONE_DIET
|
|
1615
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1616
|
+
#endif
|
|
1617
|
+
},
|
|
1618
|
+
{
|
|
1619
|
+
TMS320C64x_UNPKHU4_l2_rr, TMS320C64X_INS_UNPKHU4,
|
|
1620
|
+
#ifndef CAPSTONE_DIET
|
|
1621
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1622
|
+
#endif
|
|
1623
|
+
},
|
|
1624
|
+
{
|
|
1625
|
+
TMS320C64x_UNPKHU4_s14_rr, TMS320C64X_INS_UNPKHU4,
|
|
1626
|
+
#ifndef CAPSTONE_DIET
|
|
1627
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1628
|
+
#endif
|
|
1629
|
+
},
|
|
1630
|
+
{
|
|
1631
|
+
TMS320C64x_UNPKLU4_l2_rr, TMS320C64X_INS_UNPKLU4,
|
|
1632
|
+
#ifndef CAPSTONE_DIET
|
|
1633
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1634
|
+
#endif
|
|
1635
|
+
},
|
|
1636
|
+
{
|
|
1637
|
+
TMS320C64x_UNPKLU4_s14_rr, TMS320C64X_INS_UNPKLU4,
|
|
1638
|
+
#ifndef CAPSTONE_DIET
|
|
1639
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1640
|
+
#endif
|
|
1641
|
+
},
|
|
1642
|
+
{
|
|
1643
|
+
TMS320C64x_XOR_d2_rir, TMS320C64X_INS_XOR,
|
|
1644
|
+
#ifndef CAPSTONE_DIET
|
|
1645
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1646
|
+
#endif
|
|
1647
|
+
},
|
|
1648
|
+
{
|
|
1649
|
+
TMS320C64x_XOR_d2_rrr, TMS320C64X_INS_XOR,
|
|
1650
|
+
#ifndef CAPSTONE_DIET
|
|
1651
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_D, 0 }, 0, 0
|
|
1652
|
+
#endif
|
|
1653
|
+
},
|
|
1654
|
+
{
|
|
1655
|
+
TMS320C64x_XOR_l1_irr, TMS320C64X_INS_XOR,
|
|
1656
|
+
#ifndef CAPSTONE_DIET
|
|
1657
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1658
|
+
#endif
|
|
1659
|
+
},
|
|
1660
|
+
{
|
|
1661
|
+
TMS320C64x_XOR_l1_rrr_x2, TMS320C64X_INS_XOR,
|
|
1662
|
+
#ifndef CAPSTONE_DIET
|
|
1663
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_L, 0 }, 0, 0
|
|
1664
|
+
#endif
|
|
1665
|
+
},
|
|
1666
|
+
{
|
|
1667
|
+
TMS320C64x_XOR_s1_irr, TMS320C64X_INS_XOR,
|
|
1668
|
+
#ifndef CAPSTONE_DIET
|
|
1669
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1670
|
+
#endif
|
|
1671
|
+
},
|
|
1672
|
+
{
|
|
1673
|
+
TMS320C64x_XOR_s1_rrr, TMS320C64X_INS_XOR,
|
|
1674
|
+
#ifndef CAPSTONE_DIET
|
|
1675
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_S, 0 }, 0, 0
|
|
1676
|
+
#endif
|
|
1677
|
+
},
|
|
1678
|
+
{
|
|
1679
|
+
TMS320C64x_XPND2_m2_rr, TMS320C64X_INS_XPND2,
|
|
1680
|
+
#ifndef CAPSTONE_DIET
|
|
1681
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1682
|
+
#endif
|
|
1683
|
+
},
|
|
1684
|
+
{
|
|
1685
|
+
TMS320C64x_XPND4_m2_rr, TMS320C64X_INS_XPND4,
|
|
1686
|
+
#ifndef CAPSTONE_DIET
|
|
1687
|
+
{ 0 }, { 0 }, { TMS320C64X_GRP_FUNIT_M, 0 }, 0, 0
|
|
1688
|
+
#endif
|
|
1689
|
+
},
|
|
1690
|
+
};
|
|
1691
|
+
|
|
1692
|
+
void TMS320C64x_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|
1693
|
+
{
|
|
1694
|
+
unsigned short i;
|
|
1695
|
+
|
|
1696
|
+
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
|
|
1697
|
+
if (i != 0) {
|
|
1698
|
+
insn->id = insns[i].mapid;
|
|
1699
|
+
|
|
1700
|
+
if (h->detail) {
|
|
1701
|
+
#ifndef CAPSTONE_DIET
|
|
1702
|
+
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
|
|
1703
|
+
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
|
|
1704
|
+
|
|
1705
|
+
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
|
|
1706
|
+
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
|
|
1707
|
+
|
|
1708
|
+
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
|
|
1709
|
+
insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
|
|
1710
|
+
|
|
1711
|
+
if (insns[i].branch || insns[i].indirect_branch) {
|
|
1712
|
+
insn->detail->groups[insn->detail->groups_count] = TMS320C64X_GRP_JUMP;
|
|
1713
|
+
insn->detail->groups_count++;
|
|
1714
|
+
}
|
|
1715
|
+
#endif
|
|
1716
|
+
}
|
|
1717
|
+
}
|
|
1718
|
+
}
|
|
1719
|
+
|
|
1720
|
+
#ifndef CAPSTONE_DIET
|
|
1721
|
+
//grep TMS320C64X_INS include/capstone/tms320c64x.h | awk '{print "{"$1 "\""tolower(substr($1, 16, length($1)-16))"\"""},"}'
|
|
1722
|
+
static const name_map insn_name_maps[] = {
|
|
1723
|
+
{TMS320C64X_INS_INVALID, NULL},
|
|
1724
|
+
{TMS320C64X_INS_ABS, "abs"},
|
|
1725
|
+
{TMS320C64X_INS_ABS2, "abs2"},
|
|
1726
|
+
{TMS320C64X_INS_ADD, "add"},
|
|
1727
|
+
{TMS320C64X_INS_ADD2, "add2"},
|
|
1728
|
+
{TMS320C64X_INS_ADD4, "add4"},
|
|
1729
|
+
{TMS320C64X_INS_ADDAB, "addab"},
|
|
1730
|
+
{TMS320C64X_INS_ADDAD, "addad"},
|
|
1731
|
+
{TMS320C64X_INS_ADDAH, "addah"},
|
|
1732
|
+
{TMS320C64X_INS_ADDAW, "addaw"},
|
|
1733
|
+
{TMS320C64X_INS_ADDK, "addk"},
|
|
1734
|
+
{TMS320C64X_INS_ADDKPC, "addkpc"},
|
|
1735
|
+
{TMS320C64X_INS_ADDU, "addu"},
|
|
1736
|
+
{TMS320C64X_INS_AND, "and"},
|
|
1737
|
+
{TMS320C64X_INS_ANDN, "andn"},
|
|
1738
|
+
{TMS320C64X_INS_AVG2, "avg2"},
|
|
1739
|
+
{TMS320C64X_INS_AVGU4, "avgu4"},
|
|
1740
|
+
{TMS320C64X_INS_B, "b"},
|
|
1741
|
+
{TMS320C64X_INS_BDEC, "bdec"},
|
|
1742
|
+
{TMS320C64X_INS_BITC4, "bitc4"},
|
|
1743
|
+
{TMS320C64X_INS_BNOP, "bnop"},
|
|
1744
|
+
{TMS320C64X_INS_BPOS, "bpos"},
|
|
1745
|
+
{TMS320C64X_INS_CLR, "clr"},
|
|
1746
|
+
{TMS320C64X_INS_CMPEQ, "cmpeq"},
|
|
1747
|
+
{TMS320C64X_INS_CMPEQ2, "cmpeq2"},
|
|
1748
|
+
{TMS320C64X_INS_CMPEQ4, "cmpeq4"},
|
|
1749
|
+
{TMS320C64X_INS_CMPGT, "cmpgt"},
|
|
1750
|
+
{TMS320C64X_INS_CMPGT2, "cmpgt2"},
|
|
1751
|
+
{TMS320C64X_INS_CMPGTU4, "cmpgtu4"},
|
|
1752
|
+
{TMS320C64X_INS_CMPLT, "cmplt"},
|
|
1753
|
+
{TMS320C64X_INS_CMPLTU, "cmpltu"},
|
|
1754
|
+
{TMS320C64X_INS_DEAL, "deal"},
|
|
1755
|
+
{TMS320C64X_INS_DOTP2, "dotp2"},
|
|
1756
|
+
{TMS320C64X_INS_DOTPN2, "dotpn2"},
|
|
1757
|
+
{TMS320C64X_INS_DOTPNRSU2, "dotpnrsu2"},
|
|
1758
|
+
{TMS320C64X_INS_DOTPRSU2, "dotprsu2"},
|
|
1759
|
+
{TMS320C64X_INS_DOTPSU4, "dotpsu4"},
|
|
1760
|
+
{TMS320C64X_INS_DOTPU4, "dotpu4"},
|
|
1761
|
+
{TMS320C64X_INS_EXT, "ext"},
|
|
1762
|
+
{TMS320C64X_INS_EXTU, "extu"},
|
|
1763
|
+
{TMS320C64X_INS_GMPGTU, "gmpgtu"},
|
|
1764
|
+
{TMS320C64X_INS_GMPY4, "gmpy4"},
|
|
1765
|
+
{TMS320C64X_INS_LDB, "ldb"},
|
|
1766
|
+
{TMS320C64X_INS_LDBU, "ldbu"},
|
|
1767
|
+
{TMS320C64X_INS_LDDW, "lddw"},
|
|
1768
|
+
{TMS320C64X_INS_LDH, "ldh"},
|
|
1769
|
+
{TMS320C64X_INS_LDHU, "ldhu"},
|
|
1770
|
+
{TMS320C64X_INS_LDNDW, "ldndw"},
|
|
1771
|
+
{TMS320C64X_INS_LDNW, "ldnw"},
|
|
1772
|
+
{TMS320C64X_INS_LDW, "ldw"},
|
|
1773
|
+
{TMS320C64X_INS_LMBD, "lmbd"},
|
|
1774
|
+
{TMS320C64X_INS_MAX2, "max2"},
|
|
1775
|
+
{TMS320C64X_INS_MAXU4, "maxu4"},
|
|
1776
|
+
{TMS320C64X_INS_MIN2, "min2"},
|
|
1777
|
+
{TMS320C64X_INS_MINU4, "minu4"},
|
|
1778
|
+
{TMS320C64X_INS_MPY, "mpy"},
|
|
1779
|
+
{TMS320C64X_INS_MPY2, "mpy2"},
|
|
1780
|
+
{TMS320C64X_INS_MPYH, "mpyh"},
|
|
1781
|
+
{TMS320C64X_INS_MPYHI, "mpyhi"},
|
|
1782
|
+
{TMS320C64X_INS_MPYHIR, "mpyhir"},
|
|
1783
|
+
{TMS320C64X_INS_MPYHL, "mpyhl"},
|
|
1784
|
+
{TMS320C64X_INS_MPYHLU, "mpyhlu"},
|
|
1785
|
+
{TMS320C64X_INS_MPYHSLU, "mpyhslu"},
|
|
1786
|
+
{TMS320C64X_INS_MPYHSU, "mpyhsu"},
|
|
1787
|
+
{TMS320C64X_INS_MPYHU, "mpyhu"},
|
|
1788
|
+
{TMS320C64X_INS_MPYHULS, "mpyhuls"},
|
|
1789
|
+
{TMS320C64X_INS_MPYHUS, "mpyhus"},
|
|
1790
|
+
{TMS320C64X_INS_MPYLH, "mpylh"},
|
|
1791
|
+
{TMS320C64X_INS_MPYLHU, "mpylhu"},
|
|
1792
|
+
{TMS320C64X_INS_MPYLI, "mpyli"},
|
|
1793
|
+
{TMS320C64X_INS_MPYLIR, "mpylir"},
|
|
1794
|
+
{TMS320C64X_INS_MPYLSHU, "mpylshu"},
|
|
1795
|
+
{TMS320C64X_INS_MPYLUHS, "mpyluhs"},
|
|
1796
|
+
{TMS320C64X_INS_MPYSU, "mpysu"},
|
|
1797
|
+
{TMS320C64X_INS_MPYSU4, "mpysu4"},
|
|
1798
|
+
{TMS320C64X_INS_MPYU, "mpyu"},
|
|
1799
|
+
{TMS320C64X_INS_MPYU4, "mpyu4"},
|
|
1800
|
+
{TMS320C64X_INS_MPYUS, "mpyus"},
|
|
1801
|
+
{TMS320C64X_INS_MVC, "mvc"},
|
|
1802
|
+
{TMS320C64X_INS_MVD, "mvd"},
|
|
1803
|
+
{TMS320C64X_INS_MVK, "mvk"},
|
|
1804
|
+
{TMS320C64X_INS_MVKL, "mvkl"},
|
|
1805
|
+
{TMS320C64X_INS_MVKLH, "mvklh"},
|
|
1806
|
+
{TMS320C64X_INS_NOP, "nop"},
|
|
1807
|
+
{TMS320C64X_INS_NORM, "norm"},
|
|
1808
|
+
{TMS320C64X_INS_OR, "or"},
|
|
1809
|
+
{TMS320C64X_INS_PACK2, "pack2"},
|
|
1810
|
+
{TMS320C64X_INS_PACKH2, "packh2"},
|
|
1811
|
+
{TMS320C64X_INS_PACKH4, "packh4"},
|
|
1812
|
+
{TMS320C64X_INS_PACKHL2, "packhl2"},
|
|
1813
|
+
{TMS320C64X_INS_PACKL4, "packl4"},
|
|
1814
|
+
{TMS320C64X_INS_PACKLH2, "packlh2"},
|
|
1815
|
+
{TMS320C64X_INS_ROTL, "rotl"},
|
|
1816
|
+
{TMS320C64X_INS_SADD, "sadd"},
|
|
1817
|
+
{TMS320C64X_INS_SADD2, "sadd2"},
|
|
1818
|
+
{TMS320C64X_INS_SADDU4, "saddu4"},
|
|
1819
|
+
{TMS320C64X_INS_SADDUS2, "saddus2"},
|
|
1820
|
+
{TMS320C64X_INS_SAT, "sat"},
|
|
1821
|
+
{TMS320C64X_INS_SET, "set"},
|
|
1822
|
+
{TMS320C64X_INS_SHFL, "shfl"},
|
|
1823
|
+
{TMS320C64X_INS_SHL, "shl"},
|
|
1824
|
+
{TMS320C64X_INS_SHLMB, "shlmb"},
|
|
1825
|
+
{TMS320C64X_INS_SHR, "shr"},
|
|
1826
|
+
{TMS320C64X_INS_SHR2, "shr2"},
|
|
1827
|
+
{TMS320C64X_INS_SHRMB, "shrmb"},
|
|
1828
|
+
{TMS320C64X_INS_SHRU, "shru"},
|
|
1829
|
+
{TMS320C64X_INS_SHRU2, "shru2"},
|
|
1830
|
+
{TMS320C64X_INS_SMPY, "smpy"},
|
|
1831
|
+
{TMS320C64X_INS_SMPY2, "smpy2"},
|
|
1832
|
+
{TMS320C64X_INS_SMPYH, "smpyh"},
|
|
1833
|
+
{TMS320C64X_INS_SMPYHL, "smpyhl"},
|
|
1834
|
+
{TMS320C64X_INS_SMPYLH, "smpylh"},
|
|
1835
|
+
{TMS320C64X_INS_SPACK2, "spack2"},
|
|
1836
|
+
{TMS320C64X_INS_SPACKU4, "spacku4"},
|
|
1837
|
+
{TMS320C64X_INS_SSHL, "sshl"},
|
|
1838
|
+
{TMS320C64X_INS_SSHVL, "sshvl"},
|
|
1839
|
+
{TMS320C64X_INS_SSHVR, "sshvr"},
|
|
1840
|
+
{TMS320C64X_INS_SSUB, "ssub"},
|
|
1841
|
+
{TMS320C64X_INS_STB, "stb"},
|
|
1842
|
+
{TMS320C64X_INS_STDW, "stdw"},
|
|
1843
|
+
{TMS320C64X_INS_STH, "sth"},
|
|
1844
|
+
{TMS320C64X_INS_STNDW, "stndw"},
|
|
1845
|
+
{TMS320C64X_INS_STNW, "stnw"},
|
|
1846
|
+
{TMS320C64X_INS_STW, "stw"},
|
|
1847
|
+
{TMS320C64X_INS_SUB, "sub"},
|
|
1848
|
+
{TMS320C64X_INS_SUB2, "sub2"},
|
|
1849
|
+
{TMS320C64X_INS_SUB4, "sub4"},
|
|
1850
|
+
{TMS320C64X_INS_SUBAB, "subab"},
|
|
1851
|
+
{TMS320C64X_INS_SUBABS4, "subabs4"},
|
|
1852
|
+
{TMS320C64X_INS_SUBAH, "subah"},
|
|
1853
|
+
{TMS320C64X_INS_SUBAW, "subaw"},
|
|
1854
|
+
{TMS320C64X_INS_SUBC, "subc"},
|
|
1855
|
+
{TMS320C64X_INS_SUBU, "subu"},
|
|
1856
|
+
{TMS320C64X_INS_SWAP4, "swap4"},
|
|
1857
|
+
{TMS320C64X_INS_UNPKHU4, "unpkhu4"},
|
|
1858
|
+
{TMS320C64X_INS_UNPKLU4, "unpklu4"},
|
|
1859
|
+
{TMS320C64X_INS_XOR, "xor"},
|
|
1860
|
+
{TMS320C64X_INS_XPND2, "xpnd2"},
|
|
1861
|
+
{TMS320C64X_INS_XPND4, "xpnd4"},
|
|
1862
|
+
{TMS320C64X_INS_IDLE, "idle"},
|
|
1863
|
+
{TMS320C64X_INS_MV, "mv"},
|
|
1864
|
+
{TMS320C64X_INS_NEG, "neg"},
|
|
1865
|
+
{TMS320C64X_INS_NOT, "not"},
|
|
1866
|
+
{TMS320C64X_INS_SWAP2, "swap2"},
|
|
1867
|
+
{TMS320C64X_INS_ZERO, "zero"},
|
|
1868
|
+
};
|
|
1869
|
+
|
|
1870
|
+
#endif
|
|
1871
|
+
|
|
1872
|
+
const char *TMS320C64x_insn_name(csh handle, unsigned int id)
|
|
1873
|
+
{
|
|
1874
|
+
#ifndef CAPSTONE_DIET
|
|
1875
|
+
if (id >= TMS320C64X_INS_ENDING)
|
|
1876
|
+
return NULL;
|
|
1877
|
+
|
|
1878
|
+
return insn_name_maps[id].name;
|
|
1879
|
+
#else
|
|
1880
|
+
return NULL;
|
|
1881
|
+
#endif
|
|
1882
|
+
}
|
|
1883
|
+
|
|
1884
|
+
#ifndef CAPSTONE_DIET
|
|
1885
|
+
static const name_map group_name_maps[] = {
|
|
1886
|
+
{ TMS320C64X_GRP_INVALID, NULL },
|
|
1887
|
+
{ TMS320C64X_GRP_FUNIT_D, "funit_d" },
|
|
1888
|
+
{ TMS320C64X_GRP_FUNIT_L, "funit_l" },
|
|
1889
|
+
{ TMS320C64X_GRP_FUNIT_M, "funit_m" },
|
|
1890
|
+
{ TMS320C64X_GRP_FUNIT_S, "funit_s" },
|
|
1891
|
+
{ TMS320C64X_GRP_FUNIT_NO, "funit_no" },
|
|
1892
|
+
{ TMS320C64X_GRP_JUMP, "jump" },
|
|
1893
|
+
};
|
|
1894
|
+
#endif
|
|
1895
|
+
|
|
1896
|
+
const char *TMS320C64x_group_name(csh handle, unsigned int id)
|
|
1897
|
+
{
|
|
1898
|
+
#ifndef CAPSTONE_DIET
|
|
1899
|
+
unsigned int i;
|
|
1900
|
+
|
|
1901
|
+
if (id >= ARR_SIZE(group_name_maps))
|
|
1902
|
+
return NULL;
|
|
1903
|
+
|
|
1904
|
+
for (i = 0; i < ARR_SIZE(group_name_maps); i++) {
|
|
1905
|
+
if (group_name_maps[i].id == id)
|
|
1906
|
+
return group_name_maps[i].name;
|
|
1907
|
+
}
|
|
1908
|
+
|
|
1909
|
+
return group_name_maps[id].name;
|
|
1910
|
+
#else
|
|
1911
|
+
return NULL;
|
|
1912
|
+
#endif
|
|
1913
|
+
}
|
|
1914
|
+
|
|
1915
|
+
tms320c64x_reg TMS320C64x_map_register(unsigned int r)
|
|
1916
|
+
{
|
|
1917
|
+
static unsigned int map[] = { 0,
|
|
1918
|
+
};
|
|
1919
|
+
|
|
1920
|
+
if (r < ARR_SIZE(map))
|
|
1921
|
+
return map[r];
|
|
1922
|
+
|
|
1923
|
+
return 0;
|
|
1924
|
+
}
|
|
1925
|
+
|
|
1926
|
+
#endif
|