hexcore-capstone 1.2.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (332) hide show
  1. package/LICENSE +26 -0
  2. package/README.md +191 -0
  3. package/binding.gyp +168 -0
  4. package/deps/capstone/LEB128.h +38 -0
  5. package/deps/capstone/MCDisassembler.h +14 -0
  6. package/deps/capstone/MCFixedLenDisassembler.h +32 -0
  7. package/deps/capstone/MCInst.c +270 -0
  8. package/deps/capstone/MCInst.h +165 -0
  9. package/deps/capstone/MCInstrDesc.c +41 -0
  10. package/deps/capstone/MCInstrDesc.h +167 -0
  11. package/deps/capstone/MCRegisterInfo.c +151 -0
  12. package/deps/capstone/MCRegisterInfo.h +116 -0
  13. package/deps/capstone/Mapping.c +254 -0
  14. package/deps/capstone/Mapping.h +174 -0
  15. package/deps/capstone/MathExtras.h +442 -0
  16. package/deps/capstone/SStream.c +181 -0
  17. package/deps/capstone/SStream.h +40 -0
  18. package/deps/capstone/arch/AArch64/AArch64AddressingModes.h +945 -0
  19. package/deps/capstone/arch/AArch64/AArch64BaseInfo.c +77 -0
  20. package/deps/capstone/arch/AArch64/AArch64BaseInfo.h +585 -0
  21. package/deps/capstone/arch/AArch64/AArch64Disassembler.c +2280 -0
  22. package/deps/capstone/arch/AArch64/AArch64Disassembler.h +18 -0
  23. package/deps/capstone/arch/AArch64/AArch64GenAsmWriter.inc +26589 -0
  24. package/deps/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc +27322 -0
  25. package/deps/capstone/arch/AArch64/AArch64GenInstrInfo.inc +13194 -0
  26. package/deps/capstone/arch/AArch64/AArch64GenRegisterInfo.inc +3814 -0
  27. package/deps/capstone/arch/AArch64/AArch64GenRegisterName.inc +714 -0
  28. package/deps/capstone/arch/AArch64/AArch64GenRegisterV.inc +673 -0
  29. package/deps/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc +229 -0
  30. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands.inc +2863 -0
  31. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands_enum.inc +21 -0
  32. package/deps/capstone/arch/AArch64/AArch64InstPrinter.c +3029 -0
  33. package/deps/capstone/arch/AArch64/AArch64InstPrinter.h +28 -0
  34. package/deps/capstone/arch/AArch64/AArch64Mapping.c +883 -0
  35. package/deps/capstone/arch/AArch64/AArch64Mapping.h +43 -0
  36. package/deps/capstone/arch/AArch64/AArch64MappingInsn.inc +37790 -0
  37. package/deps/capstone/arch/AArch64/AArch64MappingInsnName.inc +1282 -0
  38. package/deps/capstone/arch/AArch64/AArch64MappingInsnOp.inc +26994 -0
  39. package/deps/capstone/arch/AArch64/AArch64Module.c +44 -0
  40. package/deps/capstone/arch/AArch64/AArch64Module.h +12 -0
  41. package/deps/capstone/arch/ARM/ARMAddressingModes.h +698 -0
  42. package/deps/capstone/arch/ARM/ARMBaseInfo.h +486 -0
  43. package/deps/capstone/arch/ARM/ARMDisassembler.c +5763 -0
  44. package/deps/capstone/arch/ARM/ARMDisassembler.h +18 -0
  45. package/deps/capstone/arch/ARM/ARMGenAsmWriter.inc +9545 -0
  46. package/deps/capstone/arch/ARM/ARMGenDisassemblerTables.inc +15185 -0
  47. package/deps/capstone/arch/ARM/ARMGenInstrInfo.inc +6632 -0
  48. package/deps/capstone/arch/ARM/ARMGenRegisterInfo.inc +2102 -0
  49. package/deps/capstone/arch/ARM/ARMGenRegisterName.inc +231 -0
  50. package/deps/capstone/arch/ARM/ARMGenRegisterName_digit.inc +231 -0
  51. package/deps/capstone/arch/ARM/ARMGenSubtargetInfo.inc +162 -0
  52. package/deps/capstone/arch/ARM/ARMGenSystemRegister.inc +270 -0
  53. package/deps/capstone/arch/ARM/ARMInstPrinter.c +3364 -0
  54. package/deps/capstone/arch/ARM/ARMInstPrinter.h +43 -0
  55. package/deps/capstone/arch/ARM/ARMMapping.c +551 -0
  56. package/deps/capstone/arch/ARM/ARMMapping.h +40 -0
  57. package/deps/capstone/arch/ARM/ARMMappingInsn.inc +18772 -0
  58. package/deps/capstone/arch/ARM/ARMMappingInsnName.inc +475 -0
  59. package/deps/capstone/arch/ARM/ARMMappingInsnOp.inc +10729 -0
  60. package/deps/capstone/arch/ARM/ARMModule.c +63 -0
  61. package/deps/capstone/arch/ARM/ARMModule.h +12 -0
  62. package/deps/capstone/arch/BPF/BPFConstants.h +88 -0
  63. package/deps/capstone/arch/BPF/BPFDisassembler.c +464 -0
  64. package/deps/capstone/arch/BPF/BPFDisassembler.h +27 -0
  65. package/deps/capstone/arch/BPF/BPFInstPrinter.c +285 -0
  66. package/deps/capstone/arch/BPF/BPFInstPrinter.h +16 -0
  67. package/deps/capstone/arch/BPF/BPFMapping.c +513 -0
  68. package/deps/capstone/arch/BPF/BPFMapping.h +21 -0
  69. package/deps/capstone/arch/BPF/BPFModule.c +34 -0
  70. package/deps/capstone/arch/BPF/BPFModule.h +12 -0
  71. package/deps/capstone/arch/EVM/EVMDisassembler.c +379 -0
  72. package/deps/capstone/arch/EVM/EVMDisassembler.h +12 -0
  73. package/deps/capstone/arch/EVM/EVMInstPrinter.c +20 -0
  74. package/deps/capstone/arch/EVM/EVMInstPrinter.h +17 -0
  75. package/deps/capstone/arch/EVM/EVMMapping.c +344 -0
  76. package/deps/capstone/arch/EVM/EVMMapping.h +8 -0
  77. package/deps/capstone/arch/EVM/EVMMappingInsn.inc +259 -0
  78. package/deps/capstone/arch/EVM/EVMModule.c +33 -0
  79. package/deps/capstone/arch/EVM/EVMModule.h +12 -0
  80. package/deps/capstone/arch/M680X/M680XDisassembler.c +2307 -0
  81. package/deps/capstone/arch/M680X/M680XDisassembler.h +17 -0
  82. package/deps/capstone/arch/M680X/M680XDisassemblerInternals.h +57 -0
  83. package/deps/capstone/arch/M680X/M680XInstPrinter.c +360 -0
  84. package/deps/capstone/arch/M680X/M680XInstPrinter.h +25 -0
  85. package/deps/capstone/arch/M680X/M680XModule.c +77 -0
  86. package/deps/capstone/arch/M680X/M680XModule.h +12 -0
  87. package/deps/capstone/arch/M680X/cpu12.inc +335 -0
  88. package/deps/capstone/arch/M680X/hcs08.inc +60 -0
  89. package/deps/capstone/arch/M680X/hd6301.inc +15 -0
  90. package/deps/capstone/arch/M680X/hd6309.inc +259 -0
  91. package/deps/capstone/arch/M680X/insn_props.inc +367 -0
  92. package/deps/capstone/arch/M680X/m6800.inc +277 -0
  93. package/deps/capstone/arch/M680X/m6801.inc +39 -0
  94. package/deps/capstone/arch/M680X/m6805.inc +277 -0
  95. package/deps/capstone/arch/M680X/m6808.inc +91 -0
  96. package/deps/capstone/arch/M680X/m6809.inc +352 -0
  97. package/deps/capstone/arch/M680X/m6811.inc +105 -0
  98. package/deps/capstone/arch/M68K/M68KDisassembler.c +3668 -0
  99. package/deps/capstone/arch/M68K/M68KDisassembler.h +30 -0
  100. package/deps/capstone/arch/M68K/M68KInstPrinter.c +387 -0
  101. package/deps/capstone/arch/M68K/M68KInstPrinter.h +21 -0
  102. package/deps/capstone/arch/M68K/M68KInstructionTable.inc +65540 -0
  103. package/deps/capstone/arch/M68K/M68KModule.c +42 -0
  104. package/deps/capstone/arch/M68K/M68KModule.h +12 -0
  105. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.c +544 -0
  106. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.h +22 -0
  107. package/deps/capstone/arch/MOS65XX/MOS65XXDisassemblerInternals.h +23 -0
  108. package/deps/capstone/arch/MOS65XX/MOS65XXModule.c +79 -0
  109. package/deps/capstone/arch/MOS65XX/MOS65XXModule.h +12 -0
  110. package/deps/capstone/arch/MOS65XX/instruction_info.inc +106 -0
  111. package/deps/capstone/arch/MOS65XX/m6502.inc +256 -0
  112. package/deps/capstone/arch/MOS65XX/m65816.inc +256 -0
  113. package/deps/capstone/arch/MOS65XX/m65c02.inc +256 -0
  114. package/deps/capstone/arch/MOS65XX/mw65c02.inc +256 -0
  115. package/deps/capstone/arch/Mips/MipsDisassembler.c +1794 -0
  116. package/deps/capstone/arch/Mips/MipsDisassembler.h +16 -0
  117. package/deps/capstone/arch/Mips/MipsGenAsmWriter.inc +5725 -0
  118. package/deps/capstone/arch/Mips/MipsGenDisassemblerTables.inc +6942 -0
  119. package/deps/capstone/arch/Mips/MipsGenInstrInfo.inc +1805 -0
  120. package/deps/capstone/arch/Mips/MipsGenRegisterInfo.inc +1679 -0
  121. package/deps/capstone/arch/Mips/MipsGenSubtargetInfo.inc +52 -0
  122. package/deps/capstone/arch/Mips/MipsInstPrinter.c +424 -0
  123. package/deps/capstone/arch/Mips/MipsInstPrinter.h +25 -0
  124. package/deps/capstone/arch/Mips/MipsMapping.c +1070 -0
  125. package/deps/capstone/arch/Mips/MipsMapping.h +25 -0
  126. package/deps/capstone/arch/Mips/MipsMappingInsn.inc +9315 -0
  127. package/deps/capstone/arch/Mips/MipsModule.c +52 -0
  128. package/deps/capstone/arch/Mips/MipsModule.h +12 -0
  129. package/deps/capstone/arch/PowerPC/PPCDisassembler.c +627 -0
  130. package/deps/capstone/arch/PowerPC/PPCDisassembler.h +17 -0
  131. package/deps/capstone/arch/PowerPC/PPCGenAsmWriter.inc +11451 -0
  132. package/deps/capstone/arch/PowerPC/PPCGenDisassemblerTables.inc +6886 -0
  133. package/deps/capstone/arch/PowerPC/PPCGenInstrInfo.inc +4772 -0
  134. package/deps/capstone/arch/PowerPC/PPCGenRegisterInfo.inc +1122 -0
  135. package/deps/capstone/arch/PowerPC/PPCGenRegisterName.inc +278 -0
  136. package/deps/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc +90 -0
  137. package/deps/capstone/arch/PowerPC/PPCInstPrinter.c +1238 -0
  138. package/deps/capstone/arch/PowerPC/PPCInstPrinter.h +15 -0
  139. package/deps/capstone/arch/PowerPC/PPCMapping.c +570 -0
  140. package/deps/capstone/arch/PowerPC/PPCMapping.h +40 -0
  141. package/deps/capstone/arch/PowerPC/PPCMappingInsn.inc +13220 -0
  142. package/deps/capstone/arch/PowerPC/PPCMappingInsnName.inc +1731 -0
  143. package/deps/capstone/arch/PowerPC/PPCModule.c +45 -0
  144. package/deps/capstone/arch/PowerPC/PPCModule.h +12 -0
  145. package/deps/capstone/arch/PowerPC/PPCPredicates.h +62 -0
  146. package/deps/capstone/arch/RISCV/RISCVBaseInfo.h +106 -0
  147. package/deps/capstone/arch/RISCV/RISCVDisassembler.c +433 -0
  148. package/deps/capstone/arch/RISCV/RISCVDisassembler.h +18 -0
  149. package/deps/capstone/arch/RISCV/RISCVGenAsmWriter.inc +2651 -0
  150. package/deps/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc +1776 -0
  151. package/deps/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc +275 -0
  152. package/deps/capstone/arch/RISCV/RISCVGenInstrInfo.inc +470 -0
  153. package/deps/capstone/arch/RISCV/RISCVGenRegisterInfo.inc +426 -0
  154. package/deps/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc +33 -0
  155. package/deps/capstone/arch/RISCV/RISCVInstPrinter.c +447 -0
  156. package/deps/capstone/arch/RISCV/RISCVInstPrinter.h +24 -0
  157. package/deps/capstone/arch/RISCV/RISCVMapping.c +366 -0
  158. package/deps/capstone/arch/RISCV/RISCVMapping.h +22 -0
  159. package/deps/capstone/arch/RISCV/RISCVMappingInsn.inc +1635 -0
  160. package/deps/capstone/arch/RISCV/RISCVModule.c +42 -0
  161. package/deps/capstone/arch/RISCV/RISCVModule.h +12 -0
  162. package/deps/capstone/arch/SH/SHDisassembler.c +2221 -0
  163. package/deps/capstone/arch/SH/SHDisassembler.h +19 -0
  164. package/deps/capstone/arch/SH/SHInsnTable.inc +66 -0
  165. package/deps/capstone/arch/SH/SHInstPrinter.c +438 -0
  166. package/deps/capstone/arch/SH/SHInstPrinter.h +23 -0
  167. package/deps/capstone/arch/SH/SHModule.c +39 -0
  168. package/deps/capstone/arch/SH/SHModule.h +12 -0
  169. package/deps/capstone/arch/SH/mktable.rb +390 -0
  170. package/deps/capstone/arch/Sparc/Sparc.h +63 -0
  171. package/deps/capstone/arch/Sparc/SparcDisassembler.c +500 -0
  172. package/deps/capstone/arch/Sparc/SparcDisassembler.h +17 -0
  173. package/deps/capstone/arch/Sparc/SparcGenAsmWriter.inc +5709 -0
  174. package/deps/capstone/arch/Sparc/SparcGenDisassemblerTables.inc +2028 -0
  175. package/deps/capstone/arch/Sparc/SparcGenInstrInfo.inc +514 -0
  176. package/deps/capstone/arch/Sparc/SparcGenRegisterInfo.inc +451 -0
  177. package/deps/capstone/arch/Sparc/SparcGenSubtargetInfo.inc +27 -0
  178. package/deps/capstone/arch/Sparc/SparcInstPrinter.c +446 -0
  179. package/deps/capstone/arch/Sparc/SparcInstPrinter.h +17 -0
  180. package/deps/capstone/arch/Sparc/SparcMapping.c +665 -0
  181. package/deps/capstone/arch/Sparc/SparcMapping.h +34 -0
  182. package/deps/capstone/arch/Sparc/SparcMappingInsn.inc +2643 -0
  183. package/deps/capstone/arch/Sparc/SparcModule.c +45 -0
  184. package/deps/capstone/arch/Sparc/SparcModule.h +12 -0
  185. package/deps/capstone/arch/SystemZ/SystemZDisassembler.c +484 -0
  186. package/deps/capstone/arch/SystemZ/SystemZDisassembler.h +17 -0
  187. package/deps/capstone/arch/SystemZ/SystemZGenAsmWriter.inc +11575 -0
  188. package/deps/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc +10262 -0
  189. package/deps/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc +2348 -0
  190. package/deps/capstone/arch/SystemZ/SystemZGenInstrInfo.inc +2820 -0
  191. package/deps/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc +741 -0
  192. package/deps/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc +49 -0
  193. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.c +433 -0
  194. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.h +15 -0
  195. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.c +195 -0
  196. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.h +51 -0
  197. package/deps/capstone/arch/SystemZ/SystemZMapping.c +479 -0
  198. package/deps/capstone/arch/SystemZ/SystemZMapping.h +23 -0
  199. package/deps/capstone/arch/SystemZ/SystemZMappingInsn.inc +14175 -0
  200. package/deps/capstone/arch/SystemZ/SystemZModule.c +44 -0
  201. package/deps/capstone/arch/SystemZ/SystemZModule.h +12 -0
  202. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c +628 -0
  203. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h +19 -0
  204. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +684 -0
  205. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc +1352 -0
  206. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc +298 -0
  207. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc +277 -0
  208. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c +572 -0
  209. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h +15 -0
  210. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.c +1926 -0
  211. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.h +26 -0
  212. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.c +39 -0
  213. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.h +12 -0
  214. package/deps/capstone/arch/TriCore/TriCore.td +134 -0
  215. package/deps/capstone/arch/TriCore/TriCoreCallingConv.td +61 -0
  216. package/deps/capstone/arch/TriCore/TriCoreDisassembler.c +1655 -0
  217. package/deps/capstone/arch/TriCore/TriCoreDisassembler.h +18 -0
  218. package/deps/capstone/arch/TriCore/TriCoreGenAsmWriter.inc +3691 -0
  219. package/deps/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc +22 -0
  220. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc +8938 -0
  221. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc +404 -0
  222. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc +7994 -0
  223. package/deps/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc +32 -0
  224. package/deps/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc +4044 -0
  225. package/deps/capstone/arch/TriCore/TriCoreGenInstrInfo.inc +2693 -0
  226. package/deps/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc +295 -0
  227. package/deps/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc +40 -0
  228. package/deps/capstone/arch/TriCore/TriCoreInstPrinter.c +488 -0
  229. package/deps/capstone/arch/TriCore/TriCoreInstrFormats.td +773 -0
  230. package/deps/capstone/arch/TriCore/TriCoreInstrInfo.td +1873 -0
  231. package/deps/capstone/arch/TriCore/TriCoreLinkage.h +21 -0
  232. package/deps/capstone/arch/TriCore/TriCoreMapping.c +241 -0
  233. package/deps/capstone/arch/TriCore/TriCoreMapping.h +32 -0
  234. package/deps/capstone/arch/TriCore/TriCoreModule.c +44 -0
  235. package/deps/capstone/arch/TriCore/TriCoreModule.h +11 -0
  236. package/deps/capstone/arch/TriCore/TriCoreRegisterInfo.td +153 -0
  237. package/deps/capstone/arch/WASM/WASMDisassembler.c +1009 -0
  238. package/deps/capstone/arch/WASM/WASMDisassembler.h +12 -0
  239. package/deps/capstone/arch/WASM/WASMInstPrinter.c +47 -0
  240. package/deps/capstone/arch/WASM/WASMInstPrinter.h +18 -0
  241. package/deps/capstone/arch/WASM/WASMMapping.c +333 -0
  242. package/deps/capstone/arch/WASM/WASMMapping.h +9 -0
  243. package/deps/capstone/arch/WASM/WASMModule.c +33 -0
  244. package/deps/capstone/arch/WASM/WASMModule.h +12 -0
  245. package/deps/capstone/arch/X86/X86ATTInstPrinter.c +997 -0
  246. package/deps/capstone/arch/X86/X86BaseInfo.h +50 -0
  247. package/deps/capstone/arch/X86/X86Disassembler.c +1033 -0
  248. package/deps/capstone/arch/X86/X86Disassembler.h +28 -0
  249. package/deps/capstone/arch/X86/X86DisassemblerDecoder.c +2358 -0
  250. package/deps/capstone/arch/X86/X86DisassemblerDecoder.h +725 -0
  251. package/deps/capstone/arch/X86/X86DisassemblerDecoderCommon.h +483 -0
  252. package/deps/capstone/arch/X86/X86GenAsmWriter.inc +49199 -0
  253. package/deps/capstone/arch/X86/X86GenAsmWriter1.inc +33196 -0
  254. package/deps/capstone/arch/X86/X86GenAsmWriter1_reduce.inc +2531 -0
  255. package/deps/capstone/arch/X86/X86GenAsmWriter_reduce.inc +2855 -0
  256. package/deps/capstone/arch/X86/X86GenDisassemblerTables.inc +112961 -0
  257. package/deps/capstone/arch/X86/X86GenDisassemblerTables2.inc +102151 -0
  258. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc +28047 -0
  259. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc +18827 -0
  260. package/deps/capstone/arch/X86/X86GenInstrInfo.inc +15158 -0
  261. package/deps/capstone/arch/X86/X86GenInstrInfo_reduce.inc +1564 -0
  262. package/deps/capstone/arch/X86/X86GenRegisterInfo.inc +1549 -0
  263. package/deps/capstone/arch/X86/X86GenRegisterName.inc +292 -0
  264. package/deps/capstone/arch/X86/X86GenRegisterName1.inc +291 -0
  265. package/deps/capstone/arch/X86/X86ImmSize.inc +335 -0
  266. package/deps/capstone/arch/X86/X86InstPrinter.h +26 -0
  267. package/deps/capstone/arch/X86/X86InstPrinterCommon.c +116 -0
  268. package/deps/capstone/arch/X86/X86InstPrinterCommon.h +16 -0
  269. package/deps/capstone/arch/X86/X86IntelInstPrinter.c +1061 -0
  270. package/deps/capstone/arch/X86/X86Lookup16.inc +16874 -0
  271. package/deps/capstone/arch/X86/X86Lookup16_reduce.inc +2308 -0
  272. package/deps/capstone/arch/X86/X86Mapping.c +2266 -0
  273. package/deps/capstone/arch/X86/X86Mapping.h +96 -0
  274. package/deps/capstone/arch/X86/X86MappingInsn.inc +105977 -0
  275. package/deps/capstone/arch/X86/X86MappingInsnName.inc +1527 -0
  276. package/deps/capstone/arch/X86/X86MappingInsnName_reduce.inc +348 -0
  277. package/deps/capstone/arch/X86/X86MappingInsnOp.inc +75700 -0
  278. package/deps/capstone/arch/X86/X86MappingInsnOp_reduce.inc +7729 -0
  279. package/deps/capstone/arch/X86/X86MappingInsn_reduce.inc +10819 -0
  280. package/deps/capstone/arch/X86/X86MappingReg.inc +280 -0
  281. package/deps/capstone/arch/X86/X86Module.c +94 -0
  282. package/deps/capstone/arch/X86/X86Module.h +12 -0
  283. package/deps/capstone/arch/XCore/XCoreDisassembler.c +794 -0
  284. package/deps/capstone/arch/XCore/XCoreDisassembler.h +17 -0
  285. package/deps/capstone/arch/XCore/XCoreGenAsmWriter.inc +772 -0
  286. package/deps/capstone/arch/XCore/XCoreGenDisassemblerTables.inc +853 -0
  287. package/deps/capstone/arch/XCore/XCoreGenInstrInfo.inc +267 -0
  288. package/deps/capstone/arch/XCore/XCoreGenRegisterInfo.inc +110 -0
  289. package/deps/capstone/arch/XCore/XCoreInstPrinter.c +250 -0
  290. package/deps/capstone/arch/XCore/XCoreInstPrinter.h +18 -0
  291. package/deps/capstone/arch/XCore/XCoreMapping.c +297 -0
  292. package/deps/capstone/arch/XCore/XCoreMapping.h +26 -0
  293. package/deps/capstone/arch/XCore/XCoreMappingInsn.inc +1287 -0
  294. package/deps/capstone/arch/XCore/XCoreModule.c +41 -0
  295. package/deps/capstone/arch/XCore/XCoreModule.h +12 -0
  296. package/deps/capstone/cs.c +1664 -0
  297. package/deps/capstone/cs_priv.h +101 -0
  298. package/deps/capstone/cs_simple_types.h +886 -0
  299. package/deps/capstone/include/capstone/arm.h +991 -0
  300. package/deps/capstone/include/capstone/arm64.h +3159 -0
  301. package/deps/capstone/include/capstone/bpf.h +209 -0
  302. package/deps/capstone/include/capstone/capstone.h +875 -0
  303. package/deps/capstone/include/capstone/evm.h +188 -0
  304. package/deps/capstone/include/capstone/m680x.h +537 -0
  305. package/deps/capstone/include/capstone/m68k.h +613 -0
  306. package/deps/capstone/include/capstone/mips.h +956 -0
  307. package/deps/capstone/include/capstone/mos65xx.h +204 -0
  308. package/deps/capstone/include/capstone/platform.h +122 -0
  309. package/deps/capstone/include/capstone/ppc.h +2108 -0
  310. package/deps/capstone/include/capstone/riscv.h +531 -0
  311. package/deps/capstone/include/capstone/sh.h +465 -0
  312. package/deps/capstone/include/capstone/sparc.h +520 -0
  313. package/deps/capstone/include/capstone/systemz.h +2601 -0
  314. package/deps/capstone/include/capstone/tms320c64x.h +359 -0
  315. package/deps/capstone/include/capstone/tricore.h +567 -0
  316. package/deps/capstone/include/capstone/wasm.h +250 -0
  317. package/deps/capstone/include/capstone/x86.h +1986 -0
  318. package/deps/capstone/include/capstone/xcore.h +235 -0
  319. package/deps/capstone/include/platform.h +110 -0
  320. package/deps/capstone/include/windowsce/intrin.h +12 -0
  321. package/deps/capstone/include/windowsce/stdint.h +133 -0
  322. package/deps/capstone/utils.c +140 -0
  323. package/deps/capstone/utils.h +54 -0
  324. package/index.d.ts +448 -0
  325. package/index.js +64 -0
  326. package/index.mjs +25 -0
  327. package/package.json +82 -0
  328. package/prebuilds/win32-x64/hexcore-capstone.node +0 -0
  329. package/src/capstone_wrapper.cpp +910 -0
  330. package/src/capstone_wrapper.h +147 -0
  331. package/src/disasm_async_worker.h +215 -0
  332. package/src/main.cpp +145 -0
@@ -0,0 +1,772 @@
1
+ /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
+ |* *|
3
+ |*Assembly Writer Source Fragment *|
4
+ |* *|
5
+ |* Automatically generated file, do not edit! *|
6
+ |* *|
7
+ \*===----------------------------------------------------------------------===*/
8
+
9
+ /* Capstone Disassembly Engine */
10
+ /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11
+
12
+ #include <stdio.h> // debug
13
+ #include <capstone/platform.h>
14
+
15
+
16
+ /// printInstruction - This method is automatically generated by tablegen
17
+ /// from the instruction set description.
18
+ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
19
+ {
20
+ static const uint32_t OpInfo[] = {
21
+ 0U, // PHI
22
+ 0U, // INLINEASM
23
+ 0U, // CFI_INSTRUCTION
24
+ 0U, // EH_LABEL
25
+ 0U, // GC_LABEL
26
+ 0U, // KILL
27
+ 0U, // EXTRACT_SUBREG
28
+ 0U, // INSERT_SUBREG
29
+ 0U, // IMPLICIT_DEF
30
+ 0U, // SUBREG_TO_REG
31
+ 0U, // COPY_TO_REGCLASS
32
+ 665U, // DBG_VALUE
33
+ 0U, // REG_SEQUENCE
34
+ 0U, // COPY
35
+ 658U, // BUNDLE
36
+ 687U, // LIFETIME_START
37
+ 645U, // LIFETIME_END
38
+ 0U, // STACKMAP
39
+ 0U, // PATCHPOINT
40
+ 0U, // LOAD_STACK_GUARD
41
+ 0U, // STATEPOINT
42
+ 0U, // FRAME_ALLOC
43
+ 2250U, // ADD_2rus
44
+ 2250U, // ADD_3r
45
+ 10363U, // ADJCALLSTACKDOWN
46
+ 10383U, // ADJCALLSTACKUP
47
+ 2361840U, // ANDNOT_2r
48
+ 2255U, // AND_3r
49
+ 2404U, // ASHR_l2rus
50
+ 2404U, // ASHR_l3r
51
+ 10769U, // BAU_1r
52
+ 2099777U, // BITREV_l2r
53
+ 19161U, // BLACP_lu10
54
+ 19161U, // BLACP_u10
55
+ 10672U, // BLAT_lu6
56
+ 10672U, // BLAT_u6
57
+ 10425U, // BLA_1r
58
+ 10510U, // BLRB_lu10
59
+ 10510U, // BLRB_u10
60
+ 10510U, // BLRF_lu10
61
+ 10510U, // BLRF_u10
62
+ 2099418U, // BRBF_lru6
63
+ 2099418U, // BRBF_ru6
64
+ 2099638U, // BRBT_lru6
65
+ 2099638U, // BRBT_ru6
66
+ 10774U, // BRBU_lu6
67
+ 10774U, // BRBU_u6
68
+ 2099418U, // BRFF_lru6
69
+ 2099418U, // BRFF_ru6
70
+ 2099638U, // BRFT_lru6
71
+ 2099638U, // BRFT_ru6
72
+ 10774U, // BRFU_lu6
73
+ 10774U, // BRFU_u6
74
+ 10791U, // BRU_1r
75
+ 553511U, // BR_JT
76
+ 815655U, // BR_JT32
77
+ 2099768U, // BYTEREV_l2r
78
+ 2132815U, // CHKCT_2r
79
+ 2132815U, // CHKCT_rus
80
+ 1163U, // CLRE_0R
81
+ 19301U, // CLRPT_1R
82
+ 10614U, // CLRSR_branch_lu6
83
+ 10614U, // CLRSR_branch_u6
84
+ 10614U, // CLRSR_lu6
85
+ 10614U, // CLRSR_u6
86
+ 2099807U, // CLZ_l2r
87
+ 5247047U, // CRC8_l4r
88
+ 17041459U, // CRC_l3r
89
+ 1168U, // DCALL_0R
90
+ 1200U, // DENTSP_0R
91
+ 10488U, // DGETREG_1r
92
+ 2474U, // DIVS_l3r
93
+ 2610U, // DIVU_l3r
94
+ 1207U, // DRESTSP_0R
95
+ 1242U, // DRET_0R
96
+ 10475U, // ECALLF_1r
97
+ 10723U, // ECALLT_1r
98
+ 19342U, // EDU_1r
99
+ 6334686U, // EEF_2r
100
+ 6334929U, // EET_2r
101
+ 19351U, // EEU_1r
102
+ 2099310U, // EH_RETURN
103
+ 6334765U, // ENDIN_2r
104
+ 10569U, // ENTSP_lu6
105
+ 10569U, // ENTSP_u6
106
+ 2400U, // EQ_2rus
107
+ 2400U, // EQ_3r
108
+ 10554U, // EXTDP_lu6
109
+ 10554U, // EXTDP_u6
110
+ 10585U, // EXTSP_lu6
111
+ 10585U, // EXTSP_u6
112
+ 10401U, // FRAME_TO_ARGS_OFFSET
113
+ 19256U, // FREER_1r
114
+ 1236U, // FREET_0R
115
+ 6334676U, // GETD_l2r
116
+ 1139U, // GETED_0R
117
+ 1224U, // GETET_0R
118
+ 1151U, // GETID_0R
119
+ 1174U, // GETKEP_0R
120
+ 1187U, // GETKSP_0R
121
+ 6334772U, // GETN_l2r
122
+ 51670U, // GETPS_l2r
123
+ 2099588U, // GETR_rus
124
+ 10252U, // GETSR_lu6
125
+ 10252U, // GETSR_u6
126
+ 6334968U, // GETST_2r
127
+ 6334883U, // GETTS_2r
128
+ 6334906U, // INCT_2r
129
+ 62438U, // INITCP_2r
130
+ 70630U, // INITDP_2r
131
+ 78822U, // INITLR_l2r
132
+ 87014U, // INITPC_2r
133
+ 95206U, // INITSP_2r
134
+ 8432212U, // INPW_l2rus
135
+ 6596970U, // INSHR_2r
136
+ 6334955U, // INT_2r
137
+ 6334768U, // IN_2r
138
+ 675U, // Int_MemBarrier
139
+ 10528U, // KCALL_1r
140
+ 10528U, // KCALL_lu6
141
+ 10528U, // KCALL_u6
142
+ 10568U, // KENTSP_lu6
143
+ 10568U, // KENTSP_u6
144
+ 10576U, // KRESTSP_lu6
145
+ 10576U, // KRESTSP_u6
146
+ 1247U, // KRET_0R
147
+ 45093065U, // LADD_l5r
148
+ 12585354U, // LD16S_3r
149
+ 12585483U, // LD8U_3r
150
+ 14682170U, // LDA16B_l3r
151
+ 12585018U, // LDA16F_l3r
152
+ 10241U, // LDAPB_lu10
153
+ 10241U, // LDAPB_u10
154
+ 10241U, // LDAPF_lu10
155
+ 10241U, // LDAPF_lu10_ba
156
+ 10241U, // LDAPF_u10
157
+ 14682697U, // LDAWB_l2rus
158
+ 14682697U, // LDAWB_l3r
159
+ 19134U, // LDAWCP_lu6
160
+ 19134U, // LDAWCP_u6
161
+ 100937U, // LDAWDP_lru6
162
+ 100937U, // LDAWDP_ru6
163
+ 2099282U, // LDAWFI
164
+ 12585545U, // LDAWF_l2rus
165
+ 12585545U, // LDAWF_l3r
166
+ 109129U, // LDAWSP_lru6
167
+ 109129U, // LDAWSP_ru6
168
+ 2099396U, // LDC_lru6
169
+ 2099396U, // LDC_ru6
170
+ 1105U, // LDET_0R
171
+ 184551985U, // LDIVU_l5r
172
+ 1075U, // LDSED_0R
173
+ 1015U, // LDSPC_0R
174
+ 1045U, // LDSSR_0R
175
+ 117327U, // LDWCP_lru6
176
+ 19148U, // LDWCP_lu10
177
+ 117327U, // LDWCP_ru6
178
+ 19148U, // LDWCP_u10
179
+ 100943U, // LDWDP_lru6
180
+ 100943U, // LDWDP_ru6
181
+ 2099292U, // LDWFI
182
+ 109135U, // LDWSP_lru6
183
+ 109135U, // LDWSP_ru6
184
+ 12585551U, // LDW_2rus
185
+ 12585551U, // LDW_3r
186
+ 268437799U, // LMUL_l6r
187
+ 2462U, // LSS_3r
188
+ 45093054U, // LSUB_l5r
189
+ 2604U, // LSU_3r
190
+ 452987281U, // MACCS_l4r
191
+ 452987418U, // MACCU_l4r
192
+ 19224U, // MJOIN_1r
193
+ 2099463U, // MKMSK_2r
194
+ 2099463U, // MKMSK_rus
195
+ 19169U, // MSYNC_1r
196
+ 2344U, // MUL_l3r
197
+ 2099443U, // NEG
198
+ 2099699U, // NOT
199
+ 2418U, // OR_3r
200
+ 2132826U, // OUTCT_2r
201
+ 2132826U, // OUTCT_rus
202
+ 78681013U, // OUTPW_l2rus
203
+ 2136899U, // OUTSHR_2r
204
+ 2132859U, // OUTT_2r
205
+ 2132869U, // OUT_2r
206
+ 6334721U, // PEEK_2r
207
+ 2456U, // REMS_l3r
208
+ 2593U, // REMU_l3r
209
+ 10561U, // RETSP_lu6
210
+ 10561U, // RETSP_u6
211
+ 612U, // SELECT_CC
212
+ 2132748U, // SETCLK_l2r
213
+ 10264U, // SETCP_1r
214
+ 2132728U, // SETC_l2r
215
+ 2132728U, // SETC_lru6
216
+ 2132728U, // SETC_ru6
217
+ 10273U, // SETDP_1r
218
+ 2132738U, // SETD_2r
219
+ 125856U, // SETEV_1r
220
+ 632U, // SETKEP_0R
221
+ 2132771U, // SETN_l2r
222
+ 2132716U, // SETPSC_2r
223
+ 2132951U, // SETPS_l2r
224
+ 2132848U, // SETPT_2r
225
+ 2132939U, // SETRDY_l2r
226
+ 10282U, // SETSP_1r
227
+ 10621U, // SETSR_branch_lu6
228
+ 10621U, // SETSR_branch_u6
229
+ 10621U, // SETSR_lu6
230
+ 10621U, // SETSR_u6
231
+ 2132928U, // SETTW_l2r
232
+ 125867U, // SETV_1r
233
+ 2361855U, // SEXT_2r
234
+ 2361855U, // SEXT_rus
235
+ 2331U, // SHL_2rus
236
+ 2331U, // SHL_3r
237
+ 2405U, // SHR_2rus
238
+ 2405U, // SHR_3r
239
+ 1133U, // SSYNC_0r
240
+ 12585025U, // ST16_l3r
241
+ 12585037U, // ST8_l3r
242
+ 1119U, // STET_0R
243
+ 1090U, // STSED_0R
244
+ 1030U, // STSPC_0R
245
+ 1060U, // STSSR_0R
246
+ 100954U, // STWDP_lru6
247
+ 100954U, // STWDP_ru6
248
+ 2099301U, // STWFI
249
+ 109146U, // STWSP_lru6
250
+ 109146U, // STWSP_ru6
251
+ 12585562U, // STW_2rus
252
+ 12585562U, // STW_l3r
253
+ 2239U, // SUB_2rus
254
+ 2239U, // SUB_3r
255
+ 19245U, // SYNCR_1r
256
+ 6334912U, // TESTCT_2r
257
+ 6334738U, // TESTLCL_l2r
258
+ 6334920U, // TESTWCT_2r
259
+ 2100415U, // TSETMR_2r
260
+ 138207U, // TSETR_3r
261
+ 19438U, // TSTART_1R
262
+ 10467U, // WAITEF_1R
263
+ 10715U, // WAITET_1R
264
+ 1252U, // WAITEU_0R
265
+ 2417U, // XOR_l3r
266
+ 2361861U, // ZEXT_2r
267
+ 2361861U, // ZEXT_rus
268
+ 0U
269
+ };
270
+
271
+ static const char AsmStrs[] = {
272
+ /* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0,
273
+ /* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0,
274
+ /* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0,
275
+ /* 32 */ 's', 'e', 't', 32, 'd', 'p', ',', 32, 0,
276
+ /* 41 */ 's', 'e', 't', 32, 's', 'p', ',', 32, 0,
277
+ /* 50 */ 'c', 'r', 'c', '3', '2', 32, 0,
278
+ /* 57 */ 'l', 'd', 'a', '1', '6', 32, 0,
279
+ /* 64 */ 's', 't', '1', '6', 32, 0,
280
+ /* 70 */ 'c', 'r', 'c', '8', 32, 0,
281
+ /* 76 */ 's', 't', '8', 32, 0,
282
+ /* 81 */ '#', 32, 'L', 'D', 'A', 'W', 'F', 'I', 32, 0,
283
+ /* 91 */ '#', 32, 'L', 'D', 'W', 'F', 'I', 32, 0,
284
+ /* 100 */ '#', 32, 'S', 'T', 'W', 'F', 'I', 32, 0,
285
+ /* 109 */ '#', 32, 'E', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 32, 0,
286
+ /* 122 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
287
+ /* 142 */ '#', 32, 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
288
+ /* 160 */ '#', 32, 'F', 'R', 'A', 'M', 'E', '_', 'T', 'O', '_', 'A', 'R', 'G', 'S', '_', 'O', 'F', 'F', 'S', 'E', 'T', 32, 0,
289
+ /* 184 */ 'b', 'l', 'a', 32, 0,
290
+ /* 189 */ 'l', 's', 'u', 'b', 32, 0,
291
+ /* 195 */ 'l', 'd', 'c', 32, 0,
292
+ /* 200 */ 'l', 'a', 'd', 'd', 32, 0,
293
+ /* 206 */ 'a', 'n', 'd', 32, 0,
294
+ /* 211 */ 'g', 'e', 't', 'd', 32, 0,
295
+ /* 217 */ 'b', 'f', 32, 0,
296
+ /* 221 */ 'e', 'e', 'f', 32, 0,
297
+ /* 226 */ 'w', 'a', 'i', 't', 'e', 'f', 32, 0,
298
+ /* 234 */ 'e', 'c', 'a', 'l', 'l', 'f', 32, 0,
299
+ /* 242 */ 'n', 'e', 'g', 32, 0,
300
+ /* 247 */ 'd', 'g', 'e', 't', 'r', 'e', 'g', 32, 0,
301
+ /* 256 */ 'p', 'e', 'e', 'k', 32, 0,
302
+ /* 262 */ 'm', 'k', 'm', 's', 'k', 32, 0,
303
+ /* 269 */ 'b', 'l', 32, 0,
304
+ /* 273 */ 't', 'e', 's', 't', 'l', 'c', 'l', 32, 0,
305
+ /* 282 */ 's', 'h', 'l', 32, 0,
306
+ /* 287 */ 'k', 'c', 'a', 'l', 'l', 32, 0,
307
+ /* 294 */ 'l', 'm', 'u', 'l', 32, 0,
308
+ /* 300 */ 'e', 'n', 'd', 'i', 'n', 32, 0,
309
+ /* 307 */ 'g', 'e', 't', 'n', 32, 0,
310
+ /* 313 */ 'e', 'x', 't', 'd', 'p', 32, 0,
311
+ /* 320 */ 'r', 'e', 't', 's', 'p', 32, 0,
312
+ /* 327 */ 'k', 'e', 'n', 't', 's', 'p', 32, 0,
313
+ /* 335 */ 'k', 'r', 'e', 's', 't', 's', 'p', 32, 0,
314
+ /* 344 */ 'e', 'x', 't', 's', 'p', 32, 0,
315
+ /* 351 */ 'e', 'q', 32, 0,
316
+ /* 355 */ 'a', 's', 'h', 'r', 32, 0,
317
+ /* 361 */ 'i', 'n', 's', 'h', 'r', 32, 0,
318
+ /* 368 */ 'x', 'o', 'r', 32, 0,
319
+ /* 373 */ 'c', 'l', 'r', 's', 'r', 32, 0,
320
+ /* 380 */ 's', 'e', 't', 's', 'r', 32, 0,
321
+ /* 387 */ 'g', 'e', 't', 'r', 32, 0,
322
+ /* 393 */ 'l', 'd', '1', '6', 's', 32, 0,
323
+ /* 400 */ 'm', 'a', 'c', 'c', 's', 32, 0,
324
+ /* 407 */ 'r', 'e', 'm', 's', 32, 0,
325
+ /* 413 */ 'l', 's', 's', 32, 0,
326
+ /* 418 */ 'g', 'e', 't', 't', 's', 32, 0,
327
+ /* 425 */ 'd', 'i', 'v', 's', 32, 0,
328
+ /* 431 */ 'b', 'l', 'a', 't', 32, 0,
329
+ /* 437 */ 'b', 't', 32, 0,
330
+ /* 441 */ 'i', 'n', 'c', 't', 32, 0,
331
+ /* 447 */ 't', 'e', 's', 't', 'c', 't', 32, 0,
332
+ /* 455 */ 't', 'e', 's', 't', 'w', 'c', 't', 32, 0,
333
+ /* 464 */ 'e', 'e', 't', 32, 0,
334
+ /* 469 */ 'g', 'e', 't', 32, 0,
335
+ /* 474 */ 'w', 'a', 'i', 't', 'e', 't', 32, 0,
336
+ /* 482 */ 'e', 'c', 'a', 'l', 'l', 't', 32, 0,
337
+ /* 490 */ 'i', 'n', 't', 32, 0,
338
+ /* 495 */ 'a', 'n', 'd', 'n', 'o', 't', 32, 0,
339
+ /* 503 */ 'g', 'e', 't', 's', 't', 32, 0,
340
+ /* 510 */ 's', 'e', 'x', 't', 32, 0,
341
+ /* 516 */ 'z', 'e', 'x', 't', 32, 0,
342
+ /* 522 */ 'l', 'd', '8', 'u', 32, 0,
343
+ /* 528 */ 'b', 'a', 'u', 32, 0,
344
+ /* 533 */ 'b', 'u', 32, 0,
345
+ /* 537 */ 'm', 'a', 'c', 'c', 'u', 32, 0,
346
+ /* 544 */ 'r', 'e', 'm', 'u', 32, 0,
347
+ /* 550 */ 'b', 'r', 'u', 32, 0,
348
+ /* 555 */ 'l', 's', 'u', 32, 0,
349
+ /* 560 */ 'l', 'd', 'i', 'v', 'u', 32, 0,
350
+ /* 567 */ 'b', 'y', 't', 'e', 'r', 'e', 'v', 32, 0,
351
+ /* 576 */ 'b', 'i', 't', 'r', 'e', 'v', 32, 0,
352
+ /* 584 */ 'l', 'd', 'a', 'w', 32, 0,
353
+ /* 590 */ 'l', 'd', 'w', 32, 0,
354
+ /* 595 */ 'i', 'n', 'p', 'w', 32, 0,
355
+ /* 601 */ 's', 't', 'w', 32, 0,
356
+ /* 606 */ 'c', 'l', 'z', 32, 0,
357
+ /* 611 */ '#', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
358
+ /* 631 */ 's', 'e', 't', 32, 'k', 'e', 'p', ',', 32, 'r', '1', '1', 0,
359
+ /* 644 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
360
+ /* 657 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
361
+ /* 664 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
362
+ /* 674 */ '#', 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
363
+ /* 686 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
364
+ /* 701 */ 'l', 'd', 'a', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
365
+ /* 715 */ 'l', 'd', 'w', 32, 'r', '1', '1', ',', 32, 'c', 'p', '[', 0,
366
+ /* 728 */ 'b', 'l', 'a', 32, 'c', 'p', '[', 0,
367
+ /* 736 */ 'm', 's', 'y', 'n', 'c', 32, 'r', 'e', 's', '[', 0,
368
+ /* 747 */ 's', 'e', 't', 'p', 's', 'c', 32, 'r', 'e', 's', '[', 0,
369
+ /* 759 */ 's', 'e', 't', 'c', 32, 'r', 'e', 's', '[', 0,
370
+ /* 769 */ 's', 'e', 't', 'd', 32, 'r', 'e', 's', '[', 0,
371
+ /* 779 */ 's', 'e', 't', 'c', 'l', 'k', 32, 'r', 'e', 's', '[', 0,
372
+ /* 791 */ 'm', 'j', 'o', 'i', 'n', 32, 'r', 'e', 's', '[', 0,
373
+ /* 802 */ 's', 'e', 't', 'n', 32, 'r', 'e', 's', '[', 0,
374
+ /* 812 */ 's', 'y', 'n', 'c', 'r', 32, 'r', 'e', 's', '[', 0,
375
+ /* 823 */ 'f', 'r', 'e', 'e', 'r', 32, 'r', 'e', 's', '[', 0,
376
+ /* 834 */ 'o', 'u', 't', 's', 'h', 'r', 32, 'r', 'e', 's', '[', 0,
377
+ /* 846 */ 'c', 'h', 'k', 'c', 't', 32, 'r', 'e', 's', '[', 0,
378
+ /* 857 */ 'o', 'u', 't', 'c', 't', 32, 'r', 'e', 's', '[', 0,
379
+ /* 868 */ 'c', 'l', 'r', 'p', 't', 32, 'r', 'e', 's', '[', 0,
380
+ /* 879 */ 's', 'e', 't', 'p', 't', 32, 'r', 'e', 's', '[', 0,
381
+ /* 890 */ 'o', 'u', 't', 't', 32, 'r', 'e', 's', '[', 0,
382
+ /* 900 */ 'o', 'u', 't', 32, 'r', 'e', 's', '[', 0,
383
+ /* 909 */ 'e', 'd', 'u', 32, 'r', 'e', 's', '[', 0,
384
+ /* 918 */ 'e', 'e', 'u', 32, 'r', 'e', 's', '[', 0,
385
+ /* 927 */ 's', 'e', 't', 'e', 'v', 32, 'r', 'e', 's', '[', 0,
386
+ /* 938 */ 's', 'e', 't', 'v', 32, 'r', 'e', 's', '[', 0,
387
+ /* 948 */ 'o', 'u', 't', 'p', 'w', 32, 'r', 'e', 's', '[', 0,
388
+ /* 959 */ 's', 'e', 't', 't', 'w', 32, 'r', 'e', 's', '[', 0,
389
+ /* 970 */ 's', 'e', 't', 'r', 'd', 'y', 32, 'r', 'e', 's', '[', 0,
390
+ /* 982 */ 's', 'e', 't', 32, 'p', 's', '[', 0,
391
+ /* 990 */ 's', 'e', 't', 32, 't', '[', 0,
392
+ /* 997 */ 'i', 'n', 'i', 't', 32, 't', '[', 0,
393
+ /* 1005 */ 's', 't', 'a', 'r', 't', 32, 't', '[', 0,
394
+ /* 1014 */ 'l', 'd', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
395
+ /* 1029 */ 's', 't', 'w', 32, 's', 'p', 'c', ',', 32, 's', 'p', '[', '1', ']', 0,
396
+ /* 1044 */ 'l', 'd', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
397
+ /* 1059 */ 's', 't', 'w', 32, 's', 's', 'r', ',', 32, 's', 'p', '[', '2', ']', 0,
398
+ /* 1074 */ 'l', 'd', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
399
+ /* 1089 */ 's', 't', 'w', 32, 's', 'e', 'd', ',', 32, 's', 'p', '[', '3', ']', 0,
400
+ /* 1104 */ 'l', 'd', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
401
+ /* 1118 */ 's', 't', 'w', 32, 'e', 't', ',', 32, 's', 'p', '[', '4', ']', 0,
402
+ /* 1132 */ 's', 's', 'y', 'n', 'c', 0,
403
+ /* 1138 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 'd', 0,
404
+ /* 1150 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'i', 'd', 0,
405
+ /* 1162 */ 'c', 'l', 'r', 'e', 0,
406
+ /* 1167 */ 'd', 'c', 'a', 'l', 'l', 0,
407
+ /* 1173 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 'e', 'p', 0,
408
+ /* 1186 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'k', 's', 'p', 0,
409
+ /* 1199 */ 'd', 'e', 'n', 't', 's', 'p', 0,
410
+ /* 1206 */ 'd', 'r', 'e', 's', 't', 's', 'p', 0,
411
+ /* 1214 */ 't', 's', 'e', 't', 'm', 'r', 32, 'r', 0,
412
+ /* 1223 */ 'g', 'e', 't', 32, 'r', '1', '1', ',', 32, 'e', 't', 0,
413
+ /* 1235 */ 'f', 'r', 'e', 'e', 't', 0,
414
+ /* 1241 */ 'd', 'r', 'e', 't', 0,
415
+ /* 1246 */ 'k', 'r', 'e', 't', 0,
416
+ /* 1251 */ 'w', 'a', 'i', 't', 'e', 'u', 0,
417
+ };
418
+
419
+ // Emit the opcode for the instruction.
420
+ uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
421
+ // assert(Bits != 0 && "Cannot print this instruction.");
422
+ #ifndef CAPSTONE_DIET
423
+ SStream_concat0(O, AsmStrs+(Bits & 2047)-1);
424
+ #endif
425
+
426
+
427
+ if (strchr((const char *)AsmStrs+(Bits & 2047)-1, '[')) {
428
+ set_mem_access(MI, true, 0);
429
+ }
430
+
431
+ // Fragment 0 encoded into 2 bits for 4 unique commands.
432
+ //printf(">>%s\n", AsmStrs+(Bits & 2047)-1);
433
+ //printf("Frag-0: %u\n", (Bits >> 11) & 3);
434
+ switch ((Bits >> 11) & 3) {
435
+ default: // unreachable.
436
+ case 0:
437
+ // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, CLRE_0R, DCALL_0R, DE...
438
+ // already done. this means we have to extract details out ourself.
439
+ XCore_insn_extract(MI, (const char *)AsmStrs+(Bits & 2047)-1);
440
+ return;
441
+ break;
442
+ case 1:
443
+ // ADD_2rus, ADD_3r, ADJCALLSTACKDOWN, ADJCALLSTACKUP, ANDNOT_2r, AND_3r,...
444
+ printOperand(MI, 0, O);
445
+ break;
446
+ case 2:
447
+ // BR_JT, BR_JT32, CRC8_l4r, INITCP_2r, INITDP_2r, INITLR_l2r, INITPC_2r,...
448
+ printOperand(MI, 1, O);
449
+ break;
450
+ case 3:
451
+ // OUTSHR_2r, TSETR_3r
452
+ printOperand(MI, 2, O);
453
+ break;
454
+ }
455
+
456
+
457
+ // Fragment 1 encoded into 5 bits for 17 unique commands.
458
+ //printf("Frag-1: %u\n", (Bits >> 13) & 31);
459
+ switch ((Bits >> 13) & 31) {
460
+ default: // unreachable.
461
+ case 0:
462
+ // ADD_2rus, ADD_3r, ANDNOT_2r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r,...
463
+ SStream_concat0(O, ", ");
464
+ break;
465
+ case 1:
466
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BAU_1r, BLAT_lu6, BLAT_u6, BLA_1r, B...
467
+ return;
468
+ break;
469
+ case 2:
470
+ // BLACP_lu10, BLACP_u10, CLRPT_1R, EDU_1r, EEU_1r, FREER_1r, LDAWCP_lu6,...
471
+ SStream_concat0(O, "]");
472
+ set_mem_access(MI, false, 0);
473
+ return;
474
+ break;
475
+ case 3:
476
+ // BR_JT, BR_JT32
477
+ SStream_concat0(O, "\n");
478
+ break;
479
+ case 4:
480
+ // CHKCT_2r, CHKCT_rus, OUTCT_2r, OUTCT_rus, OUTPW_l2rus, OUTSHR_2r, OUTT...
481
+ SStream_concat0(O, "], ");
482
+ set_mem_access(MI, false, 0);
483
+ break;
484
+ case 5:
485
+ // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
486
+ SStream_concat0(O, ", res[");
487
+ set_mem_access(MI, true, 0);
488
+ break;
489
+ case 6:
490
+ // GETPS_l2r
491
+ SStream_concat0(O, ", ps[");
492
+ set_mem_access(MI, true, 0);
493
+ printOperand(MI, 1, O);
494
+ SStream_concat0(O, "]");
495
+ set_mem_access(MI, false, 0);
496
+ return;
497
+ break;
498
+ case 7:
499
+ // INITCP_2r
500
+ SStream_concat0(O, "]:cp, ");
501
+ set_mem_access(MI, false, XCORE_REG_CP);
502
+ printOperand(MI, 0, O);
503
+ return;
504
+ break;
505
+ case 8:
506
+ // INITDP_2r
507
+ SStream_concat0(O, "]:dp, ");
508
+ set_mem_access(MI, false, XCORE_REG_DP);
509
+ printOperand(MI, 0, O);
510
+ return;
511
+ break;
512
+ case 9:
513
+ // INITLR_l2r
514
+ SStream_concat0(O, "]:lr, ");
515
+ set_mem_access(MI, false, XCORE_REG_LR);
516
+ printOperand(MI, 0, O);
517
+ return;
518
+ break;
519
+ case 10:
520
+ // INITPC_2r
521
+ SStream_concat0(O, "]:pc, ");
522
+ set_mem_access(MI, false, XCORE_REG_PC);
523
+ printOperand(MI, 0, O);
524
+ return;
525
+ break;
526
+ case 11:
527
+ // INITSP_2r
528
+ SStream_concat0(O, "]:sp, ");
529
+ set_mem_access(MI, false, XCORE_REG_SP);
530
+ printOperand(MI, 0, O);
531
+ return;
532
+ break;
533
+ case 12:
534
+ // LDAWDP_lru6, LDAWDP_ru6, LDWDP_lru6, LDWDP_ru6, STWDP_lru6, STWDP_ru6
535
+ SStream_concat0(O, ", dp[");
536
+ set_mem_access(MI, true, XCORE_REG_DP);
537
+ printOperand(MI, 1, O);
538
+ SStream_concat0(O, "]");
539
+ set_mem_access(MI, false, 0);
540
+ return;
541
+ break;
542
+ case 13:
543
+ // LDAWSP_lru6, LDAWSP_ru6, LDWSP_lru6, LDWSP_ru6, STWSP_lru6, STWSP_ru6
544
+ SStream_concat0(O, ", sp[");
545
+ set_mem_access(MI, true, XCORE_REG_SP);
546
+ printOperand(MI, 1, O);
547
+ SStream_concat0(O, "]");
548
+ set_mem_access(MI, false, 0);
549
+ return;
550
+ break;
551
+ case 14:
552
+ // LDWCP_lru6, LDWCP_ru6
553
+ SStream_concat0(O, ", cp[");
554
+ set_mem_access(MI, true, XCORE_REG_CP);
555
+ printOperand(MI, 1, O);
556
+ SStream_concat0(O, "]");
557
+ set_mem_access(MI, false, 0);
558
+ return;
559
+ break;
560
+ case 15:
561
+ // SETEV_1r, SETV_1r
562
+ SStream_concat0(O, "], r11");
563
+ set_mem_access(MI, false, 0);
564
+ return;
565
+ break;
566
+ case 16:
567
+ // TSETR_3r
568
+ SStream_concat0(O, "]:r");
569
+ set_mem_access(MI, false, 0);
570
+ printOperand(MI, 0, O);
571
+ SStream_concat0(O, ", ");
572
+ printOperand(MI, 1, O);
573
+ return;
574
+ break;
575
+ }
576
+
577
+
578
+ // Fragment 2 encoded into 3 bits for 5 unique commands.
579
+ //printf("Frag-2: %u\n", (Bits >> 18) & 7);
580
+ switch ((Bits >> 18) & 7) {
581
+ default: // unreachable.
582
+ case 0:
583
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, BITREV_l2r, BRBF_lru6,...
584
+ printOperand(MI, 1, O);
585
+ break;
586
+ case 1:
587
+ // ANDNOT_2r, CRC_l3r, INSHR_2r, SEXT_2r, SEXT_rus, ZEXT_2r, ZEXT_rus
588
+ printOperand(MI, 2, O);
589
+ break;
590
+ case 2:
591
+ // BR_JT
592
+ printInlineJT(MI, 0, O);
593
+ return;
594
+ break;
595
+ case 3:
596
+ // BR_JT32
597
+ printInlineJT32(MI, 0, O);
598
+ return;
599
+ break;
600
+ case 4:
601
+ // CRC8_l4r, LADD_l5r, LSUB_l5r, OUTPW_l2rus
602
+ printOperand(MI, 0, O);
603
+ SStream_concat0(O, ", ");
604
+ break;
605
+ }
606
+
607
+
608
+ // Fragment 3 encoded into 3 bits for 8 unique commands.
609
+ //printf("Frag-3: %u\n", (Bits >> 21) & 7);
610
+ switch ((Bits >> 21) & 7) {
611
+ default: // unreachable.
612
+ case 0:
613
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, CRC_l3r, DIVS_l3r, DIV...
614
+ SStream_concat0(O, ", ");
615
+ break;
616
+ case 1:
617
+ // ANDNOT_2r, BITREV_l2r, BRBF_lru6, BRBF_ru6, BRBT_lru6, BRBT_ru6, BRFF_...
618
+ return;
619
+ break;
620
+ case 2:
621
+ // CRC8_l4r
622
+ printOperand(MI, 3, O);
623
+ SStream_concat0(O, ", ");
624
+ printOperand(MI, 4, O);
625
+ return;
626
+ break;
627
+ case 3:
628
+ // EEF_2r, EET_2r, ENDIN_2r, GETD_l2r, GETN_l2r, GETST_2r, GETTS_2r, INCT...
629
+ SStream_concat0(O, "]");
630
+ set_mem_access(MI, false, 0);
631
+ return;
632
+ break;
633
+ case 4:
634
+ // INPW_l2rus
635
+ SStream_concat0(O, "], ");
636
+ set_mem_access(MI, false, 0);
637
+ printOperand(MI, 2, O);
638
+ return;
639
+ break;
640
+ case 5:
641
+ // LADD_l5r, LSUB_l5r, OUTPW_l2rus
642
+ printOperand(MI, 2, O);
643
+ break;
644
+ case 6:
645
+ // LD16S_3r, LD8U_3r, LDA16F_l3r, LDAWF_l2rus, LDAWF_l3r, LDW_2rus, LDW_3...
646
+ SStream_concat0(O, "[");
647
+ set_mem_access(MI, true, 0xffff);
648
+ printOperand(MI, 2, O);
649
+ SStream_concat0(O, "]");
650
+ set_mem_access(MI, false, 0);
651
+ return;
652
+ break;
653
+ case 7:
654
+ // LDA16B_l3r, LDAWB_l2rus, LDAWB_l3r
655
+ SStream_concat0(O, "[-");
656
+ set_mem_access(MI, true, -0xffff);
657
+ printOperand(MI, 2, O);
658
+ SStream_concat0(O, "]");
659
+ set_mem_access(MI, false, 0);
660
+ return;
661
+ break;
662
+ }
663
+
664
+
665
+ // Fragment 4 encoded into 3 bits for 5 unique commands.
666
+ //printf("Frag-4: %u\n", (Bits >> 24) & 7);
667
+ switch ((Bits >> 24) & 7) {
668
+ default: // unreachable.
669
+ case 0:
670
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
671
+ printOperand(MI, 2, O);
672
+ break;
673
+ case 1:
674
+ // CRC_l3r
675
+ printOperand(MI, 3, O);
676
+ return;
677
+ break;
678
+ case 2:
679
+ // LADD_l5r, LSUB_l5r
680
+ SStream_concat0(O, ", ");
681
+ printOperand(MI, 3, O);
682
+ SStream_concat0(O, ", ");
683
+ printOperand(MI, 4, O);
684
+ return;
685
+ break;
686
+ case 3:
687
+ // LDIVU_l5r, MACCS_l4r, MACCU_l4r
688
+ printOperand(MI, 4, O);
689
+ SStream_concat0(O, ", ");
690
+ break;
691
+ case 4:
692
+ // OUTPW_l2rus
693
+ return;
694
+ break;
695
+ }
696
+
697
+
698
+ // Fragment 5 encoded into 2 bits for 4 unique commands.
699
+ //printf("Frag-5: %u\n", (Bits >> 27) & 3);
700
+ switch ((Bits >> 27) & 3) {
701
+ default: // unreachable.
702
+ case 0:
703
+ // ADD_2rus, ADD_3r, AND_3r, ASHR_l2rus, ASHR_l3r, DIVS_l3r, DIVU_l3r, EQ...
704
+ return;
705
+ break;
706
+ case 1:
707
+ // LDIVU_l5r
708
+ printOperand(MI, 2, O);
709
+ SStream_concat0(O, ", ");
710
+ printOperand(MI, 3, O);
711
+ return;
712
+ break;
713
+ case 2:
714
+ // LMUL_l6r
715
+ SStream_concat0(O, ", ");
716
+ printOperand(MI, 3, O);
717
+ SStream_concat0(O, ", ");
718
+ printOperand(MI, 4, O);
719
+ SStream_concat0(O, ", ");
720
+ printOperand(MI, 5, O);
721
+ return;
722
+ break;
723
+ case 3:
724
+ // MACCS_l4r, MACCU_l4r
725
+ printOperand(MI, 5, O);
726
+ return;
727
+ break;
728
+ }
729
+ }
730
+
731
+
732
+ /// getRegisterName - This method is automatically generated by tblgen
733
+ /// from the register set description. This returns the assembler name
734
+ /// for the specified register.
735
+ static const char *getRegisterName(unsigned RegNo)
736
+ {
737
+ // assert(RegNo && RegNo < 17 && "Invalid register number!");
738
+
739
+ #ifndef CAPSTONE_DIET
740
+ static const char AsmStrs[] = {
741
+ /* 0 */ 'r', '1', '0', 0,
742
+ /* 4 */ 'r', '0', 0,
743
+ /* 7 */ 'r', '1', '1', 0,
744
+ /* 11 */ 'r', '1', 0,
745
+ /* 14 */ 'r', '2', 0,
746
+ /* 17 */ 'r', '3', 0,
747
+ /* 20 */ 'r', '4', 0,
748
+ /* 23 */ 'r', '5', 0,
749
+ /* 26 */ 'r', '6', 0,
750
+ /* 29 */ 'r', '7', 0,
751
+ /* 32 */ 'r', '8', 0,
752
+ /* 35 */ 'r', '9', 0,
753
+ /* 38 */ 'c', 'p', 0,
754
+ /* 41 */ 'd', 'p', 0,
755
+ /* 44 */ 's', 'p', 0,
756
+ /* 47 */ 'l', 'r', 0,
757
+ };
758
+
759
+ static const uint8_t RegAsmOffset[] = {
760
+ 38, 41, 47, 44, 4, 11, 14, 17, 20, 23, 26, 29, 32, 35,
761
+ 0, 7,
762
+ };
763
+
764
+ //int i;
765
+ //for (i = 0; i < sizeof(RegAsmOffset); i++)
766
+ // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
767
+ //printf("*************************\n");
768
+ return AsmStrs+RegAsmOffset[RegNo-1];
769
+ #else
770
+ return NULL;
771
+ #endif
772
+ }