hexcore-capstone 1.2.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (332) hide show
  1. package/LICENSE +26 -0
  2. package/README.md +191 -0
  3. package/binding.gyp +168 -0
  4. package/deps/capstone/LEB128.h +38 -0
  5. package/deps/capstone/MCDisassembler.h +14 -0
  6. package/deps/capstone/MCFixedLenDisassembler.h +32 -0
  7. package/deps/capstone/MCInst.c +270 -0
  8. package/deps/capstone/MCInst.h +165 -0
  9. package/deps/capstone/MCInstrDesc.c +41 -0
  10. package/deps/capstone/MCInstrDesc.h +167 -0
  11. package/deps/capstone/MCRegisterInfo.c +151 -0
  12. package/deps/capstone/MCRegisterInfo.h +116 -0
  13. package/deps/capstone/Mapping.c +254 -0
  14. package/deps/capstone/Mapping.h +174 -0
  15. package/deps/capstone/MathExtras.h +442 -0
  16. package/deps/capstone/SStream.c +181 -0
  17. package/deps/capstone/SStream.h +40 -0
  18. package/deps/capstone/arch/AArch64/AArch64AddressingModes.h +945 -0
  19. package/deps/capstone/arch/AArch64/AArch64BaseInfo.c +77 -0
  20. package/deps/capstone/arch/AArch64/AArch64BaseInfo.h +585 -0
  21. package/deps/capstone/arch/AArch64/AArch64Disassembler.c +2280 -0
  22. package/deps/capstone/arch/AArch64/AArch64Disassembler.h +18 -0
  23. package/deps/capstone/arch/AArch64/AArch64GenAsmWriter.inc +26589 -0
  24. package/deps/capstone/arch/AArch64/AArch64GenDisassemblerTables.inc +27322 -0
  25. package/deps/capstone/arch/AArch64/AArch64GenInstrInfo.inc +13194 -0
  26. package/deps/capstone/arch/AArch64/AArch64GenRegisterInfo.inc +3814 -0
  27. package/deps/capstone/arch/AArch64/AArch64GenRegisterName.inc +714 -0
  28. package/deps/capstone/arch/AArch64/AArch64GenRegisterV.inc +673 -0
  29. package/deps/capstone/arch/AArch64/AArch64GenSubtargetInfo.inc +229 -0
  30. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands.inc +2863 -0
  31. package/deps/capstone/arch/AArch64/AArch64GenSystemOperands_enum.inc +21 -0
  32. package/deps/capstone/arch/AArch64/AArch64InstPrinter.c +3029 -0
  33. package/deps/capstone/arch/AArch64/AArch64InstPrinter.h +28 -0
  34. package/deps/capstone/arch/AArch64/AArch64Mapping.c +883 -0
  35. package/deps/capstone/arch/AArch64/AArch64Mapping.h +43 -0
  36. package/deps/capstone/arch/AArch64/AArch64MappingInsn.inc +37790 -0
  37. package/deps/capstone/arch/AArch64/AArch64MappingInsnName.inc +1282 -0
  38. package/deps/capstone/arch/AArch64/AArch64MappingInsnOp.inc +26994 -0
  39. package/deps/capstone/arch/AArch64/AArch64Module.c +44 -0
  40. package/deps/capstone/arch/AArch64/AArch64Module.h +12 -0
  41. package/deps/capstone/arch/ARM/ARMAddressingModes.h +698 -0
  42. package/deps/capstone/arch/ARM/ARMBaseInfo.h +486 -0
  43. package/deps/capstone/arch/ARM/ARMDisassembler.c +5763 -0
  44. package/deps/capstone/arch/ARM/ARMDisassembler.h +18 -0
  45. package/deps/capstone/arch/ARM/ARMGenAsmWriter.inc +9545 -0
  46. package/deps/capstone/arch/ARM/ARMGenDisassemblerTables.inc +15185 -0
  47. package/deps/capstone/arch/ARM/ARMGenInstrInfo.inc +6632 -0
  48. package/deps/capstone/arch/ARM/ARMGenRegisterInfo.inc +2102 -0
  49. package/deps/capstone/arch/ARM/ARMGenRegisterName.inc +231 -0
  50. package/deps/capstone/arch/ARM/ARMGenRegisterName_digit.inc +231 -0
  51. package/deps/capstone/arch/ARM/ARMGenSubtargetInfo.inc +162 -0
  52. package/deps/capstone/arch/ARM/ARMGenSystemRegister.inc +270 -0
  53. package/deps/capstone/arch/ARM/ARMInstPrinter.c +3364 -0
  54. package/deps/capstone/arch/ARM/ARMInstPrinter.h +43 -0
  55. package/deps/capstone/arch/ARM/ARMMapping.c +551 -0
  56. package/deps/capstone/arch/ARM/ARMMapping.h +40 -0
  57. package/deps/capstone/arch/ARM/ARMMappingInsn.inc +18772 -0
  58. package/deps/capstone/arch/ARM/ARMMappingInsnName.inc +475 -0
  59. package/deps/capstone/arch/ARM/ARMMappingInsnOp.inc +10729 -0
  60. package/deps/capstone/arch/ARM/ARMModule.c +63 -0
  61. package/deps/capstone/arch/ARM/ARMModule.h +12 -0
  62. package/deps/capstone/arch/BPF/BPFConstants.h +88 -0
  63. package/deps/capstone/arch/BPF/BPFDisassembler.c +464 -0
  64. package/deps/capstone/arch/BPF/BPFDisassembler.h +27 -0
  65. package/deps/capstone/arch/BPF/BPFInstPrinter.c +285 -0
  66. package/deps/capstone/arch/BPF/BPFInstPrinter.h +16 -0
  67. package/deps/capstone/arch/BPF/BPFMapping.c +513 -0
  68. package/deps/capstone/arch/BPF/BPFMapping.h +21 -0
  69. package/deps/capstone/arch/BPF/BPFModule.c +34 -0
  70. package/deps/capstone/arch/BPF/BPFModule.h +12 -0
  71. package/deps/capstone/arch/EVM/EVMDisassembler.c +379 -0
  72. package/deps/capstone/arch/EVM/EVMDisassembler.h +12 -0
  73. package/deps/capstone/arch/EVM/EVMInstPrinter.c +20 -0
  74. package/deps/capstone/arch/EVM/EVMInstPrinter.h +17 -0
  75. package/deps/capstone/arch/EVM/EVMMapping.c +344 -0
  76. package/deps/capstone/arch/EVM/EVMMapping.h +8 -0
  77. package/deps/capstone/arch/EVM/EVMMappingInsn.inc +259 -0
  78. package/deps/capstone/arch/EVM/EVMModule.c +33 -0
  79. package/deps/capstone/arch/EVM/EVMModule.h +12 -0
  80. package/deps/capstone/arch/M680X/M680XDisassembler.c +2307 -0
  81. package/deps/capstone/arch/M680X/M680XDisassembler.h +17 -0
  82. package/deps/capstone/arch/M680X/M680XDisassemblerInternals.h +57 -0
  83. package/deps/capstone/arch/M680X/M680XInstPrinter.c +360 -0
  84. package/deps/capstone/arch/M680X/M680XInstPrinter.h +25 -0
  85. package/deps/capstone/arch/M680X/M680XModule.c +77 -0
  86. package/deps/capstone/arch/M680X/M680XModule.h +12 -0
  87. package/deps/capstone/arch/M680X/cpu12.inc +335 -0
  88. package/deps/capstone/arch/M680X/hcs08.inc +60 -0
  89. package/deps/capstone/arch/M680X/hd6301.inc +15 -0
  90. package/deps/capstone/arch/M680X/hd6309.inc +259 -0
  91. package/deps/capstone/arch/M680X/insn_props.inc +367 -0
  92. package/deps/capstone/arch/M680X/m6800.inc +277 -0
  93. package/deps/capstone/arch/M680X/m6801.inc +39 -0
  94. package/deps/capstone/arch/M680X/m6805.inc +277 -0
  95. package/deps/capstone/arch/M680X/m6808.inc +91 -0
  96. package/deps/capstone/arch/M680X/m6809.inc +352 -0
  97. package/deps/capstone/arch/M680X/m6811.inc +105 -0
  98. package/deps/capstone/arch/M68K/M68KDisassembler.c +3668 -0
  99. package/deps/capstone/arch/M68K/M68KDisassembler.h +30 -0
  100. package/deps/capstone/arch/M68K/M68KInstPrinter.c +387 -0
  101. package/deps/capstone/arch/M68K/M68KInstPrinter.h +21 -0
  102. package/deps/capstone/arch/M68K/M68KInstructionTable.inc +65540 -0
  103. package/deps/capstone/arch/M68K/M68KModule.c +42 -0
  104. package/deps/capstone/arch/M68K/M68KModule.h +12 -0
  105. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.c +544 -0
  106. package/deps/capstone/arch/MOS65XX/MOS65XXDisassembler.h +22 -0
  107. package/deps/capstone/arch/MOS65XX/MOS65XXDisassemblerInternals.h +23 -0
  108. package/deps/capstone/arch/MOS65XX/MOS65XXModule.c +79 -0
  109. package/deps/capstone/arch/MOS65XX/MOS65XXModule.h +12 -0
  110. package/deps/capstone/arch/MOS65XX/instruction_info.inc +106 -0
  111. package/deps/capstone/arch/MOS65XX/m6502.inc +256 -0
  112. package/deps/capstone/arch/MOS65XX/m65816.inc +256 -0
  113. package/deps/capstone/arch/MOS65XX/m65c02.inc +256 -0
  114. package/deps/capstone/arch/MOS65XX/mw65c02.inc +256 -0
  115. package/deps/capstone/arch/Mips/MipsDisassembler.c +1794 -0
  116. package/deps/capstone/arch/Mips/MipsDisassembler.h +16 -0
  117. package/deps/capstone/arch/Mips/MipsGenAsmWriter.inc +5725 -0
  118. package/deps/capstone/arch/Mips/MipsGenDisassemblerTables.inc +6942 -0
  119. package/deps/capstone/arch/Mips/MipsGenInstrInfo.inc +1805 -0
  120. package/deps/capstone/arch/Mips/MipsGenRegisterInfo.inc +1679 -0
  121. package/deps/capstone/arch/Mips/MipsGenSubtargetInfo.inc +52 -0
  122. package/deps/capstone/arch/Mips/MipsInstPrinter.c +424 -0
  123. package/deps/capstone/arch/Mips/MipsInstPrinter.h +25 -0
  124. package/deps/capstone/arch/Mips/MipsMapping.c +1070 -0
  125. package/deps/capstone/arch/Mips/MipsMapping.h +25 -0
  126. package/deps/capstone/arch/Mips/MipsMappingInsn.inc +9315 -0
  127. package/deps/capstone/arch/Mips/MipsModule.c +52 -0
  128. package/deps/capstone/arch/Mips/MipsModule.h +12 -0
  129. package/deps/capstone/arch/PowerPC/PPCDisassembler.c +627 -0
  130. package/deps/capstone/arch/PowerPC/PPCDisassembler.h +17 -0
  131. package/deps/capstone/arch/PowerPC/PPCGenAsmWriter.inc +11451 -0
  132. package/deps/capstone/arch/PowerPC/PPCGenDisassemblerTables.inc +6886 -0
  133. package/deps/capstone/arch/PowerPC/PPCGenInstrInfo.inc +4772 -0
  134. package/deps/capstone/arch/PowerPC/PPCGenRegisterInfo.inc +1122 -0
  135. package/deps/capstone/arch/PowerPC/PPCGenRegisterName.inc +278 -0
  136. package/deps/capstone/arch/PowerPC/PPCGenSubtargetInfo.inc +90 -0
  137. package/deps/capstone/arch/PowerPC/PPCInstPrinter.c +1238 -0
  138. package/deps/capstone/arch/PowerPC/PPCInstPrinter.h +15 -0
  139. package/deps/capstone/arch/PowerPC/PPCMapping.c +570 -0
  140. package/deps/capstone/arch/PowerPC/PPCMapping.h +40 -0
  141. package/deps/capstone/arch/PowerPC/PPCMappingInsn.inc +13220 -0
  142. package/deps/capstone/arch/PowerPC/PPCMappingInsnName.inc +1731 -0
  143. package/deps/capstone/arch/PowerPC/PPCModule.c +45 -0
  144. package/deps/capstone/arch/PowerPC/PPCModule.h +12 -0
  145. package/deps/capstone/arch/PowerPC/PPCPredicates.h +62 -0
  146. package/deps/capstone/arch/RISCV/RISCVBaseInfo.h +106 -0
  147. package/deps/capstone/arch/RISCV/RISCVDisassembler.c +433 -0
  148. package/deps/capstone/arch/RISCV/RISCVDisassembler.h +18 -0
  149. package/deps/capstone/arch/RISCV/RISCVGenAsmWriter.inc +2651 -0
  150. package/deps/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc +1776 -0
  151. package/deps/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc +275 -0
  152. package/deps/capstone/arch/RISCV/RISCVGenInstrInfo.inc +470 -0
  153. package/deps/capstone/arch/RISCV/RISCVGenRegisterInfo.inc +426 -0
  154. package/deps/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc +33 -0
  155. package/deps/capstone/arch/RISCV/RISCVInstPrinter.c +447 -0
  156. package/deps/capstone/arch/RISCV/RISCVInstPrinter.h +24 -0
  157. package/deps/capstone/arch/RISCV/RISCVMapping.c +366 -0
  158. package/deps/capstone/arch/RISCV/RISCVMapping.h +22 -0
  159. package/deps/capstone/arch/RISCV/RISCVMappingInsn.inc +1635 -0
  160. package/deps/capstone/arch/RISCV/RISCVModule.c +42 -0
  161. package/deps/capstone/arch/RISCV/RISCVModule.h +12 -0
  162. package/deps/capstone/arch/SH/SHDisassembler.c +2221 -0
  163. package/deps/capstone/arch/SH/SHDisassembler.h +19 -0
  164. package/deps/capstone/arch/SH/SHInsnTable.inc +66 -0
  165. package/deps/capstone/arch/SH/SHInstPrinter.c +438 -0
  166. package/deps/capstone/arch/SH/SHInstPrinter.h +23 -0
  167. package/deps/capstone/arch/SH/SHModule.c +39 -0
  168. package/deps/capstone/arch/SH/SHModule.h +12 -0
  169. package/deps/capstone/arch/SH/mktable.rb +390 -0
  170. package/deps/capstone/arch/Sparc/Sparc.h +63 -0
  171. package/deps/capstone/arch/Sparc/SparcDisassembler.c +500 -0
  172. package/deps/capstone/arch/Sparc/SparcDisassembler.h +17 -0
  173. package/deps/capstone/arch/Sparc/SparcGenAsmWriter.inc +5709 -0
  174. package/deps/capstone/arch/Sparc/SparcGenDisassemblerTables.inc +2028 -0
  175. package/deps/capstone/arch/Sparc/SparcGenInstrInfo.inc +514 -0
  176. package/deps/capstone/arch/Sparc/SparcGenRegisterInfo.inc +451 -0
  177. package/deps/capstone/arch/Sparc/SparcGenSubtargetInfo.inc +27 -0
  178. package/deps/capstone/arch/Sparc/SparcInstPrinter.c +446 -0
  179. package/deps/capstone/arch/Sparc/SparcInstPrinter.h +17 -0
  180. package/deps/capstone/arch/Sparc/SparcMapping.c +665 -0
  181. package/deps/capstone/arch/Sparc/SparcMapping.h +34 -0
  182. package/deps/capstone/arch/Sparc/SparcMappingInsn.inc +2643 -0
  183. package/deps/capstone/arch/Sparc/SparcModule.c +45 -0
  184. package/deps/capstone/arch/Sparc/SparcModule.h +12 -0
  185. package/deps/capstone/arch/SystemZ/SystemZDisassembler.c +484 -0
  186. package/deps/capstone/arch/SystemZ/SystemZDisassembler.h +17 -0
  187. package/deps/capstone/arch/SystemZ/SystemZGenAsmWriter.inc +11575 -0
  188. package/deps/capstone/arch/SystemZ/SystemZGenDisassemblerTables.inc +10262 -0
  189. package/deps/capstone/arch/SystemZ/SystemZGenInsnNameMaps.inc +2348 -0
  190. package/deps/capstone/arch/SystemZ/SystemZGenInstrInfo.inc +2820 -0
  191. package/deps/capstone/arch/SystemZ/SystemZGenRegisterInfo.inc +741 -0
  192. package/deps/capstone/arch/SystemZ/SystemZGenSubtargetInfo.inc +49 -0
  193. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.c +433 -0
  194. package/deps/capstone/arch/SystemZ/SystemZInstPrinter.h +15 -0
  195. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.c +195 -0
  196. package/deps/capstone/arch/SystemZ/SystemZMCTargetDesc.h +51 -0
  197. package/deps/capstone/arch/SystemZ/SystemZMapping.c +479 -0
  198. package/deps/capstone/arch/SystemZ/SystemZMapping.h +23 -0
  199. package/deps/capstone/arch/SystemZ/SystemZMappingInsn.inc +14175 -0
  200. package/deps/capstone/arch/SystemZ/SystemZModule.c +44 -0
  201. package/deps/capstone/arch/SystemZ/SystemZModule.h +12 -0
  202. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.c +628 -0
  203. package/deps/capstone/arch/TMS320C64x/TMS320C64xDisassembler.h +19 -0
  204. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +684 -0
  205. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc +1352 -0
  206. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenInstrInfo.inc +298 -0
  207. package/deps/capstone/arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc +277 -0
  208. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.c +572 -0
  209. package/deps/capstone/arch/TMS320C64x/TMS320C64xInstPrinter.h +15 -0
  210. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.c +1926 -0
  211. package/deps/capstone/arch/TMS320C64x/TMS320C64xMapping.h +26 -0
  212. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.c +39 -0
  213. package/deps/capstone/arch/TMS320C64x/TMS320C64xModule.h +12 -0
  214. package/deps/capstone/arch/TriCore/TriCore.td +134 -0
  215. package/deps/capstone/arch/TriCore/TriCoreCallingConv.td +61 -0
  216. package/deps/capstone/arch/TriCore/TriCoreDisassembler.c +1655 -0
  217. package/deps/capstone/arch/TriCore/TriCoreDisassembler.h +18 -0
  218. package/deps/capstone/arch/TriCore/TriCoreGenAsmWriter.inc +3691 -0
  219. package/deps/capstone/arch/TriCore/TriCoreGenCSFeatureName.inc +22 -0
  220. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsn.inc +8938 -0
  221. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnName.inc +404 -0
  222. package/deps/capstone/arch/TriCore/TriCoreGenCSMappingInsnOp.inc +7994 -0
  223. package/deps/capstone/arch/TriCore/TriCoreGenCSOpGroup.inc +32 -0
  224. package/deps/capstone/arch/TriCore/TriCoreGenDisassemblerTables.inc +4044 -0
  225. package/deps/capstone/arch/TriCore/TriCoreGenInstrInfo.inc +2693 -0
  226. package/deps/capstone/arch/TriCore/TriCoreGenRegisterInfo.inc +295 -0
  227. package/deps/capstone/arch/TriCore/TriCoreGenSubtargetInfo.inc +40 -0
  228. package/deps/capstone/arch/TriCore/TriCoreInstPrinter.c +488 -0
  229. package/deps/capstone/arch/TriCore/TriCoreInstrFormats.td +773 -0
  230. package/deps/capstone/arch/TriCore/TriCoreInstrInfo.td +1873 -0
  231. package/deps/capstone/arch/TriCore/TriCoreLinkage.h +21 -0
  232. package/deps/capstone/arch/TriCore/TriCoreMapping.c +241 -0
  233. package/deps/capstone/arch/TriCore/TriCoreMapping.h +32 -0
  234. package/deps/capstone/arch/TriCore/TriCoreModule.c +44 -0
  235. package/deps/capstone/arch/TriCore/TriCoreModule.h +11 -0
  236. package/deps/capstone/arch/TriCore/TriCoreRegisterInfo.td +153 -0
  237. package/deps/capstone/arch/WASM/WASMDisassembler.c +1009 -0
  238. package/deps/capstone/arch/WASM/WASMDisassembler.h +12 -0
  239. package/deps/capstone/arch/WASM/WASMInstPrinter.c +47 -0
  240. package/deps/capstone/arch/WASM/WASMInstPrinter.h +18 -0
  241. package/deps/capstone/arch/WASM/WASMMapping.c +333 -0
  242. package/deps/capstone/arch/WASM/WASMMapping.h +9 -0
  243. package/deps/capstone/arch/WASM/WASMModule.c +33 -0
  244. package/deps/capstone/arch/WASM/WASMModule.h +12 -0
  245. package/deps/capstone/arch/X86/X86ATTInstPrinter.c +997 -0
  246. package/deps/capstone/arch/X86/X86BaseInfo.h +50 -0
  247. package/deps/capstone/arch/X86/X86Disassembler.c +1033 -0
  248. package/deps/capstone/arch/X86/X86Disassembler.h +28 -0
  249. package/deps/capstone/arch/X86/X86DisassemblerDecoder.c +2358 -0
  250. package/deps/capstone/arch/X86/X86DisassemblerDecoder.h +725 -0
  251. package/deps/capstone/arch/X86/X86DisassemblerDecoderCommon.h +483 -0
  252. package/deps/capstone/arch/X86/X86GenAsmWriter.inc +49199 -0
  253. package/deps/capstone/arch/X86/X86GenAsmWriter1.inc +33196 -0
  254. package/deps/capstone/arch/X86/X86GenAsmWriter1_reduce.inc +2531 -0
  255. package/deps/capstone/arch/X86/X86GenAsmWriter_reduce.inc +2855 -0
  256. package/deps/capstone/arch/X86/X86GenDisassemblerTables.inc +112961 -0
  257. package/deps/capstone/arch/X86/X86GenDisassemblerTables2.inc +102151 -0
  258. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce.inc +28047 -0
  259. package/deps/capstone/arch/X86/X86GenDisassemblerTables_reduce2.inc +18827 -0
  260. package/deps/capstone/arch/X86/X86GenInstrInfo.inc +15158 -0
  261. package/deps/capstone/arch/X86/X86GenInstrInfo_reduce.inc +1564 -0
  262. package/deps/capstone/arch/X86/X86GenRegisterInfo.inc +1549 -0
  263. package/deps/capstone/arch/X86/X86GenRegisterName.inc +292 -0
  264. package/deps/capstone/arch/X86/X86GenRegisterName1.inc +291 -0
  265. package/deps/capstone/arch/X86/X86ImmSize.inc +335 -0
  266. package/deps/capstone/arch/X86/X86InstPrinter.h +26 -0
  267. package/deps/capstone/arch/X86/X86InstPrinterCommon.c +116 -0
  268. package/deps/capstone/arch/X86/X86InstPrinterCommon.h +16 -0
  269. package/deps/capstone/arch/X86/X86IntelInstPrinter.c +1061 -0
  270. package/deps/capstone/arch/X86/X86Lookup16.inc +16874 -0
  271. package/deps/capstone/arch/X86/X86Lookup16_reduce.inc +2308 -0
  272. package/deps/capstone/arch/X86/X86Mapping.c +2266 -0
  273. package/deps/capstone/arch/X86/X86Mapping.h +96 -0
  274. package/deps/capstone/arch/X86/X86MappingInsn.inc +105977 -0
  275. package/deps/capstone/arch/X86/X86MappingInsnName.inc +1527 -0
  276. package/deps/capstone/arch/X86/X86MappingInsnName_reduce.inc +348 -0
  277. package/deps/capstone/arch/X86/X86MappingInsnOp.inc +75700 -0
  278. package/deps/capstone/arch/X86/X86MappingInsnOp_reduce.inc +7729 -0
  279. package/deps/capstone/arch/X86/X86MappingInsn_reduce.inc +10819 -0
  280. package/deps/capstone/arch/X86/X86MappingReg.inc +280 -0
  281. package/deps/capstone/arch/X86/X86Module.c +94 -0
  282. package/deps/capstone/arch/X86/X86Module.h +12 -0
  283. package/deps/capstone/arch/XCore/XCoreDisassembler.c +794 -0
  284. package/deps/capstone/arch/XCore/XCoreDisassembler.h +17 -0
  285. package/deps/capstone/arch/XCore/XCoreGenAsmWriter.inc +772 -0
  286. package/deps/capstone/arch/XCore/XCoreGenDisassemblerTables.inc +853 -0
  287. package/deps/capstone/arch/XCore/XCoreGenInstrInfo.inc +267 -0
  288. package/deps/capstone/arch/XCore/XCoreGenRegisterInfo.inc +110 -0
  289. package/deps/capstone/arch/XCore/XCoreInstPrinter.c +250 -0
  290. package/deps/capstone/arch/XCore/XCoreInstPrinter.h +18 -0
  291. package/deps/capstone/arch/XCore/XCoreMapping.c +297 -0
  292. package/deps/capstone/arch/XCore/XCoreMapping.h +26 -0
  293. package/deps/capstone/arch/XCore/XCoreMappingInsn.inc +1287 -0
  294. package/deps/capstone/arch/XCore/XCoreModule.c +41 -0
  295. package/deps/capstone/arch/XCore/XCoreModule.h +12 -0
  296. package/deps/capstone/cs.c +1664 -0
  297. package/deps/capstone/cs_priv.h +101 -0
  298. package/deps/capstone/cs_simple_types.h +886 -0
  299. package/deps/capstone/include/capstone/arm.h +991 -0
  300. package/deps/capstone/include/capstone/arm64.h +3159 -0
  301. package/deps/capstone/include/capstone/bpf.h +209 -0
  302. package/deps/capstone/include/capstone/capstone.h +875 -0
  303. package/deps/capstone/include/capstone/evm.h +188 -0
  304. package/deps/capstone/include/capstone/m680x.h +537 -0
  305. package/deps/capstone/include/capstone/m68k.h +613 -0
  306. package/deps/capstone/include/capstone/mips.h +956 -0
  307. package/deps/capstone/include/capstone/mos65xx.h +204 -0
  308. package/deps/capstone/include/capstone/platform.h +122 -0
  309. package/deps/capstone/include/capstone/ppc.h +2108 -0
  310. package/deps/capstone/include/capstone/riscv.h +531 -0
  311. package/deps/capstone/include/capstone/sh.h +465 -0
  312. package/deps/capstone/include/capstone/sparc.h +520 -0
  313. package/deps/capstone/include/capstone/systemz.h +2601 -0
  314. package/deps/capstone/include/capstone/tms320c64x.h +359 -0
  315. package/deps/capstone/include/capstone/tricore.h +567 -0
  316. package/deps/capstone/include/capstone/wasm.h +250 -0
  317. package/deps/capstone/include/capstone/x86.h +1986 -0
  318. package/deps/capstone/include/capstone/xcore.h +235 -0
  319. package/deps/capstone/include/platform.h +110 -0
  320. package/deps/capstone/include/windowsce/intrin.h +12 -0
  321. package/deps/capstone/include/windowsce/stdint.h +133 -0
  322. package/deps/capstone/utils.c +140 -0
  323. package/deps/capstone/utils.h +54 -0
  324. package/index.d.ts +448 -0
  325. package/index.js +64 -0
  326. package/index.mjs +25 -0
  327. package/package.json +82 -0
  328. package/prebuilds/win32-x64/hexcore-capstone.node +0 -0
  329. package/src/capstone_wrapper.cpp +910 -0
  330. package/src/capstone_wrapper.h +147 -0
  331. package/src/disasm_async_worker.h +215 -0
  332. package/src/main.cpp +145 -0
@@ -0,0 +1,2693 @@
1
+ /* Capstone Disassembly Engine, http://www.capstone-engine.org */
2
+ /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
+ /* Rot127 <unisono@quyllur.org> 2022-2023 */
4
+ /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
5
+
6
+ /* LLVM-commit: <commit> */
7
+ /* LLVM-tag: <tag> */
8
+
9
+ /* Do not edit. */
10
+
11
+ /* Capstone's LLVM TableGen Backends: */
12
+ /* https://github.com/capstone-engine/llvm-capstone */
13
+
14
+ #ifdef GET_INSTRINFO_ENUM
15
+ #undef GET_INSTRINFO_ENUM
16
+
17
+ enum {
18
+ TRICORE_PHI = 0,
19
+ TRICORE_INLINEASM = 1,
20
+ TRICORE_INLINEASM_BR = 2,
21
+ TRICORE_CFI_INSTRUCTION = 3,
22
+ TRICORE_EH_LABEL = 4,
23
+ TRICORE_GC_LABEL = 5,
24
+ TRICORE_ANNOTATION_LABEL = 6,
25
+ TRICORE_KILL = 7,
26
+ TRICORE_EXTRACT_SUBREG = 8,
27
+ TRICORE_INSERT_SUBREG = 9,
28
+ TRICORE_IMPLICIT_DEF = 10,
29
+ TRICORE_SUBREG_TO_REG = 11,
30
+ TRICORE_COPY_TO_REGCLASS = 12,
31
+ TRICORE_DBG_VALUE = 13,
32
+ TRICORE_DBG_VALUE_LIST = 14,
33
+ TRICORE_DBG_INSTR_REF = 15,
34
+ TRICORE_DBG_PHI = 16,
35
+ TRICORE_DBG_LABEL = 17,
36
+ TRICORE_REG_SEQUENCE = 18,
37
+ TRICORE_COPY = 19,
38
+ TRICORE_BUNDLE = 20,
39
+ TRICORE_LIFETIME_START = 21,
40
+ TRICORE_LIFETIME_END = 22,
41
+ TRICORE_PSEUDO_PROBE = 23,
42
+ TRICORE_ARITH_FENCE = 24,
43
+ TRICORE_STACKMAP = 25,
44
+ TRICORE_FENTRY_CALL = 26,
45
+ TRICORE_PATCHPOINT = 27,
46
+ TRICORE_LOAD_STACK_GUARD = 28,
47
+ TRICORE_PREALLOCATED_SETUP = 29,
48
+ TRICORE_PREALLOCATED_ARG = 30,
49
+ TRICORE_STATEPOINT = 31,
50
+ TRICORE_LOCAL_ESCAPE = 32,
51
+ TRICORE_FAULTING_OP = 33,
52
+ TRICORE_PATCHABLE_OP = 34,
53
+ TRICORE_PATCHABLE_FUNCTION_ENTER = 35,
54
+ TRICORE_PATCHABLE_RET = 36,
55
+ TRICORE_PATCHABLE_FUNCTION_EXIT = 37,
56
+ TRICORE_PATCHABLE_TAIL_CALL = 38,
57
+ TRICORE_PATCHABLE_EVENT_CALL = 39,
58
+ TRICORE_PATCHABLE_TYPED_EVENT_CALL = 40,
59
+ TRICORE_ICALL_BRANCH_FUNNEL = 41,
60
+ TRICORE_MEMBARRIER = 42,
61
+ TRICORE_G_ASSERT_SEXT = 43,
62
+ TRICORE_G_ASSERT_ZEXT = 44,
63
+ TRICORE_G_ASSERT_ALIGN = 45,
64
+ TRICORE_G_ADD = 46,
65
+ TRICORE_G_SUB = 47,
66
+ TRICORE_G_MUL = 48,
67
+ TRICORE_G_SDIV = 49,
68
+ TRICORE_G_UDIV = 50,
69
+ TRICORE_G_SREM = 51,
70
+ TRICORE_G_UREM = 52,
71
+ TRICORE_G_SDIVREM = 53,
72
+ TRICORE_G_UDIVREM = 54,
73
+ TRICORE_G_AND = 55,
74
+ TRICORE_G_OR = 56,
75
+ TRICORE_G_XOR = 57,
76
+ TRICORE_G_IMPLICIT_DEF = 58,
77
+ TRICORE_G_PHI = 59,
78
+ TRICORE_G_FRAME_INDEX = 60,
79
+ TRICORE_G_GLOBAL_VALUE = 61,
80
+ TRICORE_G_EXTRACT = 62,
81
+ TRICORE_G_UNMERGE_VALUES = 63,
82
+ TRICORE_G_INSERT = 64,
83
+ TRICORE_G_MERGE_VALUES = 65,
84
+ TRICORE_G_BUILD_VECTOR = 66,
85
+ TRICORE_G_BUILD_VECTOR_TRUNC = 67,
86
+ TRICORE_G_CONCAT_VECTORS = 68,
87
+ TRICORE_G_PTRTOINT = 69,
88
+ TRICORE_G_INTTOPTR = 70,
89
+ TRICORE_G_BITCAST = 71,
90
+ TRICORE_G_FREEZE = 72,
91
+ TRICORE_G_INTRINSIC_FPTRUNC_ROUND = 73,
92
+ TRICORE_G_INTRINSIC_TRUNC = 74,
93
+ TRICORE_G_INTRINSIC_ROUND = 75,
94
+ TRICORE_G_INTRINSIC_LRINT = 76,
95
+ TRICORE_G_INTRINSIC_ROUNDEVEN = 77,
96
+ TRICORE_G_READCYCLECOUNTER = 78,
97
+ TRICORE_G_LOAD = 79,
98
+ TRICORE_G_SEXTLOAD = 80,
99
+ TRICORE_G_ZEXTLOAD = 81,
100
+ TRICORE_G_INDEXED_LOAD = 82,
101
+ TRICORE_G_INDEXED_SEXTLOAD = 83,
102
+ TRICORE_G_INDEXED_ZEXTLOAD = 84,
103
+ TRICORE_G_STORE = 85,
104
+ TRICORE_G_INDEXED_STORE = 86,
105
+ TRICORE_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87,
106
+ TRICORE_G_ATOMIC_CMPXCHG = 88,
107
+ TRICORE_G_ATOMICRMW_XCHG = 89,
108
+ TRICORE_G_ATOMICRMW_ADD = 90,
109
+ TRICORE_G_ATOMICRMW_SUB = 91,
110
+ TRICORE_G_ATOMICRMW_AND = 92,
111
+ TRICORE_G_ATOMICRMW_NAND = 93,
112
+ TRICORE_G_ATOMICRMW_OR = 94,
113
+ TRICORE_G_ATOMICRMW_XOR = 95,
114
+ TRICORE_G_ATOMICRMW_MAX = 96,
115
+ TRICORE_G_ATOMICRMW_MIN = 97,
116
+ TRICORE_G_ATOMICRMW_UMAX = 98,
117
+ TRICORE_G_ATOMICRMW_UMIN = 99,
118
+ TRICORE_G_ATOMICRMW_FADD = 100,
119
+ TRICORE_G_ATOMICRMW_FSUB = 101,
120
+ TRICORE_G_ATOMICRMW_FMAX = 102,
121
+ TRICORE_G_ATOMICRMW_FMIN = 103,
122
+ TRICORE_G_ATOMICRMW_UINC_WRAP = 104,
123
+ TRICORE_G_ATOMICRMW_UDEC_WRAP = 105,
124
+ TRICORE_G_FENCE = 106,
125
+ TRICORE_G_BRCOND = 107,
126
+ TRICORE_G_BRINDIRECT = 108,
127
+ TRICORE_G_INVOKE_REGION_START = 109,
128
+ TRICORE_G_INTRINSIC = 110,
129
+ TRICORE_G_INTRINSIC_W_SIDE_EFFECTS = 111,
130
+ TRICORE_G_ANYEXT = 112,
131
+ TRICORE_G_TRUNC = 113,
132
+ TRICORE_G_CONSTANT = 114,
133
+ TRICORE_G_FCONSTANT = 115,
134
+ TRICORE_G_VASTART = 116,
135
+ TRICORE_G_VAARG = 117,
136
+ TRICORE_G_SEXT = 118,
137
+ TRICORE_G_SEXT_INREG = 119,
138
+ TRICORE_G_ZEXT = 120,
139
+ TRICORE_G_SHL = 121,
140
+ TRICORE_G_LSHR = 122,
141
+ TRICORE_G_ASHR = 123,
142
+ TRICORE_G_FSHL = 124,
143
+ TRICORE_G_FSHR = 125,
144
+ TRICORE_G_ROTR = 126,
145
+ TRICORE_G_ROTL = 127,
146
+ TRICORE_G_ICMP = 128,
147
+ TRICORE_G_FCMP = 129,
148
+ TRICORE_G_SELECT = 130,
149
+ TRICORE_G_UADDO = 131,
150
+ TRICORE_G_UADDE = 132,
151
+ TRICORE_G_USUBO = 133,
152
+ TRICORE_G_USUBE = 134,
153
+ TRICORE_G_SADDO = 135,
154
+ TRICORE_G_SADDE = 136,
155
+ TRICORE_G_SSUBO = 137,
156
+ TRICORE_G_SSUBE = 138,
157
+ TRICORE_G_UMULO = 139,
158
+ TRICORE_G_SMULO = 140,
159
+ TRICORE_G_UMULH = 141,
160
+ TRICORE_G_SMULH = 142,
161
+ TRICORE_G_UADDSAT = 143,
162
+ TRICORE_G_SADDSAT = 144,
163
+ TRICORE_G_USUBSAT = 145,
164
+ TRICORE_G_SSUBSAT = 146,
165
+ TRICORE_G_USHLSAT = 147,
166
+ TRICORE_G_SSHLSAT = 148,
167
+ TRICORE_G_SMULFIX = 149,
168
+ TRICORE_G_UMULFIX = 150,
169
+ TRICORE_G_SMULFIXSAT = 151,
170
+ TRICORE_G_UMULFIXSAT = 152,
171
+ TRICORE_G_SDIVFIX = 153,
172
+ TRICORE_G_UDIVFIX = 154,
173
+ TRICORE_G_SDIVFIXSAT = 155,
174
+ TRICORE_G_UDIVFIXSAT = 156,
175
+ TRICORE_G_FADD = 157,
176
+ TRICORE_G_FSUB = 158,
177
+ TRICORE_G_FMUL = 159,
178
+ TRICORE_G_FMA = 160,
179
+ TRICORE_G_FMAD = 161,
180
+ TRICORE_G_FDIV = 162,
181
+ TRICORE_G_FREM = 163,
182
+ TRICORE_G_FPOW = 164,
183
+ TRICORE_G_FPOWI = 165,
184
+ TRICORE_G_FEXP = 166,
185
+ TRICORE_G_FEXP2 = 167,
186
+ TRICORE_G_FLOG = 168,
187
+ TRICORE_G_FLOG2 = 169,
188
+ TRICORE_G_FLOG10 = 170,
189
+ TRICORE_G_FNEG = 171,
190
+ TRICORE_G_FPEXT = 172,
191
+ TRICORE_G_FPTRUNC = 173,
192
+ TRICORE_G_FPTOSI = 174,
193
+ TRICORE_G_FPTOUI = 175,
194
+ TRICORE_G_SITOFP = 176,
195
+ TRICORE_G_UITOFP = 177,
196
+ TRICORE_G_FABS = 178,
197
+ TRICORE_G_FCOPYSIGN = 179,
198
+ TRICORE_G_IS_FPCLASS = 180,
199
+ TRICORE_G_FCANONICALIZE = 181,
200
+ TRICORE_G_FMINNUM = 182,
201
+ TRICORE_G_FMAXNUM = 183,
202
+ TRICORE_G_FMINNUM_IEEE = 184,
203
+ TRICORE_G_FMAXNUM_IEEE = 185,
204
+ TRICORE_G_FMINIMUM = 186,
205
+ TRICORE_G_FMAXIMUM = 187,
206
+ TRICORE_G_PTR_ADD = 188,
207
+ TRICORE_G_PTRMASK = 189,
208
+ TRICORE_G_SMIN = 190,
209
+ TRICORE_G_SMAX = 191,
210
+ TRICORE_G_UMIN = 192,
211
+ TRICORE_G_UMAX = 193,
212
+ TRICORE_G_ABS = 194,
213
+ TRICORE_G_LROUND = 195,
214
+ TRICORE_G_LLROUND = 196,
215
+ TRICORE_G_BR = 197,
216
+ TRICORE_G_BRJT = 198,
217
+ TRICORE_G_INSERT_VECTOR_ELT = 199,
218
+ TRICORE_G_EXTRACT_VECTOR_ELT = 200,
219
+ TRICORE_G_SHUFFLE_VECTOR = 201,
220
+ TRICORE_G_CTTZ = 202,
221
+ TRICORE_G_CTTZ_ZERO_UNDEF = 203,
222
+ TRICORE_G_CTLZ = 204,
223
+ TRICORE_G_CTLZ_ZERO_UNDEF = 205,
224
+ TRICORE_G_CTPOP = 206,
225
+ TRICORE_G_BSWAP = 207,
226
+ TRICORE_G_BITREVERSE = 208,
227
+ TRICORE_G_FCEIL = 209,
228
+ TRICORE_G_FCOS = 210,
229
+ TRICORE_G_FSIN = 211,
230
+ TRICORE_G_FSQRT = 212,
231
+ TRICORE_G_FFLOOR = 213,
232
+ TRICORE_G_FRINT = 214,
233
+ TRICORE_G_FNEARBYINT = 215,
234
+ TRICORE_G_ADDRSPACE_CAST = 216,
235
+ TRICORE_G_BLOCK_ADDR = 217,
236
+ TRICORE_G_JUMP_TABLE = 218,
237
+ TRICORE_G_DYN_STACKALLOC = 219,
238
+ TRICORE_G_STRICT_FADD = 220,
239
+ TRICORE_G_STRICT_FSUB = 221,
240
+ TRICORE_G_STRICT_FMUL = 222,
241
+ TRICORE_G_STRICT_FDIV = 223,
242
+ TRICORE_G_STRICT_FREM = 224,
243
+ TRICORE_G_STRICT_FMA = 225,
244
+ TRICORE_G_STRICT_FSQRT = 226,
245
+ TRICORE_G_READ_REGISTER = 227,
246
+ TRICORE_G_WRITE_REGISTER = 228,
247
+ TRICORE_G_MEMCPY = 229,
248
+ TRICORE_G_MEMCPY_INLINE = 230,
249
+ TRICORE_G_MEMMOVE = 231,
250
+ TRICORE_G_MEMSET = 232,
251
+ TRICORE_G_BZERO = 233,
252
+ TRICORE_G_VECREDUCE_SEQ_FADD = 234,
253
+ TRICORE_G_VECREDUCE_SEQ_FMUL = 235,
254
+ TRICORE_G_VECREDUCE_FADD = 236,
255
+ TRICORE_G_VECREDUCE_FMUL = 237,
256
+ TRICORE_G_VECREDUCE_FMAX = 238,
257
+ TRICORE_G_VECREDUCE_FMIN = 239,
258
+ TRICORE_G_VECREDUCE_ADD = 240,
259
+ TRICORE_G_VECREDUCE_MUL = 241,
260
+ TRICORE_G_VECREDUCE_AND = 242,
261
+ TRICORE_G_VECREDUCE_OR = 243,
262
+ TRICORE_G_VECREDUCE_XOR = 244,
263
+ TRICORE_G_VECREDUCE_SMAX = 245,
264
+ TRICORE_G_VECREDUCE_SMIN = 246,
265
+ TRICORE_G_VECREDUCE_UMAX = 247,
266
+ TRICORE_G_VECREDUCE_UMIN = 248,
267
+ TRICORE_G_SBFX = 249,
268
+ TRICORE_G_UBFX = 250,
269
+ TRICORE_ABSDIFS_B_rr_v110 = 251,
270
+ TRICORE_ABSDIFS_H_rr = 252,
271
+ TRICORE_ABSDIFS_rc = 253,
272
+ TRICORE_ABSDIFS_rr = 254,
273
+ TRICORE_ABSDIF_B_rr = 255,
274
+ TRICORE_ABSDIF_H_rr = 256,
275
+ TRICORE_ABSDIF_rc = 257,
276
+ TRICORE_ABSDIF_rr = 258,
277
+ TRICORE_ABSS_B_rr_v110 = 259,
278
+ TRICORE_ABSS_H_rr = 260,
279
+ TRICORE_ABSS_rr = 261,
280
+ TRICORE_ABS_B_rr = 262,
281
+ TRICORE_ABS_H_rr = 263,
282
+ TRICORE_ABS_rr = 264,
283
+ TRICORE_ADDC_rc = 265,
284
+ TRICORE_ADDC_rr = 266,
285
+ TRICORE_ADDIH_A_rlc = 267,
286
+ TRICORE_ADDIH_rlc = 268,
287
+ TRICORE_ADDI_rlc = 269,
288
+ TRICORE_ADDSC_AT_rr = 270,
289
+ TRICORE_ADDSC_AT_rr_v110 = 271,
290
+ TRICORE_ADDSC_A_rr = 272,
291
+ TRICORE_ADDSC_A_rr_v110 = 273,
292
+ TRICORE_ADDSC_A_srrs = 274,
293
+ TRICORE_ADDSC_A_srrs_v110 = 275,
294
+ TRICORE_ADDS_BU_rr_v110 = 276,
295
+ TRICORE_ADDS_B_rr = 277,
296
+ TRICORE_ADDS_H = 278,
297
+ TRICORE_ADDS_HU = 279,
298
+ TRICORE_ADDS_U = 280,
299
+ TRICORE_ADDS_U_rc = 281,
300
+ TRICORE_ADDS_rc = 282,
301
+ TRICORE_ADDS_rr = 283,
302
+ TRICORE_ADDS_srr = 284,
303
+ TRICORE_ADDX_rc = 285,
304
+ TRICORE_ADDX_rr = 286,
305
+ TRICORE_ADD_A_rr = 287,
306
+ TRICORE_ADD_A_src = 288,
307
+ TRICORE_ADD_A_srr = 289,
308
+ TRICORE_ADD_B_rr = 290,
309
+ TRICORE_ADD_F_rrr = 291,
310
+ TRICORE_ADD_H_rr = 292,
311
+ TRICORE_ADD_rc = 293,
312
+ TRICORE_ADD_rr = 294,
313
+ TRICORE_ADD_src = 295,
314
+ TRICORE_ADD_src_15a = 296,
315
+ TRICORE_ADD_src_a15 = 297,
316
+ TRICORE_ADD_srr = 298,
317
+ TRICORE_ADD_srr_15a = 299,
318
+ TRICORE_ADD_srr_a15 = 300,
319
+ TRICORE_ANDN_T = 301,
320
+ TRICORE_ANDN_rc = 302,
321
+ TRICORE_ANDN_rr = 303,
322
+ TRICORE_AND_ANDN_T = 304,
323
+ TRICORE_AND_AND_T = 305,
324
+ TRICORE_AND_EQ_rc = 306,
325
+ TRICORE_AND_EQ_rr = 307,
326
+ TRICORE_AND_GE_U_rc = 308,
327
+ TRICORE_AND_GE_U_rr = 309,
328
+ TRICORE_AND_GE_rc = 310,
329
+ TRICORE_AND_GE_rr = 311,
330
+ TRICORE_AND_LT_U_rc = 312,
331
+ TRICORE_AND_LT_U_rr = 313,
332
+ TRICORE_AND_LT_rc = 314,
333
+ TRICORE_AND_LT_rr = 315,
334
+ TRICORE_AND_NE_rc = 316,
335
+ TRICORE_AND_NE_rr = 317,
336
+ TRICORE_AND_NOR_T = 318,
337
+ TRICORE_AND_OR_T = 319,
338
+ TRICORE_AND_T = 320,
339
+ TRICORE_AND_rc = 321,
340
+ TRICORE_AND_rr = 322,
341
+ TRICORE_AND_sc = 323,
342
+ TRICORE_AND_sc_v110 = 324,
343
+ TRICORE_AND_srr = 325,
344
+ TRICORE_AND_srr_v110 = 326,
345
+ TRICORE_BISR_rc = 327,
346
+ TRICORE_BISR_rc_v161 = 328,
347
+ TRICORE_BISR_sc = 329,
348
+ TRICORE_BISR_sc_v110 = 330,
349
+ TRICORE_BMERGAE_rr_v110 = 331,
350
+ TRICORE_BMERGE_rr = 332,
351
+ TRICORE_BSPLIT_rr = 333,
352
+ TRICORE_BSPLIT_rr_v110 = 334,
353
+ TRICORE_CACHEA_I_bo_bso = 335,
354
+ TRICORE_CACHEA_I_bo_c = 336,
355
+ TRICORE_CACHEA_I_bo_pos = 337,
356
+ TRICORE_CACHEA_I_bo_pre = 338,
357
+ TRICORE_CACHEA_I_bo_r = 339,
358
+ TRICORE_CACHEA_WI_bo_bso = 340,
359
+ TRICORE_CACHEA_WI_bo_c = 341,
360
+ TRICORE_CACHEA_WI_bo_pos = 342,
361
+ TRICORE_CACHEA_WI_bo_pre = 343,
362
+ TRICORE_CACHEA_WI_bo_r = 344,
363
+ TRICORE_CACHEA_W_bo_bso = 345,
364
+ TRICORE_CACHEA_W_bo_c = 346,
365
+ TRICORE_CACHEA_W_bo_pos = 347,
366
+ TRICORE_CACHEA_W_bo_pre = 348,
367
+ TRICORE_CACHEA_W_bo_r = 349,
368
+ TRICORE_CACHEI_I_bo_bso = 350,
369
+ TRICORE_CACHEI_I_bo_pos = 351,
370
+ TRICORE_CACHEI_I_bo_pre = 352,
371
+ TRICORE_CACHEI_WI_bo_bso = 353,
372
+ TRICORE_CACHEI_WI_bo_pos = 354,
373
+ TRICORE_CACHEI_WI_bo_pre = 355,
374
+ TRICORE_CACHEI_W_bo_bso = 356,
375
+ TRICORE_CACHEI_W_bo_pos = 357,
376
+ TRICORE_CACHEI_W_bo_pre = 358,
377
+ TRICORE_CADDN_A_rcr_v110 = 359,
378
+ TRICORE_CADDN_A_rrr_v110 = 360,
379
+ TRICORE_CADDN_rcr = 361,
380
+ TRICORE_CADDN_rrr = 362,
381
+ TRICORE_CADDN_src = 363,
382
+ TRICORE_CADDN_srr_v110 = 364,
383
+ TRICORE_CADD_A_rcr_v110 = 365,
384
+ TRICORE_CADD_A_rrr_v110 = 366,
385
+ TRICORE_CADD_rcr = 367,
386
+ TRICORE_CADD_rrr = 368,
387
+ TRICORE_CADD_src = 369,
388
+ TRICORE_CADD_srr_v110 = 370,
389
+ TRICORE_CALLA_b = 371,
390
+ TRICORE_CALLI_rr = 372,
391
+ TRICORE_CALLI_rr_v110 = 373,
392
+ TRICORE_CALL_b = 374,
393
+ TRICORE_CALL_sb = 375,
394
+ TRICORE_CLO_B_rr_v110 = 376,
395
+ TRICORE_CLO_H_rr = 377,
396
+ TRICORE_CLO_rr = 378,
397
+ TRICORE_CLS_B_rr_v110 = 379,
398
+ TRICORE_CLS_H_rr = 380,
399
+ TRICORE_CLS_rr = 381,
400
+ TRICORE_CLZ_B_rr_v110 = 382,
401
+ TRICORE_CLZ_H_rr = 383,
402
+ TRICORE_CLZ_rr = 384,
403
+ TRICORE_CMOVN_src = 385,
404
+ TRICORE_CMOVN_srr = 386,
405
+ TRICORE_CMOV_src = 387,
406
+ TRICORE_CMOV_srr = 388,
407
+ TRICORE_CMPSWAP_W_bo_bso = 389,
408
+ TRICORE_CMPSWAP_W_bo_c = 390,
409
+ TRICORE_CMPSWAP_W_bo_pos = 391,
410
+ TRICORE_CMPSWAP_W_bo_pre = 392,
411
+ TRICORE_CMPSWAP_W_bo_r = 393,
412
+ TRICORE_CMP_F_rr = 394,
413
+ TRICORE_CRC32B_W_rr = 395,
414
+ TRICORE_CRC32L_W_rr = 396,
415
+ TRICORE_CRC32_B_rr = 397,
416
+ TRICORE_CRCN_rrr = 398,
417
+ TRICORE_CSUBN_A__rrr_v110 = 399,
418
+ TRICORE_CSUBN_rrr = 400,
419
+ TRICORE_CSUB_A__rrr_v110 = 401,
420
+ TRICORE_CSUB_rrr = 402,
421
+ TRICORE_DEBUG_sr = 403,
422
+ TRICORE_DEBUG_sys = 404,
423
+ TRICORE_DEXTR_rrpw = 405,
424
+ TRICORE_DEXTR_rrrr = 406,
425
+ TRICORE_DIFSC_A_rr_v110 = 407,
426
+ TRICORE_DISABLE_sys = 408,
427
+ TRICORE_DISABLE_sys_1 = 409,
428
+ TRICORE_DIV_F_rr = 410,
429
+ TRICORE_DIV_U_rr = 411,
430
+ TRICORE_DIV_rr = 412,
431
+ TRICORE_DSYNC_sys = 413,
432
+ TRICORE_DVADJ_rrr = 414,
433
+ TRICORE_DVADJ_rrr_v110 = 415,
434
+ TRICORE_DVADJ_srr_v110 = 416,
435
+ TRICORE_DVINIT_BU_rr = 417,
436
+ TRICORE_DVINIT_BU_rr_v110 = 418,
437
+ TRICORE_DVINIT_B_rr = 419,
438
+ TRICORE_DVINIT_B_rr_v110 = 420,
439
+ TRICORE_DVINIT_HU_rr = 421,
440
+ TRICORE_DVINIT_HU_rr_v110 = 422,
441
+ TRICORE_DVINIT_H_rr = 423,
442
+ TRICORE_DVINIT_H_rr_v110 = 424,
443
+ TRICORE_DVINIT_U_rr = 425,
444
+ TRICORE_DVINIT_U_rr_v110 = 426,
445
+ TRICORE_DVINIT_rr = 427,
446
+ TRICORE_DVINIT_rr_v110 = 428,
447
+ TRICORE_DVSTEP_U_rrr = 429,
448
+ TRICORE_DVSTEP_U_rrrv110 = 430,
449
+ TRICORE_DVSTEP_Uv110 = 431,
450
+ TRICORE_DVSTEP_rrr = 432,
451
+ TRICORE_DVSTEP_rrrv110 = 433,
452
+ TRICORE_DVSTEPv110 = 434,
453
+ TRICORE_ENABLE_sys = 435,
454
+ TRICORE_EQANY_B_rc = 436,
455
+ TRICORE_EQANY_B_rr = 437,
456
+ TRICORE_EQANY_H_rc = 438,
457
+ TRICORE_EQANY_H_rr = 439,
458
+ TRICORE_EQZ_A_rr = 440,
459
+ TRICORE_EQ_A_rr = 441,
460
+ TRICORE_EQ_B_rr = 442,
461
+ TRICORE_EQ_H_rr = 443,
462
+ TRICORE_EQ_W_rr = 444,
463
+ TRICORE_EQ_rc = 445,
464
+ TRICORE_EQ_rr = 446,
465
+ TRICORE_EQ_src = 447,
466
+ TRICORE_EQ_srr = 448,
467
+ TRICORE_EXTR_U_rrpw = 449,
468
+ TRICORE_EXTR_U_rrrr = 450,
469
+ TRICORE_EXTR_U_rrrw = 451,
470
+ TRICORE_EXTR_rrpw = 452,
471
+ TRICORE_EXTR_rrrr = 453,
472
+ TRICORE_EXTR_rrrw = 454,
473
+ TRICORE_FCALLA_b = 455,
474
+ TRICORE_FCALLA_i = 456,
475
+ TRICORE_FCALL_b = 457,
476
+ TRICORE_FRET_sr = 458,
477
+ TRICORE_FRET_sys = 459,
478
+ TRICORE_FTOHP_rr = 460,
479
+ TRICORE_FTOIZ_rr = 461,
480
+ TRICORE_FTOI_rr = 462,
481
+ TRICORE_FTOQ31Z_rr = 463,
482
+ TRICORE_FTOQ31_rr = 464,
483
+ TRICORE_FTOUZ_rr = 465,
484
+ TRICORE_FTOU_rr = 466,
485
+ TRICORE_GE_A_rr = 467,
486
+ TRICORE_GE_U_rc = 468,
487
+ TRICORE_GE_U_rr = 469,
488
+ TRICORE_GE_rc = 470,
489
+ TRICORE_GE_rr = 471,
490
+ TRICORE_HPTOF_rr = 472,
491
+ TRICORE_IMASK_rcpw = 473,
492
+ TRICORE_IMASK_rcrw = 474,
493
+ TRICORE_IMASK_rrpw = 475,
494
+ TRICORE_IMASK_rrrw = 476,
495
+ TRICORE_INSERT_rcpw = 477,
496
+ TRICORE_INSERT_rcrr = 478,
497
+ TRICORE_INSERT_rcrw = 479,
498
+ TRICORE_INSERT_rrpw = 480,
499
+ TRICORE_INSERT_rrrr = 481,
500
+ TRICORE_INSERT_rrrw = 482,
501
+ TRICORE_INSN_T = 483,
502
+ TRICORE_INS_T = 484,
503
+ TRICORE_ISYNC_sys = 485,
504
+ TRICORE_ITOF_rr = 486,
505
+ TRICORE_IXMAX_U_rrr = 487,
506
+ TRICORE_IXMAX_rrr = 488,
507
+ TRICORE_IXMIN_U_rrr = 489,
508
+ TRICORE_IXMIN_rrr = 490,
509
+ TRICORE_JA_b = 491,
510
+ TRICORE_JEQ_A_brr = 492,
511
+ TRICORE_JEQ_brc = 493,
512
+ TRICORE_JEQ_brr = 494,
513
+ TRICORE_JEQ_sbc1 = 495,
514
+ TRICORE_JEQ_sbc2 = 496,
515
+ TRICORE_JEQ_sbc_v110 = 497,
516
+ TRICORE_JEQ_sbr1 = 498,
517
+ TRICORE_JEQ_sbr2 = 499,
518
+ TRICORE_JEQ_sbr_v110 = 500,
519
+ TRICORE_JGEZ_sbr = 501,
520
+ TRICORE_JGEZ_sbr_v110 = 502,
521
+ TRICORE_JGE_U_brc = 503,
522
+ TRICORE_JGE_U_brr = 504,
523
+ TRICORE_JGE_brc = 505,
524
+ TRICORE_JGE_brr = 506,
525
+ TRICORE_JGTZ_sbr = 507,
526
+ TRICORE_JGTZ_sbr_v110 = 508,
527
+ TRICORE_JI_rr = 509,
528
+ TRICORE_JI_rr_v110 = 510,
529
+ TRICORE_JI_sbr_v110 = 511,
530
+ TRICORE_JI_sr = 512,
531
+ TRICORE_JLA_b = 513,
532
+ TRICORE_JLEZ_sbr = 514,
533
+ TRICORE_JLEZ_sbr_v110 = 515,
534
+ TRICORE_JLI_rr = 516,
535
+ TRICORE_JLI_rr_v110 = 517,
536
+ TRICORE_JLTZ_sbr = 518,
537
+ TRICORE_JLTZ_sbr_v110 = 519,
538
+ TRICORE_JLT_U_brc = 520,
539
+ TRICORE_JLT_U_brr = 521,
540
+ TRICORE_JLT_brc = 522,
541
+ TRICORE_JLT_brr = 523,
542
+ TRICORE_JL_b = 524,
543
+ TRICORE_JNED_brc = 525,
544
+ TRICORE_JNED_brr = 526,
545
+ TRICORE_JNEI_brc = 527,
546
+ TRICORE_JNEI_brr = 528,
547
+ TRICORE_JNE_A_brr = 529,
548
+ TRICORE_JNE_brc = 530,
549
+ TRICORE_JNE_brr = 531,
550
+ TRICORE_JNE_sbc1 = 532,
551
+ TRICORE_JNE_sbc2 = 533,
552
+ TRICORE_JNE_sbc_v110 = 534,
553
+ TRICORE_JNE_sbr1 = 535,
554
+ TRICORE_JNE_sbr2 = 536,
555
+ TRICORE_JNE_sbr_v110 = 537,
556
+ TRICORE_JNZ_A_brr = 538,
557
+ TRICORE_JNZ_A_sbr = 539,
558
+ TRICORE_JNZ_T_brn = 540,
559
+ TRICORE_JNZ_T_sbrn = 541,
560
+ TRICORE_JNZ_T_sbrn_v110 = 542,
561
+ TRICORE_JNZ_sb = 543,
562
+ TRICORE_JNZ_sb_v110 = 544,
563
+ TRICORE_JNZ_sbr = 545,
564
+ TRICORE_JNZ_sbr_v110 = 546,
565
+ TRICORE_JZ_A_brr = 547,
566
+ TRICORE_JZ_A_sbr = 548,
567
+ TRICORE_JZ_T_brn = 549,
568
+ TRICORE_JZ_T_sbrn = 550,
569
+ TRICORE_JZ_T_sbrn_v110 = 551,
570
+ TRICORE_JZ_sb = 552,
571
+ TRICORE_JZ_sb_v110 = 553,
572
+ TRICORE_JZ_sbr = 554,
573
+ TRICORE_JZ_sbr_v110 = 555,
574
+ TRICORE_J_b = 556,
575
+ TRICORE_J_sb = 557,
576
+ TRICORE_J_sb_v110 = 558,
577
+ TRICORE_LDLCX_abs = 559,
578
+ TRICORE_LDLCX_bo_bso = 560,
579
+ TRICORE_LDMST_abs = 561,
580
+ TRICORE_LDMST_bo_bso = 562,
581
+ TRICORE_LDMST_bo_c = 563,
582
+ TRICORE_LDMST_bo_pos = 564,
583
+ TRICORE_LDMST_bo_pre = 565,
584
+ TRICORE_LDMST_bo_r = 566,
585
+ TRICORE_LDUCX_abs = 567,
586
+ TRICORE_LDUCX_bo_bso = 568,
587
+ TRICORE_LD_A_abs = 569,
588
+ TRICORE_LD_A_bo_bso = 570,
589
+ TRICORE_LD_A_bo_c = 571,
590
+ TRICORE_LD_A_bo_pos = 572,
591
+ TRICORE_LD_A_bo_pre = 573,
592
+ TRICORE_LD_A_bo_r = 574,
593
+ TRICORE_LD_A_bol = 575,
594
+ TRICORE_LD_A_sc = 576,
595
+ TRICORE_LD_A_slr = 577,
596
+ TRICORE_LD_A_slr_post = 578,
597
+ TRICORE_LD_A_slr_post_v110 = 579,
598
+ TRICORE_LD_A_slr_v110 = 580,
599
+ TRICORE_LD_A_slro = 581,
600
+ TRICORE_LD_A_slro_v110 = 582,
601
+ TRICORE_LD_A_sro = 583,
602
+ TRICORE_LD_A_sro_v110 = 584,
603
+ TRICORE_LD_BU_abs = 585,
604
+ TRICORE_LD_BU_bo_bso = 586,
605
+ TRICORE_LD_BU_bo_c = 587,
606
+ TRICORE_LD_BU_bo_pos = 588,
607
+ TRICORE_LD_BU_bo_pre = 589,
608
+ TRICORE_LD_BU_bo_r = 590,
609
+ TRICORE_LD_BU_bol = 591,
610
+ TRICORE_LD_BU_slr = 592,
611
+ TRICORE_LD_BU_slr_post = 593,
612
+ TRICORE_LD_BU_slr_post_v110 = 594,
613
+ TRICORE_LD_BU_slr_v110 = 595,
614
+ TRICORE_LD_BU_slro = 596,
615
+ TRICORE_LD_BU_slro_v110 = 597,
616
+ TRICORE_LD_BU_sro = 598,
617
+ TRICORE_LD_BU_sro_v110 = 599,
618
+ TRICORE_LD_B_abs = 600,
619
+ TRICORE_LD_B_bo_bso = 601,
620
+ TRICORE_LD_B_bo_c = 602,
621
+ TRICORE_LD_B_bo_pos = 603,
622
+ TRICORE_LD_B_bo_pre = 604,
623
+ TRICORE_LD_B_bo_r = 605,
624
+ TRICORE_LD_B_bol = 606,
625
+ TRICORE_LD_B_slr_post_v110 = 607,
626
+ TRICORE_LD_B_slr_v110 = 608,
627
+ TRICORE_LD_B_slro_v110 = 609,
628
+ TRICORE_LD_B_sro_v110 = 610,
629
+ TRICORE_LD_DA_abs = 611,
630
+ TRICORE_LD_DA_bo_bso = 612,
631
+ TRICORE_LD_DA_bo_c = 613,
632
+ TRICORE_LD_DA_bo_pos = 614,
633
+ TRICORE_LD_DA_bo_pre = 615,
634
+ TRICORE_LD_DA_bo_r = 616,
635
+ TRICORE_LD_D_abs = 617,
636
+ TRICORE_LD_D_bo_bso = 618,
637
+ TRICORE_LD_D_bo_c = 619,
638
+ TRICORE_LD_D_bo_pos = 620,
639
+ TRICORE_LD_D_bo_pre = 621,
640
+ TRICORE_LD_D_bo_r = 622,
641
+ TRICORE_LD_HU_abs = 623,
642
+ TRICORE_LD_HU_bo_bso = 624,
643
+ TRICORE_LD_HU_bo_c = 625,
644
+ TRICORE_LD_HU_bo_pos = 626,
645
+ TRICORE_LD_HU_bo_pre = 627,
646
+ TRICORE_LD_HU_bo_r = 628,
647
+ TRICORE_LD_HU_bol = 629,
648
+ TRICORE_LD_H_abs = 630,
649
+ TRICORE_LD_H_bo_bso = 631,
650
+ TRICORE_LD_H_bo_c = 632,
651
+ TRICORE_LD_H_bo_pos = 633,
652
+ TRICORE_LD_H_bo_pre = 634,
653
+ TRICORE_LD_H_bo_r = 635,
654
+ TRICORE_LD_H_bol = 636,
655
+ TRICORE_LD_H_slr = 637,
656
+ TRICORE_LD_H_slr_post = 638,
657
+ TRICORE_LD_H_slr_post_v110 = 639,
658
+ TRICORE_LD_H_slr_v110 = 640,
659
+ TRICORE_LD_H_slro = 641,
660
+ TRICORE_LD_H_slro_v110 = 642,
661
+ TRICORE_LD_H_sro = 643,
662
+ TRICORE_LD_H_sro_v110 = 644,
663
+ TRICORE_LD_Q_abs = 645,
664
+ TRICORE_LD_Q_bo_bso = 646,
665
+ TRICORE_LD_Q_bo_c = 647,
666
+ TRICORE_LD_Q_bo_pos = 648,
667
+ TRICORE_LD_Q_bo_pre = 649,
668
+ TRICORE_LD_Q_bo_r = 650,
669
+ TRICORE_LD_W_abs = 651,
670
+ TRICORE_LD_W_bo_bso = 652,
671
+ TRICORE_LD_W_bo_c = 653,
672
+ TRICORE_LD_W_bo_pos = 654,
673
+ TRICORE_LD_W_bo_pre = 655,
674
+ TRICORE_LD_W_bo_r = 656,
675
+ TRICORE_LD_W_bol = 657,
676
+ TRICORE_LD_W_sc = 658,
677
+ TRICORE_LD_W_slr = 659,
678
+ TRICORE_LD_W_slr_post = 660,
679
+ TRICORE_LD_W_slr_post_v110 = 661,
680
+ TRICORE_LD_W_slr_v110 = 662,
681
+ TRICORE_LD_W_slro = 663,
682
+ TRICORE_LD_W_slro_v110 = 664,
683
+ TRICORE_LD_W_sro = 665,
684
+ TRICORE_LD_W_sro_v110 = 666,
685
+ TRICORE_LEA_abs = 667,
686
+ TRICORE_LEA_bo_bso = 668,
687
+ TRICORE_LEA_bol = 669,
688
+ TRICORE_LHA_abs = 670,
689
+ TRICORE_LOOPU_brr = 671,
690
+ TRICORE_LOOP_brr = 672,
691
+ TRICORE_LOOP_sbr = 673,
692
+ TRICORE_LT_A_rr = 674,
693
+ TRICORE_LT_B = 675,
694
+ TRICORE_LT_BU = 676,
695
+ TRICORE_LT_H = 677,
696
+ TRICORE_LT_HU = 678,
697
+ TRICORE_LT_U_rc = 679,
698
+ TRICORE_LT_U_rr = 680,
699
+ TRICORE_LT_U_srcv110 = 681,
700
+ TRICORE_LT_U_srrv110 = 682,
701
+ TRICORE_LT_W = 683,
702
+ TRICORE_LT_WU = 684,
703
+ TRICORE_LT_rc = 685,
704
+ TRICORE_LT_rr = 686,
705
+ TRICORE_LT_src = 687,
706
+ TRICORE_LT_srr = 688,
707
+ TRICORE_MADDMS_H_rrr1_LL = 689,
708
+ TRICORE_MADDMS_H_rrr1_LU = 690,
709
+ TRICORE_MADDMS_H_rrr1_UL = 691,
710
+ TRICORE_MADDMS_H_rrr1_UU = 692,
711
+ TRICORE_MADDMS_U_rcr_v110 = 693,
712
+ TRICORE_MADDMS_U_rrr2_v110 = 694,
713
+ TRICORE_MADDMS_rcr_v110 = 695,
714
+ TRICORE_MADDMS_rrr2_v110 = 696,
715
+ TRICORE_MADDM_H_rrr1_LL = 697,
716
+ TRICORE_MADDM_H_rrr1_LU = 698,
717
+ TRICORE_MADDM_H_rrr1_UL = 699,
718
+ TRICORE_MADDM_H_rrr1_UU = 700,
719
+ TRICORE_MADDM_H_rrr1_v110 = 701,
720
+ TRICORE_MADDM_Q_rrr1_v110 = 702,
721
+ TRICORE_MADDM_U_rcr_v110 = 703,
722
+ TRICORE_MADDM_U_rrr2_v110 = 704,
723
+ TRICORE_MADDM_rcr_v110 = 705,
724
+ TRICORE_MADDM_rrr2_v110 = 706,
725
+ TRICORE_MADDRS_H_rrr1_LL = 707,
726
+ TRICORE_MADDRS_H_rrr1_LU = 708,
727
+ TRICORE_MADDRS_H_rrr1_UL = 709,
728
+ TRICORE_MADDRS_H_rrr1_UL_2 = 710,
729
+ TRICORE_MADDRS_H_rrr1_UU = 711,
730
+ TRICORE_MADDRS_H_rrr1_v110 = 712,
731
+ TRICORE_MADDRS_Q_rrr1_L_L = 713,
732
+ TRICORE_MADDRS_Q_rrr1_U_U = 714,
733
+ TRICORE_MADDRS_Q_rrr1_v110 = 715,
734
+ TRICORE_MADDR_H_rrr1_LL = 716,
735
+ TRICORE_MADDR_H_rrr1_LU = 717,
736
+ TRICORE_MADDR_H_rrr1_UL = 718,
737
+ TRICORE_MADDR_H_rrr1_UL_2 = 719,
738
+ TRICORE_MADDR_H_rrr1_UU = 720,
739
+ TRICORE_MADDR_H_rrr1_v110 = 721,
740
+ TRICORE_MADDR_Q_rrr1_L_L = 722,
741
+ TRICORE_MADDR_Q_rrr1_U_U = 723,
742
+ TRICORE_MADDR_Q_rrr1_v110 = 724,
743
+ TRICORE_MADDSUMS_H_rrr1_LL = 725,
744
+ TRICORE_MADDSUMS_H_rrr1_LU = 726,
745
+ TRICORE_MADDSUMS_H_rrr1_UL = 727,
746
+ TRICORE_MADDSUMS_H_rrr1_UU = 728,
747
+ TRICORE_MADDSUM_H_rrr1_LL = 729,
748
+ TRICORE_MADDSUM_H_rrr1_LU = 730,
749
+ TRICORE_MADDSUM_H_rrr1_UL = 731,
750
+ TRICORE_MADDSUM_H_rrr1_UU = 732,
751
+ TRICORE_MADDSURS_H_rrr1_LL = 733,
752
+ TRICORE_MADDSURS_H_rrr1_LU = 734,
753
+ TRICORE_MADDSURS_H_rrr1_UL = 735,
754
+ TRICORE_MADDSURS_H_rrr1_UU = 736,
755
+ TRICORE_MADDSUR_H_rrr1_LL = 737,
756
+ TRICORE_MADDSUR_H_rrr1_LU = 738,
757
+ TRICORE_MADDSUR_H_rrr1_UL = 739,
758
+ TRICORE_MADDSUR_H_rrr1_UU = 740,
759
+ TRICORE_MADDSUS_H_rrr1_LL = 741,
760
+ TRICORE_MADDSUS_H_rrr1_LU = 742,
761
+ TRICORE_MADDSUS_H_rrr1_UL = 743,
762
+ TRICORE_MADDSUS_H_rrr1_UU = 744,
763
+ TRICORE_MADDSU_H_rrr1_LL = 745,
764
+ TRICORE_MADDSU_H_rrr1_LU = 746,
765
+ TRICORE_MADDSU_H_rrr1_UL = 747,
766
+ TRICORE_MADDSU_H_rrr1_UU = 748,
767
+ TRICORE_MADDS_H_rrr1_LL = 749,
768
+ TRICORE_MADDS_H_rrr1_LU = 750,
769
+ TRICORE_MADDS_H_rrr1_UL = 751,
770
+ TRICORE_MADDS_H_rrr1_UU = 752,
771
+ TRICORE_MADDS_H_rrr1_v110 = 753,
772
+ TRICORE_MADDS_Q_rrr1 = 754,
773
+ TRICORE_MADDS_Q_rrr1_L = 755,
774
+ TRICORE_MADDS_Q_rrr1_L_L = 756,
775
+ TRICORE_MADDS_Q_rrr1_U = 757,
776
+ TRICORE_MADDS_Q_rrr1_UU2_v110 = 758,
777
+ TRICORE_MADDS_Q_rrr1_U_U = 759,
778
+ TRICORE_MADDS_Q_rrr1_e = 760,
779
+ TRICORE_MADDS_Q_rrr1_e_L = 761,
780
+ TRICORE_MADDS_Q_rrr1_e_L_L = 762,
781
+ TRICORE_MADDS_Q_rrr1_e_U = 763,
782
+ TRICORE_MADDS_Q_rrr1_e_U_U = 764,
783
+ TRICORE_MADDS_U_rcr = 765,
784
+ TRICORE_MADDS_U_rcr_e = 766,
785
+ TRICORE_MADDS_U_rrr2 = 767,
786
+ TRICORE_MADDS_U_rrr2_e = 768,
787
+ TRICORE_MADDS_rcr = 769,
788
+ TRICORE_MADDS_rcr_e = 770,
789
+ TRICORE_MADDS_rrr2 = 771,
790
+ TRICORE_MADDS_rrr2_e = 772,
791
+ TRICORE_MADD_F_rrr = 773,
792
+ TRICORE_MADD_H_rrr1_LL = 774,
793
+ TRICORE_MADD_H_rrr1_LU = 775,
794
+ TRICORE_MADD_H_rrr1_UL = 776,
795
+ TRICORE_MADD_H_rrr1_UU = 777,
796
+ TRICORE_MADD_H_rrr1_v110 = 778,
797
+ TRICORE_MADD_Q_rrr1 = 779,
798
+ TRICORE_MADD_Q_rrr1_L = 780,
799
+ TRICORE_MADD_Q_rrr1_L_L = 781,
800
+ TRICORE_MADD_Q_rrr1_U = 782,
801
+ TRICORE_MADD_Q_rrr1_UU2_v110 = 783,
802
+ TRICORE_MADD_Q_rrr1_U_U = 784,
803
+ TRICORE_MADD_Q_rrr1_e = 785,
804
+ TRICORE_MADD_Q_rrr1_e_L = 786,
805
+ TRICORE_MADD_Q_rrr1_e_L_L = 787,
806
+ TRICORE_MADD_Q_rrr1_e_U = 788,
807
+ TRICORE_MADD_Q_rrr1_e_U_U = 789,
808
+ TRICORE_MADD_U_rcr = 790,
809
+ TRICORE_MADD_U_rrr2 = 791,
810
+ TRICORE_MADD_rcr = 792,
811
+ TRICORE_MADD_rcr_e = 793,
812
+ TRICORE_MADD_rrr2 = 794,
813
+ TRICORE_MADD_rrr2_e = 795,
814
+ TRICORE_MAX_B = 796,
815
+ TRICORE_MAX_BU = 797,
816
+ TRICORE_MAX_H = 798,
817
+ TRICORE_MAX_HU = 799,
818
+ TRICORE_MAX_U_rc = 800,
819
+ TRICORE_MAX_U_rr = 801,
820
+ TRICORE_MAX_rc = 802,
821
+ TRICORE_MAX_rr = 803,
822
+ TRICORE_MFCR_rlc = 804,
823
+ TRICORE_MIN_B = 805,
824
+ TRICORE_MIN_BU = 806,
825
+ TRICORE_MIN_H = 807,
826
+ TRICORE_MIN_HU = 808,
827
+ TRICORE_MIN_U_rc = 809,
828
+ TRICORE_MIN_U_rr = 810,
829
+ TRICORE_MIN_rc = 811,
830
+ TRICORE_MIN_rr = 812,
831
+ TRICORE_MOVH_A_rlc = 813,
832
+ TRICORE_MOVH_rlc = 814,
833
+ TRICORE_MOVZ_A_sr = 815,
834
+ TRICORE_MOV_AA_rr = 816,
835
+ TRICORE_MOV_AA_srr_srr = 817,
836
+ TRICORE_MOV_AA_srr_srr_v110 = 818,
837
+ TRICORE_MOV_A_rr = 819,
838
+ TRICORE_MOV_A_src = 820,
839
+ TRICORE_MOV_A_srr = 821,
840
+ TRICORE_MOV_A_srr_v110 = 822,
841
+ TRICORE_MOV_D_rr = 823,
842
+ TRICORE_MOV_D_srr_srr = 824,
843
+ TRICORE_MOV_D_srr_srr_v110 = 825,
844
+ TRICORE_MOV_U_rlc = 826,
845
+ TRICORE_MOV_rlc = 827,
846
+ TRICORE_MOV_rlc_e = 828,
847
+ TRICORE_MOV_rr = 829,
848
+ TRICORE_MOV_rr_e = 830,
849
+ TRICORE_MOV_rr_eab = 831,
850
+ TRICORE_MOV_sc = 832,
851
+ TRICORE_MOV_sc_v110 = 833,
852
+ TRICORE_MOV_src = 834,
853
+ TRICORE_MOV_src_e = 835,
854
+ TRICORE_MOV_srr = 836,
855
+ TRICORE_MSUBADMS_H_rrr1_LL = 837,
856
+ TRICORE_MSUBADMS_H_rrr1_LU = 838,
857
+ TRICORE_MSUBADMS_H_rrr1_UL = 839,
858
+ TRICORE_MSUBADMS_H_rrr1_UU = 840,
859
+ TRICORE_MSUBADM_H_rrr1_LL = 841,
860
+ TRICORE_MSUBADM_H_rrr1_LU = 842,
861
+ TRICORE_MSUBADM_H_rrr1_UL = 843,
862
+ TRICORE_MSUBADM_H_rrr1_UU = 844,
863
+ TRICORE_MSUBADRS_H_rrr1_LL = 845,
864
+ TRICORE_MSUBADRS_H_rrr1_LU = 846,
865
+ TRICORE_MSUBADRS_H_rrr1_UL = 847,
866
+ TRICORE_MSUBADRS_H_rrr1_UU = 848,
867
+ TRICORE_MSUBADRS_H_rrr1_v110 = 849,
868
+ TRICORE_MSUBADR_H_rrr1_LL = 850,
869
+ TRICORE_MSUBADR_H_rrr1_LU = 851,
870
+ TRICORE_MSUBADR_H_rrr1_UL = 852,
871
+ TRICORE_MSUBADR_H_rrr1_UU = 853,
872
+ TRICORE_MSUBADR_H_rrr1_v110 = 854,
873
+ TRICORE_MSUBADS_H_rrr1_LL = 855,
874
+ TRICORE_MSUBADS_H_rrr1_LU = 856,
875
+ TRICORE_MSUBADS_H_rrr1_UL = 857,
876
+ TRICORE_MSUBADS_H_rrr1_UU = 858,
877
+ TRICORE_MSUBAD_H_rrr1_LL = 859,
878
+ TRICORE_MSUBAD_H_rrr1_LU = 860,
879
+ TRICORE_MSUBAD_H_rrr1_UL = 861,
880
+ TRICORE_MSUBAD_H_rrr1_UU = 862,
881
+ TRICORE_MSUBMS_H_rrr1_LL = 863,
882
+ TRICORE_MSUBMS_H_rrr1_LU = 864,
883
+ TRICORE_MSUBMS_H_rrr1_UL = 865,
884
+ TRICORE_MSUBMS_H_rrr1_UU = 866,
885
+ TRICORE_MSUBMS_U_rcrv110 = 867,
886
+ TRICORE_MSUBMS_U_rrr2v110 = 868,
887
+ TRICORE_MSUBMS_rcrv110 = 869,
888
+ TRICORE_MSUBMS_rrr2v110 = 870,
889
+ TRICORE_MSUBM_H_rrr1_LL = 871,
890
+ TRICORE_MSUBM_H_rrr1_LU = 872,
891
+ TRICORE_MSUBM_H_rrr1_UL = 873,
892
+ TRICORE_MSUBM_H_rrr1_UU = 874,
893
+ TRICORE_MSUBM_H_rrr1_v110 = 875,
894
+ TRICORE_MSUBM_Q_rrr1_v110 = 876,
895
+ TRICORE_MSUBM_U_rcrv110 = 877,
896
+ TRICORE_MSUBM_U_rrr2v110 = 878,
897
+ TRICORE_MSUBM_rcrv110 = 879,
898
+ TRICORE_MSUBM_rrr2v110 = 880,
899
+ TRICORE_MSUBRS_H_rrr1_LL = 881,
900
+ TRICORE_MSUBRS_H_rrr1_LU = 882,
901
+ TRICORE_MSUBRS_H_rrr1_UL = 883,
902
+ TRICORE_MSUBRS_H_rrr1_UL_2 = 884,
903
+ TRICORE_MSUBRS_H_rrr1_UU = 885,
904
+ TRICORE_MSUBRS_H_rrr1_v110 = 886,
905
+ TRICORE_MSUBRS_Q_rrr1_L_L = 887,
906
+ TRICORE_MSUBRS_Q_rrr1_U_U = 888,
907
+ TRICORE_MSUBRS_Q_rrr1_v110 = 889,
908
+ TRICORE_MSUBR_H_rrr1_LL = 890,
909
+ TRICORE_MSUBR_H_rrr1_LU = 891,
910
+ TRICORE_MSUBR_H_rrr1_UL = 892,
911
+ TRICORE_MSUBR_H_rrr1_UL_2 = 893,
912
+ TRICORE_MSUBR_H_rrr1_UU = 894,
913
+ TRICORE_MSUBR_H_rrr1_v110 = 895,
914
+ TRICORE_MSUBR_Q_rrr1_L_L = 896,
915
+ TRICORE_MSUBR_Q_rrr1_U_U = 897,
916
+ TRICORE_MSUBR_Q_rrr1_v110 = 898,
917
+ TRICORE_MSUBS_H_rrr1_LL = 899,
918
+ TRICORE_MSUBS_H_rrr1_LU = 900,
919
+ TRICORE_MSUBS_H_rrr1_UL = 901,
920
+ TRICORE_MSUBS_H_rrr1_UU = 902,
921
+ TRICORE_MSUBS_H_rrr1_v110 = 903,
922
+ TRICORE_MSUBS_Q_rrr1 = 904,
923
+ TRICORE_MSUBS_Q_rrr1_L = 905,
924
+ TRICORE_MSUBS_Q_rrr1_L_L = 906,
925
+ TRICORE_MSUBS_Q_rrr1_U = 907,
926
+ TRICORE_MSUBS_Q_rrr1_UU2_v110 = 908,
927
+ TRICORE_MSUBS_Q_rrr1_U_U = 909,
928
+ TRICORE_MSUBS_Q_rrr1_e = 910,
929
+ TRICORE_MSUBS_Q_rrr1_e_L = 911,
930
+ TRICORE_MSUBS_Q_rrr1_e_L_L = 912,
931
+ TRICORE_MSUBS_Q_rrr1_e_U = 913,
932
+ TRICORE_MSUBS_Q_rrr1_e_U_U = 914,
933
+ TRICORE_MSUBS_U_rcr = 915,
934
+ TRICORE_MSUBS_U_rcr_e = 916,
935
+ TRICORE_MSUBS_U_rrr2 = 917,
936
+ TRICORE_MSUBS_U_rrr2_e = 918,
937
+ TRICORE_MSUBS_rcr = 919,
938
+ TRICORE_MSUBS_rcr_e = 920,
939
+ TRICORE_MSUBS_rrr2 = 921,
940
+ TRICORE_MSUBS_rrr2_e = 922,
941
+ TRICORE_MSUB_F_rrr = 923,
942
+ TRICORE_MSUB_H_rrr1_LL = 924,
943
+ TRICORE_MSUB_H_rrr1_LU = 925,
944
+ TRICORE_MSUB_H_rrr1_UL = 926,
945
+ TRICORE_MSUB_H_rrr1_UU = 927,
946
+ TRICORE_MSUB_H_rrr1_v110 = 928,
947
+ TRICORE_MSUB_Q_rrr1 = 929,
948
+ TRICORE_MSUB_Q_rrr1_L = 930,
949
+ TRICORE_MSUB_Q_rrr1_L_L = 931,
950
+ TRICORE_MSUB_Q_rrr1_U = 932,
951
+ TRICORE_MSUB_Q_rrr1_UU2_v110 = 933,
952
+ TRICORE_MSUB_Q_rrr1_U_U = 934,
953
+ TRICORE_MSUB_Q_rrr1_e = 935,
954
+ TRICORE_MSUB_Q_rrr1_e_L = 936,
955
+ TRICORE_MSUB_Q_rrr1_e_L_L = 937,
956
+ TRICORE_MSUB_Q_rrr1_e_U = 938,
957
+ TRICORE_MSUB_Q_rrr1_e_U_U = 939,
958
+ TRICORE_MSUB_U_rcr = 940,
959
+ TRICORE_MSUB_U_rrr2 = 941,
960
+ TRICORE_MSUB_rcr = 942,
961
+ TRICORE_MSUB_rcr_e = 943,
962
+ TRICORE_MSUB_rrr2 = 944,
963
+ TRICORE_MSUB_rrr2_e = 945,
964
+ TRICORE_MTCR_rlc = 946,
965
+ TRICORE_MULMS_H_rr1_LL2e = 947,
966
+ TRICORE_MULMS_H_rr1_LU2e = 948,
967
+ TRICORE_MULMS_H_rr1_UL2e = 949,
968
+ TRICORE_MULMS_H_rr1_UU2e = 950,
969
+ TRICORE_MULM_H_rr1_LL2e = 951,
970
+ TRICORE_MULM_H_rr1_LU2e = 952,
971
+ TRICORE_MULM_H_rr1_UL2e = 953,
972
+ TRICORE_MULM_H_rr1_UU2e = 954,
973
+ TRICORE_MULM_U_rc = 955,
974
+ TRICORE_MULM_U_rr = 956,
975
+ TRICORE_MULM_rc = 957,
976
+ TRICORE_MULM_rr = 958,
977
+ TRICORE_MULR_H_rr1_LL2e = 959,
978
+ TRICORE_MULR_H_rr1_LU2e = 960,
979
+ TRICORE_MULR_H_rr1_UL2e = 961,
980
+ TRICORE_MULR_H_rr1_UU2e = 962,
981
+ TRICORE_MULR_H_rr_v110 = 963,
982
+ TRICORE_MULR_Q_rr1_2LL = 964,
983
+ TRICORE_MULR_Q_rr1_2UU = 965,
984
+ TRICORE_MULR_Q_rr_v110 = 966,
985
+ TRICORE_MULS_U_rc = 967,
986
+ TRICORE_MULS_U_rr2 = 968,
987
+ TRICORE_MULS_U_rr_v110 = 969,
988
+ TRICORE_MULS_rc = 970,
989
+ TRICORE_MULS_rr2 = 971,
990
+ TRICORE_MULS_rr_v110 = 972,
991
+ TRICORE_MUL_F_rrr = 973,
992
+ TRICORE_MUL_H_rr1_LL2e = 974,
993
+ TRICORE_MUL_H_rr1_LU2e = 975,
994
+ TRICORE_MUL_H_rr1_UL2e = 976,
995
+ TRICORE_MUL_H_rr1_UU2e = 977,
996
+ TRICORE_MUL_H_rr_v110 = 978,
997
+ TRICORE_MUL_Q_rr1_2 = 979,
998
+ TRICORE_MUL_Q_rr1_2LL = 980,
999
+ TRICORE_MUL_Q_rr1_2UU = 981,
1000
+ TRICORE_MUL_Q_rr1_2_L = 982,
1001
+ TRICORE_MUL_Q_rr1_2_Le = 983,
1002
+ TRICORE_MUL_Q_rr1_2_U = 984,
1003
+ TRICORE_MUL_Q_rr1_2_Ue = 985,
1004
+ TRICORE_MUL_Q_rr1_2__e = 986,
1005
+ TRICORE_MUL_Q_rr_v110 = 987,
1006
+ TRICORE_MUL_U_rc = 988,
1007
+ TRICORE_MUL_U_rr2 = 989,
1008
+ TRICORE_MUL_rc = 990,
1009
+ TRICORE_MUL_rc_e = 991,
1010
+ TRICORE_MUL_rr2 = 992,
1011
+ TRICORE_MUL_rr2_e = 993,
1012
+ TRICORE_MUL_rr_v110 = 994,
1013
+ TRICORE_MUL_srr = 995,
1014
+ TRICORE_NAND_T = 996,
1015
+ TRICORE_NAND_rc = 997,
1016
+ TRICORE_NAND_rr = 998,
1017
+ TRICORE_NEZ_A = 999,
1018
+ TRICORE_NE_A = 1000,
1019
+ TRICORE_NE_rc = 1001,
1020
+ TRICORE_NE_rr = 1002,
1021
+ TRICORE_NOP_sr = 1003,
1022
+ TRICORE_NOP_sys = 1004,
1023
+ TRICORE_NOR_T = 1005,
1024
+ TRICORE_NOR_rc = 1006,
1025
+ TRICORE_NOR_rr = 1007,
1026
+ TRICORE_NOR_sr = 1008,
1027
+ TRICORE_NOR_sr_v110 = 1009,
1028
+ TRICORE_NOT_sr_v162 = 1010,
1029
+ TRICORE_ORN_T = 1011,
1030
+ TRICORE_ORN_rc = 1012,
1031
+ TRICORE_ORN_rr = 1013,
1032
+ TRICORE_OR_ANDN_T = 1014,
1033
+ TRICORE_OR_AND_T = 1015,
1034
+ TRICORE_OR_EQ_rc = 1016,
1035
+ TRICORE_OR_EQ_rr = 1017,
1036
+ TRICORE_OR_GE_U_rc = 1018,
1037
+ TRICORE_OR_GE_U_rr = 1019,
1038
+ TRICORE_OR_GE_rc = 1020,
1039
+ TRICORE_OR_GE_rr = 1021,
1040
+ TRICORE_OR_LT_U_rc = 1022,
1041
+ TRICORE_OR_LT_U_rr = 1023,
1042
+ TRICORE_OR_LT_rc = 1024,
1043
+ TRICORE_OR_LT_rr = 1025,
1044
+ TRICORE_OR_NE_rc = 1026,
1045
+ TRICORE_OR_NE_rr = 1027,
1046
+ TRICORE_OR_NOR_T = 1028,
1047
+ TRICORE_OR_OR_T = 1029,
1048
+ TRICORE_OR_T = 1030,
1049
+ TRICORE_OR_rc = 1031,
1050
+ TRICORE_OR_rr = 1032,
1051
+ TRICORE_OR_sc = 1033,
1052
+ TRICORE_OR_sc_v110 = 1034,
1053
+ TRICORE_OR_srr = 1035,
1054
+ TRICORE_OR_srr_v110 = 1036,
1055
+ TRICORE_PACK_rrr = 1037,
1056
+ TRICORE_PARITY_rr = 1038,
1057
+ TRICORE_PARITY_rr_v110 = 1039,
1058
+ TRICORE_POPCNT_W_rr = 1040,
1059
+ TRICORE_Q31TOF_rr = 1041,
1060
+ TRICORE_QSEED_F_rr = 1042,
1061
+ TRICORE_RESTORE_sys = 1043,
1062
+ TRICORE_RET_sr = 1044,
1063
+ TRICORE_RET_sys = 1045,
1064
+ TRICORE_RET_sys_v110 = 1046,
1065
+ TRICORE_RFE_sr = 1047,
1066
+ TRICORE_RFE_sys_sys = 1048,
1067
+ TRICORE_RFE_sys_sys_v110 = 1049,
1068
+ TRICORE_RFM_sys = 1050,
1069
+ TRICORE_RSLCX_sys = 1051,
1070
+ TRICORE_RSTV_sys = 1052,
1071
+ TRICORE_RSUBS_U_rc = 1053,
1072
+ TRICORE_RSUBS_rc = 1054,
1073
+ TRICORE_RSUB_rc = 1055,
1074
+ TRICORE_RSUB_sr_sr = 1056,
1075
+ TRICORE_RSUB_sr_sr_v110 = 1057,
1076
+ TRICORE_SAT_BU_rr = 1058,
1077
+ TRICORE_SAT_BU_sr = 1059,
1078
+ TRICORE_SAT_BU_sr_v110 = 1060,
1079
+ TRICORE_SAT_B_rr = 1061,
1080
+ TRICORE_SAT_B_sr = 1062,
1081
+ TRICORE_SAT_B_sr_v110 = 1063,
1082
+ TRICORE_SAT_HU_rr = 1064,
1083
+ TRICORE_SAT_HU_sr = 1065,
1084
+ TRICORE_SAT_HU_sr_v110 = 1066,
1085
+ TRICORE_SAT_H_rr = 1067,
1086
+ TRICORE_SAT_H_sr = 1068,
1087
+ TRICORE_SAT_H_sr_v110 = 1069,
1088
+ TRICORE_SELN_A_rcr_v110 = 1070,
1089
+ TRICORE_SELN_A_rrr_v110 = 1071,
1090
+ TRICORE_SELN_rcr = 1072,
1091
+ TRICORE_SELN_rrr = 1073,
1092
+ TRICORE_SEL_A_rcr_v110 = 1074,
1093
+ TRICORE_SEL_A_rrr_v110 = 1075,
1094
+ TRICORE_SEL_rcr = 1076,
1095
+ TRICORE_SEL_rrr = 1077,
1096
+ TRICORE_SHAS_rc = 1078,
1097
+ TRICORE_SHAS_rr = 1079,
1098
+ TRICORE_SHA_B_rc = 1080,
1099
+ TRICORE_SHA_B_rr = 1081,
1100
+ TRICORE_SHA_H_rc = 1082,
1101
+ TRICORE_SHA_H_rr = 1083,
1102
+ TRICORE_SHA_rc = 1084,
1103
+ TRICORE_SHA_rr = 1085,
1104
+ TRICORE_SHA_src = 1086,
1105
+ TRICORE_SHA_src_v110 = 1087,
1106
+ TRICORE_SHUFFLE_rc = 1088,
1107
+ TRICORE_SH_ANDN_T = 1089,
1108
+ TRICORE_SH_AND_T = 1090,
1109
+ TRICORE_SH_B_rc = 1091,
1110
+ TRICORE_SH_B_rr = 1092,
1111
+ TRICORE_SH_EQ_rc = 1093,
1112
+ TRICORE_SH_EQ_rr = 1094,
1113
+ TRICORE_SH_GE_U_rc = 1095,
1114
+ TRICORE_SH_GE_U_rr = 1096,
1115
+ TRICORE_SH_GE_rc = 1097,
1116
+ TRICORE_SH_GE_rr = 1098,
1117
+ TRICORE_SH_H_rc = 1099,
1118
+ TRICORE_SH_H_rr = 1100,
1119
+ TRICORE_SH_LT_U_rc = 1101,
1120
+ TRICORE_SH_LT_U_rr = 1102,
1121
+ TRICORE_SH_LT_rc = 1103,
1122
+ TRICORE_SH_LT_rr = 1104,
1123
+ TRICORE_SH_NAND_T = 1105,
1124
+ TRICORE_SH_NE_rc = 1106,
1125
+ TRICORE_SH_NE_rr = 1107,
1126
+ TRICORE_SH_NOR_T = 1108,
1127
+ TRICORE_SH_ORN_T = 1109,
1128
+ TRICORE_SH_OR_T = 1110,
1129
+ TRICORE_SH_XNOR_T = 1111,
1130
+ TRICORE_SH_XOR_T = 1112,
1131
+ TRICORE_SH_rc = 1113,
1132
+ TRICORE_SH_rr = 1114,
1133
+ TRICORE_SH_src = 1115,
1134
+ TRICORE_SH_src_v110 = 1116,
1135
+ TRICORE_STLCX_abs = 1117,
1136
+ TRICORE_STLCX_bo_bso = 1118,
1137
+ TRICORE_STUCX_abs = 1119,
1138
+ TRICORE_STUCX_bo_bso = 1120,
1139
+ TRICORE_ST_A_abs = 1121,
1140
+ TRICORE_ST_A_bo_bso = 1122,
1141
+ TRICORE_ST_A_bo_c = 1123,
1142
+ TRICORE_ST_A_bo_pos = 1124,
1143
+ TRICORE_ST_A_bo_pre = 1125,
1144
+ TRICORE_ST_A_bo_r = 1126,
1145
+ TRICORE_ST_A_bol = 1127,
1146
+ TRICORE_ST_A_sc = 1128,
1147
+ TRICORE_ST_A_sro = 1129,
1148
+ TRICORE_ST_A_sro_v110 = 1130,
1149
+ TRICORE_ST_A_ssr = 1131,
1150
+ TRICORE_ST_A_ssr_pos = 1132,
1151
+ TRICORE_ST_A_ssr_pos_v110 = 1133,
1152
+ TRICORE_ST_A_ssr_v110 = 1134,
1153
+ TRICORE_ST_A_ssro = 1135,
1154
+ TRICORE_ST_A_ssro_v110 = 1136,
1155
+ TRICORE_ST_B_abs = 1137,
1156
+ TRICORE_ST_B_bo_bso = 1138,
1157
+ TRICORE_ST_B_bo_c = 1139,
1158
+ TRICORE_ST_B_bo_pos = 1140,
1159
+ TRICORE_ST_B_bo_pre = 1141,
1160
+ TRICORE_ST_B_bo_r = 1142,
1161
+ TRICORE_ST_B_bol = 1143,
1162
+ TRICORE_ST_B_sro = 1144,
1163
+ TRICORE_ST_B_sro_v110 = 1145,
1164
+ TRICORE_ST_B_ssr = 1146,
1165
+ TRICORE_ST_B_ssr_pos = 1147,
1166
+ TRICORE_ST_B_ssr_pos_v110 = 1148,
1167
+ TRICORE_ST_B_ssr_v110 = 1149,
1168
+ TRICORE_ST_B_ssro = 1150,
1169
+ TRICORE_ST_B_ssro_v110 = 1151,
1170
+ TRICORE_ST_DA_abs = 1152,
1171
+ TRICORE_ST_DA_bo_bso = 1153,
1172
+ TRICORE_ST_DA_bo_c = 1154,
1173
+ TRICORE_ST_DA_bo_pos = 1155,
1174
+ TRICORE_ST_DA_bo_pre = 1156,
1175
+ TRICORE_ST_DA_bo_r = 1157,
1176
+ TRICORE_ST_D_abs = 1158,
1177
+ TRICORE_ST_D_bo_bso = 1159,
1178
+ TRICORE_ST_D_bo_c = 1160,
1179
+ TRICORE_ST_D_bo_pos = 1161,
1180
+ TRICORE_ST_D_bo_pre = 1162,
1181
+ TRICORE_ST_D_bo_r = 1163,
1182
+ TRICORE_ST_H_abs = 1164,
1183
+ TRICORE_ST_H_bo_bso = 1165,
1184
+ TRICORE_ST_H_bo_c = 1166,
1185
+ TRICORE_ST_H_bo_pos = 1167,
1186
+ TRICORE_ST_H_bo_pre = 1168,
1187
+ TRICORE_ST_H_bo_r = 1169,
1188
+ TRICORE_ST_H_bol = 1170,
1189
+ TRICORE_ST_H_sro = 1171,
1190
+ TRICORE_ST_H_sro_v110 = 1172,
1191
+ TRICORE_ST_H_ssr = 1173,
1192
+ TRICORE_ST_H_ssr_pos = 1174,
1193
+ TRICORE_ST_H_ssr_pos_v110 = 1175,
1194
+ TRICORE_ST_H_ssr_v110 = 1176,
1195
+ TRICORE_ST_H_ssro = 1177,
1196
+ TRICORE_ST_H_ssro_v110 = 1178,
1197
+ TRICORE_ST_Q_abs = 1179,
1198
+ TRICORE_ST_Q_bo_bso = 1180,
1199
+ TRICORE_ST_Q_bo_c = 1181,
1200
+ TRICORE_ST_Q_bo_pos = 1182,
1201
+ TRICORE_ST_Q_bo_pre = 1183,
1202
+ TRICORE_ST_Q_bo_r = 1184,
1203
+ TRICORE_ST_T = 1185,
1204
+ TRICORE_ST_W_abs = 1186,
1205
+ TRICORE_ST_W_bo_bso = 1187,
1206
+ TRICORE_ST_W_bo_c = 1188,
1207
+ TRICORE_ST_W_bo_pos = 1189,
1208
+ TRICORE_ST_W_bo_pre = 1190,
1209
+ TRICORE_ST_W_bo_r = 1191,
1210
+ TRICORE_ST_W_bol = 1192,
1211
+ TRICORE_ST_W_sc = 1193,
1212
+ TRICORE_ST_W_sro = 1194,
1213
+ TRICORE_ST_W_sro_v110 = 1195,
1214
+ TRICORE_ST_W_ssr = 1196,
1215
+ TRICORE_ST_W_ssr_pos = 1197,
1216
+ TRICORE_ST_W_ssr_pos_v110 = 1198,
1217
+ TRICORE_ST_W_ssr_v110 = 1199,
1218
+ TRICORE_ST_W_ssro = 1200,
1219
+ TRICORE_ST_W_ssro_v110 = 1201,
1220
+ TRICORE_SUBC_rr = 1202,
1221
+ TRICORE_SUBSC_A_rr = 1203,
1222
+ TRICORE_SUBS_BU_rr = 1204,
1223
+ TRICORE_SUBS_B_rr = 1205,
1224
+ TRICORE_SUBS_HU_rr = 1206,
1225
+ TRICORE_SUBS_H_rr = 1207,
1226
+ TRICORE_SUBS_U_rr = 1208,
1227
+ TRICORE_SUBS_rr = 1209,
1228
+ TRICORE_SUBS_srr = 1210,
1229
+ TRICORE_SUBX_rr = 1211,
1230
+ TRICORE_SUB_A_rr = 1212,
1231
+ TRICORE_SUB_A_sc = 1213,
1232
+ TRICORE_SUB_A_sc_v110 = 1214,
1233
+ TRICORE_SUB_B_rr = 1215,
1234
+ TRICORE_SUB_F_rrr = 1216,
1235
+ TRICORE_SUB_H_rr = 1217,
1236
+ TRICORE_SUB_rr = 1218,
1237
+ TRICORE_SUB_srr = 1219,
1238
+ TRICORE_SUB_srr_15a = 1220,
1239
+ TRICORE_SUB_srr_a15 = 1221,
1240
+ TRICORE_SVLCX_sys = 1222,
1241
+ TRICORE_SWAPMSK_W_bo_bso = 1223,
1242
+ TRICORE_SWAPMSK_W_bo_c = 1224,
1243
+ TRICORE_SWAPMSK_W_bo_i = 1225,
1244
+ TRICORE_SWAPMSK_W_bo_pos = 1226,
1245
+ TRICORE_SWAPMSK_W_bo_pre = 1227,
1246
+ TRICORE_SWAPMSK_W_bo_r = 1228,
1247
+ TRICORE_SWAP_A_abs = 1229,
1248
+ TRICORE_SWAP_A_bo_bso = 1230,
1249
+ TRICORE_SWAP_A_bo_c = 1231,
1250
+ TRICORE_SWAP_A_bo_pos = 1232,
1251
+ TRICORE_SWAP_A_bo_pre = 1233,
1252
+ TRICORE_SWAP_A_bo_r = 1234,
1253
+ TRICORE_SWAP_W_abs = 1235,
1254
+ TRICORE_SWAP_W_bo_bso = 1236,
1255
+ TRICORE_SWAP_W_bo_c = 1237,
1256
+ TRICORE_SWAP_W_bo_i = 1238,
1257
+ TRICORE_SWAP_W_bo_pos = 1239,
1258
+ TRICORE_SWAP_W_bo_pre = 1240,
1259
+ TRICORE_SWAP_W_bo_r = 1241,
1260
+ TRICORE_SYSCALL_rc = 1242,
1261
+ TRICORE_TLBDEMAP_rr = 1243,
1262
+ TRICORE_TLBFLUSH_A_rr = 1244,
1263
+ TRICORE_TLBFLUSH_B_rr = 1245,
1264
+ TRICORE_TLBMAP_rr = 1246,
1265
+ TRICORE_TLBPROBE_A_rr = 1247,
1266
+ TRICORE_TLBPROBE_I_rr = 1248,
1267
+ TRICORE_TRAPSV_sys = 1249,
1268
+ TRICORE_TRAPV_sys = 1250,
1269
+ TRICORE_UNPACK_rr_rr = 1251,
1270
+ TRICORE_UNPACK_rr_rr_v110 = 1252,
1271
+ TRICORE_UPDFL_rr = 1253,
1272
+ TRICORE_UTOF_rr = 1254,
1273
+ TRICORE_WAIT_sys = 1255,
1274
+ TRICORE_XNOR_T = 1256,
1275
+ TRICORE_XNOR_rc = 1257,
1276
+ TRICORE_XNOR_rr = 1258,
1277
+ TRICORE_XOR_EQ_rc = 1259,
1278
+ TRICORE_XOR_EQ_rr = 1260,
1279
+ TRICORE_XOR_GE_U_rc = 1261,
1280
+ TRICORE_XOR_GE_U_rr = 1262,
1281
+ TRICORE_XOR_GE_rc = 1263,
1282
+ TRICORE_XOR_GE_rr = 1264,
1283
+ TRICORE_XOR_LT_U_rc = 1265,
1284
+ TRICORE_XOR_LT_U_rr = 1266,
1285
+ TRICORE_XOR_LT_rc = 1267,
1286
+ TRICORE_XOR_LT_rr = 1268,
1287
+ TRICORE_XOR_NE_rc = 1269,
1288
+ TRICORE_XOR_NE_rr = 1270,
1289
+ TRICORE_XOR_T = 1271,
1290
+ TRICORE_XOR_rc = 1272,
1291
+ TRICORE_XOR_rr = 1273,
1292
+ TRICORE_XOR_srr = 1274,
1293
+ INSTRUCTION_LIST_END = 1275
1294
+ };
1295
+
1296
+ #endif // GET_INSTRINFO_ENUM
1297
+
1298
+ #ifdef GET_INSTRINFO_MC_DESC
1299
+ #undef GET_INSTRINFO_MC_DESC
1300
+
1301
+
1302
+ static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1303
+ static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1304
+ static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1305
+ static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1306
+ static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1307
+ static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1308
+ static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1309
+ static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, };
1310
+ static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1311
+ static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1312
+ static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
1313
+ static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1314
+ static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1315
+ static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1316
+ static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1317
+ static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
1318
+ static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1319
+ static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1320
+ static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1321
+ static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1322
+ static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
1323
+ static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1324
+ static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
1325
+ static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1326
+ static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1327
+ static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1328
+ static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1329
+ static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1330
+ static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1331
+ static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1332
+ static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1333
+ static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1334
+ static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1335
+ static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1336
+ static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1337
+ static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
1338
+ static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1339
+ static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
1340
+ static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
1341
+ static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1342
+ static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
1343
+ static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
1344
+ static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
1345
+ static const MCOperandInfo OperandInfo45[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1346
+ static const MCOperandInfo OperandInfo46[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1347
+ static const MCOperandInfo OperandInfo47[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1348
+ static const MCOperandInfo OperandInfo48[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1349
+ static const MCOperandInfo OperandInfo49[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1350
+ static const MCOperandInfo OperandInfo50[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1351
+ static const MCOperandInfo OperandInfo51[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1352
+ static const MCOperandInfo OperandInfo52[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1353
+ static const MCOperandInfo OperandInfo53[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1354
+ static const MCOperandInfo OperandInfo54[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1355
+ static const MCOperandInfo OperandInfo55[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1356
+ static const MCOperandInfo OperandInfo56[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1357
+ static const MCOperandInfo OperandInfo57[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1358
+ static const MCOperandInfo OperandInfo58[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1359
+ static const MCOperandInfo OperandInfo59[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1360
+ static const MCOperandInfo OperandInfo60[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1361
+ static const MCOperandInfo OperandInfo61[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1362
+ static const MCOperandInfo OperandInfo62[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1363
+ static const MCOperandInfo OperandInfo63[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1364
+ static const MCOperandInfo OperandInfo64[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1365
+ static const MCOperandInfo OperandInfo65[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1366
+ static const MCOperandInfo OperandInfo66[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1367
+ static const MCOperandInfo OperandInfo67[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1368
+ static const MCOperandInfo OperandInfo68[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1369
+ static const MCOperandInfo OperandInfo69[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1370
+ static const MCOperandInfo OperandInfo70[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1371
+ static const MCOperandInfo OperandInfo71[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1372
+ static const MCOperandInfo OperandInfo72[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1373
+ static const MCOperandInfo OperandInfo73[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1374
+ static const MCOperandInfo OperandInfo74[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1375
+ static const MCOperandInfo OperandInfo75[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1376
+ static const MCOperandInfo OperandInfo76[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1377
+ static const MCOperandInfo OperandInfo77[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1378
+ static const MCOperandInfo OperandInfo78[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1379
+ static const MCOperandInfo OperandInfo79[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1380
+ static const MCOperandInfo OperandInfo80[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1381
+ static const MCOperandInfo OperandInfo81[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1382
+ static const MCOperandInfo OperandInfo82[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1383
+ static const MCOperandInfo OperandInfo83[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1384
+ static const MCOperandInfo OperandInfo84[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1385
+ static const MCOperandInfo OperandInfo85[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1386
+ static const MCOperandInfo OperandInfo86[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1387
+ static const MCOperandInfo OperandInfo87[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1388
+ static const MCOperandInfo OperandInfo88[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1389
+ static const MCOperandInfo OperandInfo89[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1390
+ static const MCOperandInfo OperandInfo90[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1391
+ static const MCOperandInfo OperandInfo91[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1392
+ static const MCOperandInfo OperandInfo92[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1393
+ static const MCOperandInfo OperandInfo93[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1394
+ static const MCOperandInfo OperandInfo94[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1395
+ static const MCOperandInfo OperandInfo95[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1396
+ static const MCOperandInfo OperandInfo96[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1397
+ static const MCOperandInfo OperandInfo97[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1398
+ static const MCOperandInfo OperandInfo98[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1399
+ static const MCOperandInfo OperandInfo99[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1400
+ static const MCOperandInfo OperandInfo100[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1401
+ static const MCOperandInfo OperandInfo101[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1402
+ static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1403
+ static const MCOperandInfo OperandInfo103[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1404
+ static const MCOperandInfo OperandInfo104[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1405
+ static const MCOperandInfo OperandInfo105[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1406
+ static const MCOperandInfo OperandInfo106[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1407
+ static const MCOperandInfo OperandInfo107[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1408
+ static const MCOperandInfo OperandInfo108[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
1409
+ static const MCOperandInfo OperandInfo109[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1410
+ static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
1411
+ static const MCOperandInfo OperandInfo111[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
1412
+
1413
+ static const MCInstrDesc TriCoreInsts[] = {
1414
+ { 1, OperandInfo2 }, // Inst #0 = PHI
1415
+ { 0, 0 }, // Inst #1 = INLINEASM
1416
+ { 0, 0 }, // Inst #2 = INLINEASM_BR
1417
+ { 1, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION
1418
+ { 1, OperandInfo3 }, // Inst #4 = EH_LABEL
1419
+ { 1, OperandInfo3 }, // Inst #5 = GC_LABEL
1420
+ { 1, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL
1421
+ { 0, 0 }, // Inst #7 = KILL
1422
+ { 3, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG
1423
+ { 4, OperandInfo5 }, // Inst #9 = INSERT_SUBREG
1424
+ { 1, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF
1425
+ { 4, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG
1426
+ { 3, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS
1427
+ { 0, 0 }, // Inst #13 = DBG_VALUE
1428
+ { 0, 0 }, // Inst #14 = DBG_VALUE_LIST
1429
+ { 0, 0 }, // Inst #15 = DBG_INSTR_REF
1430
+ { 0, 0 }, // Inst #16 = DBG_PHI
1431
+ { 1, OperandInfo2 }, // Inst #17 = DBG_LABEL
1432
+ { 2, OperandInfo7 }, // Inst #18 = REG_SEQUENCE
1433
+ { 2, OperandInfo7 }, // Inst #19 = COPY
1434
+ { 0, 0 }, // Inst #20 = BUNDLE
1435
+ { 1, OperandInfo3 }, // Inst #21 = LIFETIME_START
1436
+ { 1, OperandInfo3 }, // Inst #22 = LIFETIME_END
1437
+ { 4, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE
1438
+ { 2, OperandInfo9 }, // Inst #24 = ARITH_FENCE
1439
+ { 2, OperandInfo10 }, // Inst #25 = STACKMAP
1440
+ { 0, 0 }, // Inst #26 = FENTRY_CALL
1441
+ { 6, OperandInfo11 }, // Inst #27 = PATCHPOINT
1442
+ { 1, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD
1443
+ { 1, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP
1444
+ { 3, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG
1445
+ { 0, 0 }, // Inst #31 = STATEPOINT
1446
+ { 2, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE
1447
+ { 1, OperandInfo2 }, // Inst #33 = FAULTING_OP
1448
+ { 0, 0 }, // Inst #34 = PATCHABLE_OP
1449
+ { 0, 0 }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
1450
+ { 0, 0 }, // Inst #36 = PATCHABLE_RET
1451
+ { 0, 0 }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
1452
+ { 0, 0 }, // Inst #38 = PATCHABLE_TAIL_CALL
1453
+ { 2, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL
1454
+ { 3, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1455
+ { 0, 0 }, // Inst #41 = ICALL_BRANCH_FUNNEL
1456
+ { 0, 0 }, // Inst #42 = MEMBARRIER
1457
+ { 3, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT
1458
+ { 3, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT
1459
+ { 3, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN
1460
+ { 3, OperandInfo18 }, // Inst #46 = G_ADD
1461
+ { 3, OperandInfo18 }, // Inst #47 = G_SUB
1462
+ { 3, OperandInfo18 }, // Inst #48 = G_MUL
1463
+ { 3, OperandInfo18 }, // Inst #49 = G_SDIV
1464
+ { 3, OperandInfo18 }, // Inst #50 = G_UDIV
1465
+ { 3, OperandInfo18 }, // Inst #51 = G_SREM
1466
+ { 3, OperandInfo18 }, // Inst #52 = G_UREM
1467
+ { 4, OperandInfo19 }, // Inst #53 = G_SDIVREM
1468
+ { 4, OperandInfo19 }, // Inst #54 = G_UDIVREM
1469
+ { 3, OperandInfo18 }, // Inst #55 = G_AND
1470
+ { 3, OperandInfo18 }, // Inst #56 = G_OR
1471
+ { 3, OperandInfo18 }, // Inst #57 = G_XOR
1472
+ { 1, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF
1473
+ { 1, OperandInfo20 }, // Inst #59 = G_PHI
1474
+ { 2, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX
1475
+ { 2, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE
1476
+ { 3, OperandInfo22 }, // Inst #62 = G_EXTRACT
1477
+ { 2, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES
1478
+ { 4, OperandInfo24 }, // Inst #64 = G_INSERT
1479
+ { 2, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES
1480
+ { 2, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR
1481
+ { 2, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC
1482
+ { 2, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS
1483
+ { 2, OperandInfo23 }, // Inst #69 = G_PTRTOINT
1484
+ { 2, OperandInfo23 }, // Inst #70 = G_INTTOPTR
1485
+ { 2, OperandInfo23 }, // Inst #71 = G_BITCAST
1486
+ { 2, OperandInfo25 }, // Inst #72 = G_FREEZE
1487
+ { 3, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND
1488
+ { 2, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC
1489
+ { 2, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND
1490
+ { 2, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT
1491
+ { 2, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN
1492
+ { 1, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER
1493
+ { 2, OperandInfo23 }, // Inst #79 = G_LOAD
1494
+ { 2, OperandInfo23 }, // Inst #80 = G_SEXTLOAD
1495
+ { 2, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD
1496
+ { 5, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD
1497
+ { 5, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD
1498
+ { 5, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD
1499
+ { 2, OperandInfo23 }, // Inst #85 = G_STORE
1500
+ { 5, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE
1501
+ { 5, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1502
+ { 4, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG
1503
+ { 3, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG
1504
+ { 3, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD
1505
+ { 3, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB
1506
+ { 3, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND
1507
+ { 3, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND
1508
+ { 3, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR
1509
+ { 3, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR
1510
+ { 3, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX
1511
+ { 3, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN
1512
+ { 3, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX
1513
+ { 3, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN
1514
+ { 3, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD
1515
+ { 3, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB
1516
+ { 3, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX
1517
+ { 3, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN
1518
+ { 3, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP
1519
+ { 3, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP
1520
+ { 2, OperandInfo10 }, // Inst #106 = G_FENCE
1521
+ { 2, OperandInfo21 }, // Inst #107 = G_BRCOND
1522
+ { 1, OperandInfo20 }, // Inst #108 = G_BRINDIRECT
1523
+ { 0, 0 }, // Inst #109 = G_INVOKE_REGION_START
1524
+ { 1, OperandInfo2 }, // Inst #110 = G_INTRINSIC
1525
+ { 1, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS
1526
+ { 2, OperandInfo23 }, // Inst #112 = G_ANYEXT
1527
+ { 2, OperandInfo23 }, // Inst #113 = G_TRUNC
1528
+ { 2, OperandInfo21 }, // Inst #114 = G_CONSTANT
1529
+ { 2, OperandInfo21 }, // Inst #115 = G_FCONSTANT
1530
+ { 1, OperandInfo20 }, // Inst #116 = G_VASTART
1531
+ { 3, OperandInfo32 }, // Inst #117 = G_VAARG
1532
+ { 2, OperandInfo23 }, // Inst #118 = G_SEXT
1533
+ { 3, OperandInfo17 }, // Inst #119 = G_SEXT_INREG
1534
+ { 2, OperandInfo23 }, // Inst #120 = G_ZEXT
1535
+ { 3, OperandInfo33 }, // Inst #121 = G_SHL
1536
+ { 3, OperandInfo33 }, // Inst #122 = G_LSHR
1537
+ { 3, OperandInfo33 }, // Inst #123 = G_ASHR
1538
+ { 4, OperandInfo34 }, // Inst #124 = G_FSHL
1539
+ { 4, OperandInfo34 }, // Inst #125 = G_FSHR
1540
+ { 3, OperandInfo33 }, // Inst #126 = G_ROTR
1541
+ { 3, OperandInfo33 }, // Inst #127 = G_ROTL
1542
+ { 4, OperandInfo35 }, // Inst #128 = G_ICMP
1543
+ { 4, OperandInfo35 }, // Inst #129 = G_FCMP
1544
+ { 4, OperandInfo30 }, // Inst #130 = G_SELECT
1545
+ { 4, OperandInfo30 }, // Inst #131 = G_UADDO
1546
+ { 5, OperandInfo36 }, // Inst #132 = G_UADDE
1547
+ { 4, OperandInfo30 }, // Inst #133 = G_USUBO
1548
+ { 5, OperandInfo36 }, // Inst #134 = G_USUBE
1549
+ { 4, OperandInfo30 }, // Inst #135 = G_SADDO
1550
+ { 5, OperandInfo36 }, // Inst #136 = G_SADDE
1551
+ { 4, OperandInfo30 }, // Inst #137 = G_SSUBO
1552
+ { 5, OperandInfo36 }, // Inst #138 = G_SSUBE
1553
+ { 4, OperandInfo30 }, // Inst #139 = G_UMULO
1554
+ { 4, OperandInfo30 }, // Inst #140 = G_SMULO
1555
+ { 3, OperandInfo18 }, // Inst #141 = G_UMULH
1556
+ { 3, OperandInfo18 }, // Inst #142 = G_SMULH
1557
+ { 3, OperandInfo18 }, // Inst #143 = G_UADDSAT
1558
+ { 3, OperandInfo18 }, // Inst #144 = G_SADDSAT
1559
+ { 3, OperandInfo18 }, // Inst #145 = G_USUBSAT
1560
+ { 3, OperandInfo18 }, // Inst #146 = G_SSUBSAT
1561
+ { 3, OperandInfo33 }, // Inst #147 = G_USHLSAT
1562
+ { 3, OperandInfo33 }, // Inst #148 = G_SSHLSAT
1563
+ { 4, OperandInfo37 }, // Inst #149 = G_SMULFIX
1564
+ { 4, OperandInfo37 }, // Inst #150 = G_UMULFIX
1565
+ { 4, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT
1566
+ { 4, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT
1567
+ { 4, OperandInfo37 }, // Inst #153 = G_SDIVFIX
1568
+ { 4, OperandInfo37 }, // Inst #154 = G_UDIVFIX
1569
+ { 4, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT
1570
+ { 4, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT
1571
+ { 3, OperandInfo18 }, // Inst #157 = G_FADD
1572
+ { 3, OperandInfo18 }, // Inst #158 = G_FSUB
1573
+ { 3, OperandInfo18 }, // Inst #159 = G_FMUL
1574
+ { 4, OperandInfo19 }, // Inst #160 = G_FMA
1575
+ { 4, OperandInfo19 }, // Inst #161 = G_FMAD
1576
+ { 3, OperandInfo18 }, // Inst #162 = G_FDIV
1577
+ { 3, OperandInfo18 }, // Inst #163 = G_FREM
1578
+ { 3, OperandInfo18 }, // Inst #164 = G_FPOW
1579
+ { 3, OperandInfo33 }, // Inst #165 = G_FPOWI
1580
+ { 2, OperandInfo25 }, // Inst #166 = G_FEXP
1581
+ { 2, OperandInfo25 }, // Inst #167 = G_FEXP2
1582
+ { 2, OperandInfo25 }, // Inst #168 = G_FLOG
1583
+ { 2, OperandInfo25 }, // Inst #169 = G_FLOG2
1584
+ { 2, OperandInfo25 }, // Inst #170 = G_FLOG10
1585
+ { 2, OperandInfo25 }, // Inst #171 = G_FNEG
1586
+ { 2, OperandInfo23 }, // Inst #172 = G_FPEXT
1587
+ { 2, OperandInfo23 }, // Inst #173 = G_FPTRUNC
1588
+ { 2, OperandInfo23 }, // Inst #174 = G_FPTOSI
1589
+ { 2, OperandInfo23 }, // Inst #175 = G_FPTOUI
1590
+ { 2, OperandInfo23 }, // Inst #176 = G_SITOFP
1591
+ { 2, OperandInfo23 }, // Inst #177 = G_UITOFP
1592
+ { 2, OperandInfo25 }, // Inst #178 = G_FABS
1593
+ { 3, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN
1594
+ { 3, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS
1595
+ { 2, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE
1596
+ { 3, OperandInfo18 }, // Inst #182 = G_FMINNUM
1597
+ { 3, OperandInfo18 }, // Inst #183 = G_FMAXNUM
1598
+ { 3, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE
1599
+ { 3, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE
1600
+ { 3, OperandInfo18 }, // Inst #186 = G_FMINIMUM
1601
+ { 3, OperandInfo18 }, // Inst #187 = G_FMAXIMUM
1602
+ { 3, OperandInfo33 }, // Inst #188 = G_PTR_ADD
1603
+ { 3, OperandInfo33 }, // Inst #189 = G_PTRMASK
1604
+ { 3, OperandInfo18 }, // Inst #190 = G_SMIN
1605
+ { 3, OperandInfo18 }, // Inst #191 = G_SMAX
1606
+ { 3, OperandInfo18 }, // Inst #192 = G_UMIN
1607
+ { 3, OperandInfo18 }, // Inst #193 = G_UMAX
1608
+ { 2, OperandInfo25 }, // Inst #194 = G_ABS
1609
+ { 2, OperandInfo23 }, // Inst #195 = G_LROUND
1610
+ { 2, OperandInfo23 }, // Inst #196 = G_LLROUND
1611
+ { 1, OperandInfo2 }, // Inst #197 = G_BR
1612
+ { 3, OperandInfo38 }, // Inst #198 = G_BRJT
1613
+ { 4, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT
1614
+ { 3, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT
1615
+ { 4, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR
1616
+ { 2, OperandInfo23 }, // Inst #202 = G_CTTZ
1617
+ { 2, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF
1618
+ { 2, OperandInfo23 }, // Inst #204 = G_CTLZ
1619
+ { 2, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF
1620
+ { 2, OperandInfo23 }, // Inst #206 = G_CTPOP
1621
+ { 2, OperandInfo25 }, // Inst #207 = G_BSWAP
1622
+ { 2, OperandInfo25 }, // Inst #208 = G_BITREVERSE
1623
+ { 2, OperandInfo25 }, // Inst #209 = G_FCEIL
1624
+ { 2, OperandInfo25 }, // Inst #210 = G_FCOS
1625
+ { 2, OperandInfo25 }, // Inst #211 = G_FSIN
1626
+ { 2, OperandInfo25 }, // Inst #212 = G_FSQRT
1627
+ { 2, OperandInfo25 }, // Inst #213 = G_FFLOOR
1628
+ { 2, OperandInfo25 }, // Inst #214 = G_FRINT
1629
+ { 2, OperandInfo25 }, // Inst #215 = G_FNEARBYINT
1630
+ { 2, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST
1631
+ { 2, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR
1632
+ { 2, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE
1633
+ { 3, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC
1634
+ { 3, OperandInfo18 }, // Inst #220 = G_STRICT_FADD
1635
+ { 3, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB
1636
+ { 3, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL
1637
+ { 3, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV
1638
+ { 3, OperandInfo18 }, // Inst #224 = G_STRICT_FREM
1639
+ { 4, OperandInfo19 }, // Inst #225 = G_STRICT_FMA
1640
+ { 2, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT
1641
+ { 2, OperandInfo21 }, // Inst #227 = G_READ_REGISTER
1642
+ { 2, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER
1643
+ { 4, OperandInfo43 }, // Inst #229 = G_MEMCPY
1644
+ { 3, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE
1645
+ { 4, OperandInfo43 }, // Inst #231 = G_MEMMOVE
1646
+ { 4, OperandInfo43 }, // Inst #232 = G_MEMSET
1647
+ { 3, OperandInfo22 }, // Inst #233 = G_BZERO
1648
+ { 3, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD
1649
+ { 3, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL
1650
+ { 2, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD
1651
+ { 2, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL
1652
+ { 2, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX
1653
+ { 2, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN
1654
+ { 2, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD
1655
+ { 2, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL
1656
+ { 2, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND
1657
+ { 2, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR
1658
+ { 2, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR
1659
+ { 2, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX
1660
+ { 2, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN
1661
+ { 2, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX
1662
+ { 2, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN
1663
+ { 4, OperandInfo44 }, // Inst #249 = G_SBFX
1664
+ { 4, OperandInfo44 }, // Inst #250 = G_UBFX
1665
+ { 3, OperandInfo45 }, // Inst #251 = ABSDIFS_B_rr_v110
1666
+ { 3, OperandInfo45 }, // Inst #252 = ABSDIFS_H_rr
1667
+ { 3, OperandInfo45 }, // Inst #253 = ABSDIFS_rc
1668
+ { 3, OperandInfo45 }, // Inst #254 = ABSDIFS_rr
1669
+ { 3, OperandInfo45 }, // Inst #255 = ABSDIF_B_rr
1670
+ { 3, OperandInfo45 }, // Inst #256 = ABSDIF_H_rr
1671
+ { 3, OperandInfo46 }, // Inst #257 = ABSDIF_rc
1672
+ { 3, OperandInfo45 }, // Inst #258 = ABSDIF_rr
1673
+ { 3, OperandInfo45 }, // Inst #259 = ABSS_B_rr_v110
1674
+ { 3, OperandInfo45 }, // Inst #260 = ABSS_H_rr
1675
+ { 3, OperandInfo45 }, // Inst #261 = ABSS_rr
1676
+ { 2, OperandInfo47 }, // Inst #262 = ABS_B_rr
1677
+ { 2, OperandInfo47 }, // Inst #263 = ABS_H_rr
1678
+ { 2, OperandInfo47 }, // Inst #264 = ABS_rr
1679
+ { 3, OperandInfo46 }, // Inst #265 = ADDC_rc
1680
+ { 3, OperandInfo45 }, // Inst #266 = ADDC_rr
1681
+ { 3, OperandInfo48 }, // Inst #267 = ADDIH_A_rlc
1682
+ { 3, OperandInfo46 }, // Inst #268 = ADDIH_rlc
1683
+ { 3, OperandInfo46 }, // Inst #269 = ADDI_rlc
1684
+ { 3, OperandInfo49 }, // Inst #270 = ADDSC_AT_rr
1685
+ { 3, OperandInfo50 }, // Inst #271 = ADDSC_AT_rr_v110
1686
+ { 4, OperandInfo51 }, // Inst #272 = ADDSC_A_rr
1687
+ { 4, OperandInfo52 }, // Inst #273 = ADDSC_A_rr_v110
1688
+ { 3, OperandInfo48 }, // Inst #274 = ADDSC_A_srrs
1689
+ { 3, OperandInfo53 }, // Inst #275 = ADDSC_A_srrs_v110
1690
+ { 3, OperandInfo45 }, // Inst #276 = ADDS_BU_rr_v110
1691
+ { 3, OperandInfo45 }, // Inst #277 = ADDS_B_rr
1692
+ { 3, OperandInfo45 }, // Inst #278 = ADDS_H
1693
+ { 3, OperandInfo45 }, // Inst #279 = ADDS_HU
1694
+ { 3, OperandInfo45 }, // Inst #280 = ADDS_U
1695
+ { 3, OperandInfo46 }, // Inst #281 = ADDS_U_rc
1696
+ { 3, OperandInfo46 }, // Inst #282 = ADDS_rc
1697
+ { 3, OperandInfo45 }, // Inst #283 = ADDS_rr
1698
+ { 2, OperandInfo47 }, // Inst #284 = ADDS_srr
1699
+ { 3, OperandInfo46 }, // Inst #285 = ADDX_rc
1700
+ { 3, OperandInfo45 }, // Inst #286 = ADDX_rr
1701
+ { 3, OperandInfo54 }, // Inst #287 = ADD_A_rr
1702
+ { 2, OperandInfo55 }, // Inst #288 = ADD_A_src
1703
+ { 2, OperandInfo56 }, // Inst #289 = ADD_A_srr
1704
+ { 3, OperandInfo45 }, // Inst #290 = ADD_B_rr
1705
+ { 4, OperandInfo57 }, // Inst #291 = ADD_F_rrr
1706
+ { 3, OperandInfo45 }, // Inst #292 = ADD_H_rr
1707
+ { 3, OperandInfo46 }, // Inst #293 = ADD_rc
1708
+ { 3, OperandInfo45 }, // Inst #294 = ADD_rr
1709
+ { 2, OperandInfo58 }, // Inst #295 = ADD_src
1710
+ { 2, OperandInfo58 }, // Inst #296 = ADD_src_15a
1711
+ { 2, OperandInfo58 }, // Inst #297 = ADD_src_a15
1712
+ { 2, OperandInfo47 }, // Inst #298 = ADD_srr
1713
+ { 2, OperandInfo47 }, // Inst #299 = ADD_srr_15a
1714
+ { 2, OperandInfo47 }, // Inst #300 = ADD_srr_a15
1715
+ { 5, OperandInfo59 }, // Inst #301 = ANDN_T
1716
+ { 3, OperandInfo46 }, // Inst #302 = ANDN_rc
1717
+ { 3, OperandInfo45 }, // Inst #303 = ANDN_rr
1718
+ { 5, OperandInfo59 }, // Inst #304 = AND_ANDN_T
1719
+ { 5, OperandInfo59 }, // Inst #305 = AND_AND_T
1720
+ { 3, OperandInfo46 }, // Inst #306 = AND_EQ_rc
1721
+ { 3, OperandInfo45 }, // Inst #307 = AND_EQ_rr
1722
+ { 3, OperandInfo46 }, // Inst #308 = AND_GE_U_rc
1723
+ { 3, OperandInfo45 }, // Inst #309 = AND_GE_U_rr
1724
+ { 3, OperandInfo46 }, // Inst #310 = AND_GE_rc
1725
+ { 3, OperandInfo45 }, // Inst #311 = AND_GE_rr
1726
+ { 3, OperandInfo46 }, // Inst #312 = AND_LT_U_rc
1727
+ { 3, OperandInfo45 }, // Inst #313 = AND_LT_U_rr
1728
+ { 3, OperandInfo46 }, // Inst #314 = AND_LT_rc
1729
+ { 3, OperandInfo45 }, // Inst #315 = AND_LT_rr
1730
+ { 3, OperandInfo46 }, // Inst #316 = AND_NE_rc
1731
+ { 3, OperandInfo45 }, // Inst #317 = AND_NE_rr
1732
+ { 5, OperandInfo59 }, // Inst #318 = AND_NOR_T
1733
+ { 5, OperandInfo59 }, // Inst #319 = AND_OR_T
1734
+ { 5, OperandInfo59 }, // Inst #320 = AND_T
1735
+ { 3, OperandInfo46 }, // Inst #321 = AND_rc
1736
+ { 3, OperandInfo45 }, // Inst #322 = AND_rr
1737
+ { 1, OperandInfo2 }, // Inst #323 = AND_sc
1738
+ { 1, OperandInfo2 }, // Inst #324 = AND_sc_v110
1739
+ { 2, OperandInfo47 }, // Inst #325 = AND_srr
1740
+ { 2, OperandInfo47 }, // Inst #326 = AND_srr_v110
1741
+ { 1, OperandInfo2 }, // Inst #327 = BISR_rc
1742
+ { 1, OperandInfo2 }, // Inst #328 = BISR_rc_v161
1743
+ { 1, OperandInfo2 }, // Inst #329 = BISR_sc
1744
+ { 1, OperandInfo2 }, // Inst #330 = BISR_sc_v110
1745
+ { 3, OperandInfo45 }, // Inst #331 = BMERGAE_rr_v110
1746
+ { 3, OperandInfo45 }, // Inst #332 = BMERGE_rr
1747
+ { 2, OperandInfo60 }, // Inst #333 = BSPLIT_rr
1748
+ { 2, OperandInfo60 }, // Inst #334 = BSPLIT_rr_v110
1749
+ { 2, OperandInfo55 }, // Inst #335 = CACHEA_I_bo_bso
1750
+ { 2, OperandInfo61 }, // Inst #336 = CACHEA_I_bo_c
1751
+ { 2, OperandInfo55 }, // Inst #337 = CACHEA_I_bo_pos
1752
+ { 2, OperandInfo55 }, // Inst #338 = CACHEA_I_bo_pre
1753
+ { 1, OperandInfo62 }, // Inst #339 = CACHEA_I_bo_r
1754
+ { 2, OperandInfo55 }, // Inst #340 = CACHEA_WI_bo_bso
1755
+ { 2, OperandInfo61 }, // Inst #341 = CACHEA_WI_bo_c
1756
+ { 2, OperandInfo55 }, // Inst #342 = CACHEA_WI_bo_pos
1757
+ { 2, OperandInfo55 }, // Inst #343 = CACHEA_WI_bo_pre
1758
+ { 1, OperandInfo62 }, // Inst #344 = CACHEA_WI_bo_r
1759
+ { 2, OperandInfo55 }, // Inst #345 = CACHEA_W_bo_bso
1760
+ { 2, OperandInfo61 }, // Inst #346 = CACHEA_W_bo_c
1761
+ { 2, OperandInfo55 }, // Inst #347 = CACHEA_W_bo_pos
1762
+ { 2, OperandInfo55 }, // Inst #348 = CACHEA_W_bo_pre
1763
+ { 1, OperandInfo62 }, // Inst #349 = CACHEA_W_bo_r
1764
+ { 2, OperandInfo55 }, // Inst #350 = CACHEI_I_bo_bso
1765
+ { 2, OperandInfo55 }, // Inst #351 = CACHEI_I_bo_pos
1766
+ { 2, OperandInfo55 }, // Inst #352 = CACHEI_I_bo_pre
1767
+ { 2, OperandInfo55 }, // Inst #353 = CACHEI_WI_bo_bso
1768
+ { 2, OperandInfo55 }, // Inst #354 = CACHEI_WI_bo_pos
1769
+ { 2, OperandInfo55 }, // Inst #355 = CACHEI_WI_bo_pre
1770
+ { 2, OperandInfo55 }, // Inst #356 = CACHEI_W_bo_bso
1771
+ { 2, OperandInfo55 }, // Inst #357 = CACHEI_W_bo_pos
1772
+ { 2, OperandInfo55 }, // Inst #358 = CACHEI_W_bo_pre
1773
+ { 4, OperandInfo52 }, // Inst #359 = CADDN_A_rcr_v110
1774
+ { 4, OperandInfo63 }, // Inst #360 = CADDN_A_rrr_v110
1775
+ { 4, OperandInfo64 }, // Inst #361 = CADDN_rcr
1776
+ { 4, OperandInfo57 }, // Inst #362 = CADDN_rrr
1777
+ { 2, OperandInfo58 }, // Inst #363 = CADDN_src
1778
+ { 2, OperandInfo47 }, // Inst #364 = CADDN_srr_v110
1779
+ { 4, OperandInfo52 }, // Inst #365 = CADD_A_rcr_v110
1780
+ { 4, OperandInfo63 }, // Inst #366 = CADD_A_rrr_v110
1781
+ { 4, OperandInfo64 }, // Inst #367 = CADD_rcr
1782
+ { 4, OperandInfo57 }, // Inst #368 = CADD_rrr
1783
+ { 2, OperandInfo58 }, // Inst #369 = CADD_src
1784
+ { 2, OperandInfo47 }, // Inst #370 = CADD_srr_v110
1785
+ { 1, OperandInfo2 }, // Inst #371 = CALLA_b
1786
+ { 1, OperandInfo65 }, // Inst #372 = CALLI_rr
1787
+ { 1, OperandInfo65 }, // Inst #373 = CALLI_rr_v110
1788
+ { 1, OperandInfo2 }, // Inst #374 = CALL_b
1789
+ { 1, OperandInfo2 }, // Inst #375 = CALL_sb
1790
+ { 2, OperandInfo47 }, // Inst #376 = CLO_B_rr_v110
1791
+ { 2, OperandInfo47 }, // Inst #377 = CLO_H_rr
1792
+ { 2, OperandInfo47 }, // Inst #378 = CLO_rr
1793
+ { 2, OperandInfo47 }, // Inst #379 = CLS_B_rr_v110
1794
+ { 2, OperandInfo47 }, // Inst #380 = CLS_H_rr
1795
+ { 2, OperandInfo47 }, // Inst #381 = CLS_rr
1796
+ { 2, OperandInfo47 }, // Inst #382 = CLZ_B_rr_v110
1797
+ { 2, OperandInfo47 }, // Inst #383 = CLZ_H_rr
1798
+ { 2, OperandInfo47 }, // Inst #384 = CLZ_rr
1799
+ { 2, OperandInfo58 }, // Inst #385 = CMOVN_src
1800
+ { 2, OperandInfo47 }, // Inst #386 = CMOVN_srr
1801
+ { 2, OperandInfo58 }, // Inst #387 = CMOV_src
1802
+ { 2, OperandInfo47 }, // Inst #388 = CMOV_srr
1803
+ { 3, OperandInfo66 }, // Inst #389 = CMPSWAP_W_bo_bso
1804
+ { 3, OperandInfo67 }, // Inst #390 = CMPSWAP_W_bo_c
1805
+ { 3, OperandInfo66 }, // Inst #391 = CMPSWAP_W_bo_pos
1806
+ { 3, OperandInfo66 }, // Inst #392 = CMPSWAP_W_bo_pre
1807
+ { 2, OperandInfo68 }, // Inst #393 = CMPSWAP_W_bo_r
1808
+ { 3, OperandInfo45 }, // Inst #394 = CMP_F_rr
1809
+ { 3, OperandInfo45 }, // Inst #395 = CRC32B_W_rr
1810
+ { 3, OperandInfo45 }, // Inst #396 = CRC32L_W_rr
1811
+ { 3, OperandInfo45 }, // Inst #397 = CRC32_B_rr
1812
+ { 4, OperandInfo57 }, // Inst #398 = CRCN_rrr
1813
+ { 4, OperandInfo63 }, // Inst #399 = CSUBN_A__rrr_v110
1814
+ { 4, OperandInfo57 }, // Inst #400 = CSUBN_rrr
1815
+ { 4, OperandInfo63 }, // Inst #401 = CSUB_A__rrr_v110
1816
+ { 4, OperandInfo57 }, // Inst #402 = CSUB_rrr
1817
+ { 0, 0 }, // Inst #403 = DEBUG_sr
1818
+ { 0, 0 }, // Inst #404 = DEBUG_sys
1819
+ { 5, OperandInfo69 }, // Inst #405 = DEXTR_rrpw
1820
+ { 4, OperandInfo57 }, // Inst #406 = DEXTR_rrrr
1821
+ { 4, OperandInfo70 }, // Inst #407 = DIFSC_A_rr_v110
1822
+ { 0, 0 }, // Inst #408 = DISABLE_sys
1823
+ { 1, OperandInfo71 }, // Inst #409 = DISABLE_sys_1
1824
+ { 3, OperandInfo45 }, // Inst #410 = DIV_F_rr
1825
+ { 3, OperandInfo72 }, // Inst #411 = DIV_U_rr
1826
+ { 3, OperandInfo72 }, // Inst #412 = DIV_rr
1827
+ { 0, 0 }, // Inst #413 = DSYNC_sys
1828
+ { 4, OperandInfo73 }, // Inst #414 = DVADJ_rrr
1829
+ { 4, OperandInfo73 }, // Inst #415 = DVADJ_rrr_v110
1830
+ { 2, OperandInfo60 }, // Inst #416 = DVADJ_srr_v110
1831
+ { 3, OperandInfo72 }, // Inst #417 = DVINIT_BU_rr
1832
+ { 3, OperandInfo72 }, // Inst #418 = DVINIT_BU_rr_v110
1833
+ { 3, OperandInfo72 }, // Inst #419 = DVINIT_B_rr
1834
+ { 3, OperandInfo72 }, // Inst #420 = DVINIT_B_rr_v110
1835
+ { 3, OperandInfo72 }, // Inst #421 = DVINIT_HU_rr
1836
+ { 3, OperandInfo72 }, // Inst #422 = DVINIT_HU_rr_v110
1837
+ { 3, OperandInfo72 }, // Inst #423 = DVINIT_H_rr
1838
+ { 3, OperandInfo72 }, // Inst #424 = DVINIT_H_rr_v110
1839
+ { 3, OperandInfo72 }, // Inst #425 = DVINIT_U_rr
1840
+ { 3, OperandInfo72 }, // Inst #426 = DVINIT_U_rr_v110
1841
+ { 3, OperandInfo72 }, // Inst #427 = DVINIT_rr
1842
+ { 3, OperandInfo72 }, // Inst #428 = DVINIT_rr_v110
1843
+ { 4, OperandInfo73 }, // Inst #429 = DVSTEP_U_rrr
1844
+ { 4, OperandInfo73 }, // Inst #430 = DVSTEP_U_rrrv110
1845
+ { 2, OperandInfo60 }, // Inst #431 = DVSTEP_Uv110
1846
+ { 4, OperandInfo73 }, // Inst #432 = DVSTEP_rrr
1847
+ { 4, OperandInfo73 }, // Inst #433 = DVSTEP_rrrv110
1848
+ { 2, OperandInfo60 }, // Inst #434 = DVSTEPv110
1849
+ { 0, 0 }, // Inst #435 = ENABLE_sys
1850
+ { 3, OperandInfo46 }, // Inst #436 = EQANY_B_rc
1851
+ { 3, OperandInfo45 }, // Inst #437 = EQANY_B_rr
1852
+ { 3, OperandInfo46 }, // Inst #438 = EQANY_H_rc
1853
+ { 3, OperandInfo45 }, // Inst #439 = EQANY_H_rr
1854
+ { 2, OperandInfo74 }, // Inst #440 = EQZ_A_rr
1855
+ { 3, OperandInfo75 }, // Inst #441 = EQ_A_rr
1856
+ { 3, OperandInfo45 }, // Inst #442 = EQ_B_rr
1857
+ { 3, OperandInfo45 }, // Inst #443 = EQ_H_rr
1858
+ { 3, OperandInfo45 }, // Inst #444 = EQ_W_rr
1859
+ { 3, OperandInfo46 }, // Inst #445 = EQ_rc
1860
+ { 3, OperandInfo45 }, // Inst #446 = EQ_rr
1861
+ { 2, OperandInfo58 }, // Inst #447 = EQ_src
1862
+ { 2, OperandInfo47 }, // Inst #448 = EQ_srr
1863
+ { 5, OperandInfo69 }, // Inst #449 = EXTR_U_rrpw
1864
+ { 3, OperandInfo76 }, // Inst #450 = EXTR_U_rrrr
1865
+ { 5, OperandInfo77 }, // Inst #451 = EXTR_U_rrrw
1866
+ { 5, OperandInfo69 }, // Inst #452 = EXTR_rrpw
1867
+ { 3, OperandInfo76 }, // Inst #453 = EXTR_rrrr
1868
+ { 5, OperandInfo77 }, // Inst #454 = EXTR_rrrw
1869
+ { 1, OperandInfo2 }, // Inst #455 = FCALLA_b
1870
+ { 1, OperandInfo65 }, // Inst #456 = FCALLA_i
1871
+ { 1, OperandInfo2 }, // Inst #457 = FCALL_b
1872
+ { 0, 0 }, // Inst #458 = FRET_sr
1873
+ { 0, 0 }, // Inst #459 = FRET_sys
1874
+ { 2, OperandInfo47 }, // Inst #460 = FTOHP_rr
1875
+ { 2, OperandInfo47 }, // Inst #461 = FTOIZ_rr
1876
+ { 2, OperandInfo47 }, // Inst #462 = FTOI_rr
1877
+ { 3, OperandInfo45 }, // Inst #463 = FTOQ31Z_rr
1878
+ { 3, OperandInfo45 }, // Inst #464 = FTOQ31_rr
1879
+ { 2, OperandInfo47 }, // Inst #465 = FTOUZ_rr
1880
+ { 2, OperandInfo47 }, // Inst #466 = FTOU_rr
1881
+ { 3, OperandInfo75 }, // Inst #467 = GE_A_rr
1882
+ { 3, OperandInfo46 }, // Inst #468 = GE_U_rc
1883
+ { 3, OperandInfo45 }, // Inst #469 = GE_U_rr
1884
+ { 3, OperandInfo46 }, // Inst #470 = GE_rc
1885
+ { 3, OperandInfo45 }, // Inst #471 = GE_rr
1886
+ { 2, OperandInfo47 }, // Inst #472 = HPTOF_rr
1887
+ { 5, OperandInfo78 }, // Inst #473 = IMASK_rcpw
1888
+ { 5, OperandInfo79 }, // Inst #474 = IMASK_rcrw
1889
+ { 5, OperandInfo79 }, // Inst #475 = IMASK_rrpw
1890
+ { 5, OperandInfo80 }, // Inst #476 = IMASK_rrrw
1891
+ { 5, OperandInfo81 }, // Inst #477 = INSERT_rcpw
1892
+ { 4, OperandInfo82 }, // Inst #478 = INSERT_rcrr
1893
+ { 5, OperandInfo69 }, // Inst #479 = INSERT_rcrw
1894
+ { 5, OperandInfo69 }, // Inst #480 = INSERT_rrpw
1895
+ { 4, OperandInfo83 }, // Inst #481 = INSERT_rrrr
1896
+ { 5, OperandInfo77 }, // Inst #482 = INSERT_rrrw
1897
+ { 5, OperandInfo59 }, // Inst #483 = INSN_T
1898
+ { 5, OperandInfo59 }, // Inst #484 = INS_T
1899
+ { 0, 0 }, // Inst #485 = ISYNC_sys
1900
+ { 2, OperandInfo47 }, // Inst #486 = ITOF_rr
1901
+ { 4, OperandInfo73 }, // Inst #487 = IXMAX_U_rrr
1902
+ { 4, OperandInfo73 }, // Inst #488 = IXMAX_rrr
1903
+ { 4, OperandInfo73 }, // Inst #489 = IXMIN_U_rrr
1904
+ { 4, OperandInfo73 }, // Inst #490 = IXMIN_rrr
1905
+ { 1, OperandInfo2 }, // Inst #491 = JA_b
1906
+ { 3, OperandInfo48 }, // Inst #492 = JEQ_A_brr
1907
+ { 3, OperandInfo84 }, // Inst #493 = JEQ_brc
1908
+ { 3, OperandInfo46 }, // Inst #494 = JEQ_brr
1909
+ { 2, OperandInfo7 }, // Inst #495 = JEQ_sbc1
1910
+ { 2, OperandInfo7 }, // Inst #496 = JEQ_sbc2
1911
+ { 2, OperandInfo7 }, // Inst #497 = JEQ_sbc_v110
1912
+ { 2, OperandInfo58 }, // Inst #498 = JEQ_sbr1
1913
+ { 2, OperandInfo58 }, // Inst #499 = JEQ_sbr2
1914
+ { 2, OperandInfo58 }, // Inst #500 = JEQ_sbr_v110
1915
+ { 2, OperandInfo58 }, // Inst #501 = JGEZ_sbr
1916
+ { 2, OperandInfo58 }, // Inst #502 = JGEZ_sbr_v110
1917
+ { 3, OperandInfo84 }, // Inst #503 = JGE_U_brc
1918
+ { 3, OperandInfo46 }, // Inst #504 = JGE_U_brr
1919
+ { 3, OperandInfo84 }, // Inst #505 = JGE_brc
1920
+ { 3, OperandInfo46 }, // Inst #506 = JGE_brr
1921
+ { 2, OperandInfo58 }, // Inst #507 = JGTZ_sbr
1922
+ { 2, OperandInfo58 }, // Inst #508 = JGTZ_sbr_v110
1923
+ { 1, OperandInfo65 }, // Inst #509 = JI_rr
1924
+ { 1, OperandInfo65 }, // Inst #510 = JI_rr_v110
1925
+ { 1, OperandInfo65 }, // Inst #511 = JI_sbr_v110
1926
+ { 1, OperandInfo65 }, // Inst #512 = JI_sr
1927
+ { 1, OperandInfo2 }, // Inst #513 = JLA_b
1928
+ { 2, OperandInfo58 }, // Inst #514 = JLEZ_sbr
1929
+ { 2, OperandInfo58 }, // Inst #515 = JLEZ_sbr_v110
1930
+ { 1, OperandInfo65 }, // Inst #516 = JLI_rr
1931
+ { 1, OperandInfo65 }, // Inst #517 = JLI_rr_v110
1932
+ { 2, OperandInfo58 }, // Inst #518 = JLTZ_sbr
1933
+ { 2, OperandInfo58 }, // Inst #519 = JLTZ_sbr_v110
1934
+ { 3, OperandInfo84 }, // Inst #520 = JLT_U_brc
1935
+ { 3, OperandInfo46 }, // Inst #521 = JLT_U_brr
1936
+ { 3, OperandInfo84 }, // Inst #522 = JLT_brc
1937
+ { 3, OperandInfo46 }, // Inst #523 = JLT_brr
1938
+ { 1, OperandInfo2 }, // Inst #524 = JL_b
1939
+ { 3, OperandInfo84 }, // Inst #525 = JNED_brc
1940
+ { 3, OperandInfo46 }, // Inst #526 = JNED_brr
1941
+ { 3, OperandInfo84 }, // Inst #527 = JNEI_brc
1942
+ { 3, OperandInfo46 }, // Inst #528 = JNEI_brr
1943
+ { 3, OperandInfo48 }, // Inst #529 = JNE_A_brr
1944
+ { 3, OperandInfo84 }, // Inst #530 = JNE_brc
1945
+ { 3, OperandInfo46 }, // Inst #531 = JNE_brr
1946
+ { 2, OperandInfo7 }, // Inst #532 = JNE_sbc1
1947
+ { 2, OperandInfo7 }, // Inst #533 = JNE_sbc2
1948
+ { 2, OperandInfo7 }, // Inst #534 = JNE_sbc_v110
1949
+ { 2, OperandInfo58 }, // Inst #535 = JNE_sbr1
1950
+ { 2, OperandInfo58 }, // Inst #536 = JNE_sbr2
1951
+ { 2, OperandInfo58 }, // Inst #537 = JNE_sbr_v110
1952
+ { 2, OperandInfo55 }, // Inst #538 = JNZ_A_brr
1953
+ { 2, OperandInfo55 }, // Inst #539 = JNZ_A_sbr
1954
+ { 3, OperandInfo85 }, // Inst #540 = JNZ_T_brn
1955
+ { 2, OperandInfo86 }, // Inst #541 = JNZ_T_sbrn
1956
+ { 2, OperandInfo86 }, // Inst #542 = JNZ_T_sbrn_v110
1957
+ { 1, OperandInfo2 }, // Inst #543 = JNZ_sb
1958
+ { 1, OperandInfo2 }, // Inst #544 = JNZ_sb_v110
1959
+ { 2, OperandInfo58 }, // Inst #545 = JNZ_sbr
1960
+ { 2, OperandInfo58 }, // Inst #546 = JNZ_sbr_v110
1961
+ { 2, OperandInfo55 }, // Inst #547 = JZ_A_brr
1962
+ { 2, OperandInfo55 }, // Inst #548 = JZ_A_sbr
1963
+ { 3, OperandInfo85 }, // Inst #549 = JZ_T_brn
1964
+ { 2, OperandInfo86 }, // Inst #550 = JZ_T_sbrn
1965
+ { 2, OperandInfo86 }, // Inst #551 = JZ_T_sbrn_v110
1966
+ { 1, OperandInfo2 }, // Inst #552 = JZ_sb
1967
+ { 1, OperandInfo2 }, // Inst #553 = JZ_sb_v110
1968
+ { 2, OperandInfo58 }, // Inst #554 = JZ_sbr
1969
+ { 2, OperandInfo58 }, // Inst #555 = JZ_sbr_v110
1970
+ { 1, OperandInfo2 }, // Inst #556 = J_b
1971
+ { 1, OperandInfo2 }, // Inst #557 = J_sb
1972
+ { 1, OperandInfo2 }, // Inst #558 = J_sb_v110
1973
+ { 1, OperandInfo2 }, // Inst #559 = LDLCX_abs
1974
+ { 2, OperandInfo55 }, // Inst #560 = LDLCX_bo_bso
1975
+ { 2, OperandInfo87 }, // Inst #561 = LDMST_abs
1976
+ { 3, OperandInfo66 }, // Inst #562 = LDMST_bo_bso
1977
+ { 3, OperandInfo67 }, // Inst #563 = LDMST_bo_c
1978
+ { 3, OperandInfo66 }, // Inst #564 = LDMST_bo_pos
1979
+ { 3, OperandInfo66 }, // Inst #565 = LDMST_bo_pre
1980
+ { 2, OperandInfo68 }, // Inst #566 = LDMST_bo_r
1981
+ { 1, OperandInfo2 }, // Inst #567 = LDUCX_abs
1982
+ { 2, OperandInfo55 }, // Inst #568 = LDUCX_bo_bso
1983
+ { 2, OperandInfo55 }, // Inst #569 = LD_A_abs
1984
+ { 3, OperandInfo48 }, // Inst #570 = LD_A_bo_bso
1985
+ { 3, OperandInfo88 }, // Inst #571 = LD_A_bo_c
1986
+ { 3, OperandInfo48 }, // Inst #572 = LD_A_bo_pos
1987
+ { 3, OperandInfo48 }, // Inst #573 = LD_A_bo_pre
1988
+ { 2, OperandInfo89 }, // Inst #574 = LD_A_bo_r
1989
+ { 3, OperandInfo48 }, // Inst #575 = LD_A_bol
1990
+ { 1, OperandInfo2 }, // Inst #576 = LD_A_sc
1991
+ { 2, OperandInfo56 }, // Inst #577 = LD_A_slr
1992
+ { 2, OperandInfo56 }, // Inst #578 = LD_A_slr_post
1993
+ { 2, OperandInfo56 }, // Inst #579 = LD_A_slr_post_v110
1994
+ { 2, OperandInfo56 }, // Inst #580 = LD_A_slr_v110
1995
+ { 2, OperandInfo55 }, // Inst #581 = LD_A_slro
1996
+ { 2, OperandInfo55 }, // Inst #582 = LD_A_slro_v110
1997
+ { 2, OperandInfo55 }, // Inst #583 = LD_A_sro
1998
+ { 2, OperandInfo55 }, // Inst #584 = LD_A_sro_v110
1999
+ { 2, OperandInfo58 }, // Inst #585 = LD_BU_abs
2000
+ { 3, OperandInfo90 }, // Inst #586 = LD_BU_bo_bso
2001
+ { 3, OperandInfo91 }, // Inst #587 = LD_BU_bo_c
2002
+ { 3, OperandInfo90 }, // Inst #588 = LD_BU_bo_pos
2003
+ { 3, OperandInfo90 }, // Inst #589 = LD_BU_bo_pre
2004
+ { 2, OperandInfo92 }, // Inst #590 = LD_BU_bo_r
2005
+ { 3, OperandInfo90 }, // Inst #591 = LD_BU_bol
2006
+ { 2, OperandInfo74 }, // Inst #592 = LD_BU_slr
2007
+ { 2, OperandInfo74 }, // Inst #593 = LD_BU_slr_post
2008
+ { 2, OperandInfo74 }, // Inst #594 = LD_BU_slr_post_v110
2009
+ { 2, OperandInfo74 }, // Inst #595 = LD_BU_slr_v110
2010
+ { 2, OperandInfo58 }, // Inst #596 = LD_BU_slro
2011
+ { 2, OperandInfo58 }, // Inst #597 = LD_BU_slro_v110
2012
+ { 2, OperandInfo55 }, // Inst #598 = LD_BU_sro
2013
+ { 2, OperandInfo55 }, // Inst #599 = LD_BU_sro_v110
2014
+ { 2, OperandInfo58 }, // Inst #600 = LD_B_abs
2015
+ { 3, OperandInfo90 }, // Inst #601 = LD_B_bo_bso
2016
+ { 3, OperandInfo91 }, // Inst #602 = LD_B_bo_c
2017
+ { 3, OperandInfo90 }, // Inst #603 = LD_B_bo_pos
2018
+ { 3, OperandInfo90 }, // Inst #604 = LD_B_bo_pre
2019
+ { 2, OperandInfo92 }, // Inst #605 = LD_B_bo_r
2020
+ { 3, OperandInfo90 }, // Inst #606 = LD_B_bol
2021
+ { 2, OperandInfo74 }, // Inst #607 = LD_B_slr_post_v110
2022
+ { 2, OperandInfo74 }, // Inst #608 = LD_B_slr_v110
2023
+ { 2, OperandInfo58 }, // Inst #609 = LD_B_slro_v110
2024
+ { 2, OperandInfo55 }, // Inst #610 = LD_B_sro_v110
2025
+ { 2, OperandInfo61 }, // Inst #611 = LD_DA_abs
2026
+ { 3, OperandInfo93 }, // Inst #612 = LD_DA_bo_bso
2027
+ { 3, OperandInfo94 }, // Inst #613 = LD_DA_bo_c
2028
+ { 3, OperandInfo93 }, // Inst #614 = LD_DA_bo_pos
2029
+ { 3, OperandInfo93 }, // Inst #615 = LD_DA_bo_pre
2030
+ { 2, OperandInfo95 }, // Inst #616 = LD_DA_bo_r
2031
+ { 2, OperandInfo87 }, // Inst #617 = LD_D_abs
2032
+ { 3, OperandInfo66 }, // Inst #618 = LD_D_bo_bso
2033
+ { 3, OperandInfo67 }, // Inst #619 = LD_D_bo_c
2034
+ { 3, OperandInfo66 }, // Inst #620 = LD_D_bo_pos
2035
+ { 3, OperandInfo66 }, // Inst #621 = LD_D_bo_pre
2036
+ { 2, OperandInfo68 }, // Inst #622 = LD_D_bo_r
2037
+ { 2, OperandInfo58 }, // Inst #623 = LD_HU_abs
2038
+ { 3, OperandInfo90 }, // Inst #624 = LD_HU_bo_bso
2039
+ { 3, OperandInfo91 }, // Inst #625 = LD_HU_bo_c
2040
+ { 3, OperandInfo90 }, // Inst #626 = LD_HU_bo_pos
2041
+ { 3, OperandInfo90 }, // Inst #627 = LD_HU_bo_pre
2042
+ { 2, OperandInfo92 }, // Inst #628 = LD_HU_bo_r
2043
+ { 3, OperandInfo90 }, // Inst #629 = LD_HU_bol
2044
+ { 2, OperandInfo58 }, // Inst #630 = LD_H_abs
2045
+ { 3, OperandInfo90 }, // Inst #631 = LD_H_bo_bso
2046
+ { 3, OperandInfo91 }, // Inst #632 = LD_H_bo_c
2047
+ { 3, OperandInfo90 }, // Inst #633 = LD_H_bo_pos
2048
+ { 3, OperandInfo90 }, // Inst #634 = LD_H_bo_pre
2049
+ { 2, OperandInfo92 }, // Inst #635 = LD_H_bo_r
2050
+ { 3, OperandInfo90 }, // Inst #636 = LD_H_bol
2051
+ { 2, OperandInfo74 }, // Inst #637 = LD_H_slr
2052
+ { 2, OperandInfo74 }, // Inst #638 = LD_H_slr_post
2053
+ { 2, OperandInfo74 }, // Inst #639 = LD_H_slr_post_v110
2054
+ { 2, OperandInfo74 }, // Inst #640 = LD_H_slr_v110
2055
+ { 2, OperandInfo58 }, // Inst #641 = LD_H_slro
2056
+ { 2, OperandInfo58 }, // Inst #642 = LD_H_slro_v110
2057
+ { 2, OperandInfo55 }, // Inst #643 = LD_H_sro
2058
+ { 2, OperandInfo55 }, // Inst #644 = LD_H_sro_v110
2059
+ { 2, OperandInfo58 }, // Inst #645 = LD_Q_abs
2060
+ { 3, OperandInfo90 }, // Inst #646 = LD_Q_bo_bso
2061
+ { 3, OperandInfo91 }, // Inst #647 = LD_Q_bo_c
2062
+ { 3, OperandInfo90 }, // Inst #648 = LD_Q_bo_pos
2063
+ { 3, OperandInfo90 }, // Inst #649 = LD_Q_bo_pre
2064
+ { 2, OperandInfo92 }, // Inst #650 = LD_Q_bo_r
2065
+ { 2, OperandInfo58 }, // Inst #651 = LD_W_abs
2066
+ { 3, OperandInfo90 }, // Inst #652 = LD_W_bo_bso
2067
+ { 3, OperandInfo91 }, // Inst #653 = LD_W_bo_c
2068
+ { 3, OperandInfo90 }, // Inst #654 = LD_W_bo_pos
2069
+ { 3, OperandInfo90 }, // Inst #655 = LD_W_bo_pre
2070
+ { 2, OperandInfo92 }, // Inst #656 = LD_W_bo_r
2071
+ { 3, OperandInfo90 }, // Inst #657 = LD_W_bol
2072
+ { 1, OperandInfo2 }, // Inst #658 = LD_W_sc
2073
+ { 2, OperandInfo74 }, // Inst #659 = LD_W_slr
2074
+ { 2, OperandInfo74 }, // Inst #660 = LD_W_slr_post
2075
+ { 2, OperandInfo74 }, // Inst #661 = LD_W_slr_post_v110
2076
+ { 2, OperandInfo74 }, // Inst #662 = LD_W_slr_v110
2077
+ { 2, OperandInfo58 }, // Inst #663 = LD_W_slro
2078
+ { 2, OperandInfo58 }, // Inst #664 = LD_W_slro_v110
2079
+ { 2, OperandInfo55 }, // Inst #665 = LD_W_sro
2080
+ { 2, OperandInfo55 }, // Inst #666 = LD_W_sro_v110
2081
+ { 2, OperandInfo55 }, // Inst #667 = LEA_abs
2082
+ { 3, OperandInfo48 }, // Inst #668 = LEA_bo_bso
2083
+ { 3, OperandInfo48 }, // Inst #669 = LEA_bol
2084
+ { 2, OperandInfo55 }, // Inst #670 = LHA_abs
2085
+ { 1, OperandInfo2 }, // Inst #671 = LOOPU_brr
2086
+ { 2, OperandInfo55 }, // Inst #672 = LOOP_brr
2087
+ { 2, OperandInfo55 }, // Inst #673 = LOOP_sbr
2088
+ { 3, OperandInfo75 }, // Inst #674 = LT_A_rr
2089
+ { 3, OperandInfo45 }, // Inst #675 = LT_B
2090
+ { 3, OperandInfo45 }, // Inst #676 = LT_BU
2091
+ { 3, OperandInfo45 }, // Inst #677 = LT_H
2092
+ { 3, OperandInfo45 }, // Inst #678 = LT_HU
2093
+ { 3, OperandInfo46 }, // Inst #679 = LT_U_rc
2094
+ { 3, OperandInfo45 }, // Inst #680 = LT_U_rr
2095
+ { 2, OperandInfo58 }, // Inst #681 = LT_U_srcv110
2096
+ { 2, OperandInfo47 }, // Inst #682 = LT_U_srrv110
2097
+ { 3, OperandInfo45 }, // Inst #683 = LT_W
2098
+ { 3, OperandInfo45 }, // Inst #684 = LT_WU
2099
+ { 3, OperandInfo46 }, // Inst #685 = LT_rc
2100
+ { 3, OperandInfo45 }, // Inst #686 = LT_rr
2101
+ { 2, OperandInfo58 }, // Inst #687 = LT_src
2102
+ { 2, OperandInfo47 }, // Inst #688 = LT_srr
2103
+ { 5, OperandInfo96 }, // Inst #689 = MADDMS_H_rrr1_LL
2104
+ { 5, OperandInfo96 }, // Inst #690 = MADDMS_H_rrr1_LU
2105
+ { 5, OperandInfo96 }, // Inst #691 = MADDMS_H_rrr1_UL
2106
+ { 5, OperandInfo96 }, // Inst #692 = MADDMS_H_rrr1_UU
2107
+ { 4, OperandInfo97 }, // Inst #693 = MADDMS_U_rcr_v110
2108
+ { 4, OperandInfo73 }, // Inst #694 = MADDMS_U_rrr2_v110
2109
+ { 4, OperandInfo97 }, // Inst #695 = MADDMS_rcr_v110
2110
+ { 4, OperandInfo73 }, // Inst #696 = MADDMS_rrr2_v110
2111
+ { 5, OperandInfo96 }, // Inst #697 = MADDM_H_rrr1_LL
2112
+ { 5, OperandInfo96 }, // Inst #698 = MADDM_H_rrr1_LU
2113
+ { 5, OperandInfo96 }, // Inst #699 = MADDM_H_rrr1_UL
2114
+ { 5, OperandInfo96 }, // Inst #700 = MADDM_H_rrr1_UU
2115
+ { 5, OperandInfo96 }, // Inst #701 = MADDM_H_rrr1_v110
2116
+ { 5, OperandInfo96 }, // Inst #702 = MADDM_Q_rrr1_v110
2117
+ { 4, OperandInfo97 }, // Inst #703 = MADDM_U_rcr_v110
2118
+ { 4, OperandInfo73 }, // Inst #704 = MADDM_U_rrr2_v110
2119
+ { 4, OperandInfo97 }, // Inst #705 = MADDM_rcr_v110
2120
+ { 4, OperandInfo73 }, // Inst #706 = MADDM_rrr2_v110
2121
+ { 5, OperandInfo98 }, // Inst #707 = MADDRS_H_rrr1_LL
2122
+ { 5, OperandInfo98 }, // Inst #708 = MADDRS_H_rrr1_LU
2123
+ { 5, OperandInfo98 }, // Inst #709 = MADDRS_H_rrr1_UL
2124
+ { 5, OperandInfo99 }, // Inst #710 = MADDRS_H_rrr1_UL_2
2125
+ { 5, OperandInfo98 }, // Inst #711 = MADDRS_H_rrr1_UU
2126
+ { 5, OperandInfo99 }, // Inst #712 = MADDRS_H_rrr1_v110
2127
+ { 5, OperandInfo98 }, // Inst #713 = MADDRS_Q_rrr1_L_L
2128
+ { 5, OperandInfo98 }, // Inst #714 = MADDRS_Q_rrr1_U_U
2129
+ { 5, OperandInfo98 }, // Inst #715 = MADDRS_Q_rrr1_v110
2130
+ { 5, OperandInfo98 }, // Inst #716 = MADDR_H_rrr1_LL
2131
+ { 5, OperandInfo98 }, // Inst #717 = MADDR_H_rrr1_LU
2132
+ { 5, OperandInfo98 }, // Inst #718 = MADDR_H_rrr1_UL
2133
+ { 5, OperandInfo99 }, // Inst #719 = MADDR_H_rrr1_UL_2
2134
+ { 5, OperandInfo98 }, // Inst #720 = MADDR_H_rrr1_UU
2135
+ { 5, OperandInfo99 }, // Inst #721 = MADDR_H_rrr1_v110
2136
+ { 5, OperandInfo98 }, // Inst #722 = MADDR_Q_rrr1_L_L
2137
+ { 5, OperandInfo98 }, // Inst #723 = MADDR_Q_rrr1_U_U
2138
+ { 5, OperandInfo98 }, // Inst #724 = MADDR_Q_rrr1_v110
2139
+ { 5, OperandInfo96 }, // Inst #725 = MADDSUMS_H_rrr1_LL
2140
+ { 5, OperandInfo96 }, // Inst #726 = MADDSUMS_H_rrr1_LU
2141
+ { 5, OperandInfo96 }, // Inst #727 = MADDSUMS_H_rrr1_UL
2142
+ { 5, OperandInfo96 }, // Inst #728 = MADDSUMS_H_rrr1_UU
2143
+ { 5, OperandInfo96 }, // Inst #729 = MADDSUM_H_rrr1_LL
2144
+ { 5, OperandInfo96 }, // Inst #730 = MADDSUM_H_rrr1_LU
2145
+ { 5, OperandInfo96 }, // Inst #731 = MADDSUM_H_rrr1_UL
2146
+ { 5, OperandInfo96 }, // Inst #732 = MADDSUM_H_rrr1_UU
2147
+ { 5, OperandInfo98 }, // Inst #733 = MADDSURS_H_rrr1_LL
2148
+ { 5, OperandInfo98 }, // Inst #734 = MADDSURS_H_rrr1_LU
2149
+ { 5, OperandInfo98 }, // Inst #735 = MADDSURS_H_rrr1_UL
2150
+ { 5, OperandInfo98 }, // Inst #736 = MADDSURS_H_rrr1_UU
2151
+ { 5, OperandInfo98 }, // Inst #737 = MADDSUR_H_rrr1_LL
2152
+ { 5, OperandInfo98 }, // Inst #738 = MADDSUR_H_rrr1_LU
2153
+ { 5, OperandInfo98 }, // Inst #739 = MADDSUR_H_rrr1_UL
2154
+ { 5, OperandInfo98 }, // Inst #740 = MADDSUR_H_rrr1_UU
2155
+ { 5, OperandInfo96 }, // Inst #741 = MADDSUS_H_rrr1_LL
2156
+ { 5, OperandInfo96 }, // Inst #742 = MADDSUS_H_rrr1_LU
2157
+ { 5, OperandInfo96 }, // Inst #743 = MADDSUS_H_rrr1_UL
2158
+ { 5, OperandInfo96 }, // Inst #744 = MADDSUS_H_rrr1_UU
2159
+ { 5, OperandInfo96 }, // Inst #745 = MADDSU_H_rrr1_LL
2160
+ { 5, OperandInfo96 }, // Inst #746 = MADDSU_H_rrr1_LU
2161
+ { 5, OperandInfo96 }, // Inst #747 = MADDSU_H_rrr1_UL
2162
+ { 5, OperandInfo96 }, // Inst #748 = MADDSU_H_rrr1_UU
2163
+ { 5, OperandInfo96 }, // Inst #749 = MADDS_H_rrr1_LL
2164
+ { 5, OperandInfo96 }, // Inst #750 = MADDS_H_rrr1_LU
2165
+ { 5, OperandInfo96 }, // Inst #751 = MADDS_H_rrr1_UL
2166
+ { 5, OperandInfo96 }, // Inst #752 = MADDS_H_rrr1_UU
2167
+ { 5, OperandInfo96 }, // Inst #753 = MADDS_H_rrr1_v110
2168
+ { 5, OperandInfo98 }, // Inst #754 = MADDS_Q_rrr1
2169
+ { 5, OperandInfo98 }, // Inst #755 = MADDS_Q_rrr1_L
2170
+ { 5, OperandInfo98 }, // Inst #756 = MADDS_Q_rrr1_L_L
2171
+ { 5, OperandInfo98 }, // Inst #757 = MADDS_Q_rrr1_U
2172
+ { 5, OperandInfo98 }, // Inst #758 = MADDS_Q_rrr1_UU2_v110
2173
+ { 5, OperandInfo98 }, // Inst #759 = MADDS_Q_rrr1_U_U
2174
+ { 5, OperandInfo96 }, // Inst #760 = MADDS_Q_rrr1_e
2175
+ { 5, OperandInfo96 }, // Inst #761 = MADDS_Q_rrr1_e_L
2176
+ { 5, OperandInfo96 }, // Inst #762 = MADDS_Q_rrr1_e_L_L
2177
+ { 5, OperandInfo96 }, // Inst #763 = MADDS_Q_rrr1_e_U
2178
+ { 5, OperandInfo96 }, // Inst #764 = MADDS_Q_rrr1_e_U_U
2179
+ { 4, OperandInfo64 }, // Inst #765 = MADDS_U_rcr
2180
+ { 4, OperandInfo97 }, // Inst #766 = MADDS_U_rcr_e
2181
+ { 4, OperandInfo57 }, // Inst #767 = MADDS_U_rrr2
2182
+ { 4, OperandInfo73 }, // Inst #768 = MADDS_U_rrr2_e
2183
+ { 4, OperandInfo64 }, // Inst #769 = MADDS_rcr
2184
+ { 4, OperandInfo97 }, // Inst #770 = MADDS_rcr_e
2185
+ { 4, OperandInfo57 }, // Inst #771 = MADDS_rrr2
2186
+ { 4, OperandInfo73 }, // Inst #772 = MADDS_rrr2_e
2187
+ { 4, OperandInfo57 }, // Inst #773 = MADD_F_rrr
2188
+ { 5, OperandInfo96 }, // Inst #774 = MADD_H_rrr1_LL
2189
+ { 5, OperandInfo96 }, // Inst #775 = MADD_H_rrr1_LU
2190
+ { 5, OperandInfo96 }, // Inst #776 = MADD_H_rrr1_UL
2191
+ { 5, OperandInfo96 }, // Inst #777 = MADD_H_rrr1_UU
2192
+ { 5, OperandInfo96 }, // Inst #778 = MADD_H_rrr1_v110
2193
+ { 5, OperandInfo98 }, // Inst #779 = MADD_Q_rrr1
2194
+ { 5, OperandInfo98 }, // Inst #780 = MADD_Q_rrr1_L
2195
+ { 5, OperandInfo98 }, // Inst #781 = MADD_Q_rrr1_L_L
2196
+ { 5, OperandInfo98 }, // Inst #782 = MADD_Q_rrr1_U
2197
+ { 5, OperandInfo98 }, // Inst #783 = MADD_Q_rrr1_UU2_v110
2198
+ { 5, OperandInfo98 }, // Inst #784 = MADD_Q_rrr1_U_U
2199
+ { 5, OperandInfo96 }, // Inst #785 = MADD_Q_rrr1_e
2200
+ { 5, OperandInfo96 }, // Inst #786 = MADD_Q_rrr1_e_L
2201
+ { 5, OperandInfo96 }, // Inst #787 = MADD_Q_rrr1_e_L_L
2202
+ { 5, OperandInfo96 }, // Inst #788 = MADD_Q_rrr1_e_U
2203
+ { 5, OperandInfo96 }, // Inst #789 = MADD_Q_rrr1_e_U_U
2204
+ { 4, OperandInfo97 }, // Inst #790 = MADD_U_rcr
2205
+ { 4, OperandInfo73 }, // Inst #791 = MADD_U_rrr2
2206
+ { 4, OperandInfo64 }, // Inst #792 = MADD_rcr
2207
+ { 4, OperandInfo97 }, // Inst #793 = MADD_rcr_e
2208
+ { 4, OperandInfo57 }, // Inst #794 = MADD_rrr2
2209
+ { 4, OperandInfo73 }, // Inst #795 = MADD_rrr2_e
2210
+ { 3, OperandInfo45 }, // Inst #796 = MAX_B
2211
+ { 3, OperandInfo45 }, // Inst #797 = MAX_BU
2212
+ { 3, OperandInfo45 }, // Inst #798 = MAX_H
2213
+ { 3, OperandInfo45 }, // Inst #799 = MAX_HU
2214
+ { 3, OperandInfo46 }, // Inst #800 = MAX_U_rc
2215
+ { 3, OperandInfo45 }, // Inst #801 = MAX_U_rr
2216
+ { 3, OperandInfo46 }, // Inst #802 = MAX_rc
2217
+ { 3, OperandInfo45 }, // Inst #803 = MAX_rr
2218
+ { 2, OperandInfo58 }, // Inst #804 = MFCR_rlc
2219
+ { 3, OperandInfo45 }, // Inst #805 = MIN_B
2220
+ { 3, OperandInfo45 }, // Inst #806 = MIN_BU
2221
+ { 3, OperandInfo45 }, // Inst #807 = MIN_H
2222
+ { 3, OperandInfo45 }, // Inst #808 = MIN_HU
2223
+ { 3, OperandInfo46 }, // Inst #809 = MIN_U_rc
2224
+ { 3, OperandInfo45 }, // Inst #810 = MIN_U_rr
2225
+ { 3, OperandInfo46 }, // Inst #811 = MIN_rc
2226
+ { 3, OperandInfo45 }, // Inst #812 = MIN_rr
2227
+ { 2, OperandInfo55 }, // Inst #813 = MOVH_A_rlc
2228
+ { 2, OperandInfo58 }, // Inst #814 = MOVH_rlc
2229
+ { 1, OperandInfo65 }, // Inst #815 = MOVZ_A_sr
2230
+ { 3, OperandInfo54 }, // Inst #816 = MOV_AA_rr
2231
+ { 2, OperandInfo56 }, // Inst #817 = MOV_AA_srr_srr
2232
+ { 2, OperandInfo56 }, // Inst #818 = MOV_AA_srr_srr_v110
2233
+ { 3, OperandInfo100 }, // Inst #819 = MOV_A_rr
2234
+ { 2, OperandInfo55 }, // Inst #820 = MOV_A_src
2235
+ { 2, OperandInfo101 }, // Inst #821 = MOV_A_srr
2236
+ { 2, OperandInfo101 }, // Inst #822 = MOV_A_srr_v110
2237
+ { 3, OperandInfo75 }, // Inst #823 = MOV_D_rr
2238
+ { 2, OperandInfo74 }, // Inst #824 = MOV_D_srr_srr
2239
+ { 2, OperandInfo74 }, // Inst #825 = MOV_D_srr_srr_v110
2240
+ { 2, OperandInfo58 }, // Inst #826 = MOV_U_rlc
2241
+ { 2, OperandInfo58 }, // Inst #827 = MOV_rlc
2242
+ { 2, OperandInfo87 }, // Inst #828 = MOV_rlc_e
2243
+ { 3, OperandInfo45 }, // Inst #829 = MOV_rr
2244
+ { 3, OperandInfo72 }, // Inst #830 = MOV_rr_e
2245
+ { 3, OperandInfo72 }, // Inst #831 = MOV_rr_eab
2246
+ { 1, OperandInfo2 }, // Inst #832 = MOV_sc
2247
+ { 1, OperandInfo2 }, // Inst #833 = MOV_sc_v110
2248
+ { 2, OperandInfo58 }, // Inst #834 = MOV_src
2249
+ { 2, OperandInfo87 }, // Inst #835 = MOV_src_e
2250
+ { 2, OperandInfo47 }, // Inst #836 = MOV_srr
2251
+ { 5, OperandInfo96 }, // Inst #837 = MSUBADMS_H_rrr1_LL
2252
+ { 5, OperandInfo96 }, // Inst #838 = MSUBADMS_H_rrr1_LU
2253
+ { 5, OperandInfo96 }, // Inst #839 = MSUBADMS_H_rrr1_UL
2254
+ { 5, OperandInfo96 }, // Inst #840 = MSUBADMS_H_rrr1_UU
2255
+ { 5, OperandInfo96 }, // Inst #841 = MSUBADM_H_rrr1_LL
2256
+ { 5, OperandInfo96 }, // Inst #842 = MSUBADM_H_rrr1_LU
2257
+ { 5, OperandInfo96 }, // Inst #843 = MSUBADM_H_rrr1_UL
2258
+ { 5, OperandInfo96 }, // Inst #844 = MSUBADM_H_rrr1_UU
2259
+ { 5, OperandInfo98 }, // Inst #845 = MSUBADRS_H_rrr1_LL
2260
+ { 5, OperandInfo98 }, // Inst #846 = MSUBADRS_H_rrr1_LU
2261
+ { 5, OperandInfo98 }, // Inst #847 = MSUBADRS_H_rrr1_UL
2262
+ { 5, OperandInfo98 }, // Inst #848 = MSUBADRS_H_rrr1_UU
2263
+ { 5, OperandInfo98 }, // Inst #849 = MSUBADRS_H_rrr1_v110
2264
+ { 5, OperandInfo98 }, // Inst #850 = MSUBADR_H_rrr1_LL
2265
+ { 5, OperandInfo98 }, // Inst #851 = MSUBADR_H_rrr1_LU
2266
+ { 5, OperandInfo98 }, // Inst #852 = MSUBADR_H_rrr1_UL
2267
+ { 5, OperandInfo98 }, // Inst #853 = MSUBADR_H_rrr1_UU
2268
+ { 5, OperandInfo98 }, // Inst #854 = MSUBADR_H_rrr1_v110
2269
+ { 5, OperandInfo96 }, // Inst #855 = MSUBADS_H_rrr1_LL
2270
+ { 5, OperandInfo96 }, // Inst #856 = MSUBADS_H_rrr1_LU
2271
+ { 5, OperandInfo96 }, // Inst #857 = MSUBADS_H_rrr1_UL
2272
+ { 5, OperandInfo96 }, // Inst #858 = MSUBADS_H_rrr1_UU
2273
+ { 5, OperandInfo96 }, // Inst #859 = MSUBAD_H_rrr1_LL
2274
+ { 5, OperandInfo96 }, // Inst #860 = MSUBAD_H_rrr1_LU
2275
+ { 5, OperandInfo96 }, // Inst #861 = MSUBAD_H_rrr1_UL
2276
+ { 5, OperandInfo96 }, // Inst #862 = MSUBAD_H_rrr1_UU
2277
+ { 5, OperandInfo96 }, // Inst #863 = MSUBMS_H_rrr1_LL
2278
+ { 5, OperandInfo96 }, // Inst #864 = MSUBMS_H_rrr1_LU
2279
+ { 5, OperandInfo96 }, // Inst #865 = MSUBMS_H_rrr1_UL
2280
+ { 5, OperandInfo96 }, // Inst #866 = MSUBMS_H_rrr1_UU
2281
+ { 4, OperandInfo97 }, // Inst #867 = MSUBMS_U_rcrv110
2282
+ { 4, OperandInfo73 }, // Inst #868 = MSUBMS_U_rrr2v110
2283
+ { 4, OperandInfo97 }, // Inst #869 = MSUBMS_rcrv110
2284
+ { 4, OperandInfo73 }, // Inst #870 = MSUBMS_rrr2v110
2285
+ { 5, OperandInfo96 }, // Inst #871 = MSUBM_H_rrr1_LL
2286
+ { 5, OperandInfo96 }, // Inst #872 = MSUBM_H_rrr1_LU
2287
+ { 5, OperandInfo96 }, // Inst #873 = MSUBM_H_rrr1_UL
2288
+ { 5, OperandInfo96 }, // Inst #874 = MSUBM_H_rrr1_UU
2289
+ { 5, OperandInfo96 }, // Inst #875 = MSUBM_H_rrr1_v110
2290
+ { 5, OperandInfo96 }, // Inst #876 = MSUBM_Q_rrr1_v110
2291
+ { 4, OperandInfo97 }, // Inst #877 = MSUBM_U_rcrv110
2292
+ { 4, OperandInfo73 }, // Inst #878 = MSUBM_U_rrr2v110
2293
+ { 4, OperandInfo97 }, // Inst #879 = MSUBM_rcrv110
2294
+ { 4, OperandInfo73 }, // Inst #880 = MSUBM_rrr2v110
2295
+ { 5, OperandInfo98 }, // Inst #881 = MSUBRS_H_rrr1_LL
2296
+ { 5, OperandInfo98 }, // Inst #882 = MSUBRS_H_rrr1_LU
2297
+ { 5, OperandInfo98 }, // Inst #883 = MSUBRS_H_rrr1_UL
2298
+ { 5, OperandInfo99 }, // Inst #884 = MSUBRS_H_rrr1_UL_2
2299
+ { 5, OperandInfo98 }, // Inst #885 = MSUBRS_H_rrr1_UU
2300
+ { 5, OperandInfo99 }, // Inst #886 = MSUBRS_H_rrr1_v110
2301
+ { 5, OperandInfo98 }, // Inst #887 = MSUBRS_Q_rrr1_L_L
2302
+ { 5, OperandInfo98 }, // Inst #888 = MSUBRS_Q_rrr1_U_U
2303
+ { 5, OperandInfo98 }, // Inst #889 = MSUBRS_Q_rrr1_v110
2304
+ { 5, OperandInfo98 }, // Inst #890 = MSUBR_H_rrr1_LL
2305
+ { 5, OperandInfo98 }, // Inst #891 = MSUBR_H_rrr1_LU
2306
+ { 5, OperandInfo98 }, // Inst #892 = MSUBR_H_rrr1_UL
2307
+ { 5, OperandInfo99 }, // Inst #893 = MSUBR_H_rrr1_UL_2
2308
+ { 5, OperandInfo98 }, // Inst #894 = MSUBR_H_rrr1_UU
2309
+ { 5, OperandInfo99 }, // Inst #895 = MSUBR_H_rrr1_v110
2310
+ { 5, OperandInfo98 }, // Inst #896 = MSUBR_Q_rrr1_L_L
2311
+ { 5, OperandInfo98 }, // Inst #897 = MSUBR_Q_rrr1_U_U
2312
+ { 5, OperandInfo98 }, // Inst #898 = MSUBR_Q_rrr1_v110
2313
+ { 5, OperandInfo96 }, // Inst #899 = MSUBS_H_rrr1_LL
2314
+ { 5, OperandInfo96 }, // Inst #900 = MSUBS_H_rrr1_LU
2315
+ { 5, OperandInfo96 }, // Inst #901 = MSUBS_H_rrr1_UL
2316
+ { 5, OperandInfo96 }, // Inst #902 = MSUBS_H_rrr1_UU
2317
+ { 5, OperandInfo96 }, // Inst #903 = MSUBS_H_rrr1_v110
2318
+ { 5, OperandInfo98 }, // Inst #904 = MSUBS_Q_rrr1
2319
+ { 5, OperandInfo98 }, // Inst #905 = MSUBS_Q_rrr1_L
2320
+ { 5, OperandInfo98 }, // Inst #906 = MSUBS_Q_rrr1_L_L
2321
+ { 5, OperandInfo98 }, // Inst #907 = MSUBS_Q_rrr1_U
2322
+ { 5, OperandInfo98 }, // Inst #908 = MSUBS_Q_rrr1_UU2_v110
2323
+ { 5, OperandInfo98 }, // Inst #909 = MSUBS_Q_rrr1_U_U
2324
+ { 5, OperandInfo96 }, // Inst #910 = MSUBS_Q_rrr1_e
2325
+ { 5, OperandInfo96 }, // Inst #911 = MSUBS_Q_rrr1_e_L
2326
+ { 5, OperandInfo96 }, // Inst #912 = MSUBS_Q_rrr1_e_L_L
2327
+ { 5, OperandInfo96 }, // Inst #913 = MSUBS_Q_rrr1_e_U
2328
+ { 5, OperandInfo96 }, // Inst #914 = MSUBS_Q_rrr1_e_U_U
2329
+ { 4, OperandInfo64 }, // Inst #915 = MSUBS_U_rcr
2330
+ { 4, OperandInfo97 }, // Inst #916 = MSUBS_U_rcr_e
2331
+ { 4, OperandInfo57 }, // Inst #917 = MSUBS_U_rrr2
2332
+ { 4, OperandInfo73 }, // Inst #918 = MSUBS_U_rrr2_e
2333
+ { 4, OperandInfo64 }, // Inst #919 = MSUBS_rcr
2334
+ { 4, OperandInfo97 }, // Inst #920 = MSUBS_rcr_e
2335
+ { 4, OperandInfo57 }, // Inst #921 = MSUBS_rrr2
2336
+ { 4, OperandInfo73 }, // Inst #922 = MSUBS_rrr2_e
2337
+ { 4, OperandInfo57 }, // Inst #923 = MSUB_F_rrr
2338
+ { 5, OperandInfo96 }, // Inst #924 = MSUB_H_rrr1_LL
2339
+ { 5, OperandInfo96 }, // Inst #925 = MSUB_H_rrr1_LU
2340
+ { 5, OperandInfo96 }, // Inst #926 = MSUB_H_rrr1_UL
2341
+ { 5, OperandInfo96 }, // Inst #927 = MSUB_H_rrr1_UU
2342
+ { 5, OperandInfo96 }, // Inst #928 = MSUB_H_rrr1_v110
2343
+ { 5, OperandInfo98 }, // Inst #929 = MSUB_Q_rrr1
2344
+ { 5, OperandInfo98 }, // Inst #930 = MSUB_Q_rrr1_L
2345
+ { 5, OperandInfo98 }, // Inst #931 = MSUB_Q_rrr1_L_L
2346
+ { 5, OperandInfo98 }, // Inst #932 = MSUB_Q_rrr1_U
2347
+ { 5, OperandInfo98 }, // Inst #933 = MSUB_Q_rrr1_UU2_v110
2348
+ { 5, OperandInfo98 }, // Inst #934 = MSUB_Q_rrr1_U_U
2349
+ { 5, OperandInfo96 }, // Inst #935 = MSUB_Q_rrr1_e
2350
+ { 5, OperandInfo96 }, // Inst #936 = MSUB_Q_rrr1_e_L
2351
+ { 5, OperandInfo96 }, // Inst #937 = MSUB_Q_rrr1_e_L_L
2352
+ { 5, OperandInfo96 }, // Inst #938 = MSUB_Q_rrr1_e_U
2353
+ { 5, OperandInfo96 }, // Inst #939 = MSUB_Q_rrr1_e_U_U
2354
+ { 4, OperandInfo97 }, // Inst #940 = MSUB_U_rcr
2355
+ { 4, OperandInfo73 }, // Inst #941 = MSUB_U_rrr2
2356
+ { 4, OperandInfo64 }, // Inst #942 = MSUB_rcr
2357
+ { 4, OperandInfo97 }, // Inst #943 = MSUB_rcr_e
2358
+ { 4, OperandInfo57 }, // Inst #944 = MSUB_rrr2
2359
+ { 4, OperandInfo73 }, // Inst #945 = MSUB_rrr2_e
2360
+ { 2, OperandInfo102 }, // Inst #946 = MTCR_rlc
2361
+ { 4, OperandInfo103 }, // Inst #947 = MULMS_H_rr1_LL2e
2362
+ { 4, OperandInfo103 }, // Inst #948 = MULMS_H_rr1_LU2e
2363
+ { 4, OperandInfo103 }, // Inst #949 = MULMS_H_rr1_UL2e
2364
+ { 4, OperandInfo103 }, // Inst #950 = MULMS_H_rr1_UU2e
2365
+ { 4, OperandInfo103 }, // Inst #951 = MULM_H_rr1_LL2e
2366
+ { 4, OperandInfo103 }, // Inst #952 = MULM_H_rr1_LU2e
2367
+ { 4, OperandInfo103 }, // Inst #953 = MULM_H_rr1_UL2e
2368
+ { 4, OperandInfo103 }, // Inst #954 = MULM_H_rr1_UU2e
2369
+ { 3, OperandInfo104 }, // Inst #955 = MULM_U_rc
2370
+ { 3, OperandInfo72 }, // Inst #956 = MULM_U_rr
2371
+ { 3, OperandInfo104 }, // Inst #957 = MULM_rc
2372
+ { 3, OperandInfo72 }, // Inst #958 = MULM_rr
2373
+ { 4, OperandInfo64 }, // Inst #959 = MULR_H_rr1_LL2e
2374
+ { 4, OperandInfo64 }, // Inst #960 = MULR_H_rr1_LU2e
2375
+ { 4, OperandInfo64 }, // Inst #961 = MULR_H_rr1_UL2e
2376
+ { 4, OperandInfo64 }, // Inst #962 = MULR_H_rr1_UU2e
2377
+ { 4, OperandInfo64 }, // Inst #963 = MULR_H_rr_v110
2378
+ { 4, OperandInfo64 }, // Inst #964 = MULR_Q_rr1_2LL
2379
+ { 4, OperandInfo64 }, // Inst #965 = MULR_Q_rr1_2UU
2380
+ { 4, OperandInfo64 }, // Inst #966 = MULR_Q_rr_v110
2381
+ { 3, OperandInfo46 }, // Inst #967 = MULS_U_rc
2382
+ { 3, OperandInfo45 }, // Inst #968 = MULS_U_rr2
2383
+ { 3, OperandInfo45 }, // Inst #969 = MULS_U_rr_v110
2384
+ { 3, OperandInfo46 }, // Inst #970 = MULS_rc
2385
+ { 3, OperandInfo45 }, // Inst #971 = MULS_rr2
2386
+ { 3, OperandInfo45 }, // Inst #972 = MULS_rr_v110
2387
+ { 3, OperandInfo45 }, // Inst #973 = MUL_F_rrr
2388
+ { 4, OperandInfo103 }, // Inst #974 = MUL_H_rr1_LL2e
2389
+ { 4, OperandInfo103 }, // Inst #975 = MUL_H_rr1_LU2e
2390
+ { 4, OperandInfo103 }, // Inst #976 = MUL_H_rr1_UL2e
2391
+ { 4, OperandInfo103 }, // Inst #977 = MUL_H_rr1_UU2e
2392
+ { 4, OperandInfo103 }, // Inst #978 = MUL_H_rr_v110
2393
+ { 4, OperandInfo64 }, // Inst #979 = MUL_Q_rr1_2
2394
+ { 4, OperandInfo64 }, // Inst #980 = MUL_Q_rr1_2LL
2395
+ { 4, OperandInfo64 }, // Inst #981 = MUL_Q_rr1_2UU
2396
+ { 4, OperandInfo64 }, // Inst #982 = MUL_Q_rr1_2_L
2397
+ { 4, OperandInfo103 }, // Inst #983 = MUL_Q_rr1_2_Le
2398
+ { 4, OperandInfo64 }, // Inst #984 = MUL_Q_rr1_2_U
2399
+ { 4, OperandInfo103 }, // Inst #985 = MUL_Q_rr1_2_Ue
2400
+ { 4, OperandInfo103 }, // Inst #986 = MUL_Q_rr1_2__e
2401
+ { 4, OperandInfo64 }, // Inst #987 = MUL_Q_rr_v110
2402
+ { 3, OperandInfo104 }, // Inst #988 = MUL_U_rc
2403
+ { 3, OperandInfo72 }, // Inst #989 = MUL_U_rr2
2404
+ { 3, OperandInfo46 }, // Inst #990 = MUL_rc
2405
+ { 3, OperandInfo104 }, // Inst #991 = MUL_rc_e
2406
+ { 3, OperandInfo45 }, // Inst #992 = MUL_rr2
2407
+ { 3, OperandInfo72 }, // Inst #993 = MUL_rr2_e
2408
+ { 3, OperandInfo45 }, // Inst #994 = MUL_rr_v110
2409
+ { 2, OperandInfo47 }, // Inst #995 = MUL_srr
2410
+ { 5, OperandInfo59 }, // Inst #996 = NAND_T
2411
+ { 3, OperandInfo46 }, // Inst #997 = NAND_rc
2412
+ { 3, OperandInfo45 }, // Inst #998 = NAND_rr
2413
+ { 2, OperandInfo74 }, // Inst #999 = NEZ_A
2414
+ { 3, OperandInfo75 }, // Inst #1000 = NE_A
2415
+ { 3, OperandInfo46 }, // Inst #1001 = NE_rc
2416
+ { 3, OperandInfo45 }, // Inst #1002 = NE_rr
2417
+ { 0, 0 }, // Inst #1003 = NOP_sr
2418
+ { 0, 0 }, // Inst #1004 = NOP_sys
2419
+ { 5, OperandInfo59 }, // Inst #1005 = NOR_T
2420
+ { 3, OperandInfo46 }, // Inst #1006 = NOR_rc
2421
+ { 3, OperandInfo45 }, // Inst #1007 = NOR_rr
2422
+ { 1, OperandInfo71 }, // Inst #1008 = NOR_sr
2423
+ { 1, OperandInfo71 }, // Inst #1009 = NOR_sr_v110
2424
+ { 1, OperandInfo71 }, // Inst #1010 = NOT_sr_v162
2425
+ { 5, OperandInfo59 }, // Inst #1011 = ORN_T
2426
+ { 3, OperandInfo46 }, // Inst #1012 = ORN_rc
2427
+ { 3, OperandInfo45 }, // Inst #1013 = ORN_rr
2428
+ { 5, OperandInfo59 }, // Inst #1014 = OR_ANDN_T
2429
+ { 5, OperandInfo59 }, // Inst #1015 = OR_AND_T
2430
+ { 3, OperandInfo46 }, // Inst #1016 = OR_EQ_rc
2431
+ { 3, OperandInfo45 }, // Inst #1017 = OR_EQ_rr
2432
+ { 3, OperandInfo46 }, // Inst #1018 = OR_GE_U_rc
2433
+ { 3, OperandInfo45 }, // Inst #1019 = OR_GE_U_rr
2434
+ { 3, OperandInfo46 }, // Inst #1020 = OR_GE_rc
2435
+ { 3, OperandInfo45 }, // Inst #1021 = OR_GE_rr
2436
+ { 3, OperandInfo46 }, // Inst #1022 = OR_LT_U_rc
2437
+ { 3, OperandInfo45 }, // Inst #1023 = OR_LT_U_rr
2438
+ { 3, OperandInfo46 }, // Inst #1024 = OR_LT_rc
2439
+ { 3, OperandInfo45 }, // Inst #1025 = OR_LT_rr
2440
+ { 3, OperandInfo46 }, // Inst #1026 = OR_NE_rc
2441
+ { 3, OperandInfo45 }, // Inst #1027 = OR_NE_rr
2442
+ { 5, OperandInfo59 }, // Inst #1028 = OR_NOR_T
2443
+ { 5, OperandInfo59 }, // Inst #1029 = OR_OR_T
2444
+ { 5, OperandInfo59 }, // Inst #1030 = OR_T
2445
+ { 3, OperandInfo46 }, // Inst #1031 = OR_rc
2446
+ { 3, OperandInfo45 }, // Inst #1032 = OR_rr
2447
+ { 1, OperandInfo2 }, // Inst #1033 = OR_sc
2448
+ { 1, OperandInfo2 }, // Inst #1034 = OR_sc_v110
2449
+ { 2, OperandInfo47 }, // Inst #1035 = OR_srr
2450
+ { 2, OperandInfo47 }, // Inst #1036 = OR_srr_v110
2451
+ { 4, OperandInfo83 }, // Inst #1037 = PACK_rrr
2452
+ { 2, OperandInfo47 }, // Inst #1038 = PARITY_rr
2453
+ { 2, OperandInfo47 }, // Inst #1039 = PARITY_rr_v110
2454
+ { 2, OperandInfo47 }, // Inst #1040 = POPCNT_W_rr
2455
+ { 3, OperandInfo45 }, // Inst #1041 = Q31TOF_rr
2456
+ { 2, OperandInfo47 }, // Inst #1042 = QSEED_F_rr
2457
+ { 1, OperandInfo71 }, // Inst #1043 = RESTORE_sys
2458
+ { 0, 0 }, // Inst #1044 = RET_sr
2459
+ { 0, 0 }, // Inst #1045 = RET_sys
2460
+ { 0, 0 }, // Inst #1046 = RET_sys_v110
2461
+ { 0, 0 }, // Inst #1047 = RFE_sr
2462
+ { 0, 0 }, // Inst #1048 = RFE_sys_sys
2463
+ { 0, 0 }, // Inst #1049 = RFE_sys_sys_v110
2464
+ { 0, 0 }, // Inst #1050 = RFM_sys
2465
+ { 0, 0 }, // Inst #1051 = RSLCX_sys
2466
+ { 0, 0 }, // Inst #1052 = RSTV_sys
2467
+ { 3, OperandInfo46 }, // Inst #1053 = RSUBS_U_rc
2468
+ { 3, OperandInfo46 }, // Inst #1054 = RSUBS_rc
2469
+ { 3, OperandInfo46 }, // Inst #1055 = RSUB_rc
2470
+ { 1, OperandInfo71 }, // Inst #1056 = RSUB_sr_sr
2471
+ { 1, OperandInfo71 }, // Inst #1057 = RSUB_sr_sr_v110
2472
+ { 2, OperandInfo47 }, // Inst #1058 = SAT_BU_rr
2473
+ { 1, OperandInfo71 }, // Inst #1059 = SAT_BU_sr
2474
+ { 1, OperandInfo71 }, // Inst #1060 = SAT_BU_sr_v110
2475
+ { 2, OperandInfo47 }, // Inst #1061 = SAT_B_rr
2476
+ { 1, OperandInfo71 }, // Inst #1062 = SAT_B_sr
2477
+ { 1, OperandInfo71 }, // Inst #1063 = SAT_B_sr_v110
2478
+ { 2, OperandInfo47 }, // Inst #1064 = SAT_HU_rr
2479
+ { 1, OperandInfo71 }, // Inst #1065 = SAT_HU_sr
2480
+ { 1, OperandInfo71 }, // Inst #1066 = SAT_HU_sr_v110
2481
+ { 2, OperandInfo47 }, // Inst #1067 = SAT_H_rr
2482
+ { 1, OperandInfo71 }, // Inst #1068 = SAT_H_sr
2483
+ { 1, OperandInfo71 }, // Inst #1069 = SAT_H_sr_v110
2484
+ { 4, OperandInfo52 }, // Inst #1070 = SELN_A_rcr_v110
2485
+ { 4, OperandInfo63 }, // Inst #1071 = SELN_A_rrr_v110
2486
+ { 4, OperandInfo64 }, // Inst #1072 = SELN_rcr
2487
+ { 4, OperandInfo57 }, // Inst #1073 = SELN_rrr
2488
+ { 4, OperandInfo52 }, // Inst #1074 = SEL_A_rcr_v110
2489
+ { 4, OperandInfo63 }, // Inst #1075 = SEL_A_rrr_v110
2490
+ { 4, OperandInfo64 }, // Inst #1076 = SEL_rcr
2491
+ { 4, OperandInfo57 }, // Inst #1077 = SEL_rrr
2492
+ { 3, OperandInfo46 }, // Inst #1078 = SHAS_rc
2493
+ { 3, OperandInfo45 }, // Inst #1079 = SHAS_rr
2494
+ { 3, OperandInfo46 }, // Inst #1080 = SHA_B_rc
2495
+ { 3, OperandInfo45 }, // Inst #1081 = SHA_B_rr
2496
+ { 3, OperandInfo46 }, // Inst #1082 = SHA_H_rc
2497
+ { 3, OperandInfo45 }, // Inst #1083 = SHA_H_rr
2498
+ { 3, OperandInfo46 }, // Inst #1084 = SHA_rc
2499
+ { 3, OperandInfo45 }, // Inst #1085 = SHA_rr
2500
+ { 2, OperandInfo58 }, // Inst #1086 = SHA_src
2501
+ { 2, OperandInfo58 }, // Inst #1087 = SHA_src_v110
2502
+ { 3, OperandInfo46 }, // Inst #1088 = SHUFFLE_rc
2503
+ { 5, OperandInfo59 }, // Inst #1089 = SH_ANDN_T
2504
+ { 5, OperandInfo59 }, // Inst #1090 = SH_AND_T
2505
+ { 3, OperandInfo46 }, // Inst #1091 = SH_B_rc
2506
+ { 3, OperandInfo45 }, // Inst #1092 = SH_B_rr
2507
+ { 3, OperandInfo46 }, // Inst #1093 = SH_EQ_rc
2508
+ { 3, OperandInfo45 }, // Inst #1094 = SH_EQ_rr
2509
+ { 3, OperandInfo46 }, // Inst #1095 = SH_GE_U_rc
2510
+ { 3, OperandInfo45 }, // Inst #1096 = SH_GE_U_rr
2511
+ { 3, OperandInfo46 }, // Inst #1097 = SH_GE_rc
2512
+ { 3, OperandInfo45 }, // Inst #1098 = SH_GE_rr
2513
+ { 3, OperandInfo46 }, // Inst #1099 = SH_H_rc
2514
+ { 3, OperandInfo45 }, // Inst #1100 = SH_H_rr
2515
+ { 3, OperandInfo46 }, // Inst #1101 = SH_LT_U_rc
2516
+ { 3, OperandInfo45 }, // Inst #1102 = SH_LT_U_rr
2517
+ { 3, OperandInfo46 }, // Inst #1103 = SH_LT_rc
2518
+ { 3, OperandInfo45 }, // Inst #1104 = SH_LT_rr
2519
+ { 5, OperandInfo59 }, // Inst #1105 = SH_NAND_T
2520
+ { 3, OperandInfo46 }, // Inst #1106 = SH_NE_rc
2521
+ { 3, OperandInfo45 }, // Inst #1107 = SH_NE_rr
2522
+ { 5, OperandInfo59 }, // Inst #1108 = SH_NOR_T
2523
+ { 5, OperandInfo59 }, // Inst #1109 = SH_ORN_T
2524
+ { 5, OperandInfo59 }, // Inst #1110 = SH_OR_T
2525
+ { 5, OperandInfo59 }, // Inst #1111 = SH_XNOR_T
2526
+ { 5, OperandInfo59 }, // Inst #1112 = SH_XOR_T
2527
+ { 3, OperandInfo46 }, // Inst #1113 = SH_rc
2528
+ { 3, OperandInfo45 }, // Inst #1114 = SH_rr
2529
+ { 2, OperandInfo58 }, // Inst #1115 = SH_src
2530
+ { 2, OperandInfo58 }, // Inst #1116 = SH_src_v110
2531
+ { 1, OperandInfo2 }, // Inst #1117 = STLCX_abs
2532
+ { 2, OperandInfo55 }, // Inst #1118 = STLCX_bo_bso
2533
+ { 1, OperandInfo2 }, // Inst #1119 = STUCX_abs
2534
+ { 2, OperandInfo55 }, // Inst #1120 = STUCX_bo_bso
2535
+ { 2, OperandInfo55 }, // Inst #1121 = ST_A_abs
2536
+ { 3, OperandInfo48 }, // Inst #1122 = ST_A_bo_bso
2537
+ { 3, OperandInfo93 }, // Inst #1123 = ST_A_bo_c
2538
+ { 3, OperandInfo48 }, // Inst #1124 = ST_A_bo_pos
2539
+ { 3, OperandInfo48 }, // Inst #1125 = ST_A_bo_pre
2540
+ { 2, OperandInfo105 }, // Inst #1126 = ST_A_bo_r
2541
+ { 3, OperandInfo48 }, // Inst #1127 = ST_A_bol
2542
+ { 1, OperandInfo2 }, // Inst #1128 = ST_A_sc
2543
+ { 2, OperandInfo55 }, // Inst #1129 = ST_A_sro
2544
+ { 2, OperandInfo55 }, // Inst #1130 = ST_A_sro_v110
2545
+ { 2, OperandInfo56 }, // Inst #1131 = ST_A_ssr
2546
+ { 2, OperandInfo56 }, // Inst #1132 = ST_A_ssr_pos
2547
+ { 2, OperandInfo56 }, // Inst #1133 = ST_A_ssr_pos_v110
2548
+ { 2, OperandInfo56 }, // Inst #1134 = ST_A_ssr_v110
2549
+ { 2, OperandInfo55 }, // Inst #1135 = ST_A_ssro
2550
+ { 2, OperandInfo55 }, // Inst #1136 = ST_A_ssro_v110
2551
+ { 2, OperandInfo58 }, // Inst #1137 = ST_B_abs
2552
+ { 3, OperandInfo90 }, // Inst #1138 = ST_B_bo_bso
2553
+ { 3, OperandInfo106 }, // Inst #1139 = ST_B_bo_c
2554
+ { 3, OperandInfo90 }, // Inst #1140 = ST_B_bo_pos
2555
+ { 3, OperandInfo90 }, // Inst #1141 = ST_B_bo_pre
2556
+ { 2, OperandInfo107 }, // Inst #1142 = ST_B_bo_r
2557
+ { 3, OperandInfo53 }, // Inst #1143 = ST_B_bol
2558
+ { 2, OperandInfo55 }, // Inst #1144 = ST_B_sro
2559
+ { 2, OperandInfo55 }, // Inst #1145 = ST_B_sro_v110
2560
+ { 2, OperandInfo101 }, // Inst #1146 = ST_B_ssr
2561
+ { 2, OperandInfo101 }, // Inst #1147 = ST_B_ssr_pos
2562
+ { 2, OperandInfo101 }, // Inst #1148 = ST_B_ssr_pos_v110
2563
+ { 2, OperandInfo101 }, // Inst #1149 = ST_B_ssr_v110
2564
+ { 2, OperandInfo58 }, // Inst #1150 = ST_B_ssro
2565
+ { 2, OperandInfo58 }, // Inst #1151 = ST_B_ssro_v110
2566
+ { 2, OperandInfo61 }, // Inst #1152 = ST_DA_abs
2567
+ { 3, OperandInfo93 }, // Inst #1153 = ST_DA_bo_bso
2568
+ { 3, OperandInfo94 }, // Inst #1154 = ST_DA_bo_c
2569
+ { 3, OperandInfo93 }, // Inst #1155 = ST_DA_bo_pos
2570
+ { 3, OperandInfo93 }, // Inst #1156 = ST_DA_bo_pre
2571
+ { 2, OperandInfo95 }, // Inst #1157 = ST_DA_bo_r
2572
+ { 2, OperandInfo87 }, // Inst #1158 = ST_D_abs
2573
+ { 3, OperandInfo66 }, // Inst #1159 = ST_D_bo_bso
2574
+ { 3, OperandInfo108 }, // Inst #1160 = ST_D_bo_c
2575
+ { 3, OperandInfo66 }, // Inst #1161 = ST_D_bo_pos
2576
+ { 3, OperandInfo66 }, // Inst #1162 = ST_D_bo_pre
2577
+ { 2, OperandInfo109 }, // Inst #1163 = ST_D_bo_r
2578
+ { 2, OperandInfo58 }, // Inst #1164 = ST_H_abs
2579
+ { 3, OperandInfo90 }, // Inst #1165 = ST_H_bo_bso
2580
+ { 3, OperandInfo106 }, // Inst #1166 = ST_H_bo_c
2581
+ { 3, OperandInfo90 }, // Inst #1167 = ST_H_bo_pos
2582
+ { 3, OperandInfo90 }, // Inst #1168 = ST_H_bo_pre
2583
+ { 2, OperandInfo107 }, // Inst #1169 = ST_H_bo_r
2584
+ { 3, OperandInfo53 }, // Inst #1170 = ST_H_bol
2585
+ { 2, OperandInfo55 }, // Inst #1171 = ST_H_sro
2586
+ { 2, OperandInfo55 }, // Inst #1172 = ST_H_sro_v110
2587
+ { 2, OperandInfo101 }, // Inst #1173 = ST_H_ssr
2588
+ { 2, OperandInfo101 }, // Inst #1174 = ST_H_ssr_pos
2589
+ { 2, OperandInfo101 }, // Inst #1175 = ST_H_ssr_pos_v110
2590
+ { 2, OperandInfo101 }, // Inst #1176 = ST_H_ssr_v110
2591
+ { 2, OperandInfo58 }, // Inst #1177 = ST_H_ssro
2592
+ { 2, OperandInfo58 }, // Inst #1178 = ST_H_ssro_v110
2593
+ { 2, OperandInfo58 }, // Inst #1179 = ST_Q_abs
2594
+ { 3, OperandInfo90 }, // Inst #1180 = ST_Q_bo_bso
2595
+ { 3, OperandInfo106 }, // Inst #1181 = ST_Q_bo_c
2596
+ { 3, OperandInfo90 }, // Inst #1182 = ST_Q_bo_pos
2597
+ { 3, OperandInfo90 }, // Inst #1183 = ST_Q_bo_pre
2598
+ { 2, OperandInfo107 }, // Inst #1184 = ST_Q_bo_r
2599
+ { 3, OperandInfo110 }, // Inst #1185 = ST_T
2600
+ { 2, OperandInfo58 }, // Inst #1186 = ST_W_abs
2601
+ { 3, OperandInfo90 }, // Inst #1187 = ST_W_bo_bso
2602
+ { 3, OperandInfo106 }, // Inst #1188 = ST_W_bo_c
2603
+ { 3, OperandInfo90 }, // Inst #1189 = ST_W_bo_pos
2604
+ { 3, OperandInfo90 }, // Inst #1190 = ST_W_bo_pre
2605
+ { 2, OperandInfo107 }, // Inst #1191 = ST_W_bo_r
2606
+ { 3, OperandInfo53 }, // Inst #1192 = ST_W_bol
2607
+ { 1, OperandInfo2 }, // Inst #1193 = ST_W_sc
2608
+ { 2, OperandInfo55 }, // Inst #1194 = ST_W_sro
2609
+ { 2, OperandInfo55 }, // Inst #1195 = ST_W_sro_v110
2610
+ { 2, OperandInfo101 }, // Inst #1196 = ST_W_ssr
2611
+ { 2, OperandInfo101 }, // Inst #1197 = ST_W_ssr_pos
2612
+ { 2, OperandInfo101 }, // Inst #1198 = ST_W_ssr_pos_v110
2613
+ { 2, OperandInfo101 }, // Inst #1199 = ST_W_ssr_v110
2614
+ { 2, OperandInfo58 }, // Inst #1200 = ST_W_ssro
2615
+ { 2, OperandInfo58 }, // Inst #1201 = ST_W_ssro_v110
2616
+ { 3, OperandInfo45 }, // Inst #1202 = SUBC_rr
2617
+ { 4, OperandInfo52 }, // Inst #1203 = SUBSC_A_rr
2618
+ { 3, OperandInfo45 }, // Inst #1204 = SUBS_BU_rr
2619
+ { 3, OperandInfo45 }, // Inst #1205 = SUBS_B_rr
2620
+ { 3, OperandInfo45 }, // Inst #1206 = SUBS_HU_rr
2621
+ { 3, OperandInfo45 }, // Inst #1207 = SUBS_H_rr
2622
+ { 3, OperandInfo45 }, // Inst #1208 = SUBS_U_rr
2623
+ { 3, OperandInfo45 }, // Inst #1209 = SUBS_rr
2624
+ { 2, OperandInfo47 }, // Inst #1210 = SUBS_srr
2625
+ { 3, OperandInfo45 }, // Inst #1211 = SUBX_rr
2626
+ { 3, OperandInfo54 }, // Inst #1212 = SUB_A_rr
2627
+ { 1, OperandInfo2 }, // Inst #1213 = SUB_A_sc
2628
+ { 1, OperandInfo2 }, // Inst #1214 = SUB_A_sc_v110
2629
+ { 3, OperandInfo45 }, // Inst #1215 = SUB_B_rr
2630
+ { 4, OperandInfo57 }, // Inst #1216 = SUB_F_rrr
2631
+ { 3, OperandInfo45 }, // Inst #1217 = SUB_H_rr
2632
+ { 3, OperandInfo45 }, // Inst #1218 = SUB_rr
2633
+ { 2, OperandInfo47 }, // Inst #1219 = SUB_srr
2634
+ { 2, OperandInfo47 }, // Inst #1220 = SUB_srr_15a
2635
+ { 2, OperandInfo47 }, // Inst #1221 = SUB_srr_a15
2636
+ { 0, 0 }, // Inst #1222 = SVLCX_sys
2637
+ { 3, OperandInfo66 }, // Inst #1223 = SWAPMSK_W_bo_bso
2638
+ { 3, OperandInfo108 }, // Inst #1224 = SWAPMSK_W_bo_c
2639
+ { 3, OperandInfo67 }, // Inst #1225 = SWAPMSK_W_bo_i
2640
+ { 3, OperandInfo66 }, // Inst #1226 = SWAPMSK_W_bo_pos
2641
+ { 3, OperandInfo66 }, // Inst #1227 = SWAPMSK_W_bo_pre
2642
+ { 2, OperandInfo109 }, // Inst #1228 = SWAPMSK_W_bo_r
2643
+ { 2, OperandInfo55 }, // Inst #1229 = SWAP_A_abs
2644
+ { 3, OperandInfo48 }, // Inst #1230 = SWAP_A_bo_bso
2645
+ { 3, OperandInfo93 }, // Inst #1231 = SWAP_A_bo_c
2646
+ { 3, OperandInfo48 }, // Inst #1232 = SWAP_A_bo_pos
2647
+ { 3, OperandInfo48 }, // Inst #1233 = SWAP_A_bo_pre
2648
+ { 2, OperandInfo105 }, // Inst #1234 = SWAP_A_bo_r
2649
+ { 2, OperandInfo58 }, // Inst #1235 = SWAP_W_abs
2650
+ { 3, OperandInfo90 }, // Inst #1236 = SWAP_W_bo_bso
2651
+ { 3, OperandInfo106 }, // Inst #1237 = SWAP_W_bo_c
2652
+ { 3, OperandInfo91 }, // Inst #1238 = SWAP_W_bo_i
2653
+ { 3, OperandInfo90 }, // Inst #1239 = SWAP_W_bo_pos
2654
+ { 3, OperandInfo90 }, // Inst #1240 = SWAP_W_bo_pre
2655
+ { 2, OperandInfo107 }, // Inst #1241 = SWAP_W_bo_r
2656
+ { 1, OperandInfo2 }, // Inst #1242 = SYSCALL_rc
2657
+ { 1, OperandInfo71 }, // Inst #1243 = TLBDEMAP_rr
2658
+ { 0, 0 }, // Inst #1244 = TLBFLUSH_A_rr
2659
+ { 0, 0 }, // Inst #1245 = TLBFLUSH_B_rr
2660
+ { 1, OperandInfo111 }, // Inst #1246 = TLBMAP_rr
2661
+ { 1, OperandInfo71 }, // Inst #1247 = TLBPROBE_A_rr
2662
+ { 1, OperandInfo71 }, // Inst #1248 = TLBPROBE_I_rr
2663
+ { 0, 0 }, // Inst #1249 = TRAPSV_sys
2664
+ { 0, 0 }, // Inst #1250 = TRAPV_sys
2665
+ { 2, OperandInfo60 }, // Inst #1251 = UNPACK_rr_rr
2666
+ { 2, OperandInfo60 }, // Inst #1252 = UNPACK_rr_rr_v110
2667
+ { 1, OperandInfo71 }, // Inst #1253 = UPDFL_rr
2668
+ { 2, OperandInfo47 }, // Inst #1254 = UTOF_rr
2669
+ { 0, 0 }, // Inst #1255 = WAIT_sys
2670
+ { 5, OperandInfo59 }, // Inst #1256 = XNOR_T
2671
+ { 3, OperandInfo46 }, // Inst #1257 = XNOR_rc
2672
+ { 3, OperandInfo45 }, // Inst #1258 = XNOR_rr
2673
+ { 3, OperandInfo46 }, // Inst #1259 = XOR_EQ_rc
2674
+ { 3, OperandInfo45 }, // Inst #1260 = XOR_EQ_rr
2675
+ { 3, OperandInfo46 }, // Inst #1261 = XOR_GE_U_rc
2676
+ { 3, OperandInfo45 }, // Inst #1262 = XOR_GE_U_rr
2677
+ { 3, OperandInfo46 }, // Inst #1263 = XOR_GE_rc
2678
+ { 3, OperandInfo45 }, // Inst #1264 = XOR_GE_rr
2679
+ { 3, OperandInfo46 }, // Inst #1265 = XOR_LT_U_rc
2680
+ { 3, OperandInfo45 }, // Inst #1266 = XOR_LT_U_rr
2681
+ { 3, OperandInfo46 }, // Inst #1267 = XOR_LT_rc
2682
+ { 3, OperandInfo45 }, // Inst #1268 = XOR_LT_rr
2683
+ { 3, OperandInfo46 }, // Inst #1269 = XOR_NE_rc
2684
+ { 3, OperandInfo45 }, // Inst #1270 = XOR_NE_rr
2685
+ { 5, OperandInfo59 }, // Inst #1271 = XOR_T
2686
+ { 3, OperandInfo46 }, // Inst #1272 = XOR_rc
2687
+ { 3, OperandInfo45 }, // Inst #1273 = XOR_rr
2688
+ { 2, OperandInfo47 }, // Inst #1274 = XOR_srr
2689
+ };
2690
+
2691
+ #endif // GET_INSTRINFO_MC_DESC
2692
+
2693
+