hexcore-capstone 1.2.0

package/deps/capstone/MCInst.c

@@ -0,0 +1,270 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+#include <string.h>
+#include <assert.h>
+
+#include "MCInst.h"
+#include "utils.h"
+
+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
+
+void MCInst_Init(MCInst *inst)
+{
+	// unnecessary to initialize in loop . its expensive and inst->size shuold be honored
+	inst->Operands[0].Kind = kInvalid;
+	inst->Operands[0].ImmVal = 0;
+
+	inst->Opcode = 0;
+	inst->OpcodePub = 0;
+	inst->size = 0;
+	inst->has_imm = false;
+	inst->op1_size = 0;
+	inst->writeback = false;
+	inst->ac_idx = 0;
+	inst->popcode_adjust = 0;
+	inst->assembly[0] = '\0';
+	inst->wasm_data.type = WASM_OP_INVALID;
+	inst->xAcquireRelease = 0;
+	for (int i = 0; i < MAX_MC_OPS; ++i)
+		inst->tied_op_idx[i] = -1;
+}
+
+void MCInst_clear(MCInst *inst)
+{
+	inst->size = 0;
+}
+
+// does not free @Op
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
+{
+	assert(index < MAX_MC_OPS);
+	int i;
+
+	for(i = inst->size; i > index; i--)
+		//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+		inst->Operands[i] = inst->Operands[i-1];
+
+	inst->Operands[index] = *Op;
+	inst->size++;
+}
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op)
+{
+	inst->Opcode = Op;
+}
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
+{
+	inst->OpcodePub = Op;
+}
+
+unsigned MCInst_getOpcode(const MCInst *inst)
+{
+	return inst->Opcode;
+}
+
+unsigned MCInst_getOpcodePub(const MCInst *inst)
+{
+	return inst->OpcodePub;
+}
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
+{
+	assert(i < MAX_MC_OPS);
+	return &inst->Operands[i];
+}
+
+unsigned MCInst_getNumOperands(const MCInst *inst)
+{
+	return inst->size;
+}
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
+{
+	assert(inst->size < MAX_MC_OPS);
+	inst->Operands[inst->size] = *Op;
+
+	inst->size++;
+}
+
+bool MCOperand_isValid(const MCOperand *op)
+{
+	return op->Kind != kInvalid;
+}
+
+bool MCOperand_isReg(const MCOperand *op)
+{
+	return op->Kind == kRegister;
+}
+
+bool MCOperand_isImm(const MCOperand *op)
+{
+	return op->Kind == kImmediate;
+}
+
+bool MCOperand_isFPImm(const MCOperand *op)
+{
+	return op->Kind == kFPImmediate;
+}
+
+bool MCOperand_isDFPImm(const MCOperand *op)
+{
+	return op->Kind == kDFPImmediate;
+}
+
+bool MCOperand_isExpr(const MCOperand *op)
+{
+	return op->Kind == kExpr;
+}
+
+bool MCOperand_isInst(const MCOperand *op)
+{
+	return op->Kind == kInst;
+}
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op)
+{
+	return op->RegVal;
+}
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg)
+{
+	op->RegVal = Reg;
+}
+
+int64_t MCOperand_getImm(MCOperand *op)
+{
+	return op->ImmVal;
+}
+
+void MCOperand_setImm(MCOperand *op, int64_t Val)
+{
+	op->ImmVal = Val;
+}
+
+double MCOperand_getFPImm(const MCOperand *op)
+{
+	return op->FPImmVal;
+}
+
+void MCOperand_setFPImm(MCOperand *op, double Val)
+{
+	op->FPImmVal = Val;
+}
+
+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->MachineOperandType = kRegister;
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+
+	return op;
+}
+
+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->MachineOperandType = kRegister;
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+}
+
+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->MachineOperandType = kImmediate;
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+
+	return op;
+}
+
+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
+{
+	assert(mcInst->size < MAX_MC_OPS);
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->MachineOperandType = kImmediate;
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+}
+
+/// Check if any operand of the MCInstrDesc is predicable
+bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
+{
+	const MCOperandInfo *OpInfo = MIDesc->OpInfo;
+	unsigned NumOps = MIDesc->NumOperands;
+	for (unsigned i = 0; i < NumOps; ++i) {
+		if (MCOperandInfo_isPredicate(&OpInfo[i])) {
+			return true;
+		}
+	}
+	return false;
+}
+
+/// Checks if tied operands exist in the instruction and sets
+/// - The writeback flag in detail
+/// - Saves the indices of the tied destination operands.
+void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc)
+{
+	const MCOperandInfo *OpInfo = InstDesc[MCInst_getOpcode(MI)].OpInfo;
+	unsigned short NumOps = InstDesc[MCInst_getOpcode(MI)].NumOperands;
+
+	unsigned i;
+	for (i = 0; i < NumOps; ++i) {
+		if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
+			int idx = MCOperandInfo_getOperandConstraint(
+				&InstDesc[MCInst_getOpcode(MI)], i,
+				MCOI_TIED_TO);
+
+			if (idx == -1)
+				continue;
+
+			if (i >= MAX_MC_OPS) {
+				assert(0 &&
+				       "Maximum number of MC operands reached.");
+			}
+			MI->tied_op_idx[i] = idx;
+
+			if (MI->flat_insn->detail)
+				MI->flat_insn->detail->writeback = true;
+		}
+	}
+}
+
+/// Check if operand with OpNum is tied by another operand
+/// (operand is tying destination).
+bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum)
+{
+	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
+	for (int i = 0; i < MAX_MC_OPS; ++i) {
+		if (MI->tied_op_idx[i] == OpNum)
+			return true;
+	}
+	return false;
+}
+
+/// Check if operand with OpNum is tying another operand
+/// (operand is tying src).
+bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
+{
+	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
+	return MI->tied_op_idx[OpNum] != -1;
+}

package/deps/capstone/MCInst.h

@@ -0,0 +1,165 @@
+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MCInst and MCOperand classes, which
+// is the basic representation used to represent low-level machine code
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_MCINST_H
+#define CS_MCINST_H
+
+#include "include/capstone/capstone.h"
+#include "MCInstrDesc.h"
+#include "MCRegisterInfo.h"
+
+typedef struct MCInst MCInst;
+typedef struct cs_struct cs_struct;
+typedef struct MCOperand MCOperand;
+
+/// MCOperand - Instances of this class represent operands of the MCInst class.
+/// This is a simple discriminated union.
+struct MCOperand {
+	enum {
+		kInvalid = 0,  ///< Uninitialized.
+		kRegister,     ///< Register operand.
+		kImmediate,    ///< Immediate operand.
+		kFPImmediate,  ///< Floating-point immediate operand.
+		kDFPImmediate, ///< Double-Floating-point immediate operand.
+		kExpr,	       ///< Relocatable immediate operand.
+		kInst	       ///< Sub-instruction operand.
+
+	} MachineOperandType;
+	unsigned char Kind;
+
+	union {
+		unsigned RegVal;
+		int64_t ImmVal;
+		double FPImmVal;
+	};
+};
+
+bool MCOperand_isValid(const MCOperand *op);
+
+bool MCOperand_isReg(const MCOperand *op);
+
+bool MCOperand_isImm(const MCOperand *op);
+
+bool MCOperand_isFPImm(const MCOperand *op);
+
+bool MCOperand_isDFPImm(const MCOperand *op);
+
+bool MCOperand_isExpr(const MCOperand *op);
+
+bool MCOperand_isInst(const MCOperand *op);
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op);
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg);
+
+int64_t MCOperand_getImm(MCOperand *op);
+
+void MCOperand_setImm(MCOperand *op, int64_t Val);
+
+double MCOperand_getFPImm(const MCOperand *op);
+
+void MCOperand_setFPImm(MCOperand *op, double Val);
+
+const MCInst *MCOperand_getInst(const MCOperand *op);
+
+void MCOperand_setInst(MCOperand *op, const MCInst *Val);
+
+// create Reg operand in the next slot
+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
+
+// create Reg operand use the last-unused slot
+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
+
+// create Imm operand in the next slot
+void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
+
+// create Imm operand in the last-unused slot
+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
+
+#define MAX_MC_OPS 48
+
+/// MCInst - Instances of this class represent a single low-level machine
+/// instruction.
+struct MCInst {
+	unsigned OpcodePub;  // public opcode (<arch>_INS_yyy in header files <arch>.h)
+	uint8_t size;	// number of operands
+	bool has_imm;	// indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
+	uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
+	unsigned Opcode;  // private opcode
+	MCOperand Operands[MAX_MC_OPS];
+	cs_insn *flat_insn;	// insn to be exposed to public
+	uint64_t address;	// address of this insn
+	cs_struct *csh;	// save the main csh
+	uint8_t x86opsize;	// opsize for [mem] operand
+
+	// These flags could be used to pass some info from one target subcomponent
+	// to another, for example, from disassembler to asm printer. The values of
+	// the flags have any sense on target level only (e.g. prefixes on x86).
+	unsigned flags;
+
+	// (Optional) instruction prefix, which can be up to 4 bytes.
+	// A prefix byte gets value 0 when irrelevant.
+	// This is copied from cs_x86 struct
+	uint8_t x86_prefix[4];
+	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
+	bool writeback;		// writeback for ARM
+	int8_t tied_op_idx
+		[MAX_MC_OPS]; ///< Tied operand indices. Index = Src op; Value: Dest op
+	// operand access index for list of registers sharing the same access right (for ARM)
+	uint8_t ac_idx;
+	uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
+	char assembly[8];	// for special instruction, so that we dont need printer
+	unsigned char evm_data[32];	// for EVM PUSH operand
+	cs_wasm_op wasm_data;    // for WASM operand
+	MCRegisterInfo *MRI;
+	uint8_t xAcquireRelease;   // X86 xacquire/xrelease
+};
+
+void MCInst_Init(MCInst *inst);
+
+void MCInst_clear(MCInst *inst);
+
+// do not free operand after inserting
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcode(const MCInst*);
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcodePub(const MCInst*);
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
+
+unsigned MCInst_getNumOperands(const MCInst *inst);
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
+
+bool MCInst_isPredicable(const MCInstrDesc *MIDesc);
+
+void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc);
+
+bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);
+
+bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);
+
+#endif

package/deps/capstone/MCInstrDesc.c

@@ -0,0 +1,41 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#include "MCInstrDesc.h"
+
+/// isPredicate - Set if this is one of the operands that made up of
+/// the predicate operand that controls an isPredicable() instruction.
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_Predicate);
+}
+
+/// isOptionalDef - Set if this operand is a optional def.
+///
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_OptionalDef);
+}
+
+/// Checks if operand is tied to another one.
+bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m)
+{
+	if (m->Constraints & (1 << MCOI_TIED_TO))
+		return true;
+	return false;
+}
+
+/// Returns the value of the specified operand constraint if
+/// it is present. Returns -1 if it is not present.
+int MCOperandInfo_getOperandConstraint(const MCInstrDesc *InstrDesc,
+				       unsigned OpNum,
+				       MCOI_OperandConstraint Constraint)
+{
+	const MCOperandInfo OpInfo = InstrDesc->OpInfo[OpNum];
+	if (OpNum < InstrDesc->NumOperands &&
+	    (OpInfo.Constraints & (1 << Constraint))) {
+		unsigned ValuePos = 4 + Constraint * 4;
+		return (OpInfo.Constraints >> ValuePos) & 0xf;
+	}
+	return -1;
+}

package/deps/capstone/MCInstrDesc.h

@@ -0,0 +1,167 @@
+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_LLVM_MC_MCINSTRDESC_H
+#define CS_LLVM_MC_MCINSTRDESC_H
+
+#include "MCRegisterInfo.h"
+#include "capstone/platform.h"
+
+//===----------------------------------------------------------------------===//
+// Machine Operand Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// Operand constraints. These are encoded in 16 bits with one of the
+/// low-order 3 bits specifying that a constraint is present and the
+/// corresponding high-order hex digit specifying the constraint value.
+/// This allows for a maximum of 3 constraints.
+typedef enum {
+	MCOI_TIED_TO = 0,    // Operand tied to another operand.
+	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+} MCOI_OperandConstraint;
+
+// Define a macro to produce each constraint value.
+#define CONSTRAINT_MCOI_TIED_TO(op) \
+  ((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
+
+#define CONSTRAINT_MCOI_EARLY_CLOBBER \
+  (1 << MCOI_EARLY_CLOBBER)
+
+/// OperandFlags - These are flags set on operands, but should be considered
+/// private, all access should go through the MCOperandInfo accessors.
+/// See the accessors for a description of what these are.
+enum MCOI_OperandFlags {
+	MCOI_LookupPtrRegClass = 0,
+	MCOI_Predicate,
+	MCOI_OptionalDef
+};
+
+/// Operand Type - Operands are tagged with one of the values of this enum.
+enum MCOI_OperandType {
+	MCOI_OPERAND_UNKNOWN = 0,
+	MCOI_OPERAND_IMMEDIATE = 1,
+	MCOI_OPERAND_REGISTER = 2,
+	MCOI_OPERAND_MEMORY = 3,
+	MCOI_OPERAND_PCREL = 4,
+
+	MCOI_OPERAND_FIRST_GENERIC = 6,
+	MCOI_OPERAND_GENERIC_0 = 6,
+	MCOI_OPERAND_GENERIC_1 = 7,
+	MCOI_OPERAND_GENERIC_2 = 8,
+	MCOI_OPERAND_GENERIC_3 = 9,
+	MCOI_OPERAND_GENERIC_4 = 10,
+	MCOI_OPERAND_GENERIC_5 = 11,
+	MCOI_OPERAND_LAST_GENERIC = 11,
+
+	MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
+	MCOI_OPERAND_GENERIC_IMM_0 = 12,
+	MCOI_OPERAND_LAST_GENERIC_IMM = 12,
+
+	MCOI_OPERAND_FIRST_TARGET = 13,
+};
+
+
+/// MCOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+typedef struct MCOperandInfo {
+	/// This specifies the register class enumeration of the operand
+	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+	/// get a dynamic register class.
+	int16_t RegClass;
+
+	/// These are flags from the MCOI::OperandFlags enum.
+	uint8_t Flags;
+
+	/// Information about the type of the operand.
+	uint8_t OperandType;
+
+	/// The lower 16 bits are used to specify which constraints are set.
+	/// The higher 16 bits are used to specify the value of constraints (4 bits each).
+	uint32_t Constraints;
+	/// Currently no other information.
+} MCOperandInfo;
+
+
+//===----------------------------------------------------------------------===//
+// Machine Instruction Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// MCInstrDesc flags - These should be considered private to the
+/// implementation of the MCInstrDesc class. Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly. These all correspond to
+/// bitfields in the MCInstrDesc::Flags field.
+enum {
+	MCID_Variadic = 0,
+	MCID_HasOptionalDef,
+	MCID_Pseudo,
+	MCID_Return,
+	MCID_Call,
+	MCID_Barrier,
+	MCID_Terminator,
+	MCID_Branch,
+	MCID_IndirectBranch,
+	MCID_Compare,
+	MCID_MoveImm,
+	MCID_MoveReg,
+	MCID_Bitcast,
+	MCID_Select,
+	MCID_DelaySlot,
+	MCID_FoldableAsLoad,
+	MCID_MayLoad,
+	MCID_MayStore,
+	MCID_Predicable,
+	MCID_NotDuplicable,
+	MCID_UnmodeledSideEffects,
+	MCID_Commutable,
+	MCID_ConvertibleTo3Addr,
+	MCID_UsesCustomInserter,
+	MCID_HasPostISelHook,
+	MCID_Rematerializable,
+	MCID_CheapAsAMove,
+	MCID_ExtraSrcRegAllocReq,
+	MCID_ExtraDefRegAllocReq,
+	MCID_RegSequence,
+	MCID_ExtractSubreg,
+	MCID_InsertSubreg,
+	MCID_Convergent,
+	MCID_Add,
+	MCID_Trap,
+};
+
+/// MCInstrDesc - Describe properties that are true of each instruction in the
+/// target description file. This captures information about side effects,
+/// register use and many other things. There is one instance of this struct
+/// for each target instruction class, and the MachineInstr class points to
+/// this struct directly to describe itself.
+typedef struct MCInstrDesc {
+	unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
+	const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+} MCInstrDesc;
+
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
+
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
+
+bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
+
+int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
+				       unsigned OpNum,
+				       MCOI_OperandConstraint Constraint);
+
+#endif