hexcore-capstone 1.2.0

package/deps/capstone/MCRegisterInfo.c

@@ -0,0 +1,151 @@
+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements MCRegisterInfo functions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#include "MCRegisterInfo.h"
+
+/// DiffListIterator - Base iterator class that can traverse the
+/// differentially encoded register and regunit lists in DiffLists.
+/// Don't use this class directly, use one of the specialized sub-classes
+/// defined below.
+typedef struct DiffListIterator {
+	uint16_t Val;
+	const MCPhysReg *List;
+} DiffListIterator;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		const MCRegisterDesc *D, unsigned NR,
+		unsigned RA, unsigned PC,
+		const MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2], unsigned NRU,
+		const MCPhysReg *DL,
+		const char *Strings,
+		const uint16_t *SubIndices, unsigned NumIndices,
+		const uint16_t *RET)
+{
+	RI->Desc = D;
+	RI->NumRegs = NR;
+	RI->RAReg = RA;
+	RI->PCReg = PC;
+	RI->Classes = C;
+	RI->DiffLists = DL;
+	RI->RegStrings = Strings;
+	RI->NumClasses = NC;
+	RI->RegUnitRoots = RURoots;
+	RI->NumRegUnits = NRU;
+	RI->SubRegIndices = SubIndices;
+	RI->NumSubRegIndices = NumIndices;
+	RI->RegEncodingTable = RET;
+}
+
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
+{
+	d->Val = InitVal;
+	d->List = DiffList;
+}
+
+static uint16_t DiffListIterator_getVal(DiffListIterator *d)
+{
+	return d->Val;
+}
+
+static bool DiffListIterator_next(DiffListIterator *d)
+{
+	MCPhysReg D;
+
+	if (d->List == 0)
+		return false;
+
+	D = *d->List;
+	d->List++;
+	d->Val += D;
+
+	if (!D)
+		d->List = 0;
+
+	return (D != 0);
+}
+
+static bool DiffListIterator_isValid(DiffListIterator *d)
+{
+	return (d->List != 0);
+}
+
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
+{
+	DiffListIterator iter;
+
+	if (Reg >= RI->NumRegs) {
+		return 0;
+	}
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		uint16_t val = DiffListIterator_getVal(&iter);
+		if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+			return val;
+
+		DiffListIterator_next(&iter);
+	}
+
+	return 0;
+}
+
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+{
+	DiffListIterator iter;
+	const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		if (*SRI == Idx)
+			return DiffListIterator_getVal(&iter);
+		DiffListIterator_next(&iter);
+		++SRI;
+	}
+
+	return 0;
+}
+
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
+{
+	//assert(i < getNumRegClasses() && "Register Class ID out of range");
+	if (i >= RI->NumClasses)
+		return 0;
+	return &(RI->Classes[i]);
+}
+
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
+{
+	unsigned InByte = 0;
+	unsigned Byte = 0;
+
+	// Make sure that MCRegisterInfo_getRegClass didn't return 0
+	// (for calls to GETREGCLASS_CONTAIN0)
+	if(!c)
+		return false;
+
+	InByte = Reg % 8;
+	Byte = Reg / 8;
+
+	if (Byte >= c->RegSetSize)
+		return false;
+
+	return (c->RegSet[Byte] & (1 << InByte)) != 0;
+}

package/deps/capstone/MCRegisterInfo.h

@@ -0,0 +1,116 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_LLVM_MC_MCREGISTERINFO_H
+#define CS_LLVM_MC_MCREGISTERINFO_H
+
+#include "capstone/platform.h"
+
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+typedef const MCPhysReg* iterator;
+
+typedef struct MCRegisterClass2 {
+	iterator RegsBegin;
+	const uint8_t *RegSet;
+	uint8_t RegsSize;
+	uint8_t RegSetSize;
+} MCRegisterClass2;
+
+typedef struct MCRegisterClass {
+	iterator RegsBegin;
+	const uint8_t *RegSet;
+	uint16_t RegSetSize;
+} MCRegisterClass;
+
+/// MCRegisterDesc - This record contains information about a particular
+/// register.  The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
+/// of AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of AX.
+typedef struct MCRegisterDesc {
+	uint32_t Name;      // Printable name for the reg (for debugging)
+	uint32_t SubRegs;   // Sub-register set, described above
+	uint32_t SuperRegs; // Super-register set, described above
+
+	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+	// sub-register in SubRegs.
+	uint32_t SubRegIndices;
+
+	// RegUnits - Points to the list of register units. The low 4 bits holds the
+	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+	uint32_t RegUnits;
+
+	/// Index into list with lane mask sequences. The sequence contains a lanemask
+	/// for every register unit.
+	uint16_t RegUnitLaneMasks;	// ???
+} MCRegisterDesc;
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of MCRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+typedef struct MCRegisterInfo {
+	const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+	unsigned NumRegs;                           // Number of entries in the array
+	unsigned RAReg;                             // Return address register
+	unsigned PCReg;                             // Program counter register
+	const MCRegisterClass *Classes;             // Pointer to the regclass array
+	unsigned NumClasses;                        // Number of entries in the array
+	unsigned NumRegUnits;                       // Number of regunits.
+	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+	const MCPhysReg *DiffLists;                 // Pointer to the difflists array
+	// const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
+	const char *RegStrings;                     // Pointer to the string table.
+	// const char *RegClassStrings;                // Pointer to the class strings.
+	const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+	// array.
+	unsigned NumSubRegIndices;                  // Number of subreg indices.
+	const uint16_t *RegEncodingTable;           // Pointer to array of register
+	// encodings.
+} MCRegisterInfo;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		const MCRegisterDesc *D, unsigned NR, unsigned RA,
+		unsigned PC,
+		const MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2],
+		unsigned NRU,
+		const MCPhysReg *DL,
+		const char *Strings,
+		const uint16_t *SubIndices,
+		unsigned NumIndices,
+		const uint16_t *RET);
+
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
+
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
+
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
+
+#endif

package/deps/capstone/Mapping.c

@@ -0,0 +1,254 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "Mapping.h"
+
+// create a cache for fast id lookup
+static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
+{
+	// NOTE: assume that the max id is always put at the end of insns array
+	unsigned short max_id = insns[size - 1].id;
+	unsigned int i;
+
+	unsigned short *cache =
+		(unsigned short *)cs_mem_calloc(max_id + 1, sizeof(*cache));
+
+	for (i = 1; i < size; i++)
+		cache[insns[i].id] = i;
+
+	return cache;
+}
+
+// look for @id in @insns, given its size in @max. first time call will update
+// @cache. return 0 if not found
+unsigned short insn_find(const insn_map *insns, unsigned int max,
+			 unsigned int id, unsigned short **cache)
+{
+	if (id > insns[max - 1].id)
+		return 0;
+
+	if (*cache == NULL)
+		*cache = make_id2insn(insns, max);
+
+	return (*cache)[id];
+}
+
+// Gives the id for the given @name if it is saved in @map.
+// Returns the id or -1 if not found.
+int name2id(const name_map *map, int max, const char *name)
+{
+	int i;
+
+	for (i = 0; i < max; i++) {
+		if (!strcmp(map[i].name, name)) {
+			return map[i].id;
+		}
+	}
+
+	// nothing match
+	return -1;
+}
+
+// Gives the name for the given @id if it is saved in @map.
+// Returns the name or NULL if not found.
+const char *id2name(const name_map *map, int max, const unsigned int id)
+{
+	int i;
+
+	for (i = 0; i < max; i++) {
+		if (map[i].id == id) {
+			return map[i].name;
+		}
+	}
+
+	// nothing match
+	return NULL;
+}
+
+/// Adds a register to the implicit write register list.
+/// It will not add the same register twice.
+void map_add_implicit_write(MCInst *MI, uint32_t Reg)
+{
+	if (!MI->flat_insn->detail)
+		return;
+
+	uint16_t *regs_write = MI->flat_insn->detail->regs_write;
+	for (int i = 0; i < MAX_IMPL_W_REGS; ++i) {
+		if (i == MI->flat_insn->detail->regs_write_count) {
+			regs_write[i] = Reg;
+			MI->flat_insn->detail->regs_write_count++;
+			return;
+		}
+		if (regs_write[i] == Reg)
+			return;
+	}
+}
+
+/// Copies the implicit read registers of @imap to @MI->flat_insn.
+/// Already present registers will be preserved.
+void map_implicit_reads(MCInst *MI, const insn_map *imap)
+{
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+
+	cs_detail *detail = MI->flat_insn->detail;
+	unsigned Opcode = MCInst_getOpcode(MI);
+	unsigned i = 0;
+	uint16_t reg = imap[Opcode].regs_use[i];
+	while (reg != 0) {
+		if (i >= MAX_IMPL_R_REGS ||
+		    detail->regs_read_count >= MAX_IMPL_R_REGS) {
+			printf("ERROR: Too many implicit read register defined in "
+			       "instruction mapping.\n");
+			return;
+		}
+		detail->regs_read[detail->regs_read_count++] = reg;
+		reg = imap[Opcode].regs_use[++i];
+	}
+#endif // CAPSTONE_DIET
+}
+
+/// Copies the implicit write registers of @imap to @MI->flat_insn.
+/// Already present registers will be preserved.
+void map_implicit_writes(MCInst *MI, const insn_map *imap)
+{
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+
+	cs_detail *detail = MI->flat_insn->detail;
+	unsigned Opcode = MCInst_getOpcode(MI);
+	unsigned i = 0;
+	uint16_t reg = imap[Opcode].regs_mod[i];
+	while (reg != 0) {
+		if (i >= MAX_IMPL_W_REGS ||
+		    detail->regs_write_count >= MAX_IMPL_W_REGS) {
+			printf("ERROR: Too many implicit write register defined in "
+			       "instruction mapping.\n");
+			return;
+		}
+		detail->regs_write[detail->regs_write_count++] = reg;
+		reg = imap[Opcode].regs_mod[++i];
+	}
+#endif // CAPSTONE_DIET
+}
+
+/// Copies the groups from @imap to @MI->flat_insn.
+/// Already present groups will be preserved.
+void map_groups(MCInst *MI, const insn_map *imap)
+{
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+
+	cs_detail *detail = MI->flat_insn->detail;
+	unsigned Opcode = MCInst_getOpcode(MI);
+	unsigned i = 0;
+	uint16_t group = imap[Opcode].groups[i];
+	while (group != 0) {
+		if (detail->groups_count >= MAX_NUM_GROUPS) {
+			printf("ERROR: Too many groups defined in instruction mapping.\n");
+			return;
+		}
+		detail->groups[detail->groups_count++] = group;
+		group = imap[Opcode].groups[++i];
+	}
+#endif // CAPSTONE_DIET
+}
+
+// Search for the CS instruction id for the given @MC_Opcode in @imap.
+// return -1 if none is found.
+unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
+			unsigned imap_size)
+{
+	// binary searching since the IDs are sorted in order
+	unsigned int left, right, m;
+	unsigned int max = imap_size;
+
+	right = max - 1;
+
+	if (MC_Opcode < imap[0].id || MC_Opcode > imap[right].id)
+		// not found
+		return -1;
+
+	left = 0;
+
+	while (left <= right) {
+		m = (left + right) / 2;
+		if (MC_Opcode == imap[m].id) {
+			return m;
+		}
+
+		if (MC_Opcode < imap[m].id)
+			right = m - 1;
+		else
+			left = m + 1;
+	}
+
+	return -1;
+}
+
+/// Sets the Capstone instruction id which maps to the @MI opcode.
+/// If no mapping is found the function returns and prints an error.
+void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size)
+{
+	unsigned int i = find_cs_id(MCInst_getOpcode(MI), imap, imap_size);
+	if (i != -1) {
+		MI->flat_insn->id = imap[i].mapid;
+		return;
+	}
+	printf("ERROR: Could not find CS id for MCInst opcode: %d\n",
+	       MCInst_getOpcode(MI));
+	return;
+}
+
+/// Returns the operand type information from the
+/// mapping table for instruction operands.
+/// Only usable by `auto-sync` archs!
+const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum,
+				     const map_insn_ops *insn_ops_map,
+				     size_t map_size)
+{
+	assert(MI);
+	assert(MI->Opcode < map_size);
+	assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) /
+			       sizeof(insn_ops_map[MI->Opcode].ops[0]));
+
+	return insn_ops_map[MI->Opcode].ops[OpNum].type;
+}
+
+/// Returns the operand access flags from the
+/// mapping table for instruction operands.
+/// Only usable by `auto-sync` archs!
+const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
+				       const map_insn_ops *insn_ops_map,
+				       size_t map_size)
+{
+	assert(MI);
+	assert(MI->Opcode < map_size);
+	assert(OpNum < sizeof(insn_ops_map[MI->Opcode].ops) /
+			       sizeof(insn_ops_map[MI->Opcode].ops[0]));
+
+	cs_ac_type access = insn_ops_map[MI->Opcode].ops[OpNum].access;
+	if (MCInst_opIsTied(MI, OpNum) || MCInst_opIsTying(MI, OpNum))
+		access |= (access == CS_AC_READ) ? CS_AC_WRITE : CS_AC_READ;
+	return access;
+}
+
+/// Returns the operand at detail->arch.operands[op_count + offset]
+/// Or NULL if detail is not set.
+#define DEFINE_get_detail_op(arch, ARCH) \
+	cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset) \
+	{ \
+		if (!MI->flat_insn->detail) \
+			return NULL; \
+		int OpIdx = MI->flat_insn->detail->arch.op_count + offset; \
+		assert(OpIdx >= 0 && OpIdx < MAX_MC_OPS); \
+		return &MI->flat_insn->detail->arch.operands[OpIdx]; \
+	}
+
+DEFINE_get_detail_op(arm, ARM);
+DEFINE_get_detail_op(ppc, PPC);
+DEFINE_get_detail_op(tricore, TriCore);

package/deps/capstone/Mapping.h

@@ -0,0 +1,174 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_MAPPING_H
+#define CS_MAPPING_H
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include "include/capstone/capstone.h"
+#include <stddef.h>
+#endif
+#include "cs_priv.h"
+#include <assert.h>
+#include <string.h>
+
+// map instruction to its characteristics
+typedef struct insn_map {
+	unsigned short id;		    // The LLVM instruction id
+	unsigned short mapid;		    // The Capstone instruction id
+#ifndef CAPSTONE_DIET
+	uint16_t regs_use[MAX_IMPL_R_REGS]; ///< list of implicit registers used by
+		///< this instruction
+	uint16_t regs_mod[MAX_IMPL_W_REGS]; ///< list of implicit registers modified
+		///< by this instruction
+	unsigned char groups
+		[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
+	bool branch;		  // branch instruction?
+	bool indirect_branch;	  // indirect branch instruction?
+#endif
+} insn_map;
+
+// look for @id in @m, given its size in @max. first time call will update
+// @cache. return 0 if not found
+unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
+			 unsigned short **cache);
+
+unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
+			unsigned imap_size);
+
+#define MAX_NO_DATA_TYPES 10
+
+///< A LLVM<->CS Mapping entry of an MCOperand.
+typedef struct {
+	uint8_t /* cs_op_type */ type;	 ///< Operand type (e.g.: reg, imm, mem)
+	uint8_t /* cs_ac_type */ access; ///< The access type (read, write)
+	uint8_t				 /* cs_data_type */
+		dtypes[MAX_NO_DATA_TYPES]; ///< List of op types. Terminated by
+		///< CS_DATA_TYPE_LAST
+} mapping_op;
+
+#define MAX_NO_INSN_MAP_OPS 16
+
+///< MCOperands of an instruction.
+typedef struct {
+	mapping_op
+		ops[MAX_NO_INSN_MAP_OPS]; ///< NULL terminated array of insn_op.
+} map_insn_ops;
+
+/// Only usable by `auto-sync` archs!
+const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum,
+				     const map_insn_ops *insn_ops_map,
+				     size_t map_size);
+
+/// Only usable by `auto-sync` archs!
+const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
+				       const map_insn_ops *insn_ops_map,
+				       size_t map_size);
+
+/// Macro for easier access of operand types from the map.
+/// Assumes the istruction operands map is called "insn_operands"
+/// Only usable by `auto-sync` archs!
+#define map_get_op_type(MI, OpNum) \
+	mapping_get_op_type(MI, OpNum, (const map_insn_ops *)insn_operands, \
+			    sizeof(insn_operands) / sizeof(insn_operands[0]))
+
+/// Macro for easier access of operand access flags from the map.
+/// Assumes the istruction operands map is called "insn_operands"
+/// Only usable by `auto-sync` archs!
+#define map_get_op_access(MI, OpNum) \
+	mapping_get_op_access(MI, OpNum, (const map_insn_ops *)insn_operands, \
+			      sizeof(insn_operands) / \
+				      sizeof(insn_operands[0]))
+
+///< Map for ids to their string
+typedef struct name_map {
+	unsigned int id;
+	const char *name;
+} name_map;
+
+// map a name to its ID
+// return 0 if not found
+int name2id(const name_map *map, int max, const char *name);
+
+// map ID to a name
+// return NULL if not found
+const char *id2name(const name_map *map, int max, const unsigned int id);
+
+void map_add_implicit_write(MCInst *MI, uint32_t Reg);
+
+void map_implicit_reads(MCInst *MI, const insn_map *imap);
+
+void map_implicit_writes(MCInst *MI, const insn_map *imap);
+
+void map_groups(MCInst *MI, const insn_map *imap);
+
+void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
+
+#define DECL_get_detail_op(arch, ARCH) \
+	cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset);
+
+DECL_get_detail_op(arm, ARM);
+DECL_get_detail_op(ppc, PPC);
+DECL_get_detail_op(tricore, TriCore);
+
+/// Increments the detail->arch.op_count by one.
+#define DEFINE_inc_detail_op_count(arch, ARCH) \
+	static inline void ARCH##_inc_op_count(MCInst *MI) \
+	{ \
+		MI->flat_insn->detail->arch.op_count++; \
+	}
+
+/// Decrements the detail->arch.op_count by one.
+#define DEFINE_dec_detail_op_count(arch, ARCH) \
+	static inline void ARCH##_dec_op_count(MCInst *MI) \
+	{ \
+		MI->flat_insn->detail->arch.op_count--; \
+	}
+
+DEFINE_inc_detail_op_count(arm, ARM);
+DEFINE_dec_detail_op_count(arm, ARM);
+DEFINE_inc_detail_op_count(ppc, PPC);
+DEFINE_dec_detail_op_count(ppc, PPC);
+DEFINE_inc_detail_op_count(tricore, TriCore);
+DEFINE_dec_detail_op_count(tricore, TriCore);
+
+/// Returns true if a memory operand is currently edited.
+static inline bool doing_mem(const MCInst *MI)
+{
+	return MI->csh->doing_mem;
+}
+
+/// Sets the doing_mem flag to @status.
+static inline void set_doing_mem(const MCInst *MI, bool status)
+{
+	MI->csh->doing_mem = status;
+}
+
+/// Returns detail->arch
+#define DEFINE_get_arch_detail(arch, ARCH) \
+	static inline cs_##arch *ARCH##_get_detail(const MCInst *MI) \
+	{ \
+		assert(MI && MI->flat_insn && MI->flat_insn->detail); \
+		return &MI->flat_insn->detail->arch; \
+	}
+
+DEFINE_get_arch_detail(arm, ARM);
+DEFINE_get_arch_detail(ppc, PPC);
+DEFINE_get_arch_detail(tricore, TriCore);
+
+static inline bool detail_is_set(const MCInst *MI)
+{
+	assert(MI && MI->flat_insn);
+	return MI->flat_insn->detail != NULL;
+}
+
+static inline cs_detail *get_detail(const MCInst *MI)
+{
+	assert(MI && MI->flat_insn);
+	return MI->flat_insn->detail;
+}
+
+#endif // CS_MAPPING_H