crabstone 3.0.3

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (302) hide show
  1. checksums.yaml +7 -0
  2. data/CHANGES.md +61 -0
  3. data/LICENSE +25 -0
  4. data/MANIFEST +312 -0
  5. data/README.md +103 -0
  6. data/Rakefile +27 -0
  7. data/bin/genconst +66 -0
  8. data/bin/genreg +99 -0
  9. data/crabstone.gemspec +27 -0
  10. data/examples/hello_world.rb +43 -0
  11. data/lib/arch/arm.rb +128 -0
  12. data/lib/arch/arm64.rb +167 -0
  13. data/lib/arch/arm64_const.rb +1055 -0
  14. data/lib/arch/arm64_registers.rb +295 -0
  15. data/lib/arch/arm_const.rb +777 -0
  16. data/lib/arch/arm_registers.rb +149 -0
  17. data/lib/arch/mips.rb +78 -0
  18. data/lib/arch/mips_const.rb +850 -0
  19. data/lib/arch/mips_registers.rb +208 -0
  20. data/lib/arch/ppc.rb +90 -0
  21. data/lib/arch/ppc_const.rb +1181 -0
  22. data/lib/arch/ppc_registers.rb +209 -0
  23. data/lib/arch/sparc.rb +79 -0
  24. data/lib/arch/sparc_const.rb +461 -0
  25. data/lib/arch/sparc_registers.rb +121 -0
  26. data/lib/arch/systemz.rb +79 -0
  27. data/lib/arch/sysz_const.rb +779 -0
  28. data/lib/arch/sysz_registers.rb +66 -0
  29. data/lib/arch/x86.rb +107 -0
  30. data/lib/arch/x86_const.rb +1698 -0
  31. data/lib/arch/x86_registers.rb +265 -0
  32. data/lib/arch/xcore.rb +78 -0
  33. data/lib/arch/xcore_const.rb +185 -0
  34. data/lib/arch/xcore_registers.rb +57 -0
  35. data/lib/crabstone.rb +564 -0
  36. data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
  37. data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
  38. data/test/MC/AArch64/neon-2velem.s.cs +113 -0
  39. data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
  40. data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
  41. data/test/MC/AArch64/neon-across.s.cs +40 -0
  42. data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
  43. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
  44. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
  45. data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
  46. data/test/MC/AArch64/neon-crypto.s.cs +15 -0
  47. data/test/MC/AArch64/neon-extract.s.cs +3 -0
  48. data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
  49. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
  50. data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
  51. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
  52. data/test/MC/AArch64/neon-max-min.s.cs +37 -0
  53. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
  54. data/test/MC/AArch64/neon-mov.s.cs +74 -0
  55. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
  56. data/test/MC/AArch64/neon-perm.s.cs +43 -0
  57. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
  58. data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
  59. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
  60. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
  61. data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
  62. data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
  63. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
  64. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
  65. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
  66. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
  67. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
  68. data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
  69. data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
  70. data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
  71. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
  72. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
  73. data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
  74. data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
  75. data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
  76. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
  77. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
  78. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
  79. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
  80. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
  81. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
  82. data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
  83. data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
  84. data/test/MC/AArch64/neon-shift.s.cs +22 -0
  85. data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
  86. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
  87. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
  88. data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
  89. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
  90. data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
  91. data/test/MC/AArch64/neon-tbl.s.cs +21 -0
  92. data/test/MC/AArch64/trace-regs.s.cs +383 -0
  93. data/test/MC/ARM/arm-aliases.s.cs +7 -0
  94. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
  95. data/test/MC/ARM/arm-it-block.s.cs +2 -0
  96. data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
  97. data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
  98. data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
  99. data/test/MC/ARM/arm-trustzone.s.cs +3 -0
  100. data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
  101. data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
  102. data/test/MC/ARM/arm_instructions.s.cs +25 -0
  103. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
  104. data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
  105. data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
  106. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
  107. data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
  108. data/test/MC/ARM/crc32-thumb.s.cs +7 -0
  109. data/test/MC/ARM/crc32.s.cs +7 -0
  110. data/test/MC/ARM/dot-req.s.cs +3 -0
  111. data/test/MC/ARM/fp-armv8.s.cs +52 -0
  112. data/test/MC/ARM/idiv-thumb.s.cs +3 -0
  113. data/test/MC/ARM/idiv.s.cs +3 -0
  114. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
  115. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
  116. data/test/MC/ARM/mode-switch.s.cs +7 -0
  117. data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
  118. data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
  119. data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
  120. data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
  121. data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
  122. data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
  123. data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
  124. data/test/MC/ARM/neon-crypto.s.cs +16 -0
  125. data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
  126. data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
  127. data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
  128. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
  129. data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
  130. data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
  131. data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
  132. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
  133. data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
  134. data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
  135. data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
  136. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
  137. data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
  138. data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
  139. data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
  140. data/test/MC/ARM/neon-v8.s.cs +38 -0
  141. data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
  142. data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
  143. data/test/MC/ARM/neon-vswp.s.cs +3 -0
  144. data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
  145. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
  146. data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
  147. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
  148. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
  149. data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
  150. data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
  151. data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
  152. data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
  153. data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
  154. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
  155. data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
  156. data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
  157. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
  158. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
  159. data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
  160. data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
  161. data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
  162. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
  163. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
  164. data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
  165. data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
  166. data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
  167. data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
  168. data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
  169. data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
  170. data/test/MC/ARM/thumb-hints.s.cs +12 -0
  171. data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
  172. data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
  173. data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
  174. data/test/MC/ARM/thumb.s.cs +19 -0
  175. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
  176. data/test/MC/ARM/thumb2-branches.s.cs +85 -0
  177. data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
  178. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
  179. data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
  180. data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
  181. data/test/MC/ARM/vfp4.s.cs +13 -0
  182. data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
  183. data/test/MC/ARM/vpush-vpop.s.cs +9 -0
  184. data/test/MC/Mips/hilo-addressing.s.cs +4 -0
  185. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
  186. data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
  187. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
  188. data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
  189. data/test/MC/Mips/micromips-expansions.s.cs +20 -0
  190. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
  191. data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
  192. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
  193. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
  194. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
  195. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
  196. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
  197. data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
  198. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
  199. data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
  200. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
  201. data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
  202. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
  203. data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
  204. data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
  205. data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
  206. data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
  207. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
  208. data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
  209. data/test/MC/Mips/mips-expansions.s.cs +20 -0
  210. data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
  211. data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
  212. data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
  213. data/test/MC/Mips/mips-register-names.s.cs +33 -0
  214. data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
  215. data/test/MC/Mips/mips64-instructions.s.cs +3 -0
  216. data/test/MC/Mips/mips64-register-names.s.cs +33 -0
  217. data/test/MC/Mips/mips_directives.s.cs +12 -0
  218. data/test/MC/Mips/nabi-regs.s.cs +12 -0
  219. data/test/MC/Mips/set-at-directive.s.cs +6 -0
  220. data/test/MC/Mips/test_2r.s.cs +16 -0
  221. data/test/MC/Mips/test_2rf.s.cs +33 -0
  222. data/test/MC/Mips/test_3r.s.cs +243 -0
  223. data/test/MC/Mips/test_3rf.s.cs +83 -0
  224. data/test/MC/Mips/test_bit.s.cs +49 -0
  225. data/test/MC/Mips/test_cbranch.s.cs +11 -0
  226. data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
  227. data/test/MC/Mips/test_elm.s.cs +16 -0
  228. data/test/MC/Mips/test_elm_insert.s.cs +4 -0
  229. data/test/MC/Mips/test_elm_insve.s.cs +5 -0
  230. data/test/MC/Mips/test_i10.s.cs +5 -0
  231. data/test/MC/Mips/test_i5.s.cs +45 -0
  232. data/test/MC/Mips/test_i8.s.cs +11 -0
  233. data/test/MC/Mips/test_lsa.s.cs +5 -0
  234. data/test/MC/Mips/test_mi10.s.cs +24 -0
  235. data/test/MC/Mips/test_vec.s.cs +8 -0
  236. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
  237. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
  238. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
  239. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
  240. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
  241. data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
  242. data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
  243. data/test/MC/README +6 -0
  244. data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
  245. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
  246. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
  247. data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
  248. data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
  249. data/test/MC/Sparc/sparc-vis.s.cs +2 -0
  250. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
  251. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
  252. data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
  253. data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
  254. data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
  255. data/test/MC/SystemZ/insn-good.s.cs +2265 -0
  256. data/test/MC/SystemZ/regs-good.s.cs +45 -0
  257. data/test/MC/X86/3DNow.s.cs +29 -0
  258. data/test/MC/X86/address-size.s.cs +5 -0
  259. data/test/MC/X86/avx512-encodings.s.cs +12 -0
  260. data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
  261. data/test/MC/X86/x86-32-avx.s.cs +833 -0
  262. data/test/MC/X86/x86-32-fma3.s.cs +169 -0
  263. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
  264. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
  265. data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
  266. data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
  267. data/test/MC/X86/x86_64-encoding.s.cs +59 -0
  268. data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
  269. data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
  270. data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
  271. data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
  272. data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
  273. data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
  274. data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
  275. data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
  276. data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
  277. data/test/README +6 -0
  278. data/test/test.rb +205 -0
  279. data/test/test.rb.SPEC +235 -0
  280. data/test/test_arm.rb +202 -0
  281. data/test/test_arm.rb.SPEC +275 -0
  282. data/test/test_arm64.rb +150 -0
  283. data/test/test_arm64.rb.SPEC +116 -0
  284. data/test/test_detail.rb +228 -0
  285. data/test/test_detail.rb.SPEC +322 -0
  286. data/test/test_exhaustive.rb +80 -0
  287. data/test/test_mips.rb +118 -0
  288. data/test/test_mips.rb.SPEC +91 -0
  289. data/test/test_ppc.rb +137 -0
  290. data/test/test_ppc.rb.SPEC +84 -0
  291. data/test/test_sanity.rb +83 -0
  292. data/test/test_skipdata.rb +111 -0
  293. data/test/test_skipdata.rb.SPEC +58 -0
  294. data/test/test_sparc.rb +113 -0
  295. data/test/test_sparc.rb.SPEC +116 -0
  296. data/test/test_sysz.rb +111 -0
  297. data/test/test_sysz.rb.SPEC +61 -0
  298. data/test/test_x86.rb +189 -0
  299. data/test/test_x86.rb.SPEC +579 -0
  300. data/test/test_xcore.rb +100 -0
  301. data/test/test_xcore.rb.SPEC +75 -0
  302. metadata +393 -0
@@ -0,0 +1,121 @@
1
+ # Library by Nguyen Anh Quynh
2
+ # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
+ # Additional binding work by Ben Nagy
4
+ # (c) 2013 COSEINC. All Rights Reserved.
5
+
6
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
+ # Command: ./genreg /Users/ben/src/capstone/bindings/python/capstone/
8
+ # 2015-05-02T13:24:08+12:00
9
+
10
+ module Crabstone
11
+ module Sparc
12
+ REG_LOOKUP = {
13
+ 'INVALID' => 0,
14
+ 'F0' => 1,
15
+ 'F1' => 2,
16
+ 'F2' => 3,
17
+ 'F3' => 4,
18
+ 'F4' => 5,
19
+ 'F5' => 6,
20
+ 'F6' => 7,
21
+ 'F7' => 8,
22
+ 'F8' => 9,
23
+ 'F9' => 10,
24
+ 'F10' => 11,
25
+ 'F11' => 12,
26
+ 'F12' => 13,
27
+ 'F13' => 14,
28
+ 'F14' => 15,
29
+ 'F15' => 16,
30
+ 'F16' => 17,
31
+ 'F17' => 18,
32
+ 'F18' => 19,
33
+ 'F19' => 20,
34
+ 'F20' => 21,
35
+ 'F21' => 22,
36
+ 'F22' => 23,
37
+ 'F23' => 24,
38
+ 'F24' => 25,
39
+ 'F25' => 26,
40
+ 'F26' => 27,
41
+ 'F27' => 28,
42
+ 'F28' => 29,
43
+ 'F29' => 30,
44
+ 'F30' => 31,
45
+ 'F31' => 32,
46
+ 'F32' => 33,
47
+ 'F34' => 34,
48
+ 'F36' => 35,
49
+ 'F38' => 36,
50
+ 'F40' => 37,
51
+ 'F42' => 38,
52
+ 'F44' => 39,
53
+ 'F46' => 40,
54
+ 'F48' => 41,
55
+ 'F50' => 42,
56
+ 'F52' => 43,
57
+ 'F54' => 44,
58
+ 'F56' => 45,
59
+ 'F58' => 46,
60
+ 'F60' => 47,
61
+ 'F62' => 48,
62
+ 'FCC0' => 49,
63
+ 'FCC1' => 50,
64
+ 'FCC2' => 51,
65
+ 'FCC3' => 52,
66
+ 'FP' => 53,
67
+ 'G0' => 54,
68
+ 'G1' => 55,
69
+ 'G2' => 56,
70
+ 'G3' => 57,
71
+ 'G4' => 58,
72
+ 'G5' => 59,
73
+ 'G6' => 60,
74
+ 'G7' => 61,
75
+ 'I0' => 62,
76
+ 'I1' => 63,
77
+ 'I2' => 64,
78
+ 'I3' => 65,
79
+ 'I4' => 66,
80
+ 'I5' => 67,
81
+ 'I7' => 68,
82
+ 'ICC' => 69,
83
+ 'L0' => 70,
84
+ 'L1' => 71,
85
+ 'L2' => 72,
86
+ 'L3' => 73,
87
+ 'L4' => 74,
88
+ 'L5' => 75,
89
+ 'L6' => 76,
90
+ 'L7' => 77,
91
+ 'O0' => 78,
92
+ 'O1' => 79,
93
+ 'O2' => 80,
94
+ 'O3' => 81,
95
+ 'O4' => 82,
96
+ 'O5' => 83,
97
+ 'O7' => 84,
98
+ 'SP' => 85,
99
+ 'Y' => 86,
100
+ 'XCC' => 87
101
+ }
102
+
103
+ ID_LOOKUP = REG_LOOKUP.invert
104
+
105
+ # alias registers
106
+ REG_LOOKUP['O6'] = REG_LOOKUP['SP']
107
+ REG_LOOKUP['I6'] = REG_LOOKUP['FP']
108
+
109
+ SYM_LOOKUP = Hash[REG_LOOKUP.map {|k,v| [k.downcase.to_sym,v]}]
110
+
111
+ def self.register reg
112
+ return reg if ID_LOOKUP[reg]
113
+ return SYM_LOOKUP[reg] if SYM_LOOKUP[reg]
114
+ if reg.respond_to? :upcase
115
+ return REG_LOOKUP[reg.upcase] || REG_LOOKUP['INVALID']
116
+ end
117
+ REG_LOOKUP['INVALID']
118
+ end
119
+
120
+ end
121
+ end
@@ -0,0 +1,79 @@
1
+ # Library by Nguyen Anh Quynh
2
+ # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
+ # Additional binding work by Ben Nagy
4
+ # (c) 2013 COSEINC. All Rights Reserved.
5
+
6
+ require 'ffi'
7
+
8
+ require_relative 'sysz_const'
9
+
10
+ module Crabstone
11
+ module SysZ
12
+
13
+ class MemoryOperand < FFI::Struct
14
+ layout(
15
+ :base, :uint8,
16
+ :index, :uint8,
17
+ :length, :uint64,
18
+ :disp, :int64
19
+ )
20
+ end
21
+
22
+ class OperandValue < FFI::Union
23
+ layout(
24
+ :reg, :uint,
25
+ :imm, :int64,
26
+ :mem, MemoryOperand
27
+ )
28
+ end
29
+
30
+ class Operand < FFI::Struct
31
+ layout(
32
+ :type, :uint,
33
+ :value, OperandValue
34
+ )
35
+
36
+ def value
37
+ case self[:type]
38
+ when *[OP_REG, OP_ACREG]
39
+ self[:value][:reg]
40
+ when OP_IMM
41
+ self[:value][:imm]
42
+ when OP_MEM
43
+ self[:value][:mem]
44
+ else
45
+ nil
46
+ end
47
+ end
48
+
49
+ def reg?
50
+ [OP_REG, OP_ACREG].include? self[:type]
51
+ end
52
+
53
+ def imm?
54
+ self[:type] == OP_IMM
55
+ end
56
+
57
+ def mem?
58
+ self[:type] == OP_MEM
59
+ end
60
+
61
+ def valid?
62
+ [OP_MEM, OP_IMM, OP_REG, OP_ACREG].include? self[:type]
63
+ end
64
+ end
65
+
66
+ class Instruction < FFI::Struct
67
+ layout(
68
+ :cc, :uint,
69
+ :op_count, :uint8,
70
+ :operands, [Operand, 6],
71
+ )
72
+
73
+ def operands
74
+ self[:operands].take_while {|op| op[:type].nonzero?}
75
+ end
76
+
77
+ end
78
+ end
79
+ end
@@ -0,0 +1,779 @@
1
+ # Library by Nguyen Anh Quynh
2
+ # Original binding by Nguyen Anh Quynh and Tan Sheng Di
3
+ # Additional binding work by Ben Nagy
4
+ # (c) 2013 COSEINC. All Rights Reserved.
5
+
6
+ # THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
7
+ # Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
8
+ # 2015-05-02T13:24:01+12:00
9
+
10
+ module Crabstone
11
+ module SysZ
12
+
13
+ # Enums corresponding to SystemZ condition codes
14
+
15
+ CC_INVALID = 0
16
+ CC_O = 1
17
+ CC_H = 2
18
+ CC_NLE = 3
19
+ CC_L = 4
20
+ CC_NHE = 5
21
+ CC_LH = 6
22
+ CC_NE = 7
23
+ CC_E = 8
24
+ CC_NLH = 9
25
+ CC_HE = 10
26
+ CC_NL = 11
27
+ CC_LE = 12
28
+ CC_NH = 13
29
+ CC_NO = 14
30
+
31
+ # Operand type for instruction's operands
32
+
33
+ OP_INVALID = 0
34
+ OP_REG = 1
35
+ OP_IMM = 2
36
+ OP_MEM = 3
37
+ OP_ACREG = 64
38
+
39
+ # SystemZ registers
40
+
41
+ REG_INVALID = 0
42
+ REG_0 = 1
43
+ REG_1 = 2
44
+ REG_2 = 3
45
+ REG_3 = 4
46
+ REG_4 = 5
47
+ REG_5 = 6
48
+ REG_6 = 7
49
+ REG_7 = 8
50
+ REG_8 = 9
51
+ REG_9 = 10
52
+ REG_10 = 11
53
+ REG_11 = 12
54
+ REG_12 = 13
55
+ REG_13 = 14
56
+ REG_14 = 15
57
+ REG_15 = 16
58
+ REG_CC = 17
59
+ REG_F0 = 18
60
+ REG_F1 = 19
61
+ REG_F2 = 20
62
+ REG_F3 = 21
63
+ REG_F4 = 22
64
+ REG_F5 = 23
65
+ REG_F6 = 24
66
+ REG_F7 = 25
67
+ REG_F8 = 26
68
+ REG_F9 = 27
69
+ REG_F10 = 28
70
+ REG_F11 = 29
71
+ REG_F12 = 30
72
+ REG_F13 = 31
73
+ REG_F14 = 32
74
+ REG_F15 = 33
75
+ REG_R0L = 34
76
+ REG_ENDING = 35
77
+
78
+ # SystemZ instruction
79
+
80
+ INS_INVALID = 0
81
+ INS_A = 1
82
+ INS_ADB = 2
83
+ INS_ADBR = 3
84
+ INS_AEB = 4
85
+ INS_AEBR = 5
86
+ INS_AFI = 6
87
+ INS_AG = 7
88
+ INS_AGF = 8
89
+ INS_AGFI = 9
90
+ INS_AGFR = 10
91
+ INS_AGHI = 11
92
+ INS_AGHIK = 12
93
+ INS_AGR = 13
94
+ INS_AGRK = 14
95
+ INS_AGSI = 15
96
+ INS_AH = 16
97
+ INS_AHI = 17
98
+ INS_AHIK = 18
99
+ INS_AHY = 19
100
+ INS_AIH = 20
101
+ INS_AL = 21
102
+ INS_ALC = 22
103
+ INS_ALCG = 23
104
+ INS_ALCGR = 24
105
+ INS_ALCR = 25
106
+ INS_ALFI = 26
107
+ INS_ALG = 27
108
+ INS_ALGF = 28
109
+ INS_ALGFI = 29
110
+ INS_ALGFR = 30
111
+ INS_ALGHSIK = 31
112
+ INS_ALGR = 32
113
+ INS_ALGRK = 33
114
+ INS_ALHSIK = 34
115
+ INS_ALR = 35
116
+ INS_ALRK = 36
117
+ INS_ALY = 37
118
+ INS_AR = 38
119
+ INS_ARK = 39
120
+ INS_ASI = 40
121
+ INS_AXBR = 41
122
+ INS_AY = 42
123
+ INS_BCR = 43
124
+ INS_BRC = 44
125
+ INS_BRCL = 45
126
+ INS_CGIJ = 46
127
+ INS_CGRJ = 47
128
+ INS_CIJ = 48
129
+ INS_CLGIJ = 49
130
+ INS_CLGRJ = 50
131
+ INS_CLIJ = 51
132
+ INS_CLRJ = 52
133
+ INS_CRJ = 53
134
+ INS_BER = 54
135
+ INS_JE = 55
136
+ INS_JGE = 56
137
+ INS_LOCE = 57
138
+ INS_LOCGE = 58
139
+ INS_LOCGRE = 59
140
+ INS_LOCRE = 60
141
+ INS_STOCE = 61
142
+ INS_STOCGE = 62
143
+ INS_BHR = 63
144
+ INS_BHER = 64
145
+ INS_JHE = 65
146
+ INS_JGHE = 66
147
+ INS_LOCHE = 67
148
+ INS_LOCGHE = 68
149
+ INS_LOCGRHE = 69
150
+ INS_LOCRHE = 70
151
+ INS_STOCHE = 71
152
+ INS_STOCGHE = 72
153
+ INS_JH = 73
154
+ INS_JGH = 74
155
+ INS_LOCH = 75
156
+ INS_LOCGH = 76
157
+ INS_LOCGRH = 77
158
+ INS_LOCRH = 78
159
+ INS_STOCH = 79
160
+ INS_STOCGH = 80
161
+ INS_CGIJNLH = 81
162
+ INS_CGRJNLH = 82
163
+ INS_CIJNLH = 83
164
+ INS_CLGIJNLH = 84
165
+ INS_CLGRJNLH = 85
166
+ INS_CLIJNLH = 86
167
+ INS_CLRJNLH = 87
168
+ INS_CRJNLH = 88
169
+ INS_CGIJE = 89
170
+ INS_CGRJE = 90
171
+ INS_CIJE = 91
172
+ INS_CLGIJE = 92
173
+ INS_CLGRJE = 93
174
+ INS_CLIJE = 94
175
+ INS_CLRJE = 95
176
+ INS_CRJE = 96
177
+ INS_CGIJNLE = 97
178
+ INS_CGRJNLE = 98
179
+ INS_CIJNLE = 99
180
+ INS_CLGIJNLE = 100
181
+ INS_CLGRJNLE = 101
182
+ INS_CLIJNLE = 102
183
+ INS_CLRJNLE = 103
184
+ INS_CRJNLE = 104
185
+ INS_CGIJH = 105
186
+ INS_CGRJH = 106
187
+ INS_CIJH = 107
188
+ INS_CLGIJH = 108
189
+ INS_CLGRJH = 109
190
+ INS_CLIJH = 110
191
+ INS_CLRJH = 111
192
+ INS_CRJH = 112
193
+ INS_CGIJNL = 113
194
+ INS_CGRJNL = 114
195
+ INS_CIJNL = 115
196
+ INS_CLGIJNL = 116
197
+ INS_CLGRJNL = 117
198
+ INS_CLIJNL = 118
199
+ INS_CLRJNL = 119
200
+ INS_CRJNL = 120
201
+ INS_CGIJHE = 121
202
+ INS_CGRJHE = 122
203
+ INS_CIJHE = 123
204
+ INS_CLGIJHE = 124
205
+ INS_CLGRJHE = 125
206
+ INS_CLIJHE = 126
207
+ INS_CLRJHE = 127
208
+ INS_CRJHE = 128
209
+ INS_CGIJNHE = 129
210
+ INS_CGRJNHE = 130
211
+ INS_CIJNHE = 131
212
+ INS_CLGIJNHE = 132
213
+ INS_CLGRJNHE = 133
214
+ INS_CLIJNHE = 134
215
+ INS_CLRJNHE = 135
216
+ INS_CRJNHE = 136
217
+ INS_CGIJL = 137
218
+ INS_CGRJL = 138
219
+ INS_CIJL = 139
220
+ INS_CLGIJL = 140
221
+ INS_CLGRJL = 141
222
+ INS_CLIJL = 142
223
+ INS_CLRJL = 143
224
+ INS_CRJL = 144
225
+ INS_CGIJNH = 145
226
+ INS_CGRJNH = 146
227
+ INS_CIJNH = 147
228
+ INS_CLGIJNH = 148
229
+ INS_CLGRJNH = 149
230
+ INS_CLIJNH = 150
231
+ INS_CLRJNH = 151
232
+ INS_CRJNH = 152
233
+ INS_CGIJLE = 153
234
+ INS_CGRJLE = 154
235
+ INS_CIJLE = 155
236
+ INS_CLGIJLE = 156
237
+ INS_CLGRJLE = 157
238
+ INS_CLIJLE = 158
239
+ INS_CLRJLE = 159
240
+ INS_CRJLE = 160
241
+ INS_CGIJNE = 161
242
+ INS_CGRJNE = 162
243
+ INS_CIJNE = 163
244
+ INS_CLGIJNE = 164
245
+ INS_CLGRJNE = 165
246
+ INS_CLIJNE = 166
247
+ INS_CLRJNE = 167
248
+ INS_CRJNE = 168
249
+ INS_CGIJLH = 169
250
+ INS_CGRJLH = 170
251
+ INS_CIJLH = 171
252
+ INS_CLGIJLH = 172
253
+ INS_CLGRJLH = 173
254
+ INS_CLIJLH = 174
255
+ INS_CLRJLH = 175
256
+ INS_CRJLH = 176
257
+ INS_BLR = 177
258
+ INS_BLER = 178
259
+ INS_JLE = 179
260
+ INS_JGLE = 180
261
+ INS_LOCLE = 181
262
+ INS_LOCGLE = 182
263
+ INS_LOCGRLE = 183
264
+ INS_LOCRLE = 184
265
+ INS_STOCLE = 185
266
+ INS_STOCGLE = 186
267
+ INS_BLHR = 187
268
+ INS_JLH = 188
269
+ INS_JGLH = 189
270
+ INS_LOCLH = 190
271
+ INS_LOCGLH = 191
272
+ INS_LOCGRLH = 192
273
+ INS_LOCRLH = 193
274
+ INS_STOCLH = 194
275
+ INS_STOCGLH = 195
276
+ INS_JL = 196
277
+ INS_JGL = 197
278
+ INS_LOCL = 198
279
+ INS_LOCGL = 199
280
+ INS_LOCGRL = 200
281
+ INS_LOCRL = 201
282
+ INS_LOC = 202
283
+ INS_LOCG = 203
284
+ INS_LOCGR = 204
285
+ INS_LOCR = 205
286
+ INS_STOCL = 206
287
+ INS_STOCGL = 207
288
+ INS_BNER = 208
289
+ INS_JNE = 209
290
+ INS_JGNE = 210
291
+ INS_LOCNE = 211
292
+ INS_LOCGNE = 212
293
+ INS_LOCGRNE = 213
294
+ INS_LOCRNE = 214
295
+ INS_STOCNE = 215
296
+ INS_STOCGNE = 216
297
+ INS_BNHR = 217
298
+ INS_BNHER = 218
299
+ INS_JNHE = 219
300
+ INS_JGNHE = 220
301
+ INS_LOCNHE = 221
302
+ INS_LOCGNHE = 222
303
+ INS_LOCGRNHE = 223
304
+ INS_LOCRNHE = 224
305
+ INS_STOCNHE = 225
306
+ INS_STOCGNHE = 226
307
+ INS_JNH = 227
308
+ INS_JGNH = 228
309
+ INS_LOCNH = 229
310
+ INS_LOCGNH = 230
311
+ INS_LOCGRNH = 231
312
+ INS_LOCRNH = 232
313
+ INS_STOCNH = 233
314
+ INS_STOCGNH = 234
315
+ INS_BNLR = 235
316
+ INS_BNLER = 236
317
+ INS_JNLE = 237
318
+ INS_JGNLE = 238
319
+ INS_LOCNLE = 239
320
+ INS_LOCGNLE = 240
321
+ INS_LOCGRNLE = 241
322
+ INS_LOCRNLE = 242
323
+ INS_STOCNLE = 243
324
+ INS_STOCGNLE = 244
325
+ INS_BNLHR = 245
326
+ INS_JNLH = 246
327
+ INS_JGNLH = 247
328
+ INS_LOCNLH = 248
329
+ INS_LOCGNLH = 249
330
+ INS_LOCGRNLH = 250
331
+ INS_LOCRNLH = 251
332
+ INS_STOCNLH = 252
333
+ INS_STOCGNLH = 253
334
+ INS_JNL = 254
335
+ INS_JGNL = 255
336
+ INS_LOCNL = 256
337
+ INS_LOCGNL = 257
338
+ INS_LOCGRNL = 258
339
+ INS_LOCRNL = 259
340
+ INS_STOCNL = 260
341
+ INS_STOCGNL = 261
342
+ INS_BNOR = 262
343
+ INS_JNO = 263
344
+ INS_JGNO = 264
345
+ INS_LOCNO = 265
346
+ INS_LOCGNO = 266
347
+ INS_LOCGRNO = 267
348
+ INS_LOCRNO = 268
349
+ INS_STOCNO = 269
350
+ INS_STOCGNO = 270
351
+ INS_BOR = 271
352
+ INS_JO = 272
353
+ INS_JGO = 273
354
+ INS_LOCO = 274
355
+ INS_LOCGO = 275
356
+ INS_LOCGRO = 276
357
+ INS_LOCRO = 277
358
+ INS_STOCO = 278
359
+ INS_STOCGO = 279
360
+ INS_STOC = 280
361
+ INS_STOCG = 281
362
+ INS_BASR = 282
363
+ INS_BR = 283
364
+ INS_BRAS = 284
365
+ INS_BRASL = 285
366
+ INS_J = 286
367
+ INS_JG = 287
368
+ INS_BRCT = 288
369
+ INS_BRCTG = 289
370
+ INS_C = 290
371
+ INS_CDB = 291
372
+ INS_CDBR = 292
373
+ INS_CDFBR = 293
374
+ INS_CDGBR = 294
375
+ INS_CDLFBR = 295
376
+ INS_CDLGBR = 296
377
+ INS_CEB = 297
378
+ INS_CEBR = 298
379
+ INS_CEFBR = 299
380
+ INS_CEGBR = 300
381
+ INS_CELFBR = 301
382
+ INS_CELGBR = 302
383
+ INS_CFDBR = 303
384
+ INS_CFEBR = 304
385
+ INS_CFI = 305
386
+ INS_CFXBR = 306
387
+ INS_CG = 307
388
+ INS_CGDBR = 308
389
+ INS_CGEBR = 309
390
+ INS_CGF = 310
391
+ INS_CGFI = 311
392
+ INS_CGFR = 312
393
+ INS_CGFRL = 313
394
+ INS_CGH = 314
395
+ INS_CGHI = 315
396
+ INS_CGHRL = 316
397
+ INS_CGHSI = 317
398
+ INS_CGR = 318
399
+ INS_CGRL = 319
400
+ INS_CGXBR = 320
401
+ INS_CH = 321
402
+ INS_CHF = 322
403
+ INS_CHHSI = 323
404
+ INS_CHI = 324
405
+ INS_CHRL = 325
406
+ INS_CHSI = 326
407
+ INS_CHY = 327
408
+ INS_CIH = 328
409
+ INS_CL = 329
410
+ INS_CLC = 330
411
+ INS_CLFDBR = 331
412
+ INS_CLFEBR = 332
413
+ INS_CLFHSI = 333
414
+ INS_CLFI = 334
415
+ INS_CLFXBR = 335
416
+ INS_CLG = 336
417
+ INS_CLGDBR = 337
418
+ INS_CLGEBR = 338
419
+ INS_CLGF = 339
420
+ INS_CLGFI = 340
421
+ INS_CLGFR = 341
422
+ INS_CLGFRL = 342
423
+ INS_CLGHRL = 343
424
+ INS_CLGHSI = 344
425
+ INS_CLGR = 345
426
+ INS_CLGRL = 346
427
+ INS_CLGXBR = 347
428
+ INS_CLHF = 348
429
+ INS_CLHHSI = 349
430
+ INS_CLHRL = 350
431
+ INS_CLI = 351
432
+ INS_CLIH = 352
433
+ INS_CLIY = 353
434
+ INS_CLR = 354
435
+ INS_CLRL = 355
436
+ INS_CLST = 356
437
+ INS_CLY = 357
438
+ INS_CPSDR = 358
439
+ INS_CR = 359
440
+ INS_CRL = 360
441
+ INS_CS = 361
442
+ INS_CSG = 362
443
+ INS_CSY = 363
444
+ INS_CXBR = 364
445
+ INS_CXFBR = 365
446
+ INS_CXGBR = 366
447
+ INS_CXLFBR = 367
448
+ INS_CXLGBR = 368
449
+ INS_CY = 369
450
+ INS_DDB = 370
451
+ INS_DDBR = 371
452
+ INS_DEB = 372
453
+ INS_DEBR = 373
454
+ INS_DL = 374
455
+ INS_DLG = 375
456
+ INS_DLGR = 376
457
+ INS_DLR = 377
458
+ INS_DSG = 378
459
+ INS_DSGF = 379
460
+ INS_DSGFR = 380
461
+ INS_DSGR = 381
462
+ INS_DXBR = 382
463
+ INS_EAR = 383
464
+ INS_FIDBR = 384
465
+ INS_FIDBRA = 385
466
+ INS_FIEBR = 386
467
+ INS_FIEBRA = 387
468
+ INS_FIXBR = 388
469
+ INS_FIXBRA = 389
470
+ INS_FLOGR = 390
471
+ INS_IC = 391
472
+ INS_ICY = 392
473
+ INS_IIHF = 393
474
+ INS_IIHH = 394
475
+ INS_IIHL = 395
476
+ INS_IILF = 396
477
+ INS_IILH = 397
478
+ INS_IILL = 398
479
+ INS_IPM = 399
480
+ INS_L = 400
481
+ INS_LA = 401
482
+ INS_LAA = 402
483
+ INS_LAAG = 403
484
+ INS_LAAL = 404
485
+ INS_LAALG = 405
486
+ INS_LAN = 406
487
+ INS_LANG = 407
488
+ INS_LAO = 408
489
+ INS_LAOG = 409
490
+ INS_LARL = 410
491
+ INS_LAX = 411
492
+ INS_LAXG = 412
493
+ INS_LAY = 413
494
+ INS_LB = 414
495
+ INS_LBH = 415
496
+ INS_LBR = 416
497
+ INS_LCDBR = 417
498
+ INS_LCEBR = 418
499
+ INS_LCGFR = 419
500
+ INS_LCGR = 420
501
+ INS_LCR = 421
502
+ INS_LCXBR = 422
503
+ INS_LD = 423
504
+ INS_LDEB = 424
505
+ INS_LDEBR = 425
506
+ INS_LDGR = 426
507
+ INS_LDR = 427
508
+ INS_LDXBR = 428
509
+ INS_LDXBRA = 429
510
+ INS_LDY = 430
511
+ INS_LE = 431
512
+ INS_LEDBR = 432
513
+ INS_LEDBRA = 433
514
+ INS_LER = 434
515
+ INS_LEXBR = 435
516
+ INS_LEXBRA = 436
517
+ INS_LEY = 437
518
+ INS_LFH = 438
519
+ INS_LG = 439
520
+ INS_LGB = 440
521
+ INS_LGBR = 441
522
+ INS_LGDR = 442
523
+ INS_LGF = 443
524
+ INS_LGFI = 444
525
+ INS_LGFR = 445
526
+ INS_LGFRL = 446
527
+ INS_LGH = 447
528
+ INS_LGHI = 448
529
+ INS_LGHR = 449
530
+ INS_LGHRL = 450
531
+ INS_LGR = 451
532
+ INS_LGRL = 452
533
+ INS_LH = 453
534
+ INS_LHH = 454
535
+ INS_LHI = 455
536
+ INS_LHR = 456
537
+ INS_LHRL = 457
538
+ INS_LHY = 458
539
+ INS_LLC = 459
540
+ INS_LLCH = 460
541
+ INS_LLCR = 461
542
+ INS_LLGC = 462
543
+ INS_LLGCR = 463
544
+ INS_LLGF = 464
545
+ INS_LLGFR = 465
546
+ INS_LLGFRL = 466
547
+ INS_LLGH = 467
548
+ INS_LLGHR = 468
549
+ INS_LLGHRL = 469
550
+ INS_LLH = 470
551
+ INS_LLHH = 471
552
+ INS_LLHR = 472
553
+ INS_LLHRL = 473
554
+ INS_LLIHF = 474
555
+ INS_LLIHH = 475
556
+ INS_LLIHL = 476
557
+ INS_LLILF = 477
558
+ INS_LLILH = 478
559
+ INS_LLILL = 479
560
+ INS_LMG = 480
561
+ INS_LNDBR = 481
562
+ INS_LNEBR = 482
563
+ INS_LNGFR = 483
564
+ INS_LNGR = 484
565
+ INS_LNR = 485
566
+ INS_LNXBR = 486
567
+ INS_LPDBR = 487
568
+ INS_LPEBR = 488
569
+ INS_LPGFR = 489
570
+ INS_LPGR = 490
571
+ INS_LPR = 491
572
+ INS_LPXBR = 492
573
+ INS_LR = 493
574
+ INS_LRL = 494
575
+ INS_LRV = 495
576
+ INS_LRVG = 496
577
+ INS_LRVGR = 497
578
+ INS_LRVR = 498
579
+ INS_LT = 499
580
+ INS_LTDBR = 500
581
+ INS_LTEBR = 501
582
+ INS_LTG = 502
583
+ INS_LTGF = 503
584
+ INS_LTGFR = 504
585
+ INS_LTGR = 505
586
+ INS_LTR = 506
587
+ INS_LTXBR = 507
588
+ INS_LXDB = 508
589
+ INS_LXDBR = 509
590
+ INS_LXEB = 510
591
+ INS_LXEBR = 511
592
+ INS_LXR = 512
593
+ INS_LY = 513
594
+ INS_LZDR = 514
595
+ INS_LZER = 515
596
+ INS_LZXR = 516
597
+ INS_MADB = 517
598
+ INS_MADBR = 518
599
+ INS_MAEB = 519
600
+ INS_MAEBR = 520
601
+ INS_MDB = 521
602
+ INS_MDBR = 522
603
+ INS_MDEB = 523
604
+ INS_MDEBR = 524
605
+ INS_MEEB = 525
606
+ INS_MEEBR = 526
607
+ INS_MGHI = 527
608
+ INS_MH = 528
609
+ INS_MHI = 529
610
+ INS_MHY = 530
611
+ INS_MLG = 531
612
+ INS_MLGR = 532
613
+ INS_MS = 533
614
+ INS_MSDB = 534
615
+ INS_MSDBR = 535
616
+ INS_MSEB = 536
617
+ INS_MSEBR = 537
618
+ INS_MSFI = 538
619
+ INS_MSG = 539
620
+ INS_MSGF = 540
621
+ INS_MSGFI = 541
622
+ INS_MSGFR = 542
623
+ INS_MSGR = 543
624
+ INS_MSR = 544
625
+ INS_MSY = 545
626
+ INS_MVC = 546
627
+ INS_MVGHI = 547
628
+ INS_MVHHI = 548
629
+ INS_MVHI = 549
630
+ INS_MVI = 550
631
+ INS_MVIY = 551
632
+ INS_MVST = 552
633
+ INS_MXBR = 553
634
+ INS_MXDB = 554
635
+ INS_MXDBR = 555
636
+ INS_N = 556
637
+ INS_NC = 557
638
+ INS_NG = 558
639
+ INS_NGR = 559
640
+ INS_NGRK = 560
641
+ INS_NI = 561
642
+ INS_NIHF = 562
643
+ INS_NIHH = 563
644
+ INS_NIHL = 564
645
+ INS_NILF = 565
646
+ INS_NILH = 566
647
+ INS_NILL = 567
648
+ INS_NIY = 568
649
+ INS_NR = 569
650
+ INS_NRK = 570
651
+ INS_NY = 571
652
+ INS_O = 572
653
+ INS_OC = 573
654
+ INS_OG = 574
655
+ INS_OGR = 575
656
+ INS_OGRK = 576
657
+ INS_OI = 577
658
+ INS_OIHF = 578
659
+ INS_OIHH = 579
660
+ INS_OIHL = 580
661
+ INS_OILF = 581
662
+ INS_OILH = 582
663
+ INS_OILL = 583
664
+ INS_OIY = 584
665
+ INS_OR = 585
666
+ INS_ORK = 586
667
+ INS_OY = 587
668
+ INS_PFD = 588
669
+ INS_PFDRL = 589
670
+ INS_RISBG = 590
671
+ INS_RISBHG = 591
672
+ INS_RISBLG = 592
673
+ INS_RLL = 593
674
+ INS_RLLG = 594
675
+ INS_RNSBG = 595
676
+ INS_ROSBG = 596
677
+ INS_RXSBG = 597
678
+ INS_S = 598
679
+ INS_SDB = 599
680
+ INS_SDBR = 600
681
+ INS_SEB = 601
682
+ INS_SEBR = 602
683
+ INS_SG = 603
684
+ INS_SGF = 604
685
+ INS_SGFR = 605
686
+ INS_SGR = 606
687
+ INS_SGRK = 607
688
+ INS_SH = 608
689
+ INS_SHY = 609
690
+ INS_SL = 610
691
+ INS_SLB = 611
692
+ INS_SLBG = 612
693
+ INS_SLBR = 613
694
+ INS_SLFI = 614
695
+ INS_SLG = 615
696
+ INS_SLBGR = 616
697
+ INS_SLGF = 617
698
+ INS_SLGFI = 618
699
+ INS_SLGFR = 619
700
+ INS_SLGR = 620
701
+ INS_SLGRK = 621
702
+ INS_SLL = 622
703
+ INS_SLLG = 623
704
+ INS_SLLK = 624
705
+ INS_SLR = 625
706
+ INS_SLRK = 626
707
+ INS_SLY = 627
708
+ INS_SQDB = 628
709
+ INS_SQDBR = 629
710
+ INS_SQEB = 630
711
+ INS_SQEBR = 631
712
+ INS_SQXBR = 632
713
+ INS_SR = 633
714
+ INS_SRA = 634
715
+ INS_SRAG = 635
716
+ INS_SRAK = 636
717
+ INS_SRK = 637
718
+ INS_SRL = 638
719
+ INS_SRLG = 639
720
+ INS_SRLK = 640
721
+ INS_SRST = 641
722
+ INS_ST = 642
723
+ INS_STC = 643
724
+ INS_STCH = 644
725
+ INS_STCY = 645
726
+ INS_STD = 646
727
+ INS_STDY = 647
728
+ INS_STE = 648
729
+ INS_STEY = 649
730
+ INS_STFH = 650
731
+ INS_STG = 651
732
+ INS_STGRL = 652
733
+ INS_STH = 653
734
+ INS_STHH = 654
735
+ INS_STHRL = 655
736
+ INS_STHY = 656
737
+ INS_STMG = 657
738
+ INS_STRL = 658
739
+ INS_STRV = 659
740
+ INS_STRVG = 660
741
+ INS_STY = 661
742
+ INS_SXBR = 662
743
+ INS_SY = 663
744
+ INS_TM = 664
745
+ INS_TMHH = 665
746
+ INS_TMHL = 666
747
+ INS_TMLH = 667
748
+ INS_TMLL = 668
749
+ INS_TMY = 669
750
+ INS_X = 670
751
+ INS_XC = 671
752
+ INS_XG = 672
753
+ INS_XGR = 673
754
+ INS_XGRK = 674
755
+ INS_XI = 675
756
+ INS_XIHF = 676
757
+ INS_XILF = 677
758
+ INS_XIY = 678
759
+ INS_XR = 679
760
+ INS_XRK = 680
761
+ INS_XY = 681
762
+ INS_ENDING = 682
763
+
764
+ # Group of SystemZ instructions
765
+
766
+ GRP_INVALID = 0
767
+
768
+ # Generic groups
769
+ GRP_JUMP = 1
770
+
771
+ # Architecture-specific groups
772
+ GRP_DISTINCTOPS = 128
773
+ GRP_FPEXTENSION = 129
774
+ GRP_HIGHWORD = 130
775
+ GRP_INTERLOCKEDACCESS1 = 131
776
+ GRP_LOADSTOREONCOND = 132
777
+ GRP_ENDING = 133
778
+ end
779
+ end