crabstone 3.0.3

data/test/test_arm.rb

@@ -0,0 +1,202 @@
+#! /usr/bin/env ruby
+
+# Library by Nguyen Anh Quynh
+# Original binding by Nguyen Anh Quynh and Tan Sheng Di
+# Additional binding work by Ben Nagy
+# (c) 2013 COSEINC. All Rights Reserved.
+
+require 'crabstone'
+require 'stringio'
+
+module TestARM
+
+  include Crabstone
+  include Crabstone::ARM
+
+  ARM_CODE     = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
+  ARM_CODE2    = "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
+  THUMB_CODE   = "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84"
+  THUMB_CODE2  = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
+  THUMB_MCLASS = "\xef\xf3\x02\x80"
+  ARMV8        = "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
+
+  @platforms = [
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_ARM,
+      'code' => ARM_CODE,
+      'comment' => "ARM"
+    ],
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_THUMB,
+      'code' => THUMB_CODE,
+      'comment' => "Thumb"
+    ],
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_THUMB,
+      'code' => ARM_CODE2,
+      'comment' => "Thumb-mixed"
+    ],
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_THUMB,
+      'code' => THUMB_CODE2,
+      'comment' => "Thumb-2 & register named with numbers",
+      'syntax' => :no_regname
+    ],
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_THUMB + MODE_MCLASS,
+      'code' => THUMB_MCLASS,
+      'comment' => "Thumb-MClass",
+      'syntax' => :no_regname
+    ],
+    Hash[
+      'arch' => ARCH_ARM,
+      'mode' => MODE_ARM + MODE_V8,
+      'code' => ARMV8,
+      'comment' => "Arm-V8",
+      'syntax' => :no_regname
+    ],
+  ]
+
+  def self.uint32 i
+    Integer(i) & 0xffffffff
+  end
+
+  def self.uint64 i
+    Integer(i) & ((1<<64)-1)
+  end
+
+  def self.print_detail(cs, i, sio)
+
+    # Sanity checks for register equivalency (string, const or numeric literal)
+    if i.reads_reg?( 'sp' ) || i.reads_reg?( 12 ) || i.reads_reg?( REG_SP )
+      unless i.reads_reg?( 'sp' ) && i.reads_reg?( 12 ) && i.reads_reg?( REG_SP )
+        fail "Error in reg read decomposition"
+      end
+    end
+    if i.writes_reg?( 'lr' ) || i.writes_reg?( 10 ) || i.writes_reg?( REG_LR )
+      unless i.writes_reg?( 'lr' ) && i.writes_reg?( 10 ) && i.writes_reg?( REG_LR )
+        fail "Error in reg write decomposition"
+      end
+    end
+
+    if i.op_count > 0 then
+      sio.puts "\top_count: #{i.op_count}"
+      i.operands.each.with_index do |op,idx|
+
+        case op[:type]
+        when OP_REG
+          sio.puts "\t\toperands[#{idx}].type: REG = #{cs.reg_name(op[:value][:reg])}"
+        when OP_IMM
+          sio.puts "\t\toperands[#{idx}].type: IMM = 0x#{self.uint64(op.value).to_s(16)}"
+        when OP_FP
+          sio.puts "\t\toperands[#{idx}].type: FP = 0x#{self.uint32(op[:value][:fp])}"
+        when OP_CIMM
+          sio.puts "\t\toperands[#{idx}].type: C-IMM = #{self.uint32(op[:value][:imm])}"
+        when OP_PIMM
+          sio.puts "\t\toperands[#{idx}].type: P-IMM = #{self.uint32(op[:value][:imm])}"
+        when OP_SETEND
+          if op.value == SETEND_BE
+            sio.puts "\t\toperands[#{idx}].type: SETEND = be"
+          else
+            sio.puts "\t\toperands[#{idx}].type: SETEND = le"
+          end
+        when OP_SYSREG
+          sio.puts "\t\toperands[#{idx}].type: SYSREG = #{op.value}"
+        when OP_MEM
+          sio.puts "\t\toperands[#{idx}].type: MEM"
+          if op[:value][:mem][:base] != 0 then
+            sio.puts "\t\t\toperands[#{idx}].mem.base: REG = %s" % cs.reg_name(op.value[:base])
+          end
+          if op[:value][:mem][:index] != 0 then
+            sio.puts "\t\t\toperands[#{idx}].mem.index: REG = %s" % cs.reg_name(op.value[:index])
+          end
+          if op[:value][:mem][:scale] != 1 then
+            sio.puts "\t\t\toperands[#{idx}].mem.scale = %u" % op[:value][:mem][:scale]
+          end
+          if op[:value][:mem][:disp] != 0 then
+            sio.puts "\t\t\toperands[#{idx}].mem.disp: 0x#{self.uint32(op.value[:disp]).to_s(16)}"
+          end
+        else
+          # unknown type - test will fail anyway
+        end
+
+        if op[:shift][:type].nonzero? && op[:shift][:value]
+          sio.puts "\t\t\tShift: #{op[:shift][:type]} = #{op[:shift][:value]}"
+        end
+
+        if op[:vector_index] != -1
+          sio.puts "\t\toperands[#{idx}].vector_index = #{op[:vector_index]}"
+        end
+
+        if op[:subtracted]
+          sio.puts "\t\tSubtracted: True\n"
+        end
+
+      end
+    end
+
+    if not [CC_AL, CC_INVALID].include? i.cc
+      sio.puts "\tCode condition: #{i.cc}"
+    end
+    sio.puts "\tUpdate-flags: True" if i.update_flags
+    sio.puts "\tWrite-back: True" if i.writeback
+    sio.puts "\tCPSI-mode: #{i.cps_mode}" if i.cps_mode.nonzero?
+    sio.puts "\tCPSI-flag: #{i.cps_flag}" if i.cps_flag.nonzero?
+    sio.puts "\tVector-data: #{i.vector_data}" if i.vector_data.nonzero?
+    sio.puts "\tVector-size: #{i.vector_size}" if i.vector_size.nonzero?
+    sio.puts "\tUser-mode: True" if i.usermode
+    sio.puts "\tMemory-barrier: #{i.mem_barrier}" if i.mem_barrier.nonzero?
+
+    sio.puts
+
+  end
+
+  ours = StringIO.new
+
+  begin
+    cs = Disassembler.new(0,0)
+    print "ARM Test: Capstone v #{cs.version.join('.')} - "
+  ensure
+    cs.close
+  end
+
+  #Test through all modes and architectures
+  @platforms.each do |p|
+    ours.puts "****************"
+    ours.puts "Platform: #{p['comment']}"
+    ours.puts "Code:#{p['code'].bytes.map {|b| "0x%.2x" % b}.join(' ')} "
+    ours.puts "Disasm:"
+    cs = Disassembler.new(p['arch'], p['mode'])
+
+    if p['syntax']
+      cs.syntax = p['syntax']
+    end
+
+    cs.decomposer = true
+    cache = nil
+    cs.disasm(p['code'], 0x1000).each {|insn|
+      ours.puts "0x#{insn.address.to_s(16)}:\t#{insn.mnemonic}\t#{insn.op_str}"
+      self.print_detail(cs, insn, ours)
+      cache = insn.address + insn.size
+    }
+    ours.printf("0x%x:\n", cache)
+    ours.puts
+
+    cs.close
+  end
+
+  ours.rewind
+  theirs = File.binread(__FILE__ + ".SPEC")
+  if ours.read == theirs
+    puts "#{__FILE__}: PASS"
+  else
+    ours.rewind
+    puts ours.read
+    puts "#{__FILE__}: FAIL"
+  end
+end

data/test/test_arm.rb.SPEC

@@ -0,0 +1,275 @@
+****************
+Platform: ARM
+Code:0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 0x00 0x02 0x01 0xf1 0x05 0x40 0xd0 0xe8 0xf4 0x80 0x00 0x00 
+Disasm:
+0x1000:	bl	#0xfbc
+	op_count: 1
+		operands[0].type: IMM = 0xfbc
+
+0x1004:	str	lr, [sp, #-4]!
+	op_count: 2
+		operands[0].type: REG = lr
+		operands[1].type: MEM
+			operands[1].mem.base: REG = sp
+			operands[1].mem.disp: 0xfffffffc
+	Write-back: True
+
+0x1008:	andeq	r0, r0, r0
+	op_count: 3
+		operands[0].type: REG = r0
+		operands[1].type: REG = r0
+		operands[2].type: REG = r0
+	Code condition: 1
+
+0x100c:	str	r8, [r2, #-0x3e0]!
+	op_count: 2
+		operands[0].type: REG = r8
+		operands[1].type: MEM
+			operands[1].mem.base: REG = r2
+			operands[1].mem.disp: 0xfffffc20
+	Write-back: True
+
+0x1010:	mcreq	p2, #0, r0, c3, c1, #7
+	op_count: 6
+		operands[0].type: P-IMM = 2
+		operands[1].type: IMM = 0x0
+		operands[2].type: REG = r0
+		operands[3].type: C-IMM = 3
+		operands[4].type: C-IMM = 1
+		operands[5].type: IMM = 0x7
+	Code condition: 1
+
+0x1014:	mov	r0, #0
+	op_count: 2
+		operands[0].type: REG = r0
+		operands[1].type: IMM = 0x0
+
+0x1018:	strb	r3, [r1, r2]
+	op_count: 2
+		operands[0].type: REG = r3
+		operands[1].type: MEM
+			operands[1].mem.base: REG = r1
+			operands[1].mem.index: REG = r2
+
+0x101c:	cmp	r3, #0
+	op_count: 2
+		operands[0].type: REG = r3
+		operands[1].type: IMM = 0x0
+	Update-flags: True
+
+0x1020:	setend	be
+	op_count: 1
+		operands[0].type: SETEND = be
+
+0x1024:	ldm	r0, {r0, r2, lr} ^
+	op_count: 4
+		operands[0].type: REG = r0
+		operands[1].type: REG = r0
+		operands[2].type: REG = r2
+		operands[3].type: REG = lr
+	User-mode: True
+
+0x1028:	strdeq	r8, sb, [r0], -r4
+	op_count: 4
+		operands[0].type: REG = r8
+		operands[1].type: REG = sb
+		operands[2].type: MEM
+			operands[2].mem.base: REG = r0
+		operands[3].type: REG = r4
+		Subtracted: True
+	Code condition: 1
+	Write-back: True
+
+0x102c:
+
+****************
+Platform: Thumb
+Code:0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 0x1f 0xb1 0x30 0xbf 0xaf 0xf3 0x20 0x84 
+Disasm:
+0x1000:	bx	lr
+	op_count: 1
+		operands[0].type: REG = lr
+
+0x1002:	mov	fp, sp
+	op_count: 2
+		operands[0].type: REG = fp
+		operands[1].type: REG = sp
+
+0x1004:	sub	sp, #0xc
+	op_count: 2
+		operands[0].type: REG = sp
+		operands[1].type: IMM = 0xc
+
+0x1006:	ldr	r1, [r1, #0xc]
+	op_count: 2
+		operands[0].type: REG = r1
+		operands[1].type: MEM
+			operands[1].mem.base: REG = r1
+			operands[1].mem.disp: 0xc
+
+0x1008:	cbz	r7, #0x1012
+	op_count: 2
+		operands[0].type: REG = r7
+		operands[1].type: IMM = 0x1012
+
+0x100a:	wfi	
+
+0x100c:	cpsie.w	f
+	CPSI-mode: 2
+	CPSI-flag: 1
+
+0x1010:
+
+****************
+Platform: Thumb-mixed
+Code:0xd1 0xe8 0x00 0xf0 0xf0 0x24 0x04 0x07 0x1f 0x3c 0xf2 0xc0 0x00 0x00 0x4f 0xf0 0x00 0x01 0x46 0x6c 
+Disasm:
+0x1000:	tbb	[r1, r0]
+	op_count: 1
+		operands[0].type: MEM
+			operands[0].mem.base: REG = r1
+			operands[0].mem.index: REG = r0
+
+0x1004:	movs	r4, #0xf0
+	op_count: 2
+		operands[0].type: REG = r4
+		operands[1].type: IMM = 0xf0
+	Update-flags: True
+
+0x1006:	lsls	r4, r0, #0x1c
+	op_count: 3
+		operands[0].type: REG = r4
+		operands[1].type: REG = r0
+		operands[2].type: IMM = 0x1c
+	Update-flags: True
+
+0x1008:	subs	r4, #0x1f
+	op_count: 2
+		operands[0].type: REG = r4
+		operands[1].type: IMM = 0x1f
+	Update-flags: True
+
+0x100a:	stm	r0!, {r1, r4, r5, r6, r7}
+	op_count: 6
+		operands[0].type: REG = r0
+		operands[1].type: REG = r1
+		operands[2].type: REG = r4
+		operands[3].type: REG = r5
+		operands[4].type: REG = r6
+		operands[5].type: REG = r7
+	Write-back: True
+
+0x100c:	movs	r0, r0
+	op_count: 2
+		operands[0].type: REG = r0
+		operands[1].type: REG = r0
+	Update-flags: True
+
+0x100e:	mov.w	r1, #0
+	op_count: 2
+		operands[0].type: REG = r1
+		operands[1].type: IMM = 0x0
+
+0x1012:	ldr	r6, [r0, #0x44]
+	op_count: 2
+		operands[0].type: REG = r6
+		operands[1].type: MEM
+			operands[1].mem.base: REG = r0
+			operands[1].mem.disp: 0x44
+
+0x1014:
+
+****************
+Platform: Thumb-2 & register named with numbers
+Code:0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 0x18 0xbf 0xad 0xbf 0xf3 0xff 0x0b 0x0c 0x86 0xf3 0x00 0x89 0x80 0xf3 0x00 0x8c 0x4f 0xfa 0x99 0xf6 0xd0 0xff 0xa2 0x01 
+Disasm:
+0x1000:	mov.w	r1, #0
+	op_count: 2
+		operands[0].type: REG = r1
+		operands[1].type: IMM = 0x0
+
+0x1004:	pop.w	{r11, pc}
+	op_count: 2
+		operands[0].type: REG = r11
+		operands[1].type: REG = pc
+
+0x1008:	tbb	[r1, r0]
+	op_count: 1
+		operands[0].type: MEM
+			operands[0].mem.base: REG = r1
+			operands[0].mem.index: REG = r0
+
+0x100c:	it	ne
+	Code condition: 2
+
+0x100e:	iteet	ge
+	Code condition: 11
+
+0x1010:	vdupge.8	d16, d11[1]
+	op_count: 2
+		operands[0].type: REG = d16
+		operands[1].type: REG = d11
+		operands[1].vector_index = 1
+	Code condition: 11
+	Vector-size: 8
+
+0x1014:	msrlt	cpsr_fc, r6
+	op_count: 2
+		operands[0].type: SYSREG = 144
+		operands[1].type: REG = r6
+	Code condition: 12
+
+0x1018:	msrlt	apsr_nzcvqg, r0
+	op_count: 2
+		operands[0].type: SYSREG = 259
+		operands[1].type: REG = r0
+	Code condition: 12
+
+0x101c:	sxtbge.w	r6, r9, ror #8
+	op_count: 2
+		operands[0].type: REG = r6
+		operands[1].type: REG = r9
+			Shift: 4 = 8
+	Code condition: 11
+
+0x1020:	vaddw.u16	q8, q8, d18
+	op_count: 3
+		operands[0].type: REG = q8
+		operands[1].type: REG = q8
+		operands[2].type: REG = d18
+	Vector-data: 10
+
+0x1024:
+
+****************
+Platform: Thumb-MClass
+Code:0xef 0xf3 0x02 0x80 
+Disasm:
+0x1000:	mrs	r0, eapsr
+	op_count: 2
+		operands[0].type: REG = r0
+		operands[1].type: SYSREG = 263
+
+0x1004:
+
+****************
+Platform: Arm-V8
+Code:0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
+Disasm:
+0x1000:	vcvtt.f64.f16	d3, s1
+	op_count: 2
+		operands[0].type: REG = d3
+		operands[1].type: REG = s1
+	Vector-data: 17
+
+0x1004:	crc32b	r0, r1, r2
+	op_count: 3
+		operands[0].type: REG = r0
+		operands[1].type: REG = r1
+		operands[2].type: REG = r2
+
+0x1008:	dmb	oshld
+	Memory-barrier: 2
+
+0x100c:
+