crabstone 3.0.3
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- checksums.yaml +7 -0
- data/CHANGES.md +61 -0
- data/LICENSE +25 -0
- data/MANIFEST +312 -0
- data/README.md +103 -0
- data/Rakefile +27 -0
- data/bin/genconst +66 -0
- data/bin/genreg +99 -0
- data/crabstone.gemspec +27 -0
- data/examples/hello_world.rb +43 -0
- data/lib/arch/arm.rb +128 -0
- data/lib/arch/arm64.rb +167 -0
- data/lib/arch/arm64_const.rb +1055 -0
- data/lib/arch/arm64_registers.rb +295 -0
- data/lib/arch/arm_const.rb +777 -0
- data/lib/arch/arm_registers.rb +149 -0
- data/lib/arch/mips.rb +78 -0
- data/lib/arch/mips_const.rb +850 -0
- data/lib/arch/mips_registers.rb +208 -0
- data/lib/arch/ppc.rb +90 -0
- data/lib/arch/ppc_const.rb +1181 -0
- data/lib/arch/ppc_registers.rb +209 -0
- data/lib/arch/sparc.rb +79 -0
- data/lib/arch/sparc_const.rb +461 -0
- data/lib/arch/sparc_registers.rb +121 -0
- data/lib/arch/systemz.rb +79 -0
- data/lib/arch/sysz_const.rb +779 -0
- data/lib/arch/sysz_registers.rb +66 -0
- data/lib/arch/x86.rb +107 -0
- data/lib/arch/x86_const.rb +1698 -0
- data/lib/arch/x86_registers.rb +265 -0
- data/lib/arch/xcore.rb +78 -0
- data/lib/arch/xcore_const.rb +185 -0
- data/lib/arch/xcore_registers.rb +57 -0
- data/lib/crabstone.rb +564 -0
- data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
- data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
- data/test/MC/AArch64/neon-2velem.s.cs +113 -0
- data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
- data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
- data/test/MC/AArch64/neon-across.s.cs +40 -0
- data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
- data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
- data/test/MC/AArch64/neon-crypto.s.cs +15 -0
- data/test/MC/AArch64/neon-extract.s.cs +3 -0
- data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
- data/test/MC/AArch64/neon-max-min.s.cs +37 -0
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
- data/test/MC/AArch64/neon-mov.s.cs +74 -0
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
- data/test/MC/AArch64/neon-perm.s.cs +43 -0
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
- data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
- data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
- data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
- data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
- data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
- data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
- data/test/MC/AArch64/neon-shift.s.cs +22 -0
- data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
- data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
- data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
- data/test/MC/AArch64/neon-tbl.s.cs +21 -0
- data/test/MC/AArch64/trace-regs.s.cs +383 -0
- data/test/MC/ARM/arm-aliases.s.cs +7 -0
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
- data/test/MC/ARM/arm-it-block.s.cs +2 -0
- data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
- data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
- data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
- data/test/MC/ARM/arm_instructions.s.cs +25 -0
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
- data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
- data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
- data/test/MC/ARM/crc32-thumb.s.cs +7 -0
- data/test/MC/ARM/crc32.s.cs +7 -0
- data/test/MC/ARM/dot-req.s.cs +3 -0
- data/test/MC/ARM/fp-armv8.s.cs +52 -0
- data/test/MC/ARM/idiv-thumb.s.cs +3 -0
- data/test/MC/ARM/idiv.s.cs +3 -0
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
- data/test/MC/ARM/mode-switch.s.cs +7 -0
- data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
- data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
- data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
- data/test/MC/ARM/neon-crypto.s.cs +16 -0
- data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
- data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
- data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
- data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neon-v8.s.cs +38 -0
- data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
- data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
- data/test/MC/ARM/neon-vswp.s.cs +3 -0
- data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
- data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
- data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
- data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
- data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
- data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
- data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
- data/test/MC/ARM/thumb-hints.s.cs +12 -0
- data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
- data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
- data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
- data/test/MC/ARM/thumb.s.cs +19 -0
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
- data/test/MC/ARM/thumb2-branches.s.cs +85 -0
- data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
- data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
- data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
- data/test/MC/ARM/vfp4.s.cs +13 -0
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
- data/test/MC/ARM/vpush-vpop.s.cs +9 -0
- data/test/MC/Mips/hilo-addressing.s.cs +4 -0
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
- data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
- data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
- data/test/MC/Mips/micromips-expansions.s.cs +20 -0
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
- data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
- data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
- data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
- data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
- data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
- data/test/MC/Mips/mips-expansions.s.cs +20 -0
- data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
- data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
- data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
- data/test/MC/Mips/mips-register-names.s.cs +33 -0
- data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
- data/test/MC/Mips/mips64-instructions.s.cs +3 -0
- data/test/MC/Mips/mips64-register-names.s.cs +33 -0
- data/test/MC/Mips/mips_directives.s.cs +12 -0
- data/test/MC/Mips/nabi-regs.s.cs +12 -0
- data/test/MC/Mips/set-at-directive.s.cs +6 -0
- data/test/MC/Mips/test_2r.s.cs +16 -0
- data/test/MC/Mips/test_2rf.s.cs +33 -0
- data/test/MC/Mips/test_3r.s.cs +243 -0
- data/test/MC/Mips/test_3rf.s.cs +83 -0
- data/test/MC/Mips/test_bit.s.cs +49 -0
- data/test/MC/Mips/test_cbranch.s.cs +11 -0
- data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
- data/test/MC/Mips/test_elm.s.cs +16 -0
- data/test/MC/Mips/test_elm_insert.s.cs +4 -0
- data/test/MC/Mips/test_elm_insve.s.cs +5 -0
- data/test/MC/Mips/test_i10.s.cs +5 -0
- data/test/MC/Mips/test_i5.s.cs +45 -0
- data/test/MC/Mips/test_i8.s.cs +11 -0
- data/test/MC/Mips/test_lsa.s.cs +5 -0
- data/test/MC/Mips/test_mi10.s.cs +24 -0
- data/test/MC/Mips/test_vec.s.cs +8 -0
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
- data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
- data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
- data/test/MC/README +6 -0
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
- data/test/MC/Sparc/sparc-vis.s.cs +2 -0
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
- data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
- data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
- data/test/MC/SystemZ/insn-good.s.cs +2265 -0
- data/test/MC/SystemZ/regs-good.s.cs +45 -0
- data/test/MC/X86/3DNow.s.cs +29 -0
- data/test/MC/X86/address-size.s.cs +5 -0
- data/test/MC/X86/avx512-encodings.s.cs +12 -0
- data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
- data/test/MC/X86/x86-32-avx.s.cs +833 -0
- data/test/MC/X86/x86-32-fma3.s.cs +169 -0
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
- data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
- data/test/MC/X86/x86_64-encoding.s.cs +59 -0
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
- data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
- data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
- data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
- data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
- data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
- data/test/README +6 -0
- data/test/test.rb +205 -0
- data/test/test.rb.SPEC +235 -0
- data/test/test_arm.rb +202 -0
- data/test/test_arm.rb.SPEC +275 -0
- data/test/test_arm64.rb +150 -0
- data/test/test_arm64.rb.SPEC +116 -0
- data/test/test_detail.rb +228 -0
- data/test/test_detail.rb.SPEC +322 -0
- data/test/test_exhaustive.rb +80 -0
- data/test/test_mips.rb +118 -0
- data/test/test_mips.rb.SPEC +91 -0
- data/test/test_ppc.rb +137 -0
- data/test/test_ppc.rb.SPEC +84 -0
- data/test/test_sanity.rb +83 -0
- data/test/test_skipdata.rb +111 -0
- data/test/test_skipdata.rb.SPEC +58 -0
- data/test/test_sparc.rb +113 -0
- data/test/test_sparc.rb.SPEC +116 -0
- data/test/test_sysz.rb +111 -0
- data/test/test_sysz.rb.SPEC +61 -0
- data/test/test_x86.rb +189 -0
- data/test/test_x86.rb.SPEC +579 -0
- data/test/test_xcore.rb +100 -0
- data/test/test_xcore.rb.SPEC +75 -0
- metadata +393 -0
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# Library by Nguyen Anh Quynh
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# Original binding by Nguyen Anh Quynh and Tan Sheng Di
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# Additional binding work by Ben Nagy
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# (c) 2013 COSEINC. All Rights Reserved.
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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# Command: ./genreg /Users/ben/src/capstone/bindings/python/capstone/
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# 2015-05-02T13:24:07+12:00
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module Crabstone
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module ARM
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REG_LOOKUP = {
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'INVALID' => 0,
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'APSR' => 1,
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'APSR_NZCV' => 2,
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'CPSR' => 3,
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'FPEXC' => 4,
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'FPINST' => 5,
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'FPSCR' => 6,
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'FPSCR_NZCV' => 7,
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'FPSID' => 8,
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'ITSTATE' => 9,
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'LR' => 10,
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'PC' => 11,
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'SP' => 12,
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+
'SPSR' => 13,
|
27
|
+
'D0' => 14,
|
28
|
+
'D1' => 15,
|
29
|
+
'D2' => 16,
|
30
|
+
'D3' => 17,
|
31
|
+
'D4' => 18,
|
32
|
+
'D5' => 19,
|
33
|
+
'D6' => 20,
|
34
|
+
'D7' => 21,
|
35
|
+
'D8' => 22,
|
36
|
+
'D9' => 23,
|
37
|
+
'D10' => 24,
|
38
|
+
'D11' => 25,
|
39
|
+
'D12' => 26,
|
40
|
+
'D13' => 27,
|
41
|
+
'D14' => 28,
|
42
|
+
'D15' => 29,
|
43
|
+
'D16' => 30,
|
44
|
+
'D17' => 31,
|
45
|
+
'D18' => 32,
|
46
|
+
'D19' => 33,
|
47
|
+
'D20' => 34,
|
48
|
+
'D21' => 35,
|
49
|
+
'D22' => 36,
|
50
|
+
'D23' => 37,
|
51
|
+
'D24' => 38,
|
52
|
+
'D25' => 39,
|
53
|
+
'D26' => 40,
|
54
|
+
'D27' => 41,
|
55
|
+
'D28' => 42,
|
56
|
+
'D29' => 43,
|
57
|
+
'D30' => 44,
|
58
|
+
'D31' => 45,
|
59
|
+
'FPINST2' => 46,
|
60
|
+
'MVFR0' => 47,
|
61
|
+
'MVFR1' => 48,
|
62
|
+
'MVFR2' => 49,
|
63
|
+
'Q0' => 50,
|
64
|
+
'Q1' => 51,
|
65
|
+
'Q2' => 52,
|
66
|
+
'Q3' => 53,
|
67
|
+
'Q4' => 54,
|
68
|
+
'Q5' => 55,
|
69
|
+
'Q6' => 56,
|
70
|
+
'Q7' => 57,
|
71
|
+
'Q8' => 58,
|
72
|
+
'Q9' => 59,
|
73
|
+
'Q10' => 60,
|
74
|
+
'Q11' => 61,
|
75
|
+
'Q12' => 62,
|
76
|
+
'Q13' => 63,
|
77
|
+
'Q14' => 64,
|
78
|
+
'Q15' => 65,
|
79
|
+
'R0' => 66,
|
80
|
+
'R1' => 67,
|
81
|
+
'R2' => 68,
|
82
|
+
'R3' => 69,
|
83
|
+
'R4' => 70,
|
84
|
+
'R5' => 71,
|
85
|
+
'R6' => 72,
|
86
|
+
'R7' => 73,
|
87
|
+
'R8' => 74,
|
88
|
+
'R9' => 75,
|
89
|
+
'R10' => 76,
|
90
|
+
'R11' => 77,
|
91
|
+
'R12' => 78,
|
92
|
+
'S0' => 79,
|
93
|
+
'S1' => 80,
|
94
|
+
'S2' => 81,
|
95
|
+
'S3' => 82,
|
96
|
+
'S4' => 83,
|
97
|
+
'S5' => 84,
|
98
|
+
'S6' => 85,
|
99
|
+
'S7' => 86,
|
100
|
+
'S8' => 87,
|
101
|
+
'S9' => 88,
|
102
|
+
'S10' => 89,
|
103
|
+
'S11' => 90,
|
104
|
+
'S12' => 91,
|
105
|
+
'S13' => 92,
|
106
|
+
'S14' => 93,
|
107
|
+
'S15' => 94,
|
108
|
+
'S16' => 95,
|
109
|
+
'S17' => 96,
|
110
|
+
'S18' => 97,
|
111
|
+
'S19' => 98,
|
112
|
+
'S20' => 99,
|
113
|
+
'S21' => 100,
|
114
|
+
'S22' => 101,
|
115
|
+
'S23' => 102,
|
116
|
+
'S24' => 103,
|
117
|
+
'S25' => 104,
|
118
|
+
'S26' => 105,
|
119
|
+
'S27' => 106,
|
120
|
+
'S28' => 107,
|
121
|
+
'S29' => 108,
|
122
|
+
'S30' => 109,
|
123
|
+
'S31' => 110
|
124
|
+
}
|
125
|
+
|
126
|
+
ID_LOOKUP = REG_LOOKUP.invert
|
127
|
+
|
128
|
+
# alias registers
|
129
|
+
REG_LOOKUP['R13'] = REG_LOOKUP['SP']
|
130
|
+
REG_LOOKUP['R14'] = REG_LOOKUP['LR']
|
131
|
+
REG_LOOKUP['R15'] = REG_LOOKUP['PC']
|
132
|
+
REG_LOOKUP['SB'] = REG_LOOKUP['R9']
|
133
|
+
REG_LOOKUP['SL'] = REG_LOOKUP['R10']
|
134
|
+
REG_LOOKUP['FP'] = REG_LOOKUP['R11']
|
135
|
+
REG_LOOKUP['IP'] = REG_LOOKUP['R12']
|
136
|
+
|
137
|
+
SYM_LOOKUP = Hash[REG_LOOKUP.map {|k,v| [k.downcase.to_sym,v]}]
|
138
|
+
|
139
|
+
def self.register reg
|
140
|
+
return reg if ID_LOOKUP[reg]
|
141
|
+
return SYM_LOOKUP[reg] if SYM_LOOKUP[reg]
|
142
|
+
if reg.respond_to? :upcase
|
143
|
+
return REG_LOOKUP[reg.upcase] || REG_LOOKUP['INVALID']
|
144
|
+
end
|
145
|
+
REG_LOOKUP['INVALID']
|
146
|
+
end
|
147
|
+
|
148
|
+
end
|
149
|
+
end
|
data/lib/arch/mips.rb
ADDED
@@ -0,0 +1,78 @@
|
|
1
|
+
# Library by Nguyen Anh Quynh
|
2
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
3
|
+
# Additional binding work by Ben Nagy
|
4
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
5
|
+
|
6
|
+
require 'ffi'
|
7
|
+
|
8
|
+
require_relative 'mips_const'
|
9
|
+
|
10
|
+
module Crabstone
|
11
|
+
module MIPS
|
12
|
+
|
13
|
+
class MemoryOperand < FFI::Struct
|
14
|
+
layout(
|
15
|
+
:base, :uint,
|
16
|
+
:disp, :int64
|
17
|
+
)
|
18
|
+
end
|
19
|
+
|
20
|
+
class OperandValue < FFI::Union
|
21
|
+
layout(
|
22
|
+
:reg, :uint,
|
23
|
+
:imm, :long_long,
|
24
|
+
:mem, MemoryOperand
|
25
|
+
)
|
26
|
+
end
|
27
|
+
|
28
|
+
class Operand < FFI::Struct
|
29
|
+
layout(
|
30
|
+
:type, :uint,
|
31
|
+
:value, OperandValue
|
32
|
+
)
|
33
|
+
|
34
|
+
def value
|
35
|
+
case self[:type]
|
36
|
+
when OP_REG
|
37
|
+
self[:value][:reg]
|
38
|
+
when OP_IMM
|
39
|
+
self[:value][:imm]
|
40
|
+
when OP_MEM
|
41
|
+
self[:value][:mem]
|
42
|
+
when OP_FP
|
43
|
+
self[:value][:fp]
|
44
|
+
else
|
45
|
+
nil
|
46
|
+
end
|
47
|
+
end
|
48
|
+
|
49
|
+
def reg?
|
50
|
+
self[:type] == OP_REG
|
51
|
+
end
|
52
|
+
|
53
|
+
def imm?
|
54
|
+
self[:type] == OP_IMM
|
55
|
+
end
|
56
|
+
|
57
|
+
def mem?
|
58
|
+
self[:type] == OP_MEM
|
59
|
+
end
|
60
|
+
|
61
|
+
def valid?
|
62
|
+
[OP_MEM, OP_IMM, OP_REG].include? self[:type]
|
63
|
+
end
|
64
|
+
end
|
65
|
+
|
66
|
+
class Instruction < FFI::Struct
|
67
|
+
layout(
|
68
|
+
:op_count, :uint8,
|
69
|
+
:operands, [Operand, 8]
|
70
|
+
)
|
71
|
+
|
72
|
+
def operands
|
73
|
+
self[:operands].take_while {|op| op[:type].nonzero?}
|
74
|
+
end
|
75
|
+
|
76
|
+
end
|
77
|
+
end
|
78
|
+
end
|
@@ -0,0 +1,850 @@
|
|
1
|
+
# Library by Nguyen Anh Quynh
|
2
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
3
|
+
# Additional binding work by Ben Nagy
|
4
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
5
|
+
|
6
|
+
# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
|
7
|
+
# Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
|
8
|
+
# 2015-05-02T13:24:01+12:00
|
9
|
+
|
10
|
+
module Crabstone
|
11
|
+
module MIPS
|
12
|
+
|
13
|
+
# Operand type for instruction's operands
|
14
|
+
|
15
|
+
OP_INVALID = 0
|
16
|
+
OP_REG = 1
|
17
|
+
OP_IMM = 2
|
18
|
+
OP_MEM = 3
|
19
|
+
|
20
|
+
# MIPS registers
|
21
|
+
|
22
|
+
REG_INVALID = 0
|
23
|
+
|
24
|
+
# General purpose registers
|
25
|
+
REG_0 = 1
|
26
|
+
REG_1 = 2
|
27
|
+
REG_2 = 3
|
28
|
+
REG_3 = 4
|
29
|
+
REG_4 = 5
|
30
|
+
REG_5 = 6
|
31
|
+
REG_6 = 7
|
32
|
+
REG_7 = 8
|
33
|
+
REG_8 = 9
|
34
|
+
REG_9 = 10
|
35
|
+
REG_10 = 11
|
36
|
+
REG_11 = 12
|
37
|
+
REG_12 = 13
|
38
|
+
REG_13 = 14
|
39
|
+
REG_14 = 15
|
40
|
+
REG_15 = 16
|
41
|
+
REG_16 = 17
|
42
|
+
REG_17 = 18
|
43
|
+
REG_18 = 19
|
44
|
+
REG_19 = 20
|
45
|
+
REG_20 = 21
|
46
|
+
REG_21 = 22
|
47
|
+
REG_22 = 23
|
48
|
+
REG_23 = 24
|
49
|
+
REG_24 = 25
|
50
|
+
REG_25 = 26
|
51
|
+
REG_26 = 27
|
52
|
+
REG_27 = 28
|
53
|
+
REG_28 = 29
|
54
|
+
REG_29 = 30
|
55
|
+
REG_30 = 31
|
56
|
+
REG_31 = 32
|
57
|
+
|
58
|
+
# DSP registers
|
59
|
+
REG_DSPCCOND = 33
|
60
|
+
REG_DSPCARRY = 34
|
61
|
+
REG_DSPEFI = 35
|
62
|
+
REG_DSPOUTFLAG = 36
|
63
|
+
REG_DSPOUTFLAG16_19 = 37
|
64
|
+
REG_DSPOUTFLAG20 = 38
|
65
|
+
REG_DSPOUTFLAG21 = 39
|
66
|
+
REG_DSPOUTFLAG22 = 40
|
67
|
+
REG_DSPOUTFLAG23 = 41
|
68
|
+
REG_DSPPOS = 42
|
69
|
+
REG_DSPSCOUNT = 43
|
70
|
+
|
71
|
+
# ACC registers
|
72
|
+
REG_AC0 = 44
|
73
|
+
REG_AC1 = 45
|
74
|
+
REG_AC2 = 46
|
75
|
+
REG_AC3 = 47
|
76
|
+
|
77
|
+
# COP registers
|
78
|
+
REG_CC0 = 48
|
79
|
+
REG_CC1 = 49
|
80
|
+
REG_CC2 = 50
|
81
|
+
REG_CC3 = 51
|
82
|
+
REG_CC4 = 52
|
83
|
+
REG_CC5 = 53
|
84
|
+
REG_CC6 = 54
|
85
|
+
REG_CC7 = 55
|
86
|
+
|
87
|
+
# FPU registers
|
88
|
+
REG_F0 = 56
|
89
|
+
REG_F1 = 57
|
90
|
+
REG_F2 = 58
|
91
|
+
REG_F3 = 59
|
92
|
+
REG_F4 = 60
|
93
|
+
REG_F5 = 61
|
94
|
+
REG_F6 = 62
|
95
|
+
REG_F7 = 63
|
96
|
+
REG_F8 = 64
|
97
|
+
REG_F9 = 65
|
98
|
+
REG_F10 = 66
|
99
|
+
REG_F11 = 67
|
100
|
+
REG_F12 = 68
|
101
|
+
REG_F13 = 69
|
102
|
+
REG_F14 = 70
|
103
|
+
REG_F15 = 71
|
104
|
+
REG_F16 = 72
|
105
|
+
REG_F17 = 73
|
106
|
+
REG_F18 = 74
|
107
|
+
REG_F19 = 75
|
108
|
+
REG_F20 = 76
|
109
|
+
REG_F21 = 77
|
110
|
+
REG_F22 = 78
|
111
|
+
REG_F23 = 79
|
112
|
+
REG_F24 = 80
|
113
|
+
REG_F25 = 81
|
114
|
+
REG_F26 = 82
|
115
|
+
REG_F27 = 83
|
116
|
+
REG_F28 = 84
|
117
|
+
REG_F29 = 85
|
118
|
+
REG_F30 = 86
|
119
|
+
REG_F31 = 87
|
120
|
+
REG_FCC0 = 88
|
121
|
+
REG_FCC1 = 89
|
122
|
+
REG_FCC2 = 90
|
123
|
+
REG_FCC3 = 91
|
124
|
+
REG_FCC4 = 92
|
125
|
+
REG_FCC5 = 93
|
126
|
+
REG_FCC6 = 94
|
127
|
+
REG_FCC7 = 95
|
128
|
+
|
129
|
+
# AFPR128
|
130
|
+
REG_W0 = 96
|
131
|
+
REG_W1 = 97
|
132
|
+
REG_W2 = 98
|
133
|
+
REG_W3 = 99
|
134
|
+
REG_W4 = 100
|
135
|
+
REG_W5 = 101
|
136
|
+
REG_W6 = 102
|
137
|
+
REG_W7 = 103
|
138
|
+
REG_W8 = 104
|
139
|
+
REG_W9 = 105
|
140
|
+
REG_W10 = 106
|
141
|
+
REG_W11 = 107
|
142
|
+
REG_W12 = 108
|
143
|
+
REG_W13 = 109
|
144
|
+
REG_W14 = 110
|
145
|
+
REG_W15 = 111
|
146
|
+
REG_W16 = 112
|
147
|
+
REG_W17 = 113
|
148
|
+
REG_W18 = 114
|
149
|
+
REG_W19 = 115
|
150
|
+
REG_W20 = 116
|
151
|
+
REG_W21 = 117
|
152
|
+
REG_W22 = 118
|
153
|
+
REG_W23 = 119
|
154
|
+
REG_W24 = 120
|
155
|
+
REG_W25 = 121
|
156
|
+
REG_W26 = 122
|
157
|
+
REG_W27 = 123
|
158
|
+
REG_W28 = 124
|
159
|
+
REG_W29 = 125
|
160
|
+
REG_W30 = 126
|
161
|
+
REG_W31 = 127
|
162
|
+
REG_HI = 128
|
163
|
+
REG_LO = 129
|
164
|
+
REG_P0 = 130
|
165
|
+
REG_P1 = 131
|
166
|
+
REG_P2 = 132
|
167
|
+
REG_MPL0 = 133
|
168
|
+
REG_MPL1 = 134
|
169
|
+
REG_MPL2 = 135
|
170
|
+
REG_ENDING = 136
|
171
|
+
REG_ZERO = REG_0
|
172
|
+
REG_AT = REG_1
|
173
|
+
REG_V0 = REG_2
|
174
|
+
REG_V1 = REG_3
|
175
|
+
REG_A0 = REG_4
|
176
|
+
REG_A1 = REG_5
|
177
|
+
REG_A2 = REG_6
|
178
|
+
REG_A3 = REG_7
|
179
|
+
REG_T0 = REG_8
|
180
|
+
REG_T1 = REG_9
|
181
|
+
REG_T2 = REG_10
|
182
|
+
REG_T3 = REG_11
|
183
|
+
REG_T4 = REG_12
|
184
|
+
REG_T5 = REG_13
|
185
|
+
REG_T6 = REG_14
|
186
|
+
REG_T7 = REG_15
|
187
|
+
REG_S0 = REG_16
|
188
|
+
REG_S1 = REG_17
|
189
|
+
REG_S2 = REG_18
|
190
|
+
REG_S3 = REG_19
|
191
|
+
REG_S4 = REG_20
|
192
|
+
REG_S5 = REG_21
|
193
|
+
REG_S6 = REG_22
|
194
|
+
REG_S7 = REG_23
|
195
|
+
REG_T8 = REG_24
|
196
|
+
REG_T9 = REG_25
|
197
|
+
REG_K0 = REG_26
|
198
|
+
REG_K1 = REG_27
|
199
|
+
REG_GP = REG_28
|
200
|
+
REG_SP = REG_29
|
201
|
+
REG_FP = REG_30
|
202
|
+
REG_S8 = REG_30
|
203
|
+
REG_RA = REG_31
|
204
|
+
REG_HI0 = REG_AC0
|
205
|
+
REG_HI1 = REG_AC1
|
206
|
+
REG_HI2 = REG_AC2
|
207
|
+
REG_HI3 = REG_AC3
|
208
|
+
REG_LO0 = REG_HI0
|
209
|
+
REG_LO1 = REG_HI1
|
210
|
+
REG_LO2 = REG_HI2
|
211
|
+
REG_LO3 = REG_HI3
|
212
|
+
|
213
|
+
# MIPS instruction
|
214
|
+
|
215
|
+
INS_INVALID = 0
|
216
|
+
INS_ABSQ_S = 1
|
217
|
+
INS_ADD = 2
|
218
|
+
INS_ADDIUPC = 3
|
219
|
+
INS_ADDQH = 4
|
220
|
+
INS_ADDQH_R = 5
|
221
|
+
INS_ADDQ = 6
|
222
|
+
INS_ADDQ_S = 7
|
223
|
+
INS_ADDSC = 8
|
224
|
+
INS_ADDS_A = 9
|
225
|
+
INS_ADDS_S = 10
|
226
|
+
INS_ADDS_U = 11
|
227
|
+
INS_ADDUH = 12
|
228
|
+
INS_ADDUH_R = 13
|
229
|
+
INS_ADDU = 14
|
230
|
+
INS_ADDU_S = 15
|
231
|
+
INS_ADDVI = 16
|
232
|
+
INS_ADDV = 17
|
233
|
+
INS_ADDWC = 18
|
234
|
+
INS_ADD_A = 19
|
235
|
+
INS_ADDI = 20
|
236
|
+
INS_ADDIU = 21
|
237
|
+
INS_ALIGN = 22
|
238
|
+
INS_ALUIPC = 23
|
239
|
+
INS_AND = 24
|
240
|
+
INS_ANDI = 25
|
241
|
+
INS_APPEND = 26
|
242
|
+
INS_ASUB_S = 27
|
243
|
+
INS_ASUB_U = 28
|
244
|
+
INS_AUI = 29
|
245
|
+
INS_AUIPC = 30
|
246
|
+
INS_AVER_S = 31
|
247
|
+
INS_AVER_U = 32
|
248
|
+
INS_AVE_S = 33
|
249
|
+
INS_AVE_U = 34
|
250
|
+
INS_BADDU = 35
|
251
|
+
INS_BAL = 36
|
252
|
+
INS_BALC = 37
|
253
|
+
INS_BALIGN = 38
|
254
|
+
INS_BC = 39
|
255
|
+
INS_BC0F = 40
|
256
|
+
INS_BC0FL = 41
|
257
|
+
INS_BC0T = 42
|
258
|
+
INS_BC0TL = 43
|
259
|
+
INS_BC1EQZ = 44
|
260
|
+
INS_BC1F = 45
|
261
|
+
INS_BC1FL = 46
|
262
|
+
INS_BC1NEZ = 47
|
263
|
+
INS_BC1T = 48
|
264
|
+
INS_BC1TL = 49
|
265
|
+
INS_BC2EQZ = 50
|
266
|
+
INS_BC2F = 51
|
267
|
+
INS_BC2FL = 52
|
268
|
+
INS_BC2NEZ = 53
|
269
|
+
INS_BC2T = 54
|
270
|
+
INS_BC2TL = 55
|
271
|
+
INS_BC3F = 56
|
272
|
+
INS_BC3FL = 57
|
273
|
+
INS_BC3T = 58
|
274
|
+
INS_BC3TL = 59
|
275
|
+
INS_BCLRI = 60
|
276
|
+
INS_BCLR = 61
|
277
|
+
INS_BEQ = 62
|
278
|
+
INS_BEQC = 63
|
279
|
+
INS_BEQL = 64
|
280
|
+
INS_BEQZALC = 65
|
281
|
+
INS_BEQZC = 66
|
282
|
+
INS_BGEC = 67
|
283
|
+
INS_BGEUC = 68
|
284
|
+
INS_BGEZ = 69
|
285
|
+
INS_BGEZAL = 70
|
286
|
+
INS_BGEZALC = 71
|
287
|
+
INS_BGEZALL = 72
|
288
|
+
INS_BGEZALS = 73
|
289
|
+
INS_BGEZC = 74
|
290
|
+
INS_BGEZL = 75
|
291
|
+
INS_BGTZ = 76
|
292
|
+
INS_BGTZALC = 77
|
293
|
+
INS_BGTZC = 78
|
294
|
+
INS_BGTZL = 79
|
295
|
+
INS_BINSLI = 80
|
296
|
+
INS_BINSL = 81
|
297
|
+
INS_BINSRI = 82
|
298
|
+
INS_BINSR = 83
|
299
|
+
INS_BITREV = 84
|
300
|
+
INS_BITSWAP = 85
|
301
|
+
INS_BLEZ = 86
|
302
|
+
INS_BLEZALC = 87
|
303
|
+
INS_BLEZC = 88
|
304
|
+
INS_BLEZL = 89
|
305
|
+
INS_BLTC = 90
|
306
|
+
INS_BLTUC = 91
|
307
|
+
INS_BLTZ = 92
|
308
|
+
INS_BLTZAL = 93
|
309
|
+
INS_BLTZALC = 94
|
310
|
+
INS_BLTZALL = 95
|
311
|
+
INS_BLTZALS = 96
|
312
|
+
INS_BLTZC = 97
|
313
|
+
INS_BLTZL = 98
|
314
|
+
INS_BMNZI = 99
|
315
|
+
INS_BMNZ = 100
|
316
|
+
INS_BMZI = 101
|
317
|
+
INS_BMZ = 102
|
318
|
+
INS_BNE = 103
|
319
|
+
INS_BNEC = 104
|
320
|
+
INS_BNEGI = 105
|
321
|
+
INS_BNEG = 106
|
322
|
+
INS_BNEL = 107
|
323
|
+
INS_BNEZALC = 108
|
324
|
+
INS_BNEZC = 109
|
325
|
+
INS_BNVC = 110
|
326
|
+
INS_BNZ = 111
|
327
|
+
INS_BOVC = 112
|
328
|
+
INS_BPOSGE32 = 113
|
329
|
+
INS_BREAK = 114
|
330
|
+
INS_BSELI = 115
|
331
|
+
INS_BSEL = 116
|
332
|
+
INS_BSETI = 117
|
333
|
+
INS_BSET = 118
|
334
|
+
INS_BZ = 119
|
335
|
+
INS_BEQZ = 120
|
336
|
+
INS_B = 121
|
337
|
+
INS_BNEZ = 122
|
338
|
+
INS_BTEQZ = 123
|
339
|
+
INS_BTNEZ = 124
|
340
|
+
INS_CACHE = 125
|
341
|
+
INS_CEIL = 126
|
342
|
+
INS_CEQI = 127
|
343
|
+
INS_CEQ = 128
|
344
|
+
INS_CFC1 = 129
|
345
|
+
INS_CFCMSA = 130
|
346
|
+
INS_CINS = 131
|
347
|
+
INS_CINS32 = 132
|
348
|
+
INS_CLASS = 133
|
349
|
+
INS_CLEI_S = 134
|
350
|
+
INS_CLEI_U = 135
|
351
|
+
INS_CLE_S = 136
|
352
|
+
INS_CLE_U = 137
|
353
|
+
INS_CLO = 138
|
354
|
+
INS_CLTI_S = 139
|
355
|
+
INS_CLTI_U = 140
|
356
|
+
INS_CLT_S = 141
|
357
|
+
INS_CLT_U = 142
|
358
|
+
INS_CLZ = 143
|
359
|
+
INS_CMPGDU = 144
|
360
|
+
INS_CMPGU = 145
|
361
|
+
INS_CMPU = 146
|
362
|
+
INS_CMP = 147
|
363
|
+
INS_COPY_S = 148
|
364
|
+
INS_COPY_U = 149
|
365
|
+
INS_CTC1 = 150
|
366
|
+
INS_CTCMSA = 151
|
367
|
+
INS_CVT = 152
|
368
|
+
INS_C = 153
|
369
|
+
INS_CMPI = 154
|
370
|
+
INS_DADD = 155
|
371
|
+
INS_DADDI = 156
|
372
|
+
INS_DADDIU = 157
|
373
|
+
INS_DADDU = 158
|
374
|
+
INS_DAHI = 159
|
375
|
+
INS_DALIGN = 160
|
376
|
+
INS_DATI = 161
|
377
|
+
INS_DAUI = 162
|
378
|
+
INS_DBITSWAP = 163
|
379
|
+
INS_DCLO = 164
|
380
|
+
INS_DCLZ = 165
|
381
|
+
INS_DDIV = 166
|
382
|
+
INS_DDIVU = 167
|
383
|
+
INS_DERET = 168
|
384
|
+
INS_DEXT = 169
|
385
|
+
INS_DEXTM = 170
|
386
|
+
INS_DEXTU = 171
|
387
|
+
INS_DI = 172
|
388
|
+
INS_DINS = 173
|
389
|
+
INS_DINSM = 174
|
390
|
+
INS_DINSU = 175
|
391
|
+
INS_DIV = 176
|
392
|
+
INS_DIVU = 177
|
393
|
+
INS_DIV_S = 178
|
394
|
+
INS_DIV_U = 179
|
395
|
+
INS_DLSA = 180
|
396
|
+
INS_DMFC0 = 181
|
397
|
+
INS_DMFC1 = 182
|
398
|
+
INS_DMFC2 = 183
|
399
|
+
INS_DMOD = 184
|
400
|
+
INS_DMODU = 185
|
401
|
+
INS_DMTC0 = 186
|
402
|
+
INS_DMTC1 = 187
|
403
|
+
INS_DMTC2 = 188
|
404
|
+
INS_DMUH = 189
|
405
|
+
INS_DMUHU = 190
|
406
|
+
INS_DMUL = 191
|
407
|
+
INS_DMULT = 192
|
408
|
+
INS_DMULTU = 193
|
409
|
+
INS_DMULU = 194
|
410
|
+
INS_DOTP_S = 195
|
411
|
+
INS_DOTP_U = 196
|
412
|
+
INS_DPADD_S = 197
|
413
|
+
INS_DPADD_U = 198
|
414
|
+
INS_DPAQX_SA = 199
|
415
|
+
INS_DPAQX_S = 200
|
416
|
+
INS_DPAQ_SA = 201
|
417
|
+
INS_DPAQ_S = 202
|
418
|
+
INS_DPAU = 203
|
419
|
+
INS_DPAX = 204
|
420
|
+
INS_DPA = 205
|
421
|
+
INS_DPOP = 206
|
422
|
+
INS_DPSQX_SA = 207
|
423
|
+
INS_DPSQX_S = 208
|
424
|
+
INS_DPSQ_SA = 209
|
425
|
+
INS_DPSQ_S = 210
|
426
|
+
INS_DPSUB_S = 211
|
427
|
+
INS_DPSUB_U = 212
|
428
|
+
INS_DPSU = 213
|
429
|
+
INS_DPSX = 214
|
430
|
+
INS_DPS = 215
|
431
|
+
INS_DROTR = 216
|
432
|
+
INS_DROTR32 = 217
|
433
|
+
INS_DROTRV = 218
|
434
|
+
INS_DSBH = 219
|
435
|
+
INS_DSHD = 220
|
436
|
+
INS_DSLL = 221
|
437
|
+
INS_DSLL32 = 222
|
438
|
+
INS_DSLLV = 223
|
439
|
+
INS_DSRA = 224
|
440
|
+
INS_DSRA32 = 225
|
441
|
+
INS_DSRAV = 226
|
442
|
+
INS_DSRL = 227
|
443
|
+
INS_DSRL32 = 228
|
444
|
+
INS_DSRLV = 229
|
445
|
+
INS_DSUB = 230
|
446
|
+
INS_DSUBU = 231
|
447
|
+
INS_EHB = 232
|
448
|
+
INS_EI = 233
|
449
|
+
INS_ERET = 234
|
450
|
+
INS_EXT = 235
|
451
|
+
INS_EXTP = 236
|
452
|
+
INS_EXTPDP = 237
|
453
|
+
INS_EXTPDPV = 238
|
454
|
+
INS_EXTPV = 239
|
455
|
+
INS_EXTRV_RS = 240
|
456
|
+
INS_EXTRV_R = 241
|
457
|
+
INS_EXTRV_S = 242
|
458
|
+
INS_EXTRV = 243
|
459
|
+
INS_EXTR_RS = 244
|
460
|
+
INS_EXTR_R = 245
|
461
|
+
INS_EXTR_S = 246
|
462
|
+
INS_EXTR = 247
|
463
|
+
INS_EXTS = 248
|
464
|
+
INS_EXTS32 = 249
|
465
|
+
INS_ABS = 250
|
466
|
+
INS_FADD = 251
|
467
|
+
INS_FCAF = 252
|
468
|
+
INS_FCEQ = 253
|
469
|
+
INS_FCLASS = 254
|
470
|
+
INS_FCLE = 255
|
471
|
+
INS_FCLT = 256
|
472
|
+
INS_FCNE = 257
|
473
|
+
INS_FCOR = 258
|
474
|
+
INS_FCUEQ = 259
|
475
|
+
INS_FCULE = 260
|
476
|
+
INS_FCULT = 261
|
477
|
+
INS_FCUNE = 262
|
478
|
+
INS_FCUN = 263
|
479
|
+
INS_FDIV = 264
|
480
|
+
INS_FEXDO = 265
|
481
|
+
INS_FEXP2 = 266
|
482
|
+
INS_FEXUPL = 267
|
483
|
+
INS_FEXUPR = 268
|
484
|
+
INS_FFINT_S = 269
|
485
|
+
INS_FFINT_U = 270
|
486
|
+
INS_FFQL = 271
|
487
|
+
INS_FFQR = 272
|
488
|
+
INS_FILL = 273
|
489
|
+
INS_FLOG2 = 274
|
490
|
+
INS_FLOOR = 275
|
491
|
+
INS_FMADD = 276
|
492
|
+
INS_FMAX_A = 277
|
493
|
+
INS_FMAX = 278
|
494
|
+
INS_FMIN_A = 279
|
495
|
+
INS_FMIN = 280
|
496
|
+
INS_MOV = 281
|
497
|
+
INS_FMSUB = 282
|
498
|
+
INS_FMUL = 283
|
499
|
+
INS_MUL = 284
|
500
|
+
INS_NEG = 285
|
501
|
+
INS_FRCP = 286
|
502
|
+
INS_FRINT = 287
|
503
|
+
INS_FRSQRT = 288
|
504
|
+
INS_FSAF = 289
|
505
|
+
INS_FSEQ = 290
|
506
|
+
INS_FSLE = 291
|
507
|
+
INS_FSLT = 292
|
508
|
+
INS_FSNE = 293
|
509
|
+
INS_FSOR = 294
|
510
|
+
INS_FSQRT = 295
|
511
|
+
INS_SQRT = 296
|
512
|
+
INS_FSUB = 297
|
513
|
+
INS_SUB = 298
|
514
|
+
INS_FSUEQ = 299
|
515
|
+
INS_FSULE = 300
|
516
|
+
INS_FSULT = 301
|
517
|
+
INS_FSUNE = 302
|
518
|
+
INS_FSUN = 303
|
519
|
+
INS_FTINT_S = 304
|
520
|
+
INS_FTINT_U = 305
|
521
|
+
INS_FTQ = 306
|
522
|
+
INS_FTRUNC_S = 307
|
523
|
+
INS_FTRUNC_U = 308
|
524
|
+
INS_HADD_S = 309
|
525
|
+
INS_HADD_U = 310
|
526
|
+
INS_HSUB_S = 311
|
527
|
+
INS_HSUB_U = 312
|
528
|
+
INS_ILVEV = 313
|
529
|
+
INS_ILVL = 314
|
530
|
+
INS_ILVOD = 315
|
531
|
+
INS_ILVR = 316
|
532
|
+
INS_INS = 317
|
533
|
+
INS_INSERT = 318
|
534
|
+
INS_INSV = 319
|
535
|
+
INS_INSVE = 320
|
536
|
+
INS_J = 321
|
537
|
+
INS_JAL = 322
|
538
|
+
INS_JALR = 323
|
539
|
+
INS_JALRS = 324
|
540
|
+
INS_JALS = 325
|
541
|
+
INS_JALX = 326
|
542
|
+
INS_JIALC = 327
|
543
|
+
INS_JIC = 328
|
544
|
+
INS_JR = 329
|
545
|
+
INS_JRADDIUSP = 330
|
546
|
+
INS_JRC = 331
|
547
|
+
INS_JALRC = 332
|
548
|
+
INS_LB = 333
|
549
|
+
INS_LBUX = 334
|
550
|
+
INS_LBU = 335
|
551
|
+
INS_LD = 336
|
552
|
+
INS_LDC1 = 337
|
553
|
+
INS_LDC2 = 338
|
554
|
+
INS_LDC3 = 339
|
555
|
+
INS_LDI = 340
|
556
|
+
INS_LDL = 341
|
557
|
+
INS_LDPC = 342
|
558
|
+
INS_LDR = 343
|
559
|
+
INS_LDXC1 = 344
|
560
|
+
INS_LH = 345
|
561
|
+
INS_LHX = 346
|
562
|
+
INS_LHU = 347
|
563
|
+
INS_LL = 348
|
564
|
+
INS_LLD = 349
|
565
|
+
INS_LSA = 350
|
566
|
+
INS_LUXC1 = 351
|
567
|
+
INS_LUI = 352
|
568
|
+
INS_LW = 353
|
569
|
+
INS_LWC1 = 354
|
570
|
+
INS_LWC2 = 355
|
571
|
+
INS_LWC3 = 356
|
572
|
+
INS_LWL = 357
|
573
|
+
INS_LWPC = 358
|
574
|
+
INS_LWR = 359
|
575
|
+
INS_LWUPC = 360
|
576
|
+
INS_LWU = 361
|
577
|
+
INS_LWX = 362
|
578
|
+
INS_LWXC1 = 363
|
579
|
+
INS_LI = 364
|
580
|
+
INS_MADD = 365
|
581
|
+
INS_MADDF = 366
|
582
|
+
INS_MADDR_Q = 367
|
583
|
+
INS_MADDU = 368
|
584
|
+
INS_MADDV = 369
|
585
|
+
INS_MADD_Q = 370
|
586
|
+
INS_MAQ_SA = 371
|
587
|
+
INS_MAQ_S = 372
|
588
|
+
INS_MAXA = 373
|
589
|
+
INS_MAXI_S = 374
|
590
|
+
INS_MAXI_U = 375
|
591
|
+
INS_MAX_A = 376
|
592
|
+
INS_MAX = 377
|
593
|
+
INS_MAX_S = 378
|
594
|
+
INS_MAX_U = 379
|
595
|
+
INS_MFC0 = 380
|
596
|
+
INS_MFC1 = 381
|
597
|
+
INS_MFC2 = 382
|
598
|
+
INS_MFHC1 = 383
|
599
|
+
INS_MFHI = 384
|
600
|
+
INS_MFLO = 385
|
601
|
+
INS_MINA = 386
|
602
|
+
INS_MINI_S = 387
|
603
|
+
INS_MINI_U = 388
|
604
|
+
INS_MIN_A = 389
|
605
|
+
INS_MIN = 390
|
606
|
+
INS_MIN_S = 391
|
607
|
+
INS_MIN_U = 392
|
608
|
+
INS_MOD = 393
|
609
|
+
INS_MODSUB = 394
|
610
|
+
INS_MODU = 395
|
611
|
+
INS_MOD_S = 396
|
612
|
+
INS_MOD_U = 397
|
613
|
+
INS_MOVE = 398
|
614
|
+
INS_MOVF = 399
|
615
|
+
INS_MOVN = 400
|
616
|
+
INS_MOVT = 401
|
617
|
+
INS_MOVZ = 402
|
618
|
+
INS_MSUB = 403
|
619
|
+
INS_MSUBF = 404
|
620
|
+
INS_MSUBR_Q = 405
|
621
|
+
INS_MSUBU = 406
|
622
|
+
INS_MSUBV = 407
|
623
|
+
INS_MSUB_Q = 408
|
624
|
+
INS_MTC0 = 409
|
625
|
+
INS_MTC1 = 410
|
626
|
+
INS_MTC2 = 411
|
627
|
+
INS_MTHC1 = 412
|
628
|
+
INS_MTHI = 413
|
629
|
+
INS_MTHLIP = 414
|
630
|
+
INS_MTLO = 415
|
631
|
+
INS_MTM0 = 416
|
632
|
+
INS_MTM1 = 417
|
633
|
+
INS_MTM2 = 418
|
634
|
+
INS_MTP0 = 419
|
635
|
+
INS_MTP1 = 420
|
636
|
+
INS_MTP2 = 421
|
637
|
+
INS_MUH = 422
|
638
|
+
INS_MUHU = 423
|
639
|
+
INS_MULEQ_S = 424
|
640
|
+
INS_MULEU_S = 425
|
641
|
+
INS_MULQ_RS = 426
|
642
|
+
INS_MULQ_S = 427
|
643
|
+
INS_MULR_Q = 428
|
644
|
+
INS_MULSAQ_S = 429
|
645
|
+
INS_MULSA = 430
|
646
|
+
INS_MULT = 431
|
647
|
+
INS_MULTU = 432
|
648
|
+
INS_MULU = 433
|
649
|
+
INS_MULV = 434
|
650
|
+
INS_MUL_Q = 435
|
651
|
+
INS_MUL_S = 436
|
652
|
+
INS_NLOC = 437
|
653
|
+
INS_NLZC = 438
|
654
|
+
INS_NMADD = 439
|
655
|
+
INS_NMSUB = 440
|
656
|
+
INS_NOR = 441
|
657
|
+
INS_NORI = 442
|
658
|
+
INS_NOT = 443
|
659
|
+
INS_OR = 444
|
660
|
+
INS_ORI = 445
|
661
|
+
INS_PACKRL = 446
|
662
|
+
INS_PAUSE = 447
|
663
|
+
INS_PCKEV = 448
|
664
|
+
INS_PCKOD = 449
|
665
|
+
INS_PCNT = 450
|
666
|
+
INS_PICK = 451
|
667
|
+
INS_POP = 452
|
668
|
+
INS_PRECEQU = 453
|
669
|
+
INS_PRECEQ = 454
|
670
|
+
INS_PRECEU = 455
|
671
|
+
INS_PRECRQU_S = 456
|
672
|
+
INS_PRECRQ = 457
|
673
|
+
INS_PRECRQ_RS = 458
|
674
|
+
INS_PRECR = 459
|
675
|
+
INS_PRECR_SRA = 460
|
676
|
+
INS_PRECR_SRA_R = 461
|
677
|
+
INS_PREF = 462
|
678
|
+
INS_PREPEND = 463
|
679
|
+
INS_RADDU = 464
|
680
|
+
INS_RDDSP = 465
|
681
|
+
INS_RDHWR = 466
|
682
|
+
INS_REPLV = 467
|
683
|
+
INS_REPL = 468
|
684
|
+
INS_RINT = 469
|
685
|
+
INS_ROTR = 470
|
686
|
+
INS_ROTRV = 471
|
687
|
+
INS_ROUND = 472
|
688
|
+
INS_SAT_S = 473
|
689
|
+
INS_SAT_U = 474
|
690
|
+
INS_SB = 475
|
691
|
+
INS_SC = 476
|
692
|
+
INS_SCD = 477
|
693
|
+
INS_SD = 478
|
694
|
+
INS_SDBBP = 479
|
695
|
+
INS_SDC1 = 480
|
696
|
+
INS_SDC2 = 481
|
697
|
+
INS_SDC3 = 482
|
698
|
+
INS_SDL = 483
|
699
|
+
INS_SDR = 484
|
700
|
+
INS_SDXC1 = 485
|
701
|
+
INS_SEB = 486
|
702
|
+
INS_SEH = 487
|
703
|
+
INS_SELEQZ = 488
|
704
|
+
INS_SELNEZ = 489
|
705
|
+
INS_SEL = 490
|
706
|
+
INS_SEQ = 491
|
707
|
+
INS_SEQI = 492
|
708
|
+
INS_SH = 493
|
709
|
+
INS_SHF = 494
|
710
|
+
INS_SHILO = 495
|
711
|
+
INS_SHILOV = 496
|
712
|
+
INS_SHLLV = 497
|
713
|
+
INS_SHLLV_S = 498
|
714
|
+
INS_SHLL = 499
|
715
|
+
INS_SHLL_S = 500
|
716
|
+
INS_SHRAV = 501
|
717
|
+
INS_SHRAV_R = 502
|
718
|
+
INS_SHRA = 503
|
719
|
+
INS_SHRA_R = 504
|
720
|
+
INS_SHRLV = 505
|
721
|
+
INS_SHRL = 506
|
722
|
+
INS_SLDI = 507
|
723
|
+
INS_SLD = 508
|
724
|
+
INS_SLL = 509
|
725
|
+
INS_SLLI = 510
|
726
|
+
INS_SLLV = 511
|
727
|
+
INS_SLT = 512
|
728
|
+
INS_SLTI = 513
|
729
|
+
INS_SLTIU = 514
|
730
|
+
INS_SLTU = 515
|
731
|
+
INS_SNE = 516
|
732
|
+
INS_SNEI = 517
|
733
|
+
INS_SPLATI = 518
|
734
|
+
INS_SPLAT = 519
|
735
|
+
INS_SRA = 520
|
736
|
+
INS_SRAI = 521
|
737
|
+
INS_SRARI = 522
|
738
|
+
INS_SRAR = 523
|
739
|
+
INS_SRAV = 524
|
740
|
+
INS_SRL = 525
|
741
|
+
INS_SRLI = 526
|
742
|
+
INS_SRLRI = 527
|
743
|
+
INS_SRLR = 528
|
744
|
+
INS_SRLV = 529
|
745
|
+
INS_SSNOP = 530
|
746
|
+
INS_ST = 531
|
747
|
+
INS_SUBQH = 532
|
748
|
+
INS_SUBQH_R = 533
|
749
|
+
INS_SUBQ = 534
|
750
|
+
INS_SUBQ_S = 535
|
751
|
+
INS_SUBSUS_U = 536
|
752
|
+
INS_SUBSUU_S = 537
|
753
|
+
INS_SUBS_S = 538
|
754
|
+
INS_SUBS_U = 539
|
755
|
+
INS_SUBUH = 540
|
756
|
+
INS_SUBUH_R = 541
|
757
|
+
INS_SUBU = 542
|
758
|
+
INS_SUBU_S = 543
|
759
|
+
INS_SUBVI = 544
|
760
|
+
INS_SUBV = 545
|
761
|
+
INS_SUXC1 = 546
|
762
|
+
INS_SW = 547
|
763
|
+
INS_SWC1 = 548
|
764
|
+
INS_SWC2 = 549
|
765
|
+
INS_SWC3 = 550
|
766
|
+
INS_SWL = 551
|
767
|
+
INS_SWR = 552
|
768
|
+
INS_SWXC1 = 553
|
769
|
+
INS_SYNC = 554
|
770
|
+
INS_SYSCALL = 555
|
771
|
+
INS_TEQ = 556
|
772
|
+
INS_TEQI = 557
|
773
|
+
INS_TGE = 558
|
774
|
+
INS_TGEI = 559
|
775
|
+
INS_TGEIU = 560
|
776
|
+
INS_TGEU = 561
|
777
|
+
INS_TLBP = 562
|
778
|
+
INS_TLBR = 563
|
779
|
+
INS_TLBWI = 564
|
780
|
+
INS_TLBWR = 565
|
781
|
+
INS_TLT = 566
|
782
|
+
INS_TLTI = 567
|
783
|
+
INS_TLTIU = 568
|
784
|
+
INS_TLTU = 569
|
785
|
+
INS_TNE = 570
|
786
|
+
INS_TNEI = 571
|
787
|
+
INS_TRUNC = 572
|
788
|
+
INS_V3MULU = 573
|
789
|
+
INS_VMM0 = 574
|
790
|
+
INS_VMULU = 575
|
791
|
+
INS_VSHF = 576
|
792
|
+
INS_WAIT = 577
|
793
|
+
INS_WRDSP = 578
|
794
|
+
INS_WSBH = 579
|
795
|
+
INS_XOR = 580
|
796
|
+
INS_XORI = 581
|
797
|
+
|
798
|
+
# some alias instructions
|
799
|
+
INS_NOP = 582
|
800
|
+
INS_NEGU = 583
|
801
|
+
|
802
|
+
# special instructions
|
803
|
+
INS_JALR_HB = 584
|
804
|
+
INS_JR_HB = 585
|
805
|
+
INS_ENDING = 586
|
806
|
+
|
807
|
+
# Group of MIPS instructions
|
808
|
+
|
809
|
+
GRP_INVALID = 0
|
810
|
+
|
811
|
+
# Generic groups
|
812
|
+
GRP_JUMP = 1
|
813
|
+
|
814
|
+
# Architecture-specific groups
|
815
|
+
GRP_BITCOUNT = 128
|
816
|
+
GRP_DSP = 129
|
817
|
+
GRP_DSPR2 = 130
|
818
|
+
GRP_FPIDX = 131
|
819
|
+
GRP_MSA = 132
|
820
|
+
GRP_MIPS32R2 = 133
|
821
|
+
GRP_MIPS64 = 134
|
822
|
+
GRP_MIPS64R2 = 135
|
823
|
+
GRP_SEINREG = 136
|
824
|
+
GRP_STDENC = 137
|
825
|
+
GRP_SWAP = 138
|
826
|
+
GRP_MICROMIPS = 139
|
827
|
+
GRP_MIPS16MODE = 140
|
828
|
+
GRP_FP64BIT = 141
|
829
|
+
GRP_NONANSFPMATH = 142
|
830
|
+
GRP_NOTFP64BIT = 143
|
831
|
+
GRP_NOTINMICROMIPS = 144
|
832
|
+
GRP_NOTNACL = 145
|
833
|
+
GRP_NOTMIPS32R6 = 146
|
834
|
+
GRP_NOTMIPS64R6 = 147
|
835
|
+
GRP_CNMIPS = 148
|
836
|
+
GRP_MIPS32 = 149
|
837
|
+
GRP_MIPS32R6 = 150
|
838
|
+
GRP_MIPS64R6 = 151
|
839
|
+
GRP_MIPS2 = 152
|
840
|
+
GRP_MIPS3 = 153
|
841
|
+
GRP_MIPS3_32 = 154
|
842
|
+
GRP_MIPS3_32R2 = 155
|
843
|
+
GRP_MIPS4_32 = 156
|
844
|
+
GRP_MIPS4_32R2 = 157
|
845
|
+
GRP_MIPS5_32R2 = 158
|
846
|
+
GRP_GP32BIT = 159
|
847
|
+
GRP_GP64BIT = 160
|
848
|
+
GRP_ENDING = 161
|
849
|
+
end
|
850
|
+
end
|