crabstone 3.0.3
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- checksums.yaml +7 -0
- data/CHANGES.md +61 -0
- data/LICENSE +25 -0
- data/MANIFEST +312 -0
- data/README.md +103 -0
- data/Rakefile +27 -0
- data/bin/genconst +66 -0
- data/bin/genreg +99 -0
- data/crabstone.gemspec +27 -0
- data/examples/hello_world.rb +43 -0
- data/lib/arch/arm.rb +128 -0
- data/lib/arch/arm64.rb +167 -0
- data/lib/arch/arm64_const.rb +1055 -0
- data/lib/arch/arm64_registers.rb +295 -0
- data/lib/arch/arm_const.rb +777 -0
- data/lib/arch/arm_registers.rb +149 -0
- data/lib/arch/mips.rb +78 -0
- data/lib/arch/mips_const.rb +850 -0
- data/lib/arch/mips_registers.rb +208 -0
- data/lib/arch/ppc.rb +90 -0
- data/lib/arch/ppc_const.rb +1181 -0
- data/lib/arch/ppc_registers.rb +209 -0
- data/lib/arch/sparc.rb +79 -0
- data/lib/arch/sparc_const.rb +461 -0
- data/lib/arch/sparc_registers.rb +121 -0
- data/lib/arch/systemz.rb +79 -0
- data/lib/arch/sysz_const.rb +779 -0
- data/lib/arch/sysz_registers.rb +66 -0
- data/lib/arch/x86.rb +107 -0
- data/lib/arch/x86_const.rb +1698 -0
- data/lib/arch/x86_registers.rb +265 -0
- data/lib/arch/xcore.rb +78 -0
- data/lib/arch/xcore_const.rb +185 -0
- data/lib/arch/xcore_registers.rb +57 -0
- data/lib/crabstone.rb +564 -0
- data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
- data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
- data/test/MC/AArch64/neon-2velem.s.cs +113 -0
- data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
- data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
- data/test/MC/AArch64/neon-across.s.cs +40 -0
- data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
- data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
- data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
- data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
- data/test/MC/AArch64/neon-crypto.s.cs +15 -0
- data/test/MC/AArch64/neon-extract.s.cs +3 -0
- data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
- data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
- data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
- data/test/MC/AArch64/neon-max-min.s.cs +37 -0
- data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
- data/test/MC/AArch64/neon-mov.s.cs +74 -0
- data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
- data/test/MC/AArch64/neon-perm.s.cs +43 -0
- data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
- data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
- data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
- data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
- data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
- data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
- data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
- data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
- data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
- data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
- data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
- data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
- data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
- data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
- data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
- data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
- data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
- data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
- data/test/MC/AArch64/neon-shift.s.cs +22 -0
- data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
- data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
- data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
- data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
- data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
- data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
- data/test/MC/AArch64/neon-tbl.s.cs +21 -0
- data/test/MC/AArch64/trace-regs.s.cs +383 -0
- data/test/MC/ARM/arm-aliases.s.cs +7 -0
- data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
- data/test/MC/ARM/arm-it-block.s.cs +2 -0
- data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
- data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
- data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm-trustzone.s.cs +3 -0
- data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
- data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
- data/test/MC/ARM/arm_instructions.s.cs +25 -0
- data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
- data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
- data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
- data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
- data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
- data/test/MC/ARM/crc32-thumb.s.cs +7 -0
- data/test/MC/ARM/crc32.s.cs +7 -0
- data/test/MC/ARM/dot-req.s.cs +3 -0
- data/test/MC/ARM/fp-armv8.s.cs +52 -0
- data/test/MC/ARM/idiv-thumb.s.cs +3 -0
- data/test/MC/ARM/idiv.s.cs +3 -0
- data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
- data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
- data/test/MC/ARM/mode-switch.s.cs +7 -0
- data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
- data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
- data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
- data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
- data/test/MC/ARM/neon-crypto.s.cs +16 -0
- data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
- data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
- data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
- data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
- data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
- data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
- data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
- data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neon-v8.s.cs +38 -0
- data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
- data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
- data/test/MC/ARM/neon-vswp.s.cs +3 -0
- data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
- data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
- data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
- data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
- data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
- data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
- data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
- data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
- data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
- data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
- data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
- data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
- data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
- data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
- data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
- data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
- data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
- data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
- data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
- data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
- data/test/MC/ARM/thumb-hints.s.cs +12 -0
- data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
- data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
- data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
- data/test/MC/ARM/thumb.s.cs +19 -0
- data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
- data/test/MC/ARM/thumb2-branches.s.cs +85 -0
- data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
- data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
- data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
- data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
- data/test/MC/ARM/vfp4.s.cs +13 -0
- data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
- data/test/MC/ARM/vpush-vpop.s.cs +9 -0
- data/test/MC/Mips/hilo-addressing.s.cs +4 -0
- data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
- data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
- data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
- data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
- data/test/MC/Mips/micromips-expansions.s.cs +20 -0
- data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
- data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
- data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
- data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
- data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
- data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
- data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
- data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
- data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
- data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
- data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
- data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
- data/test/MC/Mips/mips-expansions.s.cs +20 -0
- data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
- data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
- data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
- data/test/MC/Mips/mips-register-names.s.cs +33 -0
- data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
- data/test/MC/Mips/mips64-instructions.s.cs +3 -0
- data/test/MC/Mips/mips64-register-names.s.cs +33 -0
- data/test/MC/Mips/mips_directives.s.cs +12 -0
- data/test/MC/Mips/nabi-regs.s.cs +12 -0
- data/test/MC/Mips/set-at-directive.s.cs +6 -0
- data/test/MC/Mips/test_2r.s.cs +16 -0
- data/test/MC/Mips/test_2rf.s.cs +33 -0
- data/test/MC/Mips/test_3r.s.cs +243 -0
- data/test/MC/Mips/test_3rf.s.cs +83 -0
- data/test/MC/Mips/test_bit.s.cs +49 -0
- data/test/MC/Mips/test_cbranch.s.cs +11 -0
- data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
- data/test/MC/Mips/test_elm.s.cs +16 -0
- data/test/MC/Mips/test_elm_insert.s.cs +4 -0
- data/test/MC/Mips/test_elm_insve.s.cs +5 -0
- data/test/MC/Mips/test_i10.s.cs +5 -0
- data/test/MC/Mips/test_i5.s.cs +45 -0
- data/test/MC/Mips/test_i8.s.cs +11 -0
- data/test/MC/Mips/test_lsa.s.cs +5 -0
- data/test/MC/Mips/test_mi10.s.cs +24 -0
- data/test/MC/Mips/test_vec.s.cs +8 -0
- data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
- data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
- data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
- data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
- data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
- data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
- data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
- data/test/MC/README +6 -0
- data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
- data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
- data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
- data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
- data/test/MC/Sparc/sparc-vis.s.cs +2 -0
- data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
- data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
- data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
- data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
- data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
- data/test/MC/SystemZ/insn-good.s.cs +2265 -0
- data/test/MC/SystemZ/regs-good.s.cs +45 -0
- data/test/MC/X86/3DNow.s.cs +29 -0
- data/test/MC/X86/address-size.s.cs +5 -0
- data/test/MC/X86/avx512-encodings.s.cs +12 -0
- data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
- data/test/MC/X86/x86-32-avx.s.cs +833 -0
- data/test/MC/X86/x86-32-fma3.s.cs +169 -0
- data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
- data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
- data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
- data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
- data/test/MC/X86/x86_64-encoding.s.cs +59 -0
- data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
- data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
- data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
- data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
- data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
- data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
- data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
- data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
- data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
- data/test/README +6 -0
- data/test/test.rb +205 -0
- data/test/test.rb.SPEC +235 -0
- data/test/test_arm.rb +202 -0
- data/test/test_arm.rb.SPEC +275 -0
- data/test/test_arm64.rb +150 -0
- data/test/test_arm64.rb.SPEC +116 -0
- data/test/test_detail.rb +228 -0
- data/test/test_detail.rb.SPEC +322 -0
- data/test/test_exhaustive.rb +80 -0
- data/test/test_mips.rb +118 -0
- data/test/test_mips.rb.SPEC +91 -0
- data/test/test_ppc.rb +137 -0
- data/test/test_ppc.rb.SPEC +84 -0
- data/test/test_sanity.rb +83 -0
- data/test/test_skipdata.rb +111 -0
- data/test/test_skipdata.rb.SPEC +58 -0
- data/test/test_sparc.rb +113 -0
- data/test/test_sparc.rb.SPEC +116 -0
- data/test/test_sysz.rb +111 -0
- data/test/test_sysz.rb.SPEC +61 -0
- data/test/test_x86.rb +189 -0
- data/test/test_x86.rb.SPEC +579 -0
- data/test/test_xcore.rb +100 -0
- data/test/test_xcore.rb.SPEC +75 -0
- metadata +393 -0
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# Library by Nguyen Anh Quynh
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# Original binding by Nguyen Anh Quynh and Tan Sheng Di
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# Additional binding work by Ben Nagy
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# (c) 2013 COSEINC. All Rights Reserved.
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# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
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# Command: ./genreg /Users/ben/src/capstone/bindings/python/capstone/
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# 2015-05-02T13:24:07+12:00
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module Crabstone
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module MIPS
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REG_LOOKUP = {
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'INVALID' => 0,
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'0' => 1,
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'1' => 2,
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'2' => 3,
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'3' => 4,
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'4' => 5,
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'5' => 6,
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'6' => 7,
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'7' => 8,
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'8' => 9,
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'9' => 10,
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'13' => 14,
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28
|
+
'14' => 15,
|
29
|
+
'15' => 16,
|
30
|
+
'16' => 17,
|
31
|
+
'17' => 18,
|
32
|
+
'18' => 19,
|
33
|
+
'19' => 20,
|
34
|
+
'20' => 21,
|
35
|
+
'21' => 22,
|
36
|
+
'22' => 23,
|
37
|
+
'23' => 24,
|
38
|
+
'24' => 25,
|
39
|
+
'25' => 26,
|
40
|
+
'26' => 27,
|
41
|
+
'27' => 28,
|
42
|
+
'28' => 29,
|
43
|
+
'29' => 30,
|
44
|
+
'30' => 31,
|
45
|
+
'31' => 32,
|
46
|
+
'DSPCCOND' => 33,
|
47
|
+
'DSPCARRY' => 34,
|
48
|
+
'DSPEFI' => 35,
|
49
|
+
'DSPOUTFLAG' => 36,
|
50
|
+
'DSPOUTFLAG16_19' => 37,
|
51
|
+
'DSPOUTFLAG20' => 38,
|
52
|
+
'DSPOUTFLAG21' => 39,
|
53
|
+
'DSPOUTFLAG22' => 40,
|
54
|
+
'DSPOUTFLAG23' => 41,
|
55
|
+
'DSPPOS' => 42,
|
56
|
+
'DSPSCOUNT' => 43,
|
57
|
+
'AC0' => 44,
|
58
|
+
'AC1' => 45,
|
59
|
+
'AC2' => 46,
|
60
|
+
'AC3' => 47,
|
61
|
+
'CC0' => 48,
|
62
|
+
'CC1' => 49,
|
63
|
+
'CC2' => 50,
|
64
|
+
'CC3' => 51,
|
65
|
+
'CC4' => 52,
|
66
|
+
'CC5' => 53,
|
67
|
+
'CC6' => 54,
|
68
|
+
'CC7' => 55,
|
69
|
+
'F0' => 56,
|
70
|
+
'F1' => 57,
|
71
|
+
'F2' => 58,
|
72
|
+
'F3' => 59,
|
73
|
+
'F4' => 60,
|
74
|
+
'F5' => 61,
|
75
|
+
'F6' => 62,
|
76
|
+
'F7' => 63,
|
77
|
+
'F8' => 64,
|
78
|
+
'F9' => 65,
|
79
|
+
'F10' => 66,
|
80
|
+
'F11' => 67,
|
81
|
+
'F12' => 68,
|
82
|
+
'F13' => 69,
|
83
|
+
'F14' => 70,
|
84
|
+
'F15' => 71,
|
85
|
+
'F16' => 72,
|
86
|
+
'F17' => 73,
|
87
|
+
'F18' => 74,
|
88
|
+
'F19' => 75,
|
89
|
+
'F20' => 76,
|
90
|
+
'F21' => 77,
|
91
|
+
'F22' => 78,
|
92
|
+
'F23' => 79,
|
93
|
+
'F24' => 80,
|
94
|
+
'F25' => 81,
|
95
|
+
'F26' => 82,
|
96
|
+
'F27' => 83,
|
97
|
+
'F28' => 84,
|
98
|
+
'F29' => 85,
|
99
|
+
'F30' => 86,
|
100
|
+
'F31' => 87,
|
101
|
+
'FCC0' => 88,
|
102
|
+
'FCC1' => 89,
|
103
|
+
'FCC2' => 90,
|
104
|
+
'FCC3' => 91,
|
105
|
+
'FCC4' => 92,
|
106
|
+
'FCC5' => 93,
|
107
|
+
'FCC6' => 94,
|
108
|
+
'FCC7' => 95,
|
109
|
+
'W0' => 96,
|
110
|
+
'W1' => 97,
|
111
|
+
'W2' => 98,
|
112
|
+
'W3' => 99,
|
113
|
+
'W4' => 100,
|
114
|
+
'W5' => 101,
|
115
|
+
'W6' => 102,
|
116
|
+
'W7' => 103,
|
117
|
+
'W8' => 104,
|
118
|
+
'W9' => 105,
|
119
|
+
'W10' => 106,
|
120
|
+
'W11' => 107,
|
121
|
+
'W12' => 108,
|
122
|
+
'W13' => 109,
|
123
|
+
'W14' => 110,
|
124
|
+
'W15' => 111,
|
125
|
+
'W16' => 112,
|
126
|
+
'W17' => 113,
|
127
|
+
'W18' => 114,
|
128
|
+
'W19' => 115,
|
129
|
+
'W20' => 116,
|
130
|
+
'W21' => 117,
|
131
|
+
'W22' => 118,
|
132
|
+
'W23' => 119,
|
133
|
+
'W24' => 120,
|
134
|
+
'W25' => 121,
|
135
|
+
'W26' => 122,
|
136
|
+
'W27' => 123,
|
137
|
+
'W28' => 124,
|
138
|
+
'W29' => 125,
|
139
|
+
'W30' => 126,
|
140
|
+
'W31' => 127,
|
141
|
+
'HI' => 128,
|
142
|
+
'LO' => 129,
|
143
|
+
'P0' => 130,
|
144
|
+
'P1' => 131,
|
145
|
+
'P2' => 132,
|
146
|
+
'MPL0' => 133,
|
147
|
+
'MPL1' => 134,
|
148
|
+
'MPL2' => 135
|
149
|
+
}
|
150
|
+
|
151
|
+
ID_LOOKUP = REG_LOOKUP.invert
|
152
|
+
|
153
|
+
# alias registers
|
154
|
+
REG_LOOKUP['ZERO'] = REG_LOOKUP['0']
|
155
|
+
REG_LOOKUP['AT'] = REG_LOOKUP['1']
|
156
|
+
REG_LOOKUP['V0'] = REG_LOOKUP['2']
|
157
|
+
REG_LOOKUP['V1'] = REG_LOOKUP['3']
|
158
|
+
REG_LOOKUP['A0'] = REG_LOOKUP['4']
|
159
|
+
REG_LOOKUP['A1'] = REG_LOOKUP['5']
|
160
|
+
REG_LOOKUP['A2'] = REG_LOOKUP['6']
|
161
|
+
REG_LOOKUP['A3'] = REG_LOOKUP['7']
|
162
|
+
REG_LOOKUP['T0'] = REG_LOOKUP['8']
|
163
|
+
REG_LOOKUP['T1'] = REG_LOOKUP['9']
|
164
|
+
REG_LOOKUP['T2'] = REG_LOOKUP['10']
|
165
|
+
REG_LOOKUP['T3'] = REG_LOOKUP['11']
|
166
|
+
REG_LOOKUP['T4'] = REG_LOOKUP['12']
|
167
|
+
REG_LOOKUP['T5'] = REG_LOOKUP['13']
|
168
|
+
REG_LOOKUP['T6'] = REG_LOOKUP['14']
|
169
|
+
REG_LOOKUP['T7'] = REG_LOOKUP['15']
|
170
|
+
REG_LOOKUP['S0'] = REG_LOOKUP['16']
|
171
|
+
REG_LOOKUP['S1'] = REG_LOOKUP['17']
|
172
|
+
REG_LOOKUP['S2'] = REG_LOOKUP['18']
|
173
|
+
REG_LOOKUP['S3'] = REG_LOOKUP['19']
|
174
|
+
REG_LOOKUP['S4'] = REG_LOOKUP['20']
|
175
|
+
REG_LOOKUP['S5'] = REG_LOOKUP['21']
|
176
|
+
REG_LOOKUP['S6'] = REG_LOOKUP['22']
|
177
|
+
REG_LOOKUP['S7'] = REG_LOOKUP['23']
|
178
|
+
REG_LOOKUP['T8'] = REG_LOOKUP['24']
|
179
|
+
REG_LOOKUP['T9'] = REG_LOOKUP['25']
|
180
|
+
REG_LOOKUP['K0'] = REG_LOOKUP['26']
|
181
|
+
REG_LOOKUP['K1'] = REG_LOOKUP['27']
|
182
|
+
REG_LOOKUP['GP'] = REG_LOOKUP['28']
|
183
|
+
REG_LOOKUP['SP'] = REG_LOOKUP['29']
|
184
|
+
REG_LOOKUP['FP'] = REG_LOOKUP['30']
|
185
|
+
REG_LOOKUP['S8'] = REG_LOOKUP['30']
|
186
|
+
REG_LOOKUP['RA'] = REG_LOOKUP['31']
|
187
|
+
REG_LOOKUP['HI0'] = REG_LOOKUP['AC0']
|
188
|
+
REG_LOOKUP['HI1'] = REG_LOOKUP['AC1']
|
189
|
+
REG_LOOKUP['HI2'] = REG_LOOKUP['AC2']
|
190
|
+
REG_LOOKUP['HI3'] = REG_LOOKUP['AC3']
|
191
|
+
REG_LOOKUP['LO0'] = REG_LOOKUP['HI0']
|
192
|
+
REG_LOOKUP['LO1'] = REG_LOOKUP['HI1']
|
193
|
+
REG_LOOKUP['LO2'] = REG_LOOKUP['HI2']
|
194
|
+
REG_LOOKUP['LO3'] = REG_LOOKUP['HI3']
|
195
|
+
|
196
|
+
SYM_LOOKUP = Hash[REG_LOOKUP.map {|k,v| [k.downcase.to_sym,v]}]
|
197
|
+
|
198
|
+
def self.register reg
|
199
|
+
return reg if ID_LOOKUP[reg]
|
200
|
+
return SYM_LOOKUP[reg] if SYM_LOOKUP[reg]
|
201
|
+
if reg.respond_to? :upcase
|
202
|
+
return REG_LOOKUP[reg.upcase] || REG_LOOKUP['INVALID']
|
203
|
+
end
|
204
|
+
REG_LOOKUP['INVALID']
|
205
|
+
end
|
206
|
+
|
207
|
+
end
|
208
|
+
end
|
data/lib/arch/ppc.rb
ADDED
@@ -0,0 +1,90 @@
|
|
1
|
+
# Library by Nguyen Anh Quynh
|
2
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
3
|
+
# Additional binding work by Ben Nagy
|
4
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
5
|
+
|
6
|
+
require 'ffi'
|
7
|
+
|
8
|
+
require_relative 'ppc_const'
|
9
|
+
|
10
|
+
module Crabstone
|
11
|
+
module PPC
|
12
|
+
|
13
|
+
class MemoryOperand < FFI::Struct
|
14
|
+
layout(
|
15
|
+
:base, :uint,
|
16
|
+
:disp, :int32
|
17
|
+
)
|
18
|
+
end
|
19
|
+
|
20
|
+
class CrxOperand < FFI::Struct
|
21
|
+
layout(
|
22
|
+
:scale, :uint,
|
23
|
+
:reg, :uint,
|
24
|
+
:cond, :uint
|
25
|
+
)
|
26
|
+
end
|
27
|
+
|
28
|
+
class OperandValue < FFI::Union
|
29
|
+
layout(
|
30
|
+
:reg, :uint,
|
31
|
+
:imm, :int32,
|
32
|
+
:mem, MemoryOperand,
|
33
|
+
:crx, CrxOperand
|
34
|
+
)
|
35
|
+
end
|
36
|
+
|
37
|
+
class Operand < FFI::Struct
|
38
|
+
layout(
|
39
|
+
:type, :uint,
|
40
|
+
:value, OperandValue
|
41
|
+
)
|
42
|
+
|
43
|
+
def value
|
44
|
+
case self[:type]
|
45
|
+
when OP_REG
|
46
|
+
self[:value][:reg]
|
47
|
+
when OP_IMM
|
48
|
+
self[:value][:imm]
|
49
|
+
when OP_MEM
|
50
|
+
self[:value][:mem]
|
51
|
+
when OP_CRX
|
52
|
+
self[:value][:crx]
|
53
|
+
else
|
54
|
+
nil
|
55
|
+
end
|
56
|
+
end
|
57
|
+
|
58
|
+
def reg?
|
59
|
+
self[:type] == OP_REG
|
60
|
+
end
|
61
|
+
|
62
|
+
def imm?
|
63
|
+
self[:type] == OP_IMM
|
64
|
+
end
|
65
|
+
|
66
|
+
def mem?
|
67
|
+
self[:type] == OP_MEM
|
68
|
+
end
|
69
|
+
|
70
|
+
def valid?
|
71
|
+
[OP_MEM, OP_IMM, OP_REG].include? self[:type]
|
72
|
+
end
|
73
|
+
end
|
74
|
+
|
75
|
+
class Instruction < FFI::Struct
|
76
|
+
layout(
|
77
|
+
:bc, :uint,
|
78
|
+
:bh, :uint,
|
79
|
+
:update_cr0, :bool,
|
80
|
+
:op_count, :uint8,
|
81
|
+
:operands, [Operand, 8],
|
82
|
+
)
|
83
|
+
|
84
|
+
def operands
|
85
|
+
self[:operands].take_while {|op| op[:type].nonzero?}
|
86
|
+
end
|
87
|
+
|
88
|
+
end
|
89
|
+
end
|
90
|
+
end
|
@@ -0,0 +1,1181 @@
|
|
1
|
+
# Library by Nguyen Anh Quynh
|
2
|
+
# Original binding by Nguyen Anh Quynh and Tan Sheng Di
|
3
|
+
# Additional binding work by Ben Nagy
|
4
|
+
# (c) 2013 COSEINC. All Rights Reserved.
|
5
|
+
|
6
|
+
# THIS FILE WAS AUTO-GENERATED -- DO NOT EDIT!
|
7
|
+
# Command: ./genconst /Users/ben/src/capstone/bindings/python/capstone/
|
8
|
+
# 2015-05-02T13:24:01+12:00
|
9
|
+
|
10
|
+
module Crabstone
|
11
|
+
module PPC
|
12
|
+
|
13
|
+
# PPC branch codes for some branch instructions
|
14
|
+
|
15
|
+
BC_INVALID = 0
|
16
|
+
BC_LT = (0<<5)|12
|
17
|
+
BC_LE = (1<<5)|4
|
18
|
+
BC_EQ = (2<<5)|12
|
19
|
+
BC_GE = (0<<5)|4
|
20
|
+
BC_GT = (1<<5)|12
|
21
|
+
BC_NE = (2<<5)|4
|
22
|
+
BC_UN = (3<<5)|12
|
23
|
+
BC_NU = (3<<5)|4
|
24
|
+
BC_SO = (4<<5)|12
|
25
|
+
BC_NS = (4<<5)|4
|
26
|
+
|
27
|
+
# PPC branch hint for some branch instructions
|
28
|
+
|
29
|
+
BH_INVALID = 0
|
30
|
+
BH_PLUS = 1
|
31
|
+
BH_MINUS = 2
|
32
|
+
|
33
|
+
# Operand type for instruction's operands
|
34
|
+
|
35
|
+
OP_INVALID = 0
|
36
|
+
OP_REG = 1
|
37
|
+
OP_IMM = 2
|
38
|
+
OP_MEM = 3
|
39
|
+
OP_CRX = 64
|
40
|
+
|
41
|
+
# PPC registers
|
42
|
+
|
43
|
+
REG_INVALID = 0
|
44
|
+
REG_CARRY = 1
|
45
|
+
REG_CC = 2
|
46
|
+
REG_CR0 = 3
|
47
|
+
REG_CR1 = 4
|
48
|
+
REG_CR2 = 5
|
49
|
+
REG_CR3 = 6
|
50
|
+
REG_CR4 = 7
|
51
|
+
REG_CR5 = 8
|
52
|
+
REG_CR6 = 9
|
53
|
+
REG_CR7 = 10
|
54
|
+
REG_CTR = 11
|
55
|
+
REG_F0 = 12
|
56
|
+
REG_F1 = 13
|
57
|
+
REG_F2 = 14
|
58
|
+
REG_F3 = 15
|
59
|
+
REG_F4 = 16
|
60
|
+
REG_F5 = 17
|
61
|
+
REG_F6 = 18
|
62
|
+
REG_F7 = 19
|
63
|
+
REG_F8 = 20
|
64
|
+
REG_F9 = 21
|
65
|
+
REG_F10 = 22
|
66
|
+
REG_F11 = 23
|
67
|
+
REG_F12 = 24
|
68
|
+
REG_F13 = 25
|
69
|
+
REG_F14 = 26
|
70
|
+
REG_F15 = 27
|
71
|
+
REG_F16 = 28
|
72
|
+
REG_F17 = 29
|
73
|
+
REG_F18 = 30
|
74
|
+
REG_F19 = 31
|
75
|
+
REG_F20 = 32
|
76
|
+
REG_F21 = 33
|
77
|
+
REG_F22 = 34
|
78
|
+
REG_F23 = 35
|
79
|
+
REG_F24 = 36
|
80
|
+
REG_F25 = 37
|
81
|
+
REG_F26 = 38
|
82
|
+
REG_F27 = 39
|
83
|
+
REG_F28 = 40
|
84
|
+
REG_F29 = 41
|
85
|
+
REG_F30 = 42
|
86
|
+
REG_F31 = 43
|
87
|
+
REG_LR = 44
|
88
|
+
REG_R0 = 45
|
89
|
+
REG_R1 = 46
|
90
|
+
REG_R2 = 47
|
91
|
+
REG_R3 = 48
|
92
|
+
REG_R4 = 49
|
93
|
+
REG_R5 = 50
|
94
|
+
REG_R6 = 51
|
95
|
+
REG_R7 = 52
|
96
|
+
REG_R8 = 53
|
97
|
+
REG_R9 = 54
|
98
|
+
REG_R10 = 55
|
99
|
+
REG_R11 = 56
|
100
|
+
REG_R12 = 57
|
101
|
+
REG_R13 = 58
|
102
|
+
REG_R14 = 59
|
103
|
+
REG_R15 = 60
|
104
|
+
REG_R16 = 61
|
105
|
+
REG_R17 = 62
|
106
|
+
REG_R18 = 63
|
107
|
+
REG_R19 = 64
|
108
|
+
REG_R20 = 65
|
109
|
+
REG_R21 = 66
|
110
|
+
REG_R22 = 67
|
111
|
+
REG_R23 = 68
|
112
|
+
REG_R24 = 69
|
113
|
+
REG_R25 = 70
|
114
|
+
REG_R26 = 71
|
115
|
+
REG_R27 = 72
|
116
|
+
REG_R28 = 73
|
117
|
+
REG_R29 = 74
|
118
|
+
REG_R30 = 75
|
119
|
+
REG_R31 = 76
|
120
|
+
REG_V0 = 77
|
121
|
+
REG_V1 = 78
|
122
|
+
REG_V2 = 79
|
123
|
+
REG_V3 = 80
|
124
|
+
REG_V4 = 81
|
125
|
+
REG_V5 = 82
|
126
|
+
REG_V6 = 83
|
127
|
+
REG_V7 = 84
|
128
|
+
REG_V8 = 85
|
129
|
+
REG_V9 = 86
|
130
|
+
REG_V10 = 87
|
131
|
+
REG_V11 = 88
|
132
|
+
REG_V12 = 89
|
133
|
+
REG_V13 = 90
|
134
|
+
REG_V14 = 91
|
135
|
+
REG_V15 = 92
|
136
|
+
REG_V16 = 93
|
137
|
+
REG_V17 = 94
|
138
|
+
REG_V18 = 95
|
139
|
+
REG_V19 = 96
|
140
|
+
REG_V20 = 97
|
141
|
+
REG_V21 = 98
|
142
|
+
REG_V22 = 99
|
143
|
+
REG_V23 = 100
|
144
|
+
REG_V24 = 101
|
145
|
+
REG_V25 = 102
|
146
|
+
REG_V26 = 103
|
147
|
+
REG_V27 = 104
|
148
|
+
REG_V28 = 105
|
149
|
+
REG_V29 = 106
|
150
|
+
REG_V30 = 107
|
151
|
+
REG_V31 = 108
|
152
|
+
REG_VRSAVE = 109
|
153
|
+
REG_VS0 = 110
|
154
|
+
REG_VS1 = 111
|
155
|
+
REG_VS2 = 112
|
156
|
+
REG_VS3 = 113
|
157
|
+
REG_VS4 = 114
|
158
|
+
REG_VS5 = 115
|
159
|
+
REG_VS6 = 116
|
160
|
+
REG_VS7 = 117
|
161
|
+
REG_VS8 = 118
|
162
|
+
REG_VS9 = 119
|
163
|
+
REG_VS10 = 120
|
164
|
+
REG_VS11 = 121
|
165
|
+
REG_VS12 = 122
|
166
|
+
REG_VS13 = 123
|
167
|
+
REG_VS14 = 124
|
168
|
+
REG_VS15 = 125
|
169
|
+
REG_VS16 = 126
|
170
|
+
REG_VS17 = 127
|
171
|
+
REG_VS18 = 128
|
172
|
+
REG_VS19 = 129
|
173
|
+
REG_VS20 = 130
|
174
|
+
REG_VS21 = 131
|
175
|
+
REG_VS22 = 132
|
176
|
+
REG_VS23 = 133
|
177
|
+
REG_VS24 = 134
|
178
|
+
REG_VS25 = 135
|
179
|
+
REG_VS26 = 136
|
180
|
+
REG_VS27 = 137
|
181
|
+
REG_VS28 = 138
|
182
|
+
REG_VS29 = 139
|
183
|
+
REG_VS30 = 140
|
184
|
+
REG_VS31 = 141
|
185
|
+
REG_VS32 = 142
|
186
|
+
REG_VS33 = 143
|
187
|
+
REG_VS34 = 144
|
188
|
+
REG_VS35 = 145
|
189
|
+
REG_VS36 = 146
|
190
|
+
REG_VS37 = 147
|
191
|
+
REG_VS38 = 148
|
192
|
+
REG_VS39 = 149
|
193
|
+
REG_VS40 = 150
|
194
|
+
REG_VS41 = 151
|
195
|
+
REG_VS42 = 152
|
196
|
+
REG_VS43 = 153
|
197
|
+
REG_VS44 = 154
|
198
|
+
REG_VS45 = 155
|
199
|
+
REG_VS46 = 156
|
200
|
+
REG_VS47 = 157
|
201
|
+
REG_VS48 = 158
|
202
|
+
REG_VS49 = 159
|
203
|
+
REG_VS50 = 160
|
204
|
+
REG_VS51 = 161
|
205
|
+
REG_VS52 = 162
|
206
|
+
REG_VS53 = 163
|
207
|
+
REG_VS54 = 164
|
208
|
+
REG_VS55 = 165
|
209
|
+
REG_VS56 = 166
|
210
|
+
REG_VS57 = 167
|
211
|
+
REG_VS58 = 168
|
212
|
+
REG_VS59 = 169
|
213
|
+
REG_VS60 = 170
|
214
|
+
REG_VS61 = 171
|
215
|
+
REG_VS62 = 172
|
216
|
+
REG_VS63 = 173
|
217
|
+
REG_RM = 174
|
218
|
+
REG_CTR8 = 175
|
219
|
+
REG_LR8 = 176
|
220
|
+
REG_CR1EQ = 177
|
221
|
+
REG_ENDING = 178
|
222
|
+
|
223
|
+
# PPC instruction
|
224
|
+
|
225
|
+
INS_INVALID = 0
|
226
|
+
INS_ADD = 1
|
227
|
+
INS_ADDC = 2
|
228
|
+
INS_ADDE = 3
|
229
|
+
INS_ADDI = 4
|
230
|
+
INS_ADDIC = 5
|
231
|
+
INS_ADDIS = 6
|
232
|
+
INS_ADDME = 7
|
233
|
+
INS_ADDZE = 8
|
234
|
+
INS_AND = 9
|
235
|
+
INS_ANDC = 10
|
236
|
+
INS_ANDIS = 11
|
237
|
+
INS_ANDI = 12
|
238
|
+
INS_B = 13
|
239
|
+
INS_BA = 14
|
240
|
+
INS_BC = 15
|
241
|
+
INS_BCCTR = 16
|
242
|
+
INS_BCCTRL = 17
|
243
|
+
INS_BCL = 18
|
244
|
+
INS_BCLR = 19
|
245
|
+
INS_BCLRL = 20
|
246
|
+
INS_BCTR = 21
|
247
|
+
INS_BCTRL = 22
|
248
|
+
INS_BDNZ = 23
|
249
|
+
INS_BDNZA = 24
|
250
|
+
INS_BDNZL = 25
|
251
|
+
INS_BDNZLA = 26
|
252
|
+
INS_BDNZLR = 27
|
253
|
+
INS_BDNZLRL = 28
|
254
|
+
INS_BDZ = 29
|
255
|
+
INS_BDZA = 30
|
256
|
+
INS_BDZL = 31
|
257
|
+
INS_BDZLA = 32
|
258
|
+
INS_BDZLR = 33
|
259
|
+
INS_BDZLRL = 34
|
260
|
+
INS_BL = 35
|
261
|
+
INS_BLA = 36
|
262
|
+
INS_BLR = 37
|
263
|
+
INS_BLRL = 38
|
264
|
+
INS_BRINC = 39
|
265
|
+
INS_CMPD = 40
|
266
|
+
INS_CMPDI = 41
|
267
|
+
INS_CMPLD = 42
|
268
|
+
INS_CMPLDI = 43
|
269
|
+
INS_CMPLW = 44
|
270
|
+
INS_CMPLWI = 45
|
271
|
+
INS_CMPW = 46
|
272
|
+
INS_CMPWI = 47
|
273
|
+
INS_CNTLZD = 48
|
274
|
+
INS_CNTLZW = 49
|
275
|
+
INS_CREQV = 50
|
276
|
+
INS_CRXOR = 51
|
277
|
+
INS_CRAND = 52
|
278
|
+
INS_CRANDC = 53
|
279
|
+
INS_CRNAND = 54
|
280
|
+
INS_CRNOR = 55
|
281
|
+
INS_CROR = 56
|
282
|
+
INS_CRORC = 57
|
283
|
+
INS_DCBA = 58
|
284
|
+
INS_DCBF = 59
|
285
|
+
INS_DCBI = 60
|
286
|
+
INS_DCBST = 61
|
287
|
+
INS_DCBT = 62
|
288
|
+
INS_DCBTST = 63
|
289
|
+
INS_DCBZ = 64
|
290
|
+
INS_DCBZL = 65
|
291
|
+
INS_DCCCI = 66
|
292
|
+
INS_DIVD = 67
|
293
|
+
INS_DIVDU = 68
|
294
|
+
INS_DIVW = 69
|
295
|
+
INS_DIVWU = 70
|
296
|
+
INS_DSS = 71
|
297
|
+
INS_DSSALL = 72
|
298
|
+
INS_DST = 73
|
299
|
+
INS_DSTST = 74
|
300
|
+
INS_DSTSTT = 75
|
301
|
+
INS_DSTT = 76
|
302
|
+
INS_EIEIO = 77
|
303
|
+
INS_EQV = 78
|
304
|
+
INS_EVABS = 79
|
305
|
+
INS_EVADDIW = 80
|
306
|
+
INS_EVADDSMIAAW = 81
|
307
|
+
INS_EVADDSSIAAW = 82
|
308
|
+
INS_EVADDUMIAAW = 83
|
309
|
+
INS_EVADDUSIAAW = 84
|
310
|
+
INS_EVADDW = 85
|
311
|
+
INS_EVAND = 86
|
312
|
+
INS_EVANDC = 87
|
313
|
+
INS_EVCMPEQ = 88
|
314
|
+
INS_EVCMPGTS = 89
|
315
|
+
INS_EVCMPGTU = 90
|
316
|
+
INS_EVCMPLTS = 91
|
317
|
+
INS_EVCMPLTU = 92
|
318
|
+
INS_EVCNTLSW = 93
|
319
|
+
INS_EVCNTLZW = 94
|
320
|
+
INS_EVDIVWS = 95
|
321
|
+
INS_EVDIVWU = 96
|
322
|
+
INS_EVEQV = 97
|
323
|
+
INS_EVEXTSB = 98
|
324
|
+
INS_EVEXTSH = 99
|
325
|
+
INS_EVLDD = 100
|
326
|
+
INS_EVLDDX = 101
|
327
|
+
INS_EVLDH = 102
|
328
|
+
INS_EVLDHX = 103
|
329
|
+
INS_EVLDW = 104
|
330
|
+
INS_EVLDWX = 105
|
331
|
+
INS_EVLHHESPLAT = 106
|
332
|
+
INS_EVLHHESPLATX = 107
|
333
|
+
INS_EVLHHOSSPLAT = 108
|
334
|
+
INS_EVLHHOSSPLATX = 109
|
335
|
+
INS_EVLHHOUSPLAT = 110
|
336
|
+
INS_EVLHHOUSPLATX = 111
|
337
|
+
INS_EVLWHE = 112
|
338
|
+
INS_EVLWHEX = 113
|
339
|
+
INS_EVLWHOS = 114
|
340
|
+
INS_EVLWHOSX = 115
|
341
|
+
INS_EVLWHOU = 116
|
342
|
+
INS_EVLWHOUX = 117
|
343
|
+
INS_EVLWHSPLAT = 118
|
344
|
+
INS_EVLWHSPLATX = 119
|
345
|
+
INS_EVLWWSPLAT = 120
|
346
|
+
INS_EVLWWSPLATX = 121
|
347
|
+
INS_EVMERGEHI = 122
|
348
|
+
INS_EVMERGEHILO = 123
|
349
|
+
INS_EVMERGELO = 124
|
350
|
+
INS_EVMERGELOHI = 125
|
351
|
+
INS_EVMHEGSMFAA = 126
|
352
|
+
INS_EVMHEGSMFAN = 127
|
353
|
+
INS_EVMHEGSMIAA = 128
|
354
|
+
INS_EVMHEGSMIAN = 129
|
355
|
+
INS_EVMHEGUMIAA = 130
|
356
|
+
INS_EVMHEGUMIAN = 131
|
357
|
+
INS_EVMHESMF = 132
|
358
|
+
INS_EVMHESMFA = 133
|
359
|
+
INS_EVMHESMFAAW = 134
|
360
|
+
INS_EVMHESMFANW = 135
|
361
|
+
INS_EVMHESMI = 136
|
362
|
+
INS_EVMHESMIA = 137
|
363
|
+
INS_EVMHESMIAAW = 138
|
364
|
+
INS_EVMHESMIANW = 139
|
365
|
+
INS_EVMHESSF = 140
|
366
|
+
INS_EVMHESSFA = 141
|
367
|
+
INS_EVMHESSFAAW = 142
|
368
|
+
INS_EVMHESSFANW = 143
|
369
|
+
INS_EVMHESSIAAW = 144
|
370
|
+
INS_EVMHESSIANW = 145
|
371
|
+
INS_EVMHEUMI = 146
|
372
|
+
INS_EVMHEUMIA = 147
|
373
|
+
INS_EVMHEUMIAAW = 148
|
374
|
+
INS_EVMHEUMIANW = 149
|
375
|
+
INS_EVMHEUSIAAW = 150
|
376
|
+
INS_EVMHEUSIANW = 151
|
377
|
+
INS_EVMHOGSMFAA = 152
|
378
|
+
INS_EVMHOGSMFAN = 153
|
379
|
+
INS_EVMHOGSMIAA = 154
|
380
|
+
INS_EVMHOGSMIAN = 155
|
381
|
+
INS_EVMHOGUMIAA = 156
|
382
|
+
INS_EVMHOGUMIAN = 157
|
383
|
+
INS_EVMHOSMF = 158
|
384
|
+
INS_EVMHOSMFA = 159
|
385
|
+
INS_EVMHOSMFAAW = 160
|
386
|
+
INS_EVMHOSMFANW = 161
|
387
|
+
INS_EVMHOSMI = 162
|
388
|
+
INS_EVMHOSMIA = 163
|
389
|
+
INS_EVMHOSMIAAW = 164
|
390
|
+
INS_EVMHOSMIANW = 165
|
391
|
+
INS_EVMHOSSF = 166
|
392
|
+
INS_EVMHOSSFA = 167
|
393
|
+
INS_EVMHOSSFAAW = 168
|
394
|
+
INS_EVMHOSSFANW = 169
|
395
|
+
INS_EVMHOSSIAAW = 170
|
396
|
+
INS_EVMHOSSIANW = 171
|
397
|
+
INS_EVMHOUMI = 172
|
398
|
+
INS_EVMHOUMIA = 173
|
399
|
+
INS_EVMHOUMIAAW = 174
|
400
|
+
INS_EVMHOUMIANW = 175
|
401
|
+
INS_EVMHOUSIAAW = 176
|
402
|
+
INS_EVMHOUSIANW = 177
|
403
|
+
INS_EVMRA = 178
|
404
|
+
INS_EVMWHSMF = 179
|
405
|
+
INS_EVMWHSMFA = 180
|
406
|
+
INS_EVMWHSMI = 181
|
407
|
+
INS_EVMWHSMIA = 182
|
408
|
+
INS_EVMWHSSF = 183
|
409
|
+
INS_EVMWHSSFA = 184
|
410
|
+
INS_EVMWHUMI = 185
|
411
|
+
INS_EVMWHUMIA = 186
|
412
|
+
INS_EVMWLSMIAAW = 187
|
413
|
+
INS_EVMWLSMIANW = 188
|
414
|
+
INS_EVMWLSSIAAW = 189
|
415
|
+
INS_EVMWLSSIANW = 190
|
416
|
+
INS_EVMWLUMI = 191
|
417
|
+
INS_EVMWLUMIA = 192
|
418
|
+
INS_EVMWLUMIAAW = 193
|
419
|
+
INS_EVMWLUMIANW = 194
|
420
|
+
INS_EVMWLUSIAAW = 195
|
421
|
+
INS_EVMWLUSIANW = 196
|
422
|
+
INS_EVMWSMF = 197
|
423
|
+
INS_EVMWSMFA = 198
|
424
|
+
INS_EVMWSMFAA = 199
|
425
|
+
INS_EVMWSMFAN = 200
|
426
|
+
INS_EVMWSMI = 201
|
427
|
+
INS_EVMWSMIA = 202
|
428
|
+
INS_EVMWSMIAA = 203
|
429
|
+
INS_EVMWSMIAN = 204
|
430
|
+
INS_EVMWSSF = 205
|
431
|
+
INS_EVMWSSFA = 206
|
432
|
+
INS_EVMWSSFAA = 207
|
433
|
+
INS_EVMWSSFAN = 208
|
434
|
+
INS_EVMWUMI = 209
|
435
|
+
INS_EVMWUMIA = 210
|
436
|
+
INS_EVMWUMIAA = 211
|
437
|
+
INS_EVMWUMIAN = 212
|
438
|
+
INS_EVNAND = 213
|
439
|
+
INS_EVNEG = 214
|
440
|
+
INS_EVNOR = 215
|
441
|
+
INS_EVOR = 216
|
442
|
+
INS_EVORC = 217
|
443
|
+
INS_EVRLW = 218
|
444
|
+
INS_EVRLWI = 219
|
445
|
+
INS_EVRNDW = 220
|
446
|
+
INS_EVSLW = 221
|
447
|
+
INS_EVSLWI = 222
|
448
|
+
INS_EVSPLATFI = 223
|
449
|
+
INS_EVSPLATI = 224
|
450
|
+
INS_EVSRWIS = 225
|
451
|
+
INS_EVSRWIU = 226
|
452
|
+
INS_EVSRWS = 227
|
453
|
+
INS_EVSRWU = 228
|
454
|
+
INS_EVSTDD = 229
|
455
|
+
INS_EVSTDDX = 230
|
456
|
+
INS_EVSTDH = 231
|
457
|
+
INS_EVSTDHX = 232
|
458
|
+
INS_EVSTDW = 233
|
459
|
+
INS_EVSTDWX = 234
|
460
|
+
INS_EVSTWHE = 235
|
461
|
+
INS_EVSTWHEX = 236
|
462
|
+
INS_EVSTWHO = 237
|
463
|
+
INS_EVSTWHOX = 238
|
464
|
+
INS_EVSTWWE = 239
|
465
|
+
INS_EVSTWWEX = 240
|
466
|
+
INS_EVSTWWO = 241
|
467
|
+
INS_EVSTWWOX = 242
|
468
|
+
INS_EVSUBFSMIAAW = 243
|
469
|
+
INS_EVSUBFSSIAAW = 244
|
470
|
+
INS_EVSUBFUMIAAW = 245
|
471
|
+
INS_EVSUBFUSIAAW = 246
|
472
|
+
INS_EVSUBFW = 247
|
473
|
+
INS_EVSUBIFW = 248
|
474
|
+
INS_EVXOR = 249
|
475
|
+
INS_EXTSB = 250
|
476
|
+
INS_EXTSH = 251
|
477
|
+
INS_EXTSW = 252
|
478
|
+
INS_FABS = 253
|
479
|
+
INS_FADD = 254
|
480
|
+
INS_FADDS = 255
|
481
|
+
INS_FCFID = 256
|
482
|
+
INS_FCFIDS = 257
|
483
|
+
INS_FCFIDU = 258
|
484
|
+
INS_FCFIDUS = 259
|
485
|
+
INS_FCMPU = 260
|
486
|
+
INS_FCPSGN = 261
|
487
|
+
INS_FCTID = 262
|
488
|
+
INS_FCTIDUZ = 263
|
489
|
+
INS_FCTIDZ = 264
|
490
|
+
INS_FCTIW = 265
|
491
|
+
INS_FCTIWUZ = 266
|
492
|
+
INS_FCTIWZ = 267
|
493
|
+
INS_FDIV = 268
|
494
|
+
INS_FDIVS = 269
|
495
|
+
INS_FMADD = 270
|
496
|
+
INS_FMADDS = 271
|
497
|
+
INS_FMR = 272
|
498
|
+
INS_FMSUB = 273
|
499
|
+
INS_FMSUBS = 274
|
500
|
+
INS_FMUL = 275
|
501
|
+
INS_FMULS = 276
|
502
|
+
INS_FNABS = 277
|
503
|
+
INS_FNEG = 278
|
504
|
+
INS_FNMADD = 279
|
505
|
+
INS_FNMADDS = 280
|
506
|
+
INS_FNMSUB = 281
|
507
|
+
INS_FNMSUBS = 282
|
508
|
+
INS_FRE = 283
|
509
|
+
INS_FRES = 284
|
510
|
+
INS_FRIM = 285
|
511
|
+
INS_FRIN = 286
|
512
|
+
INS_FRIP = 287
|
513
|
+
INS_FRIZ = 288
|
514
|
+
INS_FRSP = 289
|
515
|
+
INS_FRSQRTE = 290
|
516
|
+
INS_FRSQRTES = 291
|
517
|
+
INS_FSEL = 292
|
518
|
+
INS_FSQRT = 293
|
519
|
+
INS_FSQRTS = 294
|
520
|
+
INS_FSUB = 295
|
521
|
+
INS_FSUBS = 296
|
522
|
+
INS_ICBI = 297
|
523
|
+
INS_ICCCI = 298
|
524
|
+
INS_ISEL = 299
|
525
|
+
INS_ISYNC = 300
|
526
|
+
INS_LA = 301
|
527
|
+
INS_LBZ = 302
|
528
|
+
INS_LBZU = 303
|
529
|
+
INS_LBZUX = 304
|
530
|
+
INS_LBZX = 305
|
531
|
+
INS_LD = 306
|
532
|
+
INS_LDARX = 307
|
533
|
+
INS_LDBRX = 308
|
534
|
+
INS_LDU = 309
|
535
|
+
INS_LDUX = 310
|
536
|
+
INS_LDX = 311
|
537
|
+
INS_LFD = 312
|
538
|
+
INS_LFDU = 313
|
539
|
+
INS_LFDUX = 314
|
540
|
+
INS_LFDX = 315
|
541
|
+
INS_LFIWAX = 316
|
542
|
+
INS_LFIWZX = 317
|
543
|
+
INS_LFS = 318
|
544
|
+
INS_LFSU = 319
|
545
|
+
INS_LFSUX = 320
|
546
|
+
INS_LFSX = 321
|
547
|
+
INS_LHA = 322
|
548
|
+
INS_LHAU = 323
|
549
|
+
INS_LHAUX = 324
|
550
|
+
INS_LHAX = 325
|
551
|
+
INS_LHBRX = 326
|
552
|
+
INS_LHZ = 327
|
553
|
+
INS_LHZU = 328
|
554
|
+
INS_LHZUX = 329
|
555
|
+
INS_LHZX = 330
|
556
|
+
INS_LI = 331
|
557
|
+
INS_LIS = 332
|
558
|
+
INS_LMW = 333
|
559
|
+
INS_LSWI = 334
|
560
|
+
INS_LVEBX = 335
|
561
|
+
INS_LVEHX = 336
|
562
|
+
INS_LVEWX = 337
|
563
|
+
INS_LVSL = 338
|
564
|
+
INS_LVSR = 339
|
565
|
+
INS_LVX = 340
|
566
|
+
INS_LVXL = 341
|
567
|
+
INS_LWA = 342
|
568
|
+
INS_LWARX = 343
|
569
|
+
INS_LWAUX = 344
|
570
|
+
INS_LWAX = 345
|
571
|
+
INS_LWBRX = 346
|
572
|
+
INS_LWZ = 347
|
573
|
+
INS_LWZU = 348
|
574
|
+
INS_LWZUX = 349
|
575
|
+
INS_LWZX = 350
|
576
|
+
INS_LXSDX = 351
|
577
|
+
INS_LXVD2X = 352
|
578
|
+
INS_LXVDSX = 353
|
579
|
+
INS_LXVW4X = 354
|
580
|
+
INS_MBAR = 355
|
581
|
+
INS_MCRF = 356
|
582
|
+
INS_MFCR = 357
|
583
|
+
INS_MFCTR = 358
|
584
|
+
INS_MFDCR = 359
|
585
|
+
INS_MFFS = 360
|
586
|
+
INS_MFLR = 361
|
587
|
+
INS_MFMSR = 362
|
588
|
+
INS_MFOCRF = 363
|
589
|
+
INS_MFSPR = 364
|
590
|
+
INS_MFSR = 365
|
591
|
+
INS_MFSRIN = 366
|
592
|
+
INS_MFTB = 367
|
593
|
+
INS_MFVSCR = 368
|
594
|
+
INS_MSYNC = 369
|
595
|
+
INS_MTCRF = 370
|
596
|
+
INS_MTCTR = 371
|
597
|
+
INS_MTDCR = 372
|
598
|
+
INS_MTFSB0 = 373
|
599
|
+
INS_MTFSB1 = 374
|
600
|
+
INS_MTFSF = 375
|
601
|
+
INS_MTLR = 376
|
602
|
+
INS_MTMSR = 377
|
603
|
+
INS_MTMSRD = 378
|
604
|
+
INS_MTOCRF = 379
|
605
|
+
INS_MTSPR = 380
|
606
|
+
INS_MTSR = 381
|
607
|
+
INS_MTSRIN = 382
|
608
|
+
INS_MTVSCR = 383
|
609
|
+
INS_MULHD = 384
|
610
|
+
INS_MULHDU = 385
|
611
|
+
INS_MULHW = 386
|
612
|
+
INS_MULHWU = 387
|
613
|
+
INS_MULLD = 388
|
614
|
+
INS_MULLI = 389
|
615
|
+
INS_MULLW = 390
|
616
|
+
INS_NAND = 391
|
617
|
+
INS_NEG = 392
|
618
|
+
INS_NOP = 393
|
619
|
+
INS_ORI = 394
|
620
|
+
INS_NOR = 395
|
621
|
+
INS_OR = 396
|
622
|
+
INS_ORC = 397
|
623
|
+
INS_ORIS = 398
|
624
|
+
INS_POPCNTD = 399
|
625
|
+
INS_POPCNTW = 400
|
626
|
+
INS_RFCI = 401
|
627
|
+
INS_RFDI = 402
|
628
|
+
INS_RFI = 403
|
629
|
+
INS_RFID = 404
|
630
|
+
INS_RFMCI = 405
|
631
|
+
INS_RLDCL = 406
|
632
|
+
INS_RLDCR = 407
|
633
|
+
INS_RLDIC = 408
|
634
|
+
INS_RLDICL = 409
|
635
|
+
INS_RLDICR = 410
|
636
|
+
INS_RLDIMI = 411
|
637
|
+
INS_RLWIMI = 412
|
638
|
+
INS_RLWINM = 413
|
639
|
+
INS_RLWNM = 414
|
640
|
+
INS_SC = 415
|
641
|
+
INS_SLBIA = 416
|
642
|
+
INS_SLBIE = 417
|
643
|
+
INS_SLBMFEE = 418
|
644
|
+
INS_SLBMTE = 419
|
645
|
+
INS_SLD = 420
|
646
|
+
INS_SLW = 421
|
647
|
+
INS_SRAD = 422
|
648
|
+
INS_SRADI = 423
|
649
|
+
INS_SRAW = 424
|
650
|
+
INS_SRAWI = 425
|
651
|
+
INS_SRD = 426
|
652
|
+
INS_SRW = 427
|
653
|
+
INS_STB = 428
|
654
|
+
INS_STBU = 429
|
655
|
+
INS_STBUX = 430
|
656
|
+
INS_STBX = 431
|
657
|
+
INS_STD = 432
|
658
|
+
INS_STDBRX = 433
|
659
|
+
INS_STDCX = 434
|
660
|
+
INS_STDU = 435
|
661
|
+
INS_STDUX = 436
|
662
|
+
INS_STDX = 437
|
663
|
+
INS_STFD = 438
|
664
|
+
INS_STFDU = 439
|
665
|
+
INS_STFDUX = 440
|
666
|
+
INS_STFDX = 441
|
667
|
+
INS_STFIWX = 442
|
668
|
+
INS_STFS = 443
|
669
|
+
INS_STFSU = 444
|
670
|
+
INS_STFSUX = 445
|
671
|
+
INS_STFSX = 446
|
672
|
+
INS_STH = 447
|
673
|
+
INS_STHBRX = 448
|
674
|
+
INS_STHU = 449
|
675
|
+
INS_STHUX = 450
|
676
|
+
INS_STHX = 451
|
677
|
+
INS_STMW = 452
|
678
|
+
INS_STSWI = 453
|
679
|
+
INS_STVEBX = 454
|
680
|
+
INS_STVEHX = 455
|
681
|
+
INS_STVEWX = 456
|
682
|
+
INS_STVX = 457
|
683
|
+
INS_STVXL = 458
|
684
|
+
INS_STW = 459
|
685
|
+
INS_STWBRX = 460
|
686
|
+
INS_STWCX = 461
|
687
|
+
INS_STWU = 462
|
688
|
+
INS_STWUX = 463
|
689
|
+
INS_STWX = 464
|
690
|
+
INS_STXSDX = 465
|
691
|
+
INS_STXVD2X = 466
|
692
|
+
INS_STXVW4X = 467
|
693
|
+
INS_SUBF = 468
|
694
|
+
INS_SUBFC = 469
|
695
|
+
INS_SUBFE = 470
|
696
|
+
INS_SUBFIC = 471
|
697
|
+
INS_SUBFME = 472
|
698
|
+
INS_SUBFZE = 473
|
699
|
+
INS_SYNC = 474
|
700
|
+
INS_TD = 475
|
701
|
+
INS_TDI = 476
|
702
|
+
INS_TLBIA = 477
|
703
|
+
INS_TLBIE = 478
|
704
|
+
INS_TLBIEL = 479
|
705
|
+
INS_TLBIVAX = 480
|
706
|
+
INS_TLBLD = 481
|
707
|
+
INS_TLBLI = 482
|
708
|
+
INS_TLBRE = 483
|
709
|
+
INS_TLBSX = 484
|
710
|
+
INS_TLBSYNC = 485
|
711
|
+
INS_TLBWE = 486
|
712
|
+
INS_TRAP = 487
|
713
|
+
INS_TW = 488
|
714
|
+
INS_TWI = 489
|
715
|
+
INS_VADDCUW = 490
|
716
|
+
INS_VADDFP = 491
|
717
|
+
INS_VADDSBS = 492
|
718
|
+
INS_VADDSHS = 493
|
719
|
+
INS_VADDSWS = 494
|
720
|
+
INS_VADDUBM = 495
|
721
|
+
INS_VADDUBS = 496
|
722
|
+
INS_VADDUHM = 497
|
723
|
+
INS_VADDUHS = 498
|
724
|
+
INS_VADDUWM = 499
|
725
|
+
INS_VADDUWS = 500
|
726
|
+
INS_VAND = 501
|
727
|
+
INS_VANDC = 502
|
728
|
+
INS_VAVGSB = 503
|
729
|
+
INS_VAVGSH = 504
|
730
|
+
INS_VAVGSW = 505
|
731
|
+
INS_VAVGUB = 506
|
732
|
+
INS_VAVGUH = 507
|
733
|
+
INS_VAVGUW = 508
|
734
|
+
INS_VCFSX = 509
|
735
|
+
INS_VCFUX = 510
|
736
|
+
INS_VCMPBFP = 511
|
737
|
+
INS_VCMPEQFP = 512
|
738
|
+
INS_VCMPEQUB = 513
|
739
|
+
INS_VCMPEQUH = 514
|
740
|
+
INS_VCMPEQUW = 515
|
741
|
+
INS_VCMPGEFP = 516
|
742
|
+
INS_VCMPGTFP = 517
|
743
|
+
INS_VCMPGTSB = 518
|
744
|
+
INS_VCMPGTSH = 519
|
745
|
+
INS_VCMPGTSW = 520
|
746
|
+
INS_VCMPGTUB = 521
|
747
|
+
INS_VCMPGTUH = 522
|
748
|
+
INS_VCMPGTUW = 523
|
749
|
+
INS_VCTSXS = 524
|
750
|
+
INS_VCTUXS = 525
|
751
|
+
INS_VEXPTEFP = 526
|
752
|
+
INS_VLOGEFP = 527
|
753
|
+
INS_VMADDFP = 528
|
754
|
+
INS_VMAXFP = 529
|
755
|
+
INS_VMAXSB = 530
|
756
|
+
INS_VMAXSH = 531
|
757
|
+
INS_VMAXSW = 532
|
758
|
+
INS_VMAXUB = 533
|
759
|
+
INS_VMAXUH = 534
|
760
|
+
INS_VMAXUW = 535
|
761
|
+
INS_VMHADDSHS = 536
|
762
|
+
INS_VMHRADDSHS = 537
|
763
|
+
INS_VMINFP = 538
|
764
|
+
INS_VMINSB = 539
|
765
|
+
INS_VMINSH = 540
|
766
|
+
INS_VMINSW = 541
|
767
|
+
INS_VMINUB = 542
|
768
|
+
INS_VMINUH = 543
|
769
|
+
INS_VMINUW = 544
|
770
|
+
INS_VMLADDUHM = 545
|
771
|
+
INS_VMRGHB = 546
|
772
|
+
INS_VMRGHH = 547
|
773
|
+
INS_VMRGHW = 548
|
774
|
+
INS_VMRGLB = 549
|
775
|
+
INS_VMRGLH = 550
|
776
|
+
INS_VMRGLW = 551
|
777
|
+
INS_VMSUMMBM = 552
|
778
|
+
INS_VMSUMSHM = 553
|
779
|
+
INS_VMSUMSHS = 554
|
780
|
+
INS_VMSUMUBM = 555
|
781
|
+
INS_VMSUMUHM = 556
|
782
|
+
INS_VMSUMUHS = 557
|
783
|
+
INS_VMULESB = 558
|
784
|
+
INS_VMULESH = 559
|
785
|
+
INS_VMULEUB = 560
|
786
|
+
INS_VMULEUH = 561
|
787
|
+
INS_VMULOSB = 562
|
788
|
+
INS_VMULOSH = 563
|
789
|
+
INS_VMULOUB = 564
|
790
|
+
INS_VMULOUH = 565
|
791
|
+
INS_VNMSUBFP = 566
|
792
|
+
INS_VNOR = 567
|
793
|
+
INS_VOR = 568
|
794
|
+
INS_VPERM = 569
|
795
|
+
INS_VPKPX = 570
|
796
|
+
INS_VPKSHSS = 571
|
797
|
+
INS_VPKSHUS = 572
|
798
|
+
INS_VPKSWSS = 573
|
799
|
+
INS_VPKSWUS = 574
|
800
|
+
INS_VPKUHUM = 575
|
801
|
+
INS_VPKUHUS = 576
|
802
|
+
INS_VPKUWUM = 577
|
803
|
+
INS_VPKUWUS = 578
|
804
|
+
INS_VREFP = 579
|
805
|
+
INS_VRFIM = 580
|
806
|
+
INS_VRFIN = 581
|
807
|
+
INS_VRFIP = 582
|
808
|
+
INS_VRFIZ = 583
|
809
|
+
INS_VRLB = 584
|
810
|
+
INS_VRLH = 585
|
811
|
+
INS_VRLW = 586
|
812
|
+
INS_VRSQRTEFP = 587
|
813
|
+
INS_VSEL = 588
|
814
|
+
INS_VSL = 589
|
815
|
+
INS_VSLB = 590
|
816
|
+
INS_VSLDOI = 591
|
817
|
+
INS_VSLH = 592
|
818
|
+
INS_VSLO = 593
|
819
|
+
INS_VSLW = 594
|
820
|
+
INS_VSPLTB = 595
|
821
|
+
INS_VSPLTH = 596
|
822
|
+
INS_VSPLTISB = 597
|
823
|
+
INS_VSPLTISH = 598
|
824
|
+
INS_VSPLTISW = 599
|
825
|
+
INS_VSPLTW = 600
|
826
|
+
INS_VSR = 601
|
827
|
+
INS_VSRAB = 602
|
828
|
+
INS_VSRAH = 603
|
829
|
+
INS_VSRAW = 604
|
830
|
+
INS_VSRB = 605
|
831
|
+
INS_VSRH = 606
|
832
|
+
INS_VSRO = 607
|
833
|
+
INS_VSRW = 608
|
834
|
+
INS_VSUBCUW = 609
|
835
|
+
INS_VSUBFP = 610
|
836
|
+
INS_VSUBSBS = 611
|
837
|
+
INS_VSUBSHS = 612
|
838
|
+
INS_VSUBSWS = 613
|
839
|
+
INS_VSUBUBM = 614
|
840
|
+
INS_VSUBUBS = 615
|
841
|
+
INS_VSUBUHM = 616
|
842
|
+
INS_VSUBUHS = 617
|
843
|
+
INS_VSUBUWM = 618
|
844
|
+
INS_VSUBUWS = 619
|
845
|
+
INS_VSUM2SWS = 620
|
846
|
+
INS_VSUM4SBS = 621
|
847
|
+
INS_VSUM4SHS = 622
|
848
|
+
INS_VSUM4UBS = 623
|
849
|
+
INS_VSUMSWS = 624
|
850
|
+
INS_VUPKHPX = 625
|
851
|
+
INS_VUPKHSB = 626
|
852
|
+
INS_VUPKHSH = 627
|
853
|
+
INS_VUPKLPX = 628
|
854
|
+
INS_VUPKLSB = 629
|
855
|
+
INS_VUPKLSH = 630
|
856
|
+
INS_VXOR = 631
|
857
|
+
INS_WAIT = 632
|
858
|
+
INS_WRTEE = 633
|
859
|
+
INS_WRTEEI = 634
|
860
|
+
INS_XOR = 635
|
861
|
+
INS_XORI = 636
|
862
|
+
INS_XORIS = 637
|
863
|
+
INS_XSABSDP = 638
|
864
|
+
INS_XSADDDP = 639
|
865
|
+
INS_XSCMPODP = 640
|
866
|
+
INS_XSCMPUDP = 641
|
867
|
+
INS_XSCPSGNDP = 642
|
868
|
+
INS_XSCVDPSP = 643
|
869
|
+
INS_XSCVDPSXDS = 644
|
870
|
+
INS_XSCVDPSXWS = 645
|
871
|
+
INS_XSCVDPUXDS = 646
|
872
|
+
INS_XSCVDPUXWS = 647
|
873
|
+
INS_XSCVSPDP = 648
|
874
|
+
INS_XSCVSXDDP = 649
|
875
|
+
INS_XSCVUXDDP = 650
|
876
|
+
INS_XSDIVDP = 651
|
877
|
+
INS_XSMADDADP = 652
|
878
|
+
INS_XSMADDMDP = 653
|
879
|
+
INS_XSMAXDP = 654
|
880
|
+
INS_XSMINDP = 655
|
881
|
+
INS_XSMSUBADP = 656
|
882
|
+
INS_XSMSUBMDP = 657
|
883
|
+
INS_XSMULDP = 658
|
884
|
+
INS_XSNABSDP = 659
|
885
|
+
INS_XSNEGDP = 660
|
886
|
+
INS_XSNMADDADP = 661
|
887
|
+
INS_XSNMADDMDP = 662
|
888
|
+
INS_XSNMSUBADP = 663
|
889
|
+
INS_XSNMSUBMDP = 664
|
890
|
+
INS_XSRDPI = 665
|
891
|
+
INS_XSRDPIC = 666
|
892
|
+
INS_XSRDPIM = 667
|
893
|
+
INS_XSRDPIP = 668
|
894
|
+
INS_XSRDPIZ = 669
|
895
|
+
INS_XSREDP = 670
|
896
|
+
INS_XSRSQRTEDP = 671
|
897
|
+
INS_XSSQRTDP = 672
|
898
|
+
INS_XSSUBDP = 673
|
899
|
+
INS_XSTDIVDP = 674
|
900
|
+
INS_XSTSQRTDP = 675
|
901
|
+
INS_XVABSDP = 676
|
902
|
+
INS_XVABSSP = 677
|
903
|
+
INS_XVADDDP = 678
|
904
|
+
INS_XVADDSP = 679
|
905
|
+
INS_XVCMPEQDP = 680
|
906
|
+
INS_XVCMPEQSP = 681
|
907
|
+
INS_XVCMPGEDP = 682
|
908
|
+
INS_XVCMPGESP = 683
|
909
|
+
INS_XVCMPGTDP = 684
|
910
|
+
INS_XVCMPGTSP = 685
|
911
|
+
INS_XVCPSGNDP = 686
|
912
|
+
INS_XVCPSGNSP = 687
|
913
|
+
INS_XVCVDPSP = 688
|
914
|
+
INS_XVCVDPSXDS = 689
|
915
|
+
INS_XVCVDPSXWS = 690
|
916
|
+
INS_XVCVDPUXDS = 691
|
917
|
+
INS_XVCVDPUXWS = 692
|
918
|
+
INS_XVCVSPDP = 693
|
919
|
+
INS_XVCVSPSXDS = 694
|
920
|
+
INS_XVCVSPSXWS = 695
|
921
|
+
INS_XVCVSPUXDS = 696
|
922
|
+
INS_XVCVSPUXWS = 697
|
923
|
+
INS_XVCVSXDDP = 698
|
924
|
+
INS_XVCVSXDSP = 699
|
925
|
+
INS_XVCVSXWDP = 700
|
926
|
+
INS_XVCVSXWSP = 701
|
927
|
+
INS_XVCVUXDDP = 702
|
928
|
+
INS_XVCVUXDSP = 703
|
929
|
+
INS_XVCVUXWDP = 704
|
930
|
+
INS_XVCVUXWSP = 705
|
931
|
+
INS_XVDIVDP = 706
|
932
|
+
INS_XVDIVSP = 707
|
933
|
+
INS_XVMADDADP = 708
|
934
|
+
INS_XVMADDASP = 709
|
935
|
+
INS_XVMADDMDP = 710
|
936
|
+
INS_XVMADDMSP = 711
|
937
|
+
INS_XVMAXDP = 712
|
938
|
+
INS_XVMAXSP = 713
|
939
|
+
INS_XVMINDP = 714
|
940
|
+
INS_XVMINSP = 715
|
941
|
+
INS_XVMSUBADP = 716
|
942
|
+
INS_XVMSUBASP = 717
|
943
|
+
INS_XVMSUBMDP = 718
|
944
|
+
INS_XVMSUBMSP = 719
|
945
|
+
INS_XVMULDP = 720
|
946
|
+
INS_XVMULSP = 721
|
947
|
+
INS_XVNABSDP = 722
|
948
|
+
INS_XVNABSSP = 723
|
949
|
+
INS_XVNEGDP = 724
|
950
|
+
INS_XVNEGSP = 725
|
951
|
+
INS_XVNMADDADP = 726
|
952
|
+
INS_XVNMADDASP = 727
|
953
|
+
INS_XVNMADDMDP = 728
|
954
|
+
INS_XVNMADDMSP = 729
|
955
|
+
INS_XVNMSUBADP = 730
|
956
|
+
INS_XVNMSUBASP = 731
|
957
|
+
INS_XVNMSUBMDP = 732
|
958
|
+
INS_XVNMSUBMSP = 733
|
959
|
+
INS_XVRDPI = 734
|
960
|
+
INS_XVRDPIC = 735
|
961
|
+
INS_XVRDPIM = 736
|
962
|
+
INS_XVRDPIP = 737
|
963
|
+
INS_XVRDPIZ = 738
|
964
|
+
INS_XVREDP = 739
|
965
|
+
INS_XVRESP = 740
|
966
|
+
INS_XVRSPI = 741
|
967
|
+
INS_XVRSPIC = 742
|
968
|
+
INS_XVRSPIM = 743
|
969
|
+
INS_XVRSPIP = 744
|
970
|
+
INS_XVRSPIZ = 745
|
971
|
+
INS_XVRSQRTEDP = 746
|
972
|
+
INS_XVRSQRTESP = 747
|
973
|
+
INS_XVSQRTDP = 748
|
974
|
+
INS_XVSQRTSP = 749
|
975
|
+
INS_XVSUBDP = 750
|
976
|
+
INS_XVSUBSP = 751
|
977
|
+
INS_XVTDIVDP = 752
|
978
|
+
INS_XVTDIVSP = 753
|
979
|
+
INS_XVTSQRTDP = 754
|
980
|
+
INS_XVTSQRTSP = 755
|
981
|
+
INS_XXLAND = 756
|
982
|
+
INS_XXLANDC = 757
|
983
|
+
INS_XXLNOR = 758
|
984
|
+
INS_XXLOR = 759
|
985
|
+
INS_XXLXOR = 760
|
986
|
+
INS_XXMRGHW = 761
|
987
|
+
INS_XXMRGLW = 762
|
988
|
+
INS_XXPERMDI = 763
|
989
|
+
INS_XXSEL = 764
|
990
|
+
INS_XXSLDWI = 765
|
991
|
+
INS_XXSPLTW = 766
|
992
|
+
INS_BCA = 767
|
993
|
+
INS_BCLA = 768
|
994
|
+
INS_SLWI = 769
|
995
|
+
INS_SRWI = 770
|
996
|
+
INS_SLDI = 771
|
997
|
+
INS_BTA = 772
|
998
|
+
INS_CRSET = 773
|
999
|
+
INS_CRNOT = 774
|
1000
|
+
INS_CRMOVE = 775
|
1001
|
+
INS_CRCLR = 776
|
1002
|
+
INS_MFBR0 = 777
|
1003
|
+
INS_MFBR1 = 778
|
1004
|
+
INS_MFBR2 = 779
|
1005
|
+
INS_MFBR3 = 780
|
1006
|
+
INS_MFBR4 = 781
|
1007
|
+
INS_MFBR5 = 782
|
1008
|
+
INS_MFBR6 = 783
|
1009
|
+
INS_MFBR7 = 784
|
1010
|
+
INS_MFXER = 785
|
1011
|
+
INS_MFRTCU = 786
|
1012
|
+
INS_MFRTCL = 787
|
1013
|
+
INS_MFDSCR = 788
|
1014
|
+
INS_MFDSISR = 789
|
1015
|
+
INS_MFDAR = 790
|
1016
|
+
INS_MFSRR2 = 791
|
1017
|
+
INS_MFSRR3 = 792
|
1018
|
+
INS_MFCFAR = 793
|
1019
|
+
INS_MFAMR = 794
|
1020
|
+
INS_MFPID = 795
|
1021
|
+
INS_MFTBLO = 796
|
1022
|
+
INS_MFTBHI = 797
|
1023
|
+
INS_MFDBATU = 798
|
1024
|
+
INS_MFDBATL = 799
|
1025
|
+
INS_MFIBATU = 800
|
1026
|
+
INS_MFIBATL = 801
|
1027
|
+
INS_MFDCCR = 802
|
1028
|
+
INS_MFICCR = 803
|
1029
|
+
INS_MFDEAR = 804
|
1030
|
+
INS_MFESR = 805
|
1031
|
+
INS_MFSPEFSCR = 806
|
1032
|
+
INS_MFTCR = 807
|
1033
|
+
INS_MFASR = 808
|
1034
|
+
INS_MFPVR = 809
|
1035
|
+
INS_MFTBU = 810
|
1036
|
+
INS_MTCR = 811
|
1037
|
+
INS_MTBR0 = 812
|
1038
|
+
INS_MTBR1 = 813
|
1039
|
+
INS_MTBR2 = 814
|
1040
|
+
INS_MTBR3 = 815
|
1041
|
+
INS_MTBR4 = 816
|
1042
|
+
INS_MTBR5 = 817
|
1043
|
+
INS_MTBR6 = 818
|
1044
|
+
INS_MTBR7 = 819
|
1045
|
+
INS_MTXER = 820
|
1046
|
+
INS_MTDSCR = 821
|
1047
|
+
INS_MTDSISR = 822
|
1048
|
+
INS_MTDAR = 823
|
1049
|
+
INS_MTSRR2 = 824
|
1050
|
+
INS_MTSRR3 = 825
|
1051
|
+
INS_MTCFAR = 826
|
1052
|
+
INS_MTAMR = 827
|
1053
|
+
INS_MTPID = 828
|
1054
|
+
INS_MTTBL = 829
|
1055
|
+
INS_MTTBU = 830
|
1056
|
+
INS_MTTBLO = 831
|
1057
|
+
INS_MTTBHI = 832
|
1058
|
+
INS_MTDBATU = 833
|
1059
|
+
INS_MTDBATL = 834
|
1060
|
+
INS_MTIBATU = 835
|
1061
|
+
INS_MTIBATL = 836
|
1062
|
+
INS_MTDCCR = 837
|
1063
|
+
INS_MTICCR = 838
|
1064
|
+
INS_MTDEAR = 839
|
1065
|
+
INS_MTESR = 840
|
1066
|
+
INS_MTSPEFSCR = 841
|
1067
|
+
INS_MTTCR = 842
|
1068
|
+
INS_NOT = 843
|
1069
|
+
INS_MR = 844
|
1070
|
+
INS_ROTLD = 845
|
1071
|
+
INS_ROTLDI = 846
|
1072
|
+
INS_CLRLDI = 847
|
1073
|
+
INS_ROTLWI = 848
|
1074
|
+
INS_CLRLWI = 849
|
1075
|
+
INS_ROTLW = 850
|
1076
|
+
INS_SUB = 851
|
1077
|
+
INS_SUBC = 852
|
1078
|
+
INS_LWSYNC = 853
|
1079
|
+
INS_PTESYNC = 854
|
1080
|
+
INS_TDLT = 855
|
1081
|
+
INS_TDEQ = 856
|
1082
|
+
INS_TDGT = 857
|
1083
|
+
INS_TDNE = 858
|
1084
|
+
INS_TDLLT = 859
|
1085
|
+
INS_TDLGT = 860
|
1086
|
+
INS_TDU = 861
|
1087
|
+
INS_TDLTI = 862
|
1088
|
+
INS_TDEQI = 863
|
1089
|
+
INS_TDGTI = 864
|
1090
|
+
INS_TDNEI = 865
|
1091
|
+
INS_TDLLTI = 866
|
1092
|
+
INS_TDLGTI = 867
|
1093
|
+
INS_TDUI = 868
|
1094
|
+
INS_TLBREHI = 869
|
1095
|
+
INS_TLBRELO = 870
|
1096
|
+
INS_TLBWEHI = 871
|
1097
|
+
INS_TLBWELO = 872
|
1098
|
+
INS_TWLT = 873
|
1099
|
+
INS_TWEQ = 874
|
1100
|
+
INS_TWGT = 875
|
1101
|
+
INS_TWNE = 876
|
1102
|
+
INS_TWLLT = 877
|
1103
|
+
INS_TWLGT = 878
|
1104
|
+
INS_TWU = 879
|
1105
|
+
INS_TWLTI = 880
|
1106
|
+
INS_TWEQI = 881
|
1107
|
+
INS_TWGTI = 882
|
1108
|
+
INS_TWNEI = 883
|
1109
|
+
INS_TWLLTI = 884
|
1110
|
+
INS_TWLGTI = 885
|
1111
|
+
INS_TWUI = 886
|
1112
|
+
INS_WAITRSV = 887
|
1113
|
+
INS_WAITIMPL = 888
|
1114
|
+
INS_XNOP = 889
|
1115
|
+
INS_XVMOVDP = 890
|
1116
|
+
INS_XVMOVSP = 891
|
1117
|
+
INS_XXSPLTD = 892
|
1118
|
+
INS_XXMRGHD = 893
|
1119
|
+
INS_XXMRGLD = 894
|
1120
|
+
INS_XXSWAPD = 895
|
1121
|
+
INS_BT = 896
|
1122
|
+
INS_BF = 897
|
1123
|
+
INS_BDNZT = 898
|
1124
|
+
INS_BDNZF = 899
|
1125
|
+
INS_BDZF = 900
|
1126
|
+
INS_BDZT = 901
|
1127
|
+
INS_BFA = 902
|
1128
|
+
INS_BDNZTA = 903
|
1129
|
+
INS_BDNZFA = 904
|
1130
|
+
INS_BDZTA = 905
|
1131
|
+
INS_BDZFA = 906
|
1132
|
+
INS_BTCTR = 907
|
1133
|
+
INS_BFCTR = 908
|
1134
|
+
INS_BTCTRL = 909
|
1135
|
+
INS_BFCTRL = 910
|
1136
|
+
INS_BTL = 911
|
1137
|
+
INS_BFL = 912
|
1138
|
+
INS_BDNZTL = 913
|
1139
|
+
INS_BDNZFL = 914
|
1140
|
+
INS_BDZTL = 915
|
1141
|
+
INS_BDZFL = 916
|
1142
|
+
INS_BTLA = 917
|
1143
|
+
INS_BFLA = 918
|
1144
|
+
INS_BDNZTLA = 919
|
1145
|
+
INS_BDNZFLA = 920
|
1146
|
+
INS_BDZTLA = 921
|
1147
|
+
INS_BDZFLA = 922
|
1148
|
+
INS_BTLR = 923
|
1149
|
+
INS_BFLR = 924
|
1150
|
+
INS_BDNZTLR = 925
|
1151
|
+
INS_BDZTLR = 926
|
1152
|
+
INS_BDZFLR = 927
|
1153
|
+
INS_BTLRL = 928
|
1154
|
+
INS_BFLRL = 929
|
1155
|
+
INS_BDNZTLRL = 930
|
1156
|
+
INS_BDNZFLRL = 931
|
1157
|
+
INS_BDZTLRL = 932
|
1158
|
+
INS_BDZFLRL = 933
|
1159
|
+
INS_ENDING = 934
|
1160
|
+
|
1161
|
+
# Group of PPC instructions
|
1162
|
+
|
1163
|
+
GRP_INVALID = 0
|
1164
|
+
|
1165
|
+
# Generic groups
|
1166
|
+
GRP_JUMP = 1
|
1167
|
+
|
1168
|
+
# Architecture-specific groups
|
1169
|
+
GRP_ALTIVEC = 128
|
1170
|
+
GRP_MODE32 = 129
|
1171
|
+
GRP_MODE64 = 130
|
1172
|
+
GRP_BOOKE = 131
|
1173
|
+
GRP_NOTBOOKE = 132
|
1174
|
+
GRP_SPE = 133
|
1175
|
+
GRP_VSX = 134
|
1176
|
+
GRP_E500 = 135
|
1177
|
+
GRP_PPC4XX = 136
|
1178
|
+
GRP_PPC6XX = 137
|
1179
|
+
GRP_ENDING = 138
|
1180
|
+
end
|
1181
|
+
end
|