crabstone 3.0.3

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Files changed (302) hide show
  1. checksums.yaml +7 -0
  2. data/CHANGES.md +61 -0
  3. data/LICENSE +25 -0
  4. data/MANIFEST +312 -0
  5. data/README.md +103 -0
  6. data/Rakefile +27 -0
  7. data/bin/genconst +66 -0
  8. data/bin/genreg +99 -0
  9. data/crabstone.gemspec +27 -0
  10. data/examples/hello_world.rb +43 -0
  11. data/lib/arch/arm.rb +128 -0
  12. data/lib/arch/arm64.rb +167 -0
  13. data/lib/arch/arm64_const.rb +1055 -0
  14. data/lib/arch/arm64_registers.rb +295 -0
  15. data/lib/arch/arm_const.rb +777 -0
  16. data/lib/arch/arm_registers.rb +149 -0
  17. data/lib/arch/mips.rb +78 -0
  18. data/lib/arch/mips_const.rb +850 -0
  19. data/lib/arch/mips_registers.rb +208 -0
  20. data/lib/arch/ppc.rb +90 -0
  21. data/lib/arch/ppc_const.rb +1181 -0
  22. data/lib/arch/ppc_registers.rb +209 -0
  23. data/lib/arch/sparc.rb +79 -0
  24. data/lib/arch/sparc_const.rb +461 -0
  25. data/lib/arch/sparc_registers.rb +121 -0
  26. data/lib/arch/systemz.rb +79 -0
  27. data/lib/arch/sysz_const.rb +779 -0
  28. data/lib/arch/sysz_registers.rb +66 -0
  29. data/lib/arch/x86.rb +107 -0
  30. data/lib/arch/x86_const.rb +1698 -0
  31. data/lib/arch/x86_registers.rb +265 -0
  32. data/lib/arch/xcore.rb +78 -0
  33. data/lib/arch/xcore_const.rb +185 -0
  34. data/lib/arch/xcore_registers.rb +57 -0
  35. data/lib/crabstone.rb +564 -0
  36. data/test/MC/AArch64/basic-a64-instructions.s.cs +2014 -0
  37. data/test/MC/AArch64/gicv3-regs.s.cs +111 -0
  38. data/test/MC/AArch64/neon-2velem.s.cs +113 -0
  39. data/test/MC/AArch64/neon-3vdiff.s.cs +143 -0
  40. data/test/MC/AArch64/neon-aba-abd.s.cs +28 -0
  41. data/test/MC/AArch64/neon-across.s.cs +40 -0
  42. data/test/MC/AArch64/neon-add-pairwise.s.cs +11 -0
  43. data/test/MC/AArch64/neon-add-sub-instructions.s.cs +21 -0
  44. data/test/MC/AArch64/neon-bitwise-instructions.s.cs +17 -0
  45. data/test/MC/AArch64/neon-compare-instructions.s.cs +136 -0
  46. data/test/MC/AArch64/neon-crypto.s.cs +15 -0
  47. data/test/MC/AArch64/neon-extract.s.cs +3 -0
  48. data/test/MC/AArch64/neon-facge-facgt.s.cs +13 -0
  49. data/test/MC/AArch64/neon-frsqrt-frecp.s.cs +7 -0
  50. data/test/MC/AArch64/neon-halving-add-sub.s.cs +25 -0
  51. data/test/MC/AArch64/neon-max-min-pairwise.s.cs +37 -0
  52. data/test/MC/AArch64/neon-max-min.s.cs +37 -0
  53. data/test/MC/AArch64/neon-mla-mls-instructions.s.cs +19 -0
  54. data/test/MC/AArch64/neon-mov.s.cs +74 -0
  55. data/test/MC/AArch64/neon-mul-div-instructions.s.cs +24 -0
  56. data/test/MC/AArch64/neon-perm.s.cs +43 -0
  57. data/test/MC/AArch64/neon-rounding-halving-add.s.cs +13 -0
  58. data/test/MC/AArch64/neon-rounding-shift.s.cs +15 -0
  59. data/test/MC/AArch64/neon-saturating-add-sub.s.cs +29 -0
  60. data/test/MC/AArch64/neon-saturating-rounding-shift.s.cs +15 -0
  61. data/test/MC/AArch64/neon-saturating-shift.s.cs +15 -0
  62. data/test/MC/AArch64/neon-scalar-abs.s.cs +8 -0
  63. data/test/MC/AArch64/neon-scalar-add-sub.s.cs +3 -0
  64. data/test/MC/AArch64/neon-scalar-by-elem-mla.s.cs +13 -0
  65. data/test/MC/AArch64/neon-scalar-by-elem-mul.s.cs +13 -0
  66. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.cs +15 -0
  67. data/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.cs +18 -0
  68. data/test/MC/AArch64/neon-scalar-compare.s.cs +12 -0
  69. data/test/MC/AArch64/neon-scalar-cvt.s.cs +34 -0
  70. data/test/MC/AArch64/neon-scalar-dup.s.cs +23 -0
  71. data/test/MC/AArch64/neon-scalar-extract-narrow.s.cs +10 -0
  72. data/test/MC/AArch64/neon-scalar-fp-compare.s.cs +21 -0
  73. data/test/MC/AArch64/neon-scalar-mul.s.cs +13 -0
  74. data/test/MC/AArch64/neon-scalar-neg.s.cs +6 -0
  75. data/test/MC/AArch64/neon-scalar-recip.s.cs +11 -0
  76. data/test/MC/AArch64/neon-scalar-reduce-pairwise.s.cs +3 -0
  77. data/test/MC/AArch64/neon-scalar-rounding-shift.s.cs +3 -0
  78. data/test/MC/AArch64/neon-scalar-saturating-add-sub.s.cs +25 -0
  79. data/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s.cs +9 -0
  80. data/test/MC/AArch64/neon-scalar-saturating-shift.s.cs +9 -0
  81. data/test/MC/AArch64/neon-scalar-shift-imm.s.cs +42 -0
  82. data/test/MC/AArch64/neon-scalar-shift.s.cs +3 -0
  83. data/test/MC/AArch64/neon-shift-left-long.s.cs +13 -0
  84. data/test/MC/AArch64/neon-shift.s.cs +22 -0
  85. data/test/MC/AArch64/neon-simd-copy.s.cs +42 -0
  86. data/test/MC/AArch64/neon-simd-ldst-multi-elem.s.cs +197 -0
  87. data/test/MC/AArch64/neon-simd-ldst-one-elem.s.cs +129 -0
  88. data/test/MC/AArch64/neon-simd-misc.s.cs +213 -0
  89. data/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s.cs +107 -0
  90. data/test/MC/AArch64/neon-simd-shift.s.cs +151 -0
  91. data/test/MC/AArch64/neon-tbl.s.cs +21 -0
  92. data/test/MC/AArch64/trace-regs.s.cs +383 -0
  93. data/test/MC/ARM/arm-aliases.s.cs +7 -0
  94. data/test/MC/ARM/arm-arithmetic-aliases.s.cs +50 -0
  95. data/test/MC/ARM/arm-it-block.s.cs +2 -0
  96. data/test/MC/ARM/arm-memory-instructions.s.cs +138 -0
  97. data/test/MC/ARM/arm-shift-encoding.s.cs +50 -0
  98. data/test/MC/ARM/arm-thumb-trustzone.s.cs +3 -0
  99. data/test/MC/ARM/arm-trustzone.s.cs +3 -0
  100. data/test/MC/ARM/arm_addrmode2.s.cs +15 -0
  101. data/test/MC/ARM/arm_addrmode3.s.cs +9 -0
  102. data/test/MC/ARM/arm_instructions.s.cs +25 -0
  103. data/test/MC/ARM/basic-arm-instructions-v8.s.cs +10 -0
  104. data/test/MC/ARM/basic-arm-instructions.s.cs +997 -0
  105. data/test/MC/ARM/basic-thumb-instructions.s.cs +130 -0
  106. data/test/MC/ARM/basic-thumb2-instructions-v8.s.cs +1 -0
  107. data/test/MC/ARM/basic-thumb2-instructions.s.cs +1242 -0
  108. data/test/MC/ARM/crc32-thumb.s.cs +7 -0
  109. data/test/MC/ARM/crc32.s.cs +7 -0
  110. data/test/MC/ARM/dot-req.s.cs +3 -0
  111. data/test/MC/ARM/fp-armv8.s.cs +52 -0
  112. data/test/MC/ARM/idiv-thumb.s.cs +3 -0
  113. data/test/MC/ARM/idiv.s.cs +3 -0
  114. data/test/MC/ARM/load-store-acquire-release-v8-thumb.s.cs +15 -0
  115. data/test/MC/ARM/load-store-acquire-release-v8.s.cs +15 -0
  116. data/test/MC/ARM/mode-switch.s.cs +7 -0
  117. data/test/MC/ARM/neon-abs-encoding.s.cs +15 -0
  118. data/test/MC/ARM/neon-absdiff-encoding.s.cs +39 -0
  119. data/test/MC/ARM/neon-add-encoding.s.cs +119 -0
  120. data/test/MC/ARM/neon-bitcount-encoding.s.cs +15 -0
  121. data/test/MC/ARM/neon-bitwise-encoding.s.cs +126 -0
  122. data/test/MC/ARM/neon-cmp-encoding.s.cs +88 -0
  123. data/test/MC/ARM/neon-convert-encoding.s.cs +27 -0
  124. data/test/MC/ARM/neon-crypto.s.cs +16 -0
  125. data/test/MC/ARM/neon-dup-encoding.s.cs +13 -0
  126. data/test/MC/ARM/neon-minmax-encoding.s.cs +57 -0
  127. data/test/MC/ARM/neon-mov-encoding.s.cs +76 -0
  128. data/test/MC/ARM/neon-mul-accum-encoding.s.cs +39 -0
  129. data/test/MC/ARM/neon-mul-encoding.s.cs +72 -0
  130. data/test/MC/ARM/neon-neg-encoding.s.cs +15 -0
  131. data/test/MC/ARM/neon-pairwise-encoding.s.cs +47 -0
  132. data/test/MC/ARM/neon-reciprocal-encoding.s.cs +13 -0
  133. data/test/MC/ARM/neon-reverse-encoding.s.cs +13 -0
  134. data/test/MC/ARM/neon-satshift-encoding.s.cs +75 -0
  135. data/test/MC/ARM/neon-shift-encoding.s.cs +238 -0
  136. data/test/MC/ARM/neon-shiftaccum-encoding.s.cs +97 -0
  137. data/test/MC/ARM/neon-shuffle-encoding.s.cs +59 -0
  138. data/test/MC/ARM/neon-sub-encoding.s.cs +82 -0
  139. data/test/MC/ARM/neon-table-encoding.s.cs +9 -0
  140. data/test/MC/ARM/neon-v8.s.cs +38 -0
  141. data/test/MC/ARM/neon-vld-encoding.s.cs +213 -0
  142. data/test/MC/ARM/neon-vst-encoding.s.cs +120 -0
  143. data/test/MC/ARM/neon-vswp.s.cs +3 -0
  144. data/test/MC/ARM/neont2-abs-encoding.s.cs +15 -0
  145. data/test/MC/ARM/neont2-absdiff-encoding.s.cs +39 -0
  146. data/test/MC/ARM/neont2-add-encoding.s.cs +65 -0
  147. data/test/MC/ARM/neont2-bitcount-encoding.s.cs +15 -0
  148. data/test/MC/ARM/neont2-bitwise-encoding.s.cs +15 -0
  149. data/test/MC/ARM/neont2-cmp-encoding.s.cs +17 -0
  150. data/test/MC/ARM/neont2-convert-encoding.s.cs +19 -0
  151. data/test/MC/ARM/neont2-dup-encoding.s.cs +19 -0
  152. data/test/MC/ARM/neont2-minmax-encoding.s.cs +57 -0
  153. data/test/MC/ARM/neont2-mov-encoding.s.cs +58 -0
  154. data/test/MC/ARM/neont2-mul-accum-encoding.s.cs +41 -0
  155. data/test/MC/ARM/neont2-mul-encoding.s.cs +31 -0
  156. data/test/MC/ARM/neont2-neg-encoding.s.cs +15 -0
  157. data/test/MC/ARM/neont2-pairwise-encoding.s.cs +43 -0
  158. data/test/MC/ARM/neont2-reciprocal-encoding.s.cs +13 -0
  159. data/test/MC/ARM/neont2-reverse-encoding.s.cs +13 -0
  160. data/test/MC/ARM/neont2-satshift-encoding.s.cs +75 -0
  161. data/test/MC/ARM/neont2-shift-encoding.s.cs +80 -0
  162. data/test/MC/ARM/neont2-shiftaccum-encoding.s.cs +97 -0
  163. data/test/MC/ARM/neont2-shuffle-encoding.s.cs +23 -0
  164. data/test/MC/ARM/neont2-sub-encoding.s.cs +23 -0
  165. data/test/MC/ARM/neont2-table-encoding.s.cs +9 -0
  166. data/test/MC/ARM/neont2-vld-encoding.s.cs +51 -0
  167. data/test/MC/ARM/neont2-vst-encoding.s.cs +48 -0
  168. data/test/MC/ARM/simple-fp-encoding.s.cs +157 -0
  169. data/test/MC/ARM/thumb-fp-armv8.s.cs +51 -0
  170. data/test/MC/ARM/thumb-hints.s.cs +12 -0
  171. data/test/MC/ARM/thumb-neon-crypto.s.cs +16 -0
  172. data/test/MC/ARM/thumb-neon-v8.s.cs +38 -0
  173. data/test/MC/ARM/thumb-shift-encoding.s.cs +19 -0
  174. data/test/MC/ARM/thumb.s.cs +19 -0
  175. data/test/MC/ARM/thumb2-b.w-encodingT4.s.cs +2 -0
  176. data/test/MC/ARM/thumb2-branches.s.cs +85 -0
  177. data/test/MC/ARM/thumb2-mclass.s.cs +41 -0
  178. data/test/MC/ARM/thumb2-narrow-dp.ll.cs +379 -0
  179. data/test/MC/ARM/thumb2-pldw.s.cs +2 -0
  180. data/test/MC/ARM/vfp4-thumb.s.cs +13 -0
  181. data/test/MC/ARM/vfp4.s.cs +13 -0
  182. data/test/MC/ARM/vpush-vpop-thumb.s.cs +9 -0
  183. data/test/MC/ARM/vpush-vpop.s.cs +9 -0
  184. data/test/MC/Mips/hilo-addressing.s.cs +4 -0
  185. data/test/MC/Mips/micromips-alu-instructions-EB.s.cs +33 -0
  186. data/test/MC/Mips/micromips-alu-instructions.s.cs +33 -0
  187. data/test/MC/Mips/micromips-branch-instructions-EB.s.cs +11 -0
  188. data/test/MC/Mips/micromips-branch-instructions.s.cs +11 -0
  189. data/test/MC/Mips/micromips-expansions.s.cs +20 -0
  190. data/test/MC/Mips/micromips-jump-instructions-EB.s.cs +5 -0
  191. data/test/MC/Mips/micromips-jump-instructions.s.cs +6 -0
  192. data/test/MC/Mips/micromips-loadstore-instructions-EB.s.cs +9 -0
  193. data/test/MC/Mips/micromips-loadstore-instructions.s.cs +9 -0
  194. data/test/MC/Mips/micromips-loadstore-unaligned-EB.s.cs +5 -0
  195. data/test/MC/Mips/micromips-loadstore-unaligned.s.cs +5 -0
  196. data/test/MC/Mips/micromips-movcond-instructions-EB.s.cs +5 -0
  197. data/test/MC/Mips/micromips-movcond-instructions.s.cs +5 -0
  198. data/test/MC/Mips/micromips-multiply-instructions-EB.s.cs +5 -0
  199. data/test/MC/Mips/micromips-multiply-instructions.s.cs +5 -0
  200. data/test/MC/Mips/micromips-shift-instructions-EB.s.cs +9 -0
  201. data/test/MC/Mips/micromips-shift-instructions.s.cs +9 -0
  202. data/test/MC/Mips/micromips-trap-instructions-EB.s.cs +13 -0
  203. data/test/MC/Mips/micromips-trap-instructions.s.cs +13 -0
  204. data/test/MC/Mips/mips-alu-instructions.s.cs +53 -0
  205. data/test/MC/Mips/mips-control-instructions-64.s.cs +33 -0
  206. data/test/MC/Mips/mips-control-instructions.s.cs +33 -0
  207. data/test/MC/Mips/mips-coprocessor-encodings.s.cs +17 -0
  208. data/test/MC/Mips/mips-dsp-instructions.s.cs +43 -0
  209. data/test/MC/Mips/mips-expansions.s.cs +20 -0
  210. data/test/MC/Mips/mips-fpu-instructions.s.cs +93 -0
  211. data/test/MC/Mips/mips-jump-instructions.s.cs +1 -0
  212. data/test/MC/Mips/mips-memory-instructions.s.cs +17 -0
  213. data/test/MC/Mips/mips-register-names.s.cs +33 -0
  214. data/test/MC/Mips/mips64-alu-instructions.s.cs +47 -0
  215. data/test/MC/Mips/mips64-instructions.s.cs +3 -0
  216. data/test/MC/Mips/mips64-register-names.s.cs +33 -0
  217. data/test/MC/Mips/mips_directives.s.cs +12 -0
  218. data/test/MC/Mips/nabi-regs.s.cs +12 -0
  219. data/test/MC/Mips/set-at-directive.s.cs +6 -0
  220. data/test/MC/Mips/test_2r.s.cs +16 -0
  221. data/test/MC/Mips/test_2rf.s.cs +33 -0
  222. data/test/MC/Mips/test_3r.s.cs +243 -0
  223. data/test/MC/Mips/test_3rf.s.cs +83 -0
  224. data/test/MC/Mips/test_bit.s.cs +49 -0
  225. data/test/MC/Mips/test_cbranch.s.cs +11 -0
  226. data/test/MC/Mips/test_ctrlregs.s.cs +33 -0
  227. data/test/MC/Mips/test_elm.s.cs +16 -0
  228. data/test/MC/Mips/test_elm_insert.s.cs +4 -0
  229. data/test/MC/Mips/test_elm_insve.s.cs +5 -0
  230. data/test/MC/Mips/test_i10.s.cs +5 -0
  231. data/test/MC/Mips/test_i5.s.cs +45 -0
  232. data/test/MC/Mips/test_i8.s.cs +11 -0
  233. data/test/MC/Mips/test_lsa.s.cs +5 -0
  234. data/test/MC/Mips/test_mi10.s.cs +24 -0
  235. data/test/MC/Mips/test_vec.s.cs +8 -0
  236. data/test/MC/PowerPC/ppc64-encoding-bookII.s.cs +25 -0
  237. data/test/MC/PowerPC/ppc64-encoding-bookIII.s.cs +35 -0
  238. data/test/MC/PowerPC/ppc64-encoding-ext.s.cs +535 -0
  239. data/test/MC/PowerPC/ppc64-encoding-fp.s.cs +110 -0
  240. data/test/MC/PowerPC/ppc64-encoding-vmx.s.cs +170 -0
  241. data/test/MC/PowerPC/ppc64-encoding.s.cs +202 -0
  242. data/test/MC/PowerPC/ppc64-operands.s.cs +32 -0
  243. data/test/MC/README +6 -0
  244. data/test/MC/Sparc/sparc-alu-instructions.s.cs +47 -0
  245. data/test/MC/Sparc/sparc-atomic-instructions.s.cs +7 -0
  246. data/test/MC/Sparc/sparc-ctrl-instructions.s.cs +11 -0
  247. data/test/MC/Sparc/sparc-fp-instructions.s.cs +59 -0
  248. data/test/MC/Sparc/sparc-mem-instructions.s.cs +25 -0
  249. data/test/MC/Sparc/sparc-vis.s.cs +2 -0
  250. data/test/MC/Sparc/sparc64-alu-instructions.s.cs +13 -0
  251. data/test/MC/Sparc/sparc64-ctrl-instructions.s.cs +102 -0
  252. data/test/MC/Sparc/sparcv8-instructions.s.cs +7 -0
  253. data/test/MC/Sparc/sparcv9-instructions.s.cs +1 -0
  254. data/test/MC/SystemZ/insn-good-z196.s.cs +589 -0
  255. data/test/MC/SystemZ/insn-good.s.cs +2265 -0
  256. data/test/MC/SystemZ/regs-good.s.cs +45 -0
  257. data/test/MC/X86/3DNow.s.cs +29 -0
  258. data/test/MC/X86/address-size.s.cs +5 -0
  259. data/test/MC/X86/avx512-encodings.s.cs +12 -0
  260. data/test/MC/X86/intel-syntax-encoding.s.cs +30 -0
  261. data/test/MC/X86/x86-32-avx.s.cs +833 -0
  262. data/test/MC/X86/x86-32-fma3.s.cs +169 -0
  263. data/test/MC/X86/x86-32-ms-inline-asm.s.cs +27 -0
  264. data/test/MC/X86/x86_64-avx-clmul-encoding.s.cs +11 -0
  265. data/test/MC/X86/x86_64-avx-encoding.s.cs +1058 -0
  266. data/test/MC/X86/x86_64-bmi-encoding.s.cs +51 -0
  267. data/test/MC/X86/x86_64-encoding.s.cs +59 -0
  268. data/test/MC/X86/x86_64-fma3-encoding.s.cs +169 -0
  269. data/test/MC/X86/x86_64-fma4-encoding.s.cs +98 -0
  270. data/test/MC/X86/x86_64-hle-encoding.s.cs +3 -0
  271. data/test/MC/X86/x86_64-imm-widths.s.cs +27 -0
  272. data/test/MC/X86/x86_64-rand-encoding.s.cs +13 -0
  273. data/test/MC/X86/x86_64-rtm-encoding.s.cs +4 -0
  274. data/test/MC/X86/x86_64-sse4a.s.cs +1 -0
  275. data/test/MC/X86/x86_64-tbm-encoding.s.cs +40 -0
  276. data/test/MC/X86/x86_64-xop-encoding.s.cs +152 -0
  277. data/test/README +6 -0
  278. data/test/test.rb +205 -0
  279. data/test/test.rb.SPEC +235 -0
  280. data/test/test_arm.rb +202 -0
  281. data/test/test_arm.rb.SPEC +275 -0
  282. data/test/test_arm64.rb +150 -0
  283. data/test/test_arm64.rb.SPEC +116 -0
  284. data/test/test_detail.rb +228 -0
  285. data/test/test_detail.rb.SPEC +322 -0
  286. data/test/test_exhaustive.rb +80 -0
  287. data/test/test_mips.rb +118 -0
  288. data/test/test_mips.rb.SPEC +91 -0
  289. data/test/test_ppc.rb +137 -0
  290. data/test/test_ppc.rb.SPEC +84 -0
  291. data/test/test_sanity.rb +83 -0
  292. data/test/test_skipdata.rb +111 -0
  293. data/test/test_skipdata.rb.SPEC +58 -0
  294. data/test/test_sparc.rb +113 -0
  295. data/test/test_sparc.rb.SPEC +116 -0
  296. data/test/test_sysz.rb +111 -0
  297. data/test/test_sysz.rb.SPEC +61 -0
  298. data/test/test_x86.rb +189 -0
  299. data/test/test_x86.rb.SPEC +579 -0
  300. data/test/test_xcore.rb +100 -0
  301. data/test/test_xcore.rb.SPEC +75 -0
  302. metadata +393 -0
data/test/MC/ARM/neon-vswp.s.cs ADDED
@@ -0,0 +1,3 @@
1
+ # CS_ARCH_ARM, CS_MODE_ARM, None
2
+ 0x02,0x10,0xb2,0xf3 = vswp d1, d2
3
+ 0x44,0x20,0xb2,0xf3 = vswp q1, q2
data/test/MC/ARM/neont2-abs-encoding.s.cs ADDED
@@ -0,0 +1,15 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xf1,0xff,0x20,0x03 = vabs.s8 d16, d16
3
+ 0xf5,0xff,0x20,0x03 = vabs.s16 d16, d16
4
+ 0xf9,0xff,0x20,0x03 = vabs.s32 d16, d16
5
+ 0xf9,0xff,0x20,0x07 = vabs.f32 d16, d16
6
+ 0xf1,0xff,0x60,0x03 = vabs.s8 q8, q8
7
+ 0xf5,0xff,0x60,0x03 = vabs.s16 q8, q8
8
+ 0xf9,0xff,0x60,0x03 = vabs.s32 q8, q8
9
+ 0xf9,0xff,0x60,0x07 = vabs.f32 q8, q8
10
+ 0xf0,0xff,0x20,0x07 = vqabs.s8 d16, d16
11
+ 0xf4,0xff,0x20,0x07 = vqabs.s16 d16, d16
12
+ 0xf8,0xff,0x20,0x07 = vqabs.s32 d16, d16
13
+ 0xf0,0xff,0x60,0x07 = vqabs.s8 q8, q8
14
+ 0xf4,0xff,0x60,0x07 = vqabs.s16 q8, q8
15
+ 0xf8,0xff,0x60,0x07 = vqabs.s32 q8, q8
data/test/MC/ARM/neont2-absdiff-encoding.s.cs ADDED
@@ -0,0 +1,39 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x40,0xef,0xa1,0x07 = vabd.s8 d16, d16, d17
3
+ 0x50,0xef,0xa1,0x07 = vabd.s16 d16, d16, d17
4
+ 0x60,0xef,0xa1,0x07 = vabd.s32 d16, d16, d17
5
+ 0x40,0xff,0xa1,0x07 = vabd.u8 d16, d16, d17
6
+ 0x50,0xff,0xa1,0x07 = vabd.u16 d16, d16, d17
7
+ 0x60,0xff,0xa1,0x07 = vabd.u32 d16, d16, d17
8
+ 0x60,0xff,0xa1,0x0d = vabd.f32 d16, d16, d17
9
+ 0x40,0xef,0xe2,0x07 = vabd.s8 q8, q8, q9
10
+ 0x50,0xef,0xe2,0x07 = vabd.s16 q8, q8, q9
11
+ 0x60,0xef,0xe2,0x07 = vabd.s32 q8, q8, q9
12
+ 0x40,0xff,0xe2,0x07 = vabd.u8 q8, q8, q9
13
+ 0x50,0xff,0xe2,0x07 = vabd.u16 q8, q8, q9
14
+ 0x60,0xff,0xe2,0x07 = vabd.u32 q8, q8, q9
15
+ 0x60,0xff,0xe2,0x0d = vabd.f32 q8, q8, q9
16
+ 0xc0,0xef,0xa1,0x07 = vabdl.s8 q8, d16, d17
17
+ 0xd0,0xef,0xa1,0x07 = vabdl.s16 q8, d16, d17
18
+ 0xe0,0xef,0xa1,0x07 = vabdl.s32 q8, d16, d17
19
+ 0xc0,0xff,0xa1,0x07 = vabdl.u8 q8, d16, d17
20
+ 0xd0,0xff,0xa1,0x07 = vabdl.u16 q8, d16, d17
21
+ 0xe0,0xff,0xa1,0x07 = vabdl.u32 q8, d16, d17
22
+ 0x42,0xef,0xb1,0x07 = vaba.s8 d16, d18, d17
23
+ 0x52,0xef,0xb1,0x07 = vaba.s16 d16, d18, d17
24
+ 0x62,0xef,0xb1,0x07 = vaba.s32 d16, d18, d17
25
+ 0x42,0xff,0xb1,0x07 = vaba.u8 d16, d18, d17
26
+ 0x52,0xff,0xb1,0x07 = vaba.u16 d16, d18, d17
27
+ 0x62,0xff,0xb1,0x07 = vaba.u32 d16, d18, d17
28
+ 0x40,0xef,0xf4,0x27 = vaba.s8 q9, q8, q10
29
+ 0x50,0xef,0xf4,0x27 = vaba.s16 q9, q8, q10
30
+ 0x60,0xef,0xf4,0x27 = vaba.s32 q9, q8, q10
31
+ 0x40,0xff,0xf4,0x27 = vaba.u8 q9, q8, q10
32
+ 0x50,0xff,0xf4,0x27 = vaba.u16 q9, q8, q10
33
+ 0x60,0xff,0xf4,0x27 = vaba.u32 q9, q8, q10
34
+ 0xc3,0xef,0xa2,0x05 = vabal.s8 q8, d19, d18
35
+ 0xd3,0xef,0xa2,0x05 = vabal.s16 q8, d19, d18
36
+ 0xe3,0xef,0xa2,0x05 = vabal.s32 q8, d19, d18
37
+ 0xc3,0xff,0xa2,0x05 = vabal.u8 q8, d19, d18
38
+ 0xd3,0xff,0xa2,0x05 = vabal.u16 q8, d19, d18
39
+ 0xe3,0xff,0xa2,0x05 = vabal.u32 q8, d19, d18
data/test/MC/ARM/neont2-add-encoding.s.cs ADDED
@@ -0,0 +1,65 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x41,0xef,0xa0,0x08 = vadd.i8 d16, d17, d16
3
+ 0x51,0xef,0xa0,0x08 = vadd.i16 d16, d17, d16
4
+ 0x71,0xef,0xa0,0x08 = vadd.i64 d16, d17, d16
5
+ 0x61,0xef,0xa0,0x08 = vadd.i32 d16, d17, d16
6
+ 0x40,0xef,0xa1,0x0d = vadd.f32 d16, d16, d17
7
+ 0x40,0xef,0xe2,0x0d = vadd.f32 q8, q8, q9
8
+ 0xc1,0xef,0xa0,0x00 = vaddl.s8 q8, d17, d16
9
+ 0xd1,0xef,0xa0,0x00 = vaddl.s16 q8, d17, d16
10
+ 0xe1,0xef,0xa0,0x00 = vaddl.s32 q8, d17, d16
11
+ 0xc1,0xff,0xa0,0x00 = vaddl.u8 q8, d17, d16
12
+ 0xd1,0xff,0xa0,0x00 = vaddl.u16 q8, d17, d16
13
+ 0xe1,0xff,0xa0,0x00 = vaddl.u32 q8, d17, d16
14
+ 0xc0,0xef,0xa2,0x01 = vaddw.s8 q8, q8, d18
15
+ 0xd0,0xef,0xa2,0x01 = vaddw.s16 q8, q8, d18
16
+ 0xe0,0xef,0xa2,0x01 = vaddw.s32 q8, q8, d18
17
+ 0xc0,0xff,0xa2,0x01 = vaddw.u8 q8, q8, d18
18
+ 0xd0,0xff,0xa2,0x01 = vaddw.u16 q8, q8, d18
19
+ 0xe0,0xff,0xa2,0x01 = vaddw.u32 q8, q8, d18
20
+ 0x40,0xef,0xa1,0x00 = vhadd.s8 d16, d16, d17
21
+ 0x50,0xef,0xa1,0x00 = vhadd.s16 d16, d16, d17
22
+ 0x60,0xef,0xa1,0x00 = vhadd.s32 d16, d16, d17
23
+ 0x40,0xff,0xa1,0x00 = vhadd.u8 d16, d16, d17
24
+ 0x50,0xff,0xa1,0x00 = vhadd.u16 d16, d16, d17
25
+ 0x60,0xff,0xa1,0x00 = vhadd.u32 d16, d16, d17
26
+ 0x40,0xef,0xe2,0x00 = vhadd.s8 q8, q8, q9
27
+ 0x50,0xef,0xe2,0x00 = vhadd.s16 q8, q8, q9
28
+ 0x60,0xef,0xe2,0x00 = vhadd.s32 q8, q8, q9
29
+ 0x40,0xff,0xe2,0x00 = vhadd.u8 q8, q8, q9
30
+ 0x50,0xff,0xe2,0x00 = vhadd.u16 q8, q8, q9
31
+ 0x60,0xff,0xe2,0x00 = vhadd.u32 q8, q8, q9
32
+ 0x40,0xef,0xa1,0x01 = vrhadd.s8 d16, d16, d17
33
+ 0x50,0xef,0xa1,0x01 = vrhadd.s16 d16, d16, d17
34
+ 0x60,0xef,0xa1,0x01 = vrhadd.s32 d16, d16, d17
35
+ 0x40,0xff,0xa1,0x01 = vrhadd.u8 d16, d16, d17
36
+ 0x50,0xff,0xa1,0x01 = vrhadd.u16 d16, d16, d17
37
+ 0x60,0xff,0xa1,0x01 = vrhadd.u32 d16, d16, d17
38
+ 0x40,0xef,0xe2,0x01 = vrhadd.s8 q8, q8, q9
39
+ 0x50,0xef,0xe2,0x01 = vrhadd.s16 q8, q8, q9
40
+ 0x60,0xef,0xe2,0x01 = vrhadd.s32 q8, q8, q9
41
+ 0x40,0xff,0xe2,0x01 = vrhadd.u8 q8, q8, q9
42
+ 0x50,0xff,0xe2,0x01 = vrhadd.u16 q8, q8, q9
43
+ 0x60,0xff,0xe2,0x01 = vrhadd.u32 q8, q8, q9
44
+ 0x40,0xef,0xb1,0x00 = vqadd.s8 d16, d16, d17
45
+ 0x50,0xef,0xb1,0x00 = vqadd.s16 d16, d16, d17
46
+ 0x60,0xef,0xb1,0x00 = vqadd.s32 d16, d16, d17
47
+ 0x70,0xef,0xb1,0x00 = vqadd.s64 d16, d16, d17
48
+ 0x40,0xff,0xb1,0x00 = vqadd.u8 d16, d16, d17
49
+ 0x50,0xff,0xb1,0x00 = vqadd.u16 d16, d16, d17
50
+ 0x60,0xff,0xb1,0x00 = vqadd.u32 d16, d16, d17
51
+ 0x70,0xff,0xb1,0x00 = vqadd.u64 d16, d16, d17
52
+ 0x40,0xef,0xf2,0x00 = vqadd.s8 q8, q8, q9
53
+ 0x50,0xef,0xf2,0x00 = vqadd.s16 q8, q8, q9
54
+ 0x60,0xef,0xf2,0x00 = vqadd.s32 q8, q8, q9
55
+ 0x70,0xef,0xf2,0x00 = vqadd.s64 q8, q8, q9
56
+ 0x40,0xff,0xf2,0x00 = vqadd.u8 q8, q8, q9
57
+ 0x50,0xff,0xf2,0x00 = vqadd.u16 q8, q8, q9
58
+ 0x60,0xff,0xf2,0x00 = vqadd.u32 q8, q8, q9
59
+ 0x70,0xff,0xf2,0x00 = vqadd.u64 q8, q8, q9
60
+ 0xc0,0xef,0xa2,0x04 = vaddhn.i16 d16, q8, q9
61
+ 0xd0,0xef,0xa2,0x04 = vaddhn.i32 d16, q8, q9
62
+ 0xe0,0xef,0xa2,0x04 = vaddhn.i64 d16, q8, q9
63
+ 0xc0,0xff,0xa2,0x04 = vraddhn.i16 d16, q8, q9
64
+ 0xd0,0xff,0xa2,0x04 = vraddhn.i32 d16, q8, q9
65
+ 0xe0,0xff,0xa2,0x04 = vraddhn.i64 d16, q8, q9
data/test/MC/ARM/neont2-bitcount-encoding.s.cs ADDED
@@ -0,0 +1,15 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xf0,0xff,0x20,0x05 = vcnt.8 d16, d16
3
+ 0xf0,0xff,0x60,0x05 = vcnt.8 q8, q8
4
+ 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16
5
+ 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16
6
+ 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16
7
+ 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8
8
+ 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8
9
+ 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8
10
+ 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16
11
+ 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16
12
+ 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16
13
+ 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8
14
+ 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8
15
+ 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8
data/test/MC/ARM/neont2-bitwise-encoding.s.cs ADDED
@@ -0,0 +1,15 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x41,0xef,0xb0,0x01 = vand d16, d17, d16
3
+ 0x40,0xef,0xf2,0x01 = vand q8, q8, q9
4
+ 0x41,0xff,0xb0,0x01 = veor d16, d17, d16
5
+ 0x40,0xff,0xf2,0x01 = veor q8, q8, q9
6
+ 0x61,0xef,0xb0,0x01 = vorr d16, d17, d16
7
+ 0x60,0xef,0xf2,0x01 = vorr q8, q8, q9
8
+ 0x51,0xef,0xb0,0x01 = vbic d16, d17, d16
9
+ 0x50,0xef,0xf2,0x01 = vbic q8, q8, q9
10
+ 0x71,0xef,0xb0,0x01 = vorn d16, d17, d16
11
+ 0x70,0xef,0xf2,0x01 = vorn q8, q8, q9
12
+ 0xf0,0xff,0xa0,0x05 = vmvn d16, d16
13
+ 0xf0,0xff,0xe0,0x05 = vmvn q8, q8
14
+ 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16
15
+ 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9
data/test/MC/ARM/neont2-cmp-encoding.s.cs ADDED
@@ -0,0 +1,17 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16
3
+ 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16
4
+ 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16
5
+ 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16
6
+ 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8
7
+ 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8
8
+ 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8
9
+ 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8
10
+ 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1
11
+ 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1
12
+ 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1
13
+ 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1
14
+ 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1
15
+ 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1
16
+ 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1
17
+ 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1
data/test/MC/ARM/neont2-convert-encoding.s.cs ADDED
@@ -0,0 +1,19 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xfb,0xff,0x20,0x07 = vcvt.s32.f32 d16, d16
3
+ 0xfb,0xff,0xa0,0x07 = vcvt.u32.f32 d16, d16
4
+ 0xfb,0xff,0x20,0x06 = vcvt.f32.s32 d16, d16
5
+ 0xfb,0xff,0xa0,0x06 = vcvt.f32.u32 d16, d16
6
+ 0xfb,0xff,0x60,0x07 = vcvt.s32.f32 q8, q8
7
+ 0xfb,0xff,0xe0,0x07 = vcvt.u32.f32 q8, q8
8
+ 0xfb,0xff,0x60,0x06 = vcvt.f32.s32 q8, q8
9
+ 0xfb,0xff,0xe0,0x06 = vcvt.f32.u32 q8, q8
10
+ 0xff,0xef,0x30,0x0f = vcvt.s32.f32 d16, d16, #1
11
+ 0xff,0xff,0x30,0x0f = vcvt.u32.f32 d16, d16, #1
12
+ 0xff,0xef,0x30,0x0e = vcvt.f32.s32 d16, d16, #1
13
+ 0xff,0xff,0x30,0x0e = vcvt.f32.u32 d16, d16, #1
14
+ 0xff,0xef,0x70,0x0f = vcvt.s32.f32 q8, q8, #1
15
+ 0xff,0xff,0x70,0x0f = vcvt.u32.f32 q8, q8, #1
16
+ 0xff,0xef,0x70,0x0e = vcvt.f32.s32 q8, q8, #1
17
+ 0xff,0xff,0x70,0x0e = vcvt.f32.u32 q8, q8, #1
18
+ 0xf6,0xff,0x20,0x07 = vcvt.f32.f16 q8, d16
19
+ 0xf6,0xff,0x20,0x06 = vcvt.f16.f32 d16, q8
data/test/MC/ARM/neont2-dup-encoding.s.cs ADDED
@@ -0,0 +1,19 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xc0,0xee,0x90,0x1b = vdup.8 d16, r1
3
+ 0x8f,0xee,0x30,0x2b = vdup.16 d15, r2
4
+ 0x8e,0xee,0x10,0x3b = vdup.32 d14, r3
5
+ 0xe2,0xee,0x90,0x4b = vdup.8 q9, r4
6
+ 0xa0,0xee,0xb0,0x5b = vdup.16 q8, r5
7
+ 0xae,0xee,0x10,0x6b = vdup.32 q7, r6
8
+ 0xf1,0xff,0x0b,0x0c = vdup.8 d16, d11[0]
9
+ 0xf2,0xff,0x0c,0x1c = vdup.16 d17, d12[0]
10
+ 0xf4,0xff,0x0d,0x2c = vdup.32 d18, d13[0]
11
+ 0xb1,0xff,0x4a,0x6c = vdup.8 q3, d10[0]
12
+ 0xf2,0xff,0x49,0x2c = vdup.16 q9, d9[0]
13
+ 0xf4,0xff,0x48,0x0c = vdup.32 q8, d8[0]
14
+ 0xf3,0xff,0x0b,0x0c = vdup.8 d16, d11[1]
15
+ 0xf6,0xff,0x0c,0x1c = vdup.16 d17, d12[1]
16
+ 0xfc,0xff,0x0d,0x2c = vdup.32 d18, d13[1]
17
+ 0xb3,0xff,0x4a,0x6c = vdup.8 q3, d10[1]
18
+ 0xf6,0xff,0x49,0x2c = vdup.16 q9, d9[1]
19
+ 0xfc,0xff,0x48,0x0c = vdup.32 q8, d8[1]
data/test/MC/ARM/neont2-minmax-encoding.s.cs ADDED
@@ -0,0 +1,57 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x02,0xef,0x03,0x16 = vmax.s8 d1, d2, d3
3
+ 0x15,0xef,0x06,0x46 = vmax.s16 d4, d5, d6
4
+ 0x28,0xef,0x09,0x76 = vmax.s32 d7, d8, d9
5
+ 0x0b,0xff,0x0c,0xa6 = vmax.u8 d10, d11, d12
6
+ 0x1e,0xff,0x0f,0xd6 = vmax.u16 d13, d14, d15
7
+ 0x61,0xff,0xa2,0x06 = vmax.u32 d16, d17, d18
8
+ 0x44,0xef,0xa5,0x3f = vmax.f32 d19, d20, d21
9
+ 0x02,0xef,0x03,0x26 = vmax.s8 d2, d2, d3
10
+ 0x15,0xef,0x06,0x56 = vmax.s16 d5, d5, d6
11
+ 0x28,0xef,0x09,0x86 = vmax.s32 d8, d8, d9
12
+ 0x0b,0xff,0x0c,0xb6 = vmax.u8 d11, d11, d12
13
+ 0x1e,0xff,0x0f,0xe6 = vmax.u16 d14, d14, d15
14
+ 0x61,0xff,0xa2,0x16 = vmax.u32 d17, d17, d18
15
+ 0x44,0xef,0xa5,0x4f = vmax.f32 d20, d20, d21
16
+ 0x04,0xef,0x46,0x26 = vmax.s8 q1, q2, q3
17
+ 0x1a,0xef,0x4c,0x86 = vmax.s16 q4, q5, q6
18
+ 0x20,0xef,0xe2,0xe6 = vmax.s32 q7, q8, q9
19
+ 0x46,0xff,0xe8,0x46 = vmax.u8 q10, q11, q12
20
+ 0x5c,0xff,0xee,0xa6 = vmax.u16 q13, q14, q15
21
+ 0x2e,0xff,0x60,0xc6 = vmax.u32 q6, q7, q8
22
+ 0x4a,0xef,0x42,0x2f = vmax.f32 q9, q5, q1
23
+ 0x04,0xef,0x46,0x46 = vmax.s8 q2, q2, q3
24
+ 0x1a,0xef,0x4c,0xa6 = vmax.s16 q5, q5, q6
25
+ 0x60,0xef,0xe2,0x06 = vmax.s32 q8, q8, q9
26
+ 0x46,0xff,0xc4,0x66 = vmax.u8 q11, q11, q2
27
+ 0x18,0xff,0x4a,0x86 = vmax.u16 q4, q4, q5
28
+ 0x2e,0xff,0x60,0xe6 = vmax.u32 q7, q7, q8
29
+ 0x04,0xef,0x42,0x4f = vmax.f32 q2, q2, q1
30
+ 0x02,0xef,0x13,0x16 = vmin.s8 d1, d2, d3
31
+ 0x15,0xef,0x16,0x46 = vmin.s16 d4, d5, d6
32
+ 0x28,0xef,0x19,0x76 = vmin.s32 d7, d8, d9
33
+ 0x0b,0xff,0x1c,0xa6 = vmin.u8 d10, d11, d12
34
+ 0x1e,0xff,0x1f,0xd6 = vmin.u16 d13, d14, d15
35
+ 0x61,0xff,0xb2,0x06 = vmin.u32 d16, d17, d18
36
+ 0x64,0xef,0xa5,0x3f = vmin.f32 d19, d20, d21
37
+ 0x02,0xef,0x13,0x26 = vmin.s8 d2, d2, d3
38
+ 0x15,0xef,0x16,0x56 = vmin.s16 d5, d5, d6
39
+ 0x28,0xef,0x19,0x86 = vmin.s32 d8, d8, d9
40
+ 0x0b,0xff,0x1c,0xb6 = vmin.u8 d11, d11, d12
41
+ 0x1e,0xff,0x1f,0xe6 = vmin.u16 d14, d14, d15
42
+ 0x61,0xff,0xb2,0x16 = vmin.u32 d17, d17, d18
43
+ 0x64,0xef,0xa5,0x4f = vmin.f32 d20, d20, d21
44
+ 0x04,0xef,0x56,0x26 = vmin.s8 q1, q2, q3
45
+ 0x1a,0xef,0x5c,0x86 = vmin.s16 q4, q5, q6
46
+ 0x20,0xef,0xf2,0xe6 = vmin.s32 q7, q8, q9
47
+ 0x46,0xff,0xf8,0x46 = vmin.u8 q10, q11, q12
48
+ 0x5c,0xff,0xfe,0xa6 = vmin.u16 q13, q14, q15
49
+ 0x2e,0xff,0x70,0xc6 = vmin.u32 q6, q7, q8
50
+ 0x6a,0xef,0x42,0x2f = vmin.f32 q9, q5, q1
51
+ 0x04,0xef,0x56,0x46 = vmin.s8 q2, q2, q3
52
+ 0x1a,0xef,0x5c,0xa6 = vmin.s16 q5, q5, q6
53
+ 0x60,0xef,0xf2,0x06 = vmin.s32 q8, q8, q9
54
+ 0x46,0xff,0xd4,0x66 = vmin.u8 q11, q11, q2
55
+ 0x18,0xff,0x5a,0x86 = vmin.u16 q4, q4, q5
56
+ 0x2e,0xff,0x70,0xe6 = vmin.u32 q7, q7, q8
57
+ 0x24,0xef,0x42,0x4f = vmin.f32 q2, q2, q1
data/test/MC/ARM/neont2-mov-encoding.s.cs ADDED
@@ -0,0 +1,58 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xc0,0xef,0x18,0x0e = vmov.i8 d16, #0x8
3
+ 0xc1,0xef,0x10,0x08 = vmov.i16 d16, #0x10
4
+ 0xc1,0xef,0x10,0x0a = vmov.i16 d16, #0x1000
5
+ 0xc2,0xef,0x10,0x00 = vmov.i32 d16, #0x20
6
+ 0xc2,0xef,0x10,0x02 = vmov.i32 d16, #0x2000
7
+ 0xc2,0xef,0x10,0x04 = vmov.i32 d16, #0x200000
8
+ 0xc2,0xef,0x10,0x06 = vmov.i32 d16, #0x20000000
9
+ 0xc2,0xef,0x10,0x0c = vmov.i32 d16, #0x20ff
10
+ 0xc2,0xef,0x10,0x0d = vmov.i32 d16, #0x20ffff
11
+ 0xc1,0xff,0x33,0x0e = vmov.i64 d16, #0xff0000ff0000ffff
12
+ 0xc0,0xef,0x58,0x0e = vmov.i8 q8, #0x8
13
+ 0xc1,0xef,0x50,0x08 = vmov.i16 q8, #0x10
14
+ 0xc1,0xef,0x50,0x0a = vmov.i16 q8, #0x1000
15
+ 0xc2,0xef,0x50,0x00 = vmov.i32 q8, #0x20
16
+ 0xc2,0xef,0x50,0x02 = vmov.i32 q8, #0x2000
17
+ 0xc2,0xef,0x50,0x04 = vmov.i32 q8, #0x200000
18
+ 0xc2,0xef,0x50,0x06 = vmov.i32 q8, #0x20000000
19
+ 0xc2,0xef,0x50,0x0c = vmov.i32 q8, #0x20ff
20
+ 0xc2,0xef,0x50,0x0d = vmov.i32 q8, #0x20ffff
21
+ 0xc1,0xff,0x73,0x0e = vmov.i64 q8, #0xff0000ff0000ffff
22
+ 0xc1,0xef,0x30,0x08 = vmvn.i16 d16, #0x10
23
+ 0xc1,0xef,0x30,0x0a = vmvn.i16 d16, #0x1000
24
+ 0xc2,0xef,0x30,0x00 = vmvn.i32 d16, #0x20
25
+ 0xc2,0xef,0x30,0x02 = vmvn.i32 d16, #0x2000
26
+ 0xc2,0xef,0x30,0x04 = vmvn.i32 d16, #0x200000
27
+ 0xc2,0xef,0x30,0x06 = vmvn.i32 d16, #0x20000000
28
+ 0xc2,0xef,0x30,0x0c = vmvn.i32 d16, #0x20ff
29
+ 0xc2,0xef,0x30,0x0d = vmvn.i32 d16, #0x20ffff
30
+ 0xc8,0xef,0x30,0x0a = vmovl.s8 q8, d16
31
+ 0xd0,0xef,0x30,0x0a = vmovl.s16 q8, d16
32
+ 0xe0,0xef,0x30,0x0a = vmovl.s32 q8, d16
33
+ 0xc8,0xff,0x30,0x0a = vmovl.u8 q8, d16
34
+ 0xd0,0xff,0x30,0x0a = vmovl.u16 q8, d16
35
+ 0xe0,0xff,0x30,0x0a = vmovl.u32 q8, d16
36
+ 0xf2,0xff,0x20,0x02 = vmovn.i16 d16, q8
37
+ 0xf6,0xff,0x20,0x02 = vmovn.i32 d16, q8
38
+ 0xfa,0xff,0x20,0x02 = vmovn.i64 d16, q8
39
+ 0xf2,0xff,0xa0,0x02 = vqmovn.s16 d16, q8
40
+ 0xf6,0xff,0xa0,0x02 = vqmovn.s32 d16, q8
41
+ 0xfa,0xff,0xa0,0x02 = vqmovn.s64 d16, q8
42
+ 0xf2,0xff,0xe0,0x02 = vqmovn.u16 d16, q8
43
+ 0xf6,0xff,0xe0,0x02 = vqmovn.u32 d16, q8
44
+ 0xfa,0xff,0xe0,0x02 = vqmovn.u64 d16, q8
45
+ 0xf2,0xff,0x60,0x02 = vqmovun.s16 d16, q8
46
+ 0xf6,0xff,0x60,0x02 = vqmovun.s32 d16, q8
47
+ 0xfa,0xff,0x60,0x02 = vqmovun.s64 d16, q8
48
+ 0x50,0xee,0xb0,0x0b = vmov.s8 r0, d16[1]
49
+ 0x10,0xee,0xf0,0x0b = vmov.s16 r0, d16[1]
50
+ 0xd0,0xee,0xb0,0x0b = vmov.u8 r0, d16[1]
51
+ 0x90,0xee,0xf0,0x0b = vmov.u16 r0, d16[1]
52
+ 0x30,0xee,0x90,0x0b = vmov.32 r0, d16[1]
53
+ 0x40,0xee,0xb0,0x1b = vmov.8 d16[1], r1
54
+ 0x00,0xee,0xf0,0x1b = vmov.16 d16[1], r1
55
+ 0x20,0xee,0x90,0x1b = vmov.32 d16[1], r1
56
+ 0x42,0xee,0xb0,0x1b = vmov.8 d18[1], r1
57
+ 0x02,0xee,0xf0,0x1b = vmov.16 d18[1], r1
58
+ 0x22,0xee,0x90,0x1b = vmov.32 d18[1], r1
data/test/MC/ARM/neont2-mul-accum-encoding.s.cs ADDED
@@ -0,0 +1,41 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x42,0xef,0xa1,0x09 = vmla.i8 d16, d18, d17
3
+ 0x52,0xef,0xa1,0x09 = vmla.i16 d16, d18, d17
4
+ 0x62,0xef,0xa1,0x09 = vmla.i32 d16, d18, d17
5
+ 0x42,0xef,0xb1,0x0d = vmla.f32 d16, d18, d17
6
+ 0x40,0xef,0xe4,0x29 = vmla.i8 q9, q8, q10
7
+ 0x50,0xef,0xe4,0x29 = vmla.i16 q9, q8, q10
8
+ 0x60,0xef,0xe4,0x29 = vmla.i32 q9, q8, q10
9
+ 0x40,0xef,0xf4,0x2d = vmla.f32 q9, q8, q10
10
+ 0xe0,0xff,0xc3,0x80 = vmla.i32 q12, q8, d3[0]
11
+ 0xc3,0xef,0xa2,0x08 = vmlal.s8 q8, d19, d18
12
+ 0xd3,0xef,0xa2,0x08 = vmlal.s16 q8, d19, d18
13
+ 0xe3,0xef,0xa2,0x08 = vmlal.s32 q8, d19, d18
14
+ 0xc3,0xff,0xa2,0x08 = vmlal.u8 q8, d19, d18
15
+ 0xd3,0xff,0xa2,0x08 = vmlal.u16 q8, d19, d18
16
+ 0xe3,0xff,0xa2,0x08 = vmlal.u32 q8, d19, d18
17
+ 0xa5,0xef,0x4a,0x02 = vmlal.s32 q0, d5, d10[0]
18
+ 0xd3,0xef,0xa2,0x09 = vqdmlal.s16 q8, d19, d18
19
+ 0xe3,0xef,0xa2,0x09 = vqdmlal.s32 q8, d19, d18
20
+ 0xdb,0xef,0x47,0x63 = vqdmlal.s16 q11, d11, d7[0]
21
+ 0xdb,0xef,0x4f,0x63 = vqdmlal.s16 q11, d11, d7[1]
22
+ 0xdb,0xef,0x67,0x63 = vqdmlal.s16 q11, d11, d7[2]
23
+ 0xdb,0xef,0x6f,0x63 = vqdmlal.s16 q11, d11, d7[3]
24
+ 0x42,0xff,0xa1,0x09 = vmls.i8 d16, d18, d17
25
+ 0x52,0xff,0xa1,0x09 = vmls.i16 d16, d18, d17
26
+ 0x62,0xff,0xa1,0x09 = vmls.i32 d16, d18, d17
27
+ 0x62,0xef,0xb1,0x0d = vmls.f32 d16, d18, d17
28
+ 0x40,0xff,0xe4,0x29 = vmls.i8 q9, q8, q10
29
+ 0x50,0xff,0xe4,0x29 = vmls.i16 q9, q8, q10
30
+ 0x60,0xff,0xe4,0x29 = vmls.i32 q9, q8, q10
31
+ 0x60,0xef,0xf4,0x2d = vmls.f32 q9, q8, q10
32
+ 0x98,0xff,0xe6,0x84 = vmls.i16 q4, q12, d6[2]
33
+ 0xc3,0xef,0xa2,0x0a = vmlsl.s8 q8, d19, d18
34
+ 0xd3,0xef,0xa2,0x0a = vmlsl.s16 q8, d19, d18
35
+ 0xe3,0xef,0xa2,0x0a = vmlsl.s32 q8, d19, d18
36
+ 0xc3,0xff,0xa2,0x0a = vmlsl.u8 q8, d19, d18
37
+ 0xd3,0xff,0xa2,0x0a = vmlsl.u16 q8, d19, d18
38
+ 0xe3,0xff,0xa2,0x0a = vmlsl.u32 q8, d19, d18
39
+ 0xd9,0xff,0xe9,0x66 = vmlsl.u16 q11, d25, d1[3]
40
+ 0xd3,0xef,0xa2,0x0b = vqdmlsl.s16 q8, d19, d18
41
+ 0xe3,0xef,0xa2,0x0b = vqdmlsl.s32 q8, d19, d18
data/test/MC/ARM/neont2-mul-encoding.s.cs ADDED
@@ -0,0 +1,31 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x40,0xef,0xb1,0x09 = vmul.i8 d16, d16, d17
3
+ 0x50,0xef,0xb1,0x09 = vmul.i16 d16, d16, d17
4
+ 0x60,0xef,0xb1,0x09 = vmul.i32 d16, d16, d17
5
+ 0x40,0xff,0xb1,0x0d = vmul.f32 d16, d16, d17
6
+ 0x40,0xef,0xf2,0x09 = vmul.i8 q8, q8, q9
7
+ 0x50,0xef,0xf2,0x09 = vmul.i16 q8, q8, q9
8
+ 0x60,0xef,0xf2,0x09 = vmul.i32 q8, q8, q9
9
+ 0x40,0xff,0xf2,0x0d = vmul.f32 q8, q8, q9
10
+ 0x40,0xff,0xb1,0x09 = vmul.p8 d16, d16, d17
11
+ 0x40,0xff,0xf2,0x09 = vmul.p8 q8, q8, q9
12
+ 0xd8,0xef,0x68,0x28 = vmul.i16 d18, d8, d0[3]
13
+ 0x50,0xef,0xa1,0x0b = vqdmulh.s16 d16, d16, d17
14
+ 0x60,0xef,0xa1,0x0b = vqdmulh.s32 d16, d16, d17
15
+ 0x50,0xef,0xe2,0x0b = vqdmulh.s16 q8, q8, q9
16
+ 0x60,0xef,0xe2,0x0b = vqdmulh.s32 q8, q8, q9
17
+ 0x92,0xef,0x43,0xbc = vqdmulh.s16 d11, d2, d3[0]
18
+ 0x50,0xff,0xa1,0x0b = vqrdmulh.s16 d16, d16, d17
19
+ 0x60,0xff,0xa1,0x0b = vqrdmulh.s32 d16, d16, d17
20
+ 0x50,0xff,0xe2,0x0b = vqrdmulh.s16 q8, q8, q9
21
+ 0x60,0xff,0xe2,0x0b = vqrdmulh.s32 q8, q8, q9
22
+ 0xc0,0xef,0xa1,0x0c = vmull.s8 q8, d16, d17
23
+ 0xd0,0xef,0xa1,0x0c = vmull.s16 q8, d16, d17
24
+ 0xe0,0xef,0xa1,0x0c = vmull.s32 q8, d16, d17
25
+ 0xc0,0xff,0xa1,0x0c = vmull.u8 q8, d16, d17
26
+ 0xd0,0xff,0xa1,0x0c = vmull.u16 q8, d16, d17
27
+ 0xe0,0xff,0xa1,0x0c = vmull.u32 q8, d16, d17
28
+ 0xc0,0xef,0xa1,0x0e = vmull.p8 q8, d16, d17
29
+ 0xd0,0xef,0xa1,0x0d = vqdmull.s16 q8, d16, d17
30
+ 0xe0,0xef,0xa1,0x0d = vqdmull.s32 q8, d16, d17
31
+ 0x97,0xef,0x49,0x2b = vqdmull.s16 q1, d7, d1[1]
data/test/MC/ARM/neont2-neg-encoding.s.cs ADDED
@@ -0,0 +1,15 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0xf1,0xff,0xa0,0x03 = vneg.s8 d16, d16
3
+ 0xf5,0xff,0xa0,0x03 = vneg.s16 d16, d16
4
+ 0xf9,0xff,0xa0,0x03 = vneg.s32 d16, d16
5
+ 0xf9,0xff,0xa0,0x07 = vneg.f32 d16, d16
6
+ 0xf1,0xff,0xe0,0x03 = vneg.s8 q8, q8
7
+ 0xf5,0xff,0xe0,0x03 = vneg.s16 q8, q8
8
+ 0xf9,0xff,0xe0,0x03 = vneg.s32 q8, q8
9
+ 0xf9,0xff,0xe0,0x07 = vneg.f32 q8, q8
10
+ 0xf0,0xff,0xa0,0x07 = vqneg.s8 d16, d16
11
+ 0xf4,0xff,0xa0,0x07 = vqneg.s16 d16, d16
12
+ 0xf8,0xff,0xa0,0x07 = vqneg.s32 d16, d16
13
+ 0xf0,0xff,0xe0,0x07 = vqneg.s8 q8, q8
14
+ 0xf4,0xff,0xe0,0x07 = vqneg.s16 q8, q8
15
+ 0xf8,0xff,0xe0,0x07 = vqneg.s32 q8, q8
data/test/MC/ARM/neont2-pairwise-encoding.s.cs ADDED
@@ -0,0 +1,43 @@
1
+ # CS_ARCH_ARM, CS_MODE_THUMB, None
2
+ 0x05,0xef,0x1b,0x1b = vpadd.i8 d1, d5, d11
3
+ 0x12,0xef,0x1c,0xdb = vpadd.i16 d13, d2, d12
4
+ 0x21,0xef,0x1d,0xeb = vpadd.i32 d14, d1, d13
5
+ 0x40,0xff,0x8e,0x3d = vpadd.f32 d19, d16, d14
6
+ 0xb0,0xff,0x0a,0x72 = vpaddl.s8 d7, d10
7
+ 0xb4,0xff,0x0b,0x82 = vpaddl.s16 d8, d11
8
+ 0xb8,0xff,0x0c,0x92 = vpaddl.s32 d9, d12
9
+ 0xb0,0xff,0x8d,0x02 = vpaddl.u8 d0, d13
10
+ 0xb4,0xff,0x8e,0x52 = vpaddl.u16 d5, d14
11
+ 0xb8,0xff,0x8f,0x62 = vpaddl.u32 d6, d15
12
+ 0xb0,0xff,0x4e,0x82 = vpaddl.s8 q4, q7
13
+ 0xb4,0xff,0x4c,0xa2 = vpaddl.s16 q5, q6
14
+ 0xb8,0xff,0x4a,0xc2 = vpaddl.s32 q6, q5
15
+ 0xb0,0xff,0xc8,0xe2 = vpaddl.u8 q7, q4
16
+ 0xf4,0xff,0xc6,0x02 = vpaddl.u16 q8, q3
17
+ 0xf8,0xff,0xc4,0x22 = vpaddl.u32 q9, q2
18
+ 0xf0,0xff,0x04,0x06 = vpadal.s8 d16, d4
19
+ 0xf4,0xff,0x09,0x46 = vpadal.s16 d20, d9
20
+ 0xf8,0xff,0x01,0x26 = vpadal.s32 d18, d1
21
+ 0xb0,0xff,0xa9,0xe6 = vpadal.u8 d14, d25
22
+ 0xb4,0xff,0x86,0xc6 = vpadal.u16 d12, d6
23
+ 0xb8,0xff,0x87,0xb6 = vpadal.u32 d11, d7
24
+ 0xb0,0xff,0x64,0x86 = vpadal.s8 q4, q10
25
+ 0xb4,0xff,0x66,0xa6 = vpadal.s16 q5, q11
26
+ 0xb8,0xff,0x68,0xc6 = vpadal.s32 q6, q12
27
+ 0xb0,0xff,0xea,0xe6 = vpadal.u8 q7, q13
28
+ 0xf4,0xff,0xec,0x06 = vpadal.u16 q8, q14
29
+ 0xf8,0xff,0xee,0x26 = vpadal.u32 q9, q15
30
+ 0x4d,0xef,0x9a,0x0a = vpmin.s8 d16, d29, d10
31
+ 0x5c,0xef,0x9b,0x1a = vpmin.s16 d17, d28, d11
32
+ 0x6b,0xef,0x9c,0x2a = vpmin.s32 d18, d27, d12
33
+ 0x4a,0xff,0x9d,0x3a = vpmin.u8 d19, d26, d13
34
+ 0x59,0xff,0x9e,0x4a = vpmin.u16 d20, d25, d14
35
+ 0x68,0xff,0x9f,0x5a = vpmin.u32 d21, d24, d15
36
+ 0x67,0xff,0xa0,0x6f = vpmin.f32 d22, d23, d16
37
+ 0x04,0xef,0xa1,0x3a = vpmax.s8 d3, d20, d17
38
+ 0x15,0xef,0xa0,0x4a = vpmax.s16 d4, d21, d16
39
+ 0x26,0xef,0x8f,0x5a = vpmax.s32 d5, d22, d15
40
+ 0x07,0xff,0x8e,0x6a = vpmax.u8 d6, d23, d14
41
+ 0x18,0xff,0x8d,0x7a = vpmax.u16 d7, d24, d13
42
+ 0x29,0xff,0x8c,0x8a = vpmax.u32 d8, d25, d12
43
+ 0x0a,0xff,0x8b,0x9f = vpmax.f32 d9, d26, d11